mirror of
https://github.com/apache/nuttx.git
synced 2026-06-08 10:32:47 +08:00
Xtensa: More interrupt-related logic
This commit is contained in:
Gregory Nutt
@@ -205,9 +205,9 @@ _xtensa_context_save:
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l32i a12, sp, (4 * REG_A12) /* Recover original a9,12,13 */
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l32i a13, sp, (4 * REG_A13)
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l32i a9, sp, (4 * REG_A9)
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addi sp, sp, (4 * REG_FRMSZ) /* Restore the interruptee's SP */
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addi sp, sp, (4 * XCPTCONTEXT_SIZE) /* Restore the interruptee's SP */
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call0 xthal_window_spill_nw /* Preserves only a4,5,8,9,12,13 */
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addi sp, sp, -(4 * REG_FRMSZ)
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addi sp, sp, -(4 * XCPTCONTEXT_SIZE)
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l32i a12, sp, (4 * REG_TMP0) /* Recover stuff from stack frame */
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l32i a13, sp, (4 * REG_TMP1)
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l32i a9, sp, (4 * REG_TMP2)
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@@ -78,10 +78,10 @@
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.macro extract_msb aout ain
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1:
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addi \aout, \ain, -1 /* aout = ain - 1 */
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and \ain, \ain, \aout /* ain = ain & aout */
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bnez \ain, 1b /* repeat until ain == 0 */
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addi \aout, \aout, 1 /* return aout + 1 */
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addi \aout, \ain, -1 /* aout = ain - 1 */
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and \ain, \ain, \aout /* ain = ain & aout */
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bnez \ain, 1b /* Repeat until ain == 0 */
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addi \aout, \aout, 1 /* Return aout + 1 */
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.endm
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/* Macro dispatch_c_isr - dispatch interrupts to user ISRs.
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@@ -148,7 +148,6 @@
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2:
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#endif
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/* Now look up in the dispatch table and call user ISR if any. */
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/* If multiple bits are set then MSB has highest priority. */
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extract_msb a4, a2 /* a4 = MSB of a2, a2 trashed */
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@@ -179,23 +178,28 @@
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wsr a4, INTCLEAR /* Clear sw or edge-triggered interrupt */
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beq a3, a4, 7f /* If timer interrupt then skip table */
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find_ms_setbit a3, a4, a3, 0 /* a3 = interrupt number */
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/* Call xtensa_int_decode with, passing that address of the register save
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* area as a parameter (A2).
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*/
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movi a4, _xt_interrupt_table
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addx8 a3, a3, a4 /* a3 = address of interrupt table entry */
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l32i a4, a3, XIE_HANDLER /* a4 = handler address */
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mov a2, sp /* Argument: Top of stack = register save area */
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call0 xtensa_int_decode /* Call xtensa_int_decode */
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#ifdef CONFIG_XTENSA_CALL0_ABI
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mov a12, a6 /* Save in callee-saved reg */
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l32i a2, a3, XIE_ARG /* a2 = handler arg */
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callx0 a4 /* call handler */
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mov a2, a12
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#else
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mov a2, a6 /* Save in windowed reg */
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l32i a6, a3, XIE_ARG /* a6 = handler arg */
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callx4 a4 /* Call handler */
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#endif
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/* On return from xtensa_int_decode, A2 will contain the address of the new
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* register save area. Usually this would be the same as the current SP.
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* But in the event of a context switch, A2 will instead refer to the TCB
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* register save area.
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*/
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beq a2, sp, 3f /* If timer interrupt then skip table */
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/* Switch stacks */
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#warning REVIST: Should use register save are on stack.
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l32i a4, sp, (4 * REG_A1) /* Retrieve stack ptr and replace */
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addi sp, a4, -(4 * XCPTCONTEXT_SIZE)
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3:
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#ifdef CONFIG_XTENSA_USE_SWPRI
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j 8f
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#else
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@@ -212,7 +216,7 @@
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*/
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#ifdef CONFIG_XTENSA_CALL0_ABI
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mov a12, a6
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mov a12, a6
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call0 XT_RTOS_TIMER_INT
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mov a2, a12
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#else
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@@ -236,8 +240,8 @@
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movi a3, _xt_intdata
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l32i a4, a3, 0 /* a4 = _xt_intenable */
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s32i a2, a3, 4 /* update _xt_vpri_mask */
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and a4, a4, a2 /* a4 = masked intenable */
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wsr a4, INTENABLE /* update INTENABLE */
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and a4, a4, a2 /* a4 = masked intenable */
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wsr a4, INTENABLE /* update INTENABLE */
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#endif
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9:
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@@ -277,17 +281,17 @@
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#if XTENSA_EXCM_LEVEL >= 2
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.section .iram1,"ax"
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.type _xtensa_level2_handler,@function
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.align 4
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.type _xtensa_level2_handler,@function
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.align 4
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_xtensa_level2_handler:
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mov a0, sp /* sp == a1 */
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addi sp, sp, -(4 * REG_FRMSZ) /* Allocate interrupt stack frame */
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mov a0, sp /* sp == a1 */
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addi sp, sp, -(4 * XCPTCONTEXT_SIZE) /* Allocate interrupt stack frame */
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s32i a0, sp, (4 * REG_A1) /* Save pre-interrupt SP */
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rsr a0, EPS_2 /* Save interruptee's PS */
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rsr a0, EPS_2 /* Save interruptee's PS */
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s32i a0, sp, (4 * REG_PS)
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rsr a0, EPC_2 /* Save interruptee's PC */
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rsr a0, EPC_2 /* Save interruptee's PC */
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s32i a0, sp, (4 * REG_PC)
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rsr a0, EXCSAVE_2 /* Save interruptee's a0 */
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rsr a0, EXCSAVE_2 /* Save interruptee's a0 */
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s32i a0, sp, (4 * REG_A0)
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/* Save rest of interrupt context and enter RTOS. */
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@@ -301,69 +305,71 @@ _xtensa_level2_handler:
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#else
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movi a0, PS_INTLEVEL(2) | PS_UM | PS_WOE
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#endif
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wsr a0, PS
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wsr a0, PS
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rsync
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/* Decode and dispatch the interrupt. In the event of an interrupt
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* level context xtensa_int_decode() will return a pointer to the new
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* register state in A2.
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* level context dispatch_c_isr() will switch stacks to the new task's
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* context save area.
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*/
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dispatch_c_isr 2 XTENSA_INTLEVEL2_MASK
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dispatch_c_isr 2 XTENSA_INTLEVEL2_MASK
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/* Restore registers in preparation to return from interrupt */
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call0 _xtensa_int_exit /* does not return directly here */
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call0 _xtensa_int_exit
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/* Restore only level-specific regs (the rest were already restored) */
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l32i a0, sp, (4 * REG_PS) /* retrieve interruptee's PS */
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wsr a0, EPS_2
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wsr a0, EPS_2
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l32i a0, sp, (4 * REG_PC) /* retrieve interruptee's PC */
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wsr a0, EPC_2
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wsr a0, EPC_2
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l32i a0, sp, (4 * REG_A0) /* retrieve interruptee's A0 */
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l32i sp, sp, (4 * REG_A1) /* remove interrupt stack frame */
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rsync /* Ensure EPS and EPC written */
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rsync /* Ensure EPS and EPC written */
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/* Return from interrupt. RFI restores the PS from EPS_2 and jumps to
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* the address in EPC_2.
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*/
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rfi 2
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rfi 2
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#endif /* XTENSA_EXCM_LEVEL >= 2 */
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/*******************************************************************************
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HIGH PRIORITY (LEVEL > XTENSA_EXCM_LEVEL) INTERRUPT VECTORS AND HANDLERS
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High priority interrupts are by definition those with priorities greater
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than XTENSA_EXCM_LEVEL. This includes non-maskable (NMI). High priority
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interrupts cannot interact with the RTOS, that is they must save all regs
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they use and not call any RTOS function.
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A further restriction imposed by the Xtensa windowed architecture is that
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high priority interrupts must not modify the stack area even logically
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"above" the top of the interrupted stack (they need to provide their
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own stack or static save area).
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Cadence Design Systems recommends high priority interrupt handlers be coded in assembly
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and used for purposes requiring very short service times.
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Here are templates for high priority (level 2+) interrupt vectors.
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They assume only one interrupt per level to avoid the burden of identifying
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which interrupts at this level are pending and enabled. This allows for
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minimum latency and avoids having to save/restore a2 in addition to a0.
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If more than one interrupt per high priority level is configured, this burden
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is on the handler which in any case must provide a way to save and restore
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registers it uses without touching the interrupted stack.
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Each vector goes at a predetermined location according to the Xtensa
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hardware configuration, which is ensured by its placement in a special
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section known to the Xtensa linker support package (LSP). It performs
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the minimum necessary before jumping to the handler in the .text section.
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*******************************************************************************/
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/****************************************************************************
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*
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* HIGH PRIORITY (LEVEL > XTENSA_EXCM_LEVEL) INTERRUPT VECTORS AND HANDLERS
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*
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* High priority interrupts are by definition those with priorities greater
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* than XTENSA_EXCM_LEVEL. This includes non-maskable (NMI). High priority
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* interrupts cannot interact with the RTOS, that is they must save all regs
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* they use and not call any RTOS function.
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*
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* A further restriction imposed by the Xtensa windowed architecture is that
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* high priority interrupts must not modify the stack area even logically
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* "above" the top of the interrupted stack (they need to provide their
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* own stack or static save area).
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*
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* Cadence Design Systems recommends high priority interrupt handlers be
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* coded in assembly and used for purposes requiring very short service
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* times.
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*
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* Here are templates for high priority (level 2+) interrupt vectors.
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* They assume only one interrupt per level to avoid the burden of
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* identifying which interrupts at this level are pending and enabled. This
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* allows for minimum latency and avoids having to save/restore a2 in
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* addition to a0. If more than one interrupt per high priority level is
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* configured, this burden is on the handler which in any case must provide
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* a way to save and restore registers it uses without touching the
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* interrupted stack.
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*
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* Each vector goes at a predetermined location according to the Xtensa
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* hardware configuration, which is ensured by its placement in a special
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* section known to the Xtensa linker support package (LSP). It performs
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* the minimum necessary before jumping to the handler in the .text section.
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*
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****************************************************************************/
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/*
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Currently only shells for high priority interrupt handlers are provided
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@@ -372,7 +378,7 @@ documentation: "Microprocessor Programmer's Guide".
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*/
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#if XTENSA_INT_NLEVELS >=2 && XTENSA_EXCM_LEVEL < 2 && XTENSA_DEBUGLEVEL !=2
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.section .iram1,"ax"
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.section .iram1,"ax"
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.type _xtensa_level2_handler, @function
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.align 4
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_xtensa_level2_handler:
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@@ -384,24 +390,24 @@ _xtensa_level2_handler:
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l32i a0, a0, 2<<2
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beqz a0, 1f
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.Ln_xtensa_level2_handler_call_hook:
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callx0 a0 /* must NOT disturb stack! */
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callx0 a0 /* Must NOT disturb stack! */
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1:
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#endif
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/* USER_EDIT:
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ADD HIGH PRIORITY LEVEL 2 INTERRUPT HANDLER CODE HERE.
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*/
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* ADD HIGH PRIORITY LEVEL 2 INTERRUPT HANDLER CODE HERE.
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*/
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.align 4
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.L_xtensa_level2_handler_exit:
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rsr a0, EXCSAVE_2 /* restore a0 */
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rfi 2
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rsr a0, EXCSAVE_2 /* Restore a0 */
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rfi 2
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#endif /* XTENSA_INT_NLEVELS >=2 && XTENSA_EXCM_LEVEL < 2 && XTENSA_DEBUGLEVEL !=2 */
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#if XTENSA_INT_NLEVELS >=3 && XTENSA_EXCM_LEVEL < 3 && XTENSA_DEBUGLEVEL !=3
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.section .iram1,"ax"
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.type _xtensa_level3_handler,@function
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.section .iram1,"ax"
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.type _xtensa_level3_handler, @function
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.align 4
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_xtensa_level3_handler:
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@@ -412,23 +418,23 @@ _xtensa_level3_handler:
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l32i a0, a0, 3<<2
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beqz a0, 1f
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.Ln_xtensa_level3_handler_call_hook:
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callx0 a0 /* must NOT disturb stack! */
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callx0 a0 /* Must NOT disturb stack! */
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1:
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#endif
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/* USER_EDIT:
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ADD HIGH PRIORITY LEVEL 3 INTERRUPT HANDLER CODE HERE.
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*/
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* ADD HIGH PRIORITY LEVEL 3 INTERRUPT HANDLER CODE HERE.
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*/
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.align 4
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.L_xtensa_level3_handler_exit:
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rsr a0, EXCSAVE_3 /* restore a0 */
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rfi 3
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rsr a0, EXCSAVE_3 /* Restore a0 */
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rfi 3
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#endif /* XTENSA_INT_NLEVELS >=3 && XTENSA_EXCM_LEVEL < 3 && XTENSA_DEBUGLEVEL !=3 */
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#if XTENSA_INT_NLEVELS >=4 && XTENSA_EXCM_LEVEL < 4 && XTENSA_DEBUGLEVEL !=4
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.section .iram1,"ax"
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.section .iram1,"ax"
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.type _xtensa_level4_handler,@function
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.align 4
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_xtensa_level4_handler:
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@@ -437,26 +443,26 @@ _xtensa_level4_handler:
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/* Call interrupt hook if present to (pre)handle interrupts. */
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movi a0, _xt_intexc_hooks
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l32i a0, a0, 4<<2
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l32i a0, a0, 4 << 2
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beqz a0, 1f
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.Ln_xtensa_level4_handler_call_hook:
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callx0 a0 /* must NOT disturb stack! */
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callx0 a0 /* Must NOT disturb stack! */
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1:
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#endif
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/* USER_EDIT:
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ADD HIGH PRIORITY LEVEL 4 INTERRUPT HANDLER CODE HERE.
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*/
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* ADD HIGH PRIORITY LEVEL 4 INTERRUPT HANDLER CODE HERE.
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*/
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.align 4
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.L_xtensa_level4_handler_exit:
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rsr a0, EXCSAVE_4 /* restore a0 */
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rfi 4
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rsr a0, EXCSAVE_4 /* Restore a0 */
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rfi 4
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#endif /* XTENSA_INT_NLEVELS >=4 && XTENSA_EXCM_LEVEL < 4 && XTENSA_DEBUGLEVEL !=4 */
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#if XTENSA_INT_NLEVELS >=5 && XTENSA_EXCM_LEVEL < 5 && XTENSA_DEBUGLEVEL !=5
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.section .iram1,"ax"
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.section .iram1,"ax"
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.type _xtensa_level5_handler,@function
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.align 4
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_xtensa_level5_handler:
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@@ -465,26 +471,26 @@ _xtensa_level5_handler:
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/* Call interrupt hook if present to (pre)handle interrupts. */
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movi a0, _xt_intexc_hooks
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l32i a0, a0, 5<<2
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l32i a0, a0, 5 << 2
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beqz a0, 1f
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.Ln_xtensa_level5_handler_call_hook:
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callx0 a0 /* must NOT disturb stack! */
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callx0 a0 /* Must NOT disturb stack! */
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1:
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#endif
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/* USER_EDIT:
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ADD HIGH PRIORITY LEVEL 5 INTERRUPT HANDLER CODE HERE.
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*/
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* ADD HIGH PRIORITY LEVEL 5 INTERRUPT HANDLER CODE HERE.
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*/
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.align 4
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.L_xtensa_level5_handler_exit:
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rsr a0, EXCSAVE_5 /* restore a0 */
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rfi 5
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rsr a0, EXCSAVE_5 /* restore a0 */
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rfi 5
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#endif /* XTENSA_INT_NLEVELS >=5 && XTENSA_EXCM_LEVEL < 5 && XTENSA_DEBUGLEVEL !=5 */
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#if XTENSA_INT_NLEVELS >=6 && XTENSA_EXCM_LEVEL < 6 && XTENSA_DEBUGLEVEL !=6
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.section .iram1,"ax"
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.section .iram1,"ax"
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.type _xtensa_level6_handler, @function
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.align 4
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_xtensa_level6_handler:
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@@ -493,20 +499,20 @@ _xtensa_level6_handler:
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/* Call interrupt hook if present to (pre)handle interrupts. */
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movi a0, _xt_intexc_hooks
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l32i a0, a0, 6<<2
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l32i a0, a0, 6 << 2
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beqz a0, 1f
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.Ln_xtensa_level6_handler_call_hook:
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callx0 a0 /* must NOT disturb stack! */
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callx0 a0 /* Must NOT disturb stack! */
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1:
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#endif
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/* USER_EDIT:
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ADD HIGH PRIORITY LEVEL 6 INTERRUPT HANDLER CODE HERE.
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*/
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* ADD HIGH PRIORITY LEVEL 6 INTERRUPT HANDLER CODE HERE.
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*/
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.align 4
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.L_xtensa_level6_handler_exit:
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rsr a0, EXCSAVE_6 /* restore a0 */
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rfi 6
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rsr a0, EXCSAVE_6 /* Restore a0 */
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rfi 6
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#endif /* XTENSA_INT_NLEVELS >=6 && XTENSA_EXCM_LEVEL < 6 && XTENSA_DEBUGLEVEL !=6 */
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