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https://github.com/apache/nuttx.git
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implementation of dumpgpio for stm32l4, was required for pwm debug.
This commit is contained in:
Sebastien Lorquet
committed by
Gregory Nutt
Gregory Nutt
parent
a3112b231c
commit
ec586ab350
@@ -381,6 +381,7 @@
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/* AHB2 peripheral reset register */
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#define RCC_AHB1ENR_GPIOEN(port) (1 << port)
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#define RCC_AHB2RSTR_GPIOARST (1 << 0) /* Bit 0: IO port A reset */
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#define RCC_AHB2RSTR_GPIOBRST (1 << 1) /* Bit 1: IO port B reset */
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#define RCC_AHB2RSTR_GPIOCRST (1 << 2) /* Bit 2: IO port C reset */
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@@ -0,0 +1,153 @@
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/****************************************************************************
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* arch/arm/src/stm32l4/stm32l4_dumpgpio.c
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*
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* Copyright (C) 2016 Sebastien Lorquet. All rights reserved.
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* Author: Sebastien Lorquet <sebastien@lorquet.fr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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/* Output debug info even if debug output is not selected. */
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#undef CONFIG_DEBUG_INFO
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#define CONFIG_DEBUG_INFO 1
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#include <sys/types.h>
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#include <debug.h>
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#include <nuttx/irq.h>
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#include "up_arch.h"
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#include "chip.h"
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#include "stm32l4_gpio.h"
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#include "stm32l4_rcc.h"
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#ifdef CONFIG_DEBUG_FEATURES
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/* Port letters for prettier debug output */
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static const char g_portchar[STM32L4_NPORTS] =
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{
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#if STM32L4_NPORTS > 11
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# error "Additional support required for this number of GPIOs"
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#elif STM32L4_NPORTS > 10
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'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K'
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#elif STM32L4_NPORTS > 9
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'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J'
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#elif STM32L4_NPORTS > 8
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'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I'
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#elif STM32L4_NPORTS > 7
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'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H'
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#elif STM32L4_NPORTS > 6
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'A', 'B', 'C', 'D', 'E', 'F', 'G'
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#elif STM32L4_NPORTS > 5
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'A', 'B', 'C', 'D', 'E', 'F'
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#elif STM32L4_NPORTS > 4
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'A', 'B', 'C', 'D', 'E'
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#elif STM32L4_NPORTS > 3
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'A', 'B', 'C', 'D'
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#elif STM32L4_NPORTS > 2
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'A', 'B', 'C'
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#elif STM32L4_NPORTS > 1
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'A', 'B'
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#elif STM32L4_NPORTS > 0
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'A'
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#else
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# error "Bad number of GPIOs"
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#endif
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};
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Function: stm32l4_dumpgpio
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*
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* Description:
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* Dump all GPIO registers associated with the provided base address
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*
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****************************************************************************/
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int stm32l4_dumpgpio(uint32_t pinset, const char *msg)
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{
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irqstate_t flags;
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uint32_t base;
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unsigned int port;
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/* Get the base address associated with the GPIO port */
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port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
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base = g_gpiobase[port];
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/* The following requires exclusive access to the GPIO registers */
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flags = enter_critical_section();
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DEBUGASSERT(port < STM32L4_NPORTS);
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_info("GPIO%c pinset: %08x base: %08x -- %s\n",
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g_portchar[port], pinset, base, msg);
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if ((getreg32(STM32L4_RCC_AHB1ENR) & RCC_AHB1ENR_GPIOEN(port)) != 0)
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{
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_info(" MODE: %08x OTYPE: %04x OSPEED: %08x PUPDR: %08x\n",
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getreg32(base + STM32L4_GPIO_MODER_OFFSET),
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getreg32(base + STM32L4_GPIO_OTYPER_OFFSET),
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getreg32(base + STM32L4_GPIO_OSPEED_OFFSET),
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getreg32(base + STM32L4_GPIO_PUPDR_OFFSET));
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_info(" IDR: %04x ODR: %04x BSRR: %08x LCKR: %04x\n",
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getreg32(base + STM32L4_GPIO_IDR_OFFSET),
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getreg32(base + STM32L4_GPIO_ODR_OFFSET),
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getreg32(base + STM32L4_GPIO_BSRR_OFFSET),
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getreg32(base + STM32L4_GPIO_LCKR_OFFSET));
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_info(" AFRH: %08x AFRL: %08x\n",
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getreg32(base + STM32L4_GPIO_AFRH_OFFSET),
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getreg32(base + STM32L4_GPIO_AFRL_OFFSET));
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}
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else
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{
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_info(" GPIO%c not enabled: AHB1ENR: %08x\n",
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g_portchar[port], getreg32(STM32L4_RCC_AHB1ENR));
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}
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leave_critical_section(flags);
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return OK;
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}
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#endif /* CONFIG_DEBUG_FEATURES */
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