mirror of
https://github.com/apache/nuttx.git
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Basic SCI support
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@1152 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
+104
-98
@@ -55,68 +55,68 @@
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/* Illegal instructions / Address errors */
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#define SH1_INVINSTR_IRQ (0) /* General invalid instruction */
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#define SH1_INVSLOT_IRQ (1) /* Invalid slot instruction */
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#define SH1_BUSERR_IRQ (2) /* CPU bus error */
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#define SH1_DMAERR_IRQ (3) /* DMA bus error */
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#define SH1_NMI_IRQ (4) /* NMI */
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#define SH1_USRBRK_IRQ (6) /* User break */
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#define SH1_INVINSTR_IRQ (0) /* General invalid instruction */
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#define SH1_INVSLOT_IRQ (1) /* Invalid slot instruction */
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#define SH1_BUSERR_IRQ (2) /* CPU bus error */
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#define SH1_DMAERR_IRQ (3) /* DMA bus error */
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#define SH1_NMI_IRQ (4) /* NMI */
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#define SH1_USRBRK_IRQ (6) /* User break */
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/* Support for traps can be provided by simply enabling the following and
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* implementing the stubs to catch the interrupts
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*/
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#if 0
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# define SH1_TRAP_IRQ (7) /* TRAPA instruction (user break) */
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# define SH1_TRAP0_IRQ (SH1_TRAP_IRQ+0) /* TRAPA instruction (user break) */
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# define SH1_TRAP1_IRQ (SH1_TRAP_IRQ+1) /* " " " " " " " " */
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# define SH1_TRAP2_IRQ (SH1_TRAP_IRQ+2) /* " " " " " " " " */
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# define SH1_TRAP3_IRQ (SH1_TRAP_IRQ+3) /* " " " " " " " " */
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# define SH1_TRAP4_IRQ (SH1_TRAP_IRQ+4) /* " " " " " " " " */
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# define SH1_TRAP5_IRQ (SH1_TRAP_IRQ+5) /* " " " " " " " " */
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# define SH1_TRAP6_IRQ (SH1_TRAP_IRQ+6) /* " " " " " " " " */
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# define SH1_TRAP7_IRQ (SH1_TRAP_IRQ+7) /* " " " " " " " " */
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# define SH1_TRAP8_IRQ (SH1_TRAP_IRQ+8) /* " " " " " " " " */
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# define SH1_TRAP9_IRQ (SH1_TRAP_IRQ+9) /* " " " " " " " " */
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# define SH1_TRAP10_IRQ (SH1_TRAP_IRQ+10) /* " " " " " " " " */
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# define SH1_TRAP11_IRQ (SH1_TRAP_IRQ+11) /* " " " " " " " " */
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# define SH1_TRAP12_IRQ (SH1_TRAP_IRQ+12) /* " " " " " " " " */
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# define SH1_TRAP13_IRQ (SH1_TRAP_IRQ+13) /* " " " " " " " " */
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# define SH1_TRAP14_IRQ (SH1_TRAP_IRQ+14) /* " " " " " " " " */
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# define SH1_TRAP15_IRQ (SH1_TRAP_IRQ+15) /* " " " " " " " " */
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# define SH1_TRAP16_IRQ (SH1_TRAP_IRQ+16) /* " " " " " " " " */
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# define SH1_TRAP17_IRQ (SH1_TRAP_IRQ+17) /* " " " " " " " " */
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# define SH1_TRAP18_IRQ (SH1_TRAP_IRQ+18) /* " " " " " " " " */
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# define SH1_TRAP19_IRQ (SH1_TRAP_IRQ+19) /* " " " " " " " " */
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# define SH1_TRAP20_IRQ (SH1_TRAP_IRQ+20) /* " " " " " " " " */
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# define SH1_TRAP21_IRQ (SH1_TRAP_IRQ+21) /* " " " " " " " " */
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# define SH1_TRAP22_IRQ (SH1_TRAP_IRQ+22) /* " " " " " " " " */
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# define SH1_TRAP23_IRQ (SH1_TRAP_IRQ+23) /* " " " " " " " " */
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# define SH1_TRAP24_IRQ (SH1_TRAP_IRQ+24) /* " " " " " " " " */
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# define SH1_TRAP25_IRQ (SH1_TRAP_IRQ+25) /* " " " " " " " " */
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# define SH1_TRAP26_IRQ (SH1_TRAP_IRQ+26) /* " " " " " " " " */
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# define SH1_TRAP27_IRQ (SH1_TRAP_IRQ+27) /* " " " " " " " " */
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# define SH1_TRAP28_IRQ (SH1_TRAP_IRQ+28) /* " " " " " " " " */
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# define SH1_TRAP29_IRQ (SH1_TRAP_IRQ+29) /* " " " " " " " " */
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# define SH1_TRAP30_IRQ (SH1_TRAP_IRQ+30) /* " " " " " " " " */
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# define SH1_TRAP31_IRQ (SH1_TRAP_IRQ+31) /* " " " " " " " " */
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# define SH1_LASTTRAP_IRQ SH1_TRAP31_IRQ
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# define SH1_TRAP_IRQ (7) /* TRAPA instruction (user break) */
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# define SH1_TRAP0_IRQ (SH1_TRAP_IRQ+0) /* TRAPA instruction (user break) */
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# define SH1_TRAP1_IRQ (SH1_TRAP_IRQ+1) /* " " " " " " " " */
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# define SH1_TRAP2_IRQ (SH1_TRAP_IRQ+2) /* " " " " " " " " */
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# define SH1_TRAP3_IRQ (SH1_TRAP_IRQ+3) /* " " " " " " " " */
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# define SH1_TRAP4_IRQ (SH1_TRAP_IRQ+4) /* " " " " " " " " */
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# define SH1_TRAP5_IRQ (SH1_TRAP_IRQ+5) /* " " " " " " " " */
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# define SH1_TRAP6_IRQ (SH1_TRAP_IRQ+6) /* " " " " " " " " */
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# define SH1_TRAP7_IRQ (SH1_TRAP_IRQ+7) /* " " " " " " " " */
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# define SH1_TRAP8_IRQ (SH1_TRAP_IRQ+8) /* " " " " " " " " */
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# define SH1_TRAP9_IRQ (SH1_TRAP_IRQ+9) /* " " " " " " " " */
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# define SH1_TRAP10_IRQ (SH1_TRAP_IRQ+10) /* " " " " " " " " */
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# define SH1_TRAP11_IRQ (SH1_TRAP_IRQ+11) /* " " " " " " " " */
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# define SH1_TRAP12_IRQ (SH1_TRAP_IRQ+12) /* " " " " " " " " */
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# define SH1_TRAP13_IRQ (SH1_TRAP_IRQ+13) /* " " " " " " " " */
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# define SH1_TRAP14_IRQ (SH1_TRAP_IRQ+14) /* " " " " " " " " */
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# define SH1_TRAP15_IRQ (SH1_TRAP_IRQ+15) /* " " " " " " " " */
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# define SH1_TRAP16_IRQ (SH1_TRAP_IRQ+16) /* " " " " " " " " */
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# define SH1_TRAP17_IRQ (SH1_TRAP_IRQ+17) /* " " " " " " " " */
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# define SH1_TRAP18_IRQ (SH1_TRAP_IRQ+18) /* " " " " " " " " */
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# define SH1_TRAP19_IRQ (SH1_TRAP_IRQ+19) /* " " " " " " " " */
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# define SH1_TRAP20_IRQ (SH1_TRAP_IRQ+20) /* " " " " " " " " */
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# define SH1_TRAP21_IRQ (SH1_TRAP_IRQ+21) /* " " " " " " " " */
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# define SH1_TRAP22_IRQ (SH1_TRAP_IRQ+22) /* " " " " " " " " */
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# define SH1_TRAP23_IRQ (SH1_TRAP_IRQ+23) /* " " " " " " " " */
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# define SH1_TRAP24_IRQ (SH1_TRAP_IRQ+24) /* " " " " " " " " */
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# define SH1_TRAP25_IRQ (SH1_TRAP_IRQ+25) /* " " " " " " " " */
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# define SH1_TRAP26_IRQ (SH1_TRAP_IRQ+26) /* " " " " " " " " */
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# define SH1_TRAP27_IRQ (SH1_TRAP_IRQ+27) /* " " " " " " " " */
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# define SH1_TRAP28_IRQ (SH1_TRAP_IRQ+28) /* " " " " " " " " */
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# define SH1_TRAP29_IRQ (SH1_TRAP_IRQ+29) /* " " " " " " " " */
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# define SH1_TRAP30_IRQ (SH1_TRAP_IRQ+30) /* " " " " " " " " */
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# define SH1_TRAP31_IRQ (SH1_TRAP_IRQ+31) /* " " " " " " " " */
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# define SH1_LASTTRAP_IRQ SH1_TRAP31_IRQ
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#else
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# define SH1_LASTTRAP_IRQ (6)
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# define SH1_LASTTRAP_IRQ (6)
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#endif
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/* Interrupts */
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#define SH1_IRQ_IRQ (SH1_LASTTRAP_IRQ+1) /* IRQ0-7 */
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#define SH1_IRQ0_IRQ (SH1_IRQ_IRQ+0) /* IRQ0 */
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#define SH1_IRQ1_IRQ (SH1_IRQ_IRQ+1) /* IRQ1 */
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#define SH1_IRQ2_IRQ (SH1_IRQ_IRQ+2) /* IRQ2 */
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#define SH1_IRQ3_IRQ (SH1_IRQ_IRQ+3) /* IRQ3 */
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#define SH1_IRQ4_IRQ (SH1_IRQ_IRQ+4) /* IRQ4 */
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#define SH1_IRQ5_IRQ (SH1_IRQ_IRQ+5) /* IRQ5 */
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#define SH1_IRQ6_IRQ (SH1_IRQ_IRQ+6) /* IRQ6 */
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#define SH1_IRQ7_IRQ (SH1_IRQ_IRQ+7) /* IRQ7 */
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#define SH1_LASTIRQ_IRQ SH1_IRQ7_IRQ
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#define SH1_IRQ_IRQ (SH1_LASTTRAP_IRQ+1) /* IRQ0-7 */
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#define SH1_IRQ0_IRQ (SH1_IRQ_IRQ+0) /* IRQ0 */
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#define SH1_IRQ1_IRQ (SH1_IRQ_IRQ+1) /* IRQ1 */
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#define SH1_IRQ2_IRQ (SH1_IRQ_IRQ+2) /* IRQ2 */
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#define SH1_IRQ3_IRQ (SH1_IRQ_IRQ+3) /* IRQ3 */
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#define SH1_IRQ4_IRQ (SH1_IRQ_IRQ+4) /* IRQ4 */
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#define SH1_IRQ5_IRQ (SH1_IRQ_IRQ+5) /* IRQ5 */
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#define SH1_IRQ6_IRQ (SH1_IRQ_IRQ+6) /* IRQ6 */
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#define SH1_IRQ7_IRQ (SH1_IRQ_IRQ+7) /* IRQ7 */
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#define SH1_LASTIRQ_IRQ SH1_IRQ7_IRQ
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/* On-chip modules -- The following may be unique to the 7032 */
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@@ -124,68 +124,74 @@
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/* DMAC */
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#define SH1_DMAC0_IRQ (SH1_LASTIRQ_IRQ+1) /* DMAC0 */
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#define SH1_DEI0_IRQ SH1_DMAC0_IRQ /* DEI0 */
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#define SH1_DMAC1_IRQ (SH1_LASTIRQ_IRQ+2) /* DMAC1 */
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#define SH1_DEI1_IRQ SH1_DMAC1_IRQ /* DEI1 */
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#define SH1_DMAC2_IRQ (SH1_LASTIRQ_IRQ+3) /* DMAC2 */
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#define SH1_DEI2_IRQ SH1_DMAC2_IRQ /* DEI2 */
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#define SH1_DMAC3_IRQ (SH1_LASTIRQ_IRQ+4) /* DMAC3 */
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#define SH1_DEI3_IRQ SH1_DMAC3_IRQ /* DEI3 */
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#define SH1_LASTDMAC_IRQ SH1_DEI3_IRQ
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#define SH1_DMAC0_IRQ (SH1_LASTIRQ_IRQ+1) /* DMAC0 */
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#define SH1_DEI0_IRQ SH1_DMAC0_IRQ /* DEI0 */
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#define SH1_DMAC1_IRQ (SH1_LASTIRQ_IRQ+2) /* DMAC1 */
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#define SH1_DEI1_IRQ SH1_DMAC1_IRQ /* DEI1 */
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#define SH1_DMAC2_IRQ (SH1_LASTIRQ_IRQ+3) /* DMAC2 */
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#define SH1_DEI2_IRQ SH1_DMAC2_IRQ /* DEI2 */
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#define SH1_DMAC3_IRQ (SH1_LASTIRQ_IRQ+4) /* DMAC3 */
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#define SH1_DEI3_IRQ SH1_DMAC3_IRQ /* DEI3 */
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#define SH1_LASTDMAC_IRQ SH1_DEI3_IRQ
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/* ITU */
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#define SH1_ITU0_IRQ (SH1_LASTDMAC_IRQ+1) /* ITU0 */
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#define SH1_IMIA0_IRQ (SH1_ITU0_IRQ+0) /* IMIA0 */
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#define SH1_IMIBO_IRQ (SH1_ITU0_IRQ+1) /* IMIB0 */
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#define SH1_OVI0_IRQ (SH1_ITU0_IRQ+2) /* OVI0 */
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#define SH1_ITU0_IRQ (SH1_LASTDMAC_IRQ+1) /* ITU0 */
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#define SH1_IMIA0_IRQ (SH1_ITU0_IRQ+0) /* IMIA0 */
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#define SH1_IMIBO_IRQ (SH1_ITU0_IRQ+1) /* IMIB0 */
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#define SH1_OVI0_IRQ (SH1_ITU0_IRQ+2) /* OVI0 */
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#define SH1_ITU1_IRQ (SH1_LASTDMAC_IRQ+4) /* ITU1 */
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#define SH1_IMIA1_IRQ (SH1_ITU1_IRQ+0) /* IMIA1 */
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#define SH1_IMIB1_IRQ (SH1_ITU1_IRQ+1) /* IMIB1 */
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#define SH1_OVI1_IRQ (SH1_ITU1_IRQ+2) /* OVI1 */
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#define SH1_ITU1_IRQ (SH1_LASTDMAC_IRQ+4) /* ITU1 */
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#define SH1_IMIA1_IRQ (SH1_ITU1_IRQ+0) /* IMIA1 */
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#define SH1_IMIB1_IRQ (SH1_ITU1_IRQ+1) /* IMIB1 */
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#define SH1_OVI1_IRQ (SH1_ITU1_IRQ+2) /* OVI1 */
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#define SH1_ITU2_IRQ (SH1_LASTDMAC_IRQ+7) /* ITU2 */
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#define SH1_IMIA2_IRQ (SH1_ITU2_IRQ+0) /* IMIA2 */
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#define SH1_IMIB2_IRQ (SH1_ITU2_IRQ+1) /* IMIB2 */
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#define SH1_OVI2_IRQ (SH1_ITU2_IRQ+2) /* OVI2 */
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#define SH1_ITU2_IRQ (SH1_LASTDMAC_IRQ+7) /* ITU2 */
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#define SH1_IMIA2_IRQ (SH1_ITU2_IRQ+0) /* IMIA2 */
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#define SH1_IMIB2_IRQ (SH1_ITU2_IRQ+1) /* IMIB2 */
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#define SH1_OVI2_IRQ (SH1_ITU2_IRQ+2) /* OVI2 */
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#define SH1_ITU3_IRQ (SH1_LASTDMAC_IRQ+10) /* ITU3 */
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#define SH1_IMIA3_IRQ (SH1_ITU3_IRQ+0) /* IMIA3 */
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#define SH1_IMIB3_IRQ (SH1_ITU3_IRQ+1) /* IMIB3 */
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#define SH1_OVI3_IRQ (SH1_ITU3_IRQ+2) /* OVI3 */
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#define SH1_ITU3_IRQ (SH1_LASTDMAC_IRQ+10) /* ITU3 */
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#define SH1_IMIA3_IRQ (SH1_ITU3_IRQ+0) /* IMIA3 */
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#define SH1_IMIB3_IRQ (SH1_ITU3_IRQ+1) /* IMIB3 */
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#define SH1_OVI3_IRQ (SH1_ITU3_IRQ+2) /* OVI3 */
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#define SH1_ITU4_IRQ (SH1_LASTDMAC_IRQ+13) /* ITU4 */
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#define SH1_IMIA4_IRQ (SH1_ITU4_IRQ+0) /* IMIA4 */
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#define SH1_IMIB4_IRQ (SH1_ITU4_IRQ+1) /* IMIB4 */
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#define SH1_OVI4_IRQ (SH1_ITU4_IRQ+2) /* OVI4 */
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#define SH1_ITU4_IRQ (SH1_LASTDMAC_IRQ+13) /* ITU4 */
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#define SH1_IMIA4_IRQ (SH1_ITU4_IRQ+0) /* IMIA4 */
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#define SH1_IMIB4_IRQ (SH1_ITU4_IRQ+1) /* IMIB4 */
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#define SH1_OVI4_IRQ (SH1_ITU4_IRQ+2) /* OVI4 */
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#define SH1_LASTITU_IRQ (SH1_LASTDMAC_IRQ+15)
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#define SH1_LASTITU_IRQ (SH1_LASTDMAC_IRQ+15)
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/* SCI */
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#define SH1_SCI0_IRQ (SH1_LASTITU_IRQ+1) /* SCI0 */
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#define SH1_ERI0_IRQ (SH1_SCI0_IRQ+0) /* ERI0 */
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#define SH1_RXI0_IRQ (SH1_SCI0_IRQ+1) /* RxI0 */
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#define SH1_TXI0_IRQ (SH1_SCI0_IRQ+2) /* TxI0 */
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#define SH1_TEI0_IRQ (SH1_SCI0_IRQ+3) /* TEI0 */
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#define SH1_ERI_IRQ_OFFSET (0) /* ERI0 */
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#define SH1_RXI_IRQ_OFFSET (1) /* RxI0 */
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#define SH1_TXI_IRQ_OFFSET (2) /* TxI0 */
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#define SH1_TEI_IRQ_OFFSET (3) /* TEI0 */
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#define SH1_SCI_NIRQS (4)
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#define SH1_SCI1_IRQ (SH1_LASTITU_IRQ+5) /* SCI1 */
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#define SH1_ERI1_IRQ (SH1_SCI1_IRQ+0) /* ERI1 */
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#define SH1_RXI1_IRQ (SH1_SCI1_IRQ+1) /* RxI1 */
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#define SH1_TXI1_IRQ (SH1_SCI1_IRQ+2) /* TxI1 */
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#define SH1_TEI1_IRQ (SH1_SCI1_IRQ+3) /* TEI1 */
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#define SH1_SCI0_IRQ (SH1_LASTITU_IRQ+1) /* SCI0 */
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#define SH1_ERI0_IRQ (SH1_SCI0_IRQ+SH1_ERI_IRQ_OFFSET) /* ERI0 */
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#define SH1_RXI0_IRQ (SH1_SCI0_IRQ+SH1_RXI_IRQ_OFFSET) /* RxI0 */
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#define SH1_TXI0_IRQ (SH1_SCI0_IRQ+SH1_TXI_IRQ_OFFSET) /* TxI0 */
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#define SH1_TEI0_IRQ (SH1_SCI0_IRQ+SH1_TEI_IRQ_OFFSET) /* TEI0 */
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#define SH1_LASTSCI_IRQ (SH1_LASTITU_IRQ+9)
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#define SH1_SCI1_IRQ (SH1_SCI0_IRQ+SH1_SCI_NIRQS) /* SCI1 */
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#define SH1_ERI1_IRQ (SH1_SCI1_IRQ+SH1_ERI_IRQ_OFFSET) /* ERI1 */
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#define SH1_RXI1_IRQ (SH1_SCI1_IRQ+SH1_RXI_IRQ_OFFSET) /* RxI1 */
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#define SH1_TXI1_IRQ (SH1_SCI1_IRQ+SH1_TXI_IRQ_OFFSET) /* TxI1 */
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#define SH1_TEI1_IRQ (SH1_SCI1_IRQ+SH1_TEI_IRQ_OFFSET) /* TEI1 */
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#define SH1_PEI_IRQ (SH1_LASTSCI_IRQ+1) /* Parity control unit PEI */
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#define SH1_ADITI_IRQ (SH1_LASTSCI_IRQ+2) /* A/D ITI */
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#define SH1_WDTITI_IRQ (SH1_LASTSCI_IRQ+3) /* WDT ITI */
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#define SH1_CMI_IRQ (SH1_LASTSCI_IRQ+4) /* REF CMI */
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#define SH1_LASTSCI_IRQ (SH1_SCI1_IRQ+SH1_SCI_NIRQS)
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#define STR71X_IRQ_SYSTIMER STR71X_IRQ_T0TIMI
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#define NR_IRQS (SH1_CMI_IRQ+1)
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#define SH1_PEI_IRQ (SH1_LASTSCI_IRQ+1) /* Parity control unit PEI */
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#define SH1_ADITI_IRQ (SH1_LASTSCI_IRQ+2) /* A/D ITI */
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#define SH1_WDTITI_IRQ (SH1_LASTSCI_IRQ+3) /* WDT ITI */
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#define SH1_CMI_IRQ (SH1_LASTSCI_IRQ+4) /* REF CMI */
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#define STR71X_IRQ_SYSTIMER STR71X_IRQ_T0TIMI
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#define NR_IRQS (SH1_CMI_IRQ+1)
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#endif
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@@ -52,7 +52,7 @@
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#undef CONFIG_SUPPRESS_INTERRUPTS /* DEFINED: Do not enable interrupts */
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#undef CONFIG_SUPPRESS_TIMER_INTS /* DEFINED: No timer */
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#undef CONFIG_SUPPRESS_SERIAL_INTS /* DEFINED: Console will poll */
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#undef CONFIG_SUPPRESS_UART_CONFIG /* DEFINED: Do not reconfig UART */
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#undef CONFIG_SUPPRESS_SCI_CONFIG /* DEFINED: Do not reconfig SCI */
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#undef CONFIG_DUMP_ON_EXIT /* DEFINED: Dump task state on exit */
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/* Determine which (if any) console driver to use */
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@@ -47,7 +47,7 @@ CMN_CSRCS += up_schedulesigaction.c up_sigdeliver.c
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endif
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CHIP_ASRCS =
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CHIP_CSRCS = sh1_lowputc.c sh1_irq.c sh1_timerisr.c
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CHIP_CSRCS = sh1_lowputc.c sh1_irq.c sh1_timerisr.c sh1_serial.c
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ifeq ($(CONFIG_USBDEV),y)
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CHIP_CSRCS +=
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||||
@@ -43,6 +43,10 @@
|
||||
#include <nuttx/config.h>
|
||||
#include <sys/types.h>
|
||||
|
||||
#ifdef CONFIG_ARCH_SH7032
|
||||
# include "sh1_703x.h"
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Definitions
|
||||
************************************************************************************/
|
||||
|
||||
+26
-25
@@ -296,12 +296,13 @@
|
||||
#define SH1_SCISCR_SISOUT2 (0x01) /* Internal clock, SCK pin used for clock output */
|
||||
#define SH1_SCISCR_SXSIN1 (0x02) /* External clock, SCK pin used for clock input */
|
||||
#define SH1_SCISCR_SXSIN2 (0x03) /* External clock, SCK pin used for clock input */
|
||||
#define SH1_SCISCR_TEIE (0x04) /* Bit 2: Transmit end interrupt enable */
|
||||
#define SH1_SCISCR_MPIE (0x08) /* Bit 3: Multiprocessor interrupt enable */
|
||||
#define SH1_SCISCR_RE (0x10) /* Bit 4: Receiver enable */
|
||||
#define SH1_SCISCR_TE (0x20) /* Bit 5: Transmitter enable */
|
||||
#define SH1_SCISCR_RIE (0x40) /* Bit 6: Recieve-data-full interrupt enable */
|
||||
#define SH1_SCISCR_TIE (Ox80) /* Bit 7: Transmit-data-empty interrupt enable */
|
||||
#define SH1_SCISCR_TEIE (0x04) /* Bit 2: 1=Transmit end interrupt enable */
|
||||
#define SH1_SCISCR_MPIE (0x08) /* Bit 3: 1=Multiprocessor interrupt enable */
|
||||
#define SH1_SCISCR_RE (0x10) /* Bit 4: 1=Receiver enable */
|
||||
#define SH1_SCISCR_TE (0x20) /* Bit 5: 1=Transmitter enable */
|
||||
#define SH1_SCISCR_RIE (0x40) /* Bit 6: 1=Recieve-data-full interrupt enable */
|
||||
#define SH1_SCISCR_TIE (Ox80) /* Bit 7: 1=Transmit-data-empty interrupt enable */
|
||||
#define SH1_SCISCR_ALLINTS (0xcc)
|
||||
|
||||
#define SH1_SCISSR_MPBT (0x01) /* Bit 0: Multi-processor Bit in Transmit data */
|
||||
#define SH1_SCISSR_MPB (0x02) /* Bit 1: Multi-processor Bit in receive data */
|
||||
@@ -314,47 +315,47 @@
|
||||
|
||||
/* Interrupt Controller (INTC) */
|
||||
|
||||
#define SH1_IPRA_IRQ3MASK (0x000f) /* Bits 0-3: IRQ3
|
||||
#define SH1_IPRA_IRQ3MASK (0x000f) /* Bits 0-3: IRQ3 */
|
||||
#define SH1_IPRA_IRQ3SHIFT (0)
|
||||
#define SH1_IPRA_IRQ2MASK (0x00f0) /* Bits 4-7: IRQ2
|
||||
#define SH1_IPRA_IRQ2MASK (0x00f0) /* Bits 4-7: IRQ2 */
|
||||
#define SH1_IPRA_IRQ2SHIFT (4)
|
||||
#define SH1_IPRA_IRQ1MASK (0x0f00) /* Bits 8-11: IRQ1
|
||||
#define SH1_IPRA_IRQ1MASK (0x0f00) /* Bits 8-11: IRQ1 */
|
||||
#define SH1_IPRA_IRQ1SHIFT (8)
|
||||
#define SH1_IPRA_IRQ0MASK (0xf000) /* Bits 12-15: IRQ0
|
||||
#define SH1_IPRA_IRQ0MASK (0xf000) /* Bits 12-15: IRQ0 */
|
||||
#define SH1_IPRA_IRQ0SHIFT (12)
|
||||
|
||||
#define SH1_IPRB_IRQ7MASK (0x000f) /* Bits 0-3: IRQ7
|
||||
#define SH1_IPRB_IRQ7MASK (0x000f) /* Bits 0-3: IRQ7 */
|
||||
#define SH1_IPRB_IRQ7SHIFT (0)
|
||||
#define SH1_IPRB_IRQ6MASK (0x00f0) /* Bits 4-7: IRQ6
|
||||
#define SH1_IPRB_IRQ6MASK (0x00f0) /* Bits 4-7: IRQ6 */
|
||||
#define SH1_IPRB_IRQ6SHIFT (4)
|
||||
#define SH1_IPRB_IRQ5MASK (0x0f00) /* Bits 8-11: IRQ5
|
||||
#define SH1_IPRB_IRQ5MASK (0x0f00) /* Bits 8-11: IRQ5 */
|
||||
#define SH1_IPRB_IRQ5SHIFT (8)
|
||||
#define SH1_IPRB_IRQ4MASK (0xf000) /* Bits 12-15: IRQ4
|
||||
#define SH1_IPRB_IRQ4MASK (0xf000) /* Bits 12-15: IRQ4 */
|
||||
#define SH1_IPRB_IRQ4SHIFT (12)
|
||||
|
||||
#define SH1_IPRC_ITU1MASK (0x000f) /* Bits 0-3: ITU1
|
||||
#define SH1_IPRC_ITU1MASK (0x000f) /* Bits 0-3: ITU1 */
|
||||
#define SH1_IPRC_ITU1SHIFT (0)
|
||||
#define SH1_IPRC_ITU0MASK (0x00f0) /* Bits 4-7: ITU0
|
||||
#define SH1_IPRC_ITU0MASK (0x00f0) /* Bits 4-7: ITU0 */
|
||||
#define SH1_IPRC_ITU0SHIFT (4)
|
||||
#define SH1_IPRC_DM23MASK (0x0f00) /* Bits 8-11: DMAC2,3
|
||||
#define SH1_IPRC_DM23MASK (0x0f00) /* Bits 8-11: DMAC2,3 */
|
||||
#define SH1_IPRC_DM23SHIFT (8)
|
||||
#define SH1_IPRC_DM01MASK (0xf000) /* Bits 12-15: DMAC0,1
|
||||
#define SH1_IPRC_DM01MASK (0xf000) /* Bits 12-15: DMAC0,1 */
|
||||
#define SH1_IPRC_DM01SHIFT (12)
|
||||
|
||||
#define SH1_IPRD_SCI0MASK (0x000f) /* Bits 0-3: SCI0
|
||||
#define SH1_IPRD_SCI0MASK (0x000f) /* Bits 0-3: SCI0 */
|
||||
#define SH1_IPRD_SCI0SHIFT (0)
|
||||
#define SH1_IPRD_ITU4MASK (0x00f0) /* Bits 4-7: ITU4
|
||||
#define SH1_IPRD_ITU4MASK (0x00f0) /* Bits 4-7: ITU4 */
|
||||
#define SH1_IPRD_ITU4SHIFT (4)
|
||||
#define SH1_IPRD_ITU3MASK (0x0f00) /* Bits 8-11: ITU3
|
||||
#define SH1_IPRD_ITU3MASK (0x0f00) /* Bits 8-11: ITU3 */
|
||||
#define SH1_IPRD_ITU3SHIFT (8)
|
||||
#define SH1_IPRD_ITU2MASK (0xf000) /* Bits 12-15: ITU2
|
||||
#define SH1_IPRD_ITU2MASK (0xf000) /* Bits 12-15: ITU2 */
|
||||
#define SH1_IPRD_ITU2SHIFT (12)
|
||||
|
||||
#define SH1_IPRE_WDRFMASK (0x00f0) /* Bits 4-7: WDT, REF
|
||||
#define SH1_IPRE_WDRFMASK (0x00f0) /* Bits 4-7: WDT, REF */
|
||||
#define SH1_IPRE_WDRFSHIFT (4)
|
||||
#define SH1_IPRE_PRADMASK (0x0f00) /* Bits 8-11: PRT, A/D
|
||||
#define SH1_IPRE_PRADMASK (0x0f00) /* Bits 8-11: PRT, A/D */
|
||||
#define SH1_IPRE_PRADSHIFT (8)
|
||||
#define SH1_IPRE_SCI1MASK (0xf000) /* Bits 12-15: SCI1
|
||||
#define SH1_IPRE_SCI1MASK (0xf000) /* Bits 12-15: SCI1 */
|
||||
#define SH1_IPRE_SCI1SHIFT (12)
|
||||
|
||||
#define SH1_ICR_IRQ7S (0x0001) /* Bits 0: Interrupt on falling edge of IRQ7 input */
|
||||
|
||||
+124
-30
@@ -40,10 +40,13 @@
|
||||
#include <nuttx/config.h>
|
||||
#include <sys/types.h>
|
||||
|
||||
#include <nuttx/arch.h>
|
||||
|
||||
#include "up_internal.h"
|
||||
#include "up_arch.h"
|
||||
|
||||
#include "chip.h"
|
||||
#include "up_internal.h"
|
||||
|
||||
/**************************************************************************
|
||||
* Private Definitions
|
||||
@@ -53,7 +56,7 @@
|
||||
|
||||
/* Is there a serial console? */
|
||||
|
||||
#if defined(CONFIG_UART0_SERIAL_CONSOLE) || defined(CONFIG_UART1_SERIAL_CONSOLE)
|
||||
#if defined(CONFIG_SCI0_SERIAL_CONSOLE) || defined(CONFIG_SCI1_SERIAL_CONSOLE)
|
||||
# define HAVE_CONSOLE
|
||||
#else
|
||||
# undef HAVE_CONSOLE
|
||||
@@ -61,46 +64,80 @@
|
||||
|
||||
/* Select UART parameters for the selected console */
|
||||
|
||||
#if defined(CONFIG_UART0_SERIAL_CONSOLE)
|
||||
# define SH1_UART_BASE
|
||||
# define SH1_UART_BAUD CONFIG_UART0_BAUD
|
||||
# define SH1_UART_BITS CONFIG_UART0_BITS
|
||||
# define SH1_UART_PARITY CONFIG_UART0_PARITY
|
||||
# define SH1_UART_2STOP CONFIG_UART0_2STOP
|
||||
#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
|
||||
# define SH1_UART_BASE
|
||||
# define SH1_UART_BAUD CONFIG_UART1_BAUD
|
||||
# define SH1_UART_BITS CONFIG_UART1_BITS
|
||||
# define SH1_UART_PARITY CONFIG_UART1_PARITY
|
||||
# define SH1_UART_2STOP CONFIG_UART1_2STOP
|
||||
#if defined(CONFIG_SCI0_SERIAL_CONSOLE)
|
||||
# define SH1_SCI_BASE SH1_SCI0_BASE
|
||||
# define SH1_SCI_BAUD CONFIG_SCI0_BAUD
|
||||
# define SH1_SCI_BITS CONFIG_SCI0_BITS
|
||||
# define SH1_SCI_PARITY CONFIG_SCI0_PARITY
|
||||
# define SH1_SCI_2STOP CONFIG_SCI0_2STOP
|
||||
#elif defined(CONFIG_SCI1_SERIAL_CONSOLE)
|
||||
# define SH1_SCI_BASE SH1_SCI1_BASE
|
||||
# define SH1_SCI_BAUD CONFIG_SCI1_BAUD
|
||||
# define SH1_SCI_BITS CONFIG_SCI1_BITS
|
||||
# define SH1_SCI_PARITY CONFIG_SCI1_PARITY
|
||||
# define SH1_SCI_2STOP CONFIG_SCI1_2STOP
|
||||
#else
|
||||
# error "No CONFIG_UARTn_SERIAL_CONSOLE Setting"
|
||||
# error "No CONFIG_SCIn_SERIAL_CONSOLE Setting"
|
||||
#endif
|
||||
|
||||
/* Get mode setting */
|
||||
|
||||
#if SH1_UART_BITS == 7
|
||||
# define SH1_UARTCR_MODE
|
||||
#elif SH1_UART_BITS == 8
|
||||
# define SH1_UARTCR_MODE SH1_UARTCR_MODE8BITP
|
||||
#if SH1_SCI_BITS == 7
|
||||
# define SH1_SMR_MODE SH1_SCISMR_CHR
|
||||
#elif SH1_SCI_BITS == 8
|
||||
# define SH1_SMR_MODE (0)
|
||||
#else
|
||||
# error "Number of bits not supported"
|
||||
#endif
|
||||
|
||||
#if SH1_UART_PARITY == 0 || SH1_UART_PARITY == 2
|
||||
# define SH1_UARTCR_PARITY
|
||||
#elif SH1_UART_PARITY == 1
|
||||
# define SH1_UARTCR_PARITY SH1_UARTCR_PARITYODD
|
||||
#if SH1_SCI_PARITY == 0
|
||||
# define SH1_SMR_PARITY (0)
|
||||
#elif SH1_SCI_PARITY == 1
|
||||
# define SH1_SMR_PARITY (SH1_SCISMR_PE|SH1_SCISMR_OE)
|
||||
#elif SH1_SCI_PARITY == 2
|
||||
# define SH1_SMR_PARITY SH1_SCISMR_PE
|
||||
#else
|
||||
# error "Invalid parity selection"
|
||||
#endif
|
||||
|
||||
#if SH1_UART_2STOP != 0
|
||||
# define SH1_UARTCR_STOP
|
||||
#if SH1_SCI_2STOP != 0
|
||||
# define SH1_SMR_STOP SH1_SCISMR_STOP
|
||||
#else
|
||||
# define SH1_UARTCR_STOP
|
||||
# define SH1_SMR_STOP (0)
|
||||
#endif
|
||||
|
||||
/* The full SMR setting also includes internal clocking with no divisor,
|
||||
* aysnchronous operation and multiprocessor disabled:
|
||||
*/
|
||||
|
||||
#define SH1_SMR_VALUE (SH1_SMR_MODE|SH1_SMR_PARITY|SH1_SMR_STOP)
|
||||
|
||||
/* Clocking ***************************************************************/
|
||||
|
||||
/* The calculation of the BRR to achieve the desired BAUD is given by the
|
||||
* following formula:
|
||||
*
|
||||
* brr = (f/(64*2**(2n-1)*b))-1
|
||||
*
|
||||
* Where:
|
||||
*
|
||||
* b = bit rate
|
||||
* f = frequency (Hz)
|
||||
* n = divider setting (0, 1, 2, 3)
|
||||
*
|
||||
* For n == 0, this simplifies to:
|
||||
*
|
||||
* brr = (f/(32*b))-1
|
||||
*
|
||||
* For example, if the processor is clocked at 10 MHz and 9600 is the
|
||||
* desired BAUD:
|
||||
*
|
||||
* brr = 10,000,000 / (32 * 9600) - 1 = 31.552 (or 32 after rounding)
|
||||
*/
|
||||
|
||||
#define SH1_DIVISOR (32 * SH1_SCI_BAUD)
|
||||
#define SH1_BRR (((SH1_CLOCK + (SH1_DIVISOR/2))/SH1_DIVISOR)-1)
|
||||
|
||||
/**************************************************************************
|
||||
* Private Types
|
||||
**************************************************************************/
|
||||
@@ -121,6 +158,19 @@
|
||||
* Private Functions
|
||||
**************************************************************************/
|
||||
|
||||
/**************************************************************************
|
||||
* Name: up_txready
|
||||
*
|
||||
* Description:
|
||||
* Return TRUE of the Transmit Data Register is empty
|
||||
*
|
||||
**************************************************************************/
|
||||
|
||||
int inline up_txready(void)
|
||||
{
|
||||
return getreg8(SH1_SCI_BASE + SH1_SCI_SSR_OFFSET) & SH1_SCISSR_TDRE;
|
||||
}
|
||||
|
||||
/**************************************************************************
|
||||
* Public Functions
|
||||
**************************************************************************/
|
||||
@@ -136,7 +186,21 @@
|
||||
void up_lowputc(char ch)
|
||||
{
|
||||
#ifdef HAVE_CONSOLE
|
||||
# warning "To be provided"
|
||||
ubyte ssr;
|
||||
|
||||
/* Wait until the TDR is avaible */
|
||||
|
||||
while (!up_txready());
|
||||
|
||||
/* Write the data to the TDR */
|
||||
|
||||
putreg8(ch, SH1_SCI_BASE + SH1_SCI_TDR_OFFSET);
|
||||
|
||||
/* Clear the TDRE bit in the SSR */
|
||||
|
||||
ssr = getreg8(SH1_SCI_BASE + SH1_SCI_SSR_OFFSET);
|
||||
ssr &= ~SH1_SCISSR_TDRE;
|
||||
putreg8(ssr, SH1_SCI_BASE + SH1_SCI_SSR_OFFSET);
|
||||
#endif
|
||||
}
|
||||
|
||||
@@ -152,9 +216,39 @@ void up_lowputc(char ch)
|
||||
|
||||
void up_lowsetup(void)
|
||||
{
|
||||
#ifdef HAVE_CONSOLE
|
||||
# warning "To be provided"
|
||||
#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_SCI_CONFIG)
|
||||
ubyte scr;
|
||||
|
||||
/* Disable the transmitter and receiver */
|
||||
|
||||
scr = getreg8(SH1_SCI_BASE + SH1_SCI_SCR_OFFSET);
|
||||
scr &= ~(SH1_SCISCR_TE | SH1_SCISCR_RE);
|
||||
putreg8(scr, SH1_SCI_BASE + SH1_SCI_SCR_OFFSET);
|
||||
|
||||
/* Set communication to be asynchronous with the configured number of data
|
||||
* bits, parity, and stop bits. Use the internal clock (undivided)
|
||||
*/
|
||||
|
||||
putreg8(SH1_SMR_VALUE, SH1_SCI_BASE + SH1_SCI_SMR_OFFSET);
|
||||
|
||||
/* Set the baud based on the configured console baud and configured
|
||||
* system clock.
|
||||
*/
|
||||
|
||||
putreg8(SH1_BRR, SH1_SCI_BASE + SH1_SCI_BRR_OFFSET);
|
||||
|
||||
/* Select the internal clock source as input */
|
||||
|
||||
scr &= ~SH1_SCISCR_CKEMASK;
|
||||
putreg8(scr, SH1_SCI_BASE + SH1_SCI_SCR_OFFSET);
|
||||
|
||||
/* Wait a bit for the clocking to settle */
|
||||
|
||||
up_udelay(100);
|
||||
|
||||
/* Then enable the transmitter and reciever */
|
||||
|
||||
scr |= (SH1_SCISCR_TE | SH1_SCISCR_RE);
|
||||
putreg8(scr, SH1_SCI_BASE + SH1_SCI_SCR_OFFSET);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -51,8 +51,14 @@
|
||||
|
||||
/* Clocking *****************************************************************/
|
||||
|
||||
#define SH1_CLOCK 10000000 /* 10 MHz */
|
||||
|
||||
/* LED definitions **********************************************************/
|
||||
|
||||
/* The SH1_LPEVB has no user controllable LEDs. These are provided only
|
||||
* in the event that CONFIG_ARCH_LEDs is enabled.
|
||||
*/
|
||||
|
||||
#define LED_STARTED 0
|
||||
#define LED_HEAPALLOCATE 1
|
||||
#define LED_IRQSENABLED 2
|
||||
|
||||
@@ -92,20 +92,20 @@ CONFIG_ARCH_STACKDUMP=y
|
||||
# CONFIG_UARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity, 3=mark 1, 4=space 0
|
||||
# CONFIG_UARTn_2STOP - Two stop bits
|
||||
#
|
||||
CONFIG_UART0_SERIAL_CONSOLE=y
|
||||
CONFIG_UART1_SERIAL_CONSOLE=n
|
||||
CONFIG_UART0_TXBUFSIZE=256
|
||||
CONFIG_UART1_TXBUFSIZE=256
|
||||
CONFIG_UART0_RXBUFSIZE=256
|
||||
CONFIG_UART1_RXBUFSIZE=256
|
||||
CONFIG_UART0_BAUD=38400
|
||||
CONFIG_UART1_BAUD=38400
|
||||
CONFIG_UART0_BITS=8
|
||||
CONFIG_UART1_BITS=8
|
||||
CONFIG_UART0_PARITY=0
|
||||
CONFIG_UART1_PARITY=0
|
||||
CONFIG_UART0_2STOP=0
|
||||
CONFIG_UART1_2STOP=0
|
||||
CONFIG_SCI0_SERIAL_CONSOLE=y
|
||||
CONFIG_SCI1_SERIAL_CONSOLE=n
|
||||
CONFIG_SCI0_TXBUFSIZE=256
|
||||
CONFIG_SCI1_TXBUFSIZE=256
|
||||
CONFIG_SCI0_RXBUFSIZE=256
|
||||
CONFIG_SCI1_RXBUFSIZE=256
|
||||
CONFIG_SCI0_BAUD=9600
|
||||
CONFIG_SCI1_BAUD=9600
|
||||
CONFIG_SCI0_BITS=8
|
||||
CONFIG_SCI1_BITS=8
|
||||
CONFIG_SCI0_PARITY=0
|
||||
CONFIG_SCI1_PARITY=0
|
||||
CONFIG_SCI0_2STOP=0
|
||||
CONFIG_SCI1_2STOP=0
|
||||
|
||||
#
|
||||
# General build options
|
||||
|
||||
@@ -67,7 +67,9 @@
|
||||
#ifdef CONFIG_ARCH_LEDS
|
||||
void up_ledinit(void)
|
||||
{
|
||||
#warning "To be provided"
|
||||
/* The SH1_LPEVB has no user controllable LEDs. This is provided only
|
||||
* in the event that CONFIG_ARCH_LEDs is enabled.
|
||||
*/
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
@@ -76,7 +78,9 @@ void up_ledinit(void)
|
||||
|
||||
void up_ledon(int led)
|
||||
{
|
||||
#warning "To be provided"
|
||||
/* The SH1_LPEVB has no user controllable LEDs. This is provided only
|
||||
* in the event that CONFIG_ARCH_LEDs is enabled.
|
||||
*/
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
@@ -85,6 +89,8 @@ void up_ledon(int led)
|
||||
|
||||
void up_ledoff(int led)
|
||||
{
|
||||
#warning "To be provided"
|
||||
/* The SH1_LPEVB has no user controllable LEDs. This is provided only
|
||||
* in the event that CONFIG_ARCH_LEDs is enabled.
|
||||
*/
|
||||
}
|
||||
#endif /* CONFIG_ARCH_LEDS */
|
||||
|
||||
Reference in New Issue
Block a user