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Minor updates from review of last PR.

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This commit is contained in:
Gregory Nutt
2019-08-15 10:05:21 -06:00
parent 77c3a06fea
commit eb4fff5221
4 changed files with 12 additions and 8 deletions
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arch/arm/src/stm32h7/stm32_bbsram.c
+3 -5
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@@ -110,7 +110,6 @@
/* File Header */ /* File Header */
struct bbsramfh_s struct bbsramfh_s
{ {
uint32_t crc; /* CRC calculated over data and this struct uint32_t crc; /* CRC calculated over data and this struct
@@ -118,14 +117,13 @@ struct bbsramfh_s
union union
{ {
uint32_t unit32; /* uint32 access to force ECC from preventing uint32_t unit32; /* uint32 access to force ECC from preventing
commit */ * commit */
struct struct
{ {
uint8_t fileno; /* The minor number */ uint8_t fileno; /* The minor number */
uint8_t dirty; /* Data has been written to the file */ uint8_t dirty; /* Data has been written to the file */
uint16_t len; /* Total Bytes in this file */ uint16_t len; /* Total Bytes in this file */
}; };
}; };
struct timespec lastwrite; /* Last write time */ struct timespec lastwrite; /* Last write time */
@@ -239,7 +237,7 @@ static void stm32_bbsram_semgive(FAR struct stm32_bbsram_s *priv)
* Returned Value: * Returned Value:
* None * None
* *
****************************************************************************/ ****************************************************************************/
static void stm32_bbsram_semtake(FAR struct stm32_bbsram_s *priv) static void stm32_bbsram_semtake(FAR struct stm32_bbsram_s *priv)
{ {
@@ -470,6 +468,7 @@ static off_t stm32_bbsram_seek(FAR struct file *filep, off_t offset,
break; break;
default: default:
/* Return EINVAL if the whence argument is invalid */ /* Return EINVAL if the whence argument is invalid */
stm32_bbsram_semgive(bbr); stm32_bbsram_semgive(bbr);
@@ -739,7 +738,6 @@ static int stm32_bbsram_probe(int *ent, struct stm32_bbsram_s pdev[])
pf->fileno != i || pf->fileno != i ||
pf->crc != stm32_bbsram_crc(pf)) pf->crc != stm32_bbsram_crc(pf))
{ {
/* Not Valid so wipe the file in BBSRAM */ /* Not Valid so wipe the file in BBSRAM */
memset((uint8_t *)pf, 0, alloc); memset((uint8_t *)pf, 0, alloc);
arch/arm/src/stm32h7/stm32_bbsram.h
+1
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@@ -106,6 +106,7 @@ extern "C"
/**************************************************************************** /****************************************************************************
* Public Function Prototypes * Public Function Prototypes
****************************************************************************/ ****************************************************************************/
/**************************************************************************** /****************************************************************************
* Function: stm32_bbsraminitialize * Function: stm32_bbsraminitialize
* *
arch/arm/src/stm32h7/stm32_pwr.c
+3 -3
View File
@@ -74,7 +74,8 @@ static inline void stm32_pwr_putreg(uint32_t offset, uint32_t value)
putreg32(value, STM32_PWR_BASE + offset); putreg32(value, STM32_PWR_BASE + offset);
} }
static inline void stm32_pwr_modifyreg(uint32_t offset, uint32_t clearbits, uint32_t setbits) static inline void stm32_pwr_modifyreg(uint32_t offset, uint32_t clearbits,
uint32_t setbits)
{ {
modifyreg32(STM32_PWR_BASE + offset, clearbits, setbits); modifyreg32(STM32_PWR_BASE + offset, clearbits, setbits);
} }
@@ -183,7 +184,7 @@ void stm32_pwr_enablebkp(bool writable)
stm32_pwr_putreg(STM32_PWR_CR1_OFFSET, regval); stm32_pwr_putreg(STM32_PWR_CR1_OFFSET, regval);
wait = true; wait = true;
} }
leave_critical_section(flags); leave_critical_section(flags);
@@ -282,7 +283,6 @@ void stm32_pwr_disablepvd(void)
void stm32_pwr_enablebreg(bool regon) void stm32_pwr_enablebreg(bool regon)
{ {
irqstate_t flags; irqstate_t flags;
uint32_t regval; uint32_t regval;
uint32_t reg_wait = 0; uint32_t reg_wait = 0;
boards/arm/s32k1xx/s32k118evb/include/board.h
+5
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@@ -53,6 +53,11 @@
/* Clocking *****************************************************************/ /* Clocking *****************************************************************/
/* The S32K118EVB is fitted with a 40MHz Crystal */
#define BOARD_XTAL_FREQUENCY 40000000
/* The S32K118 will run at 48MHz *.
/* LED definitions **********************************************************/ /* LED definitions **********************************************************/