mirror of
https://github.com/apache/nuttx.git
synced 2026-05-31 23:40:19 +08:00
Merged in david_s5/nuttx/master_h7 (pull request #995)
Master h7 * stm327f:Kconfig add depends on BBSRAM * stm32h7:memorymap fix BBSRAM name * stm32h7:Add BBSRAM support Approved-by: Gregory Nutt <gnutt@nuttx.org>
This commit is contained in:
David Sidrane
committed by
Gregory Nutt
Gregory Nutt
parent
17a4efe031
commit
77c3a06fea
@@ -2368,10 +2368,12 @@ config STM32F7_BBSRAM
|
||||
config STM32F7_BBSRAM_FILES
|
||||
int "Max Files to support in BBSRAM"
|
||||
default 4
|
||||
depends on STM32F7_BBSRAM
|
||||
|
||||
config STM32F7_SAVE_CRASHDUMP
|
||||
bool "Enable Saving Panic to BBSRAM"
|
||||
default n
|
||||
depends on STM32F7_BBSRAM
|
||||
|
||||
endif # STM32F7_BKPSRAM
|
||||
|
||||
|
||||
@@ -134,6 +134,10 @@ config STM32H7_TIM
|
||||
bool
|
||||
default n
|
||||
|
||||
config STM32H7_PWR
|
||||
bool "PWR"
|
||||
default n
|
||||
|
||||
config STM32H7_PWM
|
||||
bool
|
||||
default n
|
||||
@@ -158,6 +162,11 @@ config STM32H7_ADC3
|
||||
default n
|
||||
select STM32H7_ADC
|
||||
|
||||
config STM32H7_BKPSRAM
|
||||
bool "Enable BKP RAM Domain"
|
||||
select STM32H7_PWR
|
||||
default n
|
||||
|
||||
config STM32H7_DMA1
|
||||
bool "DMA1"
|
||||
default n
|
||||
@@ -974,6 +983,25 @@ config SDMMC2_SDIO_PULLUP
|
||||
|
||||
endmenu # "SDMMC2 Configuration"
|
||||
endmenu # "SD/MMC Configuration"
|
||||
|
||||
if STM32H7_BKPSRAM
|
||||
|
||||
config STM32H7_BBSRAM
|
||||
bool "BBSRAM File Support"
|
||||
default n
|
||||
|
||||
config STM32H7_BBSRAM_FILES
|
||||
int "Max Files to support in BBSRAM"
|
||||
default 4
|
||||
depends on STM32H7_BBSRAM
|
||||
|
||||
config STM32H7_SAVE_CRASHDUMP
|
||||
bool "Enable Saving Panic to BBSRAM"
|
||||
default n
|
||||
depends on STM32H7_BBSRAM
|
||||
|
||||
endif # STM32H7_BKPSRAM
|
||||
|
||||
config STM32H7_CUSTOM_CLOCKCONFIG
|
||||
bool "Custom clock configuration"
|
||||
default n
|
||||
|
||||
@@ -112,6 +112,10 @@ ifeq ($(CONFIG_STM32H7_ADC),y)
|
||||
CHIP_CSRCS += stm32_adc.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_STM32H7_BBSRAM),y)
|
||||
CHIP_CSRCS += stm32_bbsram.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_STM32H7_DMA),y)
|
||||
CHIP_CSRCS += stm32_dma.c
|
||||
endif
|
||||
@@ -120,6 +124,10 @@ ifeq ($(CONFIG_STM32H7_I2C),y)
|
||||
CHIP_CSRCS += stm32_i2c.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_STM32H7_PWR),y)
|
||||
CHIP_CSRCS += stm32_pwr.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_STM32H7_SPI),y)
|
||||
CHIP_CSRCS += stm32_spi.c
|
||||
endif
|
||||
|
||||
@@ -80,7 +80,7 @@
|
||||
#define STM32_SRAM3_BASE 0x3004c000 /* 0x30040000-0x30047fff: System SRAM3 */
|
||||
#define STM32_SRAM123_BASE 0x30000000 /* 0x30000000-0x30047fff: System SRAM123 */
|
||||
#define STM32_SRAM4_BASE 0x38000000 /* 0x38000000-0x3800ffff: System SRAM4 */
|
||||
#define STM32_BBRAM_BASE 0x38800000 /* 0x38800000-0x38800fff: System BBRAM */
|
||||
#define STM32_BBSRAM_BASE 0x38800000 /* 0x38800000-0x38800fff: System Backup SRAM */
|
||||
|
||||
/* Peripheral Base Addresses ********************************************************/
|
||||
|
||||
|
||||
@@ -107,6 +107,18 @@
|
||||
|
||||
/* Power control register 2 (CR2) */
|
||||
|
||||
#define PWR_CR2_BREN (1 << 0) /* Bit 0: Backup regulator enable */
|
||||
/* Bits 1-3: Reserved */
|
||||
#define PWR_CR2_MONEN (1 << 4) /* Bit 4: VBAT and temperature monitoring enable */
|
||||
/* Bits 5-15: Reserved */
|
||||
#define PWR_CR2_BRRDY (1 << 16) /* Bit 16: Backup regulator ready */
|
||||
/* Bits 17-19: Reserved */
|
||||
#define PWR_CR2_VBATL (1 << 20) /* Bit 20: VBAT level monitoring versus low threshold */
|
||||
#define PWR_CR2_VBATH (1 << 21) /* Bit 21: VBAT level monitoring versus high threshold */
|
||||
#define PWR_CR2_TEMPL (1 << 22) /* Bit 22: Temperature level monitoring versus low threshold */
|
||||
#define PWR_CR2_TEMPH (1 << 23) /* Bit 23: Temperature level monitoring versus high threshold */
|
||||
/* Bits 24-31: Reserved */
|
||||
|
||||
/* Power control register 3 (CR3) */
|
||||
|
||||
#define STM32_PWR_CR3_BYPASS (1 << 0) /* Bit 0: Power management unit bypass */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,160 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/stm32h7/stm32_bbsram.h
|
||||
*
|
||||
* Copyright (C) 2015-2016 Gregory Nutt. All rights reserved.
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32H7_STM32_BBSRAM_H
|
||||
#define __ARCH_ARM_SRC_STM32H7_STM32_BBSRAM_H
|
||||
|
||||
/****************************************************************************
|
||||
* The purpose of this driver is to add battery backup file to the file
|
||||
* system. There can be CONFIG_STM32H7_BBRSRAM_COUNT files defined.
|
||||
* These files are of fixed size up to the maximum of the backing 4K SRAM.
|
||||
*
|
||||
* If CONFIG_SAVE_CRASHDUMP is defined The driver also supports a feature
|
||||
* to save the context of a PANIC in one of these files.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <nuttx/fs/ioctl.h>
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#define STM32H7_BBSRAM_SIZE 4096
|
||||
|
||||
#if !defined(CONFIG_STM32H7_BBSRAM_FILES)
|
||||
# define CONFIG_STM32H7_BBSRAM_FILES 4
|
||||
#endif
|
||||
|
||||
/* REVISIT: What guarantees that STM32H7_BBSRAM_GETDESC_IOCTL has a unique
|
||||
* value among all over _DIOC() values?
|
||||
*/
|
||||
|
||||
#define STM32H7_BBSRAM_GETDESC_IOCTL _DIOC(0x0010) /* Returns a bbsramd_s */
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
enum bbsramdf_e
|
||||
{
|
||||
BBSRAM_CRC_VALID = 1, /* The crc is valid */
|
||||
BBSRAM_DIRTY = 2, /* The file was closed */
|
||||
};
|
||||
|
||||
struct bbsramd_s
|
||||
{
|
||||
uint8_t flags; /* The crc is valid and the file was closed */
|
||||
uint8_t fileno; /* The minor number */
|
||||
uint16_t len; /* Total Bytes in this file*/
|
||||
struct timespec lastwrite; /* Last write time */
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
# define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
# define EXTERN extern
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
/****************************************************************************
|
||||
* Function: stm32_bbsraminitialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize the Battery Backed up SRAM driver.
|
||||
*
|
||||
* Input Parameters:
|
||||
* devpath - the path to instantiate the files.
|
||||
* sizes - Pointer to a any array of file sizes to create
|
||||
* the last entry should be 0
|
||||
* A size of -1 will use all the remaining spaces
|
||||
*
|
||||
* If the length of sizes is greater then CONFIG_STM32H7_BBSRAM_FILES
|
||||
* CONFIG_STM32H7_BBSRAM_FILES will be returned.
|
||||
*
|
||||
* Returned Value:
|
||||
* Number of files created on success; Negated errno on failure.
|
||||
*
|
||||
* Assumptions:
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int stm32_bbsraminitialize(char *devpath, int *sizes);
|
||||
|
||||
/****************************************************************************
|
||||
* Function: stm32_bbsram_savepanic
|
||||
*
|
||||
* Description:
|
||||
* Saves the panic context in a previously allocated BBSRAM file
|
||||
*
|
||||
* Parameters:
|
||||
* fileno - the value returned by the ioctl STM32H7_BBSRAM_GETDESC_IOCTL
|
||||
* context - Pointer to a any array of bytes to save
|
||||
* length - The length of the data pointed to byt context
|
||||
*
|
||||
* Returned Value:
|
||||
* Length saved or negated errno.
|
||||
*
|
||||
* Assumptions:
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#if defined(CONFIG_STM32H7_SAVE_CRASHDUMP)
|
||||
int stm32_bbsram_savepanic(int fileno, uint8_t *context, int length);
|
||||
#endif
|
||||
|
||||
#undef EXTERN
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_ARM_SRC_STM32H7_STM32_BBSRAM_H */
|
||||
@@ -0,0 +1,316 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32h7/stm32_pwr.c
|
||||
*
|
||||
* Copyright (C) 2011 Uros Platise. All rights reserved.
|
||||
* Copyright (C) 2013, 2015, 2017, 2019 Gregory Nutt. All rights reserved.
|
||||
* Authors: Uros Platise <uros.platise@isotel.eu>
|
||||
* Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david.sidrane@nscdg.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <nuttx/arch.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include <errno.h>
|
||||
|
||||
#include "up_arch.h"
|
||||
#include "stm32_pwr.h"
|
||||
|
||||
#if defined(CONFIG_STM32H7_PWR)
|
||||
|
||||
#define BREG_WAIT_USTIMEOUT 1000 /* uS to wait for regulator to come ready */
|
||||
|
||||
/************************************************************************************
|
||||
* Private Data
|
||||
************************************************************************************/
|
||||
|
||||
static uint16_t g_bkp_writable_counter = 0;
|
||||
|
||||
/************************************************************************************
|
||||
* Private Functions
|
||||
************************************************************************************/
|
||||
|
||||
static inline uint32_t stm32_pwr_getreg(uint32_t offset)
|
||||
{
|
||||
return getreg32(STM32_PWR_BASE + offset);
|
||||
}
|
||||
|
||||
static inline void stm32_pwr_putreg(uint32_t offset, uint32_t value)
|
||||
{
|
||||
putreg32(value, STM32_PWR_BASE + offset);
|
||||
}
|
||||
|
||||
static inline void stm32_pwr_modifyreg(uint32_t offset, uint32_t clearbits, uint32_t setbits)
|
||||
{
|
||||
modifyreg32(STM32_PWR_BASE + offset, clearbits, setbits);
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_pwr_initbkp
|
||||
*
|
||||
* Description:
|
||||
* Insures the referenced count access to the backup domain (RTC registers,
|
||||
* RTC backup data registers and backup SRAM is consistent with the HW state
|
||||
* without relying on a variable.
|
||||
*
|
||||
* NOTE: This function should only be called by SoC Start up code.
|
||||
*
|
||||
* Input Parameters:
|
||||
* writable - True: enable ability to write to backup domain registers
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
void stm32_pwr_initbkp(bool writable)
|
||||
{
|
||||
irqstate_t flags;
|
||||
uint32_t regval;
|
||||
|
||||
flags = enter_critical_section();
|
||||
|
||||
/* Make the HW not writable */
|
||||
|
||||
regval = stm32_pwr_getreg(STM32_PWR_CR1_OFFSET);
|
||||
regval &= ~PWR_CR1_DBP;
|
||||
stm32_pwr_putreg(STM32_PWR_CR1_OFFSET, regval);
|
||||
|
||||
/* Make the reference count agree */
|
||||
|
||||
g_bkp_writable_counter = 0;
|
||||
|
||||
leave_critical_section(flags);
|
||||
|
||||
stm32_pwr_enablebkp(writable);
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_pwr_enablebkp
|
||||
*
|
||||
* Description:
|
||||
* Enables access to the backup domain (RTC registers, RTC backup data registers
|
||||
* and backup SRAM).
|
||||
*
|
||||
* NOTE: Reference counting is used in order to supported nested calls to this
|
||||
* function. As a consequence, every call to stm32_pwr_enablebkp(true) must
|
||||
* be followed by a matching call to stm32_pwr_enablebkp(false).
|
||||
*
|
||||
* Input Parameters:
|
||||
* writable - True: enable ability to write to backup domain registers
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
void stm32_pwr_enablebkp(bool writable)
|
||||
{
|
||||
irqstate_t flags;
|
||||
uint32_t regval;
|
||||
bool waswritable;
|
||||
bool wait = false;
|
||||
|
||||
flags = enter_critical_section();
|
||||
|
||||
/* Get the current state of the STM32 PWR control register */
|
||||
|
||||
regval = stm32_pwr_getreg(STM32_PWR_CR1_OFFSET);
|
||||
waswritable = ((regval & PWR_CR1_DBP) != 0);
|
||||
|
||||
if (writable)
|
||||
{
|
||||
DEBUGASSERT(g_bkp_writable_counter < UINT16_MAX);
|
||||
g_bkp_writable_counter++;
|
||||
}
|
||||
else if (g_bkp_writable_counter > 0)
|
||||
{
|
||||
g_bkp_writable_counter--;
|
||||
}
|
||||
|
||||
/* Enable or disable the ability to write */
|
||||
|
||||
if (waswritable && g_bkp_writable_counter == 0)
|
||||
{
|
||||
/* Disable backup domain access */
|
||||
|
||||
regval &= ~PWR_CR1_DBP;
|
||||
stm32_pwr_putreg(STM32_PWR_CR1_OFFSET, regval);
|
||||
}
|
||||
else if (!waswritable && g_bkp_writable_counter > 0)
|
||||
{
|
||||
/* Enable backup domain access */
|
||||
|
||||
regval |= PWR_CR1_DBP;
|
||||
stm32_pwr_putreg(STM32_PWR_CR1_OFFSET, regval);
|
||||
|
||||
wait = true;
|
||||
}
|
||||
|
||||
leave_critical_section(flags);
|
||||
|
||||
if (wait)
|
||||
{
|
||||
/* Enable does not happen right away */
|
||||
|
||||
up_udelay(4000);
|
||||
}
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_pwr_setpvd
|
||||
*
|
||||
* Description:
|
||||
* Sets power voltage detector
|
||||
*
|
||||
* Input Parameters:
|
||||
* pls - PVD level
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
* Assumptions:
|
||||
* At present, this function is called only from initialization logic. If used
|
||||
* for any other purpose that protection to assure that its operation is atomic
|
||||
* will be required.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
void stm32_pwr_setpvd(uint32_t pls)
|
||||
{
|
||||
uint32_t regval;
|
||||
|
||||
/* Set PLS */
|
||||
|
||||
regval = stm32_pwr_getreg(STM32_PWR_CR1_OFFSET);
|
||||
regval &= ~PWR_CR1_PLS_MASK;
|
||||
regval |= (pls & PWR_CR1_PLS_MASK);
|
||||
|
||||
/* Write value to register */
|
||||
|
||||
stm32_pwr_putreg(STM32_PWR_CR1_OFFSET, regval);
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_pwr_enablepvd
|
||||
*
|
||||
* Description:
|
||||
* Enable the Programmable Voltage Detector
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
void stm32_pwr_enablepvd(void)
|
||||
{
|
||||
/* Enable PVD by setting the PVDE bit in PWR_CR register. */
|
||||
|
||||
stm32_pwr_modifyreg(STM32_PWR_CR1_OFFSET, 0, PWR_CR1_PVDE);
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_pwr_disablepvd
|
||||
*
|
||||
* Description:
|
||||
* Disable the Programmable Voltage Detector
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
void stm32_pwr_disablepvd(void)
|
||||
{
|
||||
/* Disable PVD by clearing the PVDE bit in PWR_CR register. */
|
||||
|
||||
stm32_pwr_modifyreg(STM32_PWR_CR1_OFFSET, PWR_CR1_PVDE, 0);
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_pwr_enablebreg
|
||||
*
|
||||
* Description:
|
||||
* Enables the Backup regulator, the Backup regulator (used to maintain backup
|
||||
* SRAM content in Standby and VBAT modes) is enabled. If BRE is reset, the backup
|
||||
* regulator is switched off. The backup SRAM can still be used but its content will
|
||||
* be lost in the Standby and VBAT modes. Once set, the application must wait that
|
||||
* the Backup Regulator Ready flag (BRR) is set to indicate that the data written
|
||||
* into the RAM will be maintained in the Standby and VBAT modes.
|
||||
*
|
||||
* This function need to be called after stm32_pwr_enablebkp(true) has ben called.
|
||||
*
|
||||
* Input Parameters:
|
||||
* regon - state to set it to
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
void stm32_pwr_enablebreg(bool regon)
|
||||
{
|
||||
|
||||
irqstate_t flags;
|
||||
uint32_t regval;
|
||||
uint32_t reg_wait = 0;
|
||||
|
||||
flags = enter_critical_section();
|
||||
|
||||
regval = stm32_pwr_getreg(STM32_PWR_CR2_OFFSET);
|
||||
|
||||
if (regon)
|
||||
{
|
||||
/* Request to turn on, if it was off we have wait */
|
||||
|
||||
reg_wait = BREG_WAIT_USTIMEOUT;
|
||||
regval |= PWR_CR2_BREN;
|
||||
}
|
||||
else
|
||||
{
|
||||
regval &= ~PWR_CR2_BREN;
|
||||
}
|
||||
|
||||
stm32_pwr_putreg(STM32_PWR_CR2_OFFSET, regval);
|
||||
|
||||
while (reg_wait-- &&
|
||||
(stm32_pwr_getreg(STM32_PWR_CR2_OFFSET) & PWR_CR2_BREN) == 0)
|
||||
{
|
||||
up_udelay(1);
|
||||
}
|
||||
|
||||
leave_critical_section(flags);
|
||||
}
|
||||
#endif /* CONFIG_STM32_PWR */
|
||||
Reference in New Issue
Block a user