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xtensa/esp32s3: Support ESP32-S3 PM standby and sleep.
1. pm configuration demonstrates the use of power management present on the ESP32-S3.
2. You can use the pmconfig command to test the power management, for details look at
``Documentation/platforms/xtensa/esp32s3/boards/esp32s3-devkit/index.rst``
Signed-off-by: chenwen@espressif.com <chenwen@espressif.com>
This commit is contained in:
chenwen@espressif.com
committed by
Xiang Xiao
Xiang Xiao
parent
f4e31a6568
commit
ea5583b112
@@ -325,6 +325,57 @@ To test it, just run the ``oneshot`` example::
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Waiting...
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Finished
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pm
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-------
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This config demonstrate the use of power management present on the ESP32-S3.
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You can use the pmconfig command to test the power management.
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Enables PM support. You can define standby mode and sleep mode delay time::
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$ make menuconfig
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-> Board Selection
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-> (15) PM_STANDBY delay (seconds)
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(0) PM_STANDBY delay (nanoseconds)
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(20) PM_SLEEP delay (seconds)
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(0) PM_SLEEP delay (nanoseconds)
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Before switching PM status, you need to query the current PM status::
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nsh> pmconfig
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Last state 0, Next state 0
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/proc/pm/state0:
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DOMAIN0 WAKE SLEEP TOTAL
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normal 0s 00% 0s 00% 0s 00%
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idle 0s 00% 0s 00% 0s 00%
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standby 0s 00% 0s 00% 0s 00%
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sleep 0s 00% 0s 00% 0s 00%
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/proc/pm/wakelock0:
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DOMAIN0 STATE COUNT TIME
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system normal 2 1s
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system idle 1 1s
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system standby 1 1s
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system sleep 1 1s
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System switch to the PM idle mode, you need to enter::
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nsh> pmconfig relax normal
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nsh> pmconfig relax normal
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System switch to the PM standby mode, you need to enter::
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nsh> pmconfig relax idle
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nsh> pmconfig relax normal
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nsh> pmconfig relax normal
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System switch to the PM sleep mode, you need to enter::
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nsh> pmconfig relax standby
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nsh> pmconfig relax idle
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nsh> pmconfig relax normal
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nsh> pmconfig relax normal
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Note: when normal mode COUNT is 0, it will switch to the next PM state where COUNT is not 0.
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psram_quad
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----------
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@@ -186,6 +186,13 @@ ifeq ($(CONFIG_ESP32S3_AES_ACCELERATOR),y)
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CHIP_CSRCS += esp32s3_aes.c
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endif
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ifeq ($(CONFIG_PM),y)
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ifneq ($(CONFIG_ARCH_CUSTOM_PMINIT),y)
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CHIP_CSRCS += esp32s3_pminitialize.c
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endif
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CHIP_CSRCS += esp32s3_pm.c
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endif
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#############################################################################
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# Espressif HAL for 3rd Party Platforms
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#############################################################################
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@@ -24,20 +24,141 @@
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#include <nuttx/config.h>
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#include <debug.h>
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#include <arch/board/board.h>
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#include <nuttx/arch.h>
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#include <nuttx/board.h>
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#include <nuttx/power/pm.h>
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#include "xtensa.h"
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#include "esp32s3_pm.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Values for the RTC Alarm to wake up from the PM_STANDBY mode
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* (which corresponds to ESP32-C3 stop mode). If this alarm expires,
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* the logic in this file will wakeup from PM_STANDBY mode and
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* transition to PM_SLEEP mode (ESP32-C3 standby mode).
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*/
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#ifdef CONFIG_PM
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#ifndef CONFIG_PM_ALARM_SEC
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# define CONFIG_PM_ALARM_SEC 15
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#endif
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#ifndef CONFIG_PM_ALARM_NSEC
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# define CONFIG_PM_ALARM_NSEC 0
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#endif
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#ifndef CONFIG_PM_SLEEP_WAKEUP_SEC
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# define CONFIG_PM_SLEEP_WAKEUP_SEC 20
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#endif
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#ifndef CONFIG_PM_SLEEP_WAKEUP_NSEC
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# define CONFIG_PM_SLEEP_WAKEUP_NSEC 0
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#endif
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#endif
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Name: up_idlepm
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*
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* Description:
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* Perform IDLE state power management.
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*
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****************************************************************************/
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#ifdef CONFIG_PM
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static void up_idlepm(void)
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{
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irqstate_t flags;
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static enum pm_state_e oldstate = PM_NORMAL;
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enum pm_state_e newstate;
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int ret;
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/* Decide, which power saving level can be obtained */
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newstate = pm_checkstate(PM_IDLE_DOMAIN);
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/* Check for state changes */
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if (newstate != oldstate)
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{
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flags = spin_lock_irqsave(NULL);
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/* Perform board-specific, state-dependent logic here */
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_info("newstate= %d oldstate=%d\n", newstate, oldstate);
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/* Then force the global state change */
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ret = pm_changestate(PM_IDLE_DOMAIN, newstate);
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if (ret < 0)
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{
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/* The new state change failed, revert to the preceding state */
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pm_changestate(PM_IDLE_DOMAIN, oldstate);
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}
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else
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{
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/* Save the new state */
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oldstate = newstate;
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}
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spin_unlock_irqrestore(NULL, flags);
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/* MCU-specific power management logic */
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switch (newstate)
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{
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case PM_NORMAL:
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break;
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case PM_IDLE:
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break;
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case PM_STANDBY:
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{
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/* Enter Force-sleep mode */
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esp32s3_pmstandby(CONFIG_PM_ALARM_SEC * 1000000 +
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CONFIG_PM_ALARM_NSEC / 1000);
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}
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break;
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case PM_SLEEP:
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{
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/* Enter Deep-sleep mode */
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esp32s3_pmsleep(CONFIG_PM_SLEEP_WAKEUP_SEC * 1000000 +
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CONFIG_PM_SLEEP_WAKEUP_NSEC / 1000);
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}
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break;
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default:
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break;
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}
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}
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else
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{
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#ifdef CONFIG_WATCHDOG
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/* Announce the power management state change to feed watchdog */
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pm_changestate(PM_IDLE_DOMAIN, PM_NORMAL);
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#endif
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}
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}
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#else
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# define up_idlepm()
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#endif
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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@@ -86,6 +207,10 @@ void up_idle(void)
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# if XCHAL_HAVE_INTERRUPTS
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__asm__ __volatile__ ("waiti 0");
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# endif
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/* Perform IDLE mode power management */
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up_idlepm();
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#endif /* CONFIG_SUPPRESS_INTERRUPTS || CONFIG_SUPPRESS_TIMER_INTS */
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#ifdef CONFIG_ESP32S3_SPEED_UP_ISR
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,302 @@
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/****************************************************************************
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* arch/xtensa/src/esp32s3/esp32s3_pm.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#ifndef __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_PM_H
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#define __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_PM_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <stdint.h>
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#include <stdbool.h>
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#ifndef __ASSEMBLY__
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#undef EXTERN
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#if defined(__cplusplus)
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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#ifdef CONFIG_PM
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/****************************************************************************
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* Public Types
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****************************************************************************/
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/* Callback function type for peripherals to
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* know light sleep wakeup overhead.
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*/
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typedef void (*inform_out_sleep_overhead_cb_t)(uint32_t);
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/* Callback function type for peripherals to skip light sleep. */
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typedef bool (*skip_light_sleep_cb_t)(void);
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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/****************************************************************************
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* Name: esp32s3_sleep_enable_timer_wakeup
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*
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* Description:
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* Configure wake-up interval
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*
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* Input Parameters:
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* time_in_us - Configure wake-up time interval
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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void esp32s3_sleep_enable_timer_wakeup(uint64_t time_in_us);
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/****************************************************************************
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* Name: esp32s3_light_sleep_start
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*
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* Description:
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* Enter light sleep mode
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*
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* Input Parameters:
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* sleep_time - Actual sleep time
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*
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* Returned Value:
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* 0 is returned on success or a negated errno value is returned
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*
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****************************************************************************/
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int esp32s3_light_sleep_start(uint64_t *sleep_time);
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/****************************************************************************
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* Name: esp32s3_pmstandby
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*
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* Description:
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* Enter force sleep time interval.
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*
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* Input Parameters:
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* time_in_us - Force sleep time interval
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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void esp32s3_pmstandby(uint64_t time_in_us);
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/****************************************************************************
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* Name: esp32s3_deep_sleep_start
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*
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* Description:
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* Enter deep sleep mode
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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void esp32s3_deep_sleep_start(void);
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/****************************************************************************
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* Name: esp32s3_pmsleep
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*
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* Description:
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* Enter deep sleep.
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*
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* Input Parameters:
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* time_in_us - Deep sleep time interval
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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void esp32s3_pmsleep(uint64_t time_in_us);
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/****************************************************************************
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* Name: esp32s3_pm_lockacquire
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*
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* Description:
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* Take a power management lock
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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void esp32s3_pm_lockacquire(void);
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/****************************************************************************
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* Name: esp32s3_pm_lockrelease
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*
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* Description:
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* Release the lock taken using esp32s3_pm_lockacquire.
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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void esp32s3_pm_lockrelease(void);
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/****************************************************************************
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* Name: esp32s3_pm_lockstatus
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*
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* Description:
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* Return power management lock status.
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* Current pm_wakelock count
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*
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****************************************************************************/
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uint32_t esp32s3_pm_lockstatus(void);
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/****************************************************************************
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* Name: esp32s3_sleep_enable_wifi_wakeup
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*
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* Description:
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* Configure Wi-Fi wake-up source
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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void esp32s3_sleep_enable_wifi_wakeup(void);
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/****************************************************************************
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* Name: esp32s3_should_skip_light_sleep
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*
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* Description:
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* Indicates if light sleep shoule be skipped.
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* True is returned on success. Otherwise false.
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*
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****************************************************************************/
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bool esp32s3_should_skip_light_sleep(void);
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/****************************************************************************
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* Name: esp32s3_pm_register_inform_out_sleep_overhead_callback
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*
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* Description:
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* Register informing peripherals of light sleep wakeup overhead time
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* callback function.
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*
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* Input Parameters:
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* cb - Callback function
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*
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* Returned Value:
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* Zero (OK) is returned on success. Otherwise -1 (ERROR).
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*
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****************************************************************************/
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int esp32s3_pm_register_inform_out_sleep_overhead_callback(
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inform_out_sleep_overhead_cb_t cb);
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/****************************************************************************
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* Name: esp32s3_pm_unregister_inform_out_sleep_overhead_callback
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*
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* Description:
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* Unregister informing peripherals of light sleep wakeup overhead time
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* callback function.
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*
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* Input Parameters:
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* cb - Callback function
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*
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* Returned Value:
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* Zero (OK) is returned on success. Otherwise -1 (ERROR).
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*
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****************************************************************************/
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int esp32s3_pm_unregister_inform_out_sleep_overhead_callback(
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inform_out_sleep_overhead_cb_t cb);
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/****************************************************************************
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* Name: esp32s3_pm_register_skip_sleep_callback
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*
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* Description:
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* Unregister callback function of skipping light sleep.
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*
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* Input Parameters:
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* cb - Callback function
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*
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* Returned Value:
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* Zero (OK) is returned on success. Otherwise -1 (ERROR).
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*
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****************************************************************************/
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int esp32s3_pm_register_skip_sleep_callback(skip_light_sleep_cb_t cb);
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/****************************************************************************
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* Name: esp32s3_pm_unregister_skip_sleep_callback
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*
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* Description:
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* Register callback function of skipping light sleep.
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*
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* Input Parameters:
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* cb - Callback function
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*
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* Returned Value:
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* Zero (OK) is returned on success. Otherwise -1 (ERROR).
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*
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****************************************************************************/
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int esp32s3_pm_unregister_skip_sleep_callback(skip_light_sleep_cb_t cb);
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#endif /* CONFIG_PM */
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#ifdef __cplusplus
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}
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#endif
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#undef EXTERN
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#endif /* __ASSEMBLY__ */
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#endif /* __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_PM_H */
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@@ -0,0 +1,49 @@
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/****************************************************************************
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* arch/xtensa/src/esp32s3/esp32s3_pminitialize.c
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
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*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
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*
|
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****************************************************************************/
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/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <nuttx/power/pm.h>
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: xtensa_pminitialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize the power management subsystem.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void xtensa_pminitialize(void)
|
||||
{
|
||||
/* Initialize the NuttX power management subsystem proper */
|
||||
|
||||
pm_initialize();
|
||||
}
|
||||
|
||||
#endif /* CONFIG_PM */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -68,6 +68,21 @@ extern "C"
|
||||
|
||||
#define RTC_CLK_CAL_FRACT 19
|
||||
|
||||
/* Cycles for RTC Timer clock source (internal oscillator) calibrate */
|
||||
|
||||
#define RTC_CLK_SRC_CAL_CYCLES (10)
|
||||
|
||||
#define RTC_CNTL_XTL_BUF_WAIT_SLP_US (250)
|
||||
#define RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES (1)
|
||||
#define RTC_CNTL_CK8M_WAIT_SLP_CYCLES (4)
|
||||
#define RTC_CNTL_WAKEUP_DELAY_CYCLES (4)
|
||||
|
||||
#define RTC_CNTL_CK8M_DFREQ_DEFAULT 100
|
||||
#define RTC_CNTL_SCK_DCAP_DEFAULT 255
|
||||
|
||||
#define RTC_CNTL_ULPCP_TOUCH_START_WAIT_IN_SLEEP (0xFF)
|
||||
#define RTC_CNTL_ULPCP_TOUCH_START_WAIT_DEFAULT (0x10)
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
@@ -350,6 +365,23 @@ void esp32s3_rtc_init(void);
|
||||
|
||||
uint64_t esp32s3_rtc_time_get(void);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: esp32s3_rtc_sleep_low_init
|
||||
*
|
||||
* Description:
|
||||
* Low level initialize for rtc state machine waiting
|
||||
* cycles after waking up.
|
||||
*
|
||||
* Input Parameters:
|
||||
* slowclk_period - Re-calibrated slow clock period
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void esp32s3_rtc_sleep_low_init(uint32_t slowclk_period);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: esp32s3_rtc_time_us_to_slowclk
|
||||
*
|
||||
|
||||
@@ -5893,4 +5893,15 @@
|
||||
|
||||
#define RTC_SLEEP_PD_XTAL BIT(11)
|
||||
|
||||
/* These flags are not power domains, but will affect some sleep parameters */
|
||||
|
||||
#define RTC_SLEEP_DIG_USE_8M BIT(16)
|
||||
#define RTC_SLEEP_USE_ADC_TESEN_MONITOR BIT(17)
|
||||
|
||||
/* Avoid using ultra low power in deep sleep, in which RTCIO cannot
|
||||
* be used as input, and RTCMEM can't work under high temperature
|
||||
*/
|
||||
|
||||
#define RTC_SLEEP_NO_ULTRA_LOW BIT(18)
|
||||
|
||||
#endif /* __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_RTCCNTL_H */
|
||||
|
||||
@@ -860,7 +860,7 @@
|
||||
* Rx Filter configuration
|
||||
*/
|
||||
|
||||
#define UART_RX_FILT_REG (DR_REG_UART_BASE + 0x18)
|
||||
#define UART_RX_FILT_REG(i) (REG_UART_BASE(i) + 0x18)
|
||||
|
||||
/* UART_GLITCH_FILT_EN : R/W; bitpos: [8]; default: 0;
|
||||
* Set this bit to enable Rx signal filter.
|
||||
@@ -1280,7 +1280,7 @@
|
||||
* Autobaud minimum low pulse duration register
|
||||
*/
|
||||
|
||||
#define UART_LOWPULSE_REG (DR_REG_UART_BASE + 0x28)
|
||||
#define UART_LOWPULSE_REG(i) (REG_UART_BASE(i) + 0x28)
|
||||
|
||||
/* UART_LOWPULSE_MIN_CNT : RO; bitpos: [11:0]; default: 4095;
|
||||
* This register stores the value of the minimum duration time of the low
|
||||
@@ -1296,7 +1296,7 @@
|
||||
* Autobaud minimum high pulse duration register
|
||||
*/
|
||||
|
||||
#define UART_HIGHPULSE_REG (DR_REG_UART_BASE + 0x2c)
|
||||
#define UART_HIGHPULSE_REG(i) (REG_UART_BASE(i) + 0x2c)
|
||||
|
||||
/* UART_HIGHPULSE_MIN_CNT : RO; bitpos: [11:0]; default: 4095;
|
||||
* This register stores the value of the maximum duration time for the high
|
||||
@@ -1312,7 +1312,7 @@
|
||||
* Autobaud edge change count register
|
||||
*/
|
||||
|
||||
#define UART_RXD_CNT_REG (DR_REG_UART_BASE + 0x30)
|
||||
#define UART_RXD_CNT_REG(i) (REG_UART_BASE(i) + 0x30)
|
||||
|
||||
/* UART_RXD_EDGE_CNT : RO; bitpos: [9:0]; default: 0;
|
||||
* This register stores the count of rxd edge change. It is used in baud
|
||||
@@ -1328,7 +1328,7 @@
|
||||
* Software flow-control configuration
|
||||
*/
|
||||
|
||||
#define UART_FLOW_CONF_REG (DR_REG_UART_BASE + 0x34)
|
||||
#define UART_FLOW_CONF_REG(i) (REG_UART_BASE(i) + 0x34)
|
||||
|
||||
/* UART_SEND_XOFF : R/W/SS/SC; bitpos: [5]; default: 0;
|
||||
* Set this bit to send Xoff char. It is cleared by hardware automatically.
|
||||
@@ -1389,7 +1389,7 @@
|
||||
* Sleep-mode configuration
|
||||
*/
|
||||
|
||||
#define UART_SLEEP_CONF_REG (DR_REG_UART_BASE + 0x38)
|
||||
#define UART_SLEEP_CONF_REG(i) (REG_UART_BASE(i) + 0x38)
|
||||
|
||||
/* UART_ACTIVE_THRESHOLD : R/W; bitpos: [9:0]; default: 240;
|
||||
* The uart is activated from light sleeping mode when the input rxd edge
|
||||
@@ -1405,7 +1405,7 @@
|
||||
* Software flow-control character configuration
|
||||
*/
|
||||
|
||||
#define UART_SWFC_CONF0_REG (DR_REG_UART_BASE + 0x3c)
|
||||
#define UART_SWFC_CONF0_REG(i) (REG_UART_BASE(i) + 0x3c)
|
||||
|
||||
/* UART_XOFF_CHAR : R/W; bitpos: [17:10]; default: 19;
|
||||
* This register stores the Xoff flow control char.
|
||||
@@ -1430,7 +1430,7 @@
|
||||
* Software flow-control character configuration
|
||||
*/
|
||||
|
||||
#define UART_SWFC_CONF1_REG (DR_REG_UART_BASE + 0x40)
|
||||
#define UART_SWFC_CONF1_REG(i) (REG_UART_BASE(i) + 0x40)
|
||||
|
||||
/* UART_XON_CHAR : R/W; bitpos: [17:10]; default: 17;
|
||||
* This register stores the Xon flow control char.
|
||||
@@ -1455,7 +1455,7 @@
|
||||
* Tx Break character configuration
|
||||
*/
|
||||
|
||||
#define UART_TXBRK_CONF_REG (DR_REG_UART_BASE + 0x44)
|
||||
#define UART_TXBRK_CONF_REG(i) (REG_UART_BASE(i) + 0x44)
|
||||
|
||||
/* UART_TX_BRK_NUM : R/W; bitpos: [7:0]; default: 10;
|
||||
* This register is used to configure the number of 0 to be sent after the
|
||||
@@ -1567,7 +1567,7 @@
|
||||
* Pre-sequence timing configuration
|
||||
*/
|
||||
|
||||
#define UART_AT_CMD_PRECNT_REG (DR_REG_UART_BASE + 0x50)
|
||||
#define UART_AT_CMD_PRECNT_REG(i) (REG_UART_BASE(i) + 0x50)
|
||||
|
||||
/* UART_PRE_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305;
|
||||
* This register is used to configure the idle duration time before the
|
||||
@@ -1583,7 +1583,7 @@
|
||||
* Post-sequence timing configuration
|
||||
*/
|
||||
|
||||
#define UART_AT_CMD_POSTCNT_REG (DR_REG_UART_BASE + 0x54)
|
||||
#define UART_AT_CMD_POSTCNT_REG(i) (REG_UART_BASE(i) + 0x54)
|
||||
|
||||
/* UART_POST_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305;
|
||||
* This register is used to configure the duration time between the last
|
||||
@@ -1599,7 +1599,7 @@
|
||||
* Timeout configuration
|
||||
*/
|
||||
|
||||
#define UART_AT_CMD_GAPTOUT_REG (DR_REG_UART_BASE + 0x58)
|
||||
#define UART_AT_CMD_GAPTOUT_REG(i) (REG_UART_BASE(i) + 0x58)
|
||||
|
||||
/* UART_RX_GAP_TOUT : R/W; bitpos: [15:0]; default: 11;
|
||||
* This register is used to configure the duration time between the at_cmd
|
||||
@@ -1615,7 +1615,7 @@
|
||||
* AT escape sequence detection configuration
|
||||
*/
|
||||
|
||||
#define UART_AT_CMD_CHAR_REG (DR_REG_UART_BASE + 0x5c)
|
||||
#define UART_AT_CMD_CHAR_REG(i) (REG_UART_BASE(i) + 0x5c)
|
||||
|
||||
/* UART_CHAR_NUM : R/W; bitpos: [15:8]; default: 3;
|
||||
* This register is used to configure the num of continuous at_cmd chars
|
||||
@@ -1705,7 +1705,7 @@
|
||||
* Tx-FIFO write and read offset address.
|
||||
*/
|
||||
|
||||
#define UART_MEM_TX_STATUS_REG (DR_REG_UART_BASE + 0x64)
|
||||
#define UART_MEM_TX_STATUS_REG(i) (REG_UART_BASE(i) + 0x64)
|
||||
|
||||
/* UART_TX_RADDR : RO; bitpos: [20:11]; default: 0;
|
||||
* This register stores the offset address in Tx-FIFO when Tx-FSM reads data
|
||||
@@ -1731,7 +1731,7 @@
|
||||
* Rx-FIFO write and read offset address.
|
||||
*/
|
||||
|
||||
#define UART_MEM_RX_STATUS_REG (DR_REG_UART_BASE + 0x68)
|
||||
#define UART_MEM_RX_STATUS_REG(i) (REG_UART_BASE(i) + 0x68)
|
||||
|
||||
/* UART_RX_WADDR : RO; bitpos: [20:11]; default: 512;
|
||||
* This register stores the offset address in Rx-FIFO when Rx-FIFO_Ctrl
|
||||
@@ -1758,7 +1758,7 @@
|
||||
* UART transmit and receive status.
|
||||
*/
|
||||
|
||||
#define UART_FSM_STATUS_REG (DR_REG_UART_BASE + 0x6c)
|
||||
#define UART_FSM_STATUS_REG(i) (REG_UART_BASE(i) + 0x6c)
|
||||
|
||||
/* UART_ST_UTX_OUT : RO; bitpos: [7:4]; default: 0;
|
||||
* This is the status register of transmitter.
|
||||
@@ -1782,7 +1782,7 @@
|
||||
* Autobaud high pulse register
|
||||
*/
|
||||
|
||||
#define UART_POSPULSE_REG (DR_REG_UART_BASE + 0x70)
|
||||
#define UART_POSPULSE_REG(i) (REG_UART_BASE(i) + 0x70)
|
||||
|
||||
/* UART_POSEDGE_MIN_CNT : RO; bitpos: [11:0]; default: 4095;
|
||||
* This register stores the minimal input clock count between two positive
|
||||
@@ -1798,7 +1798,7 @@
|
||||
* Autobaud low pulse register
|
||||
*/
|
||||
|
||||
#define UART_NEGPULSE_REG (DR_REG_UART_BASE + 0x74)
|
||||
#define UART_NEGPULSE_REG(i) (REG_UART_BASE(i) + 0x74)
|
||||
|
||||
/* UART_NEGEDGE_MIN_CNT : RO; bitpos: [11:0]; default: 4095;
|
||||
* This register stores the minimal input clock count between two negative
|
||||
@@ -1910,7 +1910,7 @@
|
||||
* UART Version register
|
||||
*/
|
||||
|
||||
#define UART_DATE_REG (DR_REG_UART_BASE + 0x7c)
|
||||
#define UART_DATE_REG(i) (REG_UART_BASE(i) + 0x7c)
|
||||
|
||||
/* UART_DATE : R/W; bitpos: [31:0]; default: 33587824;
|
||||
* This is the version register.
|
||||
@@ -1925,7 +1925,7 @@
|
||||
* UART ID register
|
||||
*/
|
||||
|
||||
#define UART_ID_REG (DR_REG_UART_BASE + 0x80)
|
||||
#define UART_ID_REG(i) (REG_UART_BASE(i) + 0x80)
|
||||
|
||||
/* UART_REG_UPDATE : R/W/SC; bitpos: [31]; default: 0;
|
||||
* Software write 1 would synchronize registers into UART Core clock domain
|
||||
|
||||
@@ -60,4 +60,36 @@ config ESP32S3_SPIFLASH_LITTLEFS
|
||||
|
||||
endchoice # ESP32S3_SPIFLASH_FS
|
||||
|
||||
if PM
|
||||
|
||||
config PM_ALARM_SEC
|
||||
int "PM_STANDBY delay (seconds)"
|
||||
default 15
|
||||
depends on PM
|
||||
---help---
|
||||
Number of seconds to wait in PM_STANDBY before going to PM_STANDBY mode.
|
||||
|
||||
config PM_ALARM_NSEC
|
||||
int "PM_STANDBY delay (nanoseconds)"
|
||||
default 0
|
||||
depends on PM
|
||||
---help---
|
||||
Number of additional nanoseconds to wait in PM_STANDBY before going to PM_STANDBY mode.
|
||||
|
||||
config PM_SLEEP_WAKEUP_SEC
|
||||
int "PM_SLEEP delay (seconds)"
|
||||
default 20
|
||||
depends on PM
|
||||
---help---
|
||||
Number of seconds to wait in PM_SLEEP.
|
||||
|
||||
config PM_SLEEP_WAKEUP_NSEC
|
||||
int "PM_SLEEP delay (nanoseconds)"
|
||||
default 0
|
||||
depends on PM
|
||||
---help---
|
||||
Number of additional nanoseconds to wait in PM_SLEEP.
|
||||
|
||||
endif # PM
|
||||
|
||||
endif # ARCH_BOARD_ESP32S3_DEVKIT
|
||||
|
||||
@@ -0,0 +1,52 @@
|
||||
#
|
||||
# This file is autogenerated: PLEASE DO NOT EDIT IT.
|
||||
#
|
||||
# You can use "make menuconfig" to make any modifications to the installed .config file.
|
||||
# You can then do "make savedefconfig" to generate a new defconfig file that includes your
|
||||
# modifications.
|
||||
#
|
||||
# CONFIG_ARCH_LEDS is not set
|
||||
# CONFIG_NSH_ARGCAT is not set
|
||||
# CONFIG_NSH_CMDOPT_HEXDUMP is not set
|
||||
CONFIG_ARCH="xtensa"
|
||||
CONFIG_ARCH_BOARD="esp32s3-devkit"
|
||||
CONFIG_ARCH_BOARD_COMMON=y
|
||||
CONFIG_ARCH_BOARD_ESP32S3_DEVKIT=y
|
||||
CONFIG_ARCH_CHIP="esp32s3"
|
||||
CONFIG_ARCH_CHIP_ESP32S3=y
|
||||
CONFIG_ARCH_CHIP_ESP32S3WROOM1=y
|
||||
CONFIG_ARCH_INTERRUPTSTACK=2048
|
||||
CONFIG_ARCH_STACKDUMP=y
|
||||
CONFIG_ARCH_XTENSA=y
|
||||
CONFIG_BOARD_LOOPSPERMSEC=16717
|
||||
CONFIG_BUILTIN=y
|
||||
CONFIG_DEBUG_FULLOPT=y
|
||||
CONFIG_DEBUG_SYMBOLS=y
|
||||
CONFIG_ESP32S3_UART0=y
|
||||
CONFIG_FS_PROCFS=y
|
||||
CONFIG_FS_PROCFS_REGISTER=y
|
||||
CONFIG_HAVE_CXX=y
|
||||
CONFIG_HAVE_CXXINITIALIZE=y
|
||||
CONFIG_IDLETHREAD_STACKSIZE=3072
|
||||
CONFIG_INIT_ENTRYPOINT="nsh_main"
|
||||
CONFIG_INTELHEX_BINARY=y
|
||||
CONFIG_NSH_ARCHINIT=y
|
||||
CONFIG_NSH_BUILTIN_APPS=y
|
||||
CONFIG_NSH_FILEIOSIZE=512
|
||||
CONFIG_NSH_LINELEN=64
|
||||
CONFIG_NSH_READLINE=y
|
||||
CONFIG_PM=y
|
||||
CONFIG_PM_GOVERNOR_EXPLICIT_RELAX=-1
|
||||
CONFIG_PM_GOVERNOR_GREEDY=y
|
||||
CONFIG_PM_PROCFS=y
|
||||
CONFIG_PREALLOC_TIMERS=4
|
||||
CONFIG_RAM_SIZE=114688
|
||||
CONFIG_RAM_START=0x20000000
|
||||
CONFIG_RR_INTERVAL=200
|
||||
CONFIG_SCHED_WAITPID=y
|
||||
CONFIG_START_DAY=6
|
||||
CONFIG_START_MONTH=12
|
||||
CONFIG_START_YEAR=2011
|
||||
CONFIG_SYSLOG_BUFFER=y
|
||||
CONFIG_SYSTEM_NSH=y
|
||||
CONFIG_UART0_SERIAL_CONSOLE=y
|
||||
Reference in New Issue
Block a user