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arm64: fix tickless mode in SMP

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Signed-off-by: hujun5 <hujun5@xiaomi.com>
This commit is contained in:
hujun5
2024-10-01 12:10:06 +08:00
committed by Xiang Xiao
parent 060ac93f82
commit ea29217442
1 changed files with 18 additions and 9 deletions
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arch/arm64/src/common/arm64_arch_timer.c
+18 -9
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@@ -70,6 +70,8 @@ struct arm64_oneshot_lowerhalf_s
void *arg; /* Argument that is passed to the handler */
uint64_t cycle_per_tick; /* cycle per tick */
oneshot_callback_t callback; /* Internal handler that receives callback */
bool running; /* True: timer is running */
bool init[CONFIG_SMP_NCPUS]; /* True: timer is init */
};
/****************************************************************************
@@ -155,7 +157,7 @@ static int arm64_arch_timer_compare_isr(int irq, void *regs, void *arg)
arm64_arch_timer_set_irq_mask(true);
if (priv->callback)
if (priv->callback && priv->running)
{
/* Then perform the callback */
@@ -226,6 +228,7 @@ static int arm64_tick_cancel(struct oneshot_lowerhalf_s *lower,
/* Disable int */
priv->running = false;
arm64_arch_timer_set_irq_mask(true);
return OK;
@@ -266,6 +269,20 @@ static int arm64_tick_start(struct oneshot_lowerhalf_s *lower,
priv->callback = callback;
priv->arg = arg;
if (!priv->init[this_cpu()])
{
/* Enable int */
up_enable_irq(ARM_ARCH_TIMER_IRQ);
/* Start timer */
arm64_arch_timer_enable(true);
priv->init[this_cpu()] = true;
}
priv->running = true;
next_cycle =
arm64_arch_timer_count() / priv->cycle_per_tick * priv->cycle_per_tick +
ticks * priv->cycle_per_tick;
@@ -365,14 +382,6 @@ struct oneshot_lowerhalf_s *arm64_oneshot_initialize(void)
irq_attach(ARM_ARCH_TIMER_IRQ,
arm64_arch_timer_compare_isr, priv);
/* Enable int */
up_enable_irq(ARM_ARCH_TIMER_IRQ);
/* Start timer */
arm64_arch_timer_enable(true);
tmrinfo("oneshot_initialize ok %p \n", &priv->lh);
return &priv->lh;