mirror of
https://github.com/apache/nuttx.git
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nrf52: add ADC support
This commit is contained in:
raiden00pl
committed by
Alan Carvalho de Assis
Alan Carvalho de Assis
parent
a2b00fd348
commit
e7f3028aa6
@@ -535,3 +535,61 @@ config NRF52_PWM3_CHANNEL
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endif # !NRF52_PWM_MULTICHAN
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endmenu # PWM configuration
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menu "SAADC Configuration"
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if NRF52_SAADC
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choice
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prompt "SAADC trigger selection"
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default NRF52_SAADC_TASK
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---help---
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Choose mode for sample rate control
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config NRF52_SAADC_TASK
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bool "SAADC Task trigger"
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config NRF52_SAADC_TIMER
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bool "SAADC Timer trigger"
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endchoice # SAADC trigger selection
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if NRF52_SAADC_TIMER
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config NRF52_SAADC_TIMER_CC
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int "SAADC Timer CC"
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default 0
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range 80 2047
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endif #NRF52_SAADC_TIMER
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config NRF52_SAADC_OVERSAMPLE
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int "SAADC oversample"
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default 0
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range 0 8
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---help---
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SAADC oversample control
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config NRF52_SAADC_RESOLUTION
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int "SAADC resolution"
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default 0
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range 0 3
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---help---
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SAADC resolution 0 - 8 bits, 1 - 10 bits, 2 - 12 bits, 3 - 14 bits
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config NRF52_SAADC_CHANNELS
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int "SAADC channels"
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default 8
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range 0 8
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---help---
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SAADC channels
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config NRF52_SAADC_LIMITS
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bool "SAADC limits enable"
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default n
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---help---
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SAADC limist enable
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endif # NRF52_SAADC
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endmenu # SAADC Configuration
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@@ -151,3 +151,7 @@ endif
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ifeq ($(CONFIG_NRF52_PWM),y)
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CHIP_CSRCS += nrf52_pwm.c
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endif
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ifeq ($(CONFIG_NRF52_SAADC),y)
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CHIP_CSRCS += nrf52_adc.c
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endif
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@@ -1,4 +1,4 @@
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/****************************************************************************
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/***************************************************************************
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* arch/arm/src/nrf52/hardware/nrf52_saadc.h
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*
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* Copyright (C) 2019 Gregory Nutt. All rights reserved.
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@@ -43,50 +43,50 @@
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#include <nuttx/config.h>
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#include "hardware/nrf52_memorymap.h"
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/****************************************************************************
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/***************************************************************************
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* Pre-processor Definitions
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***************************************************************************/
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/* Register offsets for SAADC **********************************************/
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#define NRF52_SAADC_TASKS_START_OFFSET 0x0000 /* Start the SAADCM */
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#define NRF52_SAADC_TASKS_SAMPLE_OFFSET 0x0004 /* Takes one SAADC sample */
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#define NRF52_SAADC_TASKS_STOP_OFFSET 0x0008 /* Stop the SAADC */
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#define NRF52_SAADC_TASKS_CALOFFSET_OFFSET 0x000c /* Starts offset auto-calibration */
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#define NRF52_SAADC_EVENTS_STARTED_OFFSET 0x0100 /* The SAADC has started */
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#define NRF52_SAADC_EVENTS_END_OFFSET 0x0104 /* The SAADC has filled up the result buffer */
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#define NRF52_SAADC_EVENTS_DONE_OFFSET 0x0108 /* A conversio ntask has been completed */
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#define NRF52_SAADC_EVENTS_RESDONE_OFFSET 0x010c /* Result ready for transfer to RAM */
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#define NRF52_SAADC_EVENTS_CALDONE_OFFSET 0x0110 /* Calibration is complete */
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#define NRF52_SAADC_EVENTS_STOPPED_OFFSET 0x0110 /* The SAADC has stopped */
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#define NRF52_SAADC_EVENTS_CHLIMH_OFFSET(x) (0x118 + (x + 0x8)) /* Limit high event for channel x */
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#define NRF52_SAADC_EVENTS_CHLIML_OFFSET(x) (0x11c + (x + 0x8)) /* Limit low event for channel x */
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#define NRF52_SAADC_INTEN_OFFSET 0x0300 /* Enable or disable interrupt */
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#define NRF52_SAADC_INTENSET_OFFSET 0x0304 /* Enable interrupt */
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#define NRF52_SAADC_INTENCLR_OFFSET 0x0308 /* Disable interrupt */
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#define NRF52_SAADC_STATUS_OFFSET 0x0400 /* Status */
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#define NRF52_SAADC_ENABLE_OFFSET 0x0500 /* Enable or disable SAADC */
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#define NRF52_SAADC_CHPSELP_OFFSET(x) (0x510 + (x + 0x10)) /* Input positive pin for CH[x] */
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#define NRF52_SAADC_CHPSELN_OFFSET(x) (0x514 + (x + 0x10)) /* Input negative pin for CH[x] */
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#define NRF52_SAADC_CHCONFIG_OFFSET(x) (0x518 + (x + 0x10)) /* Input configuration for CH[x] */
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#define NRF52_SAADC_CHLIMIT_OFFSET(x) (0x51c + (x + 0x10)) /* High/low limits for event monitoring of a CH[x] */
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#define NRF52_SAADC_RESOLUTION_OFFSET 0x05f0 /* Resolution configuration */
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#define NRF52_SAADC_OVERSAMPLE_OFFSET 0x05f4 /* Oversampling configuration */
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#define NRF52_SAADC_SAMPLERATE_OFFSET 0x05f8 /* Controls normal or continuous sample rate */
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#define NRF52_SAADC_PTR_OFFSET 0x062c /* Data pointer */
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#define NRF52_SAADC_MAXCNT_OFFSET 0x0630 /* Maximum number of 16-bit samples */
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#define NRF52_SAADC_AMOUNT_OFFSET 0x0634 /* Number of 16-bit samples written to buffer */
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#define NRF52_SAADC_TASKS_START_OFFSET 0x0000 /* Start the SAADCM */
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#define NRF52_SAADC_TASKS_SAMPLE_OFFSET 0x0004 /* Takes one SAADC sample */
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#define NRF52_SAADC_TASKS_STOP_OFFSET 0x0008 /* Stop the SAADC */
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#define NRF52_SAADC_TASKS_CALOFFSET_OFFSET 0x000c /* Starts offset auto-calibration */
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#define NRF52_SAADC_EVENTS_STARTED_OFFSET 0x0100 /* The SAADC has started */
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#define NRF52_SAADC_EVENTS_END_OFFSET 0x0104 /* The SAADC has filled up the result buffer */
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#define NRF52_SAADC_EVENTS_DONE_OFFSET 0x0108 /* A conversion task has been completed */
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#define NRF52_SAADC_EVENTS_RESDONE_OFFSET 0x010c /* Result ready for transfer to RAM */
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#define NRF52_SAADC_EVENTS_CALDONE_OFFSET 0x0110 /* Calibration is complete */
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#define NRF52_SAADC_EVENTS_STOPPED_OFFSET 0x0110 /* The SAADC has stopped */
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#define NRF52_SAADC_EVENTS_CHLIMH_OFFSET(x) (0x118 + ((x) * 0x8)) /* Limit high event for channel x */
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#define NRF52_SAADC_EVENTS_CHLIML_OFFSET(x) (0x11c + ((x) * 0x8)) /* Limit low event for channel x */
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#define NRF52_SAADC_INTEN_OFFSET 0x0300 /* Enable or disable interrupt */
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#define NRF52_SAADC_INTENSET_OFFSET 0x0304 /* Enable interrupt */
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#define NRF52_SAADC_INTENCLR_OFFSET 0x0308 /* Disable interrupt */
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#define NRF52_SAADC_STATUS_OFFSET 0x0400 /* Status */
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#define NRF52_SAADC_ENABLE_OFFSET 0x0500 /* Enable or disable SAADC */
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#define NRF52_SAADC_CHPSELP_OFFSET(x) (0x510 + ((x) * 0x10)) /* Input positive pin for CH[x] */
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#define NRF52_SAADC_CHPSELN_OFFSET(x) (0x514 + ((x) * 0x10)) /* Input negative pin for CH[x] */
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#define NRF52_SAADC_CHCONFIG_OFFSET(x) (0x518 + ((x) * 0x10)) /* Input configuration for CH[x] */
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#define NRF52_SAADC_CHLIMIT_OFFSET(x) (0x51c + ((x) * 0x10)) /* High/low limits for event monitoring of a CH[x] */
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#define NRF52_SAADC_RESOLUTION_OFFSET 0x05f0 /* Resolution configuration */
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#define NRF52_SAADC_OVERSAMPLE_OFFSET 0x05f4 /* Oversampling configuration */
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#define NRF52_SAADC_SAMPLERATE_OFFSET 0x05f8 /* Controls normal or continuous sample rate */
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#define NRF52_SAADC_PTR_OFFSET 0x062c /* Data pointer */
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#define NRF52_SAADC_MAXCNT_OFFSET 0x0630 /* Maximum number of 16-bit samples */
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#define NRF52_SAADC_AMOUNT_OFFSET 0x0634 /* Number of 16-bit samples written to buffer */
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/* Register Bitfield Definitions for SAADC *********************************/
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/* INTEN/INTENSET/INTENCLR Register */
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#define SAADC_INT_STARTED (1 << 0) /* Bit 0: Interrupt for event STARTED */
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#define SAADC_INT_END (1 << 1) /* Bit 1: Interrupt for event END */
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#define SAADC_INT_DONE (1 << 2) /* Bit 2: Interrupt for event DONE */
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#define SAADC_INT_RESDONE (1 << 3) /* Bit 3: Interrupt for event RESULTDONE */
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#define SAADC_INT_CALDONE (1 << 4) /* Bit 4: Interrupt for event CALIBRATEDONE */
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#define SAADC_INT_STOPPED (1 << 5) /* Bit 5: Interrupt for event STOPPED */
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#define SAADC_INT_STARTED (1 << 0) /* Bit 0: Interrupt for event STARTED */
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#define SAADC_INT_END (1 << 1) /* Bit 1: Interrupt for event END */
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#define SAADC_INT_DONE (1 << 2) /* Bit 2: Interrupt for event DONE */
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#define SAADC_INT_RESDONE (1 << 3) /* Bit 3: Interrupt for event RESULTDONE */
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#define SAADC_INT_CALDONE (1 << 4) /* Bit 4: Interrupt for event CALIBRATEDONE */
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#define SAADC_INT_STOPPED (1 << 5) /* Bit 5: Interrupt for event STOPPED */
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#define SAADC_INT_CHXLIMH(x) (1 << (x + 0x6)) /* Bit (x+6): Interrupt for event CHxLIMITH */
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#define SAADC_INT_CHXLIML(x) (1 << (x + 0x7)) /* Bit (x+7): Interrupt for event CHxLIMITL */
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@@ -100,52 +100,36 @@
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#define SAADC_ENABLE_DIS (0) /* Bit 0: Disable SAADC */
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#define SAADC_ENABLE_EN (1 << 0) /* Bit 0: Enable SAADC */
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/* CH[n] PSELP Register */
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/* CH[n] PSELx Register */
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#define SAADC_CHPSELP_SHIFT (0) /* Bits 0-4: Input positive pin selection for CH[x] */
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#define SAADC_CHPSELP_MASK (0xf << SAADC_CHPSELP_SHIFT)
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# define SAADC_CHPSELP_NC (0x0 << SAADC_CHPSELP_SHIFT)
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# define SAADC_CHPSELP_IN0 (0x1 << SAADC_CHPSELP_SHIFT)
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# define SAADC_CHPSELP_IN1 (0x2 << SAADC_CHPSELP_SHIFT)
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# define SAADC_CHPSELP_IN2 (0x3 << SAADC_CHPSELP_SHIFT)
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# define SAADC_CHPSELP_IN3 (0x4 << SAADC_CHPSELP_SHIFT)
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# define SAADC_CHPSELP_IN4 (0x5 << SAADC_CHPSELP_SHIFT)
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# define SAADC_CHPSELP_IN5 (0x6 << SAADC_CHPSELP_SHIFT)
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# define SAADC_CHPSELP_IN6 (0x7 << SAADC_CHPSELP_SHIFT)
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# define SAADC_CHPSELP_IN7 (0x8 << SAADC_CHPSELP_SHIFT)
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# define SAADC_CHPSELP_VDD (0x9 << SAADC_CHPSELP_SHIFT)
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# define SAADC_CHPSELP_VDDHDIV5 (0xd << SAADC_CHPSELP_SHIFT)
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/* CH[n] PSELN Register */
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#define SAADC_CHPSELN_SHIFT (0) /* Bits 0-4: Input negative pin selection for CH[x] */
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#define SAADC_CHPSELN_MASK (0xf << SAADC_CHPSELN_SHIFT)
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# define SAADC_CHPSELN_NC (0x0 << SAADC_CHPSELN_SHIFT)
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# define SAADC_CHPSELN_IN0 (0x1 << SAADC_CHPSELN_SHIFT)
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# define SAADC_CHPSELN_IN1 (0x2 << SAADC_CHPSELN_SHIFT)
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# define SAADC_CHPSELN_IN2 (0x3 << SAADC_CHPSELN_SHIFT)
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# define SAADC_CHPSELN_IN3 (0x4 << SAADC_CHPSELN_SHIFT)
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# define SAADC_CHPSELN_IN4 (0x5 << SAADC_CHPSELN_SHIFT)
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# define SAADC_CHPSELN_IN5 (0x6 << SAADC_CHPSELN_SHIFT)
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# define SAADC_CHPSELN_IN6 (0x7 << SAADC_CHPSELN_SHIFT)
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# define SAADC_CHPSELN_IN7 (0x8 << SAADC_CHPSELN_SHIFT)
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# define SAADC_CHPSELN_VDD (0x9 << SAADC_CHPSELN_SHIFT)
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# define SAADC_CHPSELN_VDDHDIV5 (0xd << SAADC_CHPSELN_SHIFT)
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#define SAADC_CHPSEL_SHIFT (0) /* Bits 0-4: Input positive pin selection for CH[x] */
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#define SAADC_CHPSEL_MASK (0xf << SAADC_CHPSEL_SHIFT)
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# define SAADC_CHPSEL_NC (0x0 << SAADC_CHPSEL_SHIFT)
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# define SAADC_CHPSEL_IN0 (0x1 << SAADC_CHPSEL_SHIFT)
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# define SAADC_CHPSEL_IN1 (0x2 << SAADC_CHPSEL_SHIFT)
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# define SAADC_CHPSEL_IN2 (0x3 << SAADC_CHPSEL_SHIFT)
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# define SAADC_CHPSEL_IN3 (0x4 << SAADC_CHPSEL_SHIFT)
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# define SAADC_CHPSEL_IN4 (0x5 << SAADC_CHPSEL_SHIFT)
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# define SAADC_CHPSEL_IN5 (0x6 << SAADC_CHPSEL_SHIFT)
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# define SAADC_CHPSEL_IN6 (0x7 << SAADC_CHPSEL_SHIFT)
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# define SAADC_CHPSEL_IN7 (0x8 << SAADC_CHPSEL_SHIFT)
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# define SAADC_CHPSEL_VDD (0x9 << SAADC_CHPSEL_SHIFT)
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# define SAADC_CHPSEL_VDDHDIV5 (0xd << SAADC_CHPSEL_SHIFT)
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/* CH[n] CONFIG Register */
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#define SAADC_CONFIG_RESP_SHIFT (0) /* Bits 0-2: Positive channel resistor control */
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#define SAADC_CONFIG_RESP_MASK (0x3 << SAADC_CONFIG_RESP_SHIFT)
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# define SAADC_CONFIG_RESN_NONE (0x0 << SAADC_CONFIG_RESP_SHIFT)
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# define SAADC_CONFIG_RESN_PD (0x1 << SAADC_CONFIG_RESP_SHIFT)
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# define SAADC_CONFIG_RESN_PU (0x2 << SAADC_CONFIG_RESP_SHIFT)
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# define SAADC_CONFIG_RESN_VDD1P2 (0x3 << SAADC_CONFIG_RESP_SHIFT)
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# define SAADC_CONFIG_RESP_NONE (0x0 << SAADC_CONFIG_RESP_SHIFT)
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# define SAADC_CONFIG_RESP_PD (0x1 << SAADC_CONFIG_RESP_SHIFT)
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# define SAADC_CONFIG_RESP_PU (0x2 << SAADC_CONFIG_RESP_SHIFT)
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# define SAADC_CONFIG_RESP_VDD1P2 (0x3 << SAADC_CONFIG_RESP_SHIFT)
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#define SAADC_CONFIG_RESN_SHIFT (4) /* Bits 4-5: Negative channel resistor control */
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#define SAADC_CONFIG_RESN_MASK (0x3 << SAADC_CONFIG_RESN_SHIFT)
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# define SAADC_CONFIG_RESN_NONE (0x0 << SAADC_CONFIG_RESN_SHIFT)
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# define SAADC_CONFIG_RESN_PD (0x1 << SAADC_CONFIG_RESN_SHIFT)
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# define SAADC_CONFIG_RESN_PU (0x2 << SAADC_CONFIG_RESN_SHIFT)
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# define SAADC_CONFIG_RESN_VDD1D2 (0x3 << SAADC_CONFIG_RESN_SHIFT)
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# define SAADC_CONFIG_RESN_VDD1P2 (0x3 << SAADC_CONFIG_RESN_SHIFT)
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#define SAADC_CONFIG_GAIN_SHIFT (8) /* Bits 8-10: Gain control */
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#define SAADC_CONFIG_GAIN_MASK (0x7 << SAADC_CONFIG_GAIN_SHIFT)
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# define SAADC_CONFIG_GAIN_1P6 (0x0 << SAADC_CONFIG_GAIN_SHIFT)
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@@ -156,8 +140,8 @@
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# define SAADC_CONFIG_GAIN_1 (0x5 << SAADC_CONFIG_GAIN_SHIFT)
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# define SAADC_CONFIG_GAIN_2 (0x6 << SAADC_CONFIG_GAIN_SHIFT)
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# define SAADC_CONFIG_GAIN_4 (0x7 << SAADC_CONFIG_GAIN_SHIFT)
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#define SAADC_REFSEL_INTERNAL (0 << 12) /* Bit 12: Internal reference (0.6V) */
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#define SAADC_REFSEL_VDD1P4 (1 << 12) /* Bit 12: VDD/4 as reference */
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#define SAADC_CONFIG_REFSEL_INTERNAL (0 << 12) /* Bit 12: Internal reference (0.6V) */
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#define SAADC_CONFIG_REFSEL_VDD1P4 (1 << 12) /* Bit 12: VDD/4 as reference */
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#define SAADC_CONFIG_TACQ_SHIFT (16) /* Bits 16-18: Acquisition time */
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#define SAADC_CONFIG_TACQ_MASK (0x7 << SAADC_CONFIG_TACQ_SHIFT)
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# define SAADC_CONFIG_TACQ_3US (0x0 << SAADC_CONFIG_TACQ_SHIFT)
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,161 @@
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/****************************************************************************
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* arch/arm/src/nrf52/nrf52_adc.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_NRF52_NRF52_ADC_H
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#define __ARCH_ARM_SRC_NRF52_NRF52_ADC_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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#include <nuttx/analog/adc.h>
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/****************************************************************************
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* Public Types
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****************************************************************************/
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/* ADC input */
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enum nrf52_adc_ain_e
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{
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NRF52_ADC_IN_NC = 0, /* Not connected */
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NRF52_ADC_IN_IN0 = 1, /* Analog input 0 */
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NRF52_ADC_IN_IN1 = 2, /* Analog input 1 */
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NRF52_ADC_IN_IN2 = 3, /* Analog input 2 */
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NRF52_ADC_IN_IN3 = 4, /* Analog input 3 */
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NRF52_ADC_IN_IN4 = 5, /* Analog input 4 */
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NRF52_ADC_IN_IN5 = 6, /* Analog input 5 */
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NRF52_ADC_IN_IN6 = 7, /* Analog input 6 */
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NRF52_ADC_IN_IN7 = 8, /* Analog input 7 */
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NRF52_ADC_IN_VDD = 9, /* VDD */
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NRF52_ADC_IN_VDDHDIV5 = 10, /* VDDH/5 */
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};
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/* Resistor control */
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enum nrf52_adc_res_e
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{
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NRF52_ADC_RES_BYPASS = 0, /* Bypass resistor ladder */
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NRF52_ADC_RES_PULLDOWN = 1, /* Pull-down to GND */
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NRF52_ADC_RES_PULLUP = 2, /* Pull-up to VDD */
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NRF52_ADC_RES_VDD_2 = 3 /* Set input at VDD/2 */
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};
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/* Gain control */
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enum nrf52_adc_gain_e
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{
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NRF52_ADC_GAIN_1_6 = 0, /* 1/6 */
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NRF52_ADC_GAIN_1_5 = 1, /* 1/5 */
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NRF52_ADC_GAIN_1_4 = 2, /* 1/4 */
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NRF52_ADC_GAIN_1_3 = 3, /* 1/3 */
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NRF52_ADC_GAIN_1_2 = 4, /* 1/2 */
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NRF52_ADC_GAIN_1 = 5, /* 1 */
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NRF52_ADC_GAIN_2 = 6, /* 2 */
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NRF52_ADC_GAIN_4 = 7 /* 4 */
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};
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/* Reference control */
|
||||
|
||||
enum nrf52_adc_refsel_e
|
||||
{
|
||||
NRF52_ADC_REFSEL_INTERNAL = 0, /* Internal reference (0.6V) */
|
||||
NRF52_ADC_REFSEL_VDD_4 = 1 /* VDD/4 as reference */
|
||||
};
|
||||
|
||||
/* Acquisition time control */
|
||||
|
||||
enum nrf52_adc_tacq_e
|
||||
{
|
||||
NRF52_ADC_TACQ_3US = 0, /* 3 us */
|
||||
NRF52_ADC_TACQ_5US = 1, /* 5 us */
|
||||
NRF52_ADC_TACQ_10US = 2, /* 10 us */
|
||||
NRF52_ADC_TACQ_15US = 3, /* 15 us */
|
||||
NRF52_ADC_TACQ_20US = 4, /* 20 us */
|
||||
NRF52_ADC_TACQ_40US = 5 /* 40 us */
|
||||
};
|
||||
|
||||
/* ADC mode control */
|
||||
|
||||
enum nrf52_adc_mode_e
|
||||
{
|
||||
NRF52_ADC_MODE_SE = 0, /* Single-ended mode */
|
||||
NRF52_ADC_MODE_DIFF = 1 /* Differentail mode */
|
||||
};
|
||||
|
||||
/* ADC burst control */
|
||||
|
||||
enum nrf52_adc_burst_e
|
||||
{
|
||||
NRF52_ADC_BURST_DISABLE = 0, /* Disable burst mode */
|
||||
NRF52_ADC_BURST_ENABLE = 1 /* Enable burst mode */
|
||||
};
|
||||
|
||||
/* NRF52 ADC channel configuration */
|
||||
|
||||
struct nrf52_adc_channel_s
|
||||
{
|
||||
uint32_t p_psel; /* P pin */
|
||||
uint32_t n_psel; /* N pin */
|
||||
#ifdef CONFIG_NRF52_SAADC_LIMITS
|
||||
uint16_t limith; /* High limit */
|
||||
uint16_t limitl; /* Low limit */
|
||||
#endif
|
||||
uint8_t resp:2; /* Positive chan resistor */
|
||||
uint8_t resn:2; /* Negative chan resistor */
|
||||
uint8_t gain:3; /* Gain control */
|
||||
uint8_t refsel:1; /* Reference control */
|
||||
uint8_t tacq:3; /* Acquisition time */
|
||||
uint8_t mode:1; /* Singe-ended or differential mode */
|
||||
uint8_t burst:1; /* Burst mode */
|
||||
uint8_t _res:3; /* Reserved */
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: nrf52_adcinitialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize the ADC. See nrf52_adc.c for more details.
|
||||
*
|
||||
* Input Parameters:
|
||||
* chanlist - channels configuration
|
||||
* nchannels - number of channels
|
||||
*
|
||||
* Returned Value:
|
||||
* Valid ADC device structure reference on success; a NULL on failure
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
struct adc_dev_s *nrf52_adcinitialize(FAR struct nrf52_adc_channel_s *chan,
|
||||
int channels);
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_NRF52_NRF52_ADC_H */
|
||||
Reference in New Issue
Block a user