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Merged in jjlange/nuttx/lpc40xx (pull request #946)
Add support for LPC40xx family chips
* Corrected a few peripheral definitions and pin functions for the LPC17xx family.
Added configuration options, chip definitions, and additional pin functions for the LPC40xx family.
Added board configurations for Embedded Artists LPC4088 Quickstart board and LPC4088 Developer's kit. These configurations are still something of a work in progress. In particular, the LCD functionality is untested.
* First pass rename in *.c and *.h files.
* Renamed LPC17XX to LPC17XX_40XX in config files
* Rplaced LPC17xx with LPC17xx/LPC40xx in .c files
* Replaced LPC17xx with LPC17xx/LPC40xx in .h files
* Updated some documentation
* Working on moving directories
* moved arch/arm/src/lpc17xx and arch/arm/include/lpc17xx to lpc17xx_40xx
* Renamed LPC17_* constants / configuration options to LPC17_40_*
* Updated chip family name defines
* Renamed some chip-specific files
* Updated references to renamed files
* Updated references to lpc17_ to lpc17_40_
* Renamed source files from lpc17_* to lpc17_40_*
* Clean up white space
Approved-by: Gregory Nutt <gnutt@nuttx.org>
This commit is contained in:
jjlange
Gregory Nutt
@@ -6273,7 +6273,7 @@ int kbd_decode(FAR struct lib_instream_s *stream, FAR struct kbd_getstate_s *sta
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</p>
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<p>
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<b>Examples</b>:
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<code>arch/arm/src/lpc17xx/lpc17_usbhost.c</code>,
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<code>arch/arm/src/lpc17xx_40xx/lpc17_40_usbhost.c</code>,
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<code>arch/arm/src/stm32/stm32_otgfshost.c</code>,
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<code>arch/arm/src/sama5/sam_ohci.c</code>, and
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<code>arch/arm/src/sama5/sam_ehci.c</code>.
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@@ -6366,7 +6366,7 @@ int kbd_decode(FAR struct lib_instream_s *stream, FAR struct kbd_getstate_s *sta
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</p>
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<p>
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<b>Examples</b>:
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The function <code>nsh_waiter()</code> in the file <code>configs/olimex-lpc1766stk/src/lpc17_appinit.c</code>.
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The function <code>nsh_waiter()</code> in the file <code>configs/olimex-lpc1766stk/src/lpc17_40_appinit.c</code>.
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</p>
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</li>
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<li>
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@@ -6409,7 +6409,7 @@ int kbd_decode(FAR struct lib_instream_s *stream, FAR struct kbd_getstate_s *sta
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</p>
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<p>
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<b>Examples</b>:
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<code>arch/arm/src/dm320/dm320_usbdev.c</code>, <code>arch/arm/src/lpc17xx/lpc17_usbdev.c</code>,
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<code>arch/arm/src/dm320/dm320_usbdev.c</code>, <code>arch/arm/src/lpc17xx_40xx/lpc17_40_usbdev.c</code>,
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<code>arch/arm/src/lpc214x/lpc214x_usbdev.c</code>, <code>arch/arm/src/lpc313x/lpc313x_usbdev.c</code>, and
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<code>arch/arm/src/stm32/stm32_usbdev.c</code>.
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</p>
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@@ -112,7 +112,7 @@
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</li>
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<li>
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For the USB device driver, that 8-bit event data is provided within the USB device driver itself.
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So, for example, the 8-bit event data for the LPC1768 USB device driver is found in <code>arch/arm/src/lpc17xx/lpc17_usbdev.c</code>.
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So, for example, the 8-bit event data for the LPC1768 USB device driver is found in <code>arch/arm/src/lpc17xx_40xx/lpc17_40_usbdev.c</code>.
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</li>
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</ul>
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<p><b>16-bit Trace Data</b>.
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@@ -237,28 +237,28 @@
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<td align="center">3</td>
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<td align="left"><code>TRACE_INTENTRY_ID</code><sup>1</sup></td>
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<td align="right">1</td>
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<td align="left"><code>LPC17_TRACEINTID_USB</code><sup>2</sup></td>
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<td align="left"><code>LPC17_40_TRACEINTID_USB</code><sup>2</sup></td>
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<td align="left">0039</td>
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</tr>
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<tr>
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<td align="center">4</td>
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<td align="left"><code>TRACE_INTDECODE_ID</code><sup>2</sup></td>
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<td align="right">7</td>
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<td align="left"><code>LPC17_TRACEINTID_DEVSTAT</code><sup>2</sup></td>
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<td align="left"><code>LPC17_40_TRACEINTID_DEVSTAT</code><sup>2</sup></td>
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<td align="left">0019</td>
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</tr>
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<tr>
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<td align="center">5</td>
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<td align="left"><code>TRACE_INTDECODE_ID</code><sup>2</sup></td>
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<td align="right">32</td>
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<td align="left"><code>LPC17_TRACEINTID_SUSPENDCHG</code><sup>2</sup></td>
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<td align="left"><code>LPC17_40_TRACEINTID_SUSPENDCHG</code><sup>2</sup></td>
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<td align="left">0019</td>
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</tr>
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<tr>
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<td align="center">6</td>
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<td align="left"><code>TRACE_INTDECODE_ID</code><sup>2</sup></td>
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<td align="right">6</td>
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<td align="left"><code>LPC17_TRACEINTID_DEVRESET</code><sup>2</sup></td>
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<td align="left"><code>LPC17_40_TRACEINTID_DEVRESET</code><sup>2</sup></td>
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<td align="left">0019</td>
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</tr>
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<tr>
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@@ -279,13 +279,13 @@
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<td align="center">9</td>
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<td align="left"><code>TRACE_INTEXIT_ID</code><sup>1</sup></td>
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<td align="right">1</td>
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<td align="left"><code>LPC17_TRACEINTID_USB</code><sup>2</sup></td>
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<td align="left"><code>LPC17_40_TRACEINTID_USB</code><sup>2</sup></td>
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<td align="left">0000</td>
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</tr>
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</table>
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<p><small><b>NOTES</b>:<br>
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<sup>1</sup>See <code>include/nuttx/usb/usbdev_trace.h</code><br>
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<sup>2</sup><code>See arch/arm/src/lpc17xx/lpc17_usbdev.c</code>
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<sup>2</sup><code>See arch/arm/src/lpc17xx_40xx/lpc17_40_usbdev.c</code>
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</small></p>
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</ul>
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<p>
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@@ -168,7 +168,7 @@ arch/arm - ARM-based micro-controllers
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arch/arm/include/kl and arch/arm/src/kl
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arch/arm/include/lpc11xx and arch/arm/src/lc823450
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arch/arm/include/lpc11xx and arch/arm/src/lpc11xx
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arch/arm/include/lpc17xx and arch/arm/src/lpc17xx
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arch/arm/include/lpc17xx_40xx and arch/arm/src/lpc17xx_40xx
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arch/arm/include/lpc214x and arch/arm/src/lpc214x
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arch/arm/include/lpc2378 and arch/arm/src/lpc2378.
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arch/arm/include/lpc31xx and arch/arm/src/lpc31xx
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@@ -139,15 +139,14 @@ config ARCH_CHIP_LPC11XX
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---help---
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NXP LPC11xx architectures (ARM Cortex-M0)
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config ARCH_CHIP_LPC17XX
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bool "NXP LPC17xx"
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select ARCH_CORTEXM3
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config ARCH_CHIP_LPC17XX_40XX
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bool "NXP LPC17xx/LPC40xx"
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select ARCH_HAVE_MPU
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select ARM_HAVE_MPU_UNIFIED
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select ARCH_HAVE_FETCHADD
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select ARMV7M_HAVE_STACKCHECK
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---help---
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NXP LPC17xx architectures (ARM Cortex-M3)
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NXP LPC17xx & LPC40xx architectures (ARM Cortex-M3/4)
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config ARCH_CHIP_LPC214X
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bool "NXP LPC214x"
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@@ -667,7 +666,7 @@ config ARCH_CHIP
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default "lc823450" if ARCH_CHIP_LC823450
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default "tiva" if ARCH_CHIP_LM || ARCH_CHIP_TIVA ||ARCH_CHIP_SIMPLELINK
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default "lpc11xx" if ARCH_CHIP_LPC11XX
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default "lpc17xx" if ARCH_CHIP_LPC17XX
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default "lpc17xx_40xx" if ARCH_CHIP_LPC17XX_40XX
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default "lpc214x" if ARCH_CHIP_LPC214X
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default "lpc2378" if ARCH_CHIP_LPC2378
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default "lpc31xx" if ARCH_CHIP_LPC31XX
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@@ -880,8 +879,8 @@ endif
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if ARCH_CHIP_LPC11XX
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source arch/arm/src/lpc11xx/Kconfig
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endif
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if ARCH_CHIP_LPC17XX
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source arch/arm/src/lpc17xx/Kconfig
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if ARCH_CHIP_LPC17XX_40XX
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source arch/arm/src/lpc17xx_40xx/Kconfig
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endif
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if ARCH_CHIP_LPC214X
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source arch/arm/src/lpc214x/Kconfig
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@@ -1,388 +0,0 @@
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/************************************************************************************
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* arch/arm/include/lpc17xx/chip.h
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*
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* Copyright (C) 2010-2011, 2013 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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* with LPC178x support from Rommel Marcelo
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*
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* Redistribution and use in source and binary forms, with or without
|
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* modification, are permitted provided that the following conditions
|
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* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
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* without specific prior written permission.
|
||||
*
|
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_INCLUDE_LPC17XX_CHIP_H
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#define __ARCH_ARM_INCLUDE_LPC17XX_CHIP_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Get customizations for each supported chip */
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#if defined(CONFIG_ARCH_CHIP_LPC1751)
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# define LPC176x 1 /* LPC175/6 family */
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# undef LPC178x /* Not LPC177/8 family */
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# define LPC17_FLASH_SIZE (32*1024) /* 32Kb */
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# define LPC17_SRAM_SIZE (8*1024) /* 8Kb */
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# define LPC17_CPUSRAM_SIZE (8*1024)
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# undef LPC17_HAVE_BANK0 /* No AHB SRAM bank 0 */
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# undef LPC17_HAVE_BANK1 /* No AHB SRAM bank 1 */
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# define LPC17_NETHCONTROLLERS 0 /* No Ethernet controller */
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# define LPC17_NUSBHOST 0 /* No USB host controller */
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# define LPC17_NUSBOTG 0 /* No USB OTG controller */
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# define LPC17_NUSBDEV 1 /* One USB device controller */
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# define LPC17_NCAN 1 /* One CAN controller */
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# define LPC17_NI2S 0 /* No I2S modules */
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# define LPC17_NDAC 0 /* No DAC module */
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#elif defined(CONFIG_ARCH_CHIP_LPC1752)
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# define LPC176x 1 /* LPC175/6 family */
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# undef LPC178x /* Not LPC177/8 family */
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# define LPC17_FLASH_SIZE (64*1024) /* 65Kb */
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# define LPC17_SRAM_SIZE (16*1024) /* 16Kb */
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# define LPC17_CPUSRAM_SIZE (16*1024)
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# undef LPC17_HAVE_BANK0 /* No AHB SRAM bank 0 */
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# undef LPC17_HAVE_BANK1 /* No AHB SRAM bank 1 */
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# define LPC17_NETHCONTROLLERS 0 /* No Ethernet controller */
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# define LPC17_NUSBHOST 0 /* No USB host controller */
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# define LPC17_NUSBOTG 0 /* No USB OTG controller */
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# define LPC17_NUSBDEV 1 /* One USB device controller */
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# define LPC17_NCAN 1 /* One CAN controller */
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# define LPC17_NI2S 0 /* No I2S modules */
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# define LPC17_NDAC 0 /* No DAC module */
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#elif defined(CONFIG_ARCH_CHIP_LPC1754)
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# define LPC176x 1 /* LPC175/6 family */
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# undef LPC178x /* Not LPC177/8 family */
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# define LPC17_FLASH_SIZE (128*1024) /* 128Kb */
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# define LPC17_SRAM_SIZE (32*1024) /* 32Kb */
|
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# define LPC17_CPUSRAM_SIZE (16*1024)
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# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */
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# undef LPC17_HAVE_BANK1 /* No AHB SRAM bank 1 */
|
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# define LPC17_NETHCONTROLLERS 0 /* No Ethernet controller */
|
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# define LPC17_NUSBHOST 1 /* One USB host controller */
|
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# define LPC17_NUSBOTG 1 /* One USB OTG controller */
|
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# define LPC17_NUSBDEV 1 /* One USB device controller */
|
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# define LPC17_NCAN 1 /* One CAN controller */
|
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# define LPC17_NI2S 0 /* No I2S modules */
|
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# define LPC17_NDAC 1 /* One DAC module */
|
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#elif defined(CONFIG_ARCH_CHIP_LPC1756)
|
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# define LPC176x 1 /* LPC175/6 family */
|
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# undef LPC178x /* Not LPC177/8 family */
|
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# define LPC17_FLASH_SIZE (256*1024) /* 256Kb */
|
||||
# define LPC17_SRAM_SIZE (32*1024) /* 32Kb */
|
||||
# define LPC17_CPUSRAM_SIZE (16*1024)
|
||||
# define LPC17_HAVE_BANK0 1 /* No AHB SRAM bank 0 */
|
||||
# undef LPC17_HAVE_BANK1 /* No AHB SRAM bank 1 */
|
||||
# define LPC17_NETHCONTROLLERS 0 /* No Ethernet controller */
|
||||
# define LPC17_NUSBHOST 1 /* One USB host controller */
|
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# define LPC17_NUSBOTG 1 /* One USB OTG controller */
|
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# define LPC17_NUSBDEV 1 /* One USB device controller */
|
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# define LPC17_NCAN 2 /* Two CAN controllers */
|
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# define LPC17_NI2S 1 /* One I2S module */
|
||||
# define LPC17_NDAC 1 /* One DAC module */
|
||||
#elif defined(CONFIG_ARCH_CHIP_LPC1758)
|
||||
# define LPC176x 1 /* LPC175/6 family */
|
||||
# undef LPC178x /* Not LPC177/8 family */
|
||||
# define LPC17_FLASH_SIZE (512*1024) /* 512Kb */
|
||||
# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */
|
||||
# define LPC17_CPUSRAM_SIZE (32*1024)
|
||||
# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */
|
||||
# define LPC17_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */
|
||||
# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */
|
||||
# define LPC17_NUSBHOST 1 /* One USB host controller */
|
||||
# define LPC17_NUSBOTG 1 /* One USB OTG controller */
|
||||
# define LPC17_NUSBDEV 1 /* One USB device controller */
|
||||
# define LPC17_NCAN 2 /* Two CAN controllers */
|
||||
# define LPC17_NI2S 1 /* One I2S module */
|
||||
# define LPC17_NDAC 1 /* One DAC module */
|
||||
#elif defined(CONFIG_ARCH_CHIP_LPC1759)
|
||||
# define LPC176x 1 /* LPC175/6 family */
|
||||
# undef LPC178x /* Not LPC177/8 family */
|
||||
# define LPC17_FLASH_SIZE (512*1024) /* 512Kb */
|
||||
# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */
|
||||
# define LPC17_CPUSRAM_SIZE (32*1024)
|
||||
# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */
|
||||
# define LPC17_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */
|
||||
# define LPC17_NETHCONTROLLERS 0 /* No Ethernet controller */
|
||||
# define LPC17_NUSBHOST 1 /* One USB host controller */
|
||||
# define LPC17_NUSBOTG 1 /* One USB OTG controller */
|
||||
# define LPC17_NUSBDEV 1 /* One USB device controller */
|
||||
# define LPC17_NCAN 2 /* Two CAN controllers */
|
||||
# define LPC17_NI2S 1 /* One I2S module */
|
||||
# define LPC17_NDAC 1 /* One DAC module */
|
||||
#elif defined(CONFIG_ARCH_CHIP_LPC1764)
|
||||
# define LPC176x 1 /* LPC175/6 family */
|
||||
# undef LPC178x /* Not LPC177/8 family */
|
||||
# define LPC17_FLASH_SIZE (128*1024) /* 128Kb */
|
||||
# define LPC17_SRAM_SIZE (32*1024) /* 32Kb */
|
||||
# define LPC17_CPUSRAM_SIZE (16*1024)
|
||||
# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */
|
||||
# undef LPC17_HAVE_BANK1 /* No AHB SRAM bank 1 */
|
||||
# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */
|
||||
# define LPC17_NUSBHOST 0 /* No USB host controller */
|
||||
# define LPC17_NUSBOTG 0 /* No USB OTG controller */
|
||||
# define LPC17_NUSBDEV 1 /* One USB device controller */
|
||||
# define LPC17_NCAN 2 /* Two CAN controllers */
|
||||
# define LPC17_NI2S 0 /* No I2S modules */
|
||||
# define LPC17_NDAC 0 /* No DAC module */
|
||||
#elif defined(CONFIG_ARCH_CHIP_LPC1765)
|
||||
# define LPC176x 1 /* LPC175/6 family */
|
||||
# undef LPC178x /* Not LPC177/8 family */
|
||||
# define LPC17_FLASH_SIZE (256*1024) /* 256Kb */
|
||||
# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */
|
||||
# define LPC17_CPUSRAM_SIZE (32*1024)
|
||||
# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */
|
||||
# define LPC17_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */
|
||||
# define LPC17_NETHCONTROLLERS 0 /* No Ethernet controller */
|
||||
# define LPC17_NUSBHOST 1 /* One USB host controller */
|
||||
# define LPC17_NUSBOTG 1 /* One USB OTG controller */
|
||||
# define LPC17_NUSBDEV 1 /* One USB device controller */
|
||||
# define LPC17_NCAN 2 /* Two CAN controllers */
|
||||
# define LPC17_NI2S 1 /* One I2S module */
|
||||
# define LPC17_NDAC 1 /* One DAC module */
|
||||
#elif defined(CONFIG_ARCH_CHIP_LPC1766)
|
||||
# define LPC176x 1 /* LPC175/6 family */
|
||||
# undef LPC178x /* Not LPC177/8 family */
|
||||
# define LPC17_FLASH_SIZE (256*1024) /* 256Kb */
|
||||
# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */
|
||||
# define LPC17_CPUSRAM_SIZE (32*1024)
|
||||
# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */
|
||||
# define LPC17_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */
|
||||
# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */
|
||||
# define LPC17_NUSBHOST 1 /* One USB host controller */
|
||||
# define LPC17_NUSBOTG 1 /* One USB OTG controller */
|
||||
# define LPC17_NUSBDEV 1 /* One USB device controller */
|
||||
# define LPC17_NCAN 2 /* Two CAN controllers */
|
||||
# define LPC17_NI2S 1 /* One I2S module */
|
||||
# define LPC17_NDAC 1 /* One DAC module */
|
||||
#elif defined(CONFIG_ARCH_CHIP_LPC1767)
|
||||
# define LPC176x 1 /* LPC175/6 family */
|
||||
# undef LPC178x /* Not LPC177/8 family */
|
||||
# define LPC17_FLASH_SIZE (512*1024) /* 512Kb */
|
||||
# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */
|
||||
# define LPC17_CPUSRAM_SIZE (32*1024)
|
||||
# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */
|
||||
# define LPC17_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */
|
||||
# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */
|
||||
# define LPC17_NUSBHOST 0 /* No USB host controller */
|
||||
# define LPC17_NUSBOTG 0 /* No USB OTG controller */
|
||||
# define LPC17_NUSBDEV 0 /* No USB device controller */
|
||||
# define LPC17_NCAN 0 /* No CAN controllers */
|
||||
# define LPC17_NI2S 1 /* One I2S module */
|
||||
# define LPC17_NDAC 1 /* One DAC module */
|
||||
#elif defined(CONFIG_ARCH_CHIP_LPC1769) || defined(CONFIG_ARCH_CHIP_LPC1768)
|
||||
# define LPC176x 1 /* LPC175/6 family */
|
||||
# undef LPC178x /* Not LPC177/8 family */
|
||||
# define LPC17_FLASH_SIZE (512*1024) /* 512Kb */
|
||||
# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */
|
||||
# define LPC17_CPUSRAM_SIZE (32*1024)
|
||||
# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */
|
||||
# define LPC17_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */
|
||||
# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */
|
||||
# define LPC17_NUSBHOST 1 /* One USB host controller */
|
||||
# define LPC17_NUSBOTG 1 /* One USB OTG controller */
|
||||
# define LPC17_NUSBDEV 1 /* One USB device controller */
|
||||
# define LPC17_NCAN 2 /* Two CAN controllers */
|
||||
# define LPC17_NI2S 1 /* One I2S module */
|
||||
# define LPC17_NDAC 1 /* One DAC module */
|
||||
#elif defined(CONFIG_ARCH_CHIP_LPC1773)
|
||||
# undef LPC176x /* Not LPC175/6 family */
|
||||
# define LPC178x 1 /* LPC177/8 family */
|
||||
# define LPC17_FLASH_SIZE (128*1024) /* 128Kb */
|
||||
# define LPC17_SRAM_SIZE (40*1024) /* 40Kb */
|
||||
# define LPC17_CPUSRAM_SIZE (32*1024)
|
||||
# define LPC17_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */
|
||||
# undef LPC17_HAVE_BANK1 /* No Peripheral SRAM bank 1 */
|
||||
# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */
|
||||
# undef LPC17_NUSBHOST /* No USB host controller */
|
||||
# undef LPC17_NUSBOTG /* No USB OTG controller */
|
||||
# define LPC17_NUSBDEV 1 /* One USB device controller */
|
||||
# define LPC17_HAVE_SPIFI 1 /* Have SPIFI interface */
|
||||
# undef LPC17_HAVE_LCD /* No LCD controller */
|
||||
# undef LPC17_HAVE_QEI /* No QEI interface */
|
||||
# undef LPC17_HAVE_SD /* No SD controller */
|
||||
#elif defined(CONFIG_ARCH_CHIP_LPC1774)
|
||||
# undef LPC176x /* Not LPC175/6 family */
|
||||
# define LPC178x 1 /* LPC177/8 family */
|
||||
# define LPC17_FLASH_SIZE (128*1024) /* 128Kb */
|
||||
# define LPC17_SRAM_SIZE (40*1024) /* 40Kb */
|
||||
# define LPC17_CPUSRAM_SIZE (32*1024)
|
||||
# define LPC17_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0*/
|
||||
# undef LPC17_HAVE_BANK1 /* Have Peripheral SRAM bank 1 */
|
||||
# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */
|
||||
# undef LPC17_NUSBHOST /* One USB host controller */
|
||||
# undef LPC17_NUSBOTG /* One USB OTG controller */
|
||||
# define LPC17_NUSBDEV 1 /* One USB device controller */
|
||||
# undef LPC17_HAVE_SPIFI /* Have SPIFI interface */
|
||||
# undef LPC17_HAVE_LCD /* One LCD controller */
|
||||
# define LPC17_HAVE_QEI 1 /* One QEI interface */
|
||||
# define LPC17_HAVE_SD 1 /* One SD controller */
|
||||
#elif defined(CONFIG_ARCH_CHIP_LPC1776)
|
||||
# undef LPC176x /* Not LPC175/6 family */
|
||||
# define LPC178x 1 /* LPC177/8 family */
|
||||
# define LPC17_FLASH_SIZE (256*1024) /* 256Kb */
|
||||
# define LPC17_SRAM_SIZE (80*1024) /* 80Kb */
|
||||
# define LPC17_CPUSRAM_SIZE (64*1024)
|
||||
# define LPC17_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */
|
||||
# undef LPC17_HAVE_BANK1 /* Have Peripheral SRAM bank 1 */
|
||||
# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */
|
||||
# define LPC17_NUSBHOST 1 /* One USB host controller */
|
||||
# define LPC17_NUSBOTG 1 /* One USB OTG controller */
|
||||
# define LPC17_NUSBDEV 1 /* One USB device controller */
|
||||
# undef LPC17_HAVE_SPIFI /* Have SPIFI interface */
|
||||
# undef LPC17_HAVE_LCD /* One LCD controller */
|
||||
# define LPC17_HAVE_QEI 1 /* One QEI interface */
|
||||
# define LPC17_HAVE_SD 1 /* One SD controller */
|
||||
#elif defined(CONFIG_ARCH_CHIP_LPC1777)
|
||||
# undef LPC176x /* Not LPC175/6 family */
|
||||
# define LPC178x 1 /* LPC177/8 family */
|
||||
# define LPC17_FLASH_SIZE (512*1024) /* 512Kb */
|
||||
# define LPC17_SRAM_SIZE (96*1024) /* 96Kb */
|
||||
# define LPC17_CPUSRAM_SIZE (64*1024)
|
||||
# define LPC17_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */
|
||||
# define LPC17_HAVE_BANK1 1 /* Have Peripheral SRAM bank 1 */
|
||||
# undef LPC17_NETHCONTROLLERS /* One Ethernet controller */
|
||||
# define LPC17_NUSBHOST 1 /* One USB host controller */
|
||||
# define LPC17_NUSBOTG 1 /* One USB OTG controller */
|
||||
# define LPC17_NUSBDEV 1 /* One USB device controller */
|
||||
# undef LPC17_HAVE_SPIFI /* Have SPIFI interface */
|
||||
# undef LPC17_HAVE_LCD /* One LCD controller */
|
||||
# define LPC17_HAVE_QEI 1 /* One QEI interface */
|
||||
# define LPC17_HAVE_SD 1 /* One SD controller */
|
||||
#elif defined(CONFIG_ARCH_CHIP_LPC1778)
|
||||
# undef LPC176x /* Not LPC175/6 family */
|
||||
# define LPC178x 1 /* LPC177/8 family */
|
||||
# define LPC17_FLASH_SIZE (512*1024) /* 512Kb */
|
||||
# define LPC17_SRAM_SIZE (96*1024) /* 64Kb */
|
||||
# define LPC17_CPUSRAM_SIZE (64*1024)
|
||||
# define LPC17_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */
|
||||
# define LPC17_HAVE_BANK1 1 /* Have Peripheral SRAM bank 1 */
|
||||
# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */
|
||||
# define LPC17_NUSBHOST 1 /* One USB host controller */
|
||||
# define LPC17_NUSBOTG 1 /* One USB OTG controller */
|
||||
# define LPC17_NUSBDEV 1 /* One USB device controller */
|
||||
# undef LPC17_HAVE_SPIFI /* Have SPIFI interface */
|
||||
# undef LPC17_HAVE_LCD /* One LCD controller */
|
||||
# define LPC17_HAVE_QEI 1 /* One QEI interface */
|
||||
# define LPC17_HAVE_SD 1 /* One SD controller */
|
||||
#elif defined(CONFIG_ARCH_CHIP_LPC1785)
|
||||
# undef LPC176x /* Not LPC175/6 family */
|
||||
# define LPC178x 1 /* LPC177/8 family */
|
||||
# define LPC17_FLASH_SIZE (256*1024) /* 256Kb */
|
||||
# define LPC17_SRAM_SIZE (80*1024) /* 80Kb */
|
||||
# define LPC17_CPUSRAM_SIZE (64*1024)
|
||||
# define LPC17_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */
|
||||
# undef LPC17_HAVE_BANK1 /* Have Peripheral SRAM bank 1 */
|
||||
# undef LPC17_NETHCONTROLLERS /* One Ethernet controller */
|
||||
# define LPC17_NUSBHOST 1 /* One USB host controller */
|
||||
# define LPC17_NUSBOTG 1 /* One USB OTG controller */
|
||||
# define LPC17_NUSBDEV 1 /* One USB device controller */
|
||||
# undef LPC17_HAVE_SPIFI /* Have SPIFI interface */
|
||||
# define LPC17_HAVE_LCD 1 /* One LCD controller */
|
||||
# undef LPC17_HAVE_QEI /* One QEI interface */
|
||||
# define LPC17_HAVE_SD 1 /* One SD controller */
|
||||
#elif defined(CONFIG_ARCH_CHIP_LPC1786)
|
||||
# undef LPC176x /* Not LPC175/6 family */
|
||||
# define LPC178x 1 /* LPC177/8 family */
|
||||
# define LPC17_FLASH_SIZE (256*1024) /* 256Kb */
|
||||
# define LPC17_SRAM_SIZE (80*1024) /* 80Kb */
|
||||
# define LPC17_CPUSRAM_SIZE (64*1024)
|
||||
# define LPC17_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */
|
||||
# undef LPC17_HAVE_BANK1 /* Have Peripheral SRAM bank 1 */
|
||||
# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */
|
||||
# define LPC17_NUSBHOST 1 /* One USB host controller */
|
||||
# define LPC17_NUSBOTG 1 /* One USB OTG controller */
|
||||
# define LPC17_NUSBDEV 1 /* One USB device controller */
|
||||
# undef LPC17_HAVE_SPIFI /* Have SPIFI interface */
|
||||
# define LPC17_HAVE_LCD 1 /* One LCD controller */
|
||||
# define LPC17_HAVE_QEI 1 /* One QEI interface */
|
||||
# define LPC17_HAVE_SD 1 /* One SD controller */
|
||||
#elif defined(CONFIG_ARCH_CHIP_LPC1787)
|
||||
# undef LPC176x /* Not LPC175/6 family */
|
||||
# define LPC178x 1 /* LPC177/8 family */
|
||||
# define LPC17_FLASH_SIZE (512*1024) /* 512Kb */
|
||||
# define LPC17_SRAM_SIZE (96*1024) /* 96Kb */
|
||||
# define LPC17_CPUSRAM_SIZE (64*1024)
|
||||
# define LPC17_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */
|
||||
# define LPC17_HAVE_BANK1 1 /* Have Peripheral SRAM bank 1 */
|
||||
# undef LPC17_NETHCONTROLLERS /* One Ethernet controller */
|
||||
# define LPC17_NUSBHOST 1 /* One USB host controller */
|
||||
# define LPC17_NUSBOTG 1 /* One USB OTG controller */
|
||||
# define LPC17_NUSBDEV 1 /* One USB device controller */
|
||||
# undef LPC17_HAVE_SPIFI /* Have SPIFI interface */
|
||||
# define LPC17_HAVE_LCD 1 /* One LCD controller */
|
||||
# define LPC17_HAVE_QEI 1 /* One QEI interface */
|
||||
# define LPC17_HAVE_SD 1 /* One SD controller */
|
||||
#elif defined(CONFIG_ARCH_CHIP_LPC1788)
|
||||
# undef LPC176x /* Not LPC175/6 family */
|
||||
# define LPC178x 1 /* LPC177/8 family */
|
||||
# define LPC17_FLASH_SIZE (512*1024) /* 512Kb */
|
||||
# define LPC17_SRAM_SIZE (96*1024) /* 96Kb */
|
||||
# define LPC17_CPUSRAM_SIZE (64*1024)
|
||||
# define LPC17_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */
|
||||
# define LPC17_HAVE_BANK1 1 /* Have Peripheral SRAM bank 1 */
|
||||
# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */
|
||||
# define LPC17_NUSBHOST 1 /* One USB host controller */
|
||||
# define LPC17_NUSBOTG 1 /* One USB OTG controller */
|
||||
# define LPC17_NUSBDEV 1 /* One USB device controller */
|
||||
# undef LPC17_HAVE_SPIFI /* Have SPIFI interface */
|
||||
# define LPC17_HAVE_LCD 1 /* One LCD controller */
|
||||
# define LPC17_HAVE_QEI 1 /* One QEI interface */
|
||||
# define LPC17_HAVE_SD 1 /* One SD controller */
|
||||
#else
|
||||
# error "Unsupported LPC17xx chip"
|
||||
#endif
|
||||
|
||||
/* NVIC priority levels *************************************************************/
|
||||
/* Each priority field holds a priority value, 0-31. The lower the value, the greater
|
||||
* the priority of the corresponding interrupt. The processor implements only
|
||||
* bits[7:3] of each field, bits[2:0] read as zero and ignore writes.
|
||||
*/
|
||||
|
||||
#define NVIC_SYSH_PRIORITY_MIN 0xf8 /* All bits[7:3] set is minimum priority */
|
||||
#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
|
||||
#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
|
||||
#define NVIC_SYSH_PRIORITY_STEP 0x08 /* Five bits of interrupt priority used */
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_INCLUDE_LPC17XX_CHIP_H */
|
||||
@@ -1,245 +0,0 @@
|
||||
/****************************************************************************
|
||||
* arch/lpc17xx/lpc176x_irq.h
|
||||
*
|
||||
* Copyright (C) 2010-2011, 2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/* This file should never be included directed but, rather, only indirectly
|
||||
* through nuttx/irq.h
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_ARM_INCLUDE_LPC17XX_LPC176X_IRQ_H
|
||||
#define __ARCH_ARM_INCLUDE_LPC17XX_LPC176X_IRQ_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
/* IRQ numbers. The IRQ number corresponds vector number and hence map
|
||||
* directly to bits in the NVIC. This does, however, waste several words of
|
||||
* memory in the IRQ to handle mapping tables.
|
||||
*/
|
||||
|
||||
/* External interrupts (vectors >= 16) */
|
||||
|
||||
#define LPC17_IRQ_WDT (LPC17_IRQ_EXTINT+0) /* WDT Watchdog Interrupt (WDINT) */
|
||||
#define LPC17_IRQ_TMR0 (LPC17_IRQ_EXTINT+1) /* Timer 0 Match 0 - 1 (MR0, MR1)
|
||||
* Capture 0 - 1 (CR0, CR1) */
|
||||
#define LPC17_IRQ_TMR1 (LPC17_IRQ_EXTINT+2) /* Timer 1 Match 0 - 2 (MR0, MR1, MR2)
|
||||
* Capture 0 - 1 (CR0, CR1) */
|
||||
#define LPC17_IRQ_TMR2 (LPC17_IRQ_EXTINT+3) /* Timer 2 Match 0-3
|
||||
* Capture 0-1 */
|
||||
#define LPC17_IRQ_TMR3 (LPC17_IRQ_EXTINT+4) /* Timer 3 Match 0-3
|
||||
* Capture 0-1 */
|
||||
#define LPC17_IRQ_UART0 (LPC17_IRQ_EXTINT+5) /* UART 0 Rx Line Status (RLS)
|
||||
* Transmit Holding Register Empty (THRE)
|
||||
* Rx Data Available (RDA)
|
||||
* Character Time-out Indicator (CTI)
|
||||
* End of Auto-Baud (ABEO)
|
||||
* Auto-Baud Time-Out (ABTO) */
|
||||
#define LPC17_IRQ_UART1 (LPC17_IRQ_EXTINT+6) /* UART 1 Rx Line Status (RLS)
|
||||
* Transmit Holding Register Empty (THRE)
|
||||
* Rx Data Available (RDA)
|
||||
* Character Time-out Indicator (CTI)
|
||||
* Modem Control Change
|
||||
* End of Auto-Baud (ABEO)
|
||||
* Auto-Baud Time-Out (ABTO) */
|
||||
#define LPC17_IRQ_UART2 (LPC17_IRQ_EXTINT+7) /* UART 2 Rx Line Status (RLS)
|
||||
* Transmit Holding Register Empty (THRE)
|
||||
* Rx Data Available (RDA)
|
||||
* Character Time-out Indicator (CTI)
|
||||
* End of Auto-Baud (ABEO)
|
||||
* Auto-Baud Time-Out (ABTO) */
|
||||
#define LPC17_IRQ_UART3 (LPC17_IRQ_EXTINT+8) /* UART 3 Rx Line Status (RLS)
|
||||
* Transmit Holding Register Empty (THRE)
|
||||
* Rx Data Available (RDA)
|
||||
* Character Time-out Indicator (CTI)
|
||||
* End of Auto-Baud (ABEO)
|
||||
* Auto-Baud Time-Out (ABTO) */
|
||||
#define LPC17_IRQ_PWM1 (LPC17_IRQ_EXTINT+9) /* PWM1 Match 0 - 6 of PWM1
|
||||
* Capture 0-1 of PWM1 */
|
||||
#define LPC17_IRQ_I2C0 (LPC17_IRQ_EXTINT+10) /* I2C0 SI (state change) */
|
||||
#define LPC17_IRQ_I2C1 (LPC17_IRQ_EXTINT+11) /* I2C1 SI (state change) */
|
||||
#define LPC17_IRQ_I2C2 (LPC17_IRQ_EXTINT+12) /* I2C2 SI (state change) */
|
||||
#define LPC17_IRQ_SPIF (LPC17_IRQ_EXTINT+13) /* SPI SPI Interrupt Flag (SPIF)
|
||||
* Mode Fault (MODF) */
|
||||
#define LPC17_IRQ_SSP0 (LPC17_IRQ_EXTINT+14) /* SSP0 Tx FIFO half empty of SSP0
|
||||
* Rx FIFO half full of SSP0
|
||||
* Rx Timeout of SSP0
|
||||
* Rx Overrun of SSP0 */
|
||||
#define LPC17_IRQ_SSP1 (LPC17_IRQ_EXTINT+15) /* SSP 1 Tx FIFO half empty
|
||||
* Rx FIFO half full
|
||||
* Rx Timeout
|
||||
* Rx Overrun */
|
||||
#define LPC17_IRQ_PLL0 (LPC17_IRQ_EXTINT+16) /* PLL0 (Main PLL) PLL0 Lock (PLOCK0) */
|
||||
#define LPC17_IRQ_RTC (LPC17_IRQ_EXTINT+17) /* RTC Counter Increment (RTCCIF)
|
||||
* Alarm (RTCALF) */
|
||||
#define LPC17_IRQ_EINT0 (LPC17_IRQ_EXTINT+18) /* External Interrupt 0 (EINT0) */
|
||||
#define LPC17_IRQ_EINT1 (LPC17_IRQ_EXTINT+19) /* External Interrupt 1 (EINT1) */
|
||||
#define LPC17_IRQ_EINT2 (LPC17_IRQ_EXTINT+20) /* External Interrupt 2 (EINT2) */
|
||||
#define LPC17_IRQ_EINT3 (LPC17_IRQ_EXTINT+21) /* External Interrupt 3 (EINT3)
|
||||
* Note: EINT3 channel is shared with GPIO interrupts */
|
||||
#define LPC17_IRQ_ADC (LPC17_IRQ_EXTINT+22) /* ADC A/D Converter end of conversion */
|
||||
#define LPC17_IRQ_BOD (LPC17_IRQ_EXTINT+23) /* BOD Brown Out detect */
|
||||
#define LPC17_IRQ_USB (LPC17_IRQ_EXTINT+24) /* USB USB_INT_REQ_LP, USB_INT_REQ_HP,
|
||||
* USB_INT_REQ_DMA */
|
||||
#define LPC17_IRQ_CAN (LPC17_IRQ_EXTINT+25) /* CAN CAN Common, CAN 0 Tx, CAN 0 Rx,
|
||||
* CAN 1 Tx, CAN 1 Rx */
|
||||
#define LPC17_IRQ_GPDMA (LPC17_IRQ_EXTINT+26) /* GPDMA IntStatus of DMA channel 0,
|
||||
* IntStatus of DMA channel 1 */
|
||||
#define LPC17_IRQ_I2S (LPC17_IRQ_EXTINT+27) /* I2S irq, dmareq1, dmareq2 */
|
||||
#define LPC17_IRQ_ETH (LPC17_IRQ_EXTINT+28) /* Ethernet WakeupInt, SoftInt, TxDoneInt,
|
||||
* TxFinishedInt, TxErrorInt,* TxUnderrunInt,
|
||||
* RxDoneInt, RxFinishedInt, RxErrorInt,
|
||||
* RxOverrunInt */
|
||||
#define LPC17_IRQ_RITINT (LPC17_IRQ_EXTINT+29) /* Repetitive Interrupt Timer (RITINT) */
|
||||
#define LPC17_IRQ_MCPWM (LPC17_IRQ_EXTINT+30) /* Motor Control PWM IPER[2:0], IPW[2:0],
|
||||
* ICAP[2:0], FES */
|
||||
#define LPC17_IRQ_QEI (LPC17_IRQ_EXTINT+31) /* Quadrature Encoder INX_Int, TIM_Int, VELC_Int,
|
||||
* DIR_Int, ERR_Int, ENCLK_Int, POS0_Int, POS1_Int
|
||||
* POS2_Int, REV_Int, POS0REV_Int, OS1REV_Int,
|
||||
* POS2REV_Int */
|
||||
#define LPC17_IRQ_PLL1 (LPC17_IRQ_EXTINT+32) /* PLL1 (USB PLL) PLL1 Lock (PLOCK1) */
|
||||
#define LPC17_IRQ_USBACT (LPC17_IRQ_EXTINT+33) /* USB Activity Interrupt USB_NEED_CLK */
|
||||
#define LPC17_IRQ_CANACT (LPC17_IRQ_EXTINT+34) /* CAN Activity Interrupt CAN1WAKE, CAN2WAKE */
|
||||
#define LPC17_IRQ_NEXTINT (35)
|
||||
#define LPC17_IRQ_NIRQS (LPC17_IRQ_EXTINT+LPC17_IRQ_NEXTINT)
|
||||
|
||||
/* GPIO interrupts. The LPC17xx supports several interrupts on ports 0 and
|
||||
* 2 (only). We go through some special efforts to keep the number of IRQs
|
||||
* to a minimum in this sparse interrupt case.
|
||||
*
|
||||
* 28 interrupts on Port 0: p0.0 - p0.11, p0.15-p0.30
|
||||
* 14 interrupts on Port 2: p2.0 - p2.13
|
||||
* --
|
||||
* 42
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_LPC17_GPIOIRQ
|
||||
# define LPC17_VALID_GPIOINT0 (0x7fff8ffful) /* GPIO port 0 interrupt set */
|
||||
# define LPC17_VALID_GPIOINT2 (0x00003ffful) /* GPIO port 2 interrupt set */
|
||||
|
||||
/* Set 1: 12 interrupts p0.0-p0.11 */
|
||||
|
||||
# define LPC17_VALID_GPIOINT0L (0x00000ffful)
|
||||
# define LPC17_VALID_SHIFT0L (0)
|
||||
# define LPC17_VALID_FIRST0L (LPC17_IRQ_EXTINT+LPC17_IRQ_NEXTINT)
|
||||
|
||||
# define LPC17_IRQ_P0p0 (LPC17_VALID_FIRST0L+0)
|
||||
# define LPC17_IRQ_P0p1 (LPC17_VALID_FIRST0L+1)
|
||||
# define LPC17_IRQ_P0p2 (LPC17_VALID_FIRST0L+2)
|
||||
# define LPC17_IRQ_P0p3 (LPC17_VALID_FIRST0L+3)
|
||||
# define LPC17_IRQ_P0p4 (LPC17_VALID_FIRST0L+4)
|
||||
# define LPC17_IRQ_P0p5 (LPC17_VALID_FIRST0L+5)
|
||||
# define LPC17_IRQ_P0p6 (LPC17_VALID_FIRST0L+6)
|
||||
# define LPC17_IRQ_P0p7 (LPC17_VALID_FIRST0L+7)
|
||||
# define LPC17_IRQ_P0p8 (LPC17_VALID_FIRST0L+8)
|
||||
# define LPC17_IRQ_P0p9 (LPC17_VALID_FIRST0L+9)
|
||||
# define LPC17_IRQ_P0p10 (LPC17_VALID_FIRST0L+10)
|
||||
# define LPC17_IRQ_P0p11 (LPC17_VALID_FIRST0L+11)
|
||||
# define LPC17_VALID_NIRQS0L (12)
|
||||
|
||||
/* Set 2: 16 interrupts p0.15-p0.30 */
|
||||
|
||||
# define LPC17_VALID_GPIOINT0H (0x7fff8000ull)
|
||||
# define LPC17_VALID_SHIFT0H (15)
|
||||
# define LPC17_VALID_FIRST0H (LPC17_VALID_FIRST0L+LPC17_VALID_NIRQS0L)
|
||||
|
||||
# define LPC17_IRQ_P0p15 (LPC17_VALID_FIRST0H+0)
|
||||
# define LPC17_IRQ_P0p16 (LPC17_VALID_FIRST0H+1)
|
||||
# define LPC17_IRQ_P0p17 (LPC17_VALID_FIRST0H+2)
|
||||
# define LPC17_IRQ_P0p18 (LPC17_VALID_FIRST0H+3)
|
||||
# define LPC17_IRQ_P0p19 (LPC17_VALID_FIRST0H+4)
|
||||
# define LPC17_IRQ_P0p20 (LPC17_VALID_FIRST0H+5)
|
||||
# define LPC17_IRQ_P0p21 (LPC17_VALID_FIRST0H+6)
|
||||
# define LPC17_IRQ_P0p22 (LPC17_VALID_FIRST0H+7)
|
||||
# define LPC17_IRQ_P0p23 (LPC17_VALID_FIRST0H+8)
|
||||
# define LPC17_IRQ_P0p24 (LPC17_VALID_FIRST0H+9)
|
||||
# define LPC17_IRQ_P0p25 (LPC17_VALID_FIRST0H+10)
|
||||
# define LPC17_IRQ_P0p26 (LPC17_VALID_FIRST0H+11)
|
||||
# define LPC17_IRQ_P0p27 (LPC17_VALID_FIRST0H+12)
|
||||
# define LPC17_IRQ_P0p28 (LPC17_VALID_FIRST0H+13)
|
||||
# define LPC17_IRQ_P0p29 (LPC17_VALID_FIRST0H+14)
|
||||
# define LPC17_IRQ_P0p30 (LPC17_VALID_FIRST0H+15)
|
||||
# define LPC17_VALID_NIRQS0H (16)
|
||||
|
||||
/* Set 3: 14 interrupts p2.0-p2.13 */
|
||||
|
||||
# define LPC17_VALID_GPIOINT2 (0x00003ffful)
|
||||
# define LPC17_VALID_SHIFT2 (0)
|
||||
# define LPC17_VALID_FIRST2 (LPC17_VALID_FIRST0H+LPC17_VALID_NIRQS0H)
|
||||
|
||||
# define LPC17_IRQ_P2p0 (LPC17_VALID_FIRST2+0)
|
||||
# define LPC17_IRQ_P2p1 (LPC17_VALID_FIRST2+1)
|
||||
# define LPC17_IRQ_P2p2 (LPC17_VALID_FIRST2+2)
|
||||
# define LPC17_IRQ_P2p3 (LPC17_VALID_FIRST2+3)
|
||||
# define LPC17_IRQ_P2p4 (LPC17_VALID_FIRST2+4)
|
||||
# define LPC17_IRQ_P2p5 (LPC17_VALID_FIRST2+5)
|
||||
# define LPC17_IRQ_P2p6 (LPC17_VALID_FIRST2+6)
|
||||
# define LPC17_IRQ_P2p7 (LPC17_VALID_FIRST2+7)
|
||||
# define LPC17_IRQ_P2p8 (LPC17_VALID_FIRST2+8)
|
||||
# define LPC17_IRQ_P2p9 (LPC17_VALID_FIRST2+9)
|
||||
# define LPC17_IRQ_P2p10 (LPC17_VALID_FIRST2+10)
|
||||
# define LPC17_IRQ_P2p11 (LPC17_VALID_FIRST2+11)
|
||||
# define LPC17_IRQ_P2p12 (LPC17_VALID_FIRST2+12)
|
||||
# define LPC17_IRQ_P2p13 (LPC17_VALID_FIRST2+13)
|
||||
# define LPC17_VALID_NIRQS2 (14)
|
||||
# define LPC17_NGPIOAIRQS (LPC17_VALID_NIRQS0L+LPC17_VALID_NIRQS0H+LPC17_VALID_NIRQS2)
|
||||
#else
|
||||
# define LPC17_NGPIOAIRQS (0)
|
||||
#endif
|
||||
|
||||
/* Total number of IRQ numbers */
|
||||
|
||||
#define NR_IRQS (LPC17_IRQ_EXTINT+LPC17_IRQ_NEXTINT+LPC17_NGPIOAIRQS)
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Inline functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_INCLUDE_LPC17XX_LPC176X_IRQ_H */
|
||||
|
||||
@@ -1,291 +0,0 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/include/lpc17xxx/lpc178x_irq.h
|
||||
*
|
||||
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
|
||||
* Authors: Rommel Marcelo
|
||||
* Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/* This file should never be included directed but, rather,
|
||||
* only indirectly through nuttx/irq.h
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_ARM_INCLUDE_LPC17XX_LPC178X_IRQ_H
|
||||
#define __ARCH_ARM_INCLUDE_LPC17XX_LPC178X_IRQ_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* IRQ numbers. The IRQ number corresponds vector number and hence map
|
||||
* directly to bits in the NVIC. This does, however, waste several words of
|
||||
* memory in the IRQ to handle mapping tables.
|
||||
*/
|
||||
|
||||
/* External interrupts (vectors >= 16) */
|
||||
|
||||
#define LPC17_IRQ_WDT (LPC17_IRQ_EXTINT+0) /* WDT Watchdog Interrupt (WDINT) */
|
||||
#define LPC17_IRQ_TMR0 (LPC17_IRQ_EXTINT+1) /* Timer 0 Match 0 - 1 (MR0, MR1)
|
||||
* Capture 0 - 1 (CR0, CR1) */
|
||||
#define LPC17_IRQ_TMR1 (LPC17_IRQ_EXTINT+2) /* Timer 1 Match 0 - 2 (MR0, MR1, MR2)
|
||||
* Capture 0 - 1 (CR0, CR1) */
|
||||
#define LPC17_IRQ_TMR2 (LPC17_IRQ_EXTINT+3) /* Timer 2 Match 0-3
|
||||
* Capture 0-1 */
|
||||
#define LPC17_IRQ_TMR3 (LPC17_IRQ_EXTINT+4) /* Timer 3 Match 0-3
|
||||
* Capture 0-1 */
|
||||
#define LPC17_IRQ_UART0 (LPC17_IRQ_EXTINT+5) /* UART 0 Rx Line Status (RLS)
|
||||
* Transmit Holding Register Empty (THRE)
|
||||
* Rx Data Available (RDA)
|
||||
* Character Time-out Indicator (CTI)
|
||||
* End of Auto-Baud (ABEO)
|
||||
* Auto-Baud Time-Out (ABTO) */
|
||||
#define LPC17_IRQ_UART1 (LPC17_IRQ_EXTINT+6) /* UART 1 Rx Line Status (RLS)
|
||||
* Transmit Holding Register Empty (THRE)
|
||||
* Rx Data Available (RDA)
|
||||
* Character Time-out Indicator (CTI)
|
||||
* Modem Control Change
|
||||
* End of Auto-Baud (ABEO)
|
||||
* Auto-Baud Time-Out (ABTO) */
|
||||
#define LPC17_IRQ_UART2 (LPC17_IRQ_EXTINT+7) /* UART 2 Rx Line Status (RLS)
|
||||
* Transmit Holding Register Empty (THRE)
|
||||
* Rx Data Available (RDA)
|
||||
* Character Time-out Indicator (CTI)
|
||||
* End of Auto-Baud (ABEO)
|
||||
* Auto-Baud Time-Out (ABTO) */
|
||||
#define LPC17_IRQ_UART3 (LPC17_IRQ_EXTINT+8) /* UART 3 Rx Line Status (RLS)
|
||||
* Transmit Holding Register Empty (THRE)
|
||||
* Rx Data Available (RDA)
|
||||
* Character Time-out Indicator (CTI)
|
||||
* End of Auto-Baud (ABEO)
|
||||
* Auto-Baud Time-Out (ABTO) */
|
||||
#define LPC17_IRQ_PWM1 (LPC17_IRQ_EXTINT+9) /* PWM1 Match 0 - 6 of PWM1
|
||||
* Capture 0-1 of PWM1 */
|
||||
#define LPC17_IRQ_I2C0 (LPC17_IRQ_EXTINT+10) /* I2C0 SI (state change) */
|
||||
#define LPC17_IRQ_I2C1 (LPC17_IRQ_EXTINT+11) /* I2C1 SI (state change) */
|
||||
#define LPC17_IRQ_I2C2 (LPC17_IRQ_EXTINT+12) /* I2C2 SI (state change) */
|
||||
#define LPC17_IRQ_RESERVED29 (LPC17_IRQ_EXTINT+13) /* Unused */
|
||||
#define LPC17_IRQ_SSP0 (LPC17_IRQ_EXTINT+14) /* SSP0 Tx FIFO half empty of SSP0
|
||||
* Rx FIFO half full of SSP0
|
||||
* Rx Timeout of SSP0
|
||||
* Rx Overrun of SSP0 */
|
||||
#define LPC17_IRQ_SSP1 (LPC17_IRQ_EXTINT+15) /* SSP 1 Tx FIFO half empty
|
||||
* Rx FIFO half full
|
||||
* Rx Timeout
|
||||
* Rx Overrun */
|
||||
#define LPC17_IRQ_PLL0 (LPC17_IRQ_EXTINT+16) /* PLL0 (Main PLL) PLL0 Lock (PLOCK0) */
|
||||
#define LPC17_IRQ_RTC (LPC17_IRQ_EXTINT+17) /* RTC Counter Increment (RTCCIF)
|
||||
* Alarm (RTCALF) */
|
||||
#define LPC17_IRQ_EINT0 (LPC17_IRQ_EXTINT+18) /* External Interrupt 0 (EINT0) */
|
||||
#define LPC17_IRQ_EINT1 (LPC17_IRQ_EXTINT+19) /* External Interrupt 1 (EINT1) */
|
||||
#define LPC17_IRQ_EINT2 (LPC17_IRQ_EXTINT+20) /* External Interrupt 2 (EINT2) */
|
||||
#define LPC17_IRQ_EINT3 (LPC17_IRQ_EXTINT+21) /* External Interrupt 3 (EINT3)
|
||||
* Note: EINT3 channel is shared with GPIO interrupts */
|
||||
#define LPC17_IRQ_ADC (LPC17_IRQ_EXTINT+22) /* ADC A/D Converter end of conversion */
|
||||
#define LPC17_IRQ_BOD (LPC17_IRQ_EXTINT+23) /* BOD Brown Out detect */
|
||||
#define LPC17_IRQ_USB (LPC17_IRQ_EXTINT+24) /* USB USB_INT_REQ_LP, USB_INT_REQ_HP,
|
||||
* USB_INT_REQ_DMA */
|
||||
#define LPC17_IRQ_CAN (LPC17_IRQ_EXTINT+25) /* CAN CAN Common, CAN 0 Tx, CAN 0 Rx,
|
||||
* CAN 1 Tx, CAN 1 Rx */
|
||||
#define LPC17_IRQ_GPDMA (LPC17_IRQ_EXTINT+26) /* GPDMA IntStatus of DMA channel 0,
|
||||
* IntStatus of DMA channel 1 */
|
||||
#define LPC17_IRQ_I2S (LPC17_IRQ_EXTINT+27) /* I2S irq, dmareq1, dmareq2 */
|
||||
#define LPC17_IRQ_ETH (LPC17_IRQ_EXTINT+28) /* Ethernet WakeupInt, SoftInt, TxDoneInt,
|
||||
* TxFinishedInt, TxErrorInt,* TxUnderrunInt,
|
||||
* RxDoneInt, RxFinishedInt, RxErrorInt,
|
||||
* RxOverrunInt */
|
||||
#define LPC17_IRQ_MCI (LPC17_IRQ_EXTINT+29) /* MCI SD Card Interface */
|
||||
#define LPC17_IRQ_MCPWM (LPC17_IRQ_EXTINT+30) /* Motor Control PWM IPER[2:0], IPW[2:0],
|
||||
* ICAP[2:0], FES */
|
||||
#define LPC17_IRQ_QEI (LPC17_IRQ_EXTINT+31) /* Quadrature Encoder INX_Int, TIM_Int, VELC_Int,
|
||||
* DIR_Int, ERR_Int, ENCLK_Int, POS0_Int, POS1_Int
|
||||
* POS2_Int, REV_Int, POS0REV_Int, OS1REV_Int,
|
||||
* POS2REV_Int */
|
||||
#define LPC17_IRQ_PLL1 (LPC17_IRQ_EXTINT+32) /* PLL1 (USB PLL) PLL1 Lock (PLOCK1) */
|
||||
#define LPC17_IRQ_USBACT (LPC17_IRQ_EXTINT+33) /* USB Activity Interrupt USB_NEED_CLK */
|
||||
#define LPC17_IRQ_CANACT (LPC17_IRQ_EXTINT+34) /* CAN Activity Interrupt CAN1WAKE, CAN2WAKE */
|
||||
#define LPC17_IRQ_UART4 (LPC17_IRQ_EXTINT+35) /* UART 4 Rx Line Status (RLS)
|
||||
* Transmit Holding Register Empty (THRE)
|
||||
* Rx Data Available (RDA)
|
||||
* Character Time-out Indicator (CTI)
|
||||
* End of Auto-Baud (ABEO)
|
||||
* Auto-Baud Time-Out (ABTO) */
|
||||
#define LPC17_IRQ_SSP2 (LPC17_IRQ_EXTINT+36) /* SSP2 Tx FIFO half empty of SSP2
|
||||
* Rx FIFO half full of SSP2
|
||||
* Rx Timeout of SSP2
|
||||
* Rx Overrun of SSP2 */
|
||||
#define LPC17_IRQ_LCD (LPC17_IRQ_EXTINT+37) /* LCD interrupt
|
||||
* BER, VCompI, LNBUI, FUFI, CrsrI */
|
||||
#define LPC17_IRQ_GPIO (LPC17_IRQ_EXTINT+38) /* GPIO Interrupt
|
||||
* P0xREI, P2xREI, P0xFEI, P2xFEI */
|
||||
#define LPC17_IRQ_PWM0 (LPC17_IRQ_EXTINT+39) /* PWM0 Match 0 - 6 of PWM0
|
||||
* Capture 0-1 of PWM0 */
|
||||
#define LPC17_IRQ_EEPROM (LPC17_IRQ_EXTINT+40) /* EEPROM Interrupt
|
||||
* EE_PROG_DONE, EE_RW_DONE */
|
||||
#define LPC17_IRQ_NEXTINT (41)
|
||||
#define LPC17_IRQ_NIRQS (LPC17_IRQ_EXTINT+LPC17_IRQ_NEXTINT)
|
||||
|
||||
/* GPIO interrupts. The LPC177x_8x supports several interrupts on ports 0 and
|
||||
* 2 (only). We go through some special efforts to keep the number of IRQs
|
||||
* to a minimum in this sparse interrupt case.
|
||||
*
|
||||
* 31 interrupts on Port 0: p0.0 - p0.30
|
||||
* 31 interrupts on Port 2: p2.0 - p2.30
|
||||
* --
|
||||
* 42
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_LPC17_GPIOIRQ
|
||||
# define LPC17_VALID_GPIOINT0 (0xfffffffful) /* GPIO port 0 interrupt set */
|
||||
# define LPC17_VALID_GPIOINT2 (0xfffffffful) /* GPIO port 2 interrupt set */
|
||||
|
||||
/* Set 1: 16 interrupts p0.0-p0.15 */
|
||||
|
||||
# define LPC17_VALID_SHIFT0L (0)
|
||||
# define LPC17_VALID_FIRST0L (LPC17_IRQ_EXTINT+LPC17_IRQ_NEXTINT)
|
||||
|
||||
# define LPC17_IRQ_P0p0 (LPC17_VALID_FIRST0L+0)
|
||||
# define LPC17_IRQ_P0p1 (LPC17_VALID_FIRST0L+1)
|
||||
# define LPC17_IRQ_P0p2 (LPC17_VALID_FIRST0L+2)
|
||||
# define LPC17_IRQ_P0p3 (LPC17_VALID_FIRST0L+3)
|
||||
# define LPC17_IRQ_P0p4 (LPC17_VALID_FIRST0L+4)
|
||||
# define LPC17_IRQ_P0p5 (LPC17_VALID_FIRST0L+5)
|
||||
# define LPC17_IRQ_P0p6 (LPC17_VALID_FIRST0L+6)
|
||||
# define LPC17_IRQ_P0p7 (LPC17_VALID_FIRST0L+7)
|
||||
# define LPC17_IRQ_P0p8 (LPC17_VALID_FIRST0L+8)
|
||||
# define LPC17_IRQ_P0p9 (LPC17_VALID_FIRST0L+9)
|
||||
# define LPC17_IRQ_P0p10 (LPC17_VALID_FIRST0L+10)
|
||||
# define LPC17_IRQ_P0p11 (LPC17_VALID_FIRST0L+11)
|
||||
# define LPC17_IRQ_P0p12 (LPC17_VALID_FIRST0L+12)
|
||||
# define LPC17_IRQ_P0p13 (LPC17_VALID_FIRST0L+13)
|
||||
# define LPC17_IRQ_P0p14 (LPC17_VALID_FIRST0L+14)
|
||||
# define LPC17_IRQ_P0p15 (LPC17_VALID_FIRST0L+15)
|
||||
# define LPC17_VALID_NIRQS0L (16)
|
||||
|
||||
/* Set 2: 16 interrupts p0.16-p0.31 */
|
||||
|
||||
# define LPC17_VALID_SHIFT0H (16)
|
||||
# define LPC17_VALID_FIRST0H (LPC17_VALID_FIRST0L+LPC17_VALID_NIRQS0L)
|
||||
|
||||
# define LPC17_IRQ_P0p16 (LPC17_VALID_FIRST0H+0)
|
||||
# define LPC17_IRQ_P0p17 (LPC17_VALID_FIRST0H+1)
|
||||
# define LPC17_IRQ_P0p18 (LPC17_VALID_FIRST0H+2)
|
||||
# define LPC17_IRQ_P0p19 (LPC17_VALID_FIRST0H+3)
|
||||
# define LPC17_IRQ_P0p20 (LPC17_VALID_FIRST0H+4)
|
||||
# define LPC17_IRQ_P0p21 (LPC17_VALID_FIRST0H+5)
|
||||
# define LPC17_IRQ_P0p22 (LPC17_VALID_FIRST0H+6)
|
||||
# define LPC17_IRQ_P0p23 (LPC17_VALID_FIRST0H+7)
|
||||
# define LPC17_IRQ_P0p24 (LPC17_VALID_FIRST0H+8)
|
||||
# define LPC17_IRQ_P0p25 (LPC17_VALID_FIRST0H+9)
|
||||
# define LPC17_IRQ_P0p26 (LPC17_VALID_FIRST0H+10)
|
||||
# define LPC17_IRQ_P0p27 (LPC17_VALID_FIRST0H+11)
|
||||
# define LPC17_IRQ_P0p28 (LPC17_VALID_FIRST0H+12)
|
||||
# define LPC17_IRQ_P0p29 (LPC17_VALID_FIRST0H+13)
|
||||
# define LPC17_IRQ_P0p30 (LPC17_VALID_FIRST0H+14)
|
||||
# define LPC17_IRQ_P0p31 (LPC17_VALID_FIRST0H+15)
|
||||
# define LPC17_VALID_NIRQS0H (16)
|
||||
|
||||
/* Set 3: 16 interrupts p2.0-p2.15 */
|
||||
|
||||
# define LPC17_VALID_SHIFT2L (0)
|
||||
# define LPC17_VALID_FIRST2L (LPC17_VALID_FIRST0H+LPC17_VALID_NIRQS0H)
|
||||
|
||||
# define LPC17_IRQ_P2p0 (LPC17_VALID_FIRST2L+0)
|
||||
# define LPC17_IRQ_P2p1 (LPC17_VALID_FIRST2L+1)
|
||||
# define LPC17_IRQ_P2p2 (LPC17_VALID_FIRST2L+2)
|
||||
# define LPC17_IRQ_P2p3 (LPC17_VALID_FIRST2L+3)
|
||||
# define LPC17_IRQ_P2p4 (LPC17_VALID_FIRST2L+4)
|
||||
# define LPC17_IRQ_P2p5 (LPC17_VALID_FIRST2L+5)
|
||||
# define LPC17_IRQ_P2p6 (LPC17_VALID_FIRST2L+6)
|
||||
# define LPC17_IRQ_P2p7 (LPC17_VALID_FIRST2L+7)
|
||||
# define LPC17_IRQ_P2p8 (LPC17_VALID_FIRST2L+8)
|
||||
# define LPC17_IRQ_P2p9 (LPC17_VALID_FIRST2L+9)
|
||||
# define LPC17_IRQ_P2p10 (LPC17_VALID_FIRST2L+10)
|
||||
# define LPC17_IRQ_P2p11 (LPC17_VALID_FIRST2L+11)
|
||||
# define LPC17_IRQ_P2p12 (LPC17_VALID_FIRST2L+12)
|
||||
# define LPC17_IRQ_P2p13 (LPC17_VALID_FIRST2L+13)
|
||||
# define LPC17_IRQ_P2p14 (LPC17_VALID_FIRST2L+14)
|
||||
# define LPC17_IRQ_P2p15 (LPC17_VALID_FIRST2L+15)
|
||||
# define LPC17_VALID_NIRQS2L (16)
|
||||
|
||||
/* Set 4: 16 interrupts p2.16 - p2.31 */
|
||||
|
||||
# define LPC17_VALID_SHIFT2H (16)
|
||||
# define LPC17_VALID_FIRST2H (LPC17_VALID_FIRST2L+LPC17_VALID_NIRQS2L)
|
||||
|
||||
# define LPC17_IRQ_P2p16 (LPC17_VALID_FIRST2H+0)
|
||||
# define LPC17_IRQ_P2p17 (LPC17_VALID_FIRST2H+1)
|
||||
# define LPC17_IRQ_P2p18 (LPC17_VALID_FIRST2H+2)
|
||||
# define LPC17_IRQ_P2p19 (LPC17_VALID_FIRST2H+3)
|
||||
# define LPC17_IRQ_P2p20 (LPC17_VALID_FIRST2H+4)
|
||||
# define LPC17_IRQ_P2p21 (LPC17_VALID_FIRST2H+5)
|
||||
# define LPC17_IRQ_P2p22 (LPC17_VALID_FIRST2H+6)
|
||||
# define LPC17_IRQ_P2p23 (LPC17_VALID_FIRST2H+7)
|
||||
# define LPC17_IRQ_P2p24 (LPC17_VALID_FIRST2H+8)
|
||||
# define LPC17_IRQ_P2p25 (LPC17_VALID_FIRST2H+9)
|
||||
# define LPC17_IRQ_P2p26 (LPC17_VALID_FIRST2H+10)
|
||||
# define LPC17_IRQ_P2p27 (LPC17_VALID_FIRST2H+11)
|
||||
# define LPC17_IRQ_P2p28 (LPC17_VALID_FIRST2H+12)
|
||||
# define LPC17_IRQ_P2p29 (LPC17_VALID_FIRST2H+13)
|
||||
# define LPC17_IRQ_P2p30 (LPC17_VALID_FIRST2H+14)
|
||||
# define LPC17_IRQ_P2p31 (LPC17_VALID_FIRST2H+15)
|
||||
# define LPC17_VALID_NIRQS2H (16)
|
||||
|
||||
# define LPC17_NGPIOAIRQS (LPC17_VALID_NIRQS0L+LPC17_VALID_NIRQS0H+LPC17_VALID_NIRQS2L+LPC17_VALID_NIRQS2H)
|
||||
#else
|
||||
# define LPC17_NGPIOAIRQS (0)
|
||||
#endif
|
||||
|
||||
/* Total number of IRQ numbers */
|
||||
|
||||
#define NR_IRQS (LPC17_IRQ_EXTINT+LPC17_IRQ_NEXTINT+LPC17_NGPIOAIRQS)
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Inline functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_INCLUDE_LPC17XX_LPC178X_IRQ_H */
|
||||
|
||||
468
arch/arm/include/lpc17xx_40xx/chip.h
Normal file
468
arch/arm/include/lpc17xx_40xx/chip.h
Normal file
@@ -0,0 +1,468 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/include/lpc17xx_40xx/chip.h
|
||||
*
|
||||
* Copyright (C) 2010-2011, 2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* with LPC178x support from Rommel Marcelo
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_INCLUDE_LPC17XX_40XX_CHIP_H
|
||||
#define __ARCH_ARM_INCLUDE_LPC17XX_40XX_CHIP_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Get customizations for each supported chip */
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_LPC1751)
|
||||
# define LPC176x 1 /* LPC175/6 family */
|
||||
# undef LPC178x_40xx /* Not LPC177/8 or LPC40xx family */
|
||||
# define LPC17_40_FLASH_SIZE (32*1024) /* 32Kb */
|
||||
# define LPC17_40_SRAM_SIZE (8*1024) /* 8Kb */
|
||||
# define LPC17_40_CPUSRAM_SIZE (8*1024)
|
||||
# undef LPC17_40_HAVE_BANK0 /* No AHB SRAM bank 0 */
|
||||
# undef LPC17_40_HAVE_BANK1 /* No AHB SRAM bank 1 */
|
||||
# define LPC17_40_NETHCONTROLLERS 0 /* No Ethernet controller */
|
||||
# define LPC17_40_NUSBHOST 0 /* No USB host controller */
|
||||
# define LPC17_40_NUSBOTG 0 /* No USB OTG controller */
|
||||
# define LPC17_40_NUSBDEV 1 /* One USB device controller */
|
||||
# define LPC17_40_NCAN 1 /* One CAN controller */
|
||||
# define LPC17_40_NI2S 0 /* No I2S modules */
|
||||
# define LPC17_40_NDAC 0 /* No DAC module */
|
||||
#elif defined(CONFIG_ARCH_CHIP_LPC1752)
|
||||
# define LPC176x 1 /* LPC175/6 family */
|
||||
# undef LPC178x_40xx /* Not LPC177/8 or LPC40xx family */
|
||||
# define LPC17_40_FLASH_SIZE (64*1024) /* 65Kb */
|
||||
# define LPC17_40_SRAM_SIZE (16*1024) /* 16Kb */
|
||||
# define LPC17_40_CPUSRAM_SIZE (16*1024)
|
||||
# undef LPC17_40_HAVE_BANK0 /* No AHB SRAM bank 0 */
|
||||
# undef LPC17_40_HAVE_BANK1 /* No AHB SRAM bank 1 */
|
||||
# define LPC17_40_NETHCONTROLLERS 0 /* No Ethernet controller */
|
||||
# define LPC17_40_NUSBHOST 0 /* No USB host controller */
|
||||
# define LPC17_40_NUSBOTG 0 /* No USB OTG controller */
|
||||
# define LPC17_40_NUSBDEV 1 /* One USB device controller */
|
||||
# define LPC17_40_NCAN 1 /* One CAN controller */
|
||||
# define LPC17_40_NI2S 0 /* No I2S modules */
|
||||
# define LPC17_40_NDAC 0 /* No DAC module */
|
||||
#elif defined(CONFIG_ARCH_CHIP_LPC1754)
|
||||
# define LPC176x 1 /* LPC175/6 family */
|
||||
# undef LPC178x_40xx /* Not LPC177/8 or LPC40xx family */
|
||||
# define LPC17_40_FLASH_SIZE (128*1024) /* 128Kb */
|
||||
# define LPC17_40_SRAM_SIZE (32*1024) /* 32Kb */
|
||||
# define LPC17_40_CPUSRAM_SIZE (16*1024)
|
||||
# define LPC17_40_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */
|
||||
# undef LPC17_40_HAVE_BANK1 /* No AHB SRAM bank 1 */
|
||||
# define LPC17_40_NETHCONTROLLERS 0 /* No Ethernet controller */
|
||||
# define LPC17_40_NUSBHOST 1 /* One USB host controller */
|
||||
# define LPC17_40_NUSBOTG 1 /* One USB OTG controller */
|
||||
# define LPC17_40_NUSBDEV 1 /* One USB device controller */
|
||||
# define LPC17_40_NCAN 1 /* One CAN controller */
|
||||
# define LPC17_40_NI2S 0 /* No I2S modules */
|
||||
# define LPC17_40_NDAC 1 /* One DAC module */
|
||||
#elif defined(CONFIG_ARCH_CHIP_LPC1756)
|
||||
# define LPC176x 1 /* LPC175/6 family */
|
||||
# undef LPC178x_40xx /* Not LPC177/8 or LPC40xx family */
|
||||
# define LPC17_40_FLASH_SIZE (256*1024) /* 256Kb */
|
||||
# define LPC17_40_SRAM_SIZE (32*1024) /* 32Kb */
|
||||
# define LPC17_40_CPUSRAM_SIZE (16*1024)
|
||||
# define LPC17_40_HAVE_BANK0 1 /* No AHB SRAM bank 0 */
|
||||
# undef LPC17_40_HAVE_BANK1 /* No AHB SRAM bank 1 */
|
||||
# define LPC17_40_NETHCONTROLLERS 0 /* No Ethernet controller */
|
||||
# define LPC17_40_NUSBHOST 1 /* One USB host controller */
|
||||
# define LPC17_40_NUSBOTG 1 /* One USB OTG controller */
|
||||
# define LPC17_40_NUSBDEV 1 /* One USB device controller */
|
||||
# define LPC17_40_NCAN 2 /* Two CAN controllers */
|
||||
# define LPC17_40_NI2S 1 /* One I2S module */
|
||||
# define LPC17_40_NDAC 1 /* One DAC module */
|
||||
#elif defined(CONFIG_ARCH_CHIP_LPC1758)
|
||||
# define LPC176x 1 /* LPC175/6 family */
|
||||
# undef LPC178x_40xx /* Not LPC177/8 or LPC40xx family */
|
||||
# define LPC17_40_FLASH_SIZE (512*1024) /* 512Kb */
|
||||
# define LPC17_40_SRAM_SIZE (64*1024) /* 64Kb */
|
||||
# define LPC17_40_CPUSRAM_SIZE (32*1024)
|
||||
# define LPC17_40_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */
|
||||
# define LPC17_40_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */
|
||||
# define LPC17_40_NETHCONTROLLERS 1 /* One Ethernet controller */
|
||||
# define LPC17_40_NUSBHOST 1 /* One USB host controller */
|
||||
# define LPC17_40_NUSBOTG 1 /* One USB OTG controller */
|
||||
# define LPC17_40_NUSBDEV 1 /* One USB device controller */
|
||||
# define LPC17_40_NCAN 2 /* Two CAN controllers */
|
||||
# define LPC17_40_NI2S 1 /* One I2S module */
|
||||
# define LPC17_40_NDAC 1 /* One DAC module */
|
||||
#elif defined(CONFIG_ARCH_CHIP_LPC1759)
|
||||
# define LPC176x 1 /* LPC175/6 family */
|
||||
# undef LPC178x_40xx /* Not LPC177/8 or LPC40xx family */
|
||||
# define LPC17_40_FLASH_SIZE (512*1024) /* 512Kb */
|
||||
# define LPC17_40_SRAM_SIZE (64*1024) /* 64Kb */
|
||||
# define LPC17_40_CPUSRAM_SIZE (32*1024)
|
||||
# define LPC17_40_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */
|
||||
# define LPC17_40_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */
|
||||
# define LPC17_40_NETHCONTROLLERS 0 /* No Ethernet controller */
|
||||
# define LPC17_40_NUSBHOST 1 /* One USB host controller */
|
||||
# define LPC17_40_NUSBOTG 1 /* One USB OTG controller */
|
||||
# define LPC17_40_NUSBDEV 1 /* One USB device controller */
|
||||
# define LPC17_40_NCAN 2 /* Two CAN controllers */
|
||||
# define LPC17_40_NI2S 1 /* One I2S module */
|
||||
# define LPC17_40_NDAC 1 /* One DAC module */
|
||||
#elif defined(CONFIG_ARCH_CHIP_LPC1764)
|
||||
# define LPC176x 1 /* LPC175/6 family */
|
||||
# undef LPC178x_40xx /* Not LPC177/8 or LPC40xx family */
|
||||
# define LPC17_40_FLASH_SIZE (128*1024) /* 128Kb */
|
||||
# define LPC17_40_SRAM_SIZE (32*1024) /* 32Kb */
|
||||
# define LPC17_40_CPUSRAM_SIZE (16*1024)
|
||||
# define LPC17_40_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */
|
||||
# undef LPC17_40_HAVE_BANK1 /* No AHB SRAM bank 1 */
|
||||
# define LPC17_40_NETHCONTROLLERS 1 /* One Ethernet controller */
|
||||
# define LPC17_40_NUSBHOST 0 /* No USB host controller */
|
||||
# define LPC17_40_NUSBOTG 0 /* No USB OTG controller */
|
||||
# define LPC17_40_NUSBDEV 1 /* One USB device controller */
|
||||
# define LPC17_40_NCAN 2 /* Two CAN controllers */
|
||||
# define LPC17_40_NI2S 0 /* No I2S modules */
|
||||
# define LPC17_40_NDAC 0 /* No DAC module */
|
||||
#elif defined(CONFIG_ARCH_CHIP_LPC1765)
|
||||
# define LPC176x 1 /* LPC175/6 family */
|
||||
# undef LPC178x_40xx /* Not LPC177/8 or LPC40xx family */
|
||||
# define LPC17_40_FLASH_SIZE (256*1024) /* 256Kb */
|
||||
# define LPC17_40_SRAM_SIZE (64*1024) /* 64Kb */
|
||||
# define LPC17_40_CPUSRAM_SIZE (32*1024)
|
||||
# define LPC17_40_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */
|
||||
# define LPC17_40_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */
|
||||
# define LPC17_40_NETHCONTROLLERS 0 /* No Ethernet controller */
|
||||
# define LPC17_40_NUSBHOST 1 /* One USB host controller */
|
||||
# define LPC17_40_NUSBOTG 1 /* One USB OTG controller */
|
||||
# define LPC17_40_NUSBDEV 1 /* One USB device controller */
|
||||
# define LPC17_40_NCAN 2 /* Two CAN controllers */
|
||||
# define LPC17_40_NI2S 1 /* One I2S module */
|
||||
# define LPC17_40_NDAC 1 /* One DAC module */
|
||||
#elif defined(CONFIG_ARCH_CHIP_LPC1766)
|
||||
# define LPC176x 1 /* LPC175/6 family */
|
||||
# undef LPC178x_40xx /* Not LPC177/8 or LPC40xx family */
|
||||
# define LPC17_40_FLASH_SIZE (256*1024) /* 256Kb */
|
||||
# define LPC17_40_SRAM_SIZE (64*1024) /* 64Kb */
|
||||
# define LPC17_40_CPUSRAM_SIZE (32*1024)
|
||||
# define LPC17_40_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */
|
||||
# define LPC17_40_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */
|
||||
# define LPC17_40_NETHCONTROLLERS 1 /* One Ethernet controller */
|
||||
# define LPC17_40_NUSBHOST 1 /* One USB host controller */
|
||||
# define LPC17_40_NUSBOTG 1 /* One USB OTG controller */
|
||||
# define LPC17_40_NUSBDEV 1 /* One USB device controller */
|
||||
# define LPC17_40_NCAN 2 /* Two CAN controllers */
|
||||
# define LPC17_40_NI2S 1 /* One I2S module */
|
||||
# define LPC17_40_NDAC 1 /* One DAC module */
|
||||
#elif defined(CONFIG_ARCH_CHIP_LPC1767)
|
||||
# define LPC176x 1 /* LPC175/6 family */
|
||||
# undef LPC178x_40xx /* Not LPC177/8 or LPC40xx family */
|
||||
# define LPC17_40_FLASH_SIZE (512*1024) /* 512Kb */
|
||||
# define LPC17_40_SRAM_SIZE (64*1024) /* 64Kb */
|
||||
# define LPC17_40_CPUSRAM_SIZE (32*1024)
|
||||
# define LPC17_40_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */
|
||||
# define LPC17_40_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */
|
||||
# define LPC17_40_NETHCONTROLLERS 1 /* One Ethernet controller */
|
||||
# define LPC17_40_NUSBHOST 0 /* No USB host controller */
|
||||
# define LPC17_40_NUSBOTG 0 /* No USB OTG controller */
|
||||
# define LPC17_40_NUSBDEV 0 /* No USB device controller */
|
||||
# define LPC17_40_NCAN 0 /* No CAN controllers */
|
||||
# define LPC17_40_NI2S 1 /* One I2S module */
|
||||
# define LPC17_40_NDAC 1 /* One DAC module */
|
||||
#elif defined(CONFIG_ARCH_CHIP_LPC1769) || defined(CONFIG_ARCH_CHIP_LPC1768)
|
||||
# define LPC176x 1 /* LPC175/6 family */
|
||||
# undef LPC178x_40xx /* Not LPC177/8 or LPC40xx family */
|
||||
# define LPC17_40_FLASH_SIZE (512*1024) /* 512Kb */
|
||||
# define LPC17_40_SRAM_SIZE (64*1024) /* 64Kb */
|
||||
# define LPC17_40_CPUSRAM_SIZE (32*1024)
|
||||
# define LPC17_40_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */
|
||||
# define LPC17_40_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */
|
||||
# define LPC17_40_NETHCONTROLLERS 1 /* One Ethernet controller */
|
||||
# define LPC17_40_NUSBHOST 1 /* One USB host controller */
|
||||
# define LPC17_40_NUSBOTG 1 /* One USB OTG controller */
|
||||
# define LPC17_40_NUSBDEV 1 /* One USB device controller */
|
||||
# define LPC17_40_NCAN 2 /* Two CAN controllers */
|
||||
# define LPC17_40_NI2S 1 /* One I2S module */
|
||||
# define LPC17_40_NDAC 1 /* One DAC module */
|
||||
#elif defined(CONFIG_ARCH_CHIP_LPC1773)
|
||||
# undef LPC176x /* Not LPC175/6 family */
|
||||
# define LPC178x_40xx 1 /* LPC177/8 or LPC40xx family */
|
||||
# define LPC17_40_FLASH_SIZE (128*1024) /* 128Kb */
|
||||
# define LPC17_40_SRAM_SIZE (40*1024) /* 40Kb */
|
||||
# define LPC17_40_CPUSRAM_SIZE (32*1024)
|
||||
# define LPC17_40_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */
|
||||
# undef LPC17_40_HAVE_BANK1 /* No Peripheral SRAM bank 1 */
|
||||
# define LPC17_40_NETHCONTROLLERS 1 /* One Ethernet controller */
|
||||
# undef LPC17_40_NUSBHOST /* No USB host controller */
|
||||
# undef LPC17_40_NUSBOTG /* No USB OTG controller */
|
||||
# define LPC17_40_NUSBDEV 1 /* One USB device controller */
|
||||
# define LPC17_40_HAVE_SPIFI 1 /* Have SPIFI interface */
|
||||
# undef LPC17_40_HAVE_LCD /* No LCD controller */
|
||||
# undef LPC17_40_HAVE_QEI /* No QEI interface */
|
||||
# undef LPC17_40_HAVE_SD /* No SD controller */
|
||||
#elif defined(CONFIG_ARCH_CHIP_LPC1774)
|
||||
# undef LPC176x /* Not LPC175/6 family */
|
||||
# define LPC178x_40xx 1 /* LPC177/8 or LPC40xx family */
|
||||
# define LPC17_40_FLASH_SIZE (128*1024) /* 128Kb */
|
||||
# define LPC17_40_SRAM_SIZE (40*1024) /* 40Kb */
|
||||
# define LPC17_40_CPUSRAM_SIZE (32*1024)
|
||||
# define LPC17_40_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0*/
|
||||
# undef LPC17_40_HAVE_BANK1 /* Have Peripheral SRAM bank 1 */
|
||||
# define LPC17_40_NETHCONTROLLERS 1 /* One Ethernet controller */
|
||||
# undef LPC17_40_NUSBHOST /* One USB host controller */
|
||||
# undef LPC17_40_NUSBOTG /* One USB OTG controller */
|
||||
# define LPC17_40_NUSBDEV 1 /* One USB device controller */
|
||||
# undef LPC17_40_HAVE_SPIFI /* Have SPIFI interface */
|
||||
# undef LPC17_40_HAVE_LCD /* No LCD controller */
|
||||
# define LPC17_40_HAVE_QEI 1 /* One QEI interface */
|
||||
# define LPC17_40_HAVE_SD 1 /* One SD controller */
|
||||
#elif defined(CONFIG_ARCH_CHIP_LPC1776)
|
||||
# undef LPC176x /* Not LPC175/6 family */
|
||||
# define LPC178x_40xx 1 /* LPC177/8 or LPC40xx family */
|
||||
# define LPC17_40_FLASH_SIZE (256*1024) /* 256Kb */
|
||||
# define LPC17_40_SRAM_SIZE (80*1024) /* 80Kb */
|
||||
# define LPC17_40_CPUSRAM_SIZE (64*1024)
|
||||
# define LPC17_40_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */
|
||||
# undef LPC17_40_HAVE_BANK1 /* Have Peripheral SRAM bank 1 */
|
||||
# define LPC17_40_NETHCONTROLLERS 1 /* One Ethernet controller */
|
||||
# define LPC17_40_NUSBHOST 1 /* One USB host controller */
|
||||
# define LPC17_40_NUSBOTG 1 /* One USB OTG controller */
|
||||
# define LPC17_40_NUSBDEV 1 /* One USB device controller */
|
||||
# undef LPC17_40_HAVE_SPIFI /* Have SPIFI interface */
|
||||
# undef LPC17_40_HAVE_LCD /* No LCD controller */
|
||||
# define LPC17_40_HAVE_QEI 1 /* One QEI interface */
|
||||
# define LPC17_40_HAVE_SD 1 /* One SD controller */
|
||||
#elif defined(CONFIG_ARCH_CHIP_LPC1777)
|
||||
# undef LPC176x /* Not LPC175/6 family */
|
||||
# define LPC178x_40xx 1 /* LPC177/8 or LPC40xx family */
|
||||
# define LPC17_40_FLASH_SIZE (512*1024) /* 512Kb */
|
||||
# define LPC17_40_SRAM_SIZE (96*1024) /* 96Kb */
|
||||
# define LPC17_40_CPUSRAM_SIZE (64*1024)
|
||||
# define LPC17_40_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */
|
||||
# define LPC17_40_HAVE_BANK1 1 /* Have Peripheral SRAM bank 1 */
|
||||
# undef LPC17_40_NETHCONTROLLERS /* No Ethernet controller */
|
||||
# define LPC17_40_NUSBHOST 1 /* One USB host controller */
|
||||
# define LPC17_40_NUSBOTG 1 /* One USB OTG controller */
|
||||
# define LPC17_40_NUSBDEV 1 /* One USB device controller */
|
||||
# undef LPC17_40_HAVE_SPIFI /* Have SPIFI interface */
|
||||
# undef LPC17_40_HAVE_LCD /* No LCD controller */
|
||||
# define LPC17_40_HAVE_QEI 1 /* One QEI interface */
|
||||
# define LPC17_40_HAVE_SD 1 /* One SD controller */
|
||||
#elif defined(CONFIG_ARCH_CHIP_LPC1778)
|
||||
# undef LPC176x /* Not LPC175/6 family */
|
||||
# define LPC178x_40xx 1 /* LPC177/8 or LPC40xx family */
|
||||
# define LPC17_40_FLASH_SIZE (512*1024) /* 512Kb */
|
||||
# define LPC17_40_SRAM_SIZE (96*1024) /* 64Kb */
|
||||
# define LPC17_40_CPUSRAM_SIZE (64*1024)
|
||||
# define LPC17_40_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */
|
||||
# define LPC17_40_HAVE_BANK1 1 /* Have Peripheral SRAM bank 1 */
|
||||
# define LPC17_40_NETHCONTROLLERS 1 /* One Ethernet controller */
|
||||
# define LPC17_40_NUSBHOST 1 /* One USB host controller */
|
||||
# define LPC17_40_NUSBOTG 1 /* One USB OTG controller */
|
||||
# define LPC17_40_NUSBDEV 1 /* One USB device controller */
|
||||
# undef LPC17_40_HAVE_SPIFI /* Have SPIFI interface */
|
||||
# undef LPC17_40_HAVE_LCD /* No LCD controller */
|
||||
# define LPC17_40_HAVE_QEI 1 /* One QEI interface */
|
||||
# define LPC17_40_HAVE_SD 1 /* One SD controller */
|
||||
#elif defined(CONFIG_ARCH_CHIP_LPC1785)
|
||||
# undef LPC176x /* Not LPC175/6 family */
|
||||
# define LPC178x_40xx 1 /* LPC177/8 or LPC40xx family */
|
||||
# define LPC17_40_FLASH_SIZE (256*1024) /* 256Kb */
|
||||
# define LPC17_40_SRAM_SIZE (80*1024) /* 80Kb */
|
||||
# define LPC17_40_CPUSRAM_SIZE (64*1024)
|
||||
# define LPC17_40_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */
|
||||
# undef LPC17_40_HAVE_BANK1 /* Have Peripheral SRAM bank 1 */
|
||||
# undef LPC17_40_NETHCONTROLLERS /* No Ethernet controller */
|
||||
# define LPC17_40_NUSBHOST 1 /* One USB host controller */
|
||||
# define LPC17_40_NUSBOTG 1 /* One USB OTG controller */
|
||||
# define LPC17_40_NUSBDEV 1 /* One USB device controller */
|
||||
# undef LPC17_40_HAVE_SPIFI /* Have SPIFI interface */
|
||||
# define LPC17_40_HAVE_LCD 1 /* One LCD controller */
|
||||
# undef LPC17_40_HAVE_QEI /* One QEI interface */
|
||||
# define LPC17_40_HAVE_SD 1 /* One SD controller */
|
||||
#elif defined(CONFIG_ARCH_CHIP_LPC1786)
|
||||
# undef LPC176x /* Not LPC175/6 family */
|
||||
# define LPC178x_40xx 1 /* LPC177/8 or LPC40xx family */
|
||||
# define LPC17_40_FLASH_SIZE (256*1024) /* 256Kb */
|
||||
# define LPC17_40_SRAM_SIZE (80*1024) /* 80Kb */
|
||||
# define LPC17_40_CPUSRAM_SIZE (64*1024)
|
||||
# define LPC17_40_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */
|
||||
# undef LPC17_40_HAVE_BANK1 /* Have Peripheral SRAM bank 1 */
|
||||
# define LPC17_40_NETHCONTROLLERS 1 /* One Ethernet controller */
|
||||
# define LPC17_40_NUSBHOST 1 /* One USB host controller */
|
||||
# define LPC17_40_NUSBOTG 1 /* One USB OTG controller */
|
||||
# define LPC17_40_NUSBDEV 1 /* One USB device controller */
|
||||
# undef LPC17_40_HAVE_SPIFI /* Have SPIFI interface */
|
||||
# define LPC17_40_HAVE_LCD 1 /* One LCD controller */
|
||||
# define LPC17_40_HAVE_QEI 1 /* One QEI interface */
|
||||
# define LPC17_40_HAVE_SD 1 /* One SD controller */
|
||||
#elif defined(CONFIG_ARCH_CHIP_LPC1787)
|
||||
# undef LPC176x /* Not LPC175/6 family */
|
||||
# define LPC178x_40xx 1 /* LPC177/8 or LPC40xx family */
|
||||
# define LPC17_40_FLASH_SIZE (512*1024) /* 512Kb */
|
||||
# define LPC17_40_SRAM_SIZE (96*1024) /* 96Kb */
|
||||
# define LPC17_40_CPUSRAM_SIZE (64*1024)
|
||||
# define LPC17_40_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */
|
||||
# define LPC17_40_HAVE_BANK1 1 /* Have Peripheral SRAM bank 1 */
|
||||
# undef LPC17_40_NETHCONTROLLERS /* No Ethernet controller */
|
||||
# define LPC17_40_NUSBHOST 1 /* One USB host controller */
|
||||
# define LPC17_40_NUSBOTG 1 /* One USB OTG controller */
|
||||
# define LPC17_40_NUSBDEV 1 /* One USB device controller */
|
||||
# undef LPC17_40_HAVE_SPIFI /* Have SPIFI interface */
|
||||
# define LPC17_40_HAVE_LCD 1 /* One LCD controller */
|
||||
# define LPC17_40_HAVE_QEI 1 /* One QEI interface */
|
||||
# define LPC17_40_HAVE_SD 1 /* One SD controller */
|
||||
#elif defined(CONFIG_ARCH_CHIP_LPC1788)
|
||||
# undef LPC176x /* Not LPC175/6 family */
|
||||
# define LPC178x_40xx 1 /* LPC177/8 or LPC40xx family */
|
||||
# define LPC17_40_FLASH_SIZE (512*1024) /* 512Kb */
|
||||
# define LPC17_40_SRAM_SIZE (96*1024) /* 96Kb */
|
||||
# define LPC17_40_CPUSRAM_SIZE (64*1024)
|
||||
# define LPC17_40_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */
|
||||
# define LPC17_40_HAVE_BANK1 1 /* Have Peripheral SRAM bank 1 */
|
||||
# define LPC17_40_NETHCONTROLLERS 1 /* One Ethernet controller */
|
||||
# define LPC17_40_NUSBHOST 1 /* One USB host controller */
|
||||
# define LPC17_40_NUSBOTG 1 /* One USB OTG controller */
|
||||
# define LPC17_40_NUSBDEV 1 /* One USB device controller */
|
||||
# undef LPC17_40_HAVE_SPIFI /* Have SPIFI interface */
|
||||
# define LPC17_40_HAVE_LCD 1 /* One LCD controller */
|
||||
# define LPC17_40_HAVE_QEI 1 /* One QEI interface */
|
||||
# define LPC17_40_HAVE_SD 1 /* One SD controller */
|
||||
#elif defined(CONFIG_ARCH_CHIP_LPC4072)
|
||||
# undef LPC176x /* Not LPC175/6 family */
|
||||
# define LPC178x_40xx 1 /* LPC177/8 or LPC40xx family */
|
||||
# define LPC17_40_FLASH_SIZE (64*1024) /* 64Kb */
|
||||
# define LPC17_40_SRAM_SIZE (24*1024) /* 24Kb */
|
||||
# define LPC17_40_CPUSRAM_SIZE (16*1024)
|
||||
# define LPC17_40_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */
|
||||
# undef LPC17_40_HAVE_BANK1 /* No Peripheral SRAM bank 1 */
|
||||
# undef LPC17_40_NETHCONTROLLERS /* No Ethernet controller */
|
||||
# undef LPC17_40_NUSBHOST /* No USB host controller */
|
||||
# undef LPC17_40_NUSBOTG /* No USB OTG controller */
|
||||
# define LPC17_40_NUSBDEV 1 /* One USB device controller */
|
||||
# define LPC17_40_HAVE_SPIFI 1 /* Have SPIFI interface */
|
||||
# undef LPC17_40_HAVE_LCD /* No LCD controller */
|
||||
# undef LPC17_40_HAVE_QEI /* No QEI interface */
|
||||
# undef LPC17_40_HAVE_SD /* No SD controller */
|
||||
#elif defined(CONFIG_ARCH_CHIP_LPC4074)
|
||||
# undef LPC176x /* Not LPC175/6 family */
|
||||
# define LPC178x_40xx 1 /* LPC177/8 or LPC40xx family */
|
||||
# define LPC17_40_FLASH_SIZE (128*1024) /* 128Kb */
|
||||
# define LPC17_40_SRAM_SIZE (40*1024) /* 40Kb */
|
||||
# define LPC17_40_CPUSRAM_SIZE (32*1024)
|
||||
# define LPC17_40_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0*/
|
||||
# undef LPC17_40_HAVE_BANK1 /* Have Peripheral SRAM bank 1 */
|
||||
# undef LPC17_40_NETHCONTROLLERS 0 /* No Ethernet controller */
|
||||
# undef LPC17_40_NUSBHOST /* No USB host controller */
|
||||
# undef LPC17_40_NUSBOTG /* No USB OTG controller */
|
||||
# define LPC17_40_NUSBDEV 1 /* One USB device controller */
|
||||
# define LPC17_40_HAVE_SPIFI 1 /* Have SPIFI interface */
|
||||
# undef LPC17_40_HAVE_LCD /* One LCD controller */
|
||||
# undef LPC17_40_HAVE_QEI /* No QEI interface */
|
||||
# undef LPC17_40_HAVE_SD /* No SD controller */
|
||||
#elif defined(CONFIG_ARCH_CHIP_LPC4076)
|
||||
# undef LPC176x /* Not LPC175/6 family */
|
||||
# define LPC178x_40xx 1 /* LPC177/8 or LPC40xx family */
|
||||
# define LPC17_40_FLASH_SIZE (256*1024) /* 256Kb */
|
||||
# define LPC17_40_SRAM_SIZE (80*1024) /* 80Kb */
|
||||
# define LPC17_40_CPUSRAM_SIZE (64*1024)
|
||||
# define LPC17_40_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */
|
||||
# undef LPC17_40_HAVE_BANK1 /* Have Peripheral SRAM bank 1 */
|
||||
# define LPC17_40_NETHCONTROLLERS 1 /* One Ethernet controller */
|
||||
# define LPC17_40_NUSBHOST 1 /* One USB host controller */
|
||||
# define LPC17_40_NUSBOTG 1 /* One USB OTG controller */
|
||||
# define LPC17_40_NUSBDEV 1 /* One USB device controller */
|
||||
# define LPC17_40_HAVE_SPIFI 1 /* Have SPIFI interface */
|
||||
# undef LPC17_40_HAVE_LCD /* No LCD controller */
|
||||
# define LPC17_40_HAVE_QEI 1 /* One QEI interface */
|
||||
# define LPC17_40_HAVE_SD 1 /* One SD controller */
|
||||
#elif defined(CONFIG_ARCH_CHIP_LPC4078)
|
||||
# undef LPC176x /* Not LPC175/6 family */
|
||||
# define LPC178x_40xx 1 /* LPC177/8 or LPC40xx family */
|
||||
# define LPC17_40_FLASH_SIZE (512*1024) /* 512Kb */
|
||||
# define LPC17_40_SRAM_SIZE (96*1024) /* 96Kb */
|
||||
# define LPC17_40_CPUSRAM_SIZE (64*1024)
|
||||
# define LPC17_40_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */
|
||||
# define LPC17_40_HAVE_BANK1 1 /* Have Peripheral SRAM bank 1 */
|
||||
# define LPC17_40_NETHCONTROLLERS 1 /* One Ethernet controller */
|
||||
# define LPC17_40_NUSBHOST 1 /* One USB host controller */
|
||||
# define LPC17_40_NUSBOTG 1 /* One USB OTG controller */
|
||||
# define LPC17_40_NUSBDEV 1 /* One USB device controller */
|
||||
# define LPC17_40_HAVE_SPIFI 1 /* Have SPIFI interface */
|
||||
# undef LPC17_40_HAVE_LCD /* No LCD controller */
|
||||
# define LPC17_40_HAVE_QEI 1 /* One QEI interface */
|
||||
# define LPC17_40_HAVE_SD 1 /* One SD controller */
|
||||
#elif defined(CONFIG_ARCH_CHIP_LPC4088)
|
||||
# undef LPC176x /* Not LPC175/6 family */
|
||||
# define LPC178x_40xx 1 /* LPC177/8 or LPC40xx family */
|
||||
# define LPC17_40_FLASH_SIZE (512*1024) /* 512Kb */
|
||||
# define LPC17_40_SRAM_SIZE (96*1024) /* 64Kb */
|
||||
# define LPC17_40_CPUSRAM_SIZE (64*1024)
|
||||
# define LPC17_40_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */
|
||||
# define LPC17_40_HAVE_BANK1 1 /* Have Peripheral SRAM bank 1 */
|
||||
# define LPC17_40_NETHCONTROLLERS 1 /* One Ethernet controller */
|
||||
# define LPC17_40_NUSBHOST 1 /* One USB host controller */
|
||||
# define LPC17_40_NUSBOTG 1 /* One USB OTG controller */
|
||||
# define LPC17_40_NUSBDEV 1 /* One USB device controller */
|
||||
# define LPC17_40_HAVE_SPIFI 1 /* Have SPIFI interface */
|
||||
# define LPC17_40_HAVE_LCD 1 /* One LCD controller */
|
||||
# define LPC17_40_HAVE_QEI 1 /* One QEI interface */
|
||||
# define LPC17_40_HAVE_SD 1 /* One SD controller */
|
||||
#else
|
||||
# error "Unsupported LPC17xx/LPC40xx chip"
|
||||
#endif
|
||||
|
||||
/* NVIC priority levels *************************************************************/
|
||||
/* Each priority field holds a priority value, 0-31. The lower the value, the greater
|
||||
* the priority of the corresponding interrupt. The processor implements only
|
||||
* bits[7:3] of each field, bits[2:0] read as zero and ignore writes.
|
||||
*/
|
||||
|
||||
#define NVIC_SYSH_PRIORITY_MIN 0xf8 /* All bits[7:3] set is minimum priority */
|
||||
#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
|
||||
#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
|
||||
#define NVIC_SYSH_PRIORITY_STEP 0x08 /* Five bits of interrupt priority used */
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_INCLUDE_LPC17XX_40XX_CHIP_H */
|
||||
@@ -1,5 +1,5 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/include/lpc17xxx/irq.h
|
||||
* arch/arm/include/lpc17xx_40xxx/irq.h
|
||||
*
|
||||
* Copyright (C) 2010-2011, 2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
@@ -37,8 +37,8 @@
|
||||
* through nuttx/irq.h
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_ARM_INCLUDE_LPC17XX_IRQ_H
|
||||
#define __ARCH_ARM_INCLUDE_LPC17XX_IRQ_H
|
||||
#ifndef __ARCH_ARM_INCLUDE_LPC17XX_40XX_IRQ_H
|
||||
#define __ARCH_ARM_INCLUDE_LPC17XX_40XX_IRQ_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
@@ -47,7 +47,7 @@
|
||||
#ifndef __ASSEMBLY__
|
||||
# include <stdint.h>
|
||||
#endif
|
||||
#include <arch/lpc17xx/chip.h>
|
||||
#include <arch/lpc17xx_40xx/chip.h>
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
@@ -59,32 +59,32 @@
|
||||
|
||||
/* Common Processor Exceptions (vectors 0-15) */
|
||||
|
||||
#define LPC17_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
|
||||
/* Vector 0: Reset stack pointer value */
|
||||
/* Vector 1: Reset (not handler as an IRQ) */
|
||||
#define LPC17_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
|
||||
#define LPC17_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
|
||||
#define LPC17_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */
|
||||
#define LPC17_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */
|
||||
#define LPC17_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */
|
||||
#define LPC17_IRQ_SVCALL (11) /* Vector 11: SVC call */
|
||||
#define LPC17_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */
|
||||
/* Vector 13: Reserved */
|
||||
#define LPC17_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
|
||||
#define LPC17_IRQ_SYSTICK (15) /* Vector 15: System tick */
|
||||
#define LPC17_40_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
|
||||
/* Vector 0: Reset stack pointer value */
|
||||
/* Vector 1: Reset (not handler as an IRQ) */
|
||||
#define LPC17_40_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
|
||||
#define LPC17_40_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
|
||||
#define LPC17_40_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */
|
||||
#define LPC17_40_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */
|
||||
#define LPC17_40_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */
|
||||
#define LPC17_40_IRQ_SVCALL (11) /* Vector 11: SVC call */
|
||||
#define LPC17_40_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */
|
||||
/* Vector 13: Reserved */
|
||||
#define LPC17_40_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
|
||||
#define LPC17_40_IRQ_SYSTICK (15) /* Vector 15: System tick */
|
||||
|
||||
/* External interrupts (vectors >= 16) */
|
||||
|
||||
#define LPC17_IRQ_EXTINT (16) /* Vector number of the first external interrupt */
|
||||
#define LPC17_40_IRQ_EXTINT (16) /* Vector number of the first external interrupt */
|
||||
|
||||
/* Family Specfic Interrupts */
|
||||
|
||||
#if defined(LPC176x) /* LPC175/6 family */
|
||||
# include <arch/lpc17xx/lpc176x_irq.h>
|
||||
#elif defined(LPC178x) /* LPC177/8 family */
|
||||
# include <arch/lpc17xx/lpc178x_irq.h>
|
||||
# include <arch/lpc17xx_40xx/lpc176x_irq.h>
|
||||
#elif defined(LPC178x_40xx) /* LPC177/8 or LPC40xx family */
|
||||
# include <arch/lpc17xx_40xx/lpc178x_40xx_irq.h>
|
||||
#else
|
||||
# error "Unknown LPC17xx family"
|
||||
# error "Unknown LPC17xx/LPC40xx family"
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
@@ -116,4 +116,4 @@ extern "C"
|
||||
#endif
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* __ARCH_ARM_INCLUDE_LPC17XX_IRQ_H */
|
||||
#endif /* __ARCH_ARM_INCLUDE_LPC17XX_40XX_IRQ_H */
|
||||
245
arch/arm/include/lpc17xx_40xx/lpc176x_irq.h
Normal file
245
arch/arm/include/lpc17xx_40xx/lpc176x_irq.h
Normal file
@@ -0,0 +1,245 @@
|
||||
/****************************************************************************
|
||||
* arch/lpc17xx_40xx/lpc176x_irq.h
|
||||
*
|
||||
* Copyright (C) 2010-2011, 2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/* This file should never be included directed but, rather, only indirectly
|
||||
* through nuttx/irq.h
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_ARM_INCLUDE_LPC17XX_40XX_LPC176X_IRQ_H
|
||||
#define __ARCH_ARM_INCLUDE_LPC17XX_40XX_LPC176X_IRQ_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
/* IRQ numbers. The IRQ number corresponds vector number and hence map
|
||||
* directly to bits in the NVIC. This does, however, waste several words of
|
||||
* memory in the IRQ to handle mapping tables.
|
||||
*/
|
||||
|
||||
/* External interrupts (vectors >= 16) */
|
||||
|
||||
#define LPC17_40_IRQ_WDT (LPC17_40_IRQ_EXTINT+0) /* WDT Watchdog Interrupt (WDINT) */
|
||||
#define LPC17_40_IRQ_TMR0 (LPC17_40_IRQ_EXTINT+1) /* Timer 0 Match 0 - 1 (MR0, MR1)
|
||||
* Capture 0 - 1 (CR0, CR1) */
|
||||
#define LPC17_40_IRQ_TMR1 (LPC17_40_IRQ_EXTINT+2) /* Timer 1 Match 0 - 2 (MR0, MR1, MR2)
|
||||
* Capture 0 - 1 (CR0, CR1) */
|
||||
#define LPC17_40_IRQ_TMR2 (LPC17_40_IRQ_EXTINT+3) /* Timer 2 Match 0-3
|
||||
* Capture 0-1 */
|
||||
#define LPC17_40_IRQ_TMR3 (LPC17_40_IRQ_EXTINT+4) /* Timer 3 Match 0-3
|
||||
* Capture 0-1 */
|
||||
#define LPC17_40_IRQ_UART0 (LPC17_40_IRQ_EXTINT+5) /* UART 0 Rx Line Status (RLS)
|
||||
* Transmit Holding Register Empty (THRE)
|
||||
* Rx Data Available (RDA)
|
||||
* Character Time-out Indicator (CTI)
|
||||
* End of Auto-Baud (ABEO)
|
||||
* Auto-Baud Time-Out (ABTO) */
|
||||
#define LPC17_40_IRQ_UART1 (LPC17_40_IRQ_EXTINT+6) /* UART 1 Rx Line Status (RLS)
|
||||
* Transmit Holding Register Empty (THRE)
|
||||
* Rx Data Available (RDA)
|
||||
* Character Time-out Indicator (CTI)
|
||||
* Modem Control Change
|
||||
* End of Auto-Baud (ABEO)
|
||||
* Auto-Baud Time-Out (ABTO) */
|
||||
#define LPC17_40_IRQ_UART2 (LPC17_40_IRQ_EXTINT+7) /* UART 2 Rx Line Status (RLS)
|
||||
* Transmit Holding Register Empty (THRE)
|
||||
* Rx Data Available (RDA)
|
||||
* Character Time-out Indicator (CTI)
|
||||
* End of Auto-Baud (ABEO)
|
||||
* Auto-Baud Time-Out (ABTO) */
|
||||
#define LPC17_40_IRQ_UART3 (LPC17_40_IRQ_EXTINT+8) /* UART 3 Rx Line Status (RLS)
|
||||
* Transmit Holding Register Empty (THRE)
|
||||
* Rx Data Available (RDA)
|
||||
* Character Time-out Indicator (CTI)
|
||||
* End of Auto-Baud (ABEO)
|
||||
* Auto-Baud Time-Out (ABTO) */
|
||||
#define LPC17_40_IRQ_PWM1 (LPC17_40_IRQ_EXTINT+9) /* PWM1 Match 0 - 6 of PWM1
|
||||
* Capture 0-1 of PWM1 */
|
||||
#define LPC17_40_IRQ_I2C0 (LPC17_40_IRQ_EXTINT+10) /* I2C0 SI (state change) */
|
||||
#define LPC17_40_IRQ_I2C1 (LPC17_40_IRQ_EXTINT+11) /* I2C1 SI (state change) */
|
||||
#define LPC17_40_IRQ_I2C2 (LPC17_40_IRQ_EXTINT+12) /* I2C2 SI (state change) */
|
||||
#define LPC17_40_IRQ_SPIF (LPC17_40_IRQ_EXTINT+13) /* SPI SPI Interrupt Flag (SPIF)
|
||||
* Mode Fault (MODF) */
|
||||
#define LPC17_40_IRQ_SSP0 (LPC17_40_IRQ_EXTINT+14) /* SSP0 Tx FIFO half empty of SSP0
|
||||
* Rx FIFO half full of SSP0
|
||||
* Rx Timeout of SSP0
|
||||
* Rx Overrun of SSP0 */
|
||||
#define LPC17_40_IRQ_SSP1 (LPC17_40_IRQ_EXTINT+15) /* SSP 1 Tx FIFO half empty
|
||||
* Rx FIFO half full
|
||||
* Rx Timeout
|
||||
* Rx Overrun */
|
||||
#define LPC17_40_IRQ_PLL0 (LPC17_40_IRQ_EXTINT+16) /* PLL0 (Main PLL) PLL0 Lock (PLOCK0) */
|
||||
#define LPC17_40_IRQ_RTC (LPC17_40_IRQ_EXTINT+17) /* RTC Counter Increment (RTCCIF)
|
||||
* Alarm (RTCALF) */
|
||||
#define LPC17_40_IRQ_EINT0 (LPC17_40_IRQ_EXTINT+18) /* External Interrupt 0 (EINT0) */
|
||||
#define LPC17_40_IRQ_EINT1 (LPC17_40_IRQ_EXTINT+19) /* External Interrupt 1 (EINT1) */
|
||||
#define LPC17_40_IRQ_EINT2 (LPC17_40_IRQ_EXTINT+20) /* External Interrupt 2 (EINT2) */
|
||||
#define LPC17_40_IRQ_EINT3 (LPC17_40_IRQ_EXTINT+21) /* External Interrupt 3 (EINT3)
|
||||
* Note: EINT3 channel is shared with GPIO interrupts */
|
||||
#define LPC17_40_IRQ_ADC (LPC17_40_IRQ_EXTINT+22) /* ADC A/D Converter end of conversion */
|
||||
#define LPC17_40_IRQ_BOD (LPC17_40_IRQ_EXTINT+23) /* BOD Brown Out detect */
|
||||
#define LPC17_40_IRQ_USB (LPC17_40_IRQ_EXTINT+24) /* USB USB_INT_REQ_LP, USB_INT_REQ_HP,
|
||||
* USB_INT_REQ_DMA */
|
||||
#define LPC17_40_IRQ_CAN (LPC17_40_IRQ_EXTINT+25) /* CAN CAN Common, CAN 0 Tx, CAN 0 Rx,
|
||||
* CAN 1 Tx, CAN 1 Rx */
|
||||
#define LPC17_40_IRQ_GPDMA (LPC17_40_IRQ_EXTINT+26) /* GPDMA IntStatus of DMA channel 0,
|
||||
* IntStatus of DMA channel 1 */
|
||||
#define LPC17_40_IRQ_I2S (LPC17_40_IRQ_EXTINT+27) /* I2S irq, dmareq1, dmareq2 */
|
||||
#define LPC17_40_IRQ_ETH (LPC17_40_IRQ_EXTINT+28) /* Ethernet WakeupInt, SoftInt, TxDoneInt,
|
||||
* TxFinishedInt, TxErrorInt,* TxUnderrunInt,
|
||||
* RxDoneInt, RxFinishedInt, RxErrorInt,
|
||||
* RxOverrunInt */
|
||||
#define LPC17_40_IRQ_RITINT (LPC17_40_IRQ_EXTINT+29) /* Repetitive Interrupt Timer (RITINT) */
|
||||
#define LPC17_40_IRQ_MCPWM (LPC17_40_IRQ_EXTINT+30) /* Motor Control PWM IPER[2:0], IPW[2:0],
|
||||
* ICAP[2:0], FES */
|
||||
#define LPC17_40_IRQ_QEI (LPC17_40_IRQ_EXTINT+31) /* Quadrature Encoder INX_Int, TIM_Int, VELC_Int,
|
||||
* DIR_Int, ERR_Int, ENCLK_Int, POS0_Int, POS1_Int
|
||||
* POS2_Int, REV_Int, POS0REV_Int, OS1REV_Int,
|
||||
* POS2REV_Int */
|
||||
#define LPC17_40_IRQ_PLL1 (LPC17_40_IRQ_EXTINT+32) /* PLL1 (USB PLL) PLL1 Lock (PLOCK1) */
|
||||
#define LPC17_40_IRQ_USBACT (LPC17_40_IRQ_EXTINT+33) /* USB Activity Interrupt USB_NEED_CLK */
|
||||
#define LPC17_40_IRQ_CANACT (LPC17_40_IRQ_EXTINT+34) /* CAN Activity Interrupt CAN1WAKE, CAN2WAKE */
|
||||
#define LPC17_40_IRQ_NEXTINT (35)
|
||||
#define LPC17_40_IRQ_NIRQS (LPC17_40_IRQ_EXTINT+LPC17_40_IRQ_NEXTINT)
|
||||
|
||||
/* GPIO interrupts. The LPC17xx/LPC40xx supports several interrupts on ports 0 and
|
||||
* 2 (only). We go through some special efforts to keep the number of IRQs
|
||||
* to a minimum in this sparse interrupt case.
|
||||
*
|
||||
* 28 interrupts on Port 0: p0.0 - p0.11, p0.15-p0.30
|
||||
* 14 interrupts on Port 2: p2.0 - p2.13
|
||||
* --
|
||||
* 42
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_LPC17_40_GPIOIRQ
|
||||
# define LPC17_40_VALID_GPIOINT0 (0x7fff8ffful) /* GPIO port 0 interrupt set */
|
||||
# define LPC17_40_VALID_GPIOINT2 (0x00003ffful) /* GPIO port 2 interrupt set */
|
||||
|
||||
/* Set 1: 12 interrupts p0.0-p0.11 */
|
||||
|
||||
# define LPC17_40_VALID_GPIOINT0L (0x00000ffful)
|
||||
# define LPC17_40_VALID_SHIFT0L (0)
|
||||
# define LPC17_40_VALID_FIRST0L (LPC17_40_IRQ_EXTINT+LPC17_40_IRQ_NEXTINT)
|
||||
|
||||
# define LPC17_40_IRQ_P0p0 (LPC17_40_VALID_FIRST0L+0)
|
||||
# define LPC17_40_IRQ_P0p1 (LPC17_40_VALID_FIRST0L+1)
|
||||
# define LPC17_40_IRQ_P0p2 (LPC17_40_VALID_FIRST0L+2)
|
||||
# define LPC17_40_IRQ_P0p3 (LPC17_40_VALID_FIRST0L+3)
|
||||
# define LPC17_40_IRQ_P0p4 (LPC17_40_VALID_FIRST0L+4)
|
||||
# define LPC17_40_IRQ_P0p5 (LPC17_40_VALID_FIRST0L+5)
|
||||
# define LPC17_40_IRQ_P0p6 (LPC17_40_VALID_FIRST0L+6)
|
||||
# define LPC17_40_IRQ_P0p7 (LPC17_40_VALID_FIRST0L+7)
|
||||
# define LPC17_40_IRQ_P0p8 (LPC17_40_VALID_FIRST0L+8)
|
||||
# define LPC17_40_IRQ_P0p9 (LPC17_40_VALID_FIRST0L+9)
|
||||
# define LPC17_40_IRQ_P0p10 (LPC17_40_VALID_FIRST0L+10)
|
||||
# define LPC17_40_IRQ_P0p11 (LPC17_40_VALID_FIRST0L+11)
|
||||
# define LPC17_40_VALID_NIRQS0L (12)
|
||||
|
||||
/* Set 2: 16 interrupts p0.15-p0.30 */
|
||||
|
||||
# define LPC17_40_VALID_GPIOINT0H (0x7fff8000ull)
|
||||
# define LPC17_40_VALID_SHIFT0H (15)
|
||||
# define LPC17_40_VALID_FIRST0H (LPC17_40_VALID_FIRST0L+LPC17_40_VALID_NIRQS0L)
|
||||
|
||||
# define LPC17_40_IRQ_P0p15 (LPC17_40_VALID_FIRST0H+0)
|
||||
# define LPC17_40_IRQ_P0p16 (LPC17_40_VALID_FIRST0H+1)
|
||||
# define LPC17_40_IRQ_P0p17 (LPC17_40_VALID_FIRST0H+2)
|
||||
# define LPC17_40_IRQ_P0p18 (LPC17_40_VALID_FIRST0H+3)
|
||||
# define LPC17_40_IRQ_P0p19 (LPC17_40_VALID_FIRST0H+4)
|
||||
# define LPC17_40_IRQ_P0p20 (LPC17_40_VALID_FIRST0H+5)
|
||||
# define LPC17_40_IRQ_P0p21 (LPC17_40_VALID_FIRST0H+6)
|
||||
# define LPC17_40_IRQ_P0p22 (LPC17_40_VALID_FIRST0H+7)
|
||||
# define LPC17_40_IRQ_P0p23 (LPC17_40_VALID_FIRST0H+8)
|
||||
# define LPC17_40_IRQ_P0p24 (LPC17_40_VALID_FIRST0H+9)
|
||||
# define LPC17_40_IRQ_P0p25 (LPC17_40_VALID_FIRST0H+10)
|
||||
# define LPC17_40_IRQ_P0p26 (LPC17_40_VALID_FIRST0H+11)
|
||||
# define LPC17_40_IRQ_P0p27 (LPC17_40_VALID_FIRST0H+12)
|
||||
# define LPC17_40_IRQ_P0p28 (LPC17_40_VALID_FIRST0H+13)
|
||||
# define LPC17_40_IRQ_P0p29 (LPC17_40_VALID_FIRST0H+14)
|
||||
# define LPC17_40_IRQ_P0p30 (LPC17_40_VALID_FIRST0H+15)
|
||||
# define LPC17_40_VALID_NIRQS0H (16)
|
||||
|
||||
/* Set 3: 14 interrupts p2.0-p2.13 */
|
||||
|
||||
# define LPC17_40_VALID_GPIOINT2 (0x00003ffful)
|
||||
# define LPC17_40_VALID_SHIFT2 (0)
|
||||
# define LPC17_40_VALID_FIRST2 (LPC17_40_VALID_FIRST0H+LPC17_40_VALID_NIRQS0H)
|
||||
|
||||
# define LPC17_40_IRQ_P2p0 (LPC17_40_VALID_FIRST2+0)
|
||||
# define LPC17_40_IRQ_P2p1 (LPC17_40_VALID_FIRST2+1)
|
||||
# define LPC17_40_IRQ_P2p2 (LPC17_40_VALID_FIRST2+2)
|
||||
# define LPC17_40_IRQ_P2p3 (LPC17_40_VALID_FIRST2+3)
|
||||
# define LPC17_40_IRQ_P2p4 (LPC17_40_VALID_FIRST2+4)
|
||||
# define LPC17_40_IRQ_P2p5 (LPC17_40_VALID_FIRST2+5)
|
||||
# define LPC17_40_IRQ_P2p6 (LPC17_40_VALID_FIRST2+6)
|
||||
# define LPC17_40_IRQ_P2p7 (LPC17_40_VALID_FIRST2+7)
|
||||
# define LPC17_40_IRQ_P2p8 (LPC17_40_VALID_FIRST2+8)
|
||||
# define LPC17_40_IRQ_P2p9 (LPC17_40_VALID_FIRST2+9)
|
||||
# define LPC17_40_IRQ_P2p10 (LPC17_40_VALID_FIRST2+10)
|
||||
# define LPC17_40_IRQ_P2p11 (LPC17_40_VALID_FIRST2+11)
|
||||
# define LPC17_40_IRQ_P2p12 (LPC17_40_VALID_FIRST2+12)
|
||||
# define LPC17_40_IRQ_P2p13 (LPC17_40_VALID_FIRST2+13)
|
||||
# define LPC17_40_VALID_NIRQS2 (14)
|
||||
# define LPC17_40_NGPIOAIRQS (LPC17_40_VALID_NIRQS0L+LPC17_40_VALID_NIRQS0H+LPC17_40_VALID_NIRQS2)
|
||||
#else
|
||||
# define LPC17_40_NGPIOAIRQS (0)
|
||||
#endif
|
||||
|
||||
/* Total number of IRQ numbers */
|
||||
|
||||
#define NR_IRQS (LPC17_40_IRQ_EXTINT+LPC17_40_IRQ_NEXTINT+LPC17_40_NGPIOAIRQS)
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Inline functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_INCLUDE_LPC17XX_40XX_LPC176X_IRQ_H */
|
||||
|
||||
291
arch/arm/include/lpc17xx_40xx/lpc178x_40xx_irq.h
Normal file
291
arch/arm/include/lpc17xx_40xx/lpc178x_40xx_irq.h
Normal file
@@ -0,0 +1,291 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/include/lpc17xx_40xxx/lpc178x_40xx_irq.h
|
||||
*
|
||||
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
|
||||
* Authors: Rommel Marcelo
|
||||
* Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/* This file should never be included directed but, rather,
|
||||
* only indirectly through nuttx/irq.h
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_ARM_INCLUDE_LPC17XX_40XX_LPC178X_IRQ_H
|
||||
#define __ARCH_ARM_INCLUDE_LPC17XX_40XX_LPC178X_IRQ_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* IRQ numbers. The IRQ number corresponds vector number and hence map
|
||||
* directly to bits in the NVIC. This does, however, waste several words of
|
||||
* memory in the IRQ to handle mapping tables.
|
||||
*/
|
||||
|
||||
/* External interrupts (vectors >= 16) */
|
||||
|
||||
#define LPC17_40_IRQ_WDT (LPC17_40_IRQ_EXTINT+0) /* WDT Watchdog Interrupt (WDINT) */
|
||||
#define LPC17_40_IRQ_TMR0 (LPC17_40_IRQ_EXTINT+1) /* Timer 0 Match 0 - 1 (MR0, MR1)
|
||||
* Capture 0 - 1 (CR0, CR1) */
|
||||
#define LPC17_40_IRQ_TMR1 (LPC17_40_IRQ_EXTINT+2) /* Timer 1 Match 0 - 2 (MR0, MR1, MR2)
|
||||
* Capture 0 - 1 (CR0, CR1) */
|
||||
#define LPC17_40_IRQ_TMR2 (LPC17_40_IRQ_EXTINT+3) /* Timer 2 Match 0-3
|
||||
* Capture 0-1 */
|
||||
#define LPC17_40_IRQ_TMR3 (LPC17_40_IRQ_EXTINT+4) /* Timer 3 Match 0-3
|
||||
* Capture 0-1 */
|
||||
#define LPC17_40_IRQ_UART0 (LPC17_40_IRQ_EXTINT+5) /* UART 0 Rx Line Status (RLS)
|
||||
* Transmit Holding Register Empty (THRE)
|
||||
* Rx Data Available (RDA)
|
||||
* Character Time-out Indicator (CTI)
|
||||
* End of Auto-Baud (ABEO)
|
||||
* Auto-Baud Time-Out (ABTO) */
|
||||
#define LPC17_40_IRQ_UART1 (LPC17_40_IRQ_EXTINT+6) /* UART 1 Rx Line Status (RLS)
|
||||
* Transmit Holding Register Empty (THRE)
|
||||
* Rx Data Available (RDA)
|
||||
* Character Time-out Indicator (CTI)
|
||||
* Modem Control Change
|
||||
* End of Auto-Baud (ABEO)
|
||||
* Auto-Baud Time-Out (ABTO) */
|
||||
#define LPC17_40_IRQ_UART2 (LPC17_40_IRQ_EXTINT+7) /* UART 2 Rx Line Status (RLS)
|
||||
* Transmit Holding Register Empty (THRE)
|
||||
* Rx Data Available (RDA)
|
||||
* Character Time-out Indicator (CTI)
|
||||
* End of Auto-Baud (ABEO)
|
||||
* Auto-Baud Time-Out (ABTO) */
|
||||
#define LPC17_40_IRQ_UART3 (LPC17_40_IRQ_EXTINT+8) /* UART 3 Rx Line Status (RLS)
|
||||
* Transmit Holding Register Empty (THRE)
|
||||
* Rx Data Available (RDA)
|
||||
* Character Time-out Indicator (CTI)
|
||||
* End of Auto-Baud (ABEO)
|
||||
* Auto-Baud Time-Out (ABTO) */
|
||||
#define LPC17_40_IRQ_PWM1 (LPC17_40_IRQ_EXTINT+9) /* PWM1 Match 0 - 6 of PWM1
|
||||
* Capture 0-1 of PWM1 */
|
||||
#define LPC17_40_IRQ_I2C0 (LPC17_40_IRQ_EXTINT+10) /* I2C0 SI (state change) */
|
||||
#define LPC17_40_IRQ_I2C1 (LPC17_40_IRQ_EXTINT+11) /* I2C1 SI (state change) */
|
||||
#define LPC17_40_IRQ_I2C2 (LPC17_40_IRQ_EXTINT+12) /* I2C2 SI (state change) */
|
||||
#define LPC17_40_IRQ_RESERVED29 (LPC17_40_IRQ_EXTINT+13) /* Unused */
|
||||
#define LPC17_40_IRQ_SSP0 (LPC17_40_IRQ_EXTINT+14) /* SSP0 Tx FIFO half empty of SSP0
|
||||
* Rx FIFO half full of SSP0
|
||||
* Rx Timeout of SSP0
|
||||
* Rx Overrun of SSP0 */
|
||||
#define LPC17_40_IRQ_SSP1 (LPC17_40_IRQ_EXTINT+15) /* SSP 1 Tx FIFO half empty
|
||||
* Rx FIFO half full
|
||||
* Rx Timeout
|
||||
* Rx Overrun */
|
||||
#define LPC17_40_IRQ_PLL0 (LPC17_40_IRQ_EXTINT+16) /* PLL0 (Main PLL) PLL0 Lock (PLOCK0) */
|
||||
#define LPC17_40_IRQ_RTC (LPC17_40_IRQ_EXTINT+17) /* RTC Counter Increment (RTCCIF)
|
||||
* Alarm (RTCALF) */
|
||||
#define LPC17_40_IRQ_EINT0 (LPC17_40_IRQ_EXTINT+18) /* External Interrupt 0 (EINT0) */
|
||||
#define LPC17_40_IRQ_EINT1 (LPC17_40_IRQ_EXTINT+19) /* External Interrupt 1 (EINT1) */
|
||||
#define LPC17_40_IRQ_EINT2 (LPC17_40_IRQ_EXTINT+20) /* External Interrupt 2 (EINT2) */
|
||||
#define LPC17_40_IRQ_EINT3 (LPC17_40_IRQ_EXTINT+21) /* External Interrupt 3 (EINT3)
|
||||
* Note: EINT3 channel is shared with GPIO interrupts */
|
||||
#define LPC17_40_IRQ_ADC (LPC17_40_IRQ_EXTINT+22) /* ADC A/D Converter end of conversion */
|
||||
#define LPC17_40_IRQ_BOD (LPC17_40_IRQ_EXTINT+23) /* BOD Brown Out detect */
|
||||
#define LPC17_40_IRQ_USB (LPC17_40_IRQ_EXTINT+24) /* USB USB_INT_REQ_LP, USB_INT_REQ_HP,
|
||||
* USB_INT_REQ_DMA */
|
||||
#define LPC17_40_IRQ_CAN (LPC17_40_IRQ_EXTINT+25) /* CAN CAN Common, CAN 0 Tx, CAN 0 Rx,
|
||||
* CAN 1 Tx, CAN 1 Rx */
|
||||
#define LPC17_40_IRQ_GPDMA (LPC17_40_IRQ_EXTINT+26) /* GPDMA IntStatus of DMA channel 0,
|
||||
* IntStatus of DMA channel 1 */
|
||||
#define LPC17_40_IRQ_I2S (LPC17_40_IRQ_EXTINT+27) /* I2S irq, dmareq1, dmareq2 */
|
||||
#define LPC17_40_IRQ_ETH (LPC17_40_IRQ_EXTINT+28) /* Ethernet WakeupInt, SoftInt, TxDoneInt,
|
||||
* TxFinishedInt, TxErrorInt,* TxUnderrunInt,
|
||||
* RxDoneInt, RxFinishedInt, RxErrorInt,
|
||||
* RxOverrunInt */
|
||||
#define LPC17_40_IRQ_MCI (LPC17_40_IRQ_EXTINT+29) /* MCI SD Card Interface */
|
||||
#define LPC17_40_IRQ_MCPWM (LPC17_40_IRQ_EXTINT+30) /* Motor Control PWM IPER[2:0], IPW[2:0],
|
||||
* ICAP[2:0], FES */
|
||||
#define LPC17_40_IRQ_QEI (LPC17_40_IRQ_EXTINT+31) /* Quadrature Encoder INX_Int, TIM_Int, VELC_Int,
|
||||
* DIR_Int, ERR_Int, ENCLK_Int, POS0_Int, POS1_Int
|
||||
* POS2_Int, REV_Int, POS0REV_Int, OS1REV_Int,
|
||||
* POS2REV_Int */
|
||||
#define LPC17_40_IRQ_PLL1 (LPC17_40_IRQ_EXTINT+32) /* PLL1 (USB PLL) PLL1 Lock (PLOCK1) */
|
||||
#define LPC17_40_IRQ_USBACT (LPC17_40_IRQ_EXTINT+33) /* USB Activity Interrupt USB_NEED_CLK */
|
||||
#define LPC17_40_IRQ_CANACT (LPC17_40_IRQ_EXTINT+34) /* CAN Activity Interrupt CAN1WAKE, CAN2WAKE */
|
||||
#define LPC17_40_IRQ_UART4 (LPC17_40_IRQ_EXTINT+35) /* UART 4 Rx Line Status (RLS)
|
||||
* Transmit Holding Register Empty (THRE)
|
||||
* Rx Data Available (RDA)
|
||||
* Character Time-out Indicator (CTI)
|
||||
* End of Auto-Baud (ABEO)
|
||||
* Auto-Baud Time-Out (ABTO) */
|
||||
#define LPC17_40_IRQ_SSP2 (LPC17_40_IRQ_EXTINT+36) /* SSP2 Tx FIFO half empty of SSP2
|
||||
* Rx FIFO half full of SSP2
|
||||
* Rx Timeout of SSP2
|
||||
* Rx Overrun of SSP2 */
|
||||
#define LPC17_40_IRQ_LCD (LPC17_40_IRQ_EXTINT+37) /* LCD interrupt
|
||||
* BER, VCompI, LNBUI, FUFI, CrsrI */
|
||||
#define LPC17_40_IRQ_GPIO (LPC17_40_IRQ_EXTINT+38) /* GPIO Interrupt
|
||||
* P0xREI, P2xREI, P0xFEI, P2xFEI */
|
||||
#define LPC17_40_IRQ_PWM0 (LPC17_40_IRQ_EXTINT+39) /* PWM0 Match 0 - 6 of PWM0
|
||||
* Capture 0-1 of PWM0 */
|
||||
#define LPC17_40_IRQ_EEPROM (LPC17_40_IRQ_EXTINT+40) /* EEPROM Interrupt
|
||||
* EE_PROG_DONE, EE_RW_DONE */
|
||||
#define LPC17_40_IRQ_NEXTINT (41)
|
||||
#define LPC17_40_IRQ_NIRQS (LPC17_40_IRQ_EXTINT+LPC17_40_IRQ_NEXTINT)
|
||||
|
||||
/* GPIO interrupts. The LPC177x_8x supports several interrupts on ports 0 and
|
||||
* 2 (only). We go through some special efforts to keep the number of IRQs
|
||||
* to a minimum in this sparse interrupt case.
|
||||
*
|
||||
* 31 interrupts on Port 0: p0.0 - p0.30
|
||||
* 31 interrupts on Port 2: p2.0 - p2.30
|
||||
* --
|
||||
* 42
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_LPC17_40_GPIOIRQ
|
||||
# define LPC17_40_VALID_GPIOINT0 (0xfffffffful) /* GPIO port 0 interrupt set */
|
||||
# define LPC17_40_VALID_GPIOINT2 (0xfffffffful) /* GPIO port 2 interrupt set */
|
||||
|
||||
/* Set 1: 16 interrupts p0.0-p0.15 */
|
||||
|
||||
# define LPC17_40_VALID_SHIFT0L (0)
|
||||
# define LPC17_40_VALID_FIRST0L (LPC17_40_IRQ_EXTINT+LPC17_40_IRQ_NEXTINT)
|
||||
|
||||
# define LPC17_40_IRQ_P0p0 (LPC17_40_VALID_FIRST0L+0)
|
||||
# define LPC17_40_IRQ_P0p1 (LPC17_40_VALID_FIRST0L+1)
|
||||
# define LPC17_40_IRQ_P0p2 (LPC17_40_VALID_FIRST0L+2)
|
||||
# define LPC17_40_IRQ_P0p3 (LPC17_40_VALID_FIRST0L+3)
|
||||
# define LPC17_40_IRQ_P0p4 (LPC17_40_VALID_FIRST0L+4)
|
||||
# define LPC17_40_IRQ_P0p5 (LPC17_40_VALID_FIRST0L+5)
|
||||
# define LPC17_40_IRQ_P0p6 (LPC17_40_VALID_FIRST0L+6)
|
||||
# define LPC17_40_IRQ_P0p7 (LPC17_40_VALID_FIRST0L+7)
|
||||
# define LPC17_40_IRQ_P0p8 (LPC17_40_VALID_FIRST0L+8)
|
||||
# define LPC17_40_IRQ_P0p9 (LPC17_40_VALID_FIRST0L+9)
|
||||
# define LPC17_40_IRQ_P0p10 (LPC17_40_VALID_FIRST0L+10)
|
||||
# define LPC17_40_IRQ_P0p11 (LPC17_40_VALID_FIRST0L+11)
|
||||
# define LPC17_40_IRQ_P0p12 (LPC17_40_VALID_FIRST0L+12)
|
||||
# define LPC17_40_IRQ_P0p13 (LPC17_40_VALID_FIRST0L+13)
|
||||
# define LPC17_40_IRQ_P0p14 (LPC17_40_VALID_FIRST0L+14)
|
||||
# define LPC17_40_IRQ_P0p15 (LPC17_40_VALID_FIRST0L+15)
|
||||
# define LPC17_40_VALID_NIRQS0L (16)
|
||||
|
||||
/* Set 2: 16 interrupts p0.16-p0.31 */
|
||||
|
||||
# define LPC17_40_VALID_SHIFT0H (16)
|
||||
# define LPC17_40_VALID_FIRST0H (LPC17_40_VALID_FIRST0L+LPC17_40_VALID_NIRQS0L)
|
||||
|
||||
# define LPC17_40_IRQ_P0p16 (LPC17_40_VALID_FIRST0H+0)
|
||||
# define LPC17_40_IRQ_P0p17 (LPC17_40_VALID_FIRST0H+1)
|
||||
# define LPC17_40_IRQ_P0p18 (LPC17_40_VALID_FIRST0H+2)
|
||||
# define LPC17_40_IRQ_P0p19 (LPC17_40_VALID_FIRST0H+3)
|
||||
# define LPC17_40_IRQ_P0p20 (LPC17_40_VALID_FIRST0H+4)
|
||||
# define LPC17_40_IRQ_P0p21 (LPC17_40_VALID_FIRST0H+5)
|
||||
# define LPC17_40_IRQ_P0p22 (LPC17_40_VALID_FIRST0H+6)
|
||||
# define LPC17_40_IRQ_P0p23 (LPC17_40_VALID_FIRST0H+7)
|
||||
# define LPC17_40_IRQ_P0p24 (LPC17_40_VALID_FIRST0H+8)
|
||||
# define LPC17_40_IRQ_P0p25 (LPC17_40_VALID_FIRST0H+9)
|
||||
# define LPC17_40_IRQ_P0p26 (LPC17_40_VALID_FIRST0H+10)
|
||||
# define LPC17_40_IRQ_P0p27 (LPC17_40_VALID_FIRST0H+11)
|
||||
# define LPC17_40_IRQ_P0p28 (LPC17_40_VALID_FIRST0H+12)
|
||||
# define LPC17_40_IRQ_P0p29 (LPC17_40_VALID_FIRST0H+13)
|
||||
# define LPC17_40_IRQ_P0p30 (LPC17_40_VALID_FIRST0H+14)
|
||||
# define LPC17_40_IRQ_P0p31 (LPC17_40_VALID_FIRST0H+15)
|
||||
# define LPC17_40_VALID_NIRQS0H (16)
|
||||
|
||||
/* Set 3: 16 interrupts p2.0-p2.15 */
|
||||
|
||||
# define LPC17_40_VALID_SHIFT2L (0)
|
||||
# define LPC17_40_VALID_FIRST2L (LPC17_40_VALID_FIRST0H+LPC17_40_VALID_NIRQS0H)
|
||||
|
||||
# define LPC17_40_IRQ_P2p0 (LPC17_40_VALID_FIRST2L+0)
|
||||
# define LPC17_40_IRQ_P2p1 (LPC17_40_VALID_FIRST2L+1)
|
||||
# define LPC17_40_IRQ_P2p2 (LPC17_40_VALID_FIRST2L+2)
|
||||
# define LPC17_40_IRQ_P2p3 (LPC17_40_VALID_FIRST2L+3)
|
||||
# define LPC17_40_IRQ_P2p4 (LPC17_40_VALID_FIRST2L+4)
|
||||
# define LPC17_40_IRQ_P2p5 (LPC17_40_VALID_FIRST2L+5)
|
||||
# define LPC17_40_IRQ_P2p6 (LPC17_40_VALID_FIRST2L+6)
|
||||
# define LPC17_40_IRQ_P2p7 (LPC17_40_VALID_FIRST2L+7)
|
||||
# define LPC17_40_IRQ_P2p8 (LPC17_40_VALID_FIRST2L+8)
|
||||
# define LPC17_40_IRQ_P2p9 (LPC17_40_VALID_FIRST2L+9)
|
||||
# define LPC17_40_IRQ_P2p10 (LPC17_40_VALID_FIRST2L+10)
|
||||
# define LPC17_40_IRQ_P2p11 (LPC17_40_VALID_FIRST2L+11)
|
||||
# define LPC17_40_IRQ_P2p12 (LPC17_40_VALID_FIRST2L+12)
|
||||
# define LPC17_40_IRQ_P2p13 (LPC17_40_VALID_FIRST2L+13)
|
||||
# define LPC17_40_IRQ_P2p14 (LPC17_40_VALID_FIRST2L+14)
|
||||
# define LPC17_40_IRQ_P2p15 (LPC17_40_VALID_FIRST2L+15)
|
||||
# define LPC17_40_VALID_NIRQS2L (16)
|
||||
|
||||
/* Set 4: 16 interrupts p2.16 - p2.31 */
|
||||
|
||||
# define LPC17_40_VALID_SHIFT2H (16)
|
||||
# define LPC17_40_VALID_FIRST2H (LPC17_40_VALID_FIRST2L+LPC17_40_VALID_NIRQS2L)
|
||||
|
||||
# define LPC17_40_IRQ_P2p16 (LPC17_40_VALID_FIRST2H+0)
|
||||
# define LPC17_40_IRQ_P2p17 (LPC17_40_VALID_FIRST2H+1)
|
||||
# define LPC17_40_IRQ_P2p18 (LPC17_40_VALID_FIRST2H+2)
|
||||
# define LPC17_40_IRQ_P2p19 (LPC17_40_VALID_FIRST2H+3)
|
||||
# define LPC17_40_IRQ_P2p20 (LPC17_40_VALID_FIRST2H+4)
|
||||
# define LPC17_40_IRQ_P2p21 (LPC17_40_VALID_FIRST2H+5)
|
||||
# define LPC17_40_IRQ_P2p22 (LPC17_40_VALID_FIRST2H+6)
|
||||
# define LPC17_40_IRQ_P2p23 (LPC17_40_VALID_FIRST2H+7)
|
||||
# define LPC17_40_IRQ_P2p24 (LPC17_40_VALID_FIRST2H+8)
|
||||
# define LPC17_40_IRQ_P2p25 (LPC17_40_VALID_FIRST2H+9)
|
||||
# define LPC17_40_IRQ_P2p26 (LPC17_40_VALID_FIRST2H+10)
|
||||
# define LPC17_40_IRQ_P2p27 (LPC17_40_VALID_FIRST2H+11)
|
||||
# define LPC17_40_IRQ_P2p28 (LPC17_40_VALID_FIRST2H+12)
|
||||
# define LPC17_40_IRQ_P2p29 (LPC17_40_VALID_FIRST2H+13)
|
||||
# define LPC17_40_IRQ_P2p30 (LPC17_40_VALID_FIRST2H+14)
|
||||
# define LPC17_40_IRQ_P2p31 (LPC17_40_VALID_FIRST2H+15)
|
||||
# define LPC17_40_VALID_NIRQS2H (16)
|
||||
|
||||
# define LPC17_40_NGPIOAIRQS (LPC17_40_VALID_NIRQS0L+LPC17_40_VALID_NIRQS0H+LPC17_40_VALID_NIRQS2L+LPC17_40_VALID_NIRQS2H)
|
||||
#else
|
||||
# define LPC17_40_NGPIOAIRQS (0)
|
||||
#endif
|
||||
|
||||
/* Total number of IRQ numbers */
|
||||
|
||||
#define NR_IRQS (LPC17_40_IRQ_EXTINT+LPC17_40_IRQ_NEXTINT+LPC17_40_NGPIOAIRQS)
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Inline functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_INCLUDE_LPC17XX_40XX_LPC178X_IRQ_H */
|
||||
|
||||
@@ -86,7 +86,7 @@
|
||||
* vector table must be zero). In this case alignment to a 128 byte address
|
||||
* boundary is sufficient.
|
||||
*
|
||||
* Some parts, such as the LPC17xx family, require alignment to a 256 byte
|
||||
* Some parts, such as the LPC17xx/LPC40xx family, require alignment to a 256 byte
|
||||
* address boundary. Any other unusual alignment requirements for the vector
|
||||
* can be specified for a given architecture be redefining
|
||||
* NVIC_VECTAB_TBLOFF_MASK in the chip-specific chip.h header file for the
|
||||
|
||||
@@ -40,9 +40,9 @@
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/* This file is only a thin shell that includes the correct GPIO logic for
|
||||
* the selected LPC17xx family. The correct file cannot be selected by the
|
||||
* the selected LPC17xx/LPC40xx family. The correct file cannot be selected by the
|
||||
* make system because it needs the intelligence that only exists in chip.h
|
||||
* that can associate an LPC17xx part number with an LPC17xx family.
|
||||
* that can associate an LPC17xx/LPC40xx part number with an LPC17xx/LPC40xx family.
|
||||
*/
|
||||
|
||||
#include <arch/lpc11xx/chip.h>
|
||||
|
||||
@@ -52,7 +52,7 @@
|
||||
#include "hardware/lpc11_gpio.h"
|
||||
#include "hardware/lpc11_pinconfig.h"
|
||||
|
||||
/* Include the GPIO definitions for the selected LPC17xx family. */
|
||||
/* Include the GPIO definitions for the selected LPC17xx/LPC40xx family. */
|
||||
|
||||
#if defined(LPC111x)
|
||||
# include "lpc111x_gpio.h"
|
||||
|
||||
@@ -125,7 +125,7 @@ int lpc11_dumpgpio(lpc11_pinset_t pinset, const char *msg)
|
||||
#if defined(LPC176x)
|
||||
uint32_t pinsel;
|
||||
uint32_t pinmode;
|
||||
#elif defined(LPC178x)
|
||||
#elif defined(LPC178x_40xx)
|
||||
uint32_t iocon;
|
||||
#endif /* LPC176x */
|
||||
unsigned int port;
|
||||
@@ -139,7 +139,7 @@ int lpc11_dumpgpio(lpc11_pinset_t pinset, const char *msg)
|
||||
#if defined(LPC176x)
|
||||
pinsel = lpc11_pinsel(port, pin);
|
||||
pinmode = lpc11_pinmode(port, pin);
|
||||
#elif defined(LPC178x)
|
||||
#elif defined(LPC178x_40xx)
|
||||
iocon = LPC11_IOCON_P(port, pin);
|
||||
#endif /* LPC176x */
|
||||
|
||||
@@ -154,7 +154,7 @@ int lpc11_dumpgpio(lpc11_pinset_t pinset, const char *msg)
|
||||
pinsel, pinsel ? getreg32(pinsel) : 0,
|
||||
pinmode, pinmode ? getreg32(pinmode) : 0,
|
||||
g_odmode[port], getreg32(g_odmode[port]));
|
||||
#elif defined(LPC178x)
|
||||
#elif defined(LPC178x_40xx)
|
||||
gpioinfo(" IOCON[%08x]: %08x\n", iocon, getreg32(iocon));
|
||||
#endif
|
||||
|
||||
|
||||
@@ -165,7 +165,7 @@ static int lpc11_irq2port(int irq)
|
||||
{
|
||||
/* Set 1:
|
||||
* LPC176x: 12 interrupts p0.0-p0.11
|
||||
* LPC178x: 16 interrupts p0.0-p0.15
|
||||
* LPC178x_40xx: 16 interrupts p0.0-p0.15
|
||||
*/
|
||||
|
||||
if (irq >= LPC11_VALID_FIRST0L &&
|
||||
@@ -176,7 +176,7 @@ static int lpc11_irq2port(int irq)
|
||||
|
||||
/* Set 2:
|
||||
* LPC176x: 16 interrupts p0.15-p0.30
|
||||
* LPC178x: 16 interrupts p0.16-p0.31
|
||||
* LPC178x_40xx: 16 interrupts p0.16-p0.31
|
||||
*/
|
||||
|
||||
else if (irq >= LPC11_VALID_FIRST0H &&
|
||||
@@ -196,7 +196,7 @@ static int lpc11_irq2port(int irq)
|
||||
return 2;
|
||||
}
|
||||
|
||||
#elif defined (LPC178x)
|
||||
#elif defined (LPC178x_40xx)
|
||||
/* Set 3:
|
||||
* LPC18x: 16 interrupts p2.0-p2.15
|
||||
*/
|
||||
@@ -208,7 +208,7 @@ static int lpc11_irq2port(int irq)
|
||||
}
|
||||
|
||||
/* Set 4:
|
||||
* LPC178x: 16 interrupts p2.16-p2.31
|
||||
* LPC178x_40xx: 16 interrupts p2.16-p2.31
|
||||
*/
|
||||
|
||||
else if (irq >= LPC11_VALID_FIRST2H &&
|
||||
@@ -251,7 +251,7 @@ static int lpc11_irq2pin(int irq)
|
||||
|
||||
/* Set 2:
|
||||
* LPC176x: 16 interrupts p0.15-p0.30
|
||||
* LPC178x: 16 interrupts p0.16-p0.31
|
||||
* LPC178x_40xx: 16 interrupts p0.16-p0.31
|
||||
*
|
||||
* LPC11_VALID_SHIFT0H 15/16 - Bit number of the first bit in a group
|
||||
* of 16 interrupts
|
||||
@@ -281,7 +281,7 @@ static int lpc11_irq2pin(int irq)
|
||||
return irq - LPC11_VALID_FIRST2 + LPC11_VALID_SHIFT2;
|
||||
}
|
||||
|
||||
#elif defined(LPC178x)
|
||||
#elif defined(LPC178x_40xx)
|
||||
|
||||
/* Set 3:
|
||||
* LPC18x: 16 interrupts p2.0-p2.15
|
||||
@@ -425,7 +425,7 @@ static int lpc11_gpiointerrupt(int irq, void *context, FAR void *arg)
|
||||
LPC11_VALID_FIRST2, context);
|
||||
}
|
||||
|
||||
#elif defined(LPC178x)
|
||||
#elif defined(LPC178x_40xx)
|
||||
/* Check for an interrupt on GPIO2 */
|
||||
|
||||
if ((intstatus & GPIOINT_IOINTSTATUS_P2INT) != 0)
|
||||
@@ -471,8 +471,8 @@ void lpc11_gpioirqinitialize(void)
|
||||
(void)irq_attach(LPC11_IRQ_EINT3, lpc11_gpiointerrupt, NULL);
|
||||
up_enable_irq(LPC11_IRQ_EINT3);
|
||||
|
||||
#elif defined(LPC178x)
|
||||
/* the LPC178x family has a single, dedicated interrupt for GPIO0 and
|
||||
#elif defined(LPC178x_40xx)
|
||||
/* the LPC178x_40xx family has a single, dedicated interrupt for GPIO0 and
|
||||
* GPIO2.
|
||||
*/
|
||||
|
||||
|
||||
@@ -118,7 +118,7 @@
|
||||
* This Baud Rate configuration is based on idea suggested at LPCWare:
|
||||
* www.lpcware.com/content/blog/lpc17xx-uart-simpler-way-calculate-baudrate-timming
|
||||
*
|
||||
* The original code is for LPC17xx but with few modifications it worked
|
||||
* The original code is for LPC17xx/LPC40xx but with few modifications it worked
|
||||
* fine in the LPC11xx as well.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/lpc17xx/lpc11_timer.h
|
||||
* arch/arm/src/lpc17xx_40xx/lpc11_timer.h
|
||||
*
|
||||
* Copyright (C) 2010, 2012-2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/lpc17xx/lpc11_userspace.h
|
||||
* arch/arm/src/lpc17xx_40xx/lpc11_userspace.h
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
|
||||
@@ -1,136 +0,0 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/lpc17xx/hardware/lpc176x_memorymap.h
|
||||
*
|
||||
* Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC176X_MEMORYMAP_H
|
||||
#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC176X_MEMORYMAP_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Memory Map ***********************************************************************/
|
||||
|
||||
#define LPC17_FLASH_BASE 0x00000000 /* -0x1fffffff: On-chip non-volatile memory */
|
||||
#define LPC17_SRAM_BASE 0x10000000 /* -0x10007fff: On-chip SRAM (devices <=32Kb) */
|
||||
#define LPC17_ROM_BASE 0x1fff0000 /* -0x1fffffff: 8Kb Boot ROM with flash services */
|
||||
#define LPC17_AHBSRAM_BASE 0x20000000 /* -0x3fffffff: On-chip AHB SRAM (devices >32Kb) */
|
||||
# define LPC17_SRAM_BANK0 0x2007c000 /* -0x2007ffff: On-chip AHB SRAM Bank0 (devices >=32Kb) */
|
||||
# define LPC17_SRAM_BANK1 0x20080000 /* -0x2008ffff: On-chip AHB SRAM Bank1 (devices 64Kb) */
|
||||
#define LPC17_GPIO_BASE 0x2009c000 /* -0x2009ffff: GPIO */
|
||||
#define LPC17_APB_BASE 0x40000000 /* -0x5fffffff: APB Peripherals */
|
||||
# define LPC17_APB0_BASE 0x40000000 /* -0x4007ffff: APB0 Peripherals */
|
||||
# define LPC17_APB1_BASE 0x40080000 /* -0x400fffff: APB1 Peripherals */
|
||||
# define LPC17_AHB_BASE 0x50000000 /* -0x501fffff: DMA Controller, Ethernet, and USB */
|
||||
#define LPC17_CORTEXM3_BASE 0xe0000000 /* -0xe00fffff: (see armv7-m/nvic.h) */
|
||||
#define LPC17_SCS_BASE 0xe000e000
|
||||
#define LPC17_DEBUGMCU_BASE 0xe0042000
|
||||
|
||||
/* AHB SRAM Bank sizes **************************************************************/
|
||||
|
||||
#define LPC17_BANK0_SIZE (16*1024) /* Size of AHB SRAM Bank0 (if present) */
|
||||
#define LPC17_BANK1_SIZE (16*1024) /* Size of AHB SRAM Bank1 (if present) */
|
||||
|
||||
/* APB0 Peripherals *****************************************************************/
|
||||
|
||||
#define LPC17_WDT_BASE 0x40000000 /* -0x40003fff: Watchdog timer */
|
||||
#define LPC17_TMR0_BASE 0x40004000 /* -0x40007fff: Timer 0 */
|
||||
#define LPC17_TMR1_BASE 0x40008000 /* -0x4000bfff: Timer 1 */
|
||||
#define LPC17_UART0_BASE 0x4000c000 /* -0x4000ffff: UART 0 */
|
||||
#define LPC17_UART1_BASE 0x40010000 /* -0x40013fff: UART 1 */
|
||||
/* -0x40017fff: Reserved */
|
||||
#define LPC17_PWM1_BASE 0x40018000 /* -0x4001bfff: PWM 1 */
|
||||
#define LPC17_I2C0_BASE 0x4001c000 /* -0x4001ffff: I2C 0 */
|
||||
#define LPC17_SPI_BASE 0x40020000 /* -0x40023fff: SPI */
|
||||
#define LPC17_RTC_BASE 0x40024000 /* -0x40027fff: RTC + backup registers */
|
||||
#define LPC17_GPIOINT_BASE 0x40028000 /* -0x4002bfff: GPIO interrupts */
|
||||
#define LPC17_PINCONN_BASE 0x4002c000 /* -0x4002ffff: Pin connect block */
|
||||
#define LPC17_SSP1_BASE 0x40030000 /* -0x40033fff: SSP 1 */
|
||||
#define LPC17_ADC_BASE 0x40034000 /* -0x40037fff: ADC */
|
||||
#define LPC17_CANAFRAM_BASE 0x40038000 /* -0x4003bfff: CAN acceptance filter (AF) RAM */
|
||||
#define LPC17_CANAF_BASE 0x4003c000 /* -0x4003ffff: CAN acceptance filter (AF) registers */
|
||||
#define LPC17_CAN_BASE 0x40040000 /* -0x40043fff: CAN common registers */
|
||||
#define LPC17_CAN1_BASE 0x40044000 /* -0x40047fff: CAN controller l */
|
||||
#define LPC17_CAN2_BASE 0x40048000 /* -0x4004bfff: CAN controller 2 */
|
||||
/* -0x4005bfff: Reserved */
|
||||
#define LPC17_I2C1_BASE 0x4005c000 /* -0x4005ffff: I2C 1 */
|
||||
/* -0x4007ffff: Reserved */
|
||||
|
||||
/* APB1 Peripherals *****************************************************************/
|
||||
|
||||
/* -0x40087fff: Reserved */
|
||||
#define LPC17_SSP0_BASE 0x40088000 /* -0x4008bfff: SSP 0 */
|
||||
#define LPC17_DAC_BASE 0x4008c000 /* -0x4008ffff: DAC */
|
||||
#define LPC17_TMR2_BASE 0x40090000 /* -0x40093fff: Timer 2 */
|
||||
#define LPC17_TMR3_BASE 0x40094000 /* -0x40097fff: Timer 3 */
|
||||
#define LPC17_UART2_BASE 0x40098000 /* -0x4009bfff: UART 2 */
|
||||
#define LPC17_UART3_BASE 0x4009c000 /* -0x4009ffff: UART 3 */
|
||||
#define LPC17_I2C2_BASE 0x400a0000 /* -0x400a3fff: I2C 2 */
|
||||
/* -0x400a7fff: Reserved */
|
||||
#define LPC17_I2S_BASE 0x400a8000 /* -0x400abfff: I2S */
|
||||
/* -0x400affff: Reserved */
|
||||
#define LPC17_RIT_BASE 0x400b0000 /* -0x400b3fff: Repetitive interrupt timer */
|
||||
/* -0x400b7fff: Reserved */
|
||||
#define LPC17_MCPWM_BASE 0x400b8000 /* -0x400bbfff: Motor control PWM */
|
||||
#define LPC17_QEI_BASE 0x400bc000 /* -0x400bffff: Quadrature encoder interface */
|
||||
/* -0x400fbfff: Reserved */
|
||||
#define LPC17_SYSCON_BASE 0x400fc000 /* -0x400fffff: System control */
|
||||
|
||||
/* AHB Peripherals ******************************************************************/
|
||||
|
||||
#define LPC17_ETH_BASE 0x50000000 /* -0x50003fff: Ethernet controller */
|
||||
#define LPC17_GPDMA_BASE 0x50004000 /* -0x50007fff: GPDMA controller */
|
||||
#define LPC17_USB_BASE 0x5000c000 /* -0x5000cfff: USB controller */
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC176X_MEMORYMAP_H */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,494 +0,0 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/lpc17xx/hardware/lpc176x_syscon.h
|
||||
*
|
||||
* Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC176X_SYSCON_H
|
||||
#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC176X_SYSCON_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "hardware/lpc17_memorymap.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register offsets *****************************************************************/
|
||||
/* Flash accelerator module */
|
||||
|
||||
#define LPC17_SYSCON_FLASHCFG_OFFSET 0x0000 /* Flash Accelerator Configuration Register */
|
||||
|
||||
/* Memory Mapping Control register (MEMMAP - 0x400F C040) */
|
||||
|
||||
#define LPC17_SYSCON_MEMMAP_OFFSET 0x0040 /* Memory Mapping Control register */
|
||||
|
||||
/* Clocking and power control - Phase locked loops */
|
||||
|
||||
#define LPC17_SYSCON_PLL0CON_OFFSET 0x0080 /* PLL0 Control Register */
|
||||
#define LPC17_SYSCON_PLL0CFG_OFFSET 0x0084 /* PLL0 Configuration Register */
|
||||
#define LPC17_SYSCON_PLL0STAT_OFFSET 0x0088 /* PLL0 Status Register */
|
||||
#define LPC17_SYSCON_PLL0FEED_OFFSET 0x008c /* PLL0 Feed Register */
|
||||
|
||||
#define LPC17_SYSCON_PLL1CON_OFFSET 0x00a0 /* PLL1 Control Register */
|
||||
#define LPC17_SYSCON_PLL1CFG_OFFSET 0x00a4 /* PLL1 Configuration Register */
|
||||
#define LPC17_SYSCON_PLL1STAT_OFFSET 0x00a8 /* PLL1 Status Register */
|
||||
#define LPC17_SYSCON_PLL1FEED_OFFSET 0x00ac /* PLL1 Feed Register */
|
||||
|
||||
/* Clocking and power control - Peripheral power control registers */
|
||||
|
||||
#define LPC17_SYSCON_PCON_OFFSET 0x00c0 /* Power Control Register */
|
||||
#define LPC17_SYSCON_PCONP_OFFSET 0x00c4 /* Power Control for Peripherals Register */
|
||||
|
||||
/* Clocking and power control -- Clock dividers */
|
||||
|
||||
#define LPC17_SYSCON_CCLKCFG_OFFSET 0x0104 /* CPU Clock Configuration Register */
|
||||
#define LPC17_SYSCON_USBCLKCFG_OFFSET 0x0108 /* USB Clock Configuration Register */
|
||||
|
||||
/* 0x400f c110 - 0x400f c114: CAN Wake and Sleep Registers */
|
||||
|
||||
/* Clocking and power control -- Clock source selection */
|
||||
|
||||
#define LPC17_SYSCON_CLKSRCSEL_OFFSET 0x010c /* Clock Source Select Register */
|
||||
|
||||
/* System control registers -- External Interrupts */
|
||||
|
||||
#define LPC17_SYSCON_EXTINT_OFFSET 0x0140 /* External Interrupt Flag Register */
|
||||
|
||||
#define LPC17_SYSCON_EXTMODE_OFFSET 0x0148 /* External Interrupt Mode register */
|
||||
#define LPC17_SYSCON_EXTPOLAR_OFFSET 0x014c /* External Interrupt Polarity Register */
|
||||
|
||||
/* System control registers -- Reset */
|
||||
|
||||
#define LPC17_SYSCON_RSID_OFFSET 0x0180 /* Reset Source Identification Register */
|
||||
|
||||
/* System control registers -- Syscon Miscellaneous Registers */
|
||||
|
||||
#define LPC17_SYSCON_SCS_OFFSET 0x01a0 /* System Control and Status */
|
||||
|
||||
/* More clocking and power control -- Clock dividers */
|
||||
|
||||
#define LPC17_SYSCON_PCLKSEL0_OFFSET 0x01a8 /* Peripheral Clock Selection register 0 */
|
||||
#define LPC17_SYSCON_PCLKSEL1_OFFSET 0x01ac /* Peripheral Clock Selection register 1 */
|
||||
|
||||
/* Device Interrupt Registers (Might be a error in the User Manual, might be at 0x5000c1c0) */
|
||||
|
||||
#define LPC17_SYSCON_USBINTST_OFFSET 0x01c0 /* USB Interrupt Status */
|
||||
|
||||
/* DMA Request Select Register */
|
||||
|
||||
#define LPC17_SYSCON_DMAREQSEL_OFFSET 0x01c4 /* Selects between UART and timer DMA requests */
|
||||
|
||||
/* More clocking and power control -- Utility */
|
||||
|
||||
#define LPC17_SYSCON_CLKOUTCFG_OFFSET 0x01c8 /* Clock Output Configuration Register */
|
||||
|
||||
/* Register addresses ***************************************************************/
|
||||
/* Flash accelerator module */
|
||||
|
||||
#define LPC17_SYSCON_FLASHCFG (LPC17_SYSCON_BASE+LPC17_SYSCON_FLASHCFG_OFFSET)
|
||||
|
||||
/* Memory Mapping Control register (MEMMAP - 0x400F C040) */
|
||||
|
||||
#define LPC17_SYSCON_MEMMAP (LPC17_SYSCON_BASE+LPC17_SYSCON_MEMMAP_OFFSET)
|
||||
|
||||
/* Clocking and power control - Phase locked loops */
|
||||
|
||||
#define LPC17_SYSCON_PLL0CON (LPC17_SYSCON_BASE+LPC17_SYSCON_PLL0CON_OFFSET)
|
||||
#define LPC17_SYSCON_PLL0CFG (LPC17_SYSCON_BASE+LPC17_SYSCON_PLL0CFG_OFFSET)
|
||||
#define LPC17_SYSCON_PLL0STAT (LPC17_SYSCON_BASE+LPC17_SYSCON_PLL0STAT_OFFSET)
|
||||
#define LPC17_SYSCON_PLL0FEED (LPC17_SYSCON_BASE+LPC17_SYSCON_PLL0FEED_OFFSET)
|
||||
|
||||
#define LPC17_SYSCON_PLL1CON (LPC17_SYSCON_BASE+LPC17_SYSCON_PLL1CON_OFFSET)
|
||||
#define LPC17_SYSCON_PLL1CFG (LPC17_SYSCON_BASE+LPC17_SYSCON_PLL1CFG_OFFSET)
|
||||
#define LPC17_SYSCON_PLL1STAT (LPC17_SYSCON_BASE+LPC17_SYSCON_PLL1STAT_OFFSET)
|
||||
#define LPC17_SYSCON_PLL1FEED (LPC17_SYSCON_BASE+LPC17_SYSCON_PLL1FEED_OFFSET)
|
||||
|
||||
/* Clocking and power control - Peripheral power control registers */
|
||||
|
||||
#define LPC17_SYSCON_PCON (LPC17_SYSCON_BASE+LPC17_SYSCON_PCON_OFFSET)
|
||||
#define LPC17_SYSCON_PCONP (LPC17_SYSCON_BASE+LPC17_SYSCON_PCONP_OFFSET)
|
||||
|
||||
/* Clocking and power control -- Clock dividers */
|
||||
|
||||
#define LPC17_SYSCON_CCLKCFG (LPC17_SYSCON_BASE+LPC17_SYSCON_CCLKCFG_OFFSET)
|
||||
#define LPC17_SYSCON_USBCLKCFG (LPC17_SYSCON_BASE+LPC17_SYSCON_USBCLKCFG_OFFSET)
|
||||
|
||||
/* 0x400f c110 - 0x400f c114: CAN Wake and Sleep Registers */
|
||||
|
||||
/* Clocking and power control -- Clock source selection */
|
||||
|
||||
#define LPC17_SYSCON_CLKSRCSEL (LPC17_SYSCON_BASE+LPC17_SYSCON_CLKSRCSEL_OFFSET)
|
||||
|
||||
/* System control registers -- External Interrupts */
|
||||
|
||||
#define LPC17_SYSCON_EXTINT (LPC17_SYSCON_BASE+LPC17_SYSCON_EXTINT_OFFSET)
|
||||
|
||||
#define LPC17_SYSCON_EXTMODE (LPC17_SYSCON_BASE+LPC17_SYSCON_EXTMODE_OFFSET)
|
||||
#define LPC17_SYSCON_EXTPOLAR (LPC17_SYSCON_BASE+LPC17_SYSCON_EXTPOLAR_OFFSET)
|
||||
|
||||
/* System control registers -- Reset */
|
||||
|
||||
#define LPC17_SYSCON_RSID (LPC17_SYSCON_BASE+LPC17_SYSCON_RSID_OFFSET)
|
||||
|
||||
/* System control registers -- Syscon Miscellaneous Registers */
|
||||
|
||||
#define LPC17_SYSCON_SCS (LPC17_SYSCON_BASE+LPC17_SYSCON_SCS_OFFSET)
|
||||
|
||||
/* More clocking and power control -- Clock dividers */
|
||||
|
||||
#define LPC17_SYSCON_PCLKSEL0 (LPC17_SYSCON_BASE+LPC17_SYSCON_PCLKSEL0_OFFSET)
|
||||
#define LPC17_SYSCON_PCLKSEL1 (LPC17_SYSCON_BASE+LPC17_SYSCON_PCLKSEL1_OFFSET)
|
||||
|
||||
/* Device Interrupt Registers (Might be a error in the User Manual, might be at 0x5000c1c0) */
|
||||
|
||||
#define LPC17_SYSCON_USBINTST (LPC17_SYSCON_BASE+LPC17_SYSCON_USBINTST_OFFSET)
|
||||
|
||||
/* DMA Request Select Register */
|
||||
|
||||
#define LPC17_SYSCON_DMAREQSEL (LPC17_SYSCON_BASE+LPC17_SYSCON_DMAREQSEL_OFFSET)
|
||||
|
||||
/* More clocking and power control -- Utility */
|
||||
|
||||
#define LPC17_SYSCON_CLKOUTCFG (LPC17_SYSCON_BASE+LPC17_SYSCON_CLKOUTCFG_OFFSET)
|
||||
|
||||
/* Register bit definitions *********************************************************/
|
||||
/* Flash accelerator module */
|
||||
/* Bits 0-11: Reserved */
|
||||
#define SYSCON_FLASHCFG_TIM_SHIFT (12) /* Bits 12-15: FLASHTIM Flash access time */
|
||||
#define SYSCON_FLASHCFG_TIM_MASK (15 << SYSCON_FLASHCFG_TIM_SHIFT)
|
||||
# define SYSCON_FLASHCFG_TIM_1 (0 << SYSCON_FLASHCFG_TIM_SHIFT) /* 1 CPU clock <= 20 MHz CPU clock */
|
||||
# define SYSCON_FLASHCFG_TIM_2 (1 << SYSCON_FLASHCFG_TIM_SHIFT) /* 2 CPU clock <= 40 MHz CPU clock */
|
||||
# define SYSCON_FLASHCFG_TIM_3 (2 << SYSCON_FLASHCFG_TIM_SHIFT) /* 3 CPU clock <= 60 MHz CPU clock */
|
||||
# define SYSCON_FLASHCFG_TIM_4 (3 << SYSCON_FLASHCFG_TIM_SHIFT) /* 4 CPU clock <= 80 MHz CPU clock */
|
||||
# define SYSCON_FLASHCFG_TIM_5 (4 << SYSCON_FLASHCFG_TIM_SHIFT) /* 5 CPU clock <= 100 MHz CPU clock
|
||||
* (Up to 120 Mhz for LPC1759/69 only */
|
||||
# define SYSCON_FLASHCFG_TIM_6 (5 << SYSCON_FLASHCFG_TIM_SHIFT) /* "safe" setting for any conditions */
|
||||
/* Bits 16-31: Reserved */
|
||||
|
||||
/* Memory Mapping Control register (MEMMAP - 0x400F C040) */
|
||||
|
||||
#define SYSCON_MEMMAP_MAP (1 << 0) /* Bit 0:
|
||||
* 0:Boot mode. A portion of the Boot ROM is mapped to address 0.
|
||||
* 1:User mode. The on-chip Flash memory is mapped to address 0 */
|
||||
/* Bits 1-31: Reserved */
|
||||
|
||||
/* Clocking and power control -- Clock source selection */
|
||||
|
||||
#define SYSCON_CLKSRCSEL_SHIFT (0) /* Bits 0-1: Clock selection */
|
||||
#define SYSCON_CLKSRCSEL_MASK (3 << SYSCON_CLKSRCSEL_SHIFT)
|
||||
# define SYSCON_CLKSRCSEL_INTRC (0 << SYSCON_CLKSRCSEL_SHIFT) /* PLL0 source = internal RC oscillator */
|
||||
# define SYSCON_CLKSRCSEL_MAIN (1 << SYSCON_CLKSRCSEL_SHIFT) /* PLL0 source = main oscillator */
|
||||
# define SYSCON_CLKSRCSEL_RTC (2 << SYSCON_CLKSRCSEL_SHIFT) /* PLL0 source = RTC oscillator */
|
||||
/* Bits 2-31: Reserved */
|
||||
|
||||
/* Clocking and power control - Phase locked loops */
|
||||
/* PLL0/1 Control register */
|
||||
|
||||
#define SYSCON_PLLCON_PLLE (1 << 0) /* Bit 0: PLL0/1 Enable */
|
||||
#define SYSCON_PLLCON_PLLC (1 << 1) /* Bit 1: PLL0/1 Connect */
|
||||
/* Bits 2-31: Reserved */
|
||||
/* PLL0 Configuration register */
|
||||
|
||||
#define SYSCON_PLL0CFG_MSEL_SHIFT (0) /* Bit 0-14: PLL0 Multiplier value */
|
||||
#define SYSCON_PLL0CFG_MSEL_MASK (0x7fff << SYSCON_PLL0CFG_MSEL_SHIFT)
|
||||
/* Bit 15: Reserved */
|
||||
#define SYSCON_PLL0CFG_NSEL_SHIFT (16) /* Bit 16-23: PLL0 Pre-Divider value */
|
||||
#define SYSCON_PLL0CFG_NSEL_MASK (0xff << SYSCON_PLL0CFG_NSEL_SHIFT)
|
||||
/* Bits 24-31: Reserved */
|
||||
/* PLL1 Configuration register */
|
||||
|
||||
#define SYSCON_PLL1CFG_MSEL_SHIFT (0) /* Bit 0-4: PLL1 Multiplier value */
|
||||
#define SYSCON_PLL1CFG_MSEL_MASK (0x1f < SYSCON_PLL1CFG_MSEL_SHIFT)
|
||||
#define SYSCON_PLL1CFG_NSEL_SHIFT (5) /* Bit 5-6: PLL1 Pre-Divider value */
|
||||
#define SYSCON_PLL1CFG_NSEL_MASK (3 << SYSCON_PLL1CFG_NSEL_SHIFT)
|
||||
/* Bits 7-31: Reserved */
|
||||
/* PLL0 Status register */
|
||||
|
||||
#define SYSCON_PLL0STAT_MSEL_SHIFT (0) /* Bit 0-14: PLL0 Multiplier value readback */
|
||||
#define SYSCON_PLL0STAT_MSEL_MASK (0x7fff << SYSCON_PLL0STAT_MSEL_SHIFT)
|
||||
/* Bit 15: Reserved */
|
||||
#define SYSCON_PLL0STAT_NSEL_SHIFT (16) /* Bit 16-23: PLL0 Pre-Divider value readback */
|
||||
#define SYSCON_PLL0STAT_NSEL_MASK (0xff << SYSCON_PLL0STAT_NSEL_SHIFT)
|
||||
#define SYSCON_PLL0STAT_PLLE (1 << 24) /* Bit 24: PLL0 enable readback */
|
||||
#define SYSCON_PLL0STAT_PLLC (1 << 25) /* Bit 25: PLL0 connect readback */
|
||||
#define SYSCON_PLL0STAT_PLOCK (1 << 26) /* Bit 26: PLL0 lock status */
|
||||
/* Bits 27-31: Reserved */
|
||||
/* PLL1 Status register */
|
||||
|
||||
#define SYSCON_PLL1STAT_MSEL_SHIFT (0) /* Bit 0-4: PLL1 Multiplier value readback */
|
||||
#define SYSCON_PLL1STAT_MSEL_MASK (0x1f << SYSCON_PLL1STAT_MSEL_SHIFT)
|
||||
#define SYSCON_PLL1STAT_NSEL_SHIFT (5) /* Bit 5-6: PLL1 Pre-Divider value readback */
|
||||
#define SYSCON_PLL1STAT_NSEL_MASK (3 << SYSCON_PLL1STAT_NSEL_SHIFT)
|
||||
/* Bit 7: Reserved */
|
||||
#define SYSCON_PLL1STAT_PLLE (1 << 8) /* Bit 8: PLL1 enable readback */
|
||||
#define SYSCON_PLL1STAT_PLLC (1 << 9) /* Bit 9: PLL1 connect readback */
|
||||
#define SYSCON_PLL1STAT_PLOCK (1 << 10) /* Bit 10: PLL1 lock status */
|
||||
/* Bits 11-31: Reserved */
|
||||
/* PLL0/1 Feed register */
|
||||
|
||||
#define SYSCON_PLLFEED_SHIFT (0) /* Bit 0-7: PLL0/1 feed sequence */
|
||||
#define SYSCON_PLLFEED_MASK (0xff << SYSCON_PLLFEED_SHIFT)
|
||||
/* Bits 8-31: Reserved */
|
||||
/* Clocking and power control -- Clock dividers */
|
||||
/* CPU Clock Configuration register */
|
||||
|
||||
#define SYSCON_CCLKCFG_SHIFT (0) /* 0-7: Divide value for CPU clock (CCLK) */
|
||||
#define SYSCON_CCLKCFG_MASK (0xff << SYSCON_CCLKCFG_SHIFT)
|
||||
# define SYSCON_CCLKCFG_DIV(n) ((n-1) << SYSCON_CCLKCFG_SHIFT) /* n=2,3,..255 */
|
||||
/* Bits 8-31: Reserved */
|
||||
/* USB Clock Configuration register */
|
||||
|
||||
#define SYSCON_USBCLKCFG_SHIFT (0) /* Bits 0-3: PLL0 divide value USB clock */
|
||||
#define SYSCON_USBCLKCFG_MASK (15 << SYSCON_USBCLKCFG_SHIFT)
|
||||
# define SYSCON_USBCLKCFG_DIV6 (5 << SYSCON_USBCLKCFG_SHIFT) /* PLL0/6 for PLL0=288 MHz */
|
||||
# define SYSCON_USBCLKCFG_DIV8 (7 << SYSCON_USBCLKCFG_SHIFT) /* PLL0/8 for PLL0=384 MHz */
|
||||
# define SYSCON_USBCLKCFG_DIV10 (9 << SYSCON_USBCLKCFG_SHIFT) /* PLL0/10 for PLL0=480 MHz */
|
||||
/* Bits 8-31: Reserved */
|
||||
/* Peripheral Clock Selection registers 0 and 1 */
|
||||
|
||||
#define SYSCON_PCLKSEL_CCLK4 (0) /* PCLK_peripheral = CCLK/4 */
|
||||
#define SYSCON_PCLKSEL_CCLK (1) /* PCLK_peripheral = CCLK */
|
||||
#define SYSCON_PCLKSEL_CCLK2 (2) /* PCLK_peripheral = CCLK/2 */
|
||||
#define SYSCON_PCLKSEL_CCLK8 (3) /* PCLK_peripheral = CCLK/8 (except CAN1, CAN2, and CAN) */
|
||||
#define SYSCON_PCLKSEL_CCLK6 (3) /* PCLK_peripheral = CCLK/6 (CAN1, CAN2, and CAN) */
|
||||
#define SYSCON_PCLKSEL_MASK (3)
|
||||
|
||||
#define SYSCON_PCLKSEL0_WDT_SHIFT (0) /* Bits 0-1: Peripheral clock WDT */
|
||||
#define SYSCON_PCLKSEL0_WDT_MASK (3 << SYSCON_PCLKSEL0_WDT_SHIFT)
|
||||
#define SYSCON_PCLKSEL0_TMR0_SHIFT (2) /* Bits 2-3: Peripheral clock TIMER0 */
|
||||
#define SYSCON_PCLKSEL0_TMR0_MASK (3 << SYSCON_PCLKSEL0_TMR0_SHIFT)
|
||||
#define SYSCON_PCLKSEL0_TMR1_SHIFT (4) /* Bits 4-5: Peripheral clock TIMER1 */
|
||||
#define SYSCON_PCLKSEL0_TMR1_MASK (3 << SYSCON_PCLKSEL0_TMR1_SHIFT)
|
||||
#define SYSCON_PCLKSEL0_UART0_SHIFT (6) /* Bits 6-7: Peripheral clock UART0 */
|
||||
#define SYSCON_PCLKSEL0_UART0_MASK (3 << SYSCON_PCLKSEL0_UART0_SHIFT)
|
||||
#define SYSCON_PCLKSEL0_UART1_SHIFT (8) /* Bits 8-9: Peripheral clock UART1 */
|
||||
#define SYSCON_PCLKSEL0_UART1_MASK (3 << SYSCON_PCLKSEL0_UART1_SHIFT)
|
||||
/* Bits 10-11: Reserved */
|
||||
#define SYSCON_PCLKSEL0_PWM1_SHIFT (12) /* Bits 12-13: Peripheral clock PWM1 */
|
||||
#define SYSCON_PCLKSEL0_PWM1_MASK (3 << SYSCON_PCLKSEL0_PWM1_SHIFT)
|
||||
#define SYSCON_PCLKSEL0_I2C0_SHIFT (14) /* Bits 14-15: Peripheral clock I2C0 */
|
||||
#define SYSCON_PCLKSEL0_I2C0_MASK (3 << SYSCON_PCLKSEL0_I2C0_SHIFT)
|
||||
#define SYSCON_PCLKSEL0_SPI_SHIFT (16) /* Bits 16-17: Peripheral clock SPI */
|
||||
#define SYSCON_PCLKSEL0_SPI_MASK (3 << SYSCON_PCLKSEL0_SPI_SHIFT)
|
||||
/* Bits 18-19: Reserved */
|
||||
#define SYSCON_PCLKSEL0_SSP1_SHIFT (20) /* Bits 20-21: Peripheral clock SSP1 */
|
||||
#define SYSCON_PCLKSEL0_SSP1_MASK (3 << SYSCON_PCLKSEL0_SSP1_SHIFT)
|
||||
#define SYSCON_PCLKSEL0_DAC_SHIFT (22) /* Bits 22-23: Peripheral clock DAC */
|
||||
#define SYSCON_PCLKSEL0_DAC_MASK (3 << SYSCON_PCLKSEL0_DAC_SHIFT)
|
||||
#define SYSCON_PCLKSEL0_ADC_SHIFT (24) /* Bits 24-25: Peripheral clock ADC */
|
||||
#define SYSCON_PCLKSEL0_ADC_MASK (3 << SYSCON_PCLKSEL0_ADC_SHIFT)
|
||||
#define SYSCON_PCLKSEL0_CAN1_SHIFT (26) /* Bits 26-27: Peripheral clock CAN1 */
|
||||
#define SYSCON_PCLKSEL0_CAN1_MASK (3 << SYSCON_PCLKSEL0_CAN1_SHIFT)
|
||||
#define SYSCON_PCLKSEL0_CAN2_SHIFT (28) /* Bits 28-29: Peripheral clock CAN2 */
|
||||
#define SYSCON_PCLKSEL0_CAN2_MASK (3 << SYSCON_PCLKSEL0_CAN2_SHIFT)
|
||||
#define SYSCON_PCLKSEL0_ACF_SHIFT (30) /* Bits 30-31: Peripheral clock CAN AF */
|
||||
#define SYSCON_PCLKSEL0_ACF_MASK (3 << SYSCON_PCLKSEL0_ACF_SHIFT)
|
||||
|
||||
#define SYSCON_PCLKSEL1_QEI_SHIFT (0) /* Bits 0-1: Peripheral clock Quadrature Encoder */
|
||||
#define SYSCON_PCLKSEL1_QEI_MASK (3 << SYSCON_PCLKSEL1_QEI_SHIFT)
|
||||
#define SYSCON_PCLKSEL1_GPIOINT_SHIFT (2) /* Bits 2-3: Peripheral clock GPIO interrupts */
|
||||
#define SYSCON_PCLKSEL1_GPIOINT_MASK (3 << SYSCON_PCLKSEL1_GPIOINT_SHIFT)
|
||||
#define SYSCON_PCLKSEL1_PCB_SHIFT (4) /* Bits 4-5: Peripheral clock the Pin Connect block */
|
||||
#define SYSCON_PCLKSEL1_PCB_MASK (3 << SYSCON_PCLKSEL1_PCB_SHIFT)
|
||||
#define SYSCON_PCLKSEL1_I2C1_SHIFT (6) /* Bits 6-7: Peripheral clock I2C1 */
|
||||
#define SYSCON_PCLKSEL1_I2C1_MASK (3 << SYSCON_PCLKSEL1_I2C1_SHIFT)
|
||||
/* Bits 8-9: Reserved */
|
||||
#define SYSCON_PCLKSEL1_SSP0_SHIFT (10) /* Bits 10-11: Peripheral clock SSP0 */
|
||||
#define SYSCON_PCLKSEL1_SSP0_MASK (3 << SYSCON_PCLKSEL1_SSP0_SHIFT)
|
||||
#define SYSCON_PCLKSEL1_TMR2_SHIFT (12) /* Bits 12-13: Peripheral clock TIMER2 */
|
||||
#define SYSCON_PCLKSEL1_TMR2_MASK (3 << SYSCON_PCLKSEL1_TMR2_SHIFT)
|
||||
#define SYSCON_PCLKSEL1_TMR3_SHIFT (14) /* Bits 14-15: Peripheral clock TIMER3 */
|
||||
#define SYSCON_PCLKSEL1_TMR3_MASK (3 << SYSCON_PCLKSEL1_TMR3_SHIFT)
|
||||
#define SYSCON_PCLKSEL1_UART2_SHIFT (16) /* Bits 16-17: Peripheral clock UART2 */
|
||||
#define SYSCON_PCLKSEL1_UART2_MASK (3 << SYSCON_PCLKSEL1_UART2_SHIFT)
|
||||
#define SYSCON_PCLKSEL1_UART3_SHIFT (18) /* Bits 18-19: Peripheral clock UART3 */
|
||||
#define SYSCON_PCLKSEL1_UART3_MASK (3 << SYSCON_PCLKSEL1_UART3_SHIFT)
|
||||
#define SYSCON_PCLKSEL1_I2C2_SHIFT (20) /* Bits 20-21: Peripheral clock I2C2 */
|
||||
#define SYSCON_PCLKSEL1_I2C2_MASK (3 << SYSCON_PCLKSEL1_I2C2_SHIFT)
|
||||
#define SYSCON_PCLKSEL1_I2S_SHIFT (22) /* Bits 22-23: Peripheral clock I2S */
|
||||
#define SYSCON_PCLKSEL1_I2S_MASK (3 << SYSCON_PCLKSEL1_I2S_SHIFT)
|
||||
/* Bits 24-25: Reserved */
|
||||
#define SYSCON_PCLKSEL1_RIT_SHIFT (26) /* Bits 26-27: Peripheral clock Repetitive Interrupt Timer */
|
||||
#define SYSCON_PCLKSEL1_RIT_MASK (3 << SYSCON_PCLKSEL1_RIT_SHIFT)
|
||||
#define SYSCON_PCLKSEL1_SYSCON_SHIFT (28) /* Bits 28-29: Peripheral clock the System Control block */
|
||||
#define SYSCON_PCLKSEL1_SYSCON_MASK (3 << SYSCON_PCLKSEL1_SYSCON_SHIFT)
|
||||
#define SYSCON_PCLKSEL1_MC_SHIFT (30) /* Bits 30-31: Peripheral clock the Motor Control PWM */
|
||||
#define SYSCON_PCLKSEL1_MC_MASK (3 << SYSCON_PCLKSEL1_MC_SHIFT)
|
||||
|
||||
/* Clocking and power control - Peripheral power control registers */
|
||||
/* Power Control Register */
|
||||
|
||||
#define SYSCON_PCON_PM0 (1 << 0) /* Bit 0: Power mode control bit 0 */
|
||||
#define SYSCON_PCON_PM1 (1 << 1) /* Bit 1: Power mode control bit 1 */
|
||||
#define SYSCON_PCON_BODRPM (1 << 2) /* Bit 2: Brown-Out Reduced Power Mode */
|
||||
#define SYSCON_PCON_BOGD (1 << 3) /* Bit 3: Brown-Out Global Disable */
|
||||
#define SYSCON_PCON_BORD (1 << 4) /* Bit 4: Brown-Out Reset Disable */
|
||||
/* Bits 5-7: Reserved */
|
||||
#define SYSCON_PCON_SMFLAG (1 << 8) /* Bit 8: Sleep Mode entry flag */
|
||||
#define SYSCON_PCON_DSFLAG (1 << 9) /* Bit 9: Deep Sleep entry flag */
|
||||
#define SYSCON_PCON_PDFLAG (1 << 10) /* Bit 10: Power-down entry flag */
|
||||
#define SYSCON_PCON_DPDFLAG (1 << 11) /* Bit 11: Deep Power-down entry flag */
|
||||
/* Bits 12-31: Reserved */
|
||||
/* Power Control for Peripherals Register */
|
||||
|
||||
/* Bit 0: Reserved */
|
||||
#define SYSCON_PCONP_PCTIM0 (1 << 1) /* Bit 1: Timer/Counter 0 power/clock control */
|
||||
#define SYSCON_PCONP_PCTIM1 (1 << 2) /* Bit 2: Timer/Counter 1 power/clock control */
|
||||
#define SYSCON_PCONP_PCUART0 (1 << 3) /* Bit 3: UART0 power/clock control */
|
||||
#define SYSCON_PCONP_PCUART1 (1 << 4) /* Bit 4: UART1 power/clock control */
|
||||
/* Bit 5: Reserved */
|
||||
#define SYSCON_PCONP_PCPWM1 (1 << 6) /* Bit 6: PWM1 power/clock control */
|
||||
#define SYSCON_PCONP_PCI2C0 (1 << 7) /* Bit 7: I2C0 power/clock control */
|
||||
#define SYSCON_PCONP_PCSPI (1 << 8) /* Bit 8: SPI power/clock control */
|
||||
#define SYSCON_PCONP_PCRTC (1 << 9) /* Bit 9: RTC power/clock control */
|
||||
#define SYSCON_PCONP_PCSSP1 (1 << 10) /* Bit 10: SSP 1 power/clock control */
|
||||
/* Bit 11: Reserved */
|
||||
#define SYSCON_PCONP_PCADC (1 << 12) /* Bit 12: A/D converter (ADC) power/clock control */
|
||||
#define SYSCON_PCONP_PCCAN1 (1 << 13) /* Bit 13: CAN Controller 1 power/clock control */
|
||||
#define SYSCON_PCONP_PCCAN2 (1 << 14) /* Bit 14: CAN Controller 2 power/clock control */
|
||||
#define SYSCON_PCONP_PCGPIO (1 << 15) /* Bit 15: GPIOs power/clock enable */
|
||||
#define SYSCON_PCONP_PCRIT (1 << 16) /* Bit 16: Repetitive Interrupt Timer power/clock control */
|
||||
#define SYSCON_PCONP_PCMCPWM (1 << 17) /* Bit 17: Motor Control PWM */
|
||||
#define SYSCON_PCONP_PCQEI (1 << 18) /* Bit 18: Quadrature Encoder power/clock control */
|
||||
#define SYSCON_PCONP_PCI2C1 (1 << 19) /* Bit 19: I2C1 power/clock control */
|
||||
/* Bit 20: Reserved */
|
||||
#define SYSCON_PCONP_PCSSP0 (1 << 21) /* Bit 21: SSP0 power/clock control */
|
||||
#define SYSCON_PCONP_PCTIM2 (1 << 22) /* Bit 22: Timer 2 power/clock control */
|
||||
#define SYSCON_PCONP_PCTIM3 (1 << 23) /* Bit 23: Timer 3 power/clock control */
|
||||
#define SYSCON_PCONP_PCUART2 (1 << 24) /* Bit 24: UART 2 power/clock control */
|
||||
#define SYSCON_PCONP_PCUART3 (1 << 25) /* Bit 25: UART 3 power/clock control */
|
||||
#define SYSCON_PCONP_PCI2C2 (1 << 26) /* Bit 26: I2C 2 power/clock control */
|
||||
#define SYSCON_PCONP_PCI2S (1 << 27) /* Bit 27: I2S power/clock control */
|
||||
/* Bit 28: Reserved */
|
||||
#define SYSCON_PCONP_PCGPDMA (1 << 29) /* Bit 29: GPDMA function power/clock control */
|
||||
#define SYSCON_PCONP_PCENET (1 << 30) /* Bit 30: Ethernet block power/clock control */
|
||||
#define SYSCON_PCONP_PCUSB (1 << 31) /* Bit 31: USB power/clock control */
|
||||
|
||||
/* More clocking and power control -- Utility */
|
||||
|
||||
#define SYSCON_CLKOUTCFG_SEL_SHIFT (0) /* Bits 0-3: Selects clock source for CLKOUT */
|
||||
#define SYSCON_CLKOUTCFG_SEL_MASK (15 << SYSCON_CLKOUTCFG_SEL_SHIFT)
|
||||
# define SYSCON_CLKOUTCFG_SEL_CPU (0 << SYSCON_CLKOUTCFG_SEL_SHIFT) /* CLKOUT source=CPU clock */
|
||||
# define SYSCON_CLKOUTCFG_SEL_MAIN (1 << SYSCON_CLKOUTCFG_SEL_SHIFT) /* CLKOUT source=main osc */
|
||||
# define SYSCON_CLKOUTCFG_SEL_INTRC (2 << SYSCON_CLKOUTCFG_SEL_SHIFT) /* CLKOUT source=internal RC osc */
|
||||
# define SYSCON_CLKOUTCFG_SEL_USB (3 << SYSCON_CLKOUTCFG_SEL_SHIFT) /* CLKOUT source=USB clock */
|
||||
# define SYSCON_CLKOUTCFG_SEL_RTC (4 << SYSCON_CLKOUTCFG_SEL_SHIFT) /* CLKOUT source=RTC osc */
|
||||
#define SYSCON_CLKOUTCFG_DIV_SHIFT (4) /* Bits 4-7: CLKOUT divisor */
|
||||
#define SYSCON_CLKOUTCFG_DIV_MASK (15 << SYSCON_CLKOUTCFG_DIV_SHIFT)
|
||||
# define SYSCON_CLKOUTCFG_DIV(n) ((n-1) << SYSCON_CLKOUTCFG_DIV_SHIFT) /* n=1..16 */
|
||||
#define SYSCON_CLKOUTCFG_EN (1 << 8) /* Bit 8: CLKOUT enable control */
|
||||
#define SYSCON_CLKOUTCFG_ACT (1 << 9) /* Bit 9: CLKOUT activity indication */
|
||||
/* Bits 10-31: Reserved */
|
||||
/* System control registers -- External Interrupts */
|
||||
/* External Interrupt Flag register */
|
||||
|
||||
#define SYSCON_EXTINT_EINT0 (1 << 0) /* Bit 0: EINT0 */
|
||||
#define SYSCON_EXTINT_EINT1 (1 << 1) /* Bit 1: EINT1 */
|
||||
#define SYSCON_EXTINT_EINT2 (1 << 2) /* Bit 2: EINT2 */
|
||||
#define SYSCON_EXTINT_EINT3 (1 << 3) /* Bit 3: EINT3 */
|
||||
/* Bits 4-31: Reserved */
|
||||
/* External Interrupt Mode register */
|
||||
|
||||
#define SYSCON_EXTMODE_EINT0 (1 << 0) /* Bit 0: 1=EINT0 edge sensitive */
|
||||
#define SYSCON_EXTMODE_EINT1 (1 << 1) /* Bit 1: 1=EINT1 edge sensitive */
|
||||
#define SYSCON_EXTMODE_EINT2 (1 << 2) /* Bit 2: 1=EINT2 edge sensitive */
|
||||
#define SYSCON_EXTMODE_EINT3 (1 << 3) /* Bit 3: 1=EINT3 edge sensitive */
|
||||
/* Bits 4-31: Reserved */
|
||||
/* External Interrupt Polarity register */
|
||||
|
||||
#define SYSCON_EXTPOLAR_EINT0 (1 << 0) /* Bit 0: 1=EINT0 high active/rising edge */
|
||||
#define SYSCON_EXTPOLAR_EINT1 (1 << 1) /* Bit 1: 1=EINT1 high active/rising edge */
|
||||
#define SYSCON_EXTPOLAR_EINT2 (1 << 2) /* Bit 2: 1=EINT2 high active/rising edge */
|
||||
#define SYSCON_EXTPOLAR_EINT3 (1 << 3) /* Bit 3: 1=EINT3 high active/rising edge */
|
||||
/* Bits 4-31: Reserved */
|
||||
/* System control registers -- Reset */
|
||||
/* Reset Source Identification Register */
|
||||
|
||||
#define SYSCON_RSID_POR (1 << 0) /* Bit 0: Power on reset */
|
||||
#define SYSCON_RSID_EXTR (1 << 1) /* Bit 1: external RESET signal */
|
||||
#define SYSCON_RSID_WDTR (1 << 2) /* Bit 2: Watchdog Timer time out w/WDTRESET */
|
||||
#define SYSCON_RSID_BODR (1 << 3) /* Bit 3: Brown out detection */
|
||||
/* Bits 4-31: Reserved */
|
||||
/* System control registers -- Syscon Miscellaneous Registers */
|
||||
|
||||
/* Bits 0-3: Reserved */
|
||||
#define SYSCON_SCS_OSCRS (1 << 4) /* Bit 4: Main oscillator range select */
|
||||
#define SYSCON_SCS_OSCEN (1 << 5) /* Bit 5: Main oscillator enable */
|
||||
#define SYSCON_SCS_OSCSTAT (1 << 6) /* Bit 6: Main oscillator status */
|
||||
/* Bits 7-31: Reserved */
|
||||
/* Device Interrupt Registers */
|
||||
/* USB Interrupt Status register */
|
||||
|
||||
#define SYSCON_USBINTST_REQLP (1 << 0) /* Bit 0: Low priority interrupt line status */
|
||||
#define SYSCON_USBINTST_REQHP (1 << 1) /* Bit 1: High priority interrupt line status */
|
||||
#define SYSCON_USBINTST_REQDMA (1 << 2) /* Bit 2: DMA interrupt line status */
|
||||
#define SYSCON_USBINTST_HOSTINT (1 << 3) /* Bit 3: USB host interrupt line status */
|
||||
#define SYSCON_USBINTST_ATXINT (1 << 4) /* Bit 4: External ATX interrupt line status */
|
||||
#define SYSCON_USBINTST_OTGINT (1 << 5) /* Bit 5: OTG interrupt line status */
|
||||
#define SYSCON_USBINTST_I2CINT (1 << 6) /* Bit 6: I2C module interrupt line status */
|
||||
/* Bit 7: Reserved */
|
||||
#define SYSCON_USBINTST_NEEDCLK (1 << 8) /* Bit 8: USB need clock indicator */
|
||||
/* Bits 9-30: Reserved */
|
||||
#define SYSCON_USBINTST_ENINTS (1 << 31) /* Bit 31: Enable all USB interrupts */
|
||||
|
||||
/* DMA Request Select Register */
|
||||
|
||||
#define SYSCON_DMAREQSEL_INP8 (1 << 0) /* Bit 0: Input 8 0=UART0 TX 1=Timer 0 match 0 */
|
||||
#define SYSCON_DMAREQSEL_INP9 (1 << 1) /* Bit 1: Input 8 0=UART0 RX 1=Timer 0 match 1 */
|
||||
#define SYSCON_DMAREQSEL_INP10 (1 << 2) /* Bit 2: Input 8 0=UART1 TX 1=Timer 1 match 0 */
|
||||
#define SYSCON_DMAREQSEL_INP11 (1 << 3) /* Bit 3: Input 8 0=UART1 RX 1=Timer 1 match 1 */
|
||||
#define SYSCON_DMAREQSEL_INP12 (1 << 4) /* Bit 4: Input 8 0=UART2 TX 1=Timer 2 match 0 */
|
||||
#define SYSCON_DMAREQSEL_INP13 (1 << 5) /* Bit 5: Input 8 0=UART2 RX 1=Timer 2 match 1 */
|
||||
#define SYSCON_DMAREQSEL_INP14 (1 << 6) /* Bit 6: Input 8 0=UART3 TX 1=Timer 3 match 0 */
|
||||
#define SYSCON_DMAREQSEL_INP15 (1 << 7) /* Bit 7: Input 8 0=UART3 RX 1=Timer 3 match 1 */
|
||||
/* Bits 8-31: Reserved */
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC176X_SYSCON_H */
|
||||
@@ -1,375 +0,0 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/lpc17xx/hardware/lpc178x_iocon.h
|
||||
*
|
||||
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Rommel Marcelo
|
||||
* Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC178X_IOCON_H
|
||||
#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC178X_IOCON_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "hardware/lpc17_memorymap.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register offsets *****************************************************************/
|
||||
|
||||
#define LPC17_IOCON_PP_OFFSET(p) ((unsigned int)(p) << 2)
|
||||
#define LPC17_IOCON_PP0_OFFSET (0x0000) /* IOCON Port(n) register 0 */
|
||||
#define LPC17_IOCON_PP1_OFFSET (0x0004) /* IOCON Port(n) register 1 */
|
||||
#define LPC17_IOCON_PP2_OFFSET (0x0008) /* IOCON Port(n) register 2 */
|
||||
#define LPC17_IOCON_PP3_OFFSET (0x000c) /* IOCON Port(n) register 3 */
|
||||
#define LPC17_IOCON_PP4_OFFSET (0x0010) /* IOCON Port(n) register 4 */
|
||||
#define LPC17_IOCON_PP5_OFFSET (0x0014) /* IOCON Port(n) register 5 */
|
||||
#define LPC17_IOCON_PP6_OFFSET (0x0018) /* IOCON Port(n) register 6 */
|
||||
#define LPC17_IOCON_PP7_OFFSET (0x001c) /* IOCON Port(n) register 7 */
|
||||
#define LPC17_IOCON_PP8_OFFSET (0x0020) /* IOCON Port(n) register 8 */
|
||||
#define LPC17_IOCON_PP9_OFFSET (0x0024) /* IOCON Port(n) register 9 */
|
||||
#define LPC17_IOCON_PP10_OFFSET (0x0028) /* IOCON Port(n) register 10 */
|
||||
#define LPC17_IOCON_PP11_OFFSET (0x002c) /* IOCON Port(n) register 11 */
|
||||
#define LPC17_IOCON_PP12_OFFSET (0x0030) /* IOCON Port(n) register 12 */
|
||||
#define LPC17_IOCON_PP13_OFFSET (0x0034) /* IOCON Port(n) register 13 */
|
||||
#define LPC17_IOCON_PP14_OFFSET (0x0038) /* IOCON Port(n) register 14 */
|
||||
#define LPC17_IOCON_PP15_OFFSET (0x003c) /* IOCON Port(n) register 15 */
|
||||
#define LPC17_IOCON_PP16_OFFSET (0x0040) /* IOCON Port(n) register 16 */
|
||||
#define LPC17_IOCON_PP17_OFFSET (0x0044) /* IOCON Port(n) register 17 */
|
||||
#define LPC17_IOCON_PP18_OFFSET (0x0048) /* IOCON Port(n) register 18 */
|
||||
#define LPC17_IOCON_PP19_OFFSET (0x004c) /* IOCON Port(n) register 19 */
|
||||
#define LPC17_IOCON_PP20_OFFSET (0x0050) /* IOCON Port(n) register 20 */
|
||||
#define LPC17_IOCON_PP21_OFFSET (0x0054) /* IOCON Port(n) register 21 */
|
||||
#define LPC17_IOCON_PP22_OFFSET (0x0058) /* IOCON Port(n) register 22 */
|
||||
#define LPC17_IOCON_PP23_OFFSET (0x005c) /* IOCON Port(n) register 23 */
|
||||
#define LPC17_IOCON_PP24_OFFSET (0x0060) /* IOCON Port(n) register 24 */
|
||||
#define LPC17_IOCON_PP25_OFFSET (0x0064) /* IOCON Port(n) register 25 */
|
||||
#define LPC17_IOCON_PP26_OFFSET (0x0068) /* IOCON Port(n) register 26 */
|
||||
#define LPC17_IOCON_PP27_OFFSET (0x006c) /* IOCON Port(n) register 27 */
|
||||
#define LPC17_IOCON_PP28_OFFSET (0x0070) /* IOCON Port(n) register 28 */
|
||||
#define LPC17_IOCON_PP29_OFFSET (0x0074) /* IOCON Port(n) register 29 */
|
||||
#define LPC17_IOCON_PP30_OFFSET (0x0078) /* IOCON Port(n) register 30 */
|
||||
#define LPC17_IOCON_PP31_OFFSET (0x007c) /* IOCON Port(n) register 31 */
|
||||
|
||||
/* Register addresses ***************************************************************/
|
||||
|
||||
#define LPC17_IOCON_P_BASE(b) (LPC17_IOCON_BASE + ((unsigned int)(b) << 7))
|
||||
#define LPC17_IOCON_P0_BASE (LPC17_IOCON_BASE + 0x0000)
|
||||
#define LPC17_IOCON_P1_BASE (LPC17_IOCON_BASE + 0x0080)
|
||||
#define LPC17_IOCON_P2_BASE (LPC17_IOCON_BASE + 0x0100)
|
||||
#define LPC17_IOCON_P3_BASE (LPC17_IOCON_BASE + 0x0180)
|
||||
#define LPC17_IOCON_P4_BASE (LPC17_IOCON_BASE + 0x0200)
|
||||
#define LPC17_IOCON_P5_BASE (LPC17_IOCON_BASE + 0x0280)
|
||||
|
||||
#define LPC17_IOCON_P(b,p) (LPC17_IOCON_P_BASE(b) + LPC17_IOCON_PP_OFFSET(p))
|
||||
|
||||
#define LPC17_IOCON_P0_0 (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP0_OFFSET)
|
||||
#define LPC17_IOCON_P0_1 (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP1_OFFSET)
|
||||
#define LPC17_IOCON_P0_2 (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP2_OFFSET)
|
||||
#define LPC17_IOCON_P0_3 (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP3_OFFSET)
|
||||
#define LPC17_IOCON_P0_4 (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP4_OFFSET)
|
||||
#define LPC17_IOCON_P0_5 (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP5_OFFSET)
|
||||
#define LPC17_IOCON_P0_6 (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP6_OFFSET)
|
||||
#define LPC17_IOCON_P0_7 (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP7_OFFSET)
|
||||
#define LPC17_IOCON_P0_8 (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP8_OFFSET)
|
||||
#define LPC17_IOCON_P0_9 (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP9_OFFSET)
|
||||
#define LPC17_IOCON_P0_10 (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP10_OFFSET)
|
||||
#define LPC17_IOCON_P0_11 (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP11_OFFSET)
|
||||
#define LPC17_IOCON_P0_12 (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP12_OFFSET)
|
||||
#define LPC17_IOCON_P0_13 (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP13_OFFSET)
|
||||
#define LPC17_IOCON_P0_14 (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP14_OFFSET)
|
||||
#define LPC17_IOCON_P0_15 (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP15_OFFSET)
|
||||
#define LPC17_IOCON_P0_16 (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP16_OFFSET)
|
||||
#define LPC17_IOCON_P0_17 (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP17_OFFSET)
|
||||
#define LPC17_IOCON_P0_18 (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP18_OFFSET)
|
||||
#define LPC17_IOCON_P0_19 (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP19_OFFSET)
|
||||
#define LPC17_IOCON_P0_20 (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP20_OFFSET)
|
||||
#define LPC17_IOCON_P0_21 (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP21_OFFSET)
|
||||
#define LPC17_IOCON_P0_22 (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP22_OFFSET)
|
||||
#define LPC17_IOCON_P0_23 (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP23_OFFSET)
|
||||
#define LPC17_IOCON_P0_24 (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP24_OFFSET)
|
||||
#define LPC17_IOCON_P0_25 (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP25_OFFSET)
|
||||
#define LPC17_IOCON_P0_26 (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP26_OFFSET)
|
||||
#define LPC17_IOCON_P0_27 (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP27_OFFSET)
|
||||
#define LPC17_IOCON_P0_28 (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP28_OFFSET)
|
||||
#define LPC17_IOCON_P0_29 (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP29_OFFSET)
|
||||
#define LPC17_IOCON_P0_30 (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP30_OFFSET)
|
||||
#define LPC17_IOCON_P0_31 (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP31_OFFSET)
|
||||
|
||||
#define LPC17_IOCON_P1_0 (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP0_OFFSET)
|
||||
#define LPC17_IOCON_P1_1 (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP1_OFFSET)
|
||||
#define LPC17_IOCON_P1_2 (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP2_OFFSET)
|
||||
#define LPC17_IOCON_P1_3 (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP3_OFFSET)
|
||||
#define LPC17_IOCON_P1_4 (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP4_OFFSET)
|
||||
#define LPC17_IOCON_P1_5 (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP5_OFFSET)
|
||||
#define LPC17_IOCON_P1_6 (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP6_OFFSET)
|
||||
#define LPC17_IOCON_P1_7 (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP7_OFFSET)
|
||||
#define LPC17_IOCON_P1_8 (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP8_OFFSET)
|
||||
#define LPC17_IOCON_P1_9 (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP9_OFFSET)
|
||||
#define LPC17_IOCON_P1_10 (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP10_OFFSET)
|
||||
#define LPC17_IOCON_P1_11 (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP11_OFFSET)
|
||||
#define LPC17_IOCON_P1_12 (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP12_OFFSET)
|
||||
#define LPC17_IOCON_P1_13 (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP13_OFFSET)
|
||||
#define LPC17_IOCON_P1_14 (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP14_OFFSET)
|
||||
#define LPC17_IOCON_P1_15 (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP15_OFFSET)
|
||||
#define LPC17_IOCON_P1_16 (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP16_OFFSET)
|
||||
#define LPC17_IOCON_P1_17 (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP17_OFFSET)
|
||||
#define LPC17_IOCON_P1_18 (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP18_OFFSET)
|
||||
#define LPC17_IOCON_P1_19 (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP19_OFFSET)
|
||||
#define LPC17_IOCON_P1_20 (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP20_OFFSET)
|
||||
#define LPC17_IOCON_P1_21 (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP21_OFFSET)
|
||||
#define LPC17_IOCON_P1_22 (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP22_OFFSET)
|
||||
#define LPC17_IOCON_P1_23 (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP23_OFFSET)
|
||||
#define LPC17_IOCON_P1_24 (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP24_OFFSET)
|
||||
#define LPC17_IOCON_P1_25 (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP25_OFFSET)
|
||||
#define LPC17_IOCON_P1_26 (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP26_OFFSET)
|
||||
#define LPC17_IOCON_P1_27 (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP27_OFFSET)
|
||||
#define LPC17_IOCON_P1_28 (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP28_OFFSET)
|
||||
#define LPC17_IOCON_P1_29 (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP29_OFFSET)
|
||||
#define LPC17_IOCON_P1_30 (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP30_OFFSET)
|
||||
#define LPC17_IOCON_P1_31 (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP31_OFFSET)
|
||||
|
||||
#define LPC17_IOCON_P2_0 (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP0_OFFSET)
|
||||
#define LPC17_IOCON_P2_1 (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP1_OFFSET)
|
||||
#define LPC17_IOCON_P2_2 (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP2_OFFSET)
|
||||
#define LPC17_IOCON_P2_3 (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP3_OFFSET)
|
||||
#define LPC17_IOCON_P2_4 (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP4_OFFSET)
|
||||
#define LPC17_IOCON_P2_5 (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP5_OFFSET)
|
||||
#define LPC17_IOCON_P2_6 (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP6_OFFSET)
|
||||
#define LPC17_IOCON_P2_7 (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP7_OFFSET)
|
||||
#define LPC17_IOCON_P2_8 (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP8_OFFSET)
|
||||
#define LPC17_IOCON_P2_9 (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP9_OFFSET)
|
||||
#define LPC17_IOCON_P2_10 (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP10_OFFSET)
|
||||
#define LPC17_IOCON_P2_11 (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP11_OFFSET)
|
||||
#define LPC17_IOCON_P2_12 (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP12_OFFSET)
|
||||
#define LPC17_IOCON_P2_13 (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP13_OFFSET)
|
||||
#define LPC17_IOCON_P2_14 (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP14_OFFSET)
|
||||
#define LPC17_IOCON_P2_15 (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP15_OFFSET)
|
||||
#define LPC17_IOCON_P2_16 (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP16_OFFSET)
|
||||
#define LPC17_IOCON_P2_17 (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP17_OFFSET)
|
||||
#define LPC17_IOCON_P2_18 (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP18_OFFSET)
|
||||
#define LPC17_IOCON_P2_19 (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP19_OFFSET)
|
||||
#define LPC17_IOCON_P2_20 (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP20_OFFSET)
|
||||
#define LPC17_IOCON_P2_21 (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP21_OFFSET)
|
||||
#define LPC17_IOCON_P2_22 (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP22_OFFSET)
|
||||
#define LPC17_IOCON_P2_23 (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP23_OFFSET)
|
||||
#define LPC17_IOCON_P2_24 (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP24_OFFSET)
|
||||
#define LPC17_IOCON_P2_25 (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP25_OFFSET)
|
||||
#define LPC17_IOCON_P2_26 (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP26_OFFSET)
|
||||
#define LPC17_IOCON_P2_27 (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP27_OFFSET)
|
||||
#define LPC17_IOCON_P2_28 (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP28_OFFSET)
|
||||
#define LPC17_IOCON_P2_29 (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP29_OFFSET)
|
||||
#define LPC17_IOCON_P2_30 (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP30_OFFSET)
|
||||
#define LPC17_IOCON_P2_31 (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP31_OFFSET)
|
||||
|
||||
#define LPC17_IOCON_P3_0 (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP0_OFFSET)
|
||||
#define LPC17_IOCON_P3_1 (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP1_OFFSET)
|
||||
#define LPC17_IOCON_P3_2 (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP2_OFFSET)
|
||||
#define LPC17_IOCON_P3_3 (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP3_OFFSET)
|
||||
#define LPC17_IOCON_P3_4 (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP4_OFFSET)
|
||||
#define LPC17_IOCON_P3_5 (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP5_OFFSET)
|
||||
#define LPC17_IOCON_P3_6 (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP6_OFFSET)
|
||||
#define LPC17_IOCON_P3_7 (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP7_OFFSET)
|
||||
#define LPC17_IOCON_P3_8 (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP8_OFFSET)
|
||||
#define LPC17_IOCON_P3_9 (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP9_OFFSET)
|
||||
#define LPC17_IOCON_P3_10 (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP10_OFFSET)
|
||||
#define LPC17_IOCON_P3_11 (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP11_OFFSET)
|
||||
#define LPC17_IOCON_P3_12 (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP12_OFFSET)
|
||||
#define LPC17_IOCON_P3_13 (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP13_OFFSET)
|
||||
#define LPC17_IOCON_P3_14 (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP14_OFFSET)
|
||||
#define LPC17_IOCON_P3_15 (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP15_OFFSET)
|
||||
#define LPC17_IOCON_P3_16 (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP16_OFFSET)
|
||||
#define LPC17_IOCON_P3_17 (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP17_OFFSET)
|
||||
#define LPC17_IOCON_P3_18 (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP18_OFFSET)
|
||||
#define LPC17_IOCON_P3_19 (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP19_OFFSET)
|
||||
#define LPC17_IOCON_P3_20 (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP20_OFFSET)
|
||||
#define LPC17_IOCON_P3_21 (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP21_OFFSET)
|
||||
#define LPC17_IOCON_P3_22 (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP22_OFFSET)
|
||||
#define LPC17_IOCON_P3_23 (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP23_OFFSET)
|
||||
#define LPC17_IOCON_P3_24 (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP24_OFFSET)
|
||||
#define LPC17_IOCON_P3_25 (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP25_OFFSET)
|
||||
#define LPC17_IOCON_P3_26 (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP26_OFFSET)
|
||||
#define LPC17_IOCON_P3_27 (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP27_OFFSET)
|
||||
#define LPC17_IOCON_P3_28 (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP28_OFFSET)
|
||||
#define LPC17_IOCON_P3_29 (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP29_OFFSET)
|
||||
#define LPC17_IOCON_P3_30 (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP30_OFFSET)
|
||||
#define LPC17_IOCON_P3_31 (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP31_OFFSET)
|
||||
|
||||
#define LPC17_IOCON_P4_0 (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP0_OFFSET)
|
||||
#define LPC17_IOCON_P4_1 (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP1_OFFSET)
|
||||
#define LPC17_IOCON_P4_2 (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP2_OFFSET)
|
||||
#define LPC17_IOCON_P4_3 (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP3_OFFSET)
|
||||
#define LPC17_IOCON_P4_4 (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP4_OFFSET)
|
||||
#define LPC17_IOCON_P4_5 (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP5_OFFSET)
|
||||
#define LPC17_IOCON_P4_6 (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP6_OFFSET)
|
||||
#define LPC17_IOCON_P4_7 (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP7_OFFSET)
|
||||
#define LPC17_IOCON_P4_8 (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP8_OFFSET)
|
||||
#define LPC17_IOCON_P4_9 (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP9_OFFSET)
|
||||
#define LPC17_IOCON_P4_10 (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP10_OFFSET)
|
||||
#define LPC17_IOCON_P4_11 (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP11_OFFSET)
|
||||
#define LPC17_IOCON_P4_12 (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP12_OFFSET)
|
||||
#define LPC17_IOCON_P4_13 (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP13_OFFSET)
|
||||
#define LPC17_IOCON_P4_14 (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP14_OFFSET)
|
||||
#define LPC17_IOCON_P4_15 (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP15_OFFSET)
|
||||
#define LPC17_IOCON_P4_16 (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP16_OFFSET)
|
||||
#define LPC17_IOCON_P4_17 (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP17_OFFSET)
|
||||
#define LPC17_IOCON_P4_18 (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP18_OFFSET)
|
||||
#define LPC17_IOCON_P4_19 (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP19_OFFSET)
|
||||
#define LPC17_IOCON_P4_20 (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP20_OFFSET)
|
||||
#define LPC17_IOCON_P4_21 (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP21_OFFSET)
|
||||
#define LPC17_IOCON_P4_22 (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP22_OFFSET)
|
||||
#define LPC17_IOCON_P4_23 (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP23_OFFSET)
|
||||
#define LPC17_IOCON_P4_24 (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP24_OFFSET)
|
||||
#define LPC17_IOCON_P4_25 (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP25_OFFSET)
|
||||
#define LPC17_IOCON_P4_26 (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP26_OFFSET)
|
||||
#define LPC17_IOCON_P4_27 (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP27_OFFSET)
|
||||
#define LPC17_IOCON_P4_28 (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP28_OFFSET)
|
||||
#define LPC17_IOCON_P4_29 (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP29_OFFSET)
|
||||
#define LPC17_IOCON_P4_30 (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP30_OFFSET)
|
||||
#define LPC17_IOCON_P4_31 (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP31_OFFSET)
|
||||
|
||||
#define LPC17_IOCON_P5_0 (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP0_OFFSET)
|
||||
#define LPC17_IOCON_P5_1 (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP1_OFFSET)
|
||||
#define LPC17_IOCON_P5_2 (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP2_OFFSET)
|
||||
#define LPC17_IOCON_P5_3 (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP3_OFFSET)
|
||||
#define LPC17_IOCON_P5_4 (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP4_OFFSET)
|
||||
#define LPC17_IOCON_P5_5 (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP5_OFFSET)
|
||||
#define LPC17_IOCON_P5_6 (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP6_OFFSET)
|
||||
#define LPC17_IOCON_P5_7 (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP7_OFFSET)
|
||||
#define LPC17_IOCON_P5_8 (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP8_OFFSET)
|
||||
#define LPC17_IOCON_P5_9 (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP9_OFFSET)
|
||||
#define LPC17_IOCON_P5_10 (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP10_OFFSET)
|
||||
#define LPC17_IOCON_P5_11 (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP11_OFFSET)
|
||||
#define LPC17_IOCON_P5_12 (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP12_OFFSET)
|
||||
#define LPC17_IOCON_P5_13 (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP13_OFFSET)
|
||||
#define LPC17_IOCON_P5_14 (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP14_OFFSET)
|
||||
#define LPC17_IOCON_P5_15 (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP15_OFFSET)
|
||||
#define LPC17_IOCON_P5_16 (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP16_OFFSET)
|
||||
#define LPC17_IOCON_P5_17 (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP17_OFFSET)
|
||||
#define LPC17_IOCON_P5_18 (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP18_OFFSET)
|
||||
#define LPC17_IOCON_P5_19 (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP19_OFFSET)
|
||||
#define LPC17_IOCON_P5_20 (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP20_OFFSET)
|
||||
#define LPC17_IOCON_P5_21 (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP21_OFFSET)
|
||||
#define LPC17_IOCON_P5_22 (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP22_OFFSET)
|
||||
#define LPC17_IOCON_P5_23 (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP23_OFFSET)
|
||||
#define LPC17_IOCON_P5_24 (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP24_OFFSET)
|
||||
#define LPC17_IOCON_P5_25 (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP25_OFFSET)
|
||||
#define LPC17_IOCON_P5_26 (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP26_OFFSET)
|
||||
#define LPC17_IOCON_P5_27 (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP27_OFFSET)
|
||||
#define LPC17_IOCON_P5_28 (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP28_OFFSET)
|
||||
#define LPC17_IOCON_P5_29 (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP29_OFFSET)
|
||||
#define LPC17_IOCON_P5_30 (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP30_OFFSET)
|
||||
#define LPC17_IOCON_P5_31 (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP31_OFFSET)
|
||||
|
||||
/* Register bit definitions *********************************************************/
|
||||
/* IOCON pin function select */
|
||||
|
||||
#define IOCON_FUNC_GPIO (0)
|
||||
#define IOCON_FUNC_ALT1 (1)
|
||||
#define IOCON_FUNC_ALT2 (2)
|
||||
#define IOCON_FUNC_ALT3 (3)
|
||||
#define IOCON_FUNC_ALT4 (4)
|
||||
#define IOCON_FUNC_ALT5 (5)
|
||||
#define IOCON_FUNC_ALT6 (6)
|
||||
#define IOCON_FUNC_ALT7 (7)
|
||||
|
||||
#define IOCON_FUNC_SHIFT (0) /* Bits 0-2: All types */
|
||||
#define IOCON_FUNC_MASK (7 << IOCON_FUNC_SHIFT)
|
||||
#define IOCON_MODE_SHIFT (3) /* Bits 3-4: Type D,A,W */
|
||||
#define IOCON_MODE_MASK (3 << IOCON_MODE_SHIFT )
|
||||
#define IOCON_HYS_SHIFT (5) /* Bit 5: Type D,W */
|
||||
#define IOCON_HYS_MASK (1 << IOCON_HYS_SHIFT)
|
||||
#define IOCON_INV_SHIFT (6) /* Bit 6: Type D,A,I,W */
|
||||
#define IOCON_INV_MASK (1 << IOCON_INV_SHIFT)
|
||||
#define IOCON_ADMODE_SHIFT (7) /* Bit 7: Type A */
|
||||
#define IOCON_ADMODE_MASK (1 << IOCON_ADMODE_SHIFT)
|
||||
#define IOCON_FILTER_SHIFT (8) /* Bit 8: Type A */
|
||||
#define IOCON_FILTER_MASK (1 << IOCON_FILTER_SHIFT)
|
||||
#define IOCON_I2CHS_SHIFT (8) /* Bit 8: Type I */
|
||||
#define IOCON_I2CHS_MASK (1 << IOCON_I2CHS_SHIFT)
|
||||
#define IOCON_SLEW_SHIFT (9) /* Bit 9: Type W */
|
||||
#define IOCON_SLEW_MASK (1 << IOCON_SLEW_SHIFT)
|
||||
#define IOCON_HIDRIVE_SHIFT (9) /* Bit 9: Type I */
|
||||
#define IOCON_HIDRIVE_MASK (1 << IOCON_HIDRIVE_SHIFT)
|
||||
#define IOCON_OD_SHIFT (10) /* Bit 10: Type D,A,W */
|
||||
#define IOCON_OD_MASK (1 << IOCON_OD_SHIFT)
|
||||
#define IOCON_DACEN_SHIFT (16) /* Bit 16: Type A */
|
||||
#define IOCON_DACEN_MASK (1 << IOCON_DACEN_SHIFT)
|
||||
|
||||
/* Pin modes */
|
||||
|
||||
#define IOCON_MODE_FLOAT (0) /* 00: pin has neither pull-up nor pull-down */
|
||||
#define IOCON_MODE_PD (1) /* 01: pin has a pull-down resistor enabled */
|
||||
#define IOCON_MODE_PU (2) /* 10: pin has a pull-up resistor enabled */
|
||||
#define IOCON_MODE_RM (3) /* 11: pin has repeater mode enabled */
|
||||
|
||||
/* Pin types */
|
||||
|
||||
#define IOCON_TYPE_D_MASK (0x0000067f) /* All ports except where ADC/DAC, USB, I2C is present */
|
||||
#define IOCON_TYPE_A_MASK (0x000105df) /* USB/ADC/DAC P0:12-13, P0:23-26, P1:30-31 */
|
||||
#define IOCON_TYPE_U_MASK (0x00000007) /* USB P0:29 to 31 */
|
||||
#define IOCON_TYPE_I_MASK (0x00000347) /* I2C/USB P0:27-28, P5:2-3 */
|
||||
#define IOCON_TYPE_W_MASK (0x000007ff) /* I2S P0:7-9 */
|
||||
|
||||
/* Slew rate modes */
|
||||
|
||||
#define IOCON_SLEWMODE_NORMAL (0 << IOCON_SLEW_SHIFT)
|
||||
#define IOCON_SLEWMODE_FAST (1 << IOCON_SLEW_SHIFT)
|
||||
|
||||
/* I2C modes */
|
||||
|
||||
#define IOCON_I2CMODE_SHIFT (IOCON_I2CHS_SHIFT)
|
||||
#define IOCON_I2CMODE_MASK (3 << IOCON_I2CMODE_SHIFT)
|
||||
# define IOCON_I2CMODE_FAST (0 << IOCON_I2CMODE_SHIFT)
|
||||
# define IOCON_I2CMODE_FASTPLUS (1 << IOCON_I2CMODE_SHIFT)/* */
|
||||
# define IOCON_I2CMODE_HIOPENDRAIN (2 << IOCON_I2CMODE_SHIFT)/* */
|
||||
# define IOCON_I2CMODE_OPENDRAIN (3 << IOCON_I2CMODE_SHIFT)/* */
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC178X_IOCON_H */
|
||||
@@ -1,158 +0,0 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/lpc17xx/hardware/lpc178x_memorymap.h
|
||||
*
|
||||
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
|
||||
* Authors: Rommel Marcelo
|
||||
* Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC178X_MEMORYMAP_H
|
||||
#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC178X_MEMORYMAP_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
/* Memory Map ***********************************************************************/
|
||||
|
||||
#define LPC17_FLASH_BASE 0x00000000 /* -0x1fffffff: On-chip non-volatile memory */
|
||||
#define LPC17_SRAM_BASE 0x10000000 /* -0x10007fff: On-chip SRAM (devices <=32Kb) */
|
||||
#define LPC17_ROM_BASE 0x1fff0000 /* -0x1fffffff: 8Kb Boot ROM with flash services */
|
||||
#define LPC17_AHBSRAM_BASE 0x20000000 /* -0x3fffffff: On-chip Peripheral SRAM (devices >32Kb) */
|
||||
# define LPC17_SRAM_BANK0 0x20000000 /* -0x20003fff: On-chip Peripheral SRAM Bank0 (devices >=32Kb) */
|
||||
# define LPC17_SRAM_BANK1 0x20004000 /* -0x20007fff: On-chip Peripheral SRAM Bank1 (devices 64Kb) */
|
||||
#define LPC17_AHB_BASE 0x20080000 /* -0x2008ffff: DMA Controller, Ethernet, and USB */
|
||||
#define LPC17_SPIFI_BASE 0x28000000
|
||||
#define LPC17_APB_BASE 0x40000000 /* -0x5fffffff: APB Peripherals */
|
||||
# define LPC17_APB0_BASE 0x40000000 /* -0x4007ffff: APB0 Peripherals */
|
||||
# define LPC17_APB1_BASE 0x40080000 /* -0x400fffff: APB1 Peripherals */
|
||||
|
||||
/* Off chip Memory via External Memory Interface */
|
||||
|
||||
#define LPC17_EXTRAM_BASE 0x80000000 /* */
|
||||
# define LPC17_EXTSRAM_CS0 0x80000000 /* Chip select 0 /up to 64MB/ */
|
||||
# define LPC17_EXTSRAM_CS1 0x90000000 /* Chip select 1 /up to 64MB/ */
|
||||
# define LPC17_EXTSRAM_CS2 0x98000000 /* Chip select 2 /up to 64MB/ */
|
||||
# define LPC17_EXTSRAM_CS3 0x9c000000 /* Chip select 3 /up to 64MB/ */
|
||||
|
||||
# define LPC17_EXTDRAM_CS0 0xa0000000 /* Chip select 0 /up to 256MB/ */
|
||||
# define LPC17_EXTDRAM_CS1 0xb0000000 /* Chip select 1 /up to 256MB/ */
|
||||
# define LPC17_EXTDRAM_CS2 0xc0000000 /* Chip select 2 /up to 256MB/ */
|
||||
# define LPC17_EXTDRAM_CS3 0xd0000000 /* Chip select 3 /up to 256MB/ */
|
||||
|
||||
#define LPC17_CORTEXM3_BASE 0xe0000000 /* -0xe00fffff: (see armv7-m/nvic.h) */
|
||||
#define LPC17_SCS_BASE 0xe000e000
|
||||
#define LPC17_DEBUGMCU_BASE 0xe0042000
|
||||
|
||||
/* AHB SRAM Bank sizes **************************************************************/
|
||||
|
||||
#define LPC17_BANK0_SIZE (16*1024) /* Size of AHB SRAM Bank0 (if present) */
|
||||
#define LPC17_BANK1_SIZE (16*1024) /* Size of AHB SRAM Bank1 (if present) */
|
||||
|
||||
/* APB0 Peripherals *****************************************************************/
|
||||
|
||||
#define LPC17_WDT_BASE 0x40000000 /* -0x40003fff: Watchdog timer */
|
||||
#define LPC17_TMR0_BASE 0x40004000 /* -0x40007fff: Timer 0 */
|
||||
#define LPC17_TMR1_BASE 0x40008000 /* -0x4000bfff: Timer 1 */
|
||||
#define LPC17_UART0_BASE 0x4000c000 /* -0x4000ffff: UART 0 */
|
||||
#define LPC17_UART1_BASE 0x40010000 /* -0x40013fff: UART 1 */
|
||||
#define LPC17_PWM0_BASE 0x40014000 /* -0x40017fff: PWM 0 */
|
||||
#define LPC17_PWM1_BASE 0x40018000 /* -0x4001bfff: PWM 1 */
|
||||
#define LPC17_I2C0_BASE 0x4001c000 /* -0x4001ffff: I2C 0 */
|
||||
/* -0x40023fff: Reserved */
|
||||
#define LPC17_RTC_BASE 0x40024000 /* -0x40027fff: RTC + backup registers */
|
||||
#define LPC17_GPIOINT_BASE 0x40028000 /* -0x4002bfff: GPIO interrupts */
|
||||
#define LPC17_IOCON_BASE 0x4002c000 /* -0x4002ffff: Pin connect block */
|
||||
#define LPC17_SSP1_BASE 0x40030000 /* -0x40033fff: SSP 1 */
|
||||
#define LPC17_ADC_BASE 0x40034000 /* -0x40037fff: ADC */
|
||||
#define LPC17_CANAFRAM_BASE 0x40038000 /* -0x4003bfff: CAN acceptance filter (AF) RAM */
|
||||
#define LPC17_CANAF_BASE 0x4003c000 /* -0x4003ffff: CAN acceptance filter (AF) registers */
|
||||
#define LPC17_CAN_BASE 0x40040000 /* -0x40043fff: CAN common registers */
|
||||
#define LPC17_CAN1_BASE 0x40044000 /* -0x40047fff: CAN controller l */
|
||||
#define LPC17_CAN2_BASE 0x40048000 /* -0x4004bfff: CAN controller 2 */
|
||||
/* -0x4005bfff: Reserved */
|
||||
#define LPC17_I2C1_BASE 0x4005c000 /* -0x4005ffff: I2C 1 */
|
||||
/* -0x4007ffff: Reserved */
|
||||
|
||||
/* APB1 Peripherals *****************************************************************/
|
||||
|
||||
/* -0x40087fff: Reserved */
|
||||
#define LPC17_SSP0_BASE 0x40088000 /* -0x4008bfff: SSP 0 */
|
||||
#define LPC17_DAC_BASE 0x4008c000 /* -0x4008ffff: DAC */
|
||||
#define LPC17_TMR2_BASE 0x40090000 /* -0x40093fff: Timer 2 */
|
||||
#define LPC17_TMR3_BASE 0x40094000 /* -0x40097fff: Timer 3 */
|
||||
#define LPC17_UART2_BASE 0x40098000 /* -0x4009bfff: UART 2 */
|
||||
#define LPC17_UART3_BASE 0x4009c000 /* -0x4009ffff: UART 3 */
|
||||
#define LPC17_I2C2_BASE 0x400a0000 /* -0x400a3fff: I2C 2 */
|
||||
#define LPC17_UART4_BASE 0x400a4000 /* -0x400a7fff: UART4 */
|
||||
#define LPC17_I2S_BASE 0x400a8000 /* -0x400abfff: I2S */
|
||||
#define LPC17_SSP2_BASE 0x400ac000 /* -0x400affff: SSP2 */
|
||||
/* -0x400b3fff: Reserved */
|
||||
/* -0x400b7fff: Reserved */
|
||||
#define LPC17_MCPWM_BASE 0x400b8000 /* -0x400bbfff: Motor control PWM */
|
||||
#define LPC17_QEI_BASE 0x400bc000 /* -0x400bffff: Quadrature encoder interface */
|
||||
#define LPC17_MCI_BASE 0x400c0000 /* -0x400fbfff: SD interface */
|
||||
#define LPC17_SYSCON_BASE 0x400fc000 /* -0x400fffff: System control */
|
||||
|
||||
/* AHB Peripherals ******************************************************************/
|
||||
|
||||
#define LPC17_GPDMA_BASE 0x20080000 /* GPDMA controller */
|
||||
#define LPC17_ETH_BASE 0x20084000 /* Ethernet controller */
|
||||
#define LPC17_LCD_BASE 0x20088000 /* LCD controller */
|
||||
#define LPC17_USB_BASE 0x2008c000 /* USB controller */
|
||||
#define LPC17_CRC_BASE 0x20090000 /* CRC engine */
|
||||
#define LPC17_GPIO_BASE 0x20098000 /* GPIO */
|
||||
#define LPC17_EMC_BASE 0x2009c000 /* External Memory Controller */
|
||||
|
||||
/* EEPROM */
|
||||
|
||||
#define LPC17_EEPROM_BASE 0x00200000 /* EEPROM controller */
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC178X_MEMORYMAP_H */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,186 +0,0 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/lpc17xx/hardware/lpc17_eeprom.h
|
||||
*
|
||||
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_EEPROM_H
|
||||
#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_EEPROM_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "hardware/lpc17_memorymap.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register offsets *****************************************************************/
|
||||
|
||||
#define LPC17_EEPROM_EECMD_OFFSET 0x0080 /* Command register */
|
||||
#define LPC17_EEPROM_EEADDR_OFFSET 0x0084 /* Address register */
|
||||
#define LPC17_EEPROM_EEWDATA_OFFSET 0x0088 /* Write Data register */
|
||||
#define LPC17_EEPROM_EERDATA_OFFSET 0x008c /* Read Data register */
|
||||
#define LPC17_EEPROM_EEWSTATE_OFFSET 0x0090 /* Wait state register */
|
||||
#define LPC17_EEPROM_EECLKDIV_OFFSET 0x0094 /* Clock divider register */
|
||||
#define LPC17_EEPROM_EEPWRDWN_OFFSET 0x0098 /* Power down register */
|
||||
|
||||
#define LPC17_EEPROM_INTSTAT_OFFSET 0x0fe0 /* Interrupt status */
|
||||
#define LPC17_EEPROM_INTEN_OFFSET 0x0fe4 /* Interrupt enable */
|
||||
#define LPC17_EEPROM_INTSTATCLR_OFFSET 0x0fe8 /* Interrupt status clear */
|
||||
#define LPC17_EEPROM_INTENCLR_OFFSET 0x0fd8 /* Interrupt enable clear */
|
||||
#define LPC17_EEPROM_INTENSET_OFFSET 0x0fdc /* Interrupt enable set */
|
||||
#define LPC17_EEPROM_INTSTATSET_OFFSET 0x0fec /* Interrupt status set */
|
||||
|
||||
#define LPC17_EEPROM_EECMD (LPC17_EEPROM_BASE+LPC17_EEPROM_EECMD_OFFSET)
|
||||
#define LPC17_EEPROM_EEADDR (LPC17_EEPROM_BASE+LPC17_EEPROM_EEADDR_OFFSET)
|
||||
#define LPC17_EEPROM_EEWDATA (LPC17_EEPROM_BASE+LPC17_EEPROM_EEWDATA_OFFSET)
|
||||
#define LPC17_EEPROM_EERDATA (LPC17_EEPROM_BASE+LPC17_EEPROM_EERDATA_OFFSET)
|
||||
#define LPC17_EEPROM_EEWSTATE (LPC17_EEPROM_BASE+LPC17_EEPROM_EEWSTATE_OFFSET)
|
||||
#define LPC17_EEPROM_EECLKDIV (LPC17_EEPROM_BASE+LPC17_EEPROM_EECLKDIV_OFFSET)
|
||||
#define LPC17_EEPROM_EEPWRDWN (LPC17_EEPROM_BASE+LPC17_EEPROM_EEPWRDWN_OFFSET)
|
||||
|
||||
#define LPC17_EEPROM_INTSTAT (LPC17_EEPROM_BASE+LPC17_EEPROM_INTSTAT_OFFSET)
|
||||
#define LPC17_EEPROM_INTEN (LPC17_EEPROM_BASE+LPC17_EEPROM_INTEN_OFFSET)
|
||||
#define LPC17_EEPROM_INTSTATCLR (LPC17_EEPROM_BASE+LPC17_EEPROM_INTSTATCLR_OFFSET)
|
||||
#define LPC17_EEPROM_INTENCLR (LPC17_EEPROM_BASE+LPC17_EEPROM_INTENCLR_OFFSET)
|
||||
#define LPC17_EEPROM_INTENSET (LPC17_EEPROM_BASE+LPC17_EEPROM_INTENSET_OFFSET)
|
||||
#define LPC17_EEPROM_INTSTATSET (LPC17_EEPROM_BASE+LPC17_EEPROM_INTSTATSET_OFFSET)
|
||||
|
||||
/* EECMD - EEPROM Command Register */
|
||||
|
||||
#define EEPROM_CMD_SHIFT (0) /* Bit 0-2: Command */
|
||||
#define EEPROM_CMD_MASK (7 << EEPROM_CMD_SHIFT)
|
||||
# define EECMD_READ8 (0) /* 000: 8bit read */
|
||||
# define EECMD_READ16 (1) /* 001: 16bit read */
|
||||
# define EECMD_READ32 (2) /* 010: 32bit read */
|
||||
# define EECMD_WRITE8 (3) /* 011: 8bit write */
|
||||
# define EECMD_WRITE16 (4) /* 100: 16bit write */
|
||||
# define EECMD_WRITE32 (5) /* 101: 32bit write */
|
||||
# define EEMCD_ERASE (6) /* 110: erase/program page */
|
||||
/* 111: Reserved */
|
||||
#define EEPROM_RDPREFETCH (1 << 3) /* Bit 3: Read data prefetch bit */
|
||||
/* Bits 4-31: Reserved */
|
||||
/* EEADDR - EEPROM Address Register */
|
||||
|
||||
#define EEPROM_ADDR_SHIFT (0) /* Bits 0-11: Address */
|
||||
#define EEPROM_ADDR_MASK (0x7ff << EEPROM_EEADDR_ADDR_SHIFT)
|
||||
/* Bits 12-31: Reserved */
|
||||
/* EEPROM Read/Write Data Registers */
|
||||
/* R/W registers has no bitfields, data read/write
|
||||
* must conforms to the expected sizes
|
||||
*/
|
||||
|
||||
/* EEWSTATE - EEPROM Wait State Register */
|
||||
|
||||
#define EEPROM_WSTATE_PHASE3_SHIFT (0) /* Bits 0-7: Wait states 3 (minus 1 encoded) */
|
||||
#define EEPROM_WSTATE_PHASE3_MASK (0xff << EEWSTATE_PHASE3_SHIFT)
|
||||
#define EEPROM_WSTATE_PHASE2_SHIFT (8) /* Bits 8-15: Wait states 2 (minus 1 encoded) */
|
||||
#define EEPROM_WSTATE_PHASE2_MASK (0xff << EEWSTATE_PHASE2_SHIFT)
|
||||
#define EEPROM_WSTATE_PHASE1_SHIFT (16) /* Bits 16-23: Wait states 1 (minus 1 encoded) */
|
||||
#define EEPROM_WSTATE_PHASE1_MASK (0xff << EEWSTATE_PHASE1_SHIFT)
|
||||
/* Bits 24-31: Reserved */
|
||||
|
||||
/* EECLKDIV - EEPROM Clock Divider Register */
|
||||
|
||||
#define EEPROM_CLKDIV_SHIFT (0) /* Bits 0-15: Division factor (minus 1 encoded) */
|
||||
#define EEPROM_CLKDIV_MASK (0xffff << EECLKDIV_CLKDIV_SHIFT)
|
||||
/* Bits 16-31: Reserved */
|
||||
|
||||
/* EEPWRDWN - EEPROM Power Down Register */
|
||||
|
||||
#define EEPROM_PWRDWN (1) /* Bit 0: Power down mode bit */
|
||||
/* Bits 1-31: Reserved */
|
||||
|
||||
/* EEPROM Interrupt Registers ******************************************/
|
||||
|
||||
/* INTEN - Interrupt Enable Register */
|
||||
|
||||
/* Bits 0-25: Reserved */
|
||||
#define EEPROM_INTEN_RW_DONE (1 << 26) /* Bit 26: Read/Write finished interrupt bit */
|
||||
/* Bit 27: Reserved */
|
||||
#define EEPROM_INTEN_PROG_DONE (1 << 28) /* Bit 28: Program finished interrupt bit */
|
||||
/* Bits 29-31: Reserved */
|
||||
|
||||
/* INTENCLR - Interrupt Enable Clear Register */
|
||||
/* Bits 0-25: Reserved */
|
||||
#define EEPROM_INTENCLR_RWCLR_EN (1 << 26) /* Bit 26: Clear R/W interrupt enable bit */
|
||||
/* Bits27: Reserved */
|
||||
#define EEPROM_INTENCLR_PROG1CLR_EN (1 << 28) /* Bit 28: Clear program interrupt bit */
|
||||
/* Bits 29-31: Reserved */
|
||||
|
||||
/* INTENSET - Interrupt Enable Set Register */
|
||||
/* Bits 0-25: Reserved */
|
||||
#define EEPROM_INTENSET_RWSET_EN (1 << 26) /* Bit 26: Set Read/Write finished interrupt bit */
|
||||
/* Bit 27: Reserved */
|
||||
#define EEPROM_INTENSET_PROG1SET_EN (1 << 28) /* Bit 28: Set program interrupt bit */
|
||||
/* Bits 29-31: Reserved */
|
||||
|
||||
/* INTSTAT - Interrupt Status Register */
|
||||
/* Bits 0-25: Reserved */
|
||||
#define EEPROM_INTSTAT_RW_END (1 << 26) /* Bit 26: Read/Write done status bit */
|
||||
/* Bit 27: Reserved */
|
||||
#define EEPROM_INTSTAT_PROG1_END (1 << 28) /* Bit 28: Program done status bit */
|
||||
/* Bits 29-31: Reserved */
|
||||
|
||||
/* INTSTATCLR - Interrupt Status Clear Register */
|
||||
/* Bits 0-25: Reserved */
|
||||
#define EEPROM_INTSTATCLR_RW_CLR (1 << 26) /* Bit 26: Set Read/Write finished interrupt bit */
|
||||
/* Bit 27: Reserved */
|
||||
#define EEPROM_INTSTATCLR_PROG_1CLR (1 << 28) /* Bit 28: Set program interrupt bit */
|
||||
/* Bits 29-31: Reserved */
|
||||
|
||||
/* INTSTATSET - Interrupt Status Set Register */
|
||||
/* Bits 0-25: Reserved */
|
||||
#define EEPROM_INTSTATSET_RW_SET (1 << 26) /* Bit 26: Read/Write done status bit */
|
||||
/* Bit 27: Reserved */
|
||||
#define EEPROM_INTSTATSET_PROG1_SET (1 << 28) /* Bit 28: Program done status bit */
|
||||
/* Bits 29-31: Reserved */
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_EEPROM_H */
|
||||
@@ -1,350 +0,0 @@
|
||||
/****************************************************************************************************
|
||||
* arch/arm/src/lpc17xx/hardware/lpc17_emc
|
||||
*
|
||||
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_EMC_H
|
||||
#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_EMC_H
|
||||
|
||||
/****************************************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "hardware/lpc17_memorymap.h"
|
||||
|
||||
/****************************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************************************/
|
||||
/* Register Offsets */
|
||||
|
||||
#define LPC17_EMC_CONTROL_OFFSET 0x0000 /* EMC Control register */
|
||||
#define LPC17_EMC_STATUS_OFFSET 0x0004 /* EMC Status register */
|
||||
#define LPC17_EMC_CONFIG_OFFSET 0x0008 /* EMC Configuration register */
|
||||
#define LPC17_EMC_DYNAMICCONTROL_OFFSET 0x0020 /* Dynamic Memory Control register */
|
||||
#define LPC17_EMC_DYNAMICREFRESH_OFFSET 0x0024 /* Dynamic Memory Refresh Timer register */
|
||||
#define LPC17_EMC_DYNAMICREADCONFIG_OFFSET 0x0028 /* Dynamic Memory Read Configuration register */
|
||||
#define LPC17_EMC_DYNAMICRP_OFFSET 0x0030 /* Dynamic Memory Precharge Command Period register */
|
||||
#define LPC17_EMC_DYNAMICRAS_OFFSET 0x0034 /* Dynamic Memory Active to Precharge Command Period register */
|
||||
#define LPC17_EMC_DYNAMICSREX_OFFSET 0x0038 /* Dynamic Memory Self-refresh Exit Time register */
|
||||
#define LPC17_EMC_DYNAMICAPR_OFFSET 0x003c /* Dynamic Memory Last Data Out to Active Time register */
|
||||
#define LPC17_EMC_DYNAMICDAL_OFFSET 0x0040 /* Dynamic Memory Data-in to Active Command Time register */
|
||||
#define LPC17_EMC_DYNAMICWR_OFFSET 0x0044 /* Dynamic Memory Write Recovery Time register */
|
||||
#define LPC17_EMC_DYNAMICRC_OFFSET 0x0048 /* Dynamic Memory Active to Active Command Period register */
|
||||
#define LPC17_EMC_DYNAMICRFC_OFFSET 0x004c /* Dynamic Memory Auto-refresh Period register */
|
||||
#define LPC17_EMC_DYNAMICXSR_OFFSET 0x0050 /* Dynamic Memory Exit Self-refresh register */
|
||||
#define LPC17_EMC_DYNAMICRRD_OFFSET 0x0054 /* Dynamic Memory Active Bank A to Active Bank B Time register */
|
||||
#define LPC17_EMC_DYNAMICMRD_OFFSET 0x0058 /* Dynamic Memory Load Mode register to Active Command Time */
|
||||
#define LPC17_EMC_STATICEXTENDEDWAIT_OFFSET 0x0080 /* Static Memory Extended Wait register */
|
||||
|
||||
#define LPC17_EMC_DYNAMICCONFIG0_OFFSET 0x0100 /* Dynamic Memory Configuration register 0 */
|
||||
#define LPC17_EMC_DYNAMICRASCAS0_OFFSET 0x0104 /* Dynamic Memory RAS & CAS Delay register 0 */
|
||||
|
||||
#define LPC17_EMC_DYNAMICCONFIG1_OFFSET 0x0120 /* Dynamic Memory Configuration register 1 */
|
||||
#define LPC17_EMC_DYNAMICRASCAS1_OFFSET 0x0124 /* Dynamic Memory RAS & CAS Delay register 1 */
|
||||
|
||||
#define LPC17_EMC_DYNAMICCONFIG2_OFFSET 0x0140 /* Dynamic Memory Configuration register 2 */
|
||||
#define LPC17_EMC_DYNAMICRASCAS2_OFFSET 0x0144 /* Dynamic Memory RAS & CAS Delay register 2 */
|
||||
|
||||
#define LPC17_EMC_DYNAMICCONFIG3_OFFSET 0x0160 /* Dynamic Memory Configuration register 3 */
|
||||
#define LPC17_EMC_DYNAMICRASCAS3_OFFSET 0x0164 /* Dynamic Memory RAS & CAS Delay register 3 */
|
||||
|
||||
#define LPC17_EMC_STATICCONFIG0_OFFSET 0x0200 /* Static Memory Configuration register 0 */
|
||||
#define LPC17_EMC_STATICWAITWEN0_OFFSET 0x0204 /* Static Memory Write Enable Delay register 0 */
|
||||
#define LPC17_EMC_STATICWAITOEN0_OFFSET 0x0208 /* Static Memory Output Enable Delay registers 0 */
|
||||
#define LPC17_EMC_STATICWAITRD0_OFFSET 0x020c /* Static Memory Read Delay register 0 */
|
||||
#define LPC17_EMC_STATICWAITPAGE0_OFFSET 0x0210 /* Static Memory Page Mode Read Delay register 0*/
|
||||
#define LPC17_EMC_STATICWAITWR0_OFFSET 0x0214 /* Static Memory Write Delay register 0 */
|
||||
#define LPC17_EMC_STATICWAITTURN0_OFFSET 0x0218 /* Static Memory Turn Round Delay register 0 */
|
||||
|
||||
#define LPC17_EMC_STATICCONFIG1_OFFSET 0x0220 /* Static Memory Configuration register 1 */
|
||||
#define LPC17_EMC_STATICWAITWEN1_OFFSET 0x0224 /* Static Memory Write Enable Delay register 1 */
|
||||
#define LPC17_EMC_STATICWAITOEN1_OFFSET 0x0228 /* Static Memory Output Enable Delay register 1 */
|
||||
#define LPC17_EMC_STATICWAITRD1_OFFSET 0x022c /* Static Memory Read Delay register 1 */
|
||||
#define LPC17_EMC_STATICWAITPAGE1_OFFSET 0x0230 /* Static Memory Page Mode Read Delay register 1 */
|
||||
#define LPC17_EMC_STATICWAITWR1_OFFSET 0x0234 /* Static Memory Write Delay register 1 */
|
||||
#define LPC17_EMC_STATICWAITTURN1_OFFSET 0x0238 /* Static Memory Turn Round Delay register 1 */
|
||||
|
||||
#define LPC17_EMC_STATICCONFIG2_OFFSET 0x0240 /* Static Memory Configuration register 2 */
|
||||
#define LPC17_EMC_STATICWAITWEN2_OFFSET 0x0244 /* Static Memory Write Enable Delay register 2 */
|
||||
#define LPC17_EMC_STATICWAITOEN2_OFFSET 0x0248 /* Static Memory Output Enable Delay register 2 */
|
||||
#define LPC17_EMC_STATICWAITRD2_OFFSET 0x024c /* Static Memory Read Delay register 2 */
|
||||
#define LPC17_EMC_STATICWAITPAGE2_OFFSET 0x0250 /* Static Memory Page Mode Read Delay registers 3 */
|
||||
#define LPC17_EMC_STATICWAITWR2_OFFSET 0x0254 /* Static Memory Write Delay register 2 */
|
||||
#define LPC17_EMC_EMCSTATICWAITTURN2_OFFSET 0x0258 /* Static Memory Turn Round Delay register 2 */
|
||||
|
||||
#define LPC17_EMC_STATICCONFIG3_OFFSET 0x0260 /* Static Memory Configuration register 3 */
|
||||
#define LPC17_EMC_STATICWAITWEN3_OFFSET 0x0264 /* Static Memory Write Enable Delay register 3 */
|
||||
#define LPC17_EMC_STATICWAITOEN3_OFFSET 0x0268 /* Static Memory Output Enable Delay register 3 */
|
||||
#define LPC17_EMC_STATICWAITRD3_OFFSET 0x026c /* Static Memory Read Delay register 3 */
|
||||
#define LPC17_EMC_STATICWAITPAGE3_OFFSET 0x0270 /* Static Memory Page Mode Read Delay register 4 */
|
||||
#define LPC17_EMC_STATICWAITWR3_OFFSET 0x0274 /* Static Memory Write Delay register 3 */
|
||||
#define LPC17_EMC_STATICWAITTURN3_OFFSET 0x0278 /* Static Memory Turn Round Delay register 3 */
|
||||
|
||||
/* Register Addresses */
|
||||
|
||||
#define LPC17_EMC_CONTROL (LPC17_EMC_BASE+LPC17_EMC_CONTROL_OFFSET)
|
||||
#define LPC17_EMC_STATUS (LPC17_EMC_BASE+LPC17_EMC_STATUS_OFFSET)
|
||||
#define LPC17_EMC_CONFIG (LPC17_EMC_BASE+LPC17_EMC_CONFIG_OFFSET)
|
||||
#define LPC17_EMC_DYNAMICCONTROL (LPC17_EMC_BASE+LPC17_EMC_DYNAMICCONTROL_OFFSET)
|
||||
#define LPC17_EMC_DYNAMICREFRESH (LPC17_EMC_BASE+LPC17_EMC_DYNAMICREFRESH_OFFSET)
|
||||
#define LPC17_EMC_DYNAMICREADCONFIG (LPC17_EMC_BASE+LPC17_EMC_DYNAMICREADCONFIG_OFFSET)
|
||||
#define LPC17_EMC_DYNAMICRP (LPC17_EMC_BASE+LPC17_EMC_DYNAMICRP_OFFSET)
|
||||
#define LPC17_EMC_DYNAMICRAS (LPC17_EMC_BASE+LPC17_EMC_DYNAMICRAS_OFFSET)
|
||||
#define LPC17_EMC_DYNAMICSREX (LPC17_EMC_BASE+LPC17_EMC_DYNAMICSREX_OFFSET)
|
||||
#define LPC17_EMC_DYNAMICAPR (LPC17_EMC_BASE+LPC17_EMC_DYNAMICAPR_OFFSET)
|
||||
#define LPC17_EMC_DYNAMICDAL (LPC17_EMC_BASE+LPC17_EMC_DYNAMICDAL_OFFSET)
|
||||
#define LPC17_EMC_DYNAMICWR (LPC17_EMC_BASE+LPC17_EMC_DYNAMICWR_OFFSET)
|
||||
#define LPC17_EMC_DYNAMICRC (LPC17_EMC_BASE+LPC17_EMC_DYNAMICRC_OFFSET)
|
||||
#define LPC17_EMC_DYNAMICRFC (LPC17_EMC_BASE+LPC17_EMC_DYNAMICRFC_OFFSET)
|
||||
#define LPC17_EMC_DYNAMICXSR (LPC17_EMC_BASE+LPC17_EMC_DYNAMICXSR_OFFSET)
|
||||
#define LPC17_EMC_DYNAMICRRD (LPC17_EMC_BASE+LPC17_EMC_DYNAMICRRD_OFFSET)
|
||||
#define LPC17_EMC_DYNAMICMRD (LPC17_EMC_BASE+LPC17_EMC_DYNAMICMRD_OFFSET)
|
||||
#define LPC17_EMC_STATICEXTENDEDWAIT (LPC17_EMC_BASE+LPC17_EMC_STATICEXTENDEDWAIT_OFFSET)
|
||||
|
||||
#define LPC17_EMC_DYNAMICCONFIG0 (LPC17_EMC_BASE+LPC17_EMC_DYNAMICCONFIG0_OFFSET)
|
||||
#define LPC17_EMC_DYNAMICRASCAS0 (LPC17_EMC_BASE+LPC17_EMC_DYNAMICRASCAS0_OFFSET)
|
||||
|
||||
#define LPC17_EMC_DYNAMICCONFIG1 (LPC17_EMC_BASE+LPC17_EMC_DYNAMICCONFIG1_OFFSET)
|
||||
#define LPC17_EMC_DYNAMICRASCAS1 (LPC17_EMC_BASE+LPC17_EMC_DYNAMICRASCAS1_OFFSET)
|
||||
|
||||
#define LPC17_EMC_DYNAMICCONFIG2 (LPC17_EMC_BASE+LPC17_EMC_DYNAMICCONFIG2_OFFSET)
|
||||
#define LPC17_EMC_DYNAMICRASCAS2 (LPC17_EMC_BASE+LPC17_EMC_DYNAMICRASCAS2_OFFSET)
|
||||
|
||||
#define LPC17_EMC_DYNAMICCONFIG3 (LPC17_EMC_BASE+LPC17_EMC_DYNAMICCONFIG3_OFFSET)
|
||||
#define LPC17_EMC_DYNAMICRASCAS3 (LPC17_EMC_BASE+LPC17_EMC_DYNAMICRASCAS3_OFFSET)
|
||||
|
||||
#define LPC17_EMC_STATICCONFIG0 (LPC17_EMC_BASE+LPC17_EMC_STATICCONFIG0_OFFSET)
|
||||
#define LPC17_EMC_STATICWAITWEN0 (LPC17_EMC_BASE+LPC17_EMC_STATICWAITWEN0_OFFSET)
|
||||
#define LPC17_EMC_STATICWAITOEN0 (LPC17_EMC_BASE+LPC17_EMC_STATICWAITOEN0_OFFSET)
|
||||
#define LPC17_EMC_STATICWAITRD0 (LPC17_EMC_BASE+LPC17_EMC_STATICWAITRD0_OFFSET)
|
||||
#define LPC17_EMC_STATICWAITPAGE0 (LPC17_EMC_BASE+LPC17_EMC_STATICWAITPAGE0_OFFSET)
|
||||
#define LPC17_EMC_STATICWAITWR0 (LPC17_EMC_BASE+LPC17_EMC_STATICWAITWR0_OFFSET)
|
||||
#define LPC17_EMC_STATICWAITTURN0 (LPC17_EMC_BASE+LPC17_EMC_STATICWAITTURN0_OFFSET)
|
||||
|
||||
#define LPC17_EMC_STATICCONFIG1 (LPC17_EMC_BASE+LPC17_EMC_STATICCONFIG1_OFFSET)
|
||||
#define LPC17_EMC_STATICWAITWEN1 (LPC17_EMC_BASE+LPC17_EMC_STATICWAITWEN1_OFFSET)
|
||||
#define LPC17_EMC_STATICWAITOEN1 (LPC17_EMC_BASE+LPC17_EMC_STATICWAITOEN1_OFFSET)
|
||||
#define LPC17_EMC_STATICWAITRD (LPC17_EMC_BASE+LPC17_EMC_STATICWAITRD1_OFFSET)
|
||||
#define LPC17_EMC_STATICWAITPAGE1 (LPC17_EMC_BASE+LPC17_EMC_STATICWAITPAGE1_OFFSET)
|
||||
#define LPC17_EMC_STATICWAITWR1 (LPC17_EMC_BASE+LPC17_EMC_STATICWAITWR1_OFFSET)
|
||||
#define LPC17_EMC_STATICWAITTURN1 (LPC17_EMC_BASE+LPC17_EMC_STATICWAITTURN1_OFFSET)
|
||||
|
||||
#define LPC17_EMC_STATICCONFIG2 (LPC17_EMC_BASE+LPC17_EMC_STATICCONFIG2_OFFSET)
|
||||
#define LPC17_EMC_STATICWAITWEN2 (LPC17_EMC_BASE+LPC17_EMC_STATICWAITWEN2_OFFSET)
|
||||
#define LPC17_EMC_STATICWAITOEN2 (LPC17_EMC_BASE+LPC17_EMC_STATICWAITOEN2_OFFSET)
|
||||
#define LPC17_EMC_STATICWAITRD2 (LPC17_EMC_BASE+LPC17_EMC_STATICWAITRD2_OFFSET)
|
||||
#define LPC17_EMC_STATICWAITPAGE2 (LPC17_EMC_BASE+LPC17_EMC_STATICWAITPAGE2_OFFSET)
|
||||
#define LPC17_EMC_STATICWAITWR2 (LPC17_EMC_BASE+LPC17_EMC_STATICWAITWR2_OFFSET)
|
||||
#define LPC17_EMC_EMCSTATICWAITTURN2 (LPC17_EMC_BASE+LPC17_EMC_EMCSTATICWAITTURN2_OFFSET)
|
||||
|
||||
#define LPC17_EMC_STATICCONFIG3 (LPC17_EMC_BASE+LPC17_EMC_STATICCONFIG3_OFFSET)
|
||||
#define LPC17_EMC_STATICWAITWEN3 (LPC17_EMC_BASE+LPC17_EMC_STATICWAITWEN3_OFFSET)
|
||||
#define LPC17_EMC_STATICWAITOEN3 (LPC17_EMC_BASE+LPC17_EMC_STATICWAITOEN3_OFFSET)
|
||||
#define LPC17_EMC_STATICWAITRD3 (LPC17_EMC_BASE+LPC17_EMC_STATICWAITRD3_OFFSET)
|
||||
#define LPC17_EMC_STATICWAITPAGE3 (LPC17_EMC_BASE+LPC17_EMC_STATICWAITPAGE3_OFFSET)
|
||||
#define LPC17_EMC_STATICWAITWR3 (LPC17_EMC_BASE+LPC17_EMC_STATICWAITWR3_OFFSET)
|
||||
#define LPC17_EMC_STATICWAITTURN3 (LPC17_EMC_BASE+LPC17_EMC_STATICWAITTURN3_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions */
|
||||
|
||||
/* EMC Control register */
|
||||
|
||||
#define EMC_CONTROL_E (1 << 0) /* Bit 0: EMC Enable */
|
||||
#define EMC_CONTROL_M (1 << 1) /* Bit 1: Address mirror */
|
||||
#define EMC_CONTROL_L (1 << 2) /* Bit 2: Low-power mode */
|
||||
|
||||
/* EMC Status register */
|
||||
|
||||
#define EMC_STATUS_B (1 << 0) /* Bit 0: Busy */
|
||||
#define EMC_STATUS_S (1 << 1) /* Bit 1: Write buffer status */
|
||||
#define EMC_STATUS_SA (1 << 2) /* Bit 2: Self-refresh acknowledge */
|
||||
|
||||
/* EMC Configuration register */
|
||||
|
||||
#define EMC_CONFIG_EM (1 << 0) /* Bit 0: Endian mode */
|
||||
#define EMC_CONFIG_CLKR (1 << 8) /* Bit 8: CCLK:CLKOUT ratio */
|
||||
|
||||
/* Dynamic Memory Control register */
|
||||
|
||||
#define EMC_DYNAMICCONTROL_CE (1 << 0) /* Bit 0: Dynamic memory clock enable */
|
||||
#define EMC_DYNAMICCONTROL_CS (1 << 1) /* Bit 1: Dynamic memory clock control */
|
||||
#define EMC_DYNAMICCONTROL_SR (1 << 2) /* Bit 2: Self-refresh request */
|
||||
#define EMC_DYNAMICCONTROL_MMC (1 << 5) /* Bit 5: Memory clock control */
|
||||
#define EMC_DYNAMICCONTROL_I_SHIFT (7) /* Bits 7-8: SDRAM initialization */
|
||||
#define EMC_DYNAMICCONTROL_I_MASK (3 << EMC_DYNAMICCONTROL_I_SHIFT)
|
||||
# define EMC_DYNAMICCONTROL_I_NORMAL (0 << EMC_DYNAMICCONTROL_I_SHIFT) /* SDRAM NORMAL operation command */
|
||||
# define EMC_DYNAMICCONTROL_I_MODE (1 << EMC_DYNAMICCONTROL_I_SHIFT) /* SDRAM MODE command */
|
||||
# define EMC_DYNAMICCONTROL_I_PALL (2 << EMC_DYNAMICCONTROL_I_SHIFT) /* SDRAM PALL (precharge all) command */
|
||||
# define EMC_DYNAMICCONTROL_I_NOP (3 << EMC_DYNAMICCONTROL_I_SHIFT) /* SDRAM NOP (no operation) command) */
|
||||
|
||||
/* Dynamic Memory Refresh Timer register */
|
||||
|
||||
#define EMC_DYNAMICREFRESH_MASK (0x000007ff) /* Bits 0-10: REFRESH Refresh timer */
|
||||
|
||||
/* Dynamic Memory Read Configuration register */
|
||||
|
||||
#define EMC_DYNAMICREADCONFIG_RD_SHIFT (0) /* Bits 0-1: Read data strategy */
|
||||
#define EMC_DYNAMICREADCONFIG_RD_MASK (3 << EMC_DYNAMICREADCONFIG_RD_SHIFT)
|
||||
# define EMC_DYNAMICREADCONFIG_RD_CLKOUT (0 << EMC_DYNAMICREADCONFIG_RD_SHIFT) /* Clock out delayed strategy */
|
||||
# define EMC_DYNAMICREADCONFIG_RD_CMD (1 << EMC_DYNAMICREADCONFIG_RD_SHIFT) /* Command delayed strategy */
|
||||
# define EMC_DYNAMICREADCONFIG_RD_CMD1 (2 << EMC_DYNAMICREADCONFIG_RD_SHIFT) /* Command delayed strategy + 1 cycle */
|
||||
# define EMC_DYNAMICREADCONFIG_RD_CMD2 (3 << EMC_DYNAMICREADCONFIG_RD_SHIFT) /* Command delayed strategy + 2 cycles */
|
||||
|
||||
/* Dynamic Memory Precharge Command Period register */
|
||||
|
||||
#define EMC_DYNAMICRP_TRP_MASK (0x0000000f) /* Bits 0-3: Precharge command period */
|
||||
|
||||
/* Dynamic Memory Active to Precharge Command Period register */
|
||||
|
||||
#define EMC_DYNAMICRAS_TRAS_MASK (0x0000000f) /* Bits 0-3: Active to precharge command period */
|
||||
|
||||
/* Dynamic Memory Self-refresh Exit Time register */
|
||||
|
||||
#define EMC_DYNAMICSREX_TSREX_MASK (0x0000000f) /* Bits 0-3: Self-refresh exit time */
|
||||
|
||||
/* Dynamic Memory Last Data Out to Active Time register */
|
||||
|
||||
#define EMC_DYNAMICAPR_TAPR_MASK (0x0000000f) /* Bits 0-3: Last-data-out to active command time */
|
||||
|
||||
/* Dynamic Memory Data-in to Active Command Time register */
|
||||
|
||||
#define EMC_DYNAMICDAL_TDAL_MASK (0x0000000f) /* Bits 0-3: Data-in to active command */
|
||||
|
||||
/* Dynamic Memory Write Recovery Time register */
|
||||
|
||||
#define EMC_DYNAMICWR_TWR_MASK (0x0000000f) /* Bits 0-3: Write recovery time */
|
||||
|
||||
/* Dynamic Memory Active to Active Command Period register */
|
||||
|
||||
#define EMC_DYNAMICRC_TRC_MASK (0x0000001f) /* Bits 0-4: Active to active command period */
|
||||
|
||||
/* Dynamic Memory Auto-refresh Period register */
|
||||
|
||||
#define EMC_DYNAMICRFC_TRFC_MASK (0x0000001f) /* Bits 0-4: Auto-refresh period and auto-refresh to active command period */
|
||||
|
||||
/* Dynamic Memory Exit Self-refresh register */
|
||||
|
||||
#define EMC_DYNAMICXSR_TXSR_MASK (0x0000001f) /* Bits 0-4: Exit self-refresh to active command time */
|
||||
|
||||
/* Dynamic Memory Active Bank A to Active Bank B Time register */
|
||||
|
||||
#define EMC_DYNAMICRRD_TRRD_MASK (0x0000000f) /* Bits 0-3: Active bank A to active bank B latency */
|
||||
|
||||
/* Dynamic Memory Load Mode register to Active Command Time */
|
||||
|
||||
#define EMC_DYNAMICMRD_TMRD_MASK (0x0000000f) /* Bits 0-3: Load mode register to active command time */
|
||||
|
||||
/* Static Memory Extended Wait register */
|
||||
|
||||
#define EMC_STATICEXTENDEDWAIT_MASK (0x000003ff) /* Bits 0-9: Extended wait time out */
|
||||
|
||||
/* Dynamic Memory Configuration registers (0-3) */
|
||||
|
||||
#define EMC_DYNAMICCONFIG_MD_SHIFT (3) /* Bits 3-4: Memory device */
|
||||
#define EMC_DYNAMICCONFIG_MD_MASK (3 << EMC_DYNAMICCONFIG_MD_SHIFT)
|
||||
# define EMC_DYNAMICCONFIG_MD_SDRAM (0 << EMC_DYNAMICCONFIG_MD_SHIFT) /* SDRAM */
|
||||
# define EMC_DYNAMICCONFIG_MD_LOWPOWER (1 << EMC_DYNAMICCONFIG_MD_SHIFT) /* Low-power SDRAM */
|
||||
#define EMC_DYNAMICCONFIG_AM0_SHIFT (7) /* Bits 7-12: */
|
||||
#define EMC_DYNAMICCONFIG_AM0_MASK (63 << EMC_DYNAMICCONFIG_AM0_SHIFT)
|
||||
# define EMC_DYNAMICCONFIG_AM0(n) ((n) << EMC_DYNAMICCONFIG_AM0_SHIFT)
|
||||
#define EMC_DYNAMICCONFIG_AM1 (1 << 14) /* Bit 14: */
|
||||
#define EMC_DYNAMICCONFIG_B (1 << 19) /* Bit 19: Buffer enable */
|
||||
#define EMC_DYNAMICCONFIG_P (1 << 20) /* Bit 20: Write protect */
|
||||
|
||||
/* Dynamic Memory RAS & CAS Delay registers (0-3) */
|
||||
|
||||
#define EMC_DYNAMICRASCAS_RAS_SHIFT (0) /* Bits 0-1: RAS latency (active to read/write delay) */
|
||||
#define EMC_DYNAMICRASCAS_RAS_MASK (3 << EMC_DYNAMICRASCAS_RAS_SHIFT)
|
||||
# define EMC_DYNAMICRASCAS_RAS_1CCLK (1 << EMC_DYNAMICRASCAS_RAS_SHIFT) /* One CCLK cycle */
|
||||
# define EMC_DYNAMICRASCAS_RAS_2CCLK (2 << EMC_DYNAMICRASCAS_RAS_SHIFT) /* Two CCLK cycles */
|
||||
# define EMC_DYNAMICRASCAS_RAS_3CCLK (3 << EMC_DYNAMICRASCAS_RAS_SHIFT) /* Three CCLK cycles */
|
||||
#define EMC_DYNAMICRASCAS_CAS_SHIFT (8) /* Bits 8-9: CAS latency */
|
||||
#define EMC_DYNAMICRASCAS_CAS_MASK (3 << EMC_DYNAMICRASCAS_CAS_SHIFT)
|
||||
# define EMC_DYNAMICRASCAS_CAS_1CCLK (1 << EMC_DYNAMICRASCAS_CAS_SHIFT) /* One CCLK cycle */
|
||||
# define EMC_DYNAMICRASCAS_CAS_2CCLK (2 << EMC_DYNAMICRASCAS_CAS_SHIFT) /* Two CCLK cycles */
|
||||
# define EMC_DYNAMICRASCAS_CAS_3CCLK (3 << EMC_DYNAMICRASCAS_CAS_SHIFT) /* Three CCLK cycles */
|
||||
|
||||
/* Static Memory Configuration registers (0-3) */
|
||||
|
||||
#define EMC_STATICCONFIG_MW_SHIFT (0) /* Bits 0-1: Memory width */
|
||||
#define EMC_STATICCONFIG_MW_MASK (3 << EMC_STATICCONFIG_MW_SHIFT)
|
||||
# define EMC_STATICCONFIG_MW_8BIT (0 << EMC_STATICCONFIG_MW_SHIFT)
|
||||
# define EMC_STATICCONFIG_MW_16BIT (1 << EMC_STATICCONFIG_MW_SHIFT)
|
||||
# define EMC_STATICCONFIG_MW_32BIT (2 << EMC_STATICCONFIG_MW_SHIFT)
|
||||
#define EMC_STATICCONFIG_PM (1 << 3) /* Bit 3: Page mode */
|
||||
#define EMC_STATICCONFIG_PC (1 << 6) /* Bit 6: Chip select polarity */
|
||||
#define EMC_STATICCONFIG_PB (1 << 7) /* Bit 7: Byte lane state */
|
||||
#define EMC_STATICCONFIG_EW (1 << 8) /* Bit 8: Extended wait */
|
||||
#define EMC_STATICCONFIG_B (1 << 19) /* Bit 19: Buffer enable */
|
||||
#define EMC_STATICCONFIG_P (1 << 20) /* Bit 20: Write protect */
|
||||
|
||||
/* Static Memory Write Enable Delay registers (0-3) */
|
||||
|
||||
#define EMC_STATICWAITWEN_MASK (0x0000000f) /* Bits 0-3: Wait write enable */
|
||||
|
||||
/* Static Memory Output Enable Delay registers (0-3) */
|
||||
|
||||
#define EMC_STATICWAITOEN_MASK (0x0000000f) /* Bits 0-3: Wait output enable */
|
||||
|
||||
/* Static Memory Read Delay registers (0-3) */
|
||||
|
||||
#define EMC_STATICWAITRD_MASK (0x0000001f) /* Bits 0-4: Exit self-refresh to active command time */
|
||||
|
||||
/* Static Memory Page Mode Read Delay registers (0-3) */
|
||||
|
||||
#define EMC_STATICWAITPAGE_MASK (0x0000001f) /* Bits 0-4: Asynchronous page mode read after the first read wait states */
|
||||
|
||||
/* Static Memory Write Delay registers (0-3) */
|
||||
|
||||
#define EMC_STATICWAITWR_MASK (0x0000001f) /* Bits 0-4: Write wait states */
|
||||
|
||||
/* Static Memory Turn Round Delay registers (0-3) */
|
||||
|
||||
#define EMC_STATICWAITTURN_MASK (0x0000000f) /* Bits 0-3: Bus turn-around cycles */
|
||||
|
||||
/****************************************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************************************/
|
||||
|
||||
/****************************************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************************************/
|
||||
|
||||
/****************************************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_EMC_H */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,210 +0,0 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/lpc17xx/hardware/lpc17_gpio.h
|
||||
*
|
||||
* Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_CHIP_GPIO_H
|
||||
#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_CHIP_GPIO_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "hardware/lpc17_memorymap.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register offsets *****************************************************************/
|
||||
/* GPIO block register offsets ******************************************************/
|
||||
|
||||
#define LPC17_FIO0_OFFSET 0x0000
|
||||
#define LPC17_FIO1_OFFSET 0x0020
|
||||
#define LPC17_FIO2_OFFSET 0x0040
|
||||
#define LPC17_FIO3_OFFSET 0x0060
|
||||
#define LPC17_FIO4_OFFSET 0x0080
|
||||
#ifdef LPC178x
|
||||
# define LPC17_FIO5_OFFSET 0x00a0
|
||||
#endif
|
||||
|
||||
#define LPC17_FIO_DIR_OFFSET 0x0000 /* Fast GPIO Port Direction control */
|
||||
#define LPC17_FIO_MASK_OFFSET 0x0010 /* Fast Mask register for ports */
|
||||
#define LPC17_FIO_PIN_OFFSET 0x0014 /* Fast Port Pin value registers */
|
||||
#define LPC17_FIO_SET_OFFSET 0x0018 /* Fast Port Output Set registers */
|
||||
#define LPC17_FIO_CLR_OFFSET 0x001c /* Fast Port Output Clear register */
|
||||
|
||||
/* GPIO interrupt block register offsets ********************************************/
|
||||
|
||||
#define LPC17_GPIOINT_OFFSET(n) (0x10*(n) + 0x80)
|
||||
#define LPC17_GPIOINT0_OFFSET 0x0080
|
||||
#define LPC17_GPIOINT2_OFFSET 0x00a0
|
||||
|
||||
#define LPC17_GPIOINT_IOINTSTATUS_OFFSET 0x0000 /* GPIO overall Interrupt Status */
|
||||
#define LPC17_GPIOINT_INTSTATR_OFFSET 0x0004 /* GPIO Interrupt Status Rising edge */
|
||||
#define LPC17_GPIOINT_INTSTATF_OFFSET 0x0008 /* GPIO Interrupt Status Falling edge */
|
||||
#define LPC17_GPIOINT_INTCLR_OFFSET 0x000c /* GPIO Interrupt Clear */
|
||||
#define LPC17_GPIOINT_INTENR_OFFSET 0x0010 /* GPIO Interrupt Enable Rising edge */
|
||||
#define LPC17_GPIOINT_INTENF_OFFSET 0x0014 /* GPIO Interrupt Enable Falling edge */
|
||||
|
||||
/* Register addresses ***************************************************************/
|
||||
/* GPIO block register addresses ****************************************************/
|
||||
|
||||
#define LPC17_FIO_BASE(n) (LPC17_GPIO_BASE+LPC17_GPIOINT_OFFSET(n))
|
||||
#define LPC17_FIO0_BASE (LPC17_GPIO_BASE+LPC17_FIO0_OFFSET)
|
||||
#define LPC17_FIO1_BASE (LPC17_GPIO_BASE+LPC17_FIO1_OFFSET)
|
||||
#define LPC17_FIO2_BASE (LPC17_GPIO_BASE+LPC17_FIO2_OFFSET)
|
||||
#define LPC17_FIO3_BASE (LPC17_GPIO_BASE+LPC17_FIO3_OFFSET)
|
||||
#define LPC17_FIO4_BASE (LPC17_GPIO_BASE+LPC17_FIO4_OFFSET)
|
||||
#ifdef LPC178x
|
||||
# define LPC17_FIO5_BASE (LPC17_GPIO_BASE+LPC17_FIO5_OFFSET)
|
||||
#endif
|
||||
|
||||
#define LPC17_FIO_DIR(n) (LPC17_FIO_BASE(n)+LPC17_FIO_DIR_OFFSET)
|
||||
#define LPC17_FIO_MASK(n) (LPC17_FIO_BASE(n)+LPC17_FIO_MASK_OFFSET)
|
||||
#define LPC17_FIO_PIN(n) (LPC17_FIO_BASE(n)+LPC17_FIO_PIN_OFFSET)
|
||||
#define LPC17_FIO_SET(n) (LPC17_FIO_BASE(n)+LPC17_FIO_SET_OFFSET)
|
||||
#define LPC17_FIO_CLR(n) (LPC17_FIO_BASE(n)+LPC17_FIO_CLR_OFFSET)
|
||||
|
||||
#define LPC17_FIO0_DIR (LPC17_FIO0_BASE+LPC17_FIO_DIR_OFFSET)
|
||||
#define LPC17_FIO0_MASK (LPC17_FIO0_BASE+LPC17_FIO_MASK_OFFSET)
|
||||
#define LPC17_FIO0_PIN (LPC17_FIO0_BASE+LPC17_FIO_PIN_OFFSET)
|
||||
#define LPC17_FIO0_SET (LPC17_FIO0_BASE+LPC17_FIO_SET_OFFSET)
|
||||
#define LPC17_FIO0_CLR (LPC17_FIO0_BASE+LPC17_FIO_CLR_OFFSET)
|
||||
|
||||
#define LPC17_FIO1_DIR (LPC17_FIO1_BASE+LPC17_FIO_DIR_OFFSET)
|
||||
#define LPC17_FIO1_MASK (LPC17_FIO1_BASE+LPC17_FIO_MASK_OFFSET)
|
||||
#define LPC17_FIO1_PIN (LPC17_FIO1_BASE+LPC17_FIO_PIN_OFFSET)
|
||||
#define LPC17_FIO1_SET (LPC17_FIO1_BASE+LPC17_FIO_SET_OFFSET)
|
||||
#define LPC17_FIO1_CLR (LPC17_FIO1_BASE+LPC17_FIO_CLR_OFFSET)
|
||||
|
||||
#define LPC17_FIO2_DIR (LPC17_FIO2_BASE+LPC17_FIO_DIR_OFFSET)
|
||||
#define LPC17_FIO2_MASK (LPC17_FIO2_BASE+LPC17_FIO_MASK_OFFSET)
|
||||
#define LPC17_FIO2_PIN (LPC17_FIO2_BASE+LPC17_FIO_PIN_OFFSET)
|
||||
#define LPC17_FIO2_SET (LPC17_FIO2_BASE+LPC17_FIO_SET_OFFSET)
|
||||
#define LPC17_FIO2_CLR (LPC17_FIO2_BASE+LPC17_FIO_CLR_OFFSET)
|
||||
|
||||
#define LPC17_FIO3_DIR (LPC17_FIO3_BASE+LPC17_FIO_DIR_OFFSET)
|
||||
#define LPC17_FIO3_MASK (LPC17_FIO3_BASE+LPC17_FIO_MASK_OFFSET)
|
||||
#define LPC17_FIO3_PIN (LPC17_FIO3_BASE+LPC17_FIO_PIN_OFFSET)
|
||||
#define LPC17_FIO3_SET (LPC17_FIO3_BASE+LPC17_FIO_SET_OFFSET)
|
||||
#define LPC17_FIO3_CLR (LPC17_FIO3_BASE+LPC17_FIO_CLR_OFFSET)
|
||||
|
||||
#define LPC17_FIO4_DIR (LPC17_FIO4_BASE+LPC17_FIO_DIR_OFFSET)
|
||||
#define LPC17_FIO4_MASK (LPC17_FIO4_BASE+LPC17_FIO_MASK_OFFSET)
|
||||
#define LPC17_FIO4_PIN (LPC17_FIO4_BASE+LPC17_FIO_PIN_OFFSET)
|
||||
#define LPC17_FIO4_SET (LPC17_FIO4_BASE+LPC17_FIO_SET_OFFSET)
|
||||
#define LPC17_FIO4_CLR (LPC17_FIO4_BASE+LPC17_FIO_CLR_OFFSET)
|
||||
|
||||
#ifdef LPC178x
|
||||
# define LPC17_FIO5_DIR (LPC17_FIO5_BASE+LPC17_FIO_DIR_OFFSET)
|
||||
# define LPC17_FIO5_MASK (LPC17_FIO5_BASE+LPC17_FIO_MASK_OFFSET)
|
||||
# define LPC17_FIO5_PIN (LPC17_FIO5_BASE+LPC17_FIO_PIN_OFFSET)
|
||||
# define LPC17_FIO5_SET (LPC17_FIO5_BASE+LPC17_FIO_SET_OFFSET)
|
||||
# define LPC17_FIO5_CLR (LPC17_FIO5_BASE+LPC17_FIO_CLR_OFFSET)
|
||||
#endif
|
||||
|
||||
/* GPIO interrupt block register addresses ******************************************/
|
||||
|
||||
#define LPC17_GPIOINTn_BASE(n) (LPC17_GPIOINT_BASE+LPC17_GPIOINT_OFFSET(n))
|
||||
#define LPC17_GPIOINT0_BASE (LPC17_GPIOINT_BASE+LPC17_GPIOINT0_OFFSET)
|
||||
#define LPC17_GPIOINT2_BASE (LPC17_GPIOINT_BASE+LPC17_GPIOINT2_OFFSET)
|
||||
|
||||
#define LPC17_GPIOINT_IOINTSTATUS (LPC17_GPIOINT0_BASE+LPC17_GPIOINT_IOINTSTATUS_OFFSET)
|
||||
|
||||
#define LPC17_GPIOINT_INTSTATR(n) (LPC17_GPIOINTn_BASE(n)+LPC17_GPIOINT_INTSTATR_OFFSET)
|
||||
#define LPC17_GPIOINT_INTSTATF(n) (LPC17_GPIOINTn_BASE(n)+LPC17_GPIOINT_INTSTATF_OFFSET)
|
||||
#define LPC17_GPIOINT_INTCLR(n) (LPC17_GPIOINTn_BASE(n)+LPC17_GPIOINT_INTCLR_OFFSET)
|
||||
#define LPC17_GPIOINT_INTENR(n) (LPC17_GPIOINTn_BASE(n)+LPC17_GPIOINT_INTENR_OFFSET)
|
||||
#define LPC17_GPIOINT_INTENF(n) (LPC17_GPIOINTn_BASE(n)+LPC17_GPIOINT_INTENF_OFFSET)
|
||||
|
||||
/* Pins P0.0-31 */
|
||||
|
||||
#define LPC17_GPIOINT0_INTSTATR (LPC17_GPIOINT0_BASE+LPC17_GPIOINT_INTSTATR_OFFSET)
|
||||
#define LPC17_GPIOINT0_INTSTATF (LPC17_GPIOINT0_BASE+LPC17_GPIOINT_INTSTATF_OFFSET)
|
||||
#define LPC17_GPIOINT0_INTCLR (LPC17_GPIOINT0_BASE+LPC17_GPIOINT_INTCLR_OFFSET)
|
||||
#define LPC17_GPIOINT0_INTENR (LPC17_GPIOINT0_BASE+LPC17_GPIOINT_INTENR_OFFSET)
|
||||
#define LPC17_GPIOINT0_INTENF (LPC17_GPIOINT0_BASE+LPC17_GPIOINT_INTENF_OFFSET)
|
||||
|
||||
/* Pins P2.0-31 */
|
||||
|
||||
#define LPC17_GPIOINT2_INTSTATR (LPC17_GPIOINT2_BASE+LPC17_GPIOINT_INTSTATR_OFFSET)
|
||||
#define LPC17_GPIOINT2_INTSTATF (LPC17_GPIOINT2_BASE+LPC17_GPIOINT_INTSTATF_OFFSET)
|
||||
#define LPC17_GPIOINT2_INTCLR (LPC17_GPIOINT2_BASE+LPC17_GPIOINT_INTCLR_OFFSET)
|
||||
#define LPC17_GPIOINT2_INTENR (LPC17_GPIOINT2_BASE+LPC17_GPIOINT_INTENR_OFFSET)
|
||||
#define LPC17_GPIOINT2_INTENF (LPC17_GPIOINT2_BASE+LPC17_GPIOINT_INTENF_OFFSET)
|
||||
|
||||
/* Register bit definitions *********************************************************/
|
||||
/* GPIO block register bit definitions **********************************************/
|
||||
|
||||
/* Fast GPIO Port Direction control registers (FIODIR) */
|
||||
/* Fast Mask register for ports (FIOMASK) */
|
||||
/* Fast Port Pin value registers using FIOMASK (FIOPIN) */
|
||||
/* Fast Port Output Set registers using FIOMASK (FIOSET) */
|
||||
/* Fast Port Output Clear register using FIOMASK (FIOCLR) */
|
||||
|
||||
#define FIO(n) (1 << (n)) /* n=0,1,..31 */
|
||||
|
||||
/* GPIO interrupt block register bit definitions ************************************/
|
||||
|
||||
/* GPIO overall Interrupt Status (IOINTSTATUS) */
|
||||
#define GPIOINT_IOINTSTATUS_P0INT (1 << 0) /* Bit 0: Port 0 GPIO interrupt pending */
|
||||
/* Bit 1: Reserved */
|
||||
#define GPIOINT_IOINTSTATUS_P2INT (1 << 2) /* Bit 2: Port 2 GPIO interrupt pending */
|
||||
/* Bits 3-31: Reserved */
|
||||
|
||||
/* GPIO Interrupt Status for Rising edge (INTSTATR)
|
||||
* GPIO Interrupt Status for Falling edge (INTSTATF)
|
||||
* GPIO Interrupt Clear (INTCLR)
|
||||
* GPIO Interrupt Enable for Rising edge (INTENR)
|
||||
* GPIO Interrupt Enable for Falling edge (INTENF)
|
||||
*/
|
||||
|
||||
#define GPIOINT(n) (1 << (n)) /* n=0,1,..31 */
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_CHIP_GPIO_H */
|
||||
@@ -1,208 +0,0 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/lpc17xx/hardware/lpc17_i2c.h
|
||||
*
|
||||
* Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_I2C_H
|
||||
#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_I2C_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "hardware/lpc17_memorymap.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register offsets *****************************************************************/
|
||||
|
||||
#define LPC17_I2C_CONSET_OFFSET 0x0000 /* I2C Control Set Register */
|
||||
#define LPC17_I2C_STAT_OFFSET 0x0004 /* I2C Status Register */
|
||||
#define LPC17_I2C_DAT_OFFSET 0x0008 /* I2C Data Register */
|
||||
#define LPC17_I2C_ADR0_OFFSET 0x000c /* I2C Slave Address Register 0 */
|
||||
#define LPC17_I2C_SCLH_OFFSET 0x0010 /* SCH Duty Cycle Register High Half Word */
|
||||
#define LPC17_I2C_SCLL_OFFSET 0x0014 /* SCL Duty Cycle Register Low Half Word */
|
||||
#define LPC17_I2C_CONCLR_OFFSET 0x0018 /* I2C Control Clear Register */
|
||||
#define LPC17_I2C_MMCTRL_OFFSET 0x001c /* Monitor mode control register */
|
||||
#define LPC17_I2C_ADR1_OFFSET 0x0020 /* I2C Slave Address Register 1 */
|
||||
#define LPC17_I2C_ADR2_OFFSET 0x0024 /* I2C Slave Address Register 2 */
|
||||
#define LPC17_I2C_ADR3_OFFSET 0x0028 /* I2C Slave Address Register 3 */
|
||||
#define LPC17_I2C_BUFR_OFFSET 0x002c /* Data buffer register */
|
||||
#define LPC17_I2C_MASK0_OFFSET 0x0030 /* I2C Slave address mask register 0 */
|
||||
#define LPC17_I2C_MASK1_OFFSET 0x0034 /* I2C Slave address mask register 1 */
|
||||
#define LPC17_I2C_MASK2_OFFSET 0x0038 /* I2C Slave address mask register 2 */
|
||||
#define LPC17_I2C_MASK3_OFFSET 0x003c /* I2C Slave address mask register */
|
||||
|
||||
/* Register addresses ***************************************************************/
|
||||
|
||||
#define LPC17_I2C0_CONSET (LPC17_I2C0_BASE+LPC17_I2C_CONSET_OFFSET)
|
||||
#define LPC17_I2C0_STAT (LPC17_I2C0_BASE+LPC17_I2C_STAT_OFFSET)
|
||||
#define LPC17_I2C0_DAT (LPC17_I2C0_BASE+LPC17_I2C_DAT_OFFSET)
|
||||
#define LPC17_I2C0_ADR0 (LPC17_I2C0_BASE+LPC17_I2C_ADR0_OFFSET)
|
||||
#define LPC17_I2C0_SCLH (LPC17_I2C0_BASE+LPC17_I2C_SCLH_OFFSET)
|
||||
#define LPC17_I2C0_SCLL (LPC17_I2C0_BASE+LPC17_I2C_SCLL_OFFSET)
|
||||
#define LPC17_I2C0_CONCLR (LPC17_I2C0_BASE+LPC17_I2C_CONCLR_OFFSET)
|
||||
#define LPC17_I2C0_MMCTRL (LPC17_I2C0_BASE+LPC17_I2C_MMCTRL_OFFSET)
|
||||
#define LPC17_I2C0_ADR1 (LPC17_I2C0_BASE+LPC17_I2C_ADR1_OFFSET)
|
||||
#define LPC17_I2C0_ADR2 (LPC17_I2C0_BASE+LPC17_I2C_ADR2_OFFSET)
|
||||
#define LPC17_I2C0_ADR3 (LPC17_I2C0_BASE+LPC17_I2C_ADR3_OFFSET)
|
||||
#define LPC17_I2C0_BUFR (LPC17_I2C0_BASE+LPC17_I2C_BUFR_OFFSET)
|
||||
#define LPC17_I2C0_MASK0 (LPC17_I2C0_BASE+LPC17_I2C_MASK0_OFFSET)
|
||||
#define LPC17_I2C0_MASK1 (LPC17_I2C0_BASE+LPC17_I2C_MASK1_OFFSET)
|
||||
#define LPC17_I2C0_MASK2 (LPC17_I2C0_BASE+LPC17_I2C_MASK2_OFFSET)
|
||||
#define LPC17_I2C0_MASK3 (LPC17_I2C0_BASE+LPC17_I2C_MASK3_OFFSET)
|
||||
|
||||
#define LPC17_I2C1_CONSET (LPC17_I2C1_BASE+LPC17_I2C_CONSET_OFFSET)
|
||||
#define LPC17_I2C1_STAT (LPC17_I2C1_BASE+LPC17_I2C_STAT_OFFSET)
|
||||
#define LPC17_I2C1_DAT (LPC17_I2C1_BASE+LPC17_I2C_DAT_OFFSET)
|
||||
#define LPC17_I2C1_ADR0 (LPC17_I2C1_BASE+LPC17_I2C_ADR0_OFFSET)
|
||||
#define LPC17_I2C1_SCLH (LPC17_I2C1_BASE+LPC17_I2C_SCLH_OFFSET)
|
||||
#define LPC17_I2C1_SCLL (LPC17_I2C1_BASE+LPC17_I2C_SCLL_OFFSET)
|
||||
#define LPC17_I2C1_CONCLR (LPC17_I2C1_BASE+LPC17_I2C_CONCLR_OFFSET)
|
||||
#define LPC17_I2C1_MMCTRL (LPC17_I2C1_BASE+LPC17_I2C_MMCTRL_OFFSET)
|
||||
#define LPC17_I2C1_ADR1 (LPC17_I2C1_BASE+LPC17_I2C_ADR1_OFFSET)
|
||||
#define LPC17_I2C1_ADR2 (LPC17_I2C1_BASE+LPC17_I2C_ADR2_OFFSET)
|
||||
#define LPC17_I2C1_ADR3 (LPC17_I2C1_BASE+LPC17_I2C_ADR3_OFFSET)
|
||||
#define LPC17_I2C1_BUFR (LPC17_I2C1_BASE+LPC17_I2C_BUFR_OFFSET)
|
||||
#define LPC17_I2C1_MASK0 (LPC17_I2C1_BASE+LPC17_I2C_MASK0_OFFSET)
|
||||
#define LPC17_I2C1_MASK1 (LPC17_I2C1_BASE+LPC17_I2C_MASK1_OFFSET)
|
||||
#define LPC17_I2C1_MASK2 (LPC17_I2C1_BASE+LPC17_I2C_MASK2_OFFSET)
|
||||
#define LPC17_I2C1_MASK3 (LPC17_I2C1_BASE+LPC17_I2C_MASK3_OFFSET)
|
||||
|
||||
#define LPC17_I2C2_CONSET (LPC17_I2C2_BASE+LPC17_I2C_CONSET_OFFSET)
|
||||
#define LPC17_I2C2_STAT (LPC17_I2C2_BASE+LPC17_I2C_STAT_OFFSET)
|
||||
#define LPC17_I2C2_DAT (LPC17_I2C2_BASE+LPC17_I2C_DAT_OFFSET)
|
||||
#define LPC17_I2C2_ADR0 (LPC17_I2C2_BASE+LPC17_I2C_ADR0_OFFSET)
|
||||
#define LPC17_I2C2_SCLH (LPC17_I2C2_BASE+LPC17_I2C_SCLH_OFFSET)
|
||||
#define LPC17_I2C2_SCLL (LPC17_I2C2_BASE+LPC17_I2C_SCLL_OFFSET)
|
||||
#define LPC17_I2C2_CONCLR (LPC17_I2C2_BASE+LPC17_I2C_CONCLR_OFFSET)
|
||||
#define LPC17_I2C2_MMCTRL (LPC17_I2C2_BASE+LPC17_I2C_MMCTRL_OFFSET)
|
||||
#define LPC17_I2C2_ADR1 (LPC17_I2C2_BASE+LPC17_I2C_ADR1_OFFSET)
|
||||
#define LPC17_I2C2_ADR2 (LPC17_I2C2_BASE+LPC17_I2C_ADR2_OFFSET)
|
||||
#define LPC17_I2C2_ADR3 (LPC17_I2C2_BASE+LPC17_I2C_ADR3_OFFSET)
|
||||
#define LPC17_I2C2_BUFR (LPC17_I2C2_BASE+LPC17_I2C_BUFR_OFFSET)
|
||||
#define LPC17_I2C2_MASK0 (LPC17_I2C2_BASE+LPC17_I2C_MASK0_OFFSET)
|
||||
#define LPC17_I2C2_MASK1 (LPC17_I2C2_BASE+LPC17_I2C_MASK1_OFFSET)
|
||||
#define LPC17_I2C2_MASK2 (LPC17_I2C2_BASE+LPC17_I2C_MASK2_OFFSET)
|
||||
#define LPC17_I2C2_MASK3 (LPC17_I2C2_BASE+LPC17_I2C_MASK3_OFFSET)
|
||||
|
||||
/* Register bit definitions *********************************************************/
|
||||
/* I2C Control Set Register */
|
||||
/* Bits 0-1: Reserved */
|
||||
#define I2C_CONSET_AA (1 << 2) /* Bit 2: Assert acknowledge flag */
|
||||
#define I2C_CONSET_SI (1 << 3) /* Bit 3: I2C interrupt flag */
|
||||
#define I2C_CONSET_STO (1 << 4) /* Bit 4: STOP flag */
|
||||
#define I2C_CONSET_STA (1 << 5) /* Bit 5: START flag */
|
||||
#define I2C_CONSET_I2EN (1 << 6) /* Bit 6: I2C interface enable */
|
||||
/* Bits 7-31: Reserved */
|
||||
/* I2C Control Clear Register */
|
||||
/* Bits 0-1: Reserved */
|
||||
#define I2C_CONCLR_AAC (1 << 2) /* Bit 2: Assert acknowledge Clear bit */
|
||||
#define I2C_CONCLR_SIC (1 << 3) /* Bit 3: I2C interrupt Clear bit */
|
||||
/* Bit 4: Reserved */
|
||||
#define I2C_CONCLR_STAC (1 << 5) /* Bit 5: START flag Clear bit */
|
||||
#define I2C_CONCLRT_I2ENC (1 << 6) /* Bit 6: I2C interface Disable bit */
|
||||
/* Bits 7-31: Reserved */
|
||||
/* I2C Status Register
|
||||
*
|
||||
* See tables 399-402 in the "LPC17xx User Manual" (UM10360), Rev. 01, 4 January
|
||||
* 2010, NXP for definitions of status codes.
|
||||
*/
|
||||
|
||||
#define I2C_STAT_MASK (0xff) /* Bits 0-7: I2C interface status
|
||||
* Bits 0-1 always zero */
|
||||
/* Bits 8-31: Reserved */
|
||||
/* I2C Data Register */
|
||||
|
||||
#define I2C_DAT_MASK (0xff) /* Bits 0-7: I2C data */
|
||||
/* Bits 8-31: Reserved */
|
||||
/* Monitor mode control register */
|
||||
|
||||
#define I2C_MMCTRL_MMENA (1 << 0) /* Bit 0: Monitor mode enable */
|
||||
#define I2C_MMCTRL_ENASCL (1 << 1) /* Bit 1: SCL output enable */
|
||||
#define I2C_MMCTRL_MATCHALL (1 << 2) /* Bit 2: Select interrupt register match */
|
||||
/* Bits 3-31: Reserved */
|
||||
/* Data buffer register */
|
||||
|
||||
#define I2C_BUFR_MASK (0xff) /* Bits 0-7: 8 MSBs of the I2DAT shift register */
|
||||
/* Bits 8-31: Reserved */
|
||||
/* I2C Slave address registers:
|
||||
*
|
||||
* I2C Slave Address Register 0
|
||||
* I2C Slave Address Register 1
|
||||
* I2C Slave Address Register 2
|
||||
* I2C Slave Address Register 3
|
||||
*/
|
||||
|
||||
#define I2C_ADR_GC (1 << 0) /* Bit 0: GC General Call enable bit */
|
||||
#define I2C_ADR_ADDR_SHIFT (1) /* Bits 1-7: I2C slave address */
|
||||
#define I2C_ADR_ADDR_MASK (0x7f << I2C_ADR_ADDR_SHIFT)
|
||||
/* Bits 8-31: Reserved */
|
||||
/* I2C Slave address mask registers:
|
||||
*
|
||||
* I2C Slave address mask register 0
|
||||
* I2C Slave address mask register 1
|
||||
* I2C Slave address mask register 2
|
||||
* I2C Slave address mask register 3
|
||||
*/
|
||||
/* Bit 0: Reserved */
|
||||
#define I2C_MASK_SHIFT (1) /* Bits 1-7: I2C mask bits */
|
||||
#define I2C_MASK_MASK (0x7f << I2C_ADR_ADDR_SHIFT)
|
||||
/* Bits 8-31: Reserved */
|
||||
/* SCH Duty Cycle Register High Half Word */
|
||||
|
||||
#define I2C_SCLH_MASK (0xffff) /* Bit 0-15: Count for SCL HIGH time period selection */
|
||||
/* Bits 16-31: Reserved */
|
||||
/* SCL Duty Cycle Register Low Half Word */
|
||||
|
||||
#define I2C_SCLL_MASK (0xffff) /* Bit 0-15: Count for SCL LOW time period selection */
|
||||
/* Bits 16-31: Reserved */
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_I2C_H */
|
||||
@@ -1,190 +0,0 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/lpc17xx/hardware/lpc17_i2s
|
||||
*
|
||||
* Copyright (C) 2010, 2012 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_I2S_H
|
||||
#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_I2S_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "hardware/lpc17_memorymap.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register offsets *****************************************************************/
|
||||
|
||||
#define LPC17_I2S_DAO_OFFSET 0x0000 /* Digital Audio Output Register */
|
||||
#define LPC17_I2S_DAI_OFFSET 0x0004 /* Digital Audio Input Register */
|
||||
#define LPC17_I2S_TXFIFO_OFFSET 0x0008 /* Transmit FIFO */
|
||||
#define LPC17_I2S_RXFIFO_OFFSET 0x000c /* Receive FIFO */
|
||||
#define LPC17_I2S_STATE_OFFSET 0x0010 /* Status Feedback Register */
|
||||
#define LPC17_I2S_DMA1_OFFSET 0x0014 /* DMA Configuration Register 1 */
|
||||
#define LPC17_I2S_DMA2_OFFSET 0x0018 /* DMA Configuration Register 2 */
|
||||
#define LPC17_I2S_IRQ_OFFSET 0x001c /* Interrupt Request Control Register */
|
||||
#define LPC17_I2S_TXRATE_OFFSET 0x0020 /* Transmit MCLK divider */
|
||||
#define LPC17_I2S_RXRATE_OFFSET 0x0024 /* Receive MCLK divider */
|
||||
#define LPC17_I2S_TXBITRATE_OFFSET 0x0028 /* Transmit bit rate divider */
|
||||
#define LPC17_I2S_RXBITRATE_OFFSET 0x002c /* Receive bit rate divider */
|
||||
#define LPC17_I2S_TXMODE_OFFSET 0x0030 /* Transmit mode control */
|
||||
#define LPC17_I2S_RXMODE_OFFSET 0x0034 /* Receive mode control */
|
||||
|
||||
/* Register addresses ***************************************************************/
|
||||
|
||||
#define LPC17_I2S_DAO (LPC17_I2S_BASE+LPC17_I2S_DAO_OFFSET)
|
||||
#define LPC17_I2S_DAI (LPC17_I2S_BASE+LPC17_I2S_DAI_OFFSET)
|
||||
#define LPC17_I2S_TXFIFO (LPC17_I2S_BASE+LPC17_I2S_TXFIFO_OFFSET)
|
||||
#define LPC17_I2S_RXFIFO (LPC17_I2S_BASE+LPC17_I2S_RXFIFO_OFFSET)
|
||||
#define LPC17_I2S_STATE (LPC17_I2S_BASE+LPC17_I2S_STATE_OFFSET)
|
||||
#define LPC17_I2S_DMA1 (LPC17_I2S_BASE+LPC17_I2S_DMA1_OFFSET)
|
||||
#define LPC17_I2S_DMA2 (LPC17_I2S_BASE+LPC17_I2S_DMA2_OFFSET)
|
||||
#define LPC17_I2S_IRQ (LPC17_I2S_BASE+LPC17_I2S_IRQ_OFFSET)
|
||||
#define LPC17_I2S_TXRATE (LPC17_I2S_BASE+LPC17_I2S_TXRATE_OFFSET)
|
||||
#define LPC17_I2S_RXRATE (LPC17_I2S_BASE+LPC17_I2S_RXRATE_OFFSET)
|
||||
#define LPC17_I2S_TXBITRATE (LPC17_I2S_BASE+LPC17_I2S_TXBITRATE_OFFSET)
|
||||
#define LPC17_I2S_RXBITRATE (LPC17_I2S_BASE+LPC17_I2S_RXBITRATE_OFFSET)
|
||||
#define LPC17_I2S_TXMODE (LPC17_I2S_BASE+LPC17_I2S_TXMODE_OFFSET)
|
||||
#define LPC17_I2S_RXMODE (LPC17_I2S_BASE+LPC17_I2S_RXMODE_OFFSET)
|
||||
|
||||
/* Register bit definitions *********************************************************/
|
||||
|
||||
/* Digital Audio Output Register */
|
||||
|
||||
#define I2S_DAO_WDWID_SHIFT (0) /* Bits 0-1: Selects the number of bytes in data */
|
||||
#define I2S_DAO_WDWID_MASK (3 << I2S_DAO_WDWID_SHIFT)
|
||||
# define I2S_DAO_WDWID_8BITS (0 << I2S_DAO_WDWID_SHIFT)
|
||||
# define I2S_DAO_WDWID_16BITS (1 << I2S_DAO_WDWID_SHIFT)
|
||||
# define I2S_DAO_WDWID_32BITS (3 << I2S_DAO_WDWID_SHIFT)
|
||||
#define I2S_DAO_MONO (1 << 2) /* Bit 2: Mono format */
|
||||
#define I2S_DAO_STOP (1 << 3) /* Bit 3: Disable FIFOs / mute mode */
|
||||
#define I2S_DAO_RESET (1 << 4) /* Bit 4: Reset TX channel and FIFO */
|
||||
#define I2S_DAO_WSSEL (1 << 5) /* Bit 5: Slave mode select */
|
||||
#define I2S_DAO_WSHALFPER_SHIFT (6) /* Bits 6-14: Word select half period minus 1 */
|
||||
#define I2S_DAO_WSHALFPER_MASK (0x01ff << I2S_DAO_WSHALFPER_SHIFT)
|
||||
#define I2S_DAO_MUTE (1 << 15) /* Bit 15: Send only zeros on channel */
|
||||
/* Bits 16-31: Reserved */
|
||||
/* Digital Audio Input Register */
|
||||
|
||||
#define I2S_DAI_WDWID_SHIFT (0) /* Bits 0-1: Selects the number of bytes in data */
|
||||
#define I2S_DAI_WDWID_MASK (3 << I2S_DAI_WDWID_SHIFT)
|
||||
# define I2S_DAI_WDWID_8BITS (0 << I2S_DAI_WDWID_SHIFT)
|
||||
# define I2S_DAI_WDWID_16BITS (1 << I2S_DAI_WDWID_SHIFT)
|
||||
# define I2S_DAI_WDWID_32BITS (3 << I2S_DAI_WDWID_SHIFT)
|
||||
#define I2S_DAI_MONO (1 << 2) /* Bit 2: Mono format */
|
||||
#define I2S_DAI_STOP (1 << 3) /* Bit 3: Disable FIFOs / mute mode */
|
||||
#define I2S_DAI_RESET (1 << 4) /* Bit 4: Reset TX channel and FIFO */
|
||||
#define I2S_DAI_WSSEL (1 << 5) /* Bit 5: Slave mode select */
|
||||
#define I2S_DAI_WSHALFPER_SHIFT (6) /* Bits 6-14: Word select half period minus 1 */
|
||||
#define I2S_DAI_WSHALFPER_MASK (0x01ff << I2S_DAI_WSHALFPER_SHIFT)
|
||||
/* Bits 15-31: Reserved */
|
||||
/* Transmit FIFO: 8 × 32-bit transmit FIFO */
|
||||
/* Receive FIFO: 8 × 32-bit receive FIFO */
|
||||
|
||||
/* Status Feedback Register */
|
||||
|
||||
#define I2S_STATE_IRQ (1 << 0) /* Bit 0: Receive Transmit Interrupt */
|
||||
#define I2S_STATE_DMAREQ1 (1 << 1) /* Bit 1: Receive or Transmit DMA Request 1 */
|
||||
#define I2S_STATE_DMAREQ2 (1 << 2) /* Bit 2: Receive or Transmit DMA Request 2 */
|
||||
/* Bits 3-7: Reserved */
|
||||
#define I2S_STATE_RXLEVEL_SHIFT (8) /* Bits 8-11: Current level of the Receive FIFO */
|
||||
#define I2S_STATE_RXLEVEL_MASK (15 << I2S_STATE_RXLEVEL_SHIFT)
|
||||
/* Bits 12-15: Reserved */
|
||||
#define I2S_STATE_TXLEVEL_SHIFT (16) /* Bits 16-19: Current level of the Transmit FIFO */
|
||||
#define I2S_STATE_TXLEVEL_MASK (15 << I2S_STATE_TXLEVEL_SHIFT)
|
||||
/* Bits 20-31: Reserved */
|
||||
/* DMA Configuration Register 1 and 2 */
|
||||
|
||||
#define I2S_DMA_RXDMAEN (1 << 0) /* Bit 0: Enable DMA1 for I2S receive */
|
||||
#define I2S_DMA_TXDMAEN (1 << 1) /* Bit 1: Enable DMA1 for I2S transmit */
|
||||
/* Bits 2-7: Reserved */
|
||||
#define I2S_DMA_RXDEPTH_SHIFT (8) /* Bits 8-11: FIFO level that triggers RX request on DMA1 */
|
||||
#define I2S_DMA_RXDEPTH_MASK (15 << I2S_DMA_RXDEPTH_SHIFT)
|
||||
/* Bits 12-15: Reserved */
|
||||
#define I2S_DMA_TXDEPTH_SHIFT (16) /* Bits 16-19: FIFO level that triggers a TX request on DMA1 */
|
||||
#define I2S_DMA_TXDEPTH_MASK (15 << I2S_DMA_TXDEPTH_SHIFT)
|
||||
/* Bits 20-31: Reserved */
|
||||
/* Interrupt Request Control Register */
|
||||
|
||||
#define I2S_IRQ_RXEN (1 << 0) /* Bit 0: Enable I2S receive interrupt */
|
||||
#define I2S_IRQ_TXEN (1 << 1) /* Bit 1: Enable I2S transmit interrupt */
|
||||
/* Bits 2-7: Reserved */
|
||||
#define I2S_IRQ_RXDEPTH_SHIFT (8) /* Bits 8-11: Set FIFO level for irq request */
|
||||
#define I2S_IRQ_RXDEPTH_MASK (15 << I2S_IRQ_RXDEPTH_SHIFT)
|
||||
/* Bits 12-15: Reserved */
|
||||
#define I2S_IRQ_TXDEPTH_SHIFT (16) /* Bits 16-19: Set FIFO level for irq request */
|
||||
#define I2S_IRQ_TXDEPTH_MASK (15 << I2S_IRQ_TXDEPTH_SHIFT)
|
||||
/* Bits 20-31: Reserved */
|
||||
/* Transmit and Receive MCLK divider */
|
||||
|
||||
#define I2S_RATE_YDIV_SHIFT (0) /* Bits 0-7: I2S transmit MCLK rate denominator */
|
||||
#define I2S_RATE_YDIV_MASK (0xff << I2S_RATE_YDIV_SHIFT)
|
||||
#define I2S_RATE_XDIV_SHIFT (8) /* Bits 8-15: I2S transmit MCLK rate numerator */
|
||||
#define I2S_RATE_XDIV_MASK (0xff << I2S_RATE_XDIV_SHIFT)
|
||||
/* Bits 16-31: Reserved */
|
||||
|
||||
/* Transmit and received bit rate divider */
|
||||
|
||||
#define I2S_BITRATE_SHIFT (0) /* Bits 0-5: I2S transmit bit rate */
|
||||
#define I2S_BITRATE_MASK (0x3f << I2S_BITRATE_SHIFT)
|
||||
/* Bits 6-31: Reserved */
|
||||
/* Transmit and Receive mode control */
|
||||
|
||||
#define I2S_MODE_CLKSEL_SHIFT (0) /* Bits 0-1: Clock source for bit clock divider */
|
||||
#define I2S_MODE_CLKSEL_MASK (3 << I2S_MODE_CLKSEL_SHIFT)
|
||||
# define I2S_MODE_CLKSEL_FRACDIV (0 << I2S_MODE_CLKSEL_SHIFT) /* TX/RX fractional rate divider */
|
||||
# define I2S_MODE_CLKSEL_RXMCLK (2 << I2S_MODE_CLKSEL_SHIFT) /* RX_CLCK for TX_MCLK source */
|
||||
# define I2S_MODE_CLKSEL_TXMCLK (2 << I2S_MODE_CLKSEL_SHIFT) /* TX_CLCK for RX_MCLK source */
|
||||
#define I2S_MODE_4PIN (1 << 2) /* Bit 2: Transmit/Receive 4-pin mode selection */
|
||||
#define I2S_MODE_MCENA (1 << 3) /* Bit 3: Enable for the TX/RX_MCLK output */
|
||||
/* Bits 4-31: Reserved */
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_I2S_H */
|
||||
@@ -1,346 +0,0 @@
|
||||
/************************************************************************************************
|
||||
* arch/arm/src/lpc17xx/hardware/lpc17_lcd.h
|
||||
*
|
||||
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_LCD_H
|
||||
#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_LCD_H
|
||||
|
||||
/************************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "hardware/lpc17_memorymap.h"
|
||||
|
||||
/************************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************************/
|
||||
|
||||
/* Register offsets *****************************************************************************/
|
||||
|
||||
#define LPC17_LCD_TIMH_OFFSET (0x0000) /* Horizontal Timing Control register */
|
||||
#define LPC17_LCD_TIMV_OFFSET (0x0004) /* Vertical Timing Control register */
|
||||
#define LPC17_LCD_POL_OFFSET (0x0008) /* Clock & Signal Polarity Control register */
|
||||
#define LPC17_LCD_LE_OFFSET (0x000c) /* Line End Control register */
|
||||
#define LPC17_LCD_UPBASE_OFFSET (0x0010) /* Upper Panel Frame Base Address register */
|
||||
#define LPC17_LCD_LPBASE_OFFSET (0x0014) /* Lower Panel Frame Base Address register */
|
||||
#define LPC17_LCD_CTRL_OFFSET (0x0018) /* LCD Control register */
|
||||
#define LPC17_LCD_INTMSK_OFFSET (0x001c) /* Interrupt Mask register */
|
||||
#define LPC17_LCD_INTRAW_OFFSET (0x0020) /* Raw Interrupt Status register */
|
||||
#define LPC17_LCD_INTSTAT_OFFSET (0x0024) /* Masked Interrupt Status register */
|
||||
#define LPC17_LCD_INTCLR_OFFSET (0x0028) /* Interrupt Clear register */
|
||||
#define LPC17_LCD_UPCURR_OFFSET (0x002c) /* Upper Panel Current Address Value register */
|
||||
#define LPC17_LCD_LPCURR_OFFSET (0x0030) /* Lower Panel Current Address Value register */
|
||||
|
||||
/* 256x16-bit Color Palette registers, n=0-127 */
|
||||
|
||||
#define LPC17_LCD_PAL_OFFSET(n) (0x0200 + ((n) << 2))
|
||||
|
||||
/* Cursor Image registers, n=0-255 */
|
||||
|
||||
#define LPC17_LCD_CRSR_IMG_OFFSET(n) (0x0800 + ((n) << 2))
|
||||
|
||||
#define LPC17_LCD_CRSR_CRTL_OFFSET (0x0c00) /* Cursor Control register */
|
||||
#define LPC17_LCD_CRSR_CFG_OFFSET (0x0c04) /* Cursor Configuration register */
|
||||
#define LPC17_LCD_CRSR_PAL0_OFFSET (0x0c08) /* Cursor Palette register 0 */
|
||||
#define LPC17_LCD_CRSR_PAL1_OFFSET (0x0c0c) /* Cursor Palette register 1 */
|
||||
#define LPC17_LCD_CRSR_XY_OFFSET (0x0c10) /* Cursor XY Position register */
|
||||
#define LPC17_LCD_CRSR_CLIP_OFFSET (0x0c14) /* Cursor Clip Position register */
|
||||
#define LPC17_LCD_CRSR_INTMSK_OFFSET (0x0c20) /* Cursor Interrupt Mask regsiter */
|
||||
#define LPC17_LCD_CRSR_INTCLR_OFFSET (0x0c24) /* Cursor Interrupt Clear register */
|
||||
#define LPC17_LCD_CRSR_INTRAW_OFFSET (0x0c28) /* Cursor Raw Interrupt Status register */
|
||||
#define LPC17_LCD_CRSR_INTSTAT_OFFSET (0x0c2c) /* Cursor Masked Interrupt Status register */
|
||||
|
||||
/* Register Addresses ***************************************************************************/
|
||||
|
||||
#define LPC17_LCD_TIMH (LPC17_LCD_BASE+LPC17_LCD_TIMH_OFFSET)
|
||||
#define LPC17_LCD_TIMV (LPC17_LCD_BASE+LPC17_LCD_TIMV_OFFSET)
|
||||
#define LPC17_LCD_POL (LPC17_LCD_BASE+LPC17_LCD_POL_OFFSET)
|
||||
#define LPC17_LCD_LE (LPC17_LCD_BASE+LPC17_LCD_LE_OFFSET)
|
||||
#define LPC17_LCD_UPBASE (LPC17_LCD_BASE+LPC17_LCD_UPBASE_OFFSET)
|
||||
#define LPC17_LCD_LPBASE (LPC17_LCD_BASE+LPC17_LCD_LPBASE_OFFSET)
|
||||
#define LPC17_LCD_CTRL (LPC17_LCD_BASE+LPC17_LCD_CTRL_OFFSET)
|
||||
#define LPC17_LCD_INTMSK (LPC17_LCD_BASE+LPC17_LCD_INTMSK_OFFSET)
|
||||
#define LPC17_LCD_INTRAW (LPC17_LCD_BASE+LPC17_LCD_INTRAW_OFFSET)
|
||||
#define LPC17_LCD_INTSTAT (LPC17_LCD_BASE+LPC17_LCD_INTSTAT_OFFSET)
|
||||
#define LPC17_LCD_INTCLR (LPC17_LCD_BASE+ LPC17_LCD_INTCLR_OFFSET)
|
||||
#define LPC17_LCD_UPCURR (LPC17_LCD_BASE+LPC17_LCD_UPCURR_OFFSET)
|
||||
#define LPC17_LCD_LPCURR (LPC17_LCD_BASE+LPC17_LCD_LPCURR_OFFSET)
|
||||
|
||||
#define LPC17_LCD_PAL(n) (LPC17_LCD_BASE+LPC17_LCD_PAL_OFFSET(n))
|
||||
#define LPC17_LCD_CRSR_IMG(n) (LPC17_LCD_BASE+LPC17_LCD_CRSR_IMG_OFFSET(n))
|
||||
|
||||
#define LPC17_LCD_CRSR_CRTL (LPC17_LCD_BASE+LPC17_LCD_CRSR_CRTL_OFFSET)
|
||||
#define LPC17_LCD_CRSR_CFG (LPC17_LCD_BASE+LPC17_LCD_CRSR_CFG_OFFSET)
|
||||
#define LPC17_LCD_CRSR_PAL0 (LPC17_LCD_BASE+LPC17_LCD_CRSR_PAL0_OFFSET)
|
||||
#define LPC17_LCD_CRSR_PAL1 (LPC17_LCD_BASE+LPC17_LCD_CRSR_PAL1_OFFSET)
|
||||
#define LPC17_LCD_CRSR_XY (LPC17_LCD_BASE+LPC17_LCD_CRSR_XY_OFFSET)
|
||||
#define LPC17_LCD_CRSR_CLIP (LPC17_LCD_BASE+LPC17_LCD_CRSR_CLIP_OFFSET)
|
||||
#define LPC17_LCD_CRSR_INTMSK (LPC17_LCD_BASE+LPC17_LCD_CRSR_INTMSK_OFFSET)
|
||||
#define LPC17_LCD_CRSR_INTCLR (LPC17_LCD_BASE+LPC17_LCD_CRSR_INTCLR_OFFSET)
|
||||
#define LPC17_LCD_CRSR_INTRAW (LPC17_LCD_BASE+LPC17_LCD_CRSR_INTRAW_OFFSET)
|
||||
#define LPC17_LCD_CRSR_INTSTAT (LPC17_LCD_BASE+LPC17_LCD_CRSR_INTSTAT_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************************/
|
||||
|
||||
/* LCD_TIMH - Horizontal Timing Register */
|
||||
/* Bits 0-1: Reserved */
|
||||
#define LCD_TIMH_PPL_SHIFT (2) /* Bits 2-7: Pixels Per Line - 16-1024ppl */
|
||||
#define LCD_TIMH_PPL_MASK (0x3f << LCD_TIMH_PPL_SHIFT)
|
||||
#define LCD_TIMH_HSW_SHIFT (8) /* Bits 8-15: Horizontal Sync Pulse Width */
|
||||
#define LCD_TIMH_HWS_MASK (0xff << LCD_TIMH_HSW_SHIFT)
|
||||
#define LCD_TIMH_HFP_SHIFT (16) /* Bits 16-23: Horizontal Front Porch */
|
||||
#define LCD_TIMH_HFP_MASK (0xff << LCD_TIMH_HFP_SHIFT)
|
||||
#define LCD_TIMH_HBP_SHIFT (24) /* Bits 24-31: Horizontal Back Porch */
|
||||
#define LCD_TIMH_HBP_MASK (0xff << LCD_TIMH_HBP_SHIFT)
|
||||
|
||||
/* LCD_TIMV - Vertical Timing Register */
|
||||
|
||||
#define LCD_TIMV_LPP_SHIFT (0) /* Bits 0-9: Lines Per Panel 1-1024 lpp*/
|
||||
#define LCD_TIMV_LPP_MASK (0x3ff << LCD_TIMV_LPP_SHIFT)
|
||||
#define LCD_TIMV_VSW_SHIFT (10) /* Bits 10-15: Vertical Synch Pulse Width */
|
||||
#define LCD_TIMV_VSW_MASK (0x3f << LCD_TIMV_VSW_SHIFT)
|
||||
#define LCD_TIMV_VFP_SHIFT (16) /* Bits 16-23: Vertical Front Porch */
|
||||
#define LCD_TIMV_VFP_MASK (0xff << LCD_TIMV_VFP_SHIFT)
|
||||
#define LCD_TIMV_VBP_SHIFT (24) /* Bits 24-31: Vertical Back Porch */
|
||||
#define LCD_TIMV_VBP_MASK (0xff << LCD_TIMV_VBP_SHIFT)
|
||||
|
||||
/* LCD_POL - Clock and Signal Polarity Register */
|
||||
|
||||
#define LCD_POL_PCDLO_SHIFT (0) /* Bits 0-4: Lower 5 bits of panel clock divisor */
|
||||
#define LCD_POL_PCDLO_MASK (0x1f << LCD_POL_PCDLO_SHIFT)
|
||||
#define LCD_POL_CLKSEL (1 << 5) /* Bit 5: Clock select- 0=PCLK, 1=LCD_CLKIN */
|
||||
#define LCD_POL_ACB_SHIFT (6) /* Bits 6-10: AC bias pin frequency */
|
||||
#define LCD_POL_ACB_MASK (0x1f << LCD_POL_ACB_SHIFT)
|
||||
#define LCD_POL_IVS (1 << 11) /* Bit 11: Invert vertical sync */
|
||||
#define LCD_POL_IHS (1 << 12) /* Bit 12: Invert horizontal sync */
|
||||
#define LCD_POL_IPC (1 << 13) /* Bit 13: Invert panel clock */
|
||||
#define LCD_POL_IOE (1 << 14) /* Bit 14: Invert output enable */
|
||||
/* Bit 15: Reserved */
|
||||
#define LCD_POL_CPL_SHIFT (16) /* Bit 16-25: Clocks per line */
|
||||
#define LCD_POL_CPL_MASK (0x3ff << LCD_POL_CPL_SHIFT)
|
||||
#define LCD_POL_BCD (1 << 26) /* Bit 26: Bypass pixel clock divider */
|
||||
#define LCD_POL_PCDHI_SHIFT (27) /* Bits 27-31: Upper 5 bits of panel clock divisor */
|
||||
#define LCD_POL_PCDHI_MASK (0x1f << LCD_POL_PCDHI_SHIFT)
|
||||
|
||||
/* LCD_LE - Line End Control Register */
|
||||
|
||||
#define LCD_LE_LED_SHIFT (0) /* Bits 0-6: Line End delay */
|
||||
#define LCD_LE_LED_MASK (0x7f << LCD_LE_LED_SHIFT)
|
||||
/* Bits 7-15: Reserved */
|
||||
#define LCD_LE_LEE (1 << 16) /* Bit 16: LCD line end enable */
|
||||
/* Bit 17-31: Reserved */
|
||||
/* LCD_UPBASE - Upper Panel Frame Base Address Register */
|
||||
/* Bits 0-2: Reserved */
|
||||
#define LCD_UPBASE_LCDUPBASE_SHIFT (3) /* Bits 3-31: LCD upper panel base address */
|
||||
#define LCD_UPBASE_LCDUPBASE_MASK (0x1FFFFFFF << LCD_UPBASE_LCDUPBASE_SHIFT)
|
||||
|
||||
/* LCD_UPBASE - Lower Panel Frame Base Address Register */
|
||||
/* Bits 0-2: Reserved */
|
||||
#define LCD_UPBASE_LCDLPBASE_SHIFT (3) /* Bits 3-31: LCD lower panel base address */
|
||||
#define LCD_UPBASE_LCDLPBASE_MASK (0x1FFFFFFF << LCD_UPBASE_LCDUPBASE_SHIFT)
|
||||
|
||||
/* LCD_CTRL - Controle Register */
|
||||
|
||||
#define LCD_CTRL_LCDEN (1 << 0) /* Bit 0: LCD enable control bit */
|
||||
#define LCD_CTRL_LCDBPP_SHIFT (1) /* Bits 1-3: LCD bits per pixel */
|
||||
#define LCD_CTRL_LCDBPP_MASK (7 << LCD_CTRL_LCDBPP_SHIFT)
|
||||
# define LCD_CTRL_LCDBPP_1 (0 << LCD_CTRL_LCDBPP_SHIFT) /* 1 bpp */
|
||||
# define LCD_CTRL_LCDBPP_2 (1 << LCD_CTRL_LCDBPP_SHIFT) /* 2 bpp */
|
||||
# define LCD_CTRL_LCDBPP_4 (2 << LCD_CTRL_LCDBPP_SHIFT) /* 4 bpp */
|
||||
# define LCD_CTRL_LCDBPP_8 (3 << LCD_CTRL_LCDBPP_SHIFT) /* 8 bpp */
|
||||
# define LCD_CTRL_LCDBPP_16 (4 << LCD_CTRL_LCDBPP_SHIFT) /* 16 bpp */
|
||||
# define LCD_CTRL_LCDBPP_24 (5 << LCD_CTRL_LCDBPP_SHIFT) /* 24 bpp (TFT panel only) */
|
||||
# define LCD_CTRL_LCDBPP_565 (6 << LCD_CTRL_LCDBPP_SHIFT) /* 16 bpp, 5:6:5 mode */
|
||||
# define LCD_CTRL_LCDBPP_444 (7 << LCD_CTRL_LCDBPP_SHIFT) /* 12 bpp, 4:4:4 mode */
|
||||
#define LCD_CTRL_LCDBW (1 << 4) /* Bit 4: STN LCD monochrome/color selection */
|
||||
#define LCD_CTRL_LCDTFT (1 << 5) /* Bit 5: LCD TFT type selection */
|
||||
#define LCD_CTRL_LCDMONO8 (1 << 6) /* Bit 6: Monochrome LCD interface bit */
|
||||
#define LCD_CTRL_LCDDUAL (1 << 7) /* Bit 7: Single or Dual LCD panel selection */
|
||||
#define LCD_CTRL_BGR (1 << 8) /* Bit 8: Color format */
|
||||
#define LCD_CTRL_BEBO (1 << 9) /* Bit 9: Big-Endian Byte Order */
|
||||
#define LCD_CTRL_BEPO (1 << 10) /* Bit 10: Big-Endian Pixel Ordering */
|
||||
#define LCD_CTRL_LCDPWR (1 << 11) /* Bit 11: LCD Power enable */
|
||||
#define LCD_CTRL_LCDVCOMP_SHIFT (12) /* Bits 12-13: LCD Vertical compare interrupt */
|
||||
#define LCD_CTRL_LCDVCOMP_MASK (3 << LCD_CTRL_LCDVCOMP_SHIFT)
|
||||
/* Bits 14-15: Reserved */
|
||||
#define LCD_CTRL_WATERMARK (1 << 16) /* Bit 16: LCD DMA FIFO watermark level */
|
||||
/* Bits 17-31: Reserved */
|
||||
/* LCD_INTMSK - Interrupt Mask Register */
|
||||
/* Bits 0: Reserved */
|
||||
#define LCD_INTMSK_FUFIM (1 << 1) /* Bit 1: FIFO underflow interrupt enable */
|
||||
#define LCD_INTMSK_LNBUIM (1 << 2) /* Bit 2: LCD next base address interrupt enable */
|
||||
#define LCD_INTMSK_VCOMPIM (1 << 3) /* Bit 3: Vertical compare interrupt enable */
|
||||
#define LCD_INTMSK_BERIM (1 << 4) /* Bit 4: AHB Master error interrupt enable */
|
||||
/* Bits 5-31: Reserved */
|
||||
#define LCD_INTMSK_ALL (0x1e)
|
||||
|
||||
/* LCD_INTRAW - Raw Interrupt Status Register */
|
||||
/* Bits 0: Reserved */
|
||||
#define LCD_INTRAW_FUFRIS (1 << 1) /* Bit 1: FIFO Undeflow raw interrupt status */
|
||||
#define LCD_INTRAW_LNBURIS (1 << 2) /* Bit 2: LCD Next address base update intterupt */
|
||||
#define LCD_INTRAW_VCOMPRIS (1 << 3) /* Bit 3: Vertical compare interrupt status */
|
||||
#define LCD_INTRAW_BERRAW (1 << 4) /* Bit 4: AHB Master bus error interrupt status */
|
||||
/* Bits 5-31: Reserved */
|
||||
#define LCD_INTRAW_ALL (0x1e)
|
||||
|
||||
/* LCD_INTSTAT - Masked Interrupt Status Register */
|
||||
/* Bits 0: Reserved */
|
||||
#define LCD_INTSTAT_FUFMIS (1 << 1) /* Bit 1: FIFO Undeflow raw interrupt status */
|
||||
#define LCD_INTSTAT_LNBUMIS (1 << 2) /* Bit 2: LCD Next address base update intterupt */
|
||||
#define LCD_INTSTAT_VCOMPMIS (1 << 3) /* Bit 3: Vertical compare interrupt status */
|
||||
#define LCD_INTSTAT_BERMIS (1 << 4) /* Bit 4: AHB Master bus error interrupt status */
|
||||
/* Bits 15-31: Reserved */
|
||||
#define LCD_INTSTAT_ALL (0x1e)
|
||||
|
||||
/* LCD_INTCLR - Interrupt Clear Register */
|
||||
/* Bits 0: Reserved */
|
||||
#define LCD_INTCLR_FUFIC (1 << 1) /* Bit 1: FIFO Undeflow raw interrupt clear */
|
||||
#define LCD_INTCLR_LNBUIC (1 << 2) /* Bit 2: LCD Next address base update intterupt */
|
||||
#define LCD_INTCLR_VCOMPIC (1 << 3) /* Bit 3: Vertical compare interrupt clear */
|
||||
#define LCD_INTCLR_BERIC (1 << 4) /* Bit 4: AHB Master bus error interrupt clear */
|
||||
/* Bits 15-31: Reserved */
|
||||
#define LCD_INTCLR_ALL (0x1e)
|
||||
|
||||
/* Upper and Lower Panel Address register has no bitfields */
|
||||
/*
|
||||
* Upper Panel Current Address register (LCDUPCURR)
|
||||
* Lower Panel Current Address register (LCDLPCURR)
|
||||
*/
|
||||
|
||||
/* LCD_PAL - Color Palette Registers */
|
||||
|
||||
#define LCD_PAL_R0_SHIFT (0) /* Bits 0-4: Red palette data */
|
||||
#define LCD_PAL_R0_MASK (0x1f << LCD_PAL_R0_SHIFT)
|
||||
#define LCD_PAL_G0_SHIFT (5) /* Bits 5-9: Green palette data */
|
||||
#define LCD_PAL_G0_MASK (0x1f << LCD_PAL_G0_SHIFT)
|
||||
#define LCD_PAL_B0_SHIFT (10) /* Bits 10-14: Blue paletted data */
|
||||
#define LCD_PAL_B0_MASK (0x1f << LCD_PAL_B0_SHIFT)
|
||||
#define LCD_PAL_I0 (1 << 15) /* Bit 15: Intensity/Unused bit */
|
||||
#define LCD_PAL_R1_SHIFT (16) /* Bits 16-20: Red palette data */
|
||||
#define LCD_PAL_R1_MASK (0x1f << LCD_PAL_R1_SHIFT)
|
||||
#define LCD_PAL_G1_SHIFT (21) /* Bits 21-25: Green palette data */
|
||||
#define LCD_PAL_G1_MASK (0x1f << LCD_PAL_G1_SHIFT)
|
||||
#define LCD_PAL_B1_SHIFT (26) /* Bits 26-30: Blue palette data */
|
||||
#define LCD_PAL_B1_MASK (0x1f << LCD_PAL_B1_SHIFT)
|
||||
#define LCD_PAL_I1 (1 << 31) /* Bit 31: Intensity/Unused bit */
|
||||
|
||||
/* LCD_CRSR_IMG - Cursor Image Register - has no bitfields */
|
||||
/* The 256 words of the cursor image register defines the appearance
|
||||
* of either one 64x64 cursor, or 4 32x32 cursors.
|
||||
*/
|
||||
|
||||
/* LCD CRSR_CTRL - Cursor Control Register */
|
||||
|
||||
#define LCD_CRSR_CTRL_CRSON (1 << 0) /* Bit 0: Cursor enable */
|
||||
/* Bits 1-3: Reserved */
|
||||
#define LCD_CRSR_CTRL_CRSRNUM_SHIFT (4) /* Bits 4-5: Cursor image number */
|
||||
#define LCD_CRSR_CTRL_CRSRNUM_MASK (3 << LCD_CRSR_CTRL_CRSRNUM1_0_SHIFT)
|
||||
/* Bits 6-31: Reserved */
|
||||
/* If the selected cursor is 32x32 */
|
||||
|
||||
#define LCD_CURSOR0 (0)
|
||||
#define LCD_CURSOR1 (1)
|
||||
#define LCD_CURSOR2 (2)
|
||||
#define LCD_CURSOR3 (3)
|
||||
|
||||
/* LCD CRSR_CFG - Cursor Configuration Register */
|
||||
|
||||
#define LCD_CRSR_CFG_CRSRSIZE (1 << 0) /* Bit 0: Cursor size selection */
|
||||
#define LCD_CRSR_CFG_FRAMESYNC (1 << 1) /* Bit 1: Cursor frame sync type */
|
||||
/* Bits 2-31: Reserved */
|
||||
|
||||
#define LCD_CURSOR_SIZE32 (0) /* 32x32 */
|
||||
#define LCD_CURSOR_SIZE64 (1) /* 64x64 */
|
||||
#define LCD_CURSOR_FRAMEASYNC (0) /* Cursor coordinates are asynchronous */
|
||||
#define LCD_CURSOR_FRAMESYNC (1) /* coordinates are synchronize to framesync pulse */
|
||||
|
||||
/* LCD CRSR_PAL0/1 - Cursor Palette Registers */
|
||||
|
||||
#define LCD_CRSR_PAL_RED_SHIFT (0) /* Bits 0-7: Red color componnent */
|
||||
#define LCD_CRSR_PAL_RED_MASK (0xff << LCD_CRSR_PAL0_RED_SHIFT)
|
||||
#define LCD_CRSR_PAL_GREEN_SHIFT (8) /* Bits 8-15: Green color component */
|
||||
#define LCD_CRSR_PAL_GREEN_MASK (0xff << LCD_CRSR_PAL0_GREEN_SHIFT)
|
||||
#define LCD_CRSR_PAL_BLUE_SHIFT (16) /* Bits 16-23: Blue color component */
|
||||
#define LCD_CRSR_PAL_BLUE_MASK (0xff << LCD_CRSR_PAL0_BLUE_SHIFT)
|
||||
/* Bits 24-31: Reserved */
|
||||
/* LCD CRSR_XY - Cursor XY Position Register */
|
||||
|
||||
#define LCD_CRSR_CRSRX_SHIFT (0) /* Bits 0-9: X ordinate */
|
||||
#define LCD_CRSR_CRSRX_MASK (0x3ff << LCD_CRSR_CRSRX_SHIFT)
|
||||
/* Bits 10-15: Reserved */
|
||||
#define LCD_CRSR_CRSRY_SHIFT (16) /* Bits 16-25: Y ordinate */
|
||||
#define LCD_CRSR_CRSRY_MASK (0x3ff << LCD_CRSR_CRSRY_SHIFT)
|
||||
/* Bits 26-31: Reserved */
|
||||
/* LCD CRSR_CLIP - Cursor Clip Position Register */
|
||||
|
||||
#define LCD_CRSR_CRSRCLIPX_SHIFT (0) /* Bits 0-5: X clip position */
|
||||
#define LCD_CRSR_CRSRCLIPX_MASK (0x3f << LCD_CRSR_CRSRCLIPX_SHIFT)
|
||||
/* Bits 6-7: Reserved */
|
||||
#define LCD_CRSR_CRSRCLIPY_SHIFT (8) /* Bits 8-13: Reserved */
|
||||
#define LCD_CRSR_CRSRCLIPY_MASK (0x3f << LCD_CRSR_CRSRCLIPY_SHIFT)
|
||||
/* Bits 14-31: Reserved */
|
||||
/* LCD CRSR_INTMSK - Cursor Interrrupt Mask Register */
|
||||
|
||||
#define LCD_CRSR_INTMSK_CRSRIM (1 << 0) /* Bit 0: Cursor interrupt mask */
|
||||
/* Bits 1-31: Reserved */
|
||||
/* LCD CRSR_INTCLR - Cursor Interrrupt Clear Register */
|
||||
|
||||
#define LCD_CRSR_INTCLR_CRSRIC (1 << 0) /* Bit 0: Cursor interrupt clear */
|
||||
/* Bits 1-31: Reserved */
|
||||
|
||||
/* LCD CRSR_INTRAW - Cursor Raw Interrrupt Status Register */
|
||||
|
||||
#define LCD_CRSR_INTRAW_CRSRRIS (1 << 0) /* Bit 0: Cursor raw interrupt status */
|
||||
/* Bits 1-31: Reserved */
|
||||
/* LCD CRSR_INTSTAT - Mask Interrrupt Status Register */
|
||||
|
||||
#define LCD_CRSR_INTSTAT_CRSRMIS (1 << 0) /* Bit 0: Cursor mask interrupt status */
|
||||
/* Bits 1-31: Reserved */
|
||||
|
||||
/************************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************************/
|
||||
|
||||
/************************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************************/
|
||||
|
||||
/************************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_LCD_H */
|
||||
@@ -1,280 +0,0 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/lpc17xx/hardware/lpc17_mcpwm.h
|
||||
*
|
||||
* Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_MCPWM_H
|
||||
#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_MCPWM_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "hardware/lpc17_memorymap.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register offsets *****************************************************************/
|
||||
|
||||
#define LPC17_MCPWM_CON_OFFSET 0x0000 /* PWM Control read address */
|
||||
#define LPC17_MCPWM_CONSET_OFFSET 0x0004 /* PWM Control set address */
|
||||
#define LPC17_MCPWM_CONCLR_OFFSET 0x0008 /* PWM Control clear address */
|
||||
#define LPC17_MCPWM_CAPCON_OFFSET 0x000c /* Capture Control read address */
|
||||
#define LPC17_MCPWM_CAPCONSET_OFFSET 0x0010 /* Capture Control set address */
|
||||
#define LPC17_MCPWM_CAPCONCLR_OFFSET 0x0014 /* Event Control clear address */
|
||||
#define LPC17_MCPWM_TC0_OFFSET 0x0018 /* Timer Counter register, channel 0 */
|
||||
#define LPC17_MCPWM_TC1_OFFSET 0x001c /* Timer Counter register, channel 1 */
|
||||
#define LPC17_MCPWM_TC2_OFFSET 0x0020 /* Timer Counter register, channel 2 */
|
||||
#define LPC17_MCPWM_LIM0_OFFSET 0x0024 /* Limit register, channel 0 */
|
||||
#define LPC17_MCPWM_LIM1_OFFSET 0x0028 /* Limit register, channel 1 */
|
||||
#define LPC17_MCPWM_LIM2_OFFSET 0x002c /* Limit register, channel 2 */
|
||||
#define LPC17_MCPWM_MAT0_OFFSET 0x0030 /* Match register, channel 0 */
|
||||
#define LPC17_MCPWM_MAT1_OFFSET 0x0034 /* Match register, channel 1 */
|
||||
#define LPC17_MCPWM_MAT2_OFFSET 0x0038 /* Match register, channel 2 */
|
||||
#define LPC17_MCPWM_DT_OFFSET 0x003c /* Dead time register */
|
||||
#define LPC17_MCPWM_CP_OFFSET 0x0040 /* Commutation Pattern register */
|
||||
#define LPC17_MCPWM_CAP0_OFFSET 0x0044 /* Capture register, channel 0 */
|
||||
#define LPC17_MCPWM_CAP1_OFFSET 0x0048 /* Capture register, channel 1 */
|
||||
#define LPC17_MCPWM_CAP2_OFFSET 0x004c /* Capture register, channel 2 */
|
||||
#define LPC17_MCPWM_INTEN_OFFSET 0x0050 /* Interrupt Enable read address */
|
||||
#define LPC17_MCPWM_INTENSET_OFFSET 0x0054 /* Interrupt Enable set address */
|
||||
#define LPC17_MCPWM_INTENCLR_OFFSET 0x0058 /* Interrupt Enable clear address */
|
||||
#define LPC17_MCPWM_CNTCON_OFFSET 0x005c /* Count Control read address */
|
||||
#define LPC17_MCPWM_CNTCONSET_OFFSET 0x0060 /* Count Control set address */
|
||||
#define LPC17_MCPWM_CNTCONCLR_OFFSET 0x0064 /* Count Control clear address */
|
||||
#define LPC17_MCPWM_INTF_OFFSET 0x0068 /* Interrupt flags read address */
|
||||
#define LPC17_MCPWM_INTFSET_OFFSET 0x006c /* Interrupt flags set address */
|
||||
#define LPC17_MCPWM_INTFCLR_OFFSET 0x0070 /* Interrupt flags clear address */
|
||||
#define LPC17_MCPWM_CAPCLR_OFFSET 0x0074 /* Capture clear address */
|
||||
|
||||
/* Register addresses ***************************************************************/
|
||||
|
||||
#define LPC17_MCPWM_CON (LPC17_MCPWM_BASE+LPC17_MCPWM_CON_OFFSET)
|
||||
#define LPC17_MCPWM_CONSET (LPC17_MCPWM_BASE+LPC17_MCPWM_CONSET_OFFSET)
|
||||
#define LPC17_MCPWM_CONCLR (LPC17_MCPWM_BASE+LPC17_MCPWM_CONCLR_OFFSET)
|
||||
#define LPC17_MCPWM_CAPCON (LPC17_MCPWM_BASE+LPC17_MCPWM_CAPCON_OFFSET)
|
||||
#define LPC17_MCPWM_CAPCONSET (LPC17_MCPWM_BASE+LPC17_MCPWM_CAPCONSET_OFFSET)
|
||||
#define LPC17_MCPWM_CAPCONCLR (LPC17_MCPWM_BASE+LPC17_MCPWM_CAPCONCLR_OFFSET)
|
||||
#define LPC17_MCPWM_TC0 (LPC17_MCPWM_BASE+LPC17_MCPWM_TC0_OFFSET)
|
||||
#define LPC17_MCPWM_TC1 (LPC17_MCPWM_BASE+LPC17_MCPWM_TC1_OFFSET)
|
||||
#define LPC17_MCPWM_TC2 (LPC17_MCPWM_BASE+LPC17_MCPWM_TC2_OFFSET)
|
||||
#define LPC17_MCPWM_LIM0 (LPC17_MCPWM_BASE+LPC17_MCPWM_LIM0_OFFSET)
|
||||
#define LPC17_MCPWM_LIM1 (LPC17_MCPWM_BASE+LPC17_MCPWM_LIM1_OFFSET)
|
||||
#define LPC17_MCPWM_LIM2 (LPC17_MCPWM_BASE+LPC17_MCPWM_LIM2_OFFSET)
|
||||
#define LPC17_MCPWM_MAT0 (LPC17_MCPWM_BASE+LPC17_MCPWM_MAT0_OFFSET)
|
||||
#define LPC17_MCPWM_MAT1 (LPC17_MCPWM_BASE+LPC17_MCPWM_MAT1_OFFSET)
|
||||
#define LPC17_MCPWM_MAT2 (LPC17_MCPWM_BASE+LPC17_MCPWM_MAT2_OFFSET)
|
||||
#define LPC17_MCPWM_DT (LPC17_MCPWM_BASE+LPC17_MCPWM_DT_OFFSET)
|
||||
#define LPC17_MCPWM_CP (LPC17_MCPWM_BASE+LPC17_MCPWM_CP_OFFSET)
|
||||
#define LPC17_MCPWM_CAP0 (LPC17_MCPWM_BASE+LPC17_MCPWM_CAP0_OFFSET)
|
||||
#define LPC17_MCPWM_CAP1 (LPC17_MCPWM_BASE+LPC17_MCPWM_CAP1_OFFSET)
|
||||
#define LPC17_MCPWM_CAP2 (LPC17_MCPWM_BASE+LPC17_MCPWM_CAP2_OFFSET)
|
||||
#define LPC17_MCPWM_INTEN (LPC17_MCPWM_BASE+LPC17_MCPWM_INTEN_OFFSET)
|
||||
#define LPC17_MCPWM_INTENSET (LPC17_MCPWM_BASE+LPC17_MCPWM_INTENSET_OFFSET)
|
||||
#define LPC17_MCPWM_INTENCLR (LPC17_MCPWM_BASE+LPC17_MCPWM_INTENCLR_OFFSET)
|
||||
#define LPC17_MCPWM_CNTCON (LPC17_MCPWM_BASE+LPC17_MCPWM_CNTCON_OFFSET)
|
||||
#define LPC17_MCPWM_CNTCONSET (LPC17_MCPWM_BASE+LPC17_MCPWM_CNTCONSET_OFFSET)
|
||||
#define LPC17_MCPWM_CNTCONCLR (LPC17_MCPWM_BASE+LPC17_MCPWM_CNTCONCLR_OFFSET)
|
||||
#define LPC17_MCPWM_INTF (LPC17_MCPWM_BASE+LPC17_MCPWM_INTF_OFFSET)
|
||||
#define LPC17_MCPWM_INTFSET (LPC17_MCPWM_BASE+LPC17_MCPWM_INTFSET_OFFSET)
|
||||
#define LPC17_MCPWM_INTFCLR (LPC17_MCPWM_BASE+LPC17_MCPWM_INTFCLR_OFFSET)
|
||||
#define LPC17_MCPWM_CAPCLR (LPC17_MCPWM_BASE+LPC17_MCPWM_CAPCLR_OFFSET)
|
||||
|
||||
/* Register bit definitions *********************************************************/
|
||||
/* There are no bit field definitions for the following registers because they support
|
||||
* 32-bit values:
|
||||
*
|
||||
* - Timer Counter register, channel 0 (TC0), Timer Counter register, channel 1 (TC1),
|
||||
* and Timer Counter register, channel 2 (TC2): 32-bit Timer/Counter values for
|
||||
* channels 0, 1, 2 (no bit field definitions)
|
||||
*
|
||||
* - Limit register, channel 0 (LIM0), Limit register, channel 1 (LIM1), and Limit
|
||||
* register, channel 2 (LIM2): 32-bit Limit values for TC0, 1, 2 (no bit field
|
||||
* definitions)
|
||||
*
|
||||
* - Match register, channel 0 MAT0), Match register, channel 1 (MAT1), and Match
|
||||
* register, channel 2 (MAT2): 32-bit Match values for TC0, 1, 2 (no bit field
|
||||
* definitions).
|
||||
*
|
||||
* - Capture register, channel 0 (CAP0), Capture register, channel 1 (CAP1), and
|
||||
* Capture register, channel 2 (CAP2): 32-bit TC value at a capture event for
|
||||
* channels 0, 1, 2 (no bit field definitions)
|
||||
*/
|
||||
|
||||
/* PWM Control read address (CON), PWM Control set address (CONSET), and PWM Control
|
||||
* clear address (CONCLR) common regiser bit definitions.
|
||||
*/
|
||||
|
||||
#define MCPWM_CON_RUN0 (1 << 0) /* Bit 0: Stops/starts timer channel 0 */
|
||||
#define MCPWM_CON_CENTER0 (1 << 1) /* Bit 1: Chan 0 edge/center aligned operation */
|
||||
#define MCPWM_CON_POLA0 (1 << 2) /* Bit 2: Polarity of MCOA0 and MCOB0 */
|
||||
#define MCPWM_CON_DTE0 (1 << 3) /* Bit 3: Dead time feature control */
|
||||
#define MCPWM_CON_DISUP0 (1 << 4) /* Bit 4: Enable/disable register updates */
|
||||
/* Bits 5-7: Reserved */
|
||||
#define MCPWM_CON_RUN1 (1 << 8) /* Bit 8: Stops/starts timer channel 1 */
|
||||
#define MCPWM_CON_CENTER1 (1 << 9) /* Bit 9: Chan 1 edge/center aligned operation */
|
||||
#define MCPWM_CON_POLA1 (1 << 10) /* Bit 10: Polarity of MCOA1 and MCOB1 */
|
||||
#define MCPWM_CON_DTE1 (1 << 11) /* Bit 11: Dead time feature control */
|
||||
#define MCPWM_CON_DISUP1 (1 << 12) /* Bit 12: Enable/disable register updates */
|
||||
/* Bits 13-15: Reserved */
|
||||
#define MCPWM_CON_RUN2 (1 << 16) /* Bit 16: Stops/starts timer channel 2 */
|
||||
#define MCPWM_CON_CENTER2 (1 << 17) /* Bit 17: Chan 2 edge/center aligned operation */
|
||||
#define MCPWM_CON_POLA2 (1 << 18) /* Bit 18: Polarity of MCOA1 and MCOB1 */
|
||||
#define MCPWM_CON_DTE2 (1 << 19) /* Bit 19: Dead time feature control */
|
||||
#define MCPWM_CON_DISUP2 (1 << 20) /* Bit 20: Enable/disable register updates */
|
||||
/* Bits 21-28: Reserved */
|
||||
#define MCPWM_CON_INVBDC (1 << 29) /* Bit 29: Polarity of MCOB outputs (all channels) */
|
||||
#define MCPWM_CON_ACMODE (1 << 30) /* Bit 30: 3-phase AC mode select */
|
||||
#define MCPWM_CON_DCMODE (1 << 31) /* Bit 31: 3-phase DC mode select */
|
||||
|
||||
/* Capture Control read address (CAPCON), Capture Control set address (CAPCONSET),
|
||||
* and Event Control clear address (CAPCONCLR) common register bit defintions
|
||||
*/
|
||||
|
||||
#define MCPWM_CAPCON_CAP0MCI0RE (1 << 0) /* Bit 0: Enable chan0 rising edge capture MCI0 */
|
||||
#define MCPWM_CAPCON_CAP0MCI0FE (1 << 1) /* Bit 1: Enable chan 0 falling edge capture MCI0 */
|
||||
#define MCPWM_CAPCON_CAP0MCI1RE (1 << 2) /* Bit 2: Enable chan 0 rising edge capture MCI1 */
|
||||
#define MCPWM_CAPCON_CAP0MCI1FE (1 << 3) /* Bit 3: Enable chan 0 falling edge capture MCI1 */
|
||||
#define MCPWM_CAPCON_CAP0MCI2RE (1 << 4) /* Bit 4: Enable chan 0 rising edge capture MCI2 */
|
||||
#define MCPWM_CAPCON_CAP0MCI2FE (1 << 5) /* Bit 5: Enable chan 0 falling edge capture MCI2 */
|
||||
#define MCPWM_CAPCON_CAP1MCI0RE (1 << 6) /* Bit 6: Enable chan 1 rising edge capture MCI0 */
|
||||
#define MCPWM_CAPCON_CAP1MCI0FE (1 << 7) /* Bit 7: Enable chan 1 falling edge capture MCI0 */
|
||||
#define MCPWM_CAPCON_CAP1MCI1RE (1 << 8) /* Bit 8: Enable chan 1 rising edge capture MCI1 */
|
||||
#define MCPWM_CAPCON_CAP1MCI1FE (1 << 9) /* Bit 9: Enable chan 1 falling edge capture MCI1 */
|
||||
#define MCPWM_CAPCON_CAP1MCI2RE (1 << 10) /* Bit 10: Enable chan 1 rising edge capture MCI2 */
|
||||
#define MCPWM_CAPCON_CAP1MCI2FE (1 << 11) /* Bit 11: Enable chan 1 falling edge capture MCI2 */
|
||||
#define MCPWM_CAPCON_CAP2MCI0RE (1 << 12) /* Bit 12: Enable chan 2 rising edge capture MCI0 */
|
||||
#define MCPWM_CAPCON_CAP2MCI0FE (1 << 13) /* Bit 13: Enable chan 2 falling edge capture MCI0 */
|
||||
#define MCPWM_CAPCON_CAP2MCI1RE (1 << 14) /* Bit 14: Enable chan 2 rising edge capture MCI1 */
|
||||
#define MCPWM_CAPCON_CAP2MCI1FE (1 << 15) /* Bit 15: Enable chan 2 falling edge capture MCI1 */
|
||||
#define MCPWM_CAPCON_CAP2MCI2RE (1 << 16) /* Bit 16: Enable chan 2 rising edge capture MCI2 */
|
||||
#define MCPWM_CAPCON_CAP2MCI2FE (1 << 17) /* Bit 17: Enable chan 2 falling edge capture MCI2 */
|
||||
#define MCPWM_CAPCON_RT0 (1 << 18) /* Bit 18: TC0 reset by chan 0 capture event */
|
||||
#define MCPWM_CAPCON_RT1 (1 << 19) /* Bit 19: TC1 reset by chan 1 capture event */
|
||||
#define MCPWM_CAPCON_RT2 (1 << 20) /* Bit 20: TC2 reset by chan 2 capture event */
|
||||
#define MCPWM_CAPCON_HNFCAP0 (1 << 21) /* Bit 21: Hardware noise filter */
|
||||
#define MCPWM_CAPCON_HNFCAP1 (1 << 22) /* Bit 22: Hardware noise filter */
|
||||
#define MCPWM_CAPCON_HNFCAP2 (1 << 23) /* Bit 23: Hardware noise filter */
|
||||
/* Bits 24-31: Reserved */
|
||||
/* Dead time register */
|
||||
|
||||
#define MCPWM_DT_DT0_SHIFT (0) /* Bits 0-9: Dead time for channel 0 */
|
||||
#define MCPWM_DT_DT0_MASK (0x03ff << MCPWM_DT_DT0_SHIFT)
|
||||
#define MCPWM_DT_DT1_SHIFT (10) /* Bits 10-19: Dead time for channel 1 */
|
||||
#define MCPWM_DT_DT1_MASK (0x03ff << MCPWM_DT_DT1_SHIFT)
|
||||
#define MCPWM_DT_DT2_SHIFT (20) /* Bits 20-29: Dead time for channel 2 */
|
||||
#define MCPWM_DT_DT2_MASK (0x03ff << MCPWM_DT_DT2_SHIFT)
|
||||
/* Bits 30-31: reserved */
|
||||
/* Commutation Pattern register */
|
||||
|
||||
#define MCPWM_CP_CCPA0 (1 << 0) /* Bit 0: Iinternal MCOA0 */
|
||||
#define MCPWM_CP_CCPB0 (1 << 1) /* Bit 1: MCOB0 tracks internal MCOA0 */
|
||||
#define MCPWM_CP_CCPA1 (1 << 2) /* Bit 2: MCOA1 tracks internal MCOA0 */
|
||||
#define MCPWM_CP_CCPB1 (1 << 3) /* Bit 3: MCOB1 tracks internal MCOA0 */
|
||||
#define MCPWM_CP_CCPA2 (1 << 4) /* Bit 4: MCOA2 tracks internal MCOA0 */
|
||||
#define MCPWM_CP_CCPB2 (1 << 5) /* Bit 5: MCOB2 tracks internal MCOA0 */
|
||||
/* Bits 6-31: reserved */
|
||||
|
||||
/* Interrupt Enable read address (INTEN), Interrupt Enable set address (INTENSET),
|
||||
* Interrupt Enable clear address (INTENCLR), Interrupt flags read address (INTF),
|
||||
* Interrupt flags set address (INTFSET), and Interrupt flags clear address (INTFCLR)
|
||||
* common bit field definitions
|
||||
*/
|
||||
|
||||
#define MCPWM_INT_ILIM0 (1 << 0) /* Bit 0: Limit interrupts for channel 0 */
|
||||
#define MCPWM_INT_IMAT0 (1 << 1) /* Bit 1: Match interrupts for channel 0 */
|
||||
#define MCPWM_INT_ICAP0 (1 << 2) /* Bit 2: Capture interrupts for channel 0 */
|
||||
/* Bit 3: Reserved */
|
||||
#define MCPWM_INT_ILIM1 (1 << 4) /* Bit 4: Limit interrupts for channel 1 */
|
||||
#define MCPWM_INT_IMAT1 (1 << 5) /* Bit 5: Match interrupts for channel 1 */
|
||||
#define MCPWM_INT_ICAP1 (1 << 6) /* Bit 6: Capture interrupts for channel 1 */
|
||||
/* Bit 7: Reserved */
|
||||
#define MCPWM_INT_ILIM2 (1 << 8) /* Bit 8: Limit interrupts for channel 2 */
|
||||
#define MCPWM_INT_IMAT2 (1 << 9) /* Bit 9: Match interrupts for channel 2 */
|
||||
#define MCPWM_INT_ICAP2 (1 << 10) /* Bit 10: Capture interrupts for channel 2 */
|
||||
/* Bits 11-14: Reserved */
|
||||
#define MCPWM_INT_ABORT (1 << 15) /* Bit 15: Fast abort interrupt */
|
||||
/* Bits 16-31: Reserved */
|
||||
|
||||
/* Count Control read address (CNTCON), Count Control set address (CNTCONSET), and
|
||||
* Count Control clear address (CNTCONCLR) common register bit definitions.
|
||||
*/
|
||||
|
||||
#define MCPWM_CNTCON_TC0MCI0RE (1 << 0) /* Bit 0: Counter 0 incr on rising edge MCI0 */
|
||||
#define MCPWM_CNTCON_TC0MCI0FE (1 << 1) /* Bit 1: Counter 0 incr onfalling edge MCI0 */
|
||||
#define MCPWM_CNTCON_TC0MCI1RE (1 << 2) /* Bit 2: Counter 0 incr onrising edge MCI1 */
|
||||
#define MCPWM_CNTCON_TC0MCI1FE (1 << 3) /* Bit 3: Counter 0 incr onfalling edge MCI1 */
|
||||
#define MCPWM_CNTCON_TC0MCI2RE (1 << 4) /* Bit 4: Counter 0 incr onrising edge MCI2 */
|
||||
#define MCPWM_CNTCON_TC0MCI2FE (1 << 5) /* Bit 5: Counter 0 incr onfalling edge MCI2 */
|
||||
#define MCPWM_CNTCON_TC1MCI0RE (1 << 6) /* Bit 6: Counter 1 incr onrising edge MCI0 */
|
||||
#define MCPWM_CNTCON_TC1MCI0FE (1 << 7) /* Bit 7: Counter 1 incr onfalling edge MCI0 */
|
||||
#define MCPWM_CNTCON_TC1MCI1RE (1 << 8) /* Bit 8: Counter 1 incr onrising edge MCI1 */
|
||||
#define MCPWM_CNTCON_TC1MCI1FE (1 << 9) /* Bit 9: Counter 1 incr onfalling edge MCI1 */
|
||||
#define MCPWM_CNTCON_TC1MCI2RE (1 << 10) /* Bit 10: Counter 1 incr onrising edge MCI2 */
|
||||
#define MCPWM_CNTCON_TC1MCI2FE (1 << 11) /* Bit 11: Counter 1 incr onfalling edge MCI2 */
|
||||
#define MCPWM_CNTCON_TC2MCI0RE (1 << 12) /* Bit 12: Counter 2 incr onrising edge MCI0 */
|
||||
#define MCPWM_CNTCON_TC2MCI0FE (1 << 13) /* Bit 13: Counter 2 incr onfalling edge MCI0 */
|
||||
#define MCPWM_CNTCON_TC2MCI1RE (1 << 14) /* Bit 14: Counter 2 incr onrising edge MCI1 */
|
||||
#define MCPWM_CNTCON_TC2MCI1FE (1 << 15) /* Bit 15: Counter 2 incr onfalling edge MCI1 */
|
||||
#define MCPWM_CNTCON_TC2MCI2RE (1 << 16) /* Bit 16: Counter 2 incr onrising edge MCI2 */
|
||||
#define MCPWM_CNTCON_TC2MCI2FE (1 << 17) /* Bit 17: Counter 2 incr onfalling edge MCI2 */
|
||||
/* Bits 28-28: Reserved */
|
||||
#define MCPWM_CNTCON_CNTR0 (1 << 29) /* Bit 29: Channel 0 counter mode */
|
||||
#define MCPWM_CNTCON_CNTR1 (1 << 30) /* Bit 30: Channel 1 counter mode */
|
||||
#define MCPWM_CNTCON_CNTR2 (1 << 31) /* Bit 31: Channel 2 counter mode */
|
||||
|
||||
/* Capture clear address */
|
||||
|
||||
#define MCPWM_CAPCLR_MCCLR0 (1 << 0) /* Bit 0: Clear MCCAP0 register */
|
||||
#define MCPWM_CAPCLR_MCCLR1 (1 << 1) /* Bit 1: Clear MCCAP1 register */
|
||||
#define MCPWM_CAPCLR_MCCLR2 (1 << 2) /* Bit 2: Clear MCCAP2 register */
|
||||
/* Bits 2-31: Reserved */
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_MCPWM_H */
|
||||
@@ -1,223 +0,0 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/lpc17xx/hardware/lpc17_pwm.h
|
||||
*
|
||||
* Copyright (C) 2010 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_PWM_H
|
||||
#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_PWM_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "hardware/lpc17_memorymap.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register offsets *****************************************************************/
|
||||
|
||||
#define LPC17_PWM_IR_OFFSET 0x0000 /* Interrupt Register */
|
||||
#define LPC17_PWM_TCR_OFFSET 0x0004 /* Timer Control Register */
|
||||
#define LPC17_PWM_TC_OFFSET 0x0008 /* Timer Counter */
|
||||
#define LPC17_PWM_PR_OFFSET 0x000c /* Prescale Register */
|
||||
#define LPC17_PWM_PC_OFFSET 0x0010 /* Prescale Counter */
|
||||
#define LPC17_PWM_MCR_OFFSET 0x0014 /* Match Control Register */
|
||||
#define LPC17_PWM_MR0_OFFSET 0x0018 /* Match Register 0 */
|
||||
#define LPC17_PWM_MR1_OFFSET 0x001c /* Match Register 1 */
|
||||
#define LPC17_PWM_MR2_OFFSET 0x0020 /* Match Register 2 */
|
||||
#define LPC17_PWM_MR3_OFFSET 0x0024 /* Match Register 3 */
|
||||
#define LPC17_PWM_CCR_OFFSET 0x0028 /* Capture Control Register */
|
||||
#define LPC17_PWM_CR0_OFFSET 0x002c /* Capture Register 0 */
|
||||
#define LPC17_PWM_CR1_OFFSET 0x0030 /* Capture Register 1 */
|
||||
#define LPC17_PWM_CR2_OFFSET 0x0034 /* Capture Register 2 */
|
||||
#define LPC17_PWM_CR3_OFFSET 0x0038 /* Capture Register 3 */
|
||||
#define LPC17_PWM_MR4_OFFSET 0x0040 /* Match Register 4 */
|
||||
#define LPC17_PWM_MR5_OFFSET 0x0044 /* Match Register 5 */
|
||||
#define LPC17_PWM_MR6_OFFSET 0x0048 /* Match Register 6 */
|
||||
#define LPC17_PWM_PCR_OFFSET 0x004c /* PWM Control Register */
|
||||
#define LPC17_PWM_LER_OFFSET 0x0050 /* Load Enable Register */
|
||||
#define LPC17_PWM_CTCR_OFFSET 0x0070 /* Counter/Timer Control Register */
|
||||
|
||||
/* Register addresses ***************************************************************/
|
||||
|
||||
#define LPC17_PWM1_IR (LPC17_PWM1_BASE+LPC17_PWM_IR_OFFSET)
|
||||
#define LPC17_PWM1_TCR (LPC17_PWM1_BASE+LPC17_PWM_TCR_OFFSET)
|
||||
#define LPC17_PWM1_TC (LPC17_PWM1_BASE+LPC17_PWM_TC_OFFSET)
|
||||
#define LPC17_PWM1_PR (LPC17_PWM1_BASE+LPC17_PWM_PR_OFFSET)
|
||||
#define LPC17_PWM1_PC (LPC17_PWM1_BASE+LPC17_PWM_PC_OFFSET)
|
||||
#define LPC17_PWM1_MCR (LPC17_PWM1_BASE+LPC17_PWM_MCR_OFFSET)
|
||||
#define LPC17_PWM1_MR0 (LPC17_PWM1_BASE+LPC17_PWM_MR0_OFFSET)
|
||||
#define LPC17_PWM1_MR1 (LPC17_PWM1_BASE+LPC17_PWM_MR1_OFFSET)
|
||||
#define LPC17_PWM1_MR2 (LPC17_PWM1_BASE+LPC17_PWM_MR2_OFFSET)
|
||||
#define LPC17_PWM1_MR3 (LPC17_PWM1_BASE+LPC17_PWM_MR3_OFFSET)
|
||||
#define LPC17_PWM1_MR4 (LPC17_PWM1_BASE+LPC17_PWM_MR4_OFFSET)
|
||||
#define LPC17_PWM1_MR5 (LPC17_PWM1_BASE+LPC17_PWM_MR5_OFFSET)
|
||||
#define LPC17_PWM1_MR6 (LPC17_PWM1_BASE+LPC17_PWM_MR6_OFFSET)
|
||||
#define LPC17_PWM1_CCR (LPC17_PWM1_BASE+LPC17_PWM_CCR_OFFSET)
|
||||
#define LPC17_PWM1_CR0 (LPC17_PWM1_BASE+LPC17_PWM_CR0_OFFSET)
|
||||
#define LPC17_PWM1_CR1 (LPC17_PWM1_BASE+LPC17_PWM_CR1_OFFSET)
|
||||
#define LPC17_PWM1_CR2 (LPC17_PWM1_BASE+LPC17_PWM_CR2_OFFSET)
|
||||
#define LPC17_PWM1_CR3 (LPC17_PWM1_BASE+LPC17_PWM_CR3_OFFSET)
|
||||
#define LPC17_PWM1_PCR (LPC17_PWM1_BASE+LPC17_PWM_PCR_OFFSET)
|
||||
#define LPC17_PWM1_LER (LPC17_PWM1_BASE+LPC17_PWM_LER_OFFSET)
|
||||
#define LPC17_PWM1_CTCR (LPC17_PWM1_BASE+LPC17_PWM_CTCR_OFFSET)
|
||||
|
||||
/* Register bit definitions *********************************************************/
|
||||
/* Registers holding 32-bit numeric values (no bit field definitions):
|
||||
*
|
||||
* Timer Counter (TC)
|
||||
* Prescale Register (PR)
|
||||
* Prescale Counter (PC)
|
||||
* Match Register 0 (MR0)
|
||||
* Match Register 1 (MR1)
|
||||
* Match Register 2 (MR2)
|
||||
* Match Register 3 (MR3)
|
||||
* Match Register 4 (MR3)
|
||||
* Match Register 5 (MR3)
|
||||
* Match Register 6 (MR3)
|
||||
* Capture Register 0 (CR0)
|
||||
* Capture Register 1 (CR1)
|
||||
* Capture Register 1 (CR2)
|
||||
* Capture Register 1 (CR3)
|
||||
*/
|
||||
|
||||
/* Interrupt Register */
|
||||
|
||||
#define PWM_IR_MR0 (1 << 0) /* Bit 0: PWM match channel 0 interrupt */
|
||||
#define PWM_IR_MR1 (1 << 1) /* Bit 1: PWM match channel 1 interrupt */
|
||||
#define PWM_IR_MR2 (1 << 2) /* Bit 2: PWM match channel 2 interrupt */
|
||||
#define PWM_IR_MR3 (1 << 3) /* Bit 3: PWM match channel 3 interrupt */
|
||||
#define PWM_IR_CAP0 (1 << 4) /* Bit 4: Capture input 0 interrupt */
|
||||
#define PWM_IR_CAP1 (1 << 5) /* Bit 5: Capture input 1 interrupt */
|
||||
/* Bits 6-7: Reserved */
|
||||
#define PWM_IR_MR4 (1 << 8) /* Bit 8: PWM match channel 4 interrupt */
|
||||
#define PWM_IR_MR5 (1 << 9) /* Bit 9: PWM match channel 5 interrupt */
|
||||
#define PWM_IR_MR6 (1 << 10) /* Bit 10: PWM match channel 6 interrupt */
|
||||
/* Bits 11-31: Reserved */
|
||||
/* Timer Control Register */
|
||||
|
||||
#define PWM_TCR_CNTREN (1 << 0) /* Bit 0: Counter Enable */
|
||||
#define PWM_TCR_CNTRRST (1 << 1) /* Bit 1: Counter Reset */
|
||||
/* Bit 2: Reserved */
|
||||
#define PWM_TCR_PWMEN (1 << 3) /* Bit 3: PWM Enable */
|
||||
/* Bits 4-31: Reserved */
|
||||
/* Match Control Register */
|
||||
|
||||
#define PWM_MCR_MR0I (1 << 0) /* Bit 0: Interrupt on MR0 */
|
||||
#define PWM_MCR_MR0R (1 << 1) /* Bit 1: Reset on MR0 */
|
||||
#define PWM_MCR_MR0S (1 << 2) /* Bit 2: Stop on MR0 */
|
||||
#define PWM_MCR_MR1I (1 << 3) /* Bit 3: Interrupt on MR1 */
|
||||
#define PWM_MCR_MR1R (1 << 4) /* Bit 4: Reset on MR1 */
|
||||
#define PWM_MCR_MR1S (1 << 5) /* Bit 5: Stop on MR1 */
|
||||
#define PWM_MCR_MR2I (1 << 6) /* Bit 6: Interrupt on MR2 */
|
||||
#define PWM_MCR_MR2R (1 << 7) /* Bit 7: Reset on MR2 */
|
||||
#define PWM_MCR_MR2S (1 << 8) /* Bit 8: Stop on MR2 */
|
||||
#define PWM_MCR_MR3I (1 << 9) /* Bit 9: Interrupt on MR3 */
|
||||
#define PWM_MCR_MR3R (1 << 10) /* Bit 10: Reset on MR3 */
|
||||
#define PWM_MCR_MR3S (1 << 11) /* Bit 11: Stop on MR3 */
|
||||
#define PWM_MCR_MR4I (1 << 12) /* Bit 12: Interrupt on MR4 */
|
||||
#define PWM_MCR_MR4R (1 << 13) /* Bit 13: Reset on MR4 */
|
||||
#define PWM_MCR_MR4S (1 << 14) /* Bit 14: Stop on MR4 */
|
||||
#define PWM_MCR_MR5I (1 << 15) /* Bit 15: Interrupt on MR5 */
|
||||
#define PWM_MCR_MR5R (1 << 16) /* Bit 16: Reset on MR5*/
|
||||
#define PWM_MCR_MR5S (1 << 17) /* Bit 17: Stop on MR5 */
|
||||
#define PWM_MCR_MR6I (1 << 18) /* Bit 18: Interrupt on MR6 */
|
||||
#define PWM_MCR_MR6R (1 << 19) /* Bit 19: Reset on MR6 */
|
||||
#define PWM_MCR_MR6S (1 << 20) /* Bit 20: Stop on MR6 */
|
||||
/* Bits 21-31: Reserved */
|
||||
/* Capture Control Register (Where are CAP2 and 3?) */
|
||||
|
||||
#define PWM_CCR_CAP0RE (1 << 0) /* Bit 0: Capture on CAPn.0 rising edge */
|
||||
#define PWM_CCR_CAP0FE (1 << 1) /* Bit 1: Capture on CAPn.0 falling edg */
|
||||
#define PWM_CCR_CAP0I (1 << 2) /* Bit 2: Interrupt on CAPn.0 */
|
||||
#define PWM_CCR_CAP1RE (1 << 3) /* Bit 3: Capture on CAPn.1 rising edge */
|
||||
#define PWM_CCR_CAP1FE (1 << 4) /* Bit 4: Capture on CAPn.1 falling edg */
|
||||
#define PWM_CCR_CAP1I (1 << 5) /* Bit 5: Interrupt on CAPn.1 */
|
||||
/* Bits 6-31: Reserved */
|
||||
/* PWM Control Register */
|
||||
/* Bits 0-1: Reserved */
|
||||
#define PWM_PCR_SEL2 (1 << 2) /* Bit 2: PWM2 single edge controlled mode */
|
||||
#define PWM_PCR_SEL3 (1 << 3) /* Bit 3: PWM3 single edge controlled mode */
|
||||
#define PWM_PCR_SEL4 (1 << 4) /* Bit 4: PWM4 single edge controlled mode */
|
||||
#define PWM_PCR_SEL5 (1 << 5) /* Bit 5: PWM5 single edge controlled mode */
|
||||
#define PWM_PCR_SEL6 (1 << 6) /* Bit 6: PWM6 single edge controlled mode */
|
||||
/* Bits 7-8: Reserved */
|
||||
#define PWM_PCR_ENA1 (1 << 9) /* Bit 9: Enable PWM1 output */
|
||||
#define PWM_PCR_ENA2 (1 << 10) /* Bit 10: Enable PWM2 output */
|
||||
#define PWM_PCR_ENA3 (1 << 11) /* Bit 11: Enable PWM3 output */
|
||||
#define PWM_PCR_ENA4 (1 << 12) /* Bit 12: Enable PWM4 output */
|
||||
#define PWM_PCR_ENA5 (1 << 13) /* Bit 13: Enable PWM5 output */
|
||||
#define PWM_PCR_ENA6 (1 << 14) /* Bit 14: Enable PWM6 output */
|
||||
/* Bits 15-31: Reserved */
|
||||
/* Load Enable Register */
|
||||
|
||||
#define PWM_LER_M0EN (1 << 0) /* Bit 0: Enable PWM Match 0 Latch */
|
||||
#define PWM_LER_M1EN (1 << 1) /* Bit 1: Enable PWM Match 1 Latch */
|
||||
#define PWM_LER_M2EN (1 << 2) /* Bit 2: Enable PWM Match 2 Latch */
|
||||
#define PWM_LER_M3EN (1 << 3) /* Bit 3: Enable PWM Match 3 Latch */
|
||||
#define PWM_LER_M4EN (1 << 4) /* Bit 4: Enable PWM Match 4 Latch */
|
||||
#define PWM_LER_M5EN (1 << 5) /* Bit 5: Enable PWM Match 5 Latch */
|
||||
#define PWM_LER_M6EN (1 << 6) /* Bit 6: Enable PWM Match 6 Latch */
|
||||
/* Bits 7-31: Reserved */
|
||||
/* Counter/Timer Control Register */
|
||||
|
||||
#define PWM_CTCR_MODE_SHIFT (0) /* Bits 0-1: Counter/Timer Mode */
|
||||
#define PWM_CTCR_MODE_MASK (3 << PWM_CTCR_MODE_SHIFT)
|
||||
# define PWM_CTCR_MODE_TIMER (0 << PWM_CTCR_MODE_SHIFT) /* Timer Mode, prescal match */
|
||||
# define PWM_CTCR_MODE_CNTRRE (1 << PWM_CTCR_MODE_SHIFT) /* Counter Mode, CAP rising edge */
|
||||
# define PWM_CTCR_MODE_CNTRFE (2 << PWM_CTCR_MODE_SHIFT) /* Counter Mode, CAP falling edge */
|
||||
# define PWM_CTCR_MODE_CNTRBE (3 << PWM_CTCR_MODE_SHIFT) /* Counter Mode, CAP both edges */
|
||||
#define PWM_CTCR_INPSEL_SHIFT (2) /* Bits 2-3: Count Input Select */
|
||||
#define PWM_CTCR_INPSEL_MASK (3 << PWM_CTCR_INPSEL_SHIFT)
|
||||
# define PWM_CTCR_INPSEL_CAPNp0 (0 << PWM_CTCR_INPSEL_SHIFT) /* CAPn.0 for TIMERn */
|
||||
# define PWM_CTCR_INPSEL_CAPNp1 (1 << PWM_CTCR_INPSEL_SHIFT) /* CAPn.0 for TIMERn */
|
||||
/* Bits 4-31: Reserved */
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_PWM_H */
|
||||
@@ -1,214 +0,0 @@
|
||||
/********************************************************************************************
|
||||
* arch/arm/src/lpc17xx/hardware/lpc17_qei.h
|
||||
*
|
||||
* Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
********************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_QEI_H
|
||||
#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_QEI_H
|
||||
|
||||
/********************************************************************************************
|
||||
* Included Files
|
||||
********************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "hardware/lpc17_memorymap.h"
|
||||
|
||||
/********************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
********************************************************************************************/
|
||||
|
||||
/* Register offsets *************************************************************************/
|
||||
/* Control registers */
|
||||
|
||||
#define LPC17_QEI_CON_OFFSET 0x0000 /* Control register */
|
||||
#define LPC17_QEI_STAT_OFFSET 0x0004 /* Encoder status register */
|
||||
#define LPC17_QEI_CONF_OFFSET 0x0008 /* Configuration register */
|
||||
|
||||
/* Position, index, and timer registers */
|
||||
|
||||
#define LPC17_QEI_POS_OFFSET 0x000c /* Position register */
|
||||
#define LPC17_QEI_MAXPOS_OFFSET 0x0010 /* Maximum position register */
|
||||
#define LPC17_QEI_CMPOS0_OFFSET 0x0014 /* Position compare register */
|
||||
#define LPC17_QEI_CMPOS1_OFFSET 0x0018 /* Position compare register */
|
||||
#define LPC17_QEI_CMPOS2_OFFSET 0x001c /* Position compare register */
|
||||
#define LPC17_QEI_INXCNT_OFFSET 0x0020 /* Index count register */
|
||||
#define LPC17_QEI_INXCMP_OFFSET 0x0024 /* Index compare register */
|
||||
#define LPC17_QEI_LOAD_OFFSET 0x0028 /* Velocity timer reload register */
|
||||
#define LPC17_QEI_TIME_OFFSET 0x002c /* Velocity timer register */
|
||||
#define LPC17_QEI_VEL_OFFSET 0x0030 /* Velocity counter register */
|
||||
#define LPC17_QEI_CAP_OFFSET 0x0034 /* Velocity capture register */
|
||||
#define LPC17_QEI_VELCOMP_OFFSET 0x0038 /* Velocity compare register */
|
||||
#define LPC17_QEI_FILTER_OFFSET 0x003c /* Digital filter register */
|
||||
|
||||
#ifdef LPC178
|
||||
# define LPC17_QEI_INXCMP0_OFFSET 0x0024 /* Index compare0 register */
|
||||
# define LPC17_QEI_INXCMP1_OFFSET 0x004c /* Index compare1 register */
|
||||
# define LPC17_QEI_INXCMP2_OFFSET 0x0050 /* Index compare2 register */
|
||||
# define LPC17_QEI_FILTER_PHA_OFFSET 0x003c /* Digital filter register */
|
||||
# define LPC17_QEI_FILTER_PHB_OFFSET 0x0040 /* Digital filter register */
|
||||
# define LPC17_QEI_FILTER_INX_OFFSET 0x0044 /* Digital filter register */
|
||||
# define LPC17_QEI_WINDOW_OFFSET 0x0048 /* Index acceptance register */
|
||||
#endif
|
||||
|
||||
/* Interrupt registers */
|
||||
|
||||
#define LPC17_QEI_IEC_OFFSET 0x0fd8 /* Interrupt enable clear register */
|
||||
#define LPC17_QEI_IES_OFFSET 0x0fdc /* Interrupt enable set register */
|
||||
#define LPC17_QEI_INTSTAT_OFFSET 0x0fe0 /* Interrupt status register */
|
||||
#define LPC17_QEI_IE_OFFSET 0x0fe4 /* Interrupt enable register */
|
||||
#define LPC17_QEI_CLR_OFFSET 0x0fe8 /* Interrupt status clear register */
|
||||
#define LPC17_QEI_SET_OFFSET 0x0fec /* Interrupt status set register */
|
||||
|
||||
/* Register addresses ***********************************************************************/
|
||||
/* Control registers */
|
||||
|
||||
#define LPC17_QEI_CON (LPC17_QEI_BASE+LPC17_QEI_CON_OFFSET)
|
||||
#define LPC17_QEI_STAT (LPC17_QEI_BASE+LPC17_QEI_STAT_OFFSET)
|
||||
#define LPC17_QEI_CONF (LPC17_QEI_BASE+LPC17_QEI_CONF_OFFSET)
|
||||
|
||||
/* Position, index, and timer registers */
|
||||
|
||||
#define LPC17_QEI_POS (LPC17_QEI_BASE+LPC17_QEI_POS_OFFSET)
|
||||
#define LPC17_QEI_MAXPOS (LPC17_QEI_BASE+LPC17_QEI_MAXPOS_OFFSET)
|
||||
#define LPC17_QEI_CMPOS0 (LPC17_QEI_BASE+LPC17_QEI_CMPOS0_OFFSET)
|
||||
#define LPC17_QEI_CMPOS1 (LPC17_QEI_BASE+LPC17_QEI_CMPOS1_OFFSET)
|
||||
#define LPC17_QEI_CMPOS2 (LPC17_QEI_BASE+LPC17_QEI_CMPOS2_OFFSET)
|
||||
#define LPC17_QEI_INXCNT (LPC17_QEI_BASE+LPC17_QEI_INXCNT_OFFSET)
|
||||
#define LPC17_QEI_INXCMP (LPC17_QEI_BASE+LPC17_QEI_INXCMP_OFFSET)
|
||||
#define LPC17_QEI_LOAD (LPC17_QEI_BASE+LPC17_QEI_LOAD_OFFSET)
|
||||
#define LPC17_QEI_TIME (LPC17_QEI_BASE+LPC17_QEI_TIME_OFFSET)
|
||||
#define LPC17_QEI_VEL (LPC17_QEI_BASE+LPC17_QEI_VEL_OFFSET)
|
||||
#define LPC17_QEI_CAP (LPC17_QEI_BASE+LPC17_QEI_CAP_OFFSET)
|
||||
#define LPC17_QEI_VELCOMP (LPC17_QEI_BASE+LPC17_QEI_VELCOMP_OFFSET)
|
||||
#define LPC17_QEI_FILTER (LPC17_QEI_BASE+LPC17_QEI_FILTER_OFFSET)
|
||||
|
||||
/* Interrupt registers */
|
||||
|
||||
#define LPC17_QEI_IEC (LPC17_QEI_BASE+LPC17_QEI_IEC_OFFSET)
|
||||
#define LPC17_QEI_IES (LPC17_QEI_BASE+LPC17_QEI_IES_OFFSET)
|
||||
#define LPC17_QEI_INTSTAT (LPC17_QEI_BASE+LPC17_QEI_INTSTAT_OFFSET)
|
||||
#define LPC17_QEI_IE (LPC17_QEI_BASE+LPC17_QEI_IE_OFFSET)
|
||||
#define LPC17_QEI_CLR (LPC17_QEI_BASE+LPC17_QEI_CLR_OFFSET)
|
||||
#define LPC17_QEI_SET (LPC17_QEI_BASE+LPC17_QEI_SET_OFFSET)
|
||||
|
||||
/* Register bit definitions *****************************************************************/
|
||||
/* The following registers hold 32-bit integer values and have no bit fields defined
|
||||
* in this section:
|
||||
*
|
||||
* Position register (POS)
|
||||
* Maximum position register (MAXPOS)
|
||||
* Position compare register 0 (CMPOS0)
|
||||
* Position compare register 1 (CMPOS)
|
||||
* Position compare register 2 (CMPOS2)
|
||||
* Index count register (INXCNT)
|
||||
* Index compare register (INXCMP)
|
||||
* Velocity timer reload register (LOAD)
|
||||
* Velocity timer register (TIME)
|
||||
* Velocity counter register (VEL)
|
||||
* Velocity capture register (CAP)
|
||||
* Velocity compare register (VELCOMP)
|
||||
* Digital filter register (FILTER)
|
||||
*/
|
||||
|
||||
/* Control registers */
|
||||
/* Control register */
|
||||
|
||||
#define QEI_CON_RESP (1 << 0) /* Bit 0: Reset position counter */
|
||||
#define QEI_CON_RESPI (1 << 1) /* Bit 1: Reset position counter on index */
|
||||
#define QEI_CON_RESV (1 << 2) /* Bit 2: Reset velocity */
|
||||
#define QEI_CON_RESI (1 << 3) /* Bit 3: Reset index counter */
|
||||
/* Bits 4-31: reserved */
|
||||
/* Encoder status register */
|
||||
|
||||
#define QEI_STAT_DIR (1 << 0) /* Bit 0: Direction bit */
|
||||
/* Bits 1-31: reserved */
|
||||
/* Configuration register */
|
||||
|
||||
#define QEI_CONF_DIRINV (1 << 0) /* Bit 0: Direction invert */
|
||||
#define QEI_CONF_SIGMODE (1 << 1) /* Bit 1: Signal Mode */
|
||||
#define QEI_CONF_CAPMODE (1 << 2) /* Bit 2: Capture Mode */
|
||||
#define QEI_CONF_INVINX (1 << 3) /* Bit 3: Invert Index */
|
||||
|
||||
#ifdef LPC178x
|
||||
# define QEI_CONF_CRESPI (1 << 4) /* Bit 4: Continuous Index reset */
|
||||
/* Bits 5-15: reserved */
|
||||
# define QEI_CONF_INXGATE_SHIFT (16) /* Bit 16:19 Index Gating */
|
||||
# define QEI_CONF_INXGATE_MASK (15 << QEI_CONF_INXGATE_SHIFT)
|
||||
#endif
|
||||
/* Bits 20-31: reserved */
|
||||
|
||||
/* Position, index, and timer registers (all 32-bit integer values with not bit fields */
|
||||
|
||||
/* Interrupt registers */
|
||||
/* Interrupt enable clear register (IEC), Interrupt enable set register (IES),
|
||||
* Interrupt status register (INTSTAT), Interrupt enable register (IE), Interrupt
|
||||
* status clear register (CLR), and Interrupt status set register (SET) common
|
||||
* bit definitions.
|
||||
*/
|
||||
|
||||
#define QEI_INT_INX (1 << 0) /* Bit 0: Index pulse detected */
|
||||
#define QEI_INT_TIM (1 << 1) /* Bit 1: Velocity timer overflow occurred */
|
||||
#define QEI_INT_VELC (1 << 2) /* Bit 2: Captured velocity less than compare velocity */
|
||||
#define QEI_INT_DIR (1 << 3) /* Bit 3: Change of direction detected */
|
||||
#define QEI_INT_ERR (1 << 4) /* Bit 4: Encoder phase error detected */
|
||||
#define QEI_INT_ENCLK (1 << 5) /* Bit 5: Eencoder clock pulse detected */
|
||||
#define QEI_INT_POS0 (1 << 6) /* Bit 6: Position 0 compare equal to current position */
|
||||
#define QEI_INT_POS1 (1 << 7) /* Bit 7: Position 1 compare equal to current position */
|
||||
#define QEI_INT_POS2 (1 << 8) /* Bit 8: Position 2 compare equal to current position */
|
||||
#define QEI_INT_REV (1 << 9) /* Bit 9: Index compare value equal to current index count */
|
||||
#define QEI_INT_POS0REV (1 << 10) /* Bit 10: Combined position 0 and revolution count interrupt */
|
||||
#define QEI_INT_POS1REV (1 << 11) /* Bit 11: Position 1 and revolution count interrupt */
|
||||
#define QEI_INT_POS2REV (1 << 12) /* Bit 12: Position 2 and revolution count interrupt */
|
||||
|
||||
#ifdef LPC178x
|
||||
# define QEI_INT_REV1 (1 << 13) /* Bit 13: Index compare1 value to current index interrupt */
|
||||
# define QEI_INT_REV2 (1 << 14) /* Bit 14: Index compare2 value to current index interrupt */
|
||||
# define QEI_INT_MAXPOS (1 << 15) /* Bit 15: Current position count interrupt */
|
||||
#endif
|
||||
/* Bits 16-31: reserved */
|
||||
|
||||
/********************************************************************************************
|
||||
* Public Types
|
||||
********************************************************************************************/
|
||||
|
||||
/********************************************************************************************
|
||||
* Public Data
|
||||
********************************************************************************************/
|
||||
|
||||
/********************************************************************************************
|
||||
* Public Functions
|
||||
********************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_QEI_H */
|
||||
@@ -1,277 +0,0 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/lpc17xx/hardware/lpc17_rtc.h
|
||||
*
|
||||
* Copyright (C) 2010, 2012-2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_RTC_H
|
||||
#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_RTC_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "hardware/lpc17_memorymap.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register offsets *****************************************************************/
|
||||
/* Miscellaneous registers */
|
||||
|
||||
#define LPC17_RTC_ILR_OFFSET 0x0000 /* Interrupt Location Register */
|
||||
#define LPC17_RTC_CCR_OFFSET 0x0008 /* Clock Control Register */
|
||||
#define LPC17_RTC_CIIR_OFFSET 0x000c /* Counter Increment Interrupt Register */
|
||||
#define LPC17_RTC_AMR_OFFSET 0x0010 /* Alarm Mask Register */
|
||||
#define LPC17_RTC_AUXEN_OFFSET 0x0058 /* RTC Auxiliary Enable register */
|
||||
#define LPC17_RTC_AUX_OFFSET 0x005c /* RTC Auxiliary control register */
|
||||
|
||||
/* Consolidated time registers */
|
||||
|
||||
#define LPC17_RTC_CTIME0_OFFSET 0x0014 /* Consolidated Time Register 0 */
|
||||
#define LPC17_RTC_CTIME1_OFFSET 0x0018 /* Consolidated Time Register 1 */
|
||||
#define LPC17_RTC_CTIME2_OFFSET 0x001c /* Consolidated Time Register 2 */
|
||||
|
||||
/* Time counter registers */
|
||||
|
||||
#define LPC17_RTC_SEC_OFFSET 0x0020 /* Seconds Counter */
|
||||
#define LPC17_RTC_MIN_OFFSET 0x0024 /* Minutes Register */
|
||||
#define LPC17_RTC_HOUR_OFFSET 0x0028 /* Hours Register */
|
||||
#define LPC17_RTC_DOM_OFFSET 0x002c /* Day of Month Register */
|
||||
#define LPC17_RTC_DOW_OFFSET 0x0030 /* Day of Week Register */
|
||||
#define LPC17_RTC_DOY_OFFSET 0x0034 /* Day of Year Register */
|
||||
#define LPC17_RTC_MONTH_OFFSET 0x0038 /* Months Register */
|
||||
#define LPC17_RTC_YEAR_OFFSET 0x003c /* Years Register */
|
||||
#define LPC17_RTC_CALIB_OFFSET 0x0040 /* Calibration Value Register */
|
||||
|
||||
/* General purpose registers */
|
||||
|
||||
#define LPC17_RTC_GPREG0_OFFSET 0x0044 /* General Purpose Register 0 */
|
||||
#define LPC17_RTC_GPREG1_OFFSET 0x0048 /* General Purpose Register 1 */
|
||||
#define LPC17_RTC_GPREG2_OFFSET 0x004c /* General Purpose Register 2 */
|
||||
#define LPC17_RTC_GPREG3_OFFSET 0x0050 /* General Purpose Register 3 */
|
||||
#define LPC17_RTC_GPREG4_OFFSET 0x0054 /* General Purpose Register 4 */
|
||||
|
||||
/* Alarm register group */
|
||||
|
||||
#define LPC17_RTC_ALSEC_OFFSET 0x0060 /* Alarm value for Seconds */
|
||||
#define LPC17_RTC_ALMIN_OFFSET 0x0064 /* Alarm value for Minutes */
|
||||
#define LPC17_RTC_ALHOUR_OFFSET 0x0068 /* Alarm value for Hours */
|
||||
#define LPC17_RTC_ALDOM_OFFSET 0x006c /* Alarm value for Day of Month */
|
||||
#define LPC17_RTC_ALDOW_OFFSET 0x0070 /* Alarm value for Day of Week */
|
||||
#define LPC17_RTC_ALDOY_OFFSET 0x0074 /* Alarm value for Day of Year */
|
||||
#define LPC17_RTC_ALMON_OFFSET 0x0078 /* Alarm value for Months */
|
||||
#define LPC17_RTC_ALYEAR_OFFSET 0x007c /* Alarm value for Year */
|
||||
|
||||
/* Register addresses ***************************************************************/
|
||||
/* Miscellaneous registers */
|
||||
|
||||
#define LPC17_RTC_ILR (LPC17_RTC_BASE+LPC17_RTC_ILR_OFFSET)
|
||||
#define LPC17_RTC_CCR (LPC17_RTC_BASE+LPC17_RTC_CCR_OFFSET)
|
||||
#define LPC17_RTC_CIIR (LPC17_RTC_BASE+LPC17_RTC_CIIR_OFFSET)
|
||||
#define LPC17_RTC_AMR (LPC17_RTC_BASE+LPC17_RTC_AMR_OFFSET)
|
||||
#define LPC17_RTC_AUXEN (LPC17_RTC_BASE+LPC17_RTC_AUXEN_OFFSET)
|
||||
#define LPC17_RTC_AUX (LPC17_RTC_BASE+LPC17_RTC_AUX_OFFSET)
|
||||
|
||||
/* Consolidated time registers */
|
||||
|
||||
#define LPC17_RTC_CTIME0 (LPC17_RTC_BASE+LPC17_RTC_CTIME0_OFFSET)
|
||||
#define LPC17_RTC_CTIME1 (LPC17_RTC_BASE+LPC17_RTC_CTIME1_OFFSET)
|
||||
#define LPC17_RTC_CTIME2 (LPC17_RTC_BASE+LPC17_RTC_CTIME2_OFFSET)
|
||||
|
||||
/* Time counter registers */
|
||||
|
||||
#define LPC17_RTC_SEC (LPC17_RTC_BASE+LPC17_RTC_SEC_OFFSET)
|
||||
#define LPC17_RTC_MIN (LPC17_RTC_BASE+LPC17_RTC_MIN_OFFSET)
|
||||
#define LPC17_RTC_HOUR (LPC17_RTC_BASE+LPC17_RTC_HOUR_OFFSET)
|
||||
#define LPC17_RTC_DOM (LPC17_RTC_BASE+LPC17_RTC_DOM_OFFSET)
|
||||
#define LPC17_RTC_DOW (LPC17_RTC_BASE+LPC17_RTC_DOW_OFFSET)
|
||||
#define LPC17_RTC_DOY (LPC17_RTC_BASE+LPC17_RTC_DOY_OFFSET)
|
||||
#define LPC17_RTC_MONTH (LPC17_RTC_BASE+LPC17_RTC_MONTH_OFFSET)
|
||||
#define LPC17_RTC_YEAR (LPC17_RTC_BASE+LPC17_RTC_YEAR_OFFSET)
|
||||
#define LPC17_RTC_CALIB (LPC17_RTC_BASE+LPC17_RTC_CALIB_OFFSET)
|
||||
|
||||
/* General purpose registers */
|
||||
|
||||
#define LPC17_RTC_GPREG0 (LPC17_RTC_BASE+LPC17_RTC_GPREG0_OFFSET)
|
||||
#define LPC17_RTC_GPREG1 (LPC17_RTC_BASE+LPC17_RTC_GPREG1_OFFSET)
|
||||
#define LPC17_RTC_GPREG2 (LPC17_RTC_BASE+LPC17_RTC_GPREG2_OFFSET)
|
||||
#define LPC17_RTC_GPREG3 (LPC17_RTC_BASE+LPC17_RTC_GPREG3_OFFSET)
|
||||
#define LPC17_RTC_GPREG4 (LPC17_RTC_BASE+LPC17_RTC_GPREG4_OFFSET)
|
||||
|
||||
/* Alarm register group */
|
||||
|
||||
#define LPC17_RTC_ALSEC (LPC17_RTC_BASE+LPC17_RTC_ALSEC_OFFSET)
|
||||
#define LPC17_RTC_ALMIN (LPC17_RTC_BASE+LPC17_RTC_ALMIN_OFFSET)
|
||||
#define LPC17_RTC_ALHOUR (LPC17_RTC_BASE+LPC17_RTC_ALHOUR_OFFSET)
|
||||
#define LPC17_RTC_ALDOM (LPC17_RTC_BASE+LPC17_RTC_ALDOM_OFFSET)
|
||||
#define LPC17_RTC_ALDOW (LPC17_RTC_BASE+LPC17_RTC_ALDOW_OFFSET)
|
||||
#define LPC17_RTC_ALDOY (LPC17_RTC_BASE+LPC17_RTC_ALDOY_OFFSET)
|
||||
#define LPC17_RTC_ALMON (LPC17_RTC_BASE+LPC17_RTC_ALMON_OFFSET)
|
||||
#define LPC17_RTC_ALYEAR (LPC17_RTC_BASE+LPC17_RTC_ALYEAR_OFFSET)
|
||||
|
||||
/* Register bit definitions *********************************************************/
|
||||
/* The following registers hold 32-bit values and have no bit fields to be defined:
|
||||
*
|
||||
* General Purpose Register 0
|
||||
* General Purpose Register 1
|
||||
* General Purpose Register 2
|
||||
* General Purpose Register 3
|
||||
* General Purpose Register 4
|
||||
*/
|
||||
|
||||
/* Miscellaneous registers */
|
||||
/* Interrupt Location Register */
|
||||
|
||||
#define RTC_ILR_RTCCIF (1 << 0) /* Bit 0: Counter Increment Interrupt */
|
||||
#define RTC_ILR_RTCALF (1 << 1) /* Bit 1: Alarm interrupt */
|
||||
/* Bits 2-31: Reserved */
|
||||
/* Clock Control Register */
|
||||
|
||||
#define RTC_CCR_CLKEN (1 << 0) /* Bit 0: Clock Enable */
|
||||
#define RTC_CCR_CTCRST (1 << 1) /* Bit 1: CTC Reset */
|
||||
/* Bits 2-3: Internal test mode controls */
|
||||
#define RTC_CCR_CCALEN (1 << 4) /* Bit 4: Calibration counter enable */
|
||||
/* Bits 5-31: Reserved */
|
||||
/* Counter Increment Interrupt Register */
|
||||
|
||||
#define RTC_CIIR_IMSEC (1 << 0) /* Bit 0: Second interrupt */
|
||||
#define RTC_CIIR_IMMIN (1 << 1) /* Bit 1: Minute interrupt */
|
||||
#define RTC_CIIR_IMHOUR (1 << 2) /* Bit 2: Hour interrupt */
|
||||
#define RTC_CIIR_IMDOM (1 << 3) /* Bit 3: Day of Month value interrupt */
|
||||
#define RTC_CIIR_IMDOW (1 << 4) /* Bit 4: Day of Week value interrupt */
|
||||
#define RTC_CIIR_IMDOY (1 << 5) /* Bit 5: Day of Year interrupt */
|
||||
#define RTC_CIIR_IMMON (1 << 6) /* Bit 6: Month interrupt */
|
||||
#define RTC_CIIR_IMYEAR (1 << 7) /* Bit 7: Yearinterrupt */
|
||||
/* Bits 8-31: Reserved */
|
||||
/* Alarm Mask Register */
|
||||
|
||||
#define RTC_AMR_SEC (1 << 0) /* Bit 0: Second not compared for alarm */
|
||||
#define RTC_AMR_MIN (1 << 1) /* Bit 1: Minutes not compared for alarm */
|
||||
#define RTC_AMR_HOUR (1 << 2) /* Bit 2: Hour not compared for alarm */
|
||||
#define RTC_AMR_DOM (1 << 3) /* Bit 3: Day of Monthnot compared for alarm */
|
||||
#define RTC_AMR_DOW (1 << 4) /* Bit 4: Day of Week not compared for alarm */
|
||||
#define RTC_AMR_DOY (1 << 5) /* Bit 5: Day of Year not compared for alarm */
|
||||
#define RTC_AMR_MON (1 << 6) /* Bit 6: Month not compared for alarm */
|
||||
#define RTC_AMR_YEAR (1 << 7) /* Bit 7: Year not compared for alarm */
|
||||
/* Bits 8-31: Reserved */
|
||||
|
||||
/* RTC Auxiliary Control Register */
|
||||
/* Bits 0-3: Reserved */
|
||||
#define RTC_AUXEN_RTCOSCF (1 << 4) /* Bit 4: RTC Oscillator Fail detect flag */
|
||||
#ifdef LPC178x
|
||||
/* Bit 5: Reserved */
|
||||
# define RTC_AUXEN_RTCPDOUT (1 << 6) /* Bit 6: RTC power down mode flag */
|
||||
/* Bits 7-31: Reserved */
|
||||
#endif
|
||||
|
||||
/* RTC Auxiliary Enable Register */
|
||||
/* Bits 0-3: Reserved */
|
||||
#define RTC_AUX_OSCFEN (1 << 4) /* Bit 4: Oscillator Fail Detect interrupt enable */
|
||||
/* Bits 5-31: Reserved */
|
||||
|
||||
/* Consolidated Time Registers */
|
||||
/* Consolidated Time Register 0 */
|
||||
|
||||
#define RTC_CTIME0_SEC_SHIFT (0) /* Bits 0-5: Seconds */
|
||||
#define RTC_CTIME0_SEC_MASK (63 << RTC_CTIME0_SEC_SHIFT)
|
||||
/* Bits 6-7: Reserved */
|
||||
#define RTC_CTIME0_MIN_SHIFT (8) /* Bits 8-13: Minutes */
|
||||
#define RTC_CTIME0_MIN_MASK (63 << RTC_CTIME0_MIN_SHIFT)
|
||||
/* Bits 14-15: Reserved */
|
||||
#define RTC_CTIME0_HOURS_SHIFT (16) /* Bits 16-20: Hours */
|
||||
#define RTC_CTIME0_HOURS_MASK (31 << RTC_CTIME0_HOURS_SHIFT)
|
||||
/* Bits 21-23: Reserved */
|
||||
#define RTC_CTIME0_DOW_SHIFT (24) /* Bits 24-26: Day of Week */
|
||||
#define RTC_CTIME0_DOW_MASK (7 << RTC_CTIME0_DOW_SHIFT)
|
||||
/* Bits 27-31: Reserved */
|
||||
/* Consolidated Time Register 1 */
|
||||
|
||||
#define RTC_CTIME1_DOM_SHIFT (0) /* Bits 0-4: Day of Month */
|
||||
#define RTC_CTIME1_DOM_MASK (31 << RTC_CTIME1_DOM_SHIFT)
|
||||
/* Bits 5-7: Reserved */
|
||||
#define RTC_CTIME1_MON_SHIFT (8) /* Bits 8-11: Month */
|
||||
#define RTC_CTIME1_MON_MASK (15 << RTC_CTIME1_MON_SHIFT)
|
||||
/* Bits 12-15: Reserved */
|
||||
#define RTC_CTIME1_YEAR_SHIFT (16) /* Bits 16-27: Year */
|
||||
#define RTC_CTIME1_YEAR_MASK (0x0fff << RTC_CTIME1_YEAR_SHIFT)
|
||||
/* Bits 28-31: Reserved */
|
||||
/* Consolidated Time Register 2 */
|
||||
|
||||
#define RTC_CTIME2_DOY_SHIFT (0) /* Bits 0-11: Day of Year */
|
||||
#define RTC_CTIME2_DOY_MASK (0x0fff << RTC_CTIME2_DOY_SHIFT)
|
||||
/* Bits 12-31: Reserved */
|
||||
/* Time counter registers */
|
||||
|
||||
#define RTC_SEC_MASK (0x003f)
|
||||
#define RTC_MIN_MASK (0x003f)
|
||||
#define RTC_HOUR_MASK (0x001f)
|
||||
#define RTC_DOM_MASK (0x001f)
|
||||
#define RTC_DOW_MASK (0x0007)
|
||||
#define RTC_DOY_MASK (0x01ff)
|
||||
#define RTC_MONTH_MASK (0x000f)
|
||||
#define RTC_YEAR_MASK (0x0fff)
|
||||
|
||||
/* Calibration Value Register */
|
||||
|
||||
#define RTC_CALIB_CALVAL_SHIFT (0) /* Bits 0-16: calibration counter counts to this value */
|
||||
#define RTC_CALIB_CALVAL_MASK (0xffff << RTC_CALIB_CALVAL_SHIFT)
|
||||
#define RTC_CALIB_CALDIR (1 << 17) /* Bit 17: Calibration direction */
|
||||
/* Bits 18-31: Reserved */
|
||||
/* Alarm register group */
|
||||
|
||||
#define RTC_ALSEC_MASK (0x003f)
|
||||
#define RTC_ALMIN_MASK (0x003f)
|
||||
#define RTC_ALHOUR_MASK (0x001f)
|
||||
#define RTC_ALDOM_MASK (0x001f)
|
||||
#define RTC_ALDOW_MASK (0x0007)
|
||||
#define RTC_ALDOY_MASK (0x01ff)
|
||||
#define RTC_ALMON_MASK (0x000f)
|
||||
#define RTC_ALYEAR_MASK (0x0fff)
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_RTC_H */
|
||||
@@ -1,143 +0,0 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/lpc17xx/hardware/lpc17_rtcevmr.h
|
||||
*
|
||||
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_RTCEVMR_H
|
||||
#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_RTCEVMR_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "hardware/lpc17_memorymap.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register offsets *****************************************************************/
|
||||
|
||||
#define LPC17_RTCEV_ERCONTROL_OFFSET 0x0084 /* Monitor/Recorder Control register */
|
||||
#define LPC17_RTCEV_ERSTATUS_OFFSET 0x0080 /* Status register */
|
||||
#define LPC17_RTCEV_ERCOUNTERS_OFFSET 0x0088 /* Counters register */
|
||||
#define LPC17_RTCEV_ERFIRSTSTAMP0_OFFSET 0x0090 /* Channel 0 first Stamp register */
|
||||
#define LPC17_RTCEV_ERFIRSTSTAMP1_OFFSET 0x0090 /* Channel 1 first Stamp register */
|
||||
#define LPC17_RTCEV_ERFIRSTSTAMP2_OFFSET 0x0090 /* Channel 2 first Stamp register */
|
||||
#define LPC17_RTCEV_ERLASTSTAMP0_OFFSET 0x0098 /* Channel 0 last stamp register */
|
||||
#define LPC17_RTCEV_ERLASTSTAMP1_OFFSET 0x00a0 /* Channel 1 last stamp register */
|
||||
#define LPC17_RTCEV_ERLASTSTAMP2_OFFSET 0x00a8 /* Channel 2 last stamp register */
|
||||
|
||||
#define LPC17_RTCEV_ERCONTROL (LPC17_RTC_BASE+LPC17_RTCEV_ERCONTROL_OFFSET)
|
||||
#define LPC17_RTCEV_ERSTATUS (LPC17_RTC_BASE+LPC17_RTCEV_ERSTATUS_OFFSET)
|
||||
#define LPC17_RTCEV_ERCOUNTERS (LPC17_RTC_BASE+LPC17_RTCEV_ERCOUNTERS_OFFSET)
|
||||
#define LPC17_RTCEV_ERFIRSTSTAMP0 (LPC17_RTC_BASE+LPC17_RTCEV_ERFIRSTSTAMP0_OFFSET)
|
||||
#define LPC17_RTCEV_ERFIRSTSTAMP1 (LPC17_RTC_BASE+LPC17_RTCEV_ERFIRSTSTAMP1_OFFSET)
|
||||
#define LPC17_RTCEV_ERFIRSTSTAMP2 (LPC17_RTC_BASE+LPC17_RTCEV_ERFIRSTSTAMP2_OFFSET)
|
||||
#define LPC17_RTCEV_ERLASTSTAMP0 (LPC17_RTC_BASE+LPC17_RTCEV_ERLASTSTAMP0_OFFSET)
|
||||
#define LPC17_RTCEV_ERLASTSTAMP1 (LPC17_RTC_BASE+LPC17_RTCEV_ERLASTSTAMP1_OFFSET)
|
||||
#define LPC17_RTCEV_ERLASTSTAMP2 (LPC17_RTC_BASE+LPC17_RTCEV_ERLASTSTAMP2_OFFSET)
|
||||
|
||||
/* RTCEV ERCONTROL Event Monitor/Recorder Control Register */
|
||||
|
||||
#define RTCEV_ERCONTROL_INTWAKE_EN0 (1) /* Bit 0: Interrupt/wakeup enable channel 0 */
|
||||
#define RTCEV_ERCONTROL_GPCLEAR_EN0 (1 << 1) /* Bit 1: Automatic clearing of RTC - channel 0 */
|
||||
#define RTCEV_ERCONTROL_POL0 (1 << 2) /* Bit 2: Edge polarity on RTC_EV0 pins */
|
||||
#define RTCEV_ERCONTROL_EV0_INPUT_EN (1 << 3) /* Bit 3: Event enable for channel 0 */
|
||||
/* Bits 4-9: Reserved */
|
||||
#define RTCEV_ERCONTROL_INTWAKE_EN1 (1 << 10) /* Bit 10: Interrupt/wakeup enable - channel 1 */
|
||||
#define RTCEV_ERCONTROL_GPCLEAR_EN1 (1 << 11) /* Bit 11: Automatic clearing of RTC - channel 1 */
|
||||
#define RTCEV_ERCONTROL_POL1 (1 << 12) /* Bit 12: Edge polarity on RTC_EV1 pins */
|
||||
#define RTCEV_ERCONTROL_EV1_INPUT_EN (1 << 13) /* Bit 13: Event enable for channel 1 */
|
||||
/* Bits 14-19: Reserved */
|
||||
#define RTCEV_ERCONTROL_INTWAKE_EN2 (1 << 20) /* Bit 20: Interrupt/wakeup enable - channel 2 */
|
||||
#define RTCEV_ERCONTROL_GPCLEAR_EN2 (1 << 21) /* Bit 21: Automatic clearing of RTC - channel 2 */
|
||||
#define RTCEV_ERCONTROL_POL2 (1 << 22) /* Bit 22: Edge polarity on RTC_EV2 pins */
|
||||
#define RTCEV_ERCONTROL_EV2_INPUT_EN (1 << 23) /* Bit 23: Event enable for channel 1 */
|
||||
/* Bits 24-29: Reserved */
|
||||
#define RTCEV_ERCONTROL_ERMODE_SHIFT (30) /* Bits 30-31: Event monitoring mode */
|
||||
#define RTCEV_ERCONTROL_ERMODE_MASK (3 << RTCEV_ERCONTROL_ERMODE_SHIFT)
|
||||
# define ERMODE0 (0) /* monitor/clocks disabled */
|
||||
# define ERMODE1 (1) /* 16Hz sample clock */
|
||||
# define ERMODE2 (2) /* 64Hz sample clock */
|
||||
# define ERMODE3 (3) /* 1000Hz sample clock */
|
||||
|
||||
/* RTCEV ERSTATUS - Monitor/Recorder Status Register */
|
||||
|
||||
#define RTCEV_ERSTATUS_EV0 (1) /* Bit 0: Event flag - channel 0 */
|
||||
#define RTCEV_ERSTATUS_EV1 (1 << 1) /* Bit 1: Event flag - channel 1 */
|
||||
#define RTCEV_ERSTATUS_EV2 (1 << 2) /* Bit 2: Event flag - channel 2 */
|
||||
#define RTCEV_ERSTATUS_EV2 (1 << 3) /* Bit 3: GPReg async clear flag */
|
||||
/* Bits 4-30: Reserved */
|
||||
#define RTCEV_ERSTATUS_WAKEUP (1 << 31) /* Bit 31: Interrupt/Wakeup request flag */
|
||||
|
||||
/* RTCEV ERCOUNTERS - Monitor/Recorder Counters Register */
|
||||
|
||||
#define RTCEV_ERCOUNTER_COUNTER0_SHIFT (0) /* Bits 0-2: Value for event 0 */
|
||||
#define RTCEV_ERCOUNTER_COUNTER0_MASK (7 << RTCEV_ERCOUNTER_COUNTER0_SHIFT)
|
||||
/* Bits 3-7: Reserved */
|
||||
#define RTCEV_ERCOUNTER_COUNTER1_SHIFT (8) i /* Bits 8-10: Value for event 1 */
|
||||
#define RTCEV_ERCOUNTER_COUNTER1_MASK (7 << RTCEV_ERCOUNTER_COUNTER1_SHIFT)
|
||||
/* Bits 11-15: Reserved */
|
||||
#define RTCEV_ERCOUNTER_COUNTER2_SHIFT (16) /* Bits 16-18: Value for event 2 */
|
||||
#define RTCEV_ERCOUNTER_COUNTER2_MASK (7 << RTCEV_ERCOUNTER_COUNTER2_SHIFT)
|
||||
/* Bits 19-31: Reserved */
|
||||
|
||||
/* RTCEV ERFIRSTSTAMP[0-2] - Monitor/Recorder First Stamp Registers */
|
||||
/* RTCEV ERLASTSTAMP[0-2] - Monitor/Recorder Last Stamp Registers */
|
||||
|
||||
#define RTCEV_TIMESTAMP_SEC_SHIFT (0) /* Bits 0-5: Seconds value 0-59 */
|
||||
#define RTCEV_TIMESTAMP_SEC_MASK (0x3f << RTCEV_TIMESTAMP_SEC_SHIFT)
|
||||
#define RTCEV_TIMESTAMP_MIN_SHIFT (6) /* Bits 6-11: Minutes value 0-59 */
|
||||
#define RTCEV_TIMESTAMP_MIN_MASK (0x3f << RTCEV_TIMESTAMP_MIN_SHIFT)
|
||||
#define RTCEV_TIMESTAMP_HOUR_SHIFT (12) /* Bits 12-16: Hours value 0-23 */
|
||||
#define RTCEV_TIMESTAMP_HOUR_MASK (0x1f << RTCEV_TIMESTAMP_HOUR_SHIFT)
|
||||
#define RTCEV_TIMESTAMP_DOY_SHIFT (17) /* Bits 17-25: Day of the year value 1-366 */
|
||||
#define RTCEV_TIMESTAMP_DOY_MASK (0x1ff << RTCEV_TIMESTAMP_DOY_SHIFT)
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_RTCEVMR_H */
|
||||
@@ -1,272 +0,0 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/lpc17xx/hardware/lpc17_sdcard.h
|
||||
*
|
||||
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_SDCARD_H
|
||||
#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_SDCARD_H
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
#define LPC17_SDCARD_PWR_OFFSET 0x0000 /* SD card power control register */
|
||||
#define LPC17_SDCARD_CLOCK_OFFSET 0x0004 /* SD card clock control register */
|
||||
#define LPC17_SDCARD_ARG_OFFSET 0x0008 /* SD card argument register */
|
||||
#define LPC17_SDCARD_CMD_OFFSET 0x000c /* SD card command register */
|
||||
#define LPC17_SDCARD_RESPCMD_OFFSET 0x0010 /* SD card command response register */
|
||||
#define LPC17_SDCARD_RESP_OFFSET(n) (0x0010+4*(n))
|
||||
# define LPC17_SDCARD_RESP0_OFFSET 0x0014 /* SD card response 1 register */
|
||||
# define LPC17_SDCARD_RESP1_OFFSET 0x0018 /* SD card response 2 register */
|
||||
# define LPC17_SDCARD_RESP2_OFFSET 0x001c /* SD card response 3 register */
|
||||
# define LPC17_SDCARD_RESP3_OFFSET 0x0020 /* SD card response 4 register */
|
||||
#define LPC17_SDCARD_DTIMER_OFFSET 0x0024 /* SD card data timer register */
|
||||
#define LPC17_SDCARD_DLEN_OFFSET 0x0028 /* SD card data length register */
|
||||
#define LPC17_SDCARD_DCTRL_OFFSET 0x002c /* SD card data control register */
|
||||
#define LPC17_SDCARD_DCOUNT_OFFSET 0x0030 /* SD card data counter register */
|
||||
#define LPC17_SDCARD_STATUS_OFFSET 0x0034 /* SD card status register */
|
||||
#define LPC17_SDCARD_CLEAR_OFFSET 0x0038 /* SD card interrupt clear register */
|
||||
#define LPC17_SDCARD_MASK0_OFFSET 0x003c /* SD card mask register */
|
||||
#define LPC17_SDCARD_FIFOCNT_OFFSET 0x0048 /* SD card FIFO counter register */
|
||||
#define LPC17_SDCARD_FIFO_OFFSET 0x0080 /* SD card data FIFO register */
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
#define LPC17_SDCARD_PWR (LPC17_MCI_BASE+LPC17_SDCARD_PWR_OFFSET)
|
||||
#define LPC17_SDCARD_CLOCK (LPC17_MCI_BASE+LPC17_SDCARD_CLOCK_OFFSET)
|
||||
#define LPC17_SDCARD_ARG (LPC17_MCI_BASE+LPC17_SDCARD_ARG_OFFSET)
|
||||
#define LPC17_SDCARD_CMD (LPC17_MCI_BASE+LPC17_SDCARD_CMD_OFFSET)
|
||||
#define LPC17_SDCARD_RESPCMD (LPC17_MCI_BASE+LPC17_SDCARD_RESPCMD_OFFSET)
|
||||
#define LPC17_SDCARD_RESP(n) (LPC17_MCI_BASE+LPC17_SDCARD_RESP_OFFSET(n))
|
||||
#define LPC17_SDCARD_RESP0 (LPC17_MCI_BASE+LPC17_SDCARD_RESP0_OFFSET)
|
||||
#define LPC17_SDCARD_RESP1 (LPC17_MCI_BASE+LPC17_SDCARD_RESP1_OFFSET)
|
||||
#define LPC17_SDCARD_RESP2 (LPC17_MCI_BASE+LPC17_SDCARD_RESP2_OFFSET)
|
||||
#define LPC17_SDCARD_RESP3 (LPC17_MCI_BASE+LPC17_SDCARD_RESP3_OFFSET)
|
||||
#define LPC17_SDCARD_DTIMER (LPC17_MCI_BASE+LPC17_SDCARD_DTIMER_OFFSET)
|
||||
#define LPC17_SDCARD_DLEN (LPC17_MCI_BASE+LPC17_SDCARD_DLEN_OFFSET)
|
||||
#define LPC17_SDCARD_DCTRL (LPC17_MCI_BASE+LPC17_SDCARD_DCTRL_OFFSET)
|
||||
#define LPC17_SDCARD_DCOUNT (LPC17_MCI_BASE+LPC17_SDCARD_DCOUNT_OFFSET)
|
||||
#define LPC17_SDCARD_STATUS (LPC17_MCI_BASE+LPC17_SDCARD_STATUS_OFFSET)
|
||||
#define LPC17_SDCARD_CLEAR (LPC17_MCI_BASE+LPC17_SDCARD_CLEAR_OFFSET)
|
||||
#define LPC17_SDCARD_MASK0 (LPC17_MCI_BASE+LPC17_SDCARD_MASK0_OFFSET)
|
||||
#define LPC17_SDCARD_FIFOCNT (LPC17_MCI_BASE+LPC17_SDCARD_FIFOCNT_OFFSET)
|
||||
#define LPC17_SDCARD_FIFO (LPC17_MCI_BASE+LPC17_SDCARD_FIFO_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
|
||||
/* MCI Power Control Registers - PWR - 0x400c 0000*/
|
||||
|
||||
#define SDCARD_PWR_CTRL_SHIFT (0) /* Bits 0-1: Power supply control bits */
|
||||
#define SDCARD_PWR_CTRL_MASK (3 << SDCARD_PWR_CTRL_SHIFT)
|
||||
# define SDCARD_PWR_CTRL_OFF (0 << SDCARD_PWR_CTRL_SHIFT) /* 00: Power-off: card clock stopped */
|
||||
# define SDCARD_PWR_CTRL_PWRUP (2 << SDCARD_PWR_CTRL_SHIFT) /* 10: Reserved power-up */
|
||||
# define SDCARD_PWR_CTRL_ON (3 << SDCARD_PWR_CTRL_SHIFT) /* 11: Power-on: card is clocked */
|
||||
/* Bits 2-5 Reserved */
|
||||
#define SDCARD_PWR_OPENDRAIN (1 << 6) /* SD_CMD Output Control */
|
||||
#define SDCARD_PWR_ROD (1 << 7) /* Rod Control */
|
||||
/* Bits 8-31: Reserved */
|
||||
#define SDCARD_PWR_RESET (0) /* Reset value */
|
||||
|
||||
/* MCI Clock Control Register - CLOCK - 0x400c 0004 */
|
||||
|
||||
#define SDCARD_CLOCK_CLKDIV_SHIFT (0) /* Bits 7-0: Clock divide factor */
|
||||
#define SDCARD_CLOCK_CLKDIV_MASK (0xff << SDCARD_CLOCK_CLKDIV_SHIFT)
|
||||
#define SDCARD_CLOCK_CLKEN (1 << 8) /* Bit 8: Clock enable bit */
|
||||
#define SDCARD_CLOCK_PWRSAV (1 << 9) /* Bit 9: Power saving configuration bit */
|
||||
#define SDCARD_CLOCK_BYPASS (1 << 10) /* Bit 10: Clock divider bypass enable bit */
|
||||
#define SDCARD_CLOCK_WIDBUS (1 << 11) /* Bit 11: Wide bus mode enable bit */
|
||||
# define SDCARD_CLOCK_WIDBUS_D1 (0) /* 0: Default (SDIO_D0) */
|
||||
# define SDCARD_CLOCK_WIDBUS_D4 (SDCARD_CLOCK_WIDBUS) /* 1: 4-wide (SDIO_D[3:0]) */
|
||||
/* Bits 12-31: Reserved */
|
||||
|
||||
#define SDCARD_CLOCK_RESET (0) /* Reset value */
|
||||
|
||||
/* MCI Argument Register - ARGUMENT - 0x400c 0008 has no bitfields */
|
||||
|
||||
#define SDCARD_ARG_RESET (0) /* Reset value */
|
||||
|
||||
/* MCI Command Register - COMMAND - 0x400c 000c */
|
||||
|
||||
#define SDCARD_CMD_INDEX_SHIFT (0) /* Bits 0-5: Command Index */
|
||||
#define SDCARD_CMD_INDEX_MASK (0x3f << SDCARD_CMD_INDEX_SHIFT)
|
||||
#define SDCARD_CMD_WAITRESP_SHIFT (6) /* Bits 7-6: Wait for response bits */
|
||||
#define SDCARD_CMD_WAITRESP_MASK (3 << SDCARD_CMD_WAITRESP_SHIFT)
|
||||
# define SDCARD_CMD_NORESPONSE (0 << SDCARD_CMD_WAITRESP_SHIFT) /* 00/01: No response */
|
||||
# define SDCARD_CMD_SHORTRESPONSE (1 << SDCARD_CMD_WAITRESP_SHIFT) /* 10: Short response */
|
||||
# define SDCARD_CMD_LONGRESPONSE (3 << SDCARD_CMD_WAITRESP_SHIFT) /* 11: Long response */
|
||||
#define SDCARD_CMD_WAITINT (1 << 8) /* Bit 8: CPSM waits for interrupt request */
|
||||
#define SDCARD_CMD_WAITPEND (1 << 9) /* Bit 9: CPSM Waits for ends of data transfer */
|
||||
#define SDCARD_CMD_CPSMEN (1 << 10) /* Bit 10: Command path state machine enable */
|
||||
/* Bits 11-31: Reserved */
|
||||
|
||||
#define SDCARD_CMD_RESET (0) /* Reset value */
|
||||
|
||||
/* MCI Command Response Register - RESPCOMMAND - 0x400c 0010 */
|
||||
|
||||
#define SDCARD_RESPCMD_SHIFT (0) /* Bits 0-5: Resopnse Command index */
|
||||
#define SDCARD_RESPCMD_MASK (0x3f << SDCARD_RESPCMD_SHIFT)
|
||||
/* Bits 6-31: Reserved */
|
||||
|
||||
/* MCI Response Registers RESPONSE0-3 - 0x400c 0014, 0x400c 0018,
|
||||
No bitfields 0x400c 001c, 0x400c 0020 */
|
||||
|
||||
|
||||
/* MCI - Data Timer Register DATATIMER - 0x400c 0024 */
|
||||
/* No bitfields */
|
||||
|
||||
#define SDCARD_DTIMER_RESET (0) /* Reset value */
|
||||
|
||||
/* MCI - Data Length Register DATALENGTH - 0x400C 0028 */
|
||||
|
||||
#define SDCARD_DATALENGTH_SHIFT (0) /* Bits 0-15: Data length value */
|
||||
#define SDCARD_DATALENGTH_MASK (0xffff << SDCARD_DATALENGTH_SHIFT)
|
||||
/* Bits 16-31: Reserved */
|
||||
|
||||
#define SDCARD_DLEN_RESET (0) /* Reset value */
|
||||
|
||||
/* MCI - Data Control Register - DATACTRL - 0x400c 002c */
|
||||
|
||||
#define SDCARD_DCTRL_DTEN (1 << 0) /* Bit 0: Data transfer enabled bit */
|
||||
#define SDCARD_DCTRL_DTDIR (1 << 1) /* Bit 1: Data transfer direction */
|
||||
#define SDCARD_DCTRL_DTMODE (1 << 2) /* Bit 2: Data transfer mode */
|
||||
#define SDCARD_DCTRL_DMAEN (1 << 3) /* Bit 3: DMA enable bit */
|
||||
#define SDCARD_DCTRL_DBLOCKSIZE_SHIFT (4) /* Bits 4-7: Data block size */
|
||||
#define SDCARD_DCTRL_DBLOCKSIZE_MASK (15 << SDCARD_DCTRL_DBLOCKSIZE_SHIFT)
|
||||
# define SDCARD_DCTRL_1BYTE (0 << SDCARD_DCTRL_DBLOCKSIZE_SHIFT)
|
||||
# define SDCARD_DCTRL_2BYTES (1 << SDCARD_DCTRL_DBLOCKSIZE_SHIFT)
|
||||
# define SDCARD_DCTRL_4BYTES (2 << SDCARD_DCTRL_DBLOCKSIZE_SHIFT)
|
||||
# define SDCARD_DCTRL_8BYTES (3 << SDCARD_DCTRL_DBLOCKSIZE_SHIFT)
|
||||
# define SDCARD_DCTRL_16BYTES (4 << SDCARD_DCTRL_DBLOCKSIZE_SHIFT)
|
||||
# define SDCARD_DCTRL_32BYTES (5 << SDCARD_DCTRL_DBLOCKSIZE_SHIFT)
|
||||
# define SDCARD_DCTRL_64BYTES (6 << SDCARD_DCTRL_DBLOCKSIZE_SHIFT)
|
||||
# define SDCARD_DCTRL_128BYTES (7 << SDCARD_DCTRL_DBLOCKSIZE_SHIFT)
|
||||
# define SDCARD_DCTRL_256BYTES (8 << SDCARD_DCTRL_DBLOCKSIZE_SHIFT)
|
||||
# define SDCARD_DCTRL_512BYTES (9 << SDCARD_DCTRL_DBLOCKSIZE_SHIFT)
|
||||
# define SDCARD_DCTRL_1KBYTE (10 << SDCARD_DCTRL_DBLOCKSIZE_SHIFT)
|
||||
# define SDCARD_DCTRL_2KBYTES (11 << SDCARD_DCTRL_DBLOCKSIZE_SHIFT)
|
||||
/* Bits 8-31: Reserved */
|
||||
|
||||
#define SDCARD_DCTRL_RESET (0) /* Reset value */
|
||||
|
||||
/* MCI - Data Length Register DATALENGTH - 0x400c 0028 */
|
||||
|
||||
#define SDCARD_DATACOUNT_SHIFT (0) /* Bits 0-15: Remaining data */
|
||||
#define SDCARD_DATACOUNT_MASK (0xffff << SDCARD_DATACOUNT_SHIFT)
|
||||
/* Bits 16-31: Reserved */
|
||||
|
||||
/* MCI - Status Register -Status - 0x400c 0034 */
|
||||
|
||||
#define SDCARD_STATUS_CCRCFAIL (1 << 0) /* Bit 0: Command response CRC fail */
|
||||
#define SDCARD_STATUS_DCRCFAIL (1 << 1) /* Bit 1: Data block CRC fail */
|
||||
#define SDCARD_STATUS_CTIMEOUT (1 << 2) /* Bit 2: Command response timeout */
|
||||
#define SDCARD_STATUS_DTIMEOUT (1 << 3) /* Bit 3: Data timeout */
|
||||
#define SDCARD_STATUS_TXUNDERR (1 << 4) /* Bit 4: Transmit FIFO underrun error */
|
||||
#define SDCARD_STATUS_RXOVERR (1 << 5) /* Bit 5: Received FIFO overrun error */
|
||||
#define SDCARD_STATUS_CMDREND (1 << 6) /* Bit 6: Command response received */
|
||||
#define SDCARD_STATUS_CMDSENT (1 << 7) /* Bit 7: Command sent */
|
||||
#define SDCARD_STATUS_DATAEND (1 << 8) /* Bit 8: Data end */
|
||||
#define SDCARD_STATUS_STBITERR (1 << 9) /* Bit 9: Start bit not detected */
|
||||
#define SDCARD_STATUS_DBCKEND (1 << 10) /* Bit 10: Data block sent/received */
|
||||
#define SDCARD_STATUS_CMDACT (1 << 11) /* Bit 11: Command transfer in progress */
|
||||
#define SDCARD_STATUS_TXACT (1 << 12) /* Bit 12: Data transmit in progress */
|
||||
#define SDCARD_STATUS_RXACT (1 << 13) /* Bit 13: Data receive in progress */
|
||||
#define SDCARD_STATUS_TXFIFOHE (1 << 14) /* Bit 14: Transmit FIFO half empty */
|
||||
#define SDCARD_STATUS_RXFIFOHF (1 << 15) /* Bit 15: Receive FIFO half full */
|
||||
#define SDCARD_STATUS_TXFIFOF (1 << 16) /* Bit 16: Transmit FIFO full */
|
||||
#define SDCARD_STATUS_RXFIFOF (1 << 17) /* Bit 17: Receive FIFO full */
|
||||
#define SDCARD_STATUS_TXFIFOE (1 << 18) /* Bit 18: Transmit FIFO empty */
|
||||
#define SDCARD_STATUS_RXFIFOE (1 << 19) /* Bit 19: Receive FIFO empty */
|
||||
#define SDCARD_STATUS_TXDAVL (1 << 20) /* Bit 20: Data available in transmit FIFO */
|
||||
#define SDCARD_STATUS_RXDAVL (1 << 21) /* Bit 21: Data available in receive FIFO */
|
||||
/* Bits 22-31: Reserved */
|
||||
|
||||
/* MCI - Clear Register CLEAR - 0x400c 0038 */
|
||||
|
||||
#define SDCARD_CLEAR_CCRCFAILC (1 << 0) /* Bit 0: CCRCFAIL flag clear bit */
|
||||
#define SDCARD_CLEAR_DCRCFAILC (1 << 1) /* Bit 1: DCRCFAIL flag clear bit */
|
||||
#define SDCARD_CLEAR_CTIMEOUTC (1 << 2) /* Bit 2: CTIMEOUT flag clear bit */
|
||||
#define SDCARD_CLEAR_DTIMEOUTC (1 << 3) /* Bit 3: DTIMEOUT flag clear bit */
|
||||
#define SDCARD_CLEAR_TXUNDERRC (1 << 4) /* Bit 4: TXUNDERR flag clear bit */
|
||||
#define SDCARD_CLEAR_RXOVERRC (1 << 5) /* Bit 5: RXOVERR flag clear bit */
|
||||
#define SDCARD_CLEAR_CMDRENDC (1 << 6) /* Bit 6: CMDREND flag clear bit */
|
||||
#define SDCARD_CLEAR_CMDSENTC (1 << 7) /* Bit 7: CMDSENT flag clear bit */
|
||||
#define SDCARD_CLEAR_DATAENDC (1 << 8) /* Bit 8: DATAEND flag clear bit */
|
||||
#define SDCARD_CLEAR_STBITERRC (1 << 9) /* Bit 9: STBITERR flag clear bit */
|
||||
#define SDCARD_CLEAR_DBCKENDC (1 << 10) /* Bit 10: DBCKEND flag clear bit */
|
||||
/* Bits 11-31: Reserved */
|
||||
|
||||
#define SDCARD_CLEAR_RESET 0x000007ff
|
||||
#define SDCARD_CLEAR_STATICFLAGS 0x000005ff
|
||||
|
||||
/* MCI - Interrupt Mask Registers - MASK0 - 0x400c 003c */
|
||||
|
||||
#define SDCARD_MASK0_CCRCFAILIE (1 << 0) /* Bit 0: Command CRC fail interrupt enable */
|
||||
#define SDCARD_MASK0_DCRCFAILIE (1 << 1) /* Bit 1: Data CRC fail interrupt enable */
|
||||
#define SDCARD_MASK0_CTIMEOUTIE (1 << 2) /* Bit 2: Command timeout interrupt enable */
|
||||
#define SDCARD_MASK0_DTIMEOUTIE (1 << 3) /* Bit 3: Data timeout interrupt enable */
|
||||
#define SDCARD_MASK0_TXUNDERRIE (1 << 4) /* Bit 4: Tx FIFO underrun error interrupt enable */
|
||||
#define SDCARD_MASK0_RXOVERRIE (1 << 5) /* Bit 5: Rx FIFO overrun error interrupt enable */
|
||||
#define SDCARD_MASK0_CMDRENDIE (1 << 6) /* Bit 6: Command response received interrupt enable */
|
||||
#define SDCARD_MASK0_CMDSENTIE (1 << 7) /* Bit 7: Command sent interrupt enable */
|
||||
#define SDCARD_MASK0_DATAENDIE (1 << 8) /* Bit 8: Data end interrupt enable */
|
||||
#define SDCARD_MASK0_STBITERRIE (1 << 9) /* Bit 9: Start bit error interrupt enable */
|
||||
#define SDCARD_MASK0_DBCKENDIE (1 << 10) /* Bit 10: Data block end interrupt enable */
|
||||
#define SDCARD_MASK0_CMDACTIE (1 << 11) /* Bit 11: Command acting interrupt enable */
|
||||
#define SDCARD_MASK0_TXACTIE (1 << 12) /* Bit 12: Data transmit acting interrupt enable */
|
||||
#define SDCARD_MASK0_RXACTIE (1 << 13) /* Bit 13: Data receive acting interrupt enable */
|
||||
#define SDCARD_MASK0_TXFIFOHEIE (1 << 14) /* Bit 14: Tx FIFO half empty interrupt enable */
|
||||
#define SDCARD_MASK0_RXFIFOHFIE (1 << 15) /* Bit 15: Rx FIFO half full interrupt enable */
|
||||
#define SDCARD_MASK0_TXFIFOFIE (1 << 16) /* Bit 16: Tx FIFO full interrupt enable */
|
||||
#define SDCARD_MASK0_RXFIFOFIE (1 << 17) /* Bit 17: Rx FIFO full interrupt enable */
|
||||
#define SDCARD_MASK0_TXFIFOEIE (1 << 18) /* Bit 18: Tx FIFO empty interrupt enable */
|
||||
#define SDCARD_MASK0_RXFIFOEIE (1 << 19) /* Bit 19: Rx FIFO empty interrupt enable */
|
||||
#define SDCARD_MASK0_TXDAVLIE (1 << 20) /* Bit 20: Data available in Tx FIFO interrupt enable */
|
||||
#define SDCARD_MASK0_RXDAVLIE (1 << 21) /* Bit 21: Data available in Rx FIFO interrupt enable */
|
||||
/* Bits 22-31: Reserved */
|
||||
#define SDCARD_MASK0_RESET (0)
|
||||
|
||||
/* MCI - FIFO Counter Register (FIFOCNT - 0x400c 0048 */
|
||||
|
||||
#define SDCARD_FIFOCNT_SHIFT (0) /* Bits 0-14: Remaining data */
|
||||
#define SDCARD_FIFOCNT_MASK (0x7fff << SDCARD_FIFOCNT_SHIFT)
|
||||
/* Bits 15-31: Reserved */
|
||||
|
||||
/* MCI - Data FIFO Register - FIFO - 0x400c 0080 to 0x400c 00bc */
|
||||
/* The receive and transmit FIFOs can be read or written as 32 bit wide registers.
|
||||
* The FIFOs contain 16 entries on 16 sequential addresses.
|
||||
*/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_SDCARD_H */
|
||||
|
||||
@@ -1,141 +0,0 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/lpc17xx/hardware/lpc17_spi.h
|
||||
*
|
||||
* Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_SPI_H
|
||||
#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_SPI_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "hardware/lpc17_memorymap.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register offsets *****************************************************************/
|
||||
|
||||
#define LPC17_SPI_CR_OFFSET 0x0000 /* Control Register */
|
||||
#define LPC17_SPI_SR_OFFSET 0x0004 /* SPI Status Register */
|
||||
#define LPC17_SPI_DR_OFFSET 0x0008 /* SPI Data Register */
|
||||
#define LPC17_SPI_CCR_OFFSET 0x000c /* SPI Clock Counter Register */
|
||||
#define LPC17_SPI_TCR_OFFSET 0x0010 /* SPI Test Control Register */
|
||||
#define LPC17_SPI_TSR_OFFSET 0x0014 /* SPI Test Status Register */
|
||||
#define LPC17_SPI_INT_OFFSET 0x001c /* SPI Interrupt Register */
|
||||
|
||||
/* Register addresses ***************************************************************/
|
||||
|
||||
#define LPC17_SPI_CR (LPC17_SPI_BASE+LPC17_SPI_CR_OFFSET)
|
||||
#define LPC17_SPI_SR (LPC17_SPI_BASE+LPC17_SPI_SR_OFFSET)
|
||||
#define LPC17_SPI_DR (LPC17_SPI_BASE+LPC17_SPI_DR_OFFSET)
|
||||
#define LPC17_SPI_CCR (LPC17_SPI_BASE+LPC17_SPI_CCR_OFFSET)
|
||||
#define LPC17_TCR_CCR (LPC17_SPI_BASE+LPC17_SPI_TCR_OFFSET)
|
||||
#define LPC17_TSR_CCR (LPC17_SPI_BASE+LPC17_SPI_TSR_OFFSET)
|
||||
#define LPC17_SPI_INT (LPC17_SPI_BASE+LPC17_SPI_INT_OFFSET)
|
||||
|
||||
/* Register bit definitions *********************************************************/
|
||||
|
||||
/* Control Register */
|
||||
/* Bits 0-1: Reserved */
|
||||
#define SPI_CR_BITENABLE (1 << 2) /* Bit 2: Enable word size selected by BITS */
|
||||
#define SPI_CR_CPHA (1 << 3) /* Bit 3: Clock phase control */
|
||||
#define SPI_CR_CPOL (1 << 4) /* Bit 4: Clock polarity control */
|
||||
#define SPI_CR_MSTR (1 << 5) /* Bit 5: Master mode select */
|
||||
#define SPI_CR_LSBF (1 << 6) /* Bit 6: SPI data is transferred LSB first */
|
||||
#define SPI_CR_SPIE (1 << 7) /* Bit 7: Serial peripheral interrupt enable */
|
||||
#define SPI_CR_BITS_SHIFT (8) /* Bits 8-11: Number of bits per word (BITENABLE==1) */
|
||||
#define SPI_CR_BITS_MASK (15 << SPI_CR_BITS_SHIFT)
|
||||
# define SPI_CR_BITS_8BITS (8 << SPI_CR_BITS_SHIFT) /* 8 bits per transfer */
|
||||
# define SPI_CR_BITS_9BITS (9 << SPI_CR_BITS_SHIFT) /* 9 bits per transfer */
|
||||
# define SPI_CR_BITS_10BITS (10 << SPI_CR_BITS_SHIFT) /* 10 bits per transfer */
|
||||
# define SPI_CR_BITS_11BITS (11 << SPI_CR_BITS_SHIFT) /* 11 bits per transfer */
|
||||
# define SPI_CR_BITS_12BITS (12 << SPI_CR_BITS_SHIFT) /* 12 bits per transfer */
|
||||
# define SPI_CR_BITS_13BITS (13 << SPI_CR_BITS_SHIFT) /* 13 bits per transfer */
|
||||
# define SPI_CR_BITS_14BITS (14 << SPI_CR_BITS_SHIFT) /* 14 bits per transfer */
|
||||
# define SPI_CR_BITS_15BITS (15 << SPI_CR_BITS_SHIFT) /* 15 bits per transfer */
|
||||
# define SPI_CR_BITS_16BITS (0 << SPI_CR_BITS_SHIFT) /* 16 bits per transfer */
|
||||
/* Bits 12-31: Reserved */
|
||||
/* SPI Status Register */
|
||||
/* Bits 0-2: Reserved */
|
||||
#define SPI_SR_ABRT (1 << 3) /* Bit 3: Slave abort */
|
||||
#define SPI_SR_MODF (1 << 4) /* Bit 4: Mode fault */
|
||||
#define SPI_SR_ROVR (1 << 5) /* Bit 5: Read overrun */
|
||||
#define SPI_SR_WCOL (1 << 6) /* Bit 6: Write collision */
|
||||
#define SPI_SR_SPIF (1 << 7) /* Bit 7: SPI transfer complete */
|
||||
/* Bits 8-31: Reserved */
|
||||
/* SPI Data Register */
|
||||
|
||||
#define SPI_DR_MASK (0xff) /* Bits 0-15: SPI Bi-directional data port */
|
||||
#define SPI_DR_MASKWIDE (0xffff) /* Bits 0-15: If SPI_CR_BITENABLE != 0 */
|
||||
/* Bits 8-31: Reserved */
|
||||
/* SPI Clock Counter Register */
|
||||
|
||||
#define SPI_CCR_MASK (0xff) /* Bits 0-7: SPI Clock counter setting */
|
||||
/* Bits 8-31: Reserved */
|
||||
/* SPI Test Control Register */
|
||||
/* Bit 0: Reserved */
|
||||
#define SPI_TCR_TEST_SHIFT (1) /* Bits 1-7: SPI test mode */
|
||||
#define SPI_TCR_TEST_MASK (0x7f << SPI_TCR_TEST_SHIFT)
|
||||
/* Bits 8-31: Reserved */
|
||||
/* SPI Test Status Register */
|
||||
/* Bits 0-2: Reserved */
|
||||
#define SPI_TSR_ABRT (1 << 3) /* Bit 3: Slave abort */
|
||||
#define SPI_TSR_MODF (1 << 4) /* Bit 4: Mode fault */
|
||||
#define SPI_TSR_ROVR (1 << 5) /* Bit 5: Read overrun */
|
||||
#define SPI_TSR_WCOL (1 << 6) /* Bit 6: Write collision */
|
||||
#define SPI_TSR_SPIF (1 << 7) /* Bit 7: SPI transfer complete */
|
||||
/* Bits 8-31: Reserved */
|
||||
/* SPI Interrupt Register */
|
||||
|
||||
#define SPI_INT_SPIF (1 << 0) /* SPI interrupt */
|
||||
/* Bits 1-31: Reserved */
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_SPI_H */
|
||||
@@ -1,185 +0,0 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/lpc17xx/hardware/lpc17_ssp.h
|
||||
*
|
||||
* Copyright (C) 2010, 2012-2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_SSP_H
|
||||
#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_SSP_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "hardware/lpc17_memorymap.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
/* 8 frame FIFOs for both transmit and receive */
|
||||
|
||||
#define LPC17_SSP_FIFOSZ 8
|
||||
|
||||
/* Register offsets *****************************************************************/
|
||||
|
||||
#define LPC17_SSP_CR0_OFFSET 0x0000 /* Control Register 0 */
|
||||
#define LPC17_SSP_CR1_OFFSET 0x0004 /* Control Register 1 */
|
||||
#define LPC17_SSP_DR_OFFSET 0x0008 /* Data Register */
|
||||
#define LPC17_SSP_SR_OFFSET 0x000c /* Status Register */
|
||||
#define LPC17_SSP_CPSR_OFFSET 0x0010 /* Clock Prescale Register */
|
||||
#define LPC17_SSP_IMSC_OFFSET 0x0014 /* Interrupt Mask Set and Clear Register */
|
||||
#define LPC17_SSP_RIS_OFFSET 0x0018 /* Raw Interrupt Status Register */
|
||||
#define LPC17_SSP_MIS_OFFSET 0x001c /* Masked Interrupt Status Register */
|
||||
#define LPC17_SSP_ICR_OFFSET 0x0020 /* Interrupt Clear Register */
|
||||
#define LPC17_SSP_DMACR_OFFSET 0x0024 /* DMA Control Register */
|
||||
|
||||
/* Register addresses ***************************************************************/
|
||||
|
||||
#define LPC17_SSP0_CR0 (LPC17_SSP0_BASE+LPC17_SSP_CR0_OFFSET)
|
||||
#define LPC17_SSP0_CR1 (LPC17_SSP0_BASE+LPC17_SSP_CR1_OFFSET)
|
||||
#define LPC17_SSP0_DR (LPC17_SSP0_BASE+LPC17_SSP_DR_OFFSET)
|
||||
#define LPC17_SSP0_SR (LPC17_SSP0_BASE+LPC17_SSP_SR_OFFSET)
|
||||
#define LPC17_SSP0_CPSR (LPC17_SSP0_BASE+LPC17_SSP_CPSR_OFFSET)
|
||||
#define LPC17_SSP0_IMSC (LPC17_SSP0_BASE+LPC17_SSP_IMSC_OFFSET)
|
||||
#define LPC17_SSP0_RIS (LPC17_SSP0_BASE+LPC17_SSP_RIS_OFFSET)
|
||||
#define LPC17_SSP0_MIS (LPC17_SSP0_BASE+LPC17_SSP_MIS_OFFSET)
|
||||
#define LPC17_SSP0_ICR (LPC17_SSP0_BASE+LPC17_SSP_ICR_OFFSET)
|
||||
#define LPC17_SSP0_DMACR (LPC17_SSP0_BASE+LPC17_SSP_DMACR_OFFSET)
|
||||
|
||||
#define LPC17_SSP1_CR0 (LPC17_SSP1_BASE+LPC17_SSP_CR0_OFFSET)
|
||||
#define LPC17_SSP1_CR1 (LPC17_SSP1_BASE+LPC17_SSP_CR1_OFFSET)
|
||||
#define LPC17_SSP1_DR (LPC17_SSP1_BASE+LPC17_SSP_DR_OFFSET)
|
||||
#define LPC17_SSP1_SR (LPC17_SSP1_BASE+LPC17_SSP_SR_OFFSET)
|
||||
#define LPC17_SSP1_CPSR (LPC17_SSP1_BASE+LPC17_SSP_CPSR_OFFSET)
|
||||
#define LPC17_SSP1_IMSC (LPC17_SSP1_BASE+LPC17_SSP_IMSC_OFFSET)
|
||||
#define LPC17_SSP1_RIS (LPC17_SSP1_BASE+LPC17_SSP_RIS_OFFSET)
|
||||
#define LPC17_SSP1_MIS (LPC17_SSP1_BASE+LPC17_SSP_MIS_OFFSET)
|
||||
#define LPC17_SSP1_ICR (LPC17_SSP1_BASE+LPC17_SSP_ICR_OFFSET)
|
||||
#define LPC17_SSP1_DMACR (LPC17_SSP1_BASE+LPC17_SSP_DMACR_OFFSET)
|
||||
|
||||
#define LPC17_SSP2_CR0 (LPC17_SSP2_BASE+LPC17_SSP_CR0_OFFSET)
|
||||
#define LPC17_SSP2_CR1 (LPC17_SSP2_BASE+LPC17_SSP_CR1_OFFSET)
|
||||
#define LPC17_SSP2_DR (LPC17_SSP2_BASE+LPC17_SSP_DR_OFFSET)
|
||||
#define LPC17_SSP2_SR (LPC17_SSP2_BASE+LPC17_SSP_SR_OFFSET)
|
||||
#define LPC17_SSP2_CPSR (LPC17_SSP2_BASE+LPC17_SSP_CPSR_OFFSET)
|
||||
#define LPC17_SSP2_IMSC (LPC17_SSP2_BASE+LPC17_SSP_IMSC_OFFSET)
|
||||
#define LPC17_SSP2_RIS (LPC17_SSP2_BASE+LPC17_SSP_RIS_OFFSET)
|
||||
#define LPC17_SSP2_MIS (LPC17_SSP2_BASE+LPC17_SSP_MIS_OFFSET)
|
||||
#define LPC17_SSP2_ICR (LPC17_SSP2_BASE+LPC17_SSP_ICR_OFFSET)
|
||||
#define LPC17_SSP2_DMACR (LPC17_SSP2_BASE+LPC17_SSP_DMACR_OFFSET)
|
||||
|
||||
/* Register bit definitions *********************************************************/
|
||||
/* Control Register 0 */
|
||||
|
||||
#define SSP_CR0_DSS_SHIFT (0) /* Bits 0-3: DSS Data Size Select */
|
||||
#define SSP_CR0_DSS_MASK (15 << SSP_CR0_DSS_SHIFT)
|
||||
# define SSP_CR0_DSS_4BIT (3 << SSP_CR0_DSS_SHIFT)
|
||||
# define SSP_CR0_DSS_5BIT (4 << SSP_CR0_DSS_SHIFT)
|
||||
# define SSP_CR0_DSS_6BIT (5 << SSP_CR0_DSS_SHIFT)
|
||||
# define SSP_CR0_DSS_7BIT (6 << SSP_CR0_DSS_SHIFT)
|
||||
# define SSP_CR0_DSS_8BIT (7 << SSP_CR0_DSS_SHIFT)
|
||||
# define SSP_CR0_DSS_9BIT (8 << SSP_CR0_DSS_SHIFT)
|
||||
# define SSP_CR0_DSS_10BIT (9 << SSP_CR0_DSS_SHIFT)
|
||||
# define SSP_CR0_DSS_11BIT (10 << SSP_CR0_DSS_SHIFT)
|
||||
# define SSP_CR0_DSS_12BIT (11 << SSP_CR0_DSS_SHIFT)
|
||||
# define SSP_CR0_DSS_13BIT (12 << SSP_CR0_DSS_SHIFT)
|
||||
# define SSP_CR0_DSS_14BIT (13 << SSP_CR0_DSS_SHIFT)
|
||||
# define SSP_CR0_DSS_15BIT (14 << SSP_CR0_DSS_SHIFT)
|
||||
# define SSP_CR0_DSS_16BIT (15 << SSP_CR0_DSS_SHIFT)
|
||||
#define SSP_CR0_FRF_SHIFT (4) /* Bits 4-5: FRF Frame Format */
|
||||
#define SSP_CR0_FRF_MASK (3 << SSP_CR0_FRF_SHIFT)
|
||||
# define SSP_CR0_FRF_SPI (0 << SSP_CR0_FRF_SHIFT)
|
||||
# define SSP_CR0_FRF_TI (1 << SSP_CR0_FRF_SHIFT)
|
||||
# define SSP_CR0_FRF_UWIRE (2 << SSP_CR0_FRF_SHIFT)
|
||||
#define SSP_CR0_CPOL (1 << 6) /* Bit 6: Clock Out Polarity */
|
||||
#define SSP_CR0_CPHA (1 << 7) /* Bit 7: Clock Out Phase */
|
||||
#define SSP_CR0_SCR_SHIFT (8) /* Bits 8-15: Serial Clock Rate */
|
||||
#define SSP_CR0_SCR_MASK (0xff << SSP_CR0_SCR_SHIFT)
|
||||
/* Bits 8-31: Reserved */
|
||||
/* Control Register 1 */
|
||||
|
||||
#define SSP_CR1_LBM (1 << 0) /* Bit 0: Loop Back Mode */
|
||||
#define SSP_CR1_SSE (1 << 1) /* Bit 1: SSP Enable */
|
||||
#define SSP_CR1_MS (1 << 2) /* Bit 2: Master/Slave Mode */
|
||||
#define SSP_CR1_SOD (1 << 3) /* Bit 3: Slave Output Disable */
|
||||
/* Bits 4-31: Reserved */
|
||||
/* Data Register */
|
||||
|
||||
#define SSP_DR_MASK (0xffff) /* Bits 0-15: Data */
|
||||
/* Bits 16-31: Reserved */
|
||||
/* Status Register */
|
||||
|
||||
#define SSP_SR_TFE (1 << 0) /* Bit 0: Transmit FIFO Empty */
|
||||
#define SSP_SR_TNF (1 << 1) /* Bit 1: Transmit FIFO Not Full */
|
||||
#define SSP_SR_RNE (1 << 2) /* Bit 2: Receive FIFO Not Empty */
|
||||
#define SSP_SR_RFF (1 << 3) /* Bit 3: Receive FIFO Full */
|
||||
#define SSP_SR_BSY (1 << 4) /* Bit 4: Busy */
|
||||
/* Bits 5-31: Reserved */
|
||||
/* Clock Prescale Register */
|
||||
|
||||
#define SSP_CPSR_DVSR_MASK (0xff) /* Bits 0-7: clock = SSP_PCLK/DVSR */
|
||||
/* Bits 8-31: Reserved */
|
||||
/* Common format for interrupt control registers:
|
||||
*
|
||||
* Interrupt Mask Set and Clear Register (IMSC)
|
||||
* Raw Interrupt Status Register (RIS)
|
||||
* Masked Interrupt Status Register (MIS)
|
||||
* Interrupt Clear Register (ICR)
|
||||
*/
|
||||
|
||||
#define SSP_INT_ROR (1 << 0) /* Bit 0: RX FIFO overrun */
|
||||
#define SSP_INT_RT (1 << 1) /* Bit 1: RX FIFO timeout */
|
||||
#define SSP_INT_RX (1 << 2) /* Bit 2: RX FIFO at least half full (not ICR) */
|
||||
#define SSP_INT_TX (1 << 3 ) /* Bit 3: TX FIFO at least half empy (not ICR) */
|
||||
/* Bits 4-31: Reserved */
|
||||
/* DMA Control Register */
|
||||
|
||||
#define SSP_DMACR_RXDMAE (1 << 0) /* Bit 0: Receive DMA Enable */
|
||||
#define SSP_DMACR_TXDMAE (1 << 1) /* Bit 1: Transmit DMA Enable */
|
||||
/* Bits 2-31: Reserved */
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_SSP_H */
|
||||
@@ -1,250 +0,0 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/lpc17xx/hardware/lpc17_timer.h
|
||||
*
|
||||
* Copyright (C) 2010, 2012-2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_TIMER_H
|
||||
#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_TIMER_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "hardware/lpc17_memorymap.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register offsets *****************************************************************/
|
||||
|
||||
#define LPC17_TMR_IR_OFFSET 0x0000 /* Interrupt Register */
|
||||
#define LPC17_TMR_TCR_OFFSET 0x0004 /* Timer Control Register */
|
||||
#define LPC17_TMR_TC_OFFSET 0x0008 /* Timer Counter */
|
||||
#define LPC17_TMR_PR_OFFSET 0x000c /* Prescale Register */
|
||||
#define LPC17_TMR_PC_OFFSET 0x0010 /* Prescale Counter */
|
||||
#define LPC17_TMR_MCR_OFFSET 0x0014 /* Match Control Register */
|
||||
#define LPC17_TMR_MR0_OFFSET 0x0018 /* Match Register 0 */
|
||||
#define LPC17_TMR_MR1_OFFSET 0x001c /* Match Register 1 */
|
||||
#define LPC17_TMR_MR2_OFFSET 0x0020 /* Match Register 2 */
|
||||
#define LPC17_TMR_MR3_OFFSET 0x0024 /* Match Register 3 */
|
||||
#define LPC17_TMR_CCR_OFFSET 0x0028 /* Capture Control Register */
|
||||
#define LPC17_TMR_CR0_OFFSET 0x002c /* Capture Register 0 */
|
||||
#define LPC17_TMR_CR1_OFFSET 0x0030 /* Capture Register 1 */
|
||||
#define LPC17_TMR_EMR_OFFSET 0x003c /* External Match Register */
|
||||
#define LPC17_TMR_CTCR_OFFSET 0x0070 /* Count Control Register */
|
||||
|
||||
/* Register addresses ***************************************************************/
|
||||
|
||||
#define LPC17_TMR0_IR (LPC17_TMR0_BASE+LPC17_TMR_IR_OFFSET)
|
||||
#define LPC17_TMR0_TCR (LPC17_TMR0_BASE+LPC17_TMR_TCR_OFFSET)
|
||||
#define LPC17_TMR0_TC (LPC17_TMR0_BASE+LPC17_TMR_TC_OFFSET)
|
||||
#define LPC17_TMR0_PR (LPC17_TMR0_BASE+LPC17_TMR_PR_OFFSET)
|
||||
#define LPC17_TMR0_PC (LPC17_TMR0_BASE+LPC17_TMR_PC_OFFSET)
|
||||
#define LPC17_TMR0_MCR (LPC17_TMR0_BASE+LPC17_TMR_MCR_OFFSET)
|
||||
#define LPC17_TMR0_MR0 (LPC17_TMR0_BASE+LPC17_TMR_MR0_OFFSET)
|
||||
#define LPC17_TMR0_MR1 (LPC17_TMR0_BASE+LPC17_TMR_MR1_OFFSET)
|
||||
#define LPC17_TMR0_MR2 (LPC17_TMR0_BASE+LPC17_TMR_MR2_OFFSET)
|
||||
#define LPC17_TMR0_MR3 (LPC17_TMR0_BASE+LPC17_TMR_MR3_OFFSET)
|
||||
#define LPC17_TMR0_CCR (LPC17_TMR0_BASE+LPC17_TMR_CCR_OFFSET)
|
||||
#define LPC17_TMR0_CR0 (LPC17_TMR0_BASE+LPC17_TMR_CR0_OFFSET)
|
||||
#define LPC17_TMR0_CR1 (LPC17_TMR0_BASE+LPC17_TMR_CR1_OFFSET)
|
||||
#define LPC17_TMR0_EMR (LPC17_TMR0_BASE+LPC17_TMR_EMR_OFFSET)
|
||||
#define LPC17_TMR0_CTCR (LPC17_TMR0_BASE+LPC17_TMR_CTCR_OFFSET)
|
||||
|
||||
#define LPC17_TMR1_IR (LPC17_TMR1_BASE+LPC17_TMR_IR_OFFSET)
|
||||
#define LPC17_TMR1_TCR (LPC17_TMR1_BASE+LPC17_TMR_TCR_OFFSET)
|
||||
#define LPC17_TMR1_TC (LPC17_TMR1_BASE+LPC17_TMR_TC_OFFSET)
|
||||
#define LPC17_TMR1_PR (LPC17_TMR1_BASE+LPC17_TMR_PR_OFFSET)
|
||||
#define LPC17_TMR1_PC (LPC17_TMR1_BASE+LPC17_TMR_PC_OFFSET)
|
||||
#define LPC17_TMR1_MCR (LPC17_TMR1_BASE+LPC17_TMR_MCR_OFFSET)
|
||||
#define LPC17_TMR1_MR0 (LPC17_TMR1_BASE+LPC17_TMR_MR0_OFFSET)
|
||||
#define LPC17_TMR1_MR1 (LPC17_TMR1_BASE+LPC17_TMR_MR1_OFFSET)
|
||||
#define LPC17_TMR1_MR2 (LPC17_TMR1_BASE+LPC17_TMR_MR2_OFFSET)
|
||||
#define LPC17_TMR1_MR3 (LPC17_TMR1_BASE+LPC17_TMR_MR3_OFFSET)
|
||||
#define LPC17_TMR1_CCR (LPC17_TMR1_BASE+LPC17_TMR_CCR_OFFSET)
|
||||
#define LPC17_TMR1_CR0 (LPC17_TMR1_BASE+LPC17_TMR_CR0_OFFSET)
|
||||
#define LPC17_TMR1_CR1 (LPC17_TMR1_BASE+LPC17_TMR_CR1_OFFSET)
|
||||
#define LPC17_TMR1_EMR (LPC17_TMR1_BASE+LPC17_TMR_EMR_OFFSET)
|
||||
#define LPC17_TMR1_CTCR (LPC17_TMR1_BASE+LPC17_TMR_CTCR_OFFSET)
|
||||
|
||||
#define LPC17_TMR2_IR (LPC17_TMR2_BASE+LPC17_TMR_IR_OFFSET)
|
||||
#define LPC17_TMR2_TCR (LPC17_TMR2_BASE+LPC17_TMR_TCR_OFFSET)
|
||||
#define LPC17_TMR2_TC (LPC17_TMR2_BASE+LPC17_TMR_TC_OFFSET)
|
||||
#define LPC17_TMR2_PR (LPC17_TMR2_BASE+LPC17_TMR_PR_OFFSET)
|
||||
#define LPC17_TMR2_PC (LPC17_TMR2_BASE+LPC17_TMR_PC_OFFSET)
|
||||
#define LPC17_TMR2_MCR (LPC17_TMR2_BASE+LPC17_TMR_MCR_OFFSET)
|
||||
#define LPC17_TMR2_MR0 (LPC17_TMR2_BASE+LPC17_TMR_MR0_OFFSET)
|
||||
#define LPC17_TMR2_MR1 (LPC17_TMR2_BASE+LPC17_TMR_MR1_OFFSET)
|
||||
#define LPC17_TMR2_MR2 (LPC17_TMR2_BASE+LPC17_TMR_MR2_OFFSET)
|
||||
#define LPC17_TMR2_MR3 (LPC17_TMR2_BASE+LPC17_TMR_MR3_OFFSET)
|
||||
#define LPC17_TMR2_CCR (LPC17_TMR2_BASE+LPC17_TMR_CCR_OFFSET)
|
||||
#define LPC17_TMR2_CR0 (LPC17_TMR2_BASE+LPC17_TMR_CR0_OFFSET)
|
||||
#define LPC17_TMR2_CR1 (LPC17_TMR2_BASE+LPC17_TMR_CR1_OFFSET)
|
||||
#define LPC17_TMR2_EMR (LPC17_TMR2_BASE+LPC17_TMR_EMR_OFFSET)
|
||||
#define LPC17_TMR2_CTCR (LPC17_TMR2_BASE+LPC17_TMR_CTCR_OFFSET)
|
||||
|
||||
#define LPC17_TMR3_IR (LPC17_TMR3_BASE+LPC17_TMR_IR_OFFSET)
|
||||
#define LPC17_TMR3_TCR (LPC17_TMR3_BASE+LPC17_TMR_TCR_OFFSET)
|
||||
#define LPC17_TMR3_TC (LPC17_TMR3_BASE+LPC17_TMR_TC_OFFSET)
|
||||
#define LPC17_TMR3_PR (LPC17_TMR3_BASE+LPC17_TMR_PR_OFFSET)
|
||||
#define LPC17_TMR3_PC (LPC17_TMR3_BASE+LPC17_TMR_PC_OFFSET)
|
||||
#define LPC17_TMR3_MCR (LPC17_TMR3_BASE+LPC17_TMR_MCR_OFFSET)
|
||||
#define LPC17_TMR3_MR0 (LPC17_TMR3_BASE+LPC17_TMR_MR0_OFFSET)
|
||||
#define LPC17_TMR3_MR1 (LPC17_TMR3_BASE+LPC17_TMR_MR1_OFFSET)
|
||||
#define LPC17_TMR3_MR2 (LPC17_TMR3_BASE+LPC17_TMR_MR2_OFFSET)
|
||||
#define LPC17_TMR3_MR3 (LPC17_TMR3_BASE+LPC17_TMR_MR3_OFFSET)
|
||||
#define LPC17_TMR3_CCR (LPC17_TMR3_BASE+LPC17_TMR_CCR_OFFSET)
|
||||
#define LPC17_TMR3_CR0 (LPC17_TMR3_BASE+LPC17_TMR_CR0_OFFSET)
|
||||
#define LPC17_TMR3_CR1 (LPC17_TMR3_BASE+LPC17_TMR_CR1_OFFSET)
|
||||
#define LPC17_TMR3_EMR (LPC17_TMR3_BASE+LPC17_TMR_EMR_OFFSET)
|
||||
#define LPC17_TMR3_CTCR (LPC17_TMR3_BASE+LPC17_TMR_CTCR_OFFSET)
|
||||
|
||||
/* Register bit definitions *********************************************************/
|
||||
/* Registers holding 32-bit numeric values (no bit field definitions):
|
||||
*
|
||||
* Timer Counter (TC)
|
||||
* Prescale Register (PR)
|
||||
* Prescale Counter (PC)
|
||||
* Match Register 0 (MR0)
|
||||
* Match Register 1 (MR1)
|
||||
* Match Register 2 (MR2)
|
||||
* Match Register 3 (MR3)
|
||||
* Capture Register 0 (CR0)
|
||||
* Capture Register 1 (CR1)
|
||||
*/
|
||||
|
||||
/* Interrupt Register */
|
||||
|
||||
#define TMR_IR_MR0 (1 << 0) /* Bit 0: Match channel 0 interrupt */
|
||||
#define TMR_IR_MR1 (1 << 1) /* Bit 1: Match channel 1 interrupt */
|
||||
#define TMR_IR_MR2 (1 << 2) /* Bit 2: Match channel 2 interrupt */
|
||||
#define TMR_IR_MR3 (1 << 3) /* Bit 3: Match channel 3 interrupt */
|
||||
#define TMR_IR_CR0 (1 << 4) /* Bit 4: Capture channel 0 interrupt */
|
||||
#define TMR_IR_CR1 (1 << 5) /* Bit 5: Capture channel 1 interrupt */
|
||||
/* Bits 6-31: Reserved */
|
||||
/* Timer Control Register */
|
||||
|
||||
#define TMR_TCR_EN (1 << 0) /* Bit 0: Counter Enable */
|
||||
#define TMR_TCR_RESET (1 << 1) /* Bit 1: Counter Reset */
|
||||
/* Bits 2-31: Reserved */
|
||||
/* Match Control Register */
|
||||
|
||||
#define TMR_MCR_MR0I (1 << 0) /* Bit 0: Interrupt on MR0 */
|
||||
#define TMR_MCR_MR0R (1 << 1) /* Bit 1: Reset on MR0 */
|
||||
#define TMR_MCR_MR0S (1 << 2) /* Bit 2: Stop on MR0 */
|
||||
#define TMR_MCR_MR1I (1 << 3) /* Bit 3: Interrupt on MR1 */
|
||||
#define TMR_MCR_MR1R (1 << 4) /* Bit 4: Reset on MR1 */
|
||||
#define TMR_MCR_MR1S (1 << 5) /* Bit 5: Stop on MR1 */
|
||||
#define TMR_MCR_MR2I (1 << 6) /* Bit 6: Interrupt on MR2 */
|
||||
#define TMR_MCR_MR2R (1 << 7) /* Bit 7: Reset on MR2 */
|
||||
#define TMR_MCR_MR2S (1 << 8) /* Bit 8: Stop on MR2 */
|
||||
#define TMR_MCR_MR3I (1 << 9) /* Bit 9: Interrupt on MR3 */
|
||||
#define TMR_MCR_MR3R (1 << 10) /* Bit 10: Reset on MR3 */
|
||||
#define TMR_MCR_MR3S (1 << 11) /* Bit 11: Stop on MR3 */
|
||||
/* Bits 12-31: Reserved */
|
||||
/* Capture Control Register */
|
||||
|
||||
#define TMR_CCR_CAP0RE (1 << 0) /* Bit 0: Capture on CAPn.0 rising edge */
|
||||
#define TMR_CCR_CAP0FE (1 << 1) /* Bit 1: Capture on CAPn.0 falling edge */
|
||||
#define TMR_CCR_CAP0I (1 << 2) /* Bit 2: Interrupt on CAPn.0 */
|
||||
#define TMR_CCR_CAP1RE (1 << 3) /* Bit 3: Capture on CAPn.1 rising edge */
|
||||
#define TMR_CCR_CAP1FE (1 << 4) /* Bit 4: Capture on CAPn.1 falling edge */
|
||||
#define TMR_CCR_CAP1I (1 << 5) /* Bit 5: Interrupt on CAPn.1 */
|
||||
/* Bits 6-31: Reserved */
|
||||
/* External Match Register */
|
||||
|
||||
#define TMR_EMR_NOTHING (0) /* Do Nothing */
|
||||
#define TMR_EMR_CLEAR (1) /* Clear external match bit MATn.m */
|
||||
#define TMR_EMR_SET (2) /* Set external match bit MATn.m */
|
||||
#define TMR_EMR_TOGGLE (3) /* Toggle external match bit MATn.m */
|
||||
|
||||
#define TMR_EMR_EM0 (1 << 0) /* Bit 0: External Match 0 */
|
||||
#define TMR_EMR_EM1 (1 << 1) /* Bit 1: External Match 1 */
|
||||
#define TMR_EMR_EM2 (1 << 2) /* Bit 2: External Match 2 */
|
||||
#define TMR_EMR_EM3 (1 << 3) /* Bit 3: External Match 3 */
|
||||
#define TMR_EMR_EMC0_SHIFT (4) /* Bits 4-5: External Match Control 0 */
|
||||
#define TMR_EMR_EMC0_MASK (3 << TMR_EMR_EMC0_SHIFTy)
|
||||
# define TMR_EMR_EMC0_NOTHING (TMR_EMR_NOTHING << TMR_EMR_EMC0_SHIFT)
|
||||
# define TMR_EMR_EMC0_CLEAR (TMR_EMR_CLEAR << TMR_EMR_EMC0_SHIFT)
|
||||
# define TMR_EMR_EMC0_SET (TMR_EMR_SET << TMR_EMR_EMC0_SHIFT)
|
||||
# define TMR_EMR_EMC0_TOGGLE (TMR_EMR_TOGGLE << TMR_EMR_EMC0_SHIFT)
|
||||
#define TMR_EMR_EMC1_SHIFT (6) /* Bits 6-7: External Match Control 1 */
|
||||
#define TMR_EMR_EMC1_MASK (3 << TMR_EMR_EMC1_SHIFT)
|
||||
# define TMR_EMR_EMC1_NOTHING (TMR_EMR_NOTHING << TMR_EMR_EMC1_SHIFT)
|
||||
# define TMR_EMR_EMC1_CLEAR (TMR_EMR_CLEAR << TMR_EMR_EMC1_SHIFT)
|
||||
# define TMR_EMR_EMC1_SET (TMR_EMR_SET << TMR_EMR_EMC1_SHIFT)
|
||||
# define TMR_EMR_EMC1_TOGGLE (TMR_EMR_TOGGLE << TMR_EMR_EMC1_SHIFT)
|
||||
#define TMR_EMR_EMC2_SHIFT (8) /* Bits 8-9: External Match Control 2 */
|
||||
#define TMR_EMR_EMC2_MASK (3 << TMR_EMR_EMC2_SHIFT)
|
||||
# define TMR_EMR_EMC2_NOTHING (TMR_EMR_NOTHING << TMR_EMR_EMC2_SHIFT)
|
||||
# define TMR_EMR_EMC2_CLEAR (TMR_EMR_CLEAR << TMR_EMR_EMC2_SHIFT)
|
||||
# define TMR_EMR_EMC2_SET (TMR_EMR_SET << TMR_EMR_EMC2_SHIFT)
|
||||
# define TMR_EMR_EMC2_TOGGLE (TMR_EMR_TOGGLE << TMR_EMR_EMC2_SHIFT)
|
||||
#define TMR_EMR_EMC3_SHIFT (10) /* Bits 10-11: External Match Control 3 */
|
||||
#define TMR_EMR_EMC3_MASK (3 << TMR_EMR_EMC3_SHIFT)
|
||||
# define TMR_EMR_EMC3_NOTHING (TMR_EMR_NOTHING << TMR_EMR_EMC3_SHIFT)
|
||||
# define TMR_EMR_EMC3_CLEAR (TMR_EMR_CLEAR << TMR_EMR_EMC3_SHIFT)
|
||||
# define TMR_EMR_EMC3_SET (TMR_EMR_SET << TMR_EMR_EMC3_SHIFT)
|
||||
# define TMR_EMR_EMC3_TOGGLE (TMR_EMR_TOGGLE << TMR_EMR_EMC3_SHIFT)
|
||||
/* Bits 12-31: Reserved */
|
||||
/* Count Control Register */
|
||||
|
||||
#define TMR_CTCR_MODE_SHIFT (0) /* Bits 0-1: Counter/Timer Mode */
|
||||
#define TMR_CTCR_MODE_MASK (3 << TMR_CTCR_MODE_SHIFT)
|
||||
# define TMR_CTCR_MODE_TIMER (0 << TMR_CTCR_MODE_SHIFT) /* Timer Mode, prescale match */
|
||||
# define TMR_CTCR_MODE_CNTRRE (1 << TMR_CTCR_MODE_SHIFT) /* Counter Mode, CAP rising edge */
|
||||
# define TMR_CTCR_MODE_CNTRFE (2 << TMR_CTCR_MODE_SHIFT) /* Counter Mode, CAP falling edge */
|
||||
# define TMR_CTCR_MODE_CNTRBE (3 << TMR_CTCR_MODE_SHIFT) /* Counter Mode, CAP both edges */
|
||||
#define TMR_CTCR_INPSEL_SHIFT (2) /* Bits 2-3: Count Input Select */
|
||||
#define TMR_CTCR_INPSEL_MASK (3 << TMR_CTCR_INPSEL_SHIFT)
|
||||
# define TMR_CTCR_INPSEL_CAPNp0 (0 << TMR_CTCR_INPSEL_SHIFT) /* CAPn.0 for TIMERn */
|
||||
# define TMR_CTCR_INPSEL_CAPNp1 (1 << TMR_CTCR_INPSEL_SHIFT) /* CAPn.1 for TIMERn */
|
||||
/* Bits 4-31: Reserved */
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_TIMER_H */
|
||||
@@ -1,414 +0,0 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/lpc17xx/hardware/lpc17_uart.h
|
||||
*
|
||||
* Copyright (C) 2010, 2012-2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_UART_H
|
||||
#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_UART_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "hardware/lpc17_memorymap.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register offsets *****************************************************************/
|
||||
|
||||
#define LPC17_UART_RBR_OFFSET 0x0000 /* (DLAB =0) Receiver Buffer Register (all) */
|
||||
#define LPC17_UART_THR_OFFSET 0x0000 /* (DLAB =0) Transmit Holding Register (all) */
|
||||
#define LPC17_UART_DLL_OFFSET 0x0000 /* (DLAB =1) Divisor Latch LSB (all) */
|
||||
#define LPC17_UART_DLM_OFFSET 0x0004 /* (DLAB =1) Divisor Latch MSB (all) */
|
||||
#define LPC17_UART_IER_OFFSET 0x0004 /* (DLAB =0) Interrupt Enable Register (all) */
|
||||
#define LPC17_UART_IIR_OFFSET 0x0008 /* Interrupt ID Register (all) */
|
||||
#define LPC17_UART_FCR_OFFSET 0x0008 /* FIFO Control Register (all) */
|
||||
#define LPC17_UART_LCR_OFFSET 0x000c /* Line Control Register (all) */
|
||||
#define LPC17_UART_MCR_OFFSET 0x0010 /* Modem Control Register (UART1 only) */
|
||||
#define LPC17_UART_LSR_OFFSET 0x0014 /* Line Status Register (all) */
|
||||
#define LPC17_UART_MSR_OFFSET 0x0018 /* Modem Status Register (UART1 only) */
|
||||
#define LPC17_UART_SCR_OFFSET 0x001c /* Scratch Pad Register (all) */
|
||||
#define LPC17_UART_ACR_OFFSET 0x0020 /* Auto-baud Control Register (all) */
|
||||
#define LPC17_UART_ICR_OFFSET 0x0024 /* IrDA Control Register (UART0,2,3 only) */
|
||||
#define LPC17_UART_FDR_OFFSET 0x0028 /* Fractional Divider Register (all) */
|
||||
#define LPC17_UART_TER_OFFSET 0x0030 /* Transmit Enable Register (all) */
|
||||
#define LPC17_UART_RS485CTRL_OFFSET 0x004c /* RS-485/EIA-485 Control (UART1 only) */
|
||||
#define LPC17_UART_ADRMATCH_OFFSET 0x0050 /* RS-485/EIA-485 address match (UART1 only) */
|
||||
#define LPC17_UART_RS485DLY_OFFSET 0x0054 /* RS-485/EIA-485 direction control delay (UART1 only) */
|
||||
#define LPC17_UART_FIFOLVL_OFFSET 0x0058 /* FIFO Level register (all) */
|
||||
|
||||
#ifdef LPC178x
|
||||
# define LPC17_UART_OSR_OFFSET 0x002c /* Oversampling Register (UART4 only) */
|
||||
# define LPC17_UART_SCICTRL_OFFSET 0x0048 /* Smart Card Interface Register (UART4 only) */
|
||||
# define LPC17_UART_SYNCCTRL_OFFSET 0x0058 /* Synchronous Mode Register (UART4 only) */
|
||||
#endif
|
||||
|
||||
/* Register addresses ***************************************************************/
|
||||
|
||||
#define LPC17_UART0_RBR (LPC17_UART0_BASE+LPC17_UART_RBR_OFFSET)
|
||||
#define LPC17_UART0_THR (LPC17_UART0_BASE+LPC17_UART_THR_OFFSET)
|
||||
#define LPC17_UART0_DLL (LPC17_UART0_BASE+LPC17_UART_DLL_OFFSET)
|
||||
#define LPC17_UART0_DLM (LPC17_UART0_BASE+LPC17_UART_DLM_OFFSET)
|
||||
#define LPC17_UART0_IER (LPC17_UART0_BASE+LPC17_UART_IER_OFFSET)
|
||||
#define LPC17_UART0_IIR (LPC17_UART0_BASE+LPC17_UART_IIR_OFFSET)
|
||||
#define LPC17_UART0_FCR (LPC17_UART0_BASE+LPC17_UART_FCR_OFFSET)
|
||||
#define LPC17_UART0_LCR (LPC17_UART0_BASE+LPC17_UART_LCR_OFFSET)
|
||||
#define LPC17_UART0_LSR (LPC17_UART0_BASE+LPC17_UART_LSR_OFFSET)
|
||||
#define LPC17_UART0_SCR (LPC17_UART0_BASE+LPC17_UART_SCR_OFFSET)
|
||||
#define LPC17_UART0_ACR (LPC17_UART0_BASE+LPC17_UART_ACR_OFFSET)
|
||||
#define LPC17_UART0_ICR (LPC17_UART0_BASE+LPC17_UART_ICR_OFFSET)
|
||||
#define LPC17_UART0_FDR (LPC17_UART0_BASE+LPC17_UART_FDR_OFFSET)
|
||||
#define LPC17_UART0_TER (LPC17_UART0_BASE+LPC17_UART_TER_OFFSET)
|
||||
|
||||
#ifdef LPC178x
|
||||
# define LPC17_UART0_RS485CTRL (LPC17_UART0_BASE+LPC17_UART_RS485CTRL_OFFSET)
|
||||
# define LPC17_UART0_ADRMATCH (LPC17_UART0_BASE+LPC17_UART_ADRMATCH_OFFSET)
|
||||
# define LPC17_UART0_RS485DLY (LPC17_UART0_BASE+LPC17_UART_RS485DLY_OFFSET)
|
||||
#endif
|
||||
|
||||
#define LPC17_UART0_FIFOLVL (LPC17_UART0_BASE+LPC17_UART_FIFOLVL_OFFSET)
|
||||
|
||||
#define LPC17_UART1_RBR (LPC17_UART1_BASE+LPC17_UART_RBR_OFFSET)
|
||||
#define LPC17_UART1_THR (LPC17_UART1_BASE+LPC17_UART_THR_OFFSET)
|
||||
#define LPC17_UART1_DLL (LPC17_UART1_BASE+LPC17_UART_DLL_OFFSET)
|
||||
#define LPC17_UART1_DLM (LPC17_UART1_BASE+LPC17_UART_DLM_OFFSET)
|
||||
#define LPC17_UART1_IER (LPC17_UART1_BASE+LPC17_UART_IER_OFFSET)
|
||||
#define LPC17_UART1_IIR (LPC17_UART1_BASE+LPC17_UART_IIR_OFFSET)
|
||||
#define LPC17_UART1_FCR (LPC17_UART1_BASE+LPC17_UART_FCR_OFFSET)
|
||||
#define LPC17_UART1_LCR (LPC17_UART1_BASE+LPC17_UART_LCR_OFFSET)
|
||||
#define LPC17_UART1_MCR (LPC17_UART1_BASE+LPC17_UART_MCR_OFFSET)
|
||||
#define LPC17_UART1_LSR (LPC17_UART1_BASE+LPC17_UART_LSR_OFFSET)
|
||||
#define LPC17_UART1_MSR (LPC17_UART1_BASE+LPC17_UART_MSR_OFFSET)
|
||||
#define LPC17_UART1_SCR (LPC17_UART1_BASE+LPC17_UART_SCR_OFFSET)
|
||||
#define LPC17_UART1_ACR (LPC17_UART1_BASE+LPC17_UART_ACR_OFFSET)
|
||||
#define LPC17_UART1_FDR (LPC17_UART1_BASE+LPC17_UART_FDR_OFFSET)
|
||||
#define LPC17_UART1_TER (LPC17_UART1_BASE+LPC17_UART_TER_OFFSET)
|
||||
#define LPC17_UART1_RS485CTRL (LPC17_UART1_BASE+LPC17_UART_RS485CTRL_OFFSET)
|
||||
#define LPC17_UART1_ADRMATCH (LPC17_UART1_BASE+LPC17_UART_ADRMATCH_OFFSET)
|
||||
#define LPC17_UART1_RS485DLY (LPC17_UART1_BASE+LPC17_UART_RS485DLY_OFFSET)
|
||||
#define LPC17_UART1_FIFOLVL (LPC17_UART1_BASE+LPC17_UART_FIFOLVL_OFFSET)
|
||||
|
||||
#define LPC17_UART2_RBR (LPC17_UART2_BASE+LPC17_UART_RBR_OFFSET)
|
||||
#define LPC17_UART2_THR (LPC17_UART2_BASE+LPC17_UART_THR_OFFSET)
|
||||
#define LPC17_UART2_DLL (LPC17_UART2_BASE+LPC17_UART_DLL_OFFSET)
|
||||
#define LPC17_UART2_DLM (LPC17_UART2_BASE+LPC17_UART_DLM_OFFSET)
|
||||
#define LPC17_UART2_IER (LPC17_UART2_BASE+LPC17_UART_IER_OFFSET)
|
||||
#define LPC17_UART2_IIR (LPC17_UART2_BASE+LPC17_UART_IIR_OFFSET)
|
||||
#define LPC17_UART2_FCR (LPC17_UART2_BASE+LPC17_UART_FCR_OFFSET)
|
||||
#define LPC17_UART2_LCR (LPC17_UART2_BASE+LPC17_UART_LCR_OFFSET)
|
||||
#define LPC17_UART2_LSR (LPC17_UART2_BASE+LPC17_UART_LSR_OFFSET)
|
||||
#define LPC17_UART2_SCR (LPC17_UART2_BASE+LPC17_UART_SCR_OFFSET)
|
||||
#define LPC17_UART2_ACR (LPC17_UART2_BASE+LPC17_UART_ACR_OFFSET)
|
||||
#define LPC17_UART2_ICR (LPC17_UART2_BASE+LPC17_UART_ICR_OFFSET)
|
||||
#define LPC17_UART2_FDR (LPC17_UART2_BASE+LPC17_UART_FDR_OFFSET)
|
||||
#define LPC17_UART2_TER (LPC17_UART2_BASE+LPC17_UART_TER_OFFSET)
|
||||
|
||||
#ifdef LPC178x
|
||||
# define LPC17_UART2_RS485CTRL (LPC17_UART2_BASE+LPC17_UART_RS485CTRL_OFFSET)
|
||||
# define LPC17_UART2_ADRMATCH (LPC17_UART2_BASE+LPC17_UART_ADRMATCH_OFFSET)
|
||||
# define LPC17_UART2_RS485DLY (LPC17_UART2_BASE+LPC17_UART_RS485DLY_OFFSET)
|
||||
#endif
|
||||
|
||||
#define LPC17_UART2_FIFOLVL (LPC17_UART2_BASE+LPC17_UART_FIFOLVL_OFFSET)
|
||||
|
||||
#define LPC17_UART3_RBR (LPC17_UART3_BASE+LPC17_UART_RBR_OFFSET)
|
||||
#define LPC17_UART3_THR (LPC17_UART3_BASE+LPC17_UART_THR_OFFSET)
|
||||
#define LPC17_UART3_DLL (LPC17_UART3_BASE+LPC17_UART_DLL_OFFSET)
|
||||
#define LPC17_UART3_DLM (LPC17_UART3_BASE+LPC17_UART_DLM_OFFSET)
|
||||
#define LPC17_UART3_IER (LPC17_UART3_BASE+LPC17_UART_IER_OFFSET)
|
||||
#define LPC17_UART3_IIR (LPC17_UART3_BASE+LPC17_UART_IIR_OFFSET)
|
||||
#define LPC17_UART3_FCR (LPC17_UART3_BASE+LPC17_UART_FCR_OFFSET)
|
||||
#define LPC17_UART3_LCR (LPC17_UART3_BASE+LPC17_UART_LCR_OFFSET)
|
||||
#define LPC17_UART3_LSR (LPC17_UART3_BASE+LPC17_UART_LSR_OFFSET)
|
||||
#define LPC17_UART3_SCR (LPC17_UART3_BASE+LPC17_UART_SCR_OFFSET)
|
||||
#define LPC17_UART3_ACR (LPC17_UART3_BASE+LPC17_UART_ACR_OFFSET)
|
||||
#define LPC17_UART3_ICR (LPC17_UART3_BASE+LPC17_UART_ICR_OFFSET)
|
||||
#define LPC17_UART3_FDR (LPC17_UART3_BASE+LPC17_UART_FDR_OFFSET)
|
||||
#define LPC17_UART3_TER (LPC17_UART3_BASE+LPC17_UART_TER_OFFSET)
|
||||
|
||||
#ifdef LPC178x
|
||||
# define LPC17_UART3_RS485CTRL (LPC17_UART3_BASE+LPC17_UART_RS485CTRL_OFFSET)
|
||||
# define LPC17_UART3_ADRMATCH (LPC17_UART3_BASE+LPC17_UART_ADRMATCH_OFFSET)
|
||||
# define LPC17_UART3_RS485DLY (LPC17_UART3_BASE+LPC17_UART_RS485DLY_OFFSET)
|
||||
#endif
|
||||
|
||||
#define LPC17_UART3_FIFOLVL (LPC17_UART3_BASE+LPC17_UART_FIFOLVL_OFFSET)
|
||||
|
||||
#ifdef LPC178x
|
||||
# define LPC17_UART4_RBR (LPC17_UART4_BASE+LPC17_UART_RBR_OFFSET)
|
||||
# define LPC17_UART4_THR (LPC17_UART4_BASE+LPC17_UART_THR_OFFSET)
|
||||
# define LPC17_UART4_DLL (LPC17_UART4_BASE+LPC17_UART_DLL_OFFSET)
|
||||
# define LPC17_UART4_DLM (LPC17_UART4_BASE+LPC17_UART_DLM_OFFSET)
|
||||
# define LPC17_UART4_IER (LPC17_UART4_BASE+LPC17_UART_IER_OFFSET)
|
||||
# define LPC17_UART4_IIR (LPC17_UART4_BASE+LPC17_UART_IIR_OFFSET)
|
||||
# define LPC17_UART4_FCR (LPC17_UART4_BASE+LPC17_UART_FCR_OFFSET)
|
||||
# define LPC17_UART4_LCR (LPC17_UART4_BASE+LPC17_UART_LCR_OFFSET)
|
||||
# define LPC17_UART4_LSR (LPC17_UART4_BASE+LPC17_UART_LSR_OFFSET)
|
||||
# define LPC17_UART4_SCR (LPC17_UART4_BASE+LPC17_UART_SCR_OFFSET)
|
||||
# define LPC17_UART4_ACR (LPC17_UART4_BASE+LPC17_UART_ACR_OFFSET)
|
||||
# define LPC17_UART4_ICR (LPC17_UART4_BASE+LPC17_UART_ICR_OFFSET)
|
||||
# define LPC17_UART4_FDR (LPC17_UART4_BASE+LPC17_UART_FDR_OFFSET)
|
||||
# define LPC17_UART4_TER (LPC17_UART4_BASE+LPC17_UART_TER_OFFSET)
|
||||
# define LPC17_UART4_RS485CTRL (LPC17_UART4_BASE+LPC17_UART_RS485CTRL_OFFSET)
|
||||
# define LPC17_UART4_ADRMATCH (LPC17_UART4_BASE+LPC17_UART_ADRMATCH_OFFSET)
|
||||
# define LPC17_UART4_RS485DLY (LPC17_UART4_BASE+LPC17_UART_RS485DLY_OFFSET)
|
||||
# define LPC17_UART4_FIFOLVL (LPC17_UART4_BASE+LPC17_UART_FIFOLVL_OFFSET)
|
||||
# define LPC17_UART4_OSR (LPC17_UART4_BASE+LPC17_UART4_OSR_OFFSET)
|
||||
# define LPC17_UART4_SCICTRL (LPC17_UART4_BASE+LPC17_UART4_SCICTRL_OFFSET)
|
||||
# define LPC17_UART4_SYNCCTRL (LPC17_UART4_BASE+LPC17_UART4_SYNCCTRL_OFFSET)
|
||||
#endif
|
||||
|
||||
/* Register bit definitions *********************************************************/
|
||||
|
||||
/* RBR (DLAB =0) Receiver Buffer Register (all) */
|
||||
|
||||
#define UART_RBR_MASK (0xff) /* Bits 0-7: Oldest received byte in RX FIFO */
|
||||
/* Bits 8-31: Reserved */
|
||||
|
||||
/* THR (DLAB =0) Transmit Holding Register (all) */
|
||||
|
||||
#define UART_THR_MASK (0xff) /* Bits 0-7: Adds byte to TX FIFO */
|
||||
/* Bits 8-31: Reserved */
|
||||
|
||||
/* DLL (DLAB =1) Divisor Latch LSB (all) */
|
||||
|
||||
#define UART_DLL_MASK (0xff) /* Bits 0-7: DLL */
|
||||
/* Bits 8-31: Reserved */
|
||||
|
||||
/* DLM (DLAB =1) Divisor Latch MSB (all) */
|
||||
|
||||
#define UART_DLM_MASK (0xff) /* Bits 0-7: DLM */
|
||||
/* Bits 8-31: Reserved */
|
||||
|
||||
/* IER (DLAB =0) Interrupt Enable Register (all) */
|
||||
|
||||
#define UART_IER_RBRIE (1 << 0) /* Bit 0: RBR Interrupt Enable */
|
||||
#define UART_IER_THREIE (1 << 1) /* Bit 1: THRE Interrupt Enable */
|
||||
#define UART_IER_RLSIE (1 << 2) /* Bit 2: RX Line Status Interrupt Enable */
|
||||
#define UART_IER_MSIE (1 << 3) /* Bit 3: Modem Status Interrupt Enable (UART1 only) */
|
||||
/* Bits 4-6: Reserved */
|
||||
#define UART_IER_CTSIE (1 << 7) /* Bit 7: CTS transition interrupt (UART1 only) */
|
||||
#define UART_IER_ABEOIE (1 << 8) /* Bit 8: Enables the end of auto-baud interrupt */
|
||||
#define UART_IER_ABTOIE (1 << 9) /* Bit 9: Enables the auto-baud time-out interrupt */
|
||||
/* Bits 10-31: Reserved */
|
||||
#define UART_IER_ALLIE (0x038f)
|
||||
|
||||
/* IIR Interrupt ID Register (all) */
|
||||
|
||||
#define UART_IIR_INTSTATUS (1 << 0) /* Bit 0: Interrupt status (active low) */
|
||||
#define UART_IIR_INTID_SHIFT (1) /* Bits 1-3: Interrupt identification */
|
||||
#define UART_IIR_INTID_MASK (7 << UART_IIR_INTID_SHIFT)
|
||||
# define UART_IIR_INTID_MSI (0 << UART_IIR_INTID_SHIFT) /* Modem Status (UART1 only) */
|
||||
# define UART_IIR_INTID_THRE (1 << UART_IIR_INTID_SHIFT) /* THRE Interrupt */
|
||||
# define UART_IIR_INTID_RDA (2 << UART_IIR_INTID_SHIFT) /* 2a - Receive Data Available (RDA) */
|
||||
# define UART_IIR_INTID_RLS (3 << UART_IIR_INTID_SHIFT) /* 1 - Receive Line Status (RLS) */
|
||||
# define UART_IIR_INTID_CTI (6 << UART_IIR_INTID_SHIFT) /* 2b - Character Time-out Indicator (CTI) */
|
||||
/* Bits 4-5: Reserved */
|
||||
#define UART_IIR_FIFOEN_SHIFT (6) /* Bits 6-7: Copies of FCR bit 0 */
|
||||
#define UART_IIR_FIFOEN_MASK (3 << UART_IIR_FIFOEN_SHIFT)
|
||||
#define UART_IIR_ABEOINT (1 << 8) /* Bit 8: End of auto-baud interrupt */
|
||||
#define UART_IIR_ABTOINT (1 << 9) /* Bit 9: Auto-baud time-out interrupt */
|
||||
/* Bits 10-31: Reserved */
|
||||
/* FCR FIFO Control Register (all) */
|
||||
|
||||
#define UART_FCR_FIFOEN (1 << 0) /* Bit 0: Enable FIFOs */
|
||||
#define UART_FCR_RXRST (1 << 1) /* Bit 1: RX FIFO Reset */
|
||||
#define UART_FCR_TXRST (1 << 2) /* Bit 2: TX FIFO Reset */
|
||||
#define UART_FCR_DMAMODE (1 << 3) /* Bit 3: DMA Mode Select */
|
||||
/* Bits 4-5: Reserved */
|
||||
#define UART_FCR_RXTRIGGER_SHIFT (6) /* Bits 6-7: RX Trigger Level */
|
||||
#define UART_FCR_RXTRIGGER_MASK (3 << UART_FCR_RXTRIGGER_SHIFT)
|
||||
# define UART_FCR_RXTRIGGER_0 (0 << UART_FCR_RXTRIGGER_SHIFT) /* Trigger level 0 (1 character) */
|
||||
# define UART_FCR_RXTRIGGER_4 (1 << UART_FCR_RXTRIGGER_SHIFT) /* Trigger level 1 (4 characters) */
|
||||
# define UART_FCR_RXTRIGGER_8 (2 << UART_FCR_RXTRIGGER_SHIFT) /* Trigger level 2 (8 characters) */
|
||||
# define UART_FCR_RXTRIGGER_14 (3 << UART_FCR_RXTRIGGER_SHIFT) /* Trigger level 3 (14 characters) */
|
||||
/* Bits 8-31: Reserved */
|
||||
/* LCR Line Control Register (all) */
|
||||
|
||||
#define UART_LCR_WLS_SHIFT (0) /* Bit 0-1: Word Length Select */
|
||||
#define UART_LCR_WLS_MASK (3 << UART_LCR_WLS_SHIFT)
|
||||
# define UART_LCR_WLS_5BIT (0 << UART_LCR_WLS_SHIFT)
|
||||
# define UART_LCR_WLS_6BIT (1 << UART_LCR_WLS_SHIFT)
|
||||
# define UART_LCR_WLS_7BIT (2 << UART_LCR_WLS_SHIFT)
|
||||
# define UART_LCR_WLS_8BIT (3 << UART_LCR_WLS_SHIFT)
|
||||
#define UART_LCR_STOP (1 << 2) /* Bit 2: Stop Bit Select */
|
||||
#define UART_LCR_PE (1 << 3) /* Bit 3: Parity Enable */
|
||||
#define UART_LCR_PS_SHIFT (4) /* Bits 4-5: Parity Select */
|
||||
#define UART_LCR_PS_MASK (3 << UART_LCR_PS_SHIFT)
|
||||
# define UART_LCR_PS_ODD (0 << UART_LCR_PS_SHIFT) /* Odd parity */
|
||||
# define UART_LCR_PS_EVEN (1 << UART_LCR_PS_SHIFT) /* Even Parity */
|
||||
# define UART_LCR_PS_STICK1 (2 << UART_LCR_PS_SHIFT) /* Forced "1" stick parity */
|
||||
# define UART_LCR_PS_STICK0 (3 << UART_LCR_PS_SHIFT) /* Forced "0" stick parity */
|
||||
#define UART_LCR_BRK (1 << 6) /* Bit 6: Break Control */
|
||||
#define UART_LCR_DLAB (1 << 7) /* Bit 7: Divisor Latch Access Bit (DLAB) */
|
||||
/* Bits 8-31: Reserved */
|
||||
/* MCR Modem Control Register (UART1 only) */
|
||||
|
||||
#define UART_MCR_DTR (1 << 0) /* Bit 0: DTR Control Source for DTR output */
|
||||
#define UART_MCR_RTS (1 << 1) /* Bit 1: Control Source for RTS output */
|
||||
/* Bits 2-3: Reserved */
|
||||
#define UART_MCR_LPBK (1 << 4) /* Bit 4: Loopback Mode Select */
|
||||
/* Bit 5: Reserved */
|
||||
#define UART_MCR_RTSEN (1 << 6) /* Bit 6: Enable auto-rts flow control */
|
||||
#define UART_MCR_CTSEN (1 << 7) /* Bit 7: Enable auto-cts flow control */
|
||||
/* Bits 8-31: Reserved */
|
||||
/* LSR Line Status Register (all) */
|
||||
|
||||
#define UART_LSR_RDR (1 << 0) /* Bit 0: Receiver Data Ready */
|
||||
#define UART_LSR_OE (1 << 1) /* Bit 1: Overrun Error */
|
||||
#define UART_LSR_PE (1 << 2) /* Bit 2: Parity Error */
|
||||
#define UART_LSR_FE (1 << 3) /* Bit 3: Framing Error */
|
||||
#define UART_LSR_BI (1 << 4) /* Bit 4: Break Interrupt */
|
||||
#define UART_LSR_THRE (1 << 5) /* Bit 5: Transmitter Holding Register Empty */
|
||||
#define UART_LSR_TEMT (1 << 6) /* Bit 6: Transmitter Empty */
|
||||
#define UART_LSR_RXFE (1 << 7) /* Bit 7: Error in RX FIFO (RXFE) */
|
||||
/* Bits 8-31: Reserved */
|
||||
/* MSR Modem Status Register (UART1 only) */
|
||||
|
||||
#define UART_MSR_DELTACTS (1 << 0) /* Bit 0: CTS state change */
|
||||
#define UART_MSR_DELTADSR (1 << 1) /* Bit 1: DSR state change */
|
||||
#define UART_MSR_RIEDGE (1 << 2) /* Bit 2: RI ow to high transition */
|
||||
#define UART_MSR_DELTADCD (1 << 3) /* Bit 3: DCD state change */
|
||||
#define UART_MSR_CTS (1 << 4) /* Bit 4: CTS State */
|
||||
#define UART_MSR_DSR (1 << 5) /* Bit 5: DSR State */
|
||||
#define UART_MSR_RI (1 << 6) /* Bit 6: Ring Indicator State */
|
||||
#define UART_MSR_DCD (1 << 7) /* Bit 7: Data Carrier Detect State */
|
||||
/* Bits 8-31: Reserved */
|
||||
/* SCR Scratch Pad Register (all) */
|
||||
|
||||
#define UART_SCR_MASK (0xff) /* Bits 0-7: SCR data */
|
||||
/* Bits 8-31: Reserved */
|
||||
/* ACR Auto-baud Control Register (all) */
|
||||
|
||||
#define UART_ACR_START (1 << 0) /* Bit 0: Auto-baud start/running*/
|
||||
#define UART_ACR_MODE (1 << 1) /* Bit 1: Auto-baud mode select*/
|
||||
#define UART_ACR_AUTORESTART (1 << 2) /* Bit 2: Restart in case of time-out*/
|
||||
/* Bits 3-7: Reserved */
|
||||
#define UART_ACR_ABEOINTCLR (1 << 8) /* Bit 8: End of auto-baud interrupt clear */
|
||||
#define UART_ACR_ABTOINTCLRT (1 << 9) /* Bit 9: Auto-baud time-out interrupt clear */
|
||||
/* Bits 10-31: Reserved */
|
||||
/* ICA IrDA Control Register (UART0,2,3 only) */
|
||||
|
||||
#define UART_ICR_IRDAEN (1 << 0) /* Bit 0: Enable IrDA mode */
|
||||
#define UART_ICR_IRDAINV (1 << 1) /* Bit 1: Invert serial input */
|
||||
#define UART_ICR_FIXPULSEEN (1 << 2) /* Bit 2: Enable IrDA fixed pulse width mode */
|
||||
#define UART_ICR_PULSEDIV_SHIFT (3) /* Bits 3-5: Configures the pulse when FixPulseEn = 1 */
|
||||
#define UART_ICR_PULSEDIV_MASK (7 << UART_ICR_PULSEDIV_SHIFT)
|
||||
# define UART_ICR_PULSEDIV_2TPCLK (0 << UART_ICR_PULSEDIV_SHIFT) /* 2 x TPCLK */
|
||||
# define UART_ICR_PULSEDIV_4TPCLK (1 << UART_ICR_PULSEDIV_SHIFT) /* 4 x TPCLK */
|
||||
# define UART_ICR_PULSEDIV_8TPCLK (2 << UART_ICR_PULSEDIV_SHIFT) /* 8 x TPCLK */
|
||||
# define UART_ICR_PULSEDIV_16TPCLK (3 << UART_ICR_PULSEDIV_SHIFT) /* 16 x TPCLK */
|
||||
# define UART_ICR_PULSEDIV_32TPCLK (4 << UART_ICR_PULSEDIV_SHIFT) /* 32 x TPCLK */
|
||||
# define UART_ICR_PULSEDIV_64TPCLK (5 << UART_ICR_PULSEDIV_SHIFT) /* 64 x TPCLK */
|
||||
# define UART_ICR_PULSEDIV_128TPCLK (6 << UART_ICR_PULSEDIV_SHIFT) /* 128 x TPCLK */
|
||||
# define UART_ICR_PULSEDIV_256TPCLK (7 << UART_ICR_PULSEDIV_SHIFT) /* 246 x TPCLK */
|
||||
/* Bits 6-31: Reserved */
|
||||
/* FDR Fractional Divider Register (all) */
|
||||
|
||||
#define UART_FDR_DIVADDVAL_SHIFT (0) /* Bits 0-3: Baud-rate generation pre-scaler divisor value */
|
||||
#define UART_FDR_DIVADDVAL_MASK (15 << UART_FDR_DIVADDVAL_SHIFT)
|
||||
#define UART_FDR_MULVAL_SHIFT (4) /* Bits 4-7 Baud-rate pre-scaler multiplier value */
|
||||
#define UART_FDR_MULVAL_MASK (15 << UART_FDR_MULVAL_SHIFT)
|
||||
/* Bits 8-31: Reserved */
|
||||
/* TER Transmit Enable Register (all) */
|
||||
/* Bits 0-6: Reserved */
|
||||
#define UART_TER_TXEN (1 << 7) /* Bit 7: TX Enable */
|
||||
/* Bits 8-31: Reserved */
|
||||
/* RS-485/EIA-485 Control (UART1 only) */
|
||||
|
||||
#define UART_RS485CTRL_NMMEN (1 << 0) /* Bit 0: RS-485/EIA-485 Normal Multidrop Mode (NMM) enabled */
|
||||
#define UART_RS485CTRL_RXDIS (1 << 1) /* Bit 1: Receiver is disabled */
|
||||
#define UART_RS485CTRL_AADEN (1 << 2) /* Bit 2: Auto Address Detect (AAD) is enabled */
|
||||
#define UART_RS485CTRL_SEL (1 << 3) /* Bit 3: RTS/DTR used for direction control (DCTRL=1) */
|
||||
#define UART_RS485CTRL_DCTRL (1 << 4) /* Bit 4: Enable Auto Direction Control */
|
||||
#define UART_RS485CTRL_OINV (1 << 5) /* Bit 5: Polarity of the direction control signal on RTS/DTR */
|
||||
/* Bits 6-31: Reserved */
|
||||
/* RS-485/EIA-485 address match (UART1 only) */
|
||||
|
||||
#define UART_ADRMATCH_MASK (0xff) /* Bits 0-7: Address match value */
|
||||
/* Bits 8-31: Reserved */
|
||||
/* RS-485/EIA-485 direction control delay (UART1 only) */
|
||||
|
||||
#define UART_RS485DLY_MASK (0xff) /* Bits 0-7: Direction control (RTS/DTR) delay */
|
||||
/* Bits 8-31: Reserved */
|
||||
/* FIFOLVL FIFO Level register (all) */
|
||||
|
||||
#define UART_FIFOLVL_RX_SHIFT (0) /* Bits 0-3: Current level of the UART RX FIFO */
|
||||
#define UART_FIFOLVL_RX_MASK (15 << UART_FIFOLVL_RX_SHIFT)
|
||||
/* Bits 4-7: Reserved */
|
||||
#define UART_FIFOLVL_TX_SHIFT (8) /* Bits 8-11: Current level of the UART TX FIFO */
|
||||
#define UART_FIFOLVL_TX_MASK (15 << UART_FIFOLVL_TX_SHIFT)
|
||||
/* Bits 12-31: Reserved */
|
||||
|
||||
/* SCICTL Smart Card Interface (UART4 only) */
|
||||
|
||||
#ifdef LPC178x
|
||||
# define UART_SCIEN (1 << 0) /* Bit 0: Smart Card Interface enable */
|
||||
# define UART_NACKDIS (1 << 1) /* Bit 1: NACK response disable.Applicable if PROTSEL=0 */
|
||||
# define UART_PROTSEL (1 << 2) /* Bit 2: Protocol Selection ISO7816-3 */
|
||||
# define UART_TXRETRY (7 << 5) /* Bits 5-7: Maximum number of Re-Transmission */
|
||||
# define UART_GUARDTIME_SHIFT (8) /* Bits 8-15: Extra guard time */
|
||||
# define UART_GUARDTIME_MASK (0xff << UART_GUARDTIME_SHIFT)
|
||||
/* Bits 16-31: Reserved */
|
||||
#endif
|
||||
|
||||
/* OSR Oversampling Register (UART4 only) */
|
||||
|
||||
#ifdef LPC178x
|
||||
/* Bit 0: Reserved */
|
||||
# define UART_OSFRAC (7 << 1) /* Bits 1-3: Fractional part of Oversampling Ratio */
|
||||
# define UART_OSINT_SHIFT (4) /* Bits 4-7: Integer part of (Oversampling Ratio -1) */
|
||||
# define UART_OSINT_MASK (0x0f << UART_OSINT_SHIFT)
|
||||
# define UART_FDINT_SHIFT (8) /* Bits 8-14: OSINT extension in Smart Card mode */
|
||||
# define UART_FDINT_MASK (0x7f << UART_FDINT_SHIFT)
|
||||
/* Bits 15-31: Reserved */
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_UART_H */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,156 +0,0 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/lpc17xx/hardware/lpc17_wdt.h
|
||||
*
|
||||
* Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_WDT_H
|
||||
#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_WDT_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "hardware/lpc17_memorymap.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register offsets *****************************************************************/
|
||||
|
||||
#define LPC17_WDT_MOD_OFFSET 0x0000 /* Watchdog mode register */
|
||||
#define LPC17_WDT_TC_OFFSET 0x0004 /* Watchdog timer constant register */
|
||||
#define LPC17_WDT_FEED_OFFSET 0x0008 /* Watchdog feed sequence register */
|
||||
#define LPC17_WDT_TV_OFFSET 0x000c /* Watchdog timer value register */
|
||||
|
||||
#ifdef LPC176x
|
||||
# define LPC17_WDT_CLKSEL_OFFSET 0x0010 /* Watchdog clock source selection register */
|
||||
#endif
|
||||
|
||||
#ifdef LPC178x
|
||||
# define LPC17_WDT_WARNINT_OFFSET 0x0014 /* Watchdog warning interrupt */
|
||||
# define LPC17_WDT_WINDOW_OFFSET 0x0018 /* Watchdog window compare value */
|
||||
#endif
|
||||
|
||||
/* Register addresses ***************************************************************/
|
||||
|
||||
#define LPC17_WDT_MOD (LPC17_WDT_BASE+LPC17_WDT_MOD_OFFSET)
|
||||
#define LPC17_WDT_TC (LPC17_WDT_BASE+LPC17_WDT_TC_OFFSET)
|
||||
#define LPC17_WDT_FEED (LPC17_WDT_BASE+LPC17_WDT_FEED_OFFSET)
|
||||
#define LPC17_WDT_TV (LPC17_WDT_BASE+LPC17_WDT_TV_OFFSET)
|
||||
#define LPC17_WDT_CLKSEL (LPC17_WDT_BASE+LPC17_WDT_CLKSEL_OFFSET)
|
||||
|
||||
#ifdef LPC178x
|
||||
# define LPC17_WDT_WARNINT (LPC17_WDT_BASE+LPC17_WDT_WARNINT_OFFSET)
|
||||
# define LPC17_WDT_WINDOW (LPC17_WDT_BASE+LPC17_WDT_WINDOW_OFFSET)
|
||||
#endif
|
||||
|
||||
/* Register bit definitions *********************************************************/
|
||||
|
||||
/* Watchdog mode register */
|
||||
|
||||
#define WDT_MOD_WDEN (1 << 0) /* Bit 0: Watchdog enable */
|
||||
#define WDT_MOD_WDRESET (1 << 1) /* Bit 1: Watchdog reset enable */
|
||||
#define WDT_MOD_WDTOF (1 << 2) /* Bit 2: Watchdog time-out */
|
||||
#define WDT_MOD_WDINT (1 << 3) /* Bit 3: Watchdog interrupt */
|
||||
#ifdef LPC178x
|
||||
# define WDT_MOD_WDPROTECT (1 << 4) /* Bit 4: Watchdog interrupt */
|
||||
#endif
|
||||
/* Bits 5-31: Reserved */
|
||||
/* Watchdog timer constant register */
|
||||
|
||||
#ifdef LPC176x
|
||||
# define WDT_TC (0xffffffff) /* Bits 0-31: Watchdog time-out interval */
|
||||
#endif
|
||||
#ifdef LPC178x
|
||||
# define WDT_TC (0x00ffffff) /* Bits 0-23: Watchdog time-out interval */
|
||||
/* Bits 24-31: Reserved */
|
||||
#endif
|
||||
|
||||
/* Watchdog feed sequence register */
|
||||
|
||||
#define WDT_FEED_MASK (0xff) /* Bits 0-7: Feed value should be 0xaa
|
||||
* followed by 0x55 */
|
||||
/* Bits 14-31: Reserved */
|
||||
/* Watchdog timer value register */
|
||||
|
||||
#ifdef LPC176x
|
||||
# define WDT_TVT (0xffffffff) /* Bits 0-31: Watchdog timer value */
|
||||
#endif
|
||||
#ifdef LPC178x
|
||||
# define WDT_TVT (0xffffff) /* Bits 0-23: Watchdog timer value */
|
||||
/* Bits 24-31: Reserved */
|
||||
#endif
|
||||
|
||||
/* Watchdog clock source selection register */
|
||||
|
||||
#ifdef LPC176x
|
||||
# define WDT_CLKSEL_WDSEL_SHIFT (0) /* Bits 0-1: Clock source for the Watchdog timer */
|
||||
# define WDT_CLKSEL_WDSEL_MASK (3 << WDT_CLKSEL_WDSEL_SHIFT)
|
||||
# define WDT_CLKSEL_WDSEL_INTRC (0 << WDT_CLKSEL_WDSEL_SHIFT) /* Internal RC osc */
|
||||
# define WDT_CLKSEL_WDSEL_APB (1 << WDT_CLKSEL_WDSEL_SHIFT) /* APB peripheral clock (watchdog pclk) */
|
||||
# define WDT_CLKSEL_WDSEL_RTC (2 << WDT_CLKSEL_WDSEL_SHIFT) /* RTC oscillator (rtc_clk) */
|
||||
/* Bits 2-30: Reserved */
|
||||
# define WDT_CLKSEL_WDLOCK (1 << 31) /* Bit 31: Lock WDT register bits if set */
|
||||
#endif
|
||||
|
||||
/* Watchdog timer warning interrupt register */
|
||||
|
||||
#ifdef LPC178x
|
||||
# define WDT_WARNINT (0x3ff) /* Bits 0-9: Warning Interrupt compare value */
|
||||
/* Bits 10-31: Reserved */
|
||||
#endif
|
||||
|
||||
/* Watchdog timer value register */
|
||||
|
||||
#ifdef LPC178x
|
||||
# define WDT_WINDOW (0xffffff) /* Bits 0-23: Watchdog window value */
|
||||
/* Bits 24-31: Reserved */
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_WDT_H */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,5 +1,5 @@
|
||||
############################################################################
|
||||
# arch/arm/src/lpc17xx/Make.defs
|
||||
# arch/arm/src/lpc17xx_40xx/Make.defs
|
||||
#
|
||||
# Copyright (C) 2010-2011, 2013-2015, 2018 Gregory Nutt. All rights reserved.
|
||||
# Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
@@ -80,7 +80,7 @@ endif
|
||||
# up_initialize(). Then this stub would not be needed.
|
||||
|
||||
ifeq ($(CONFIG_NET),y)
|
||||
ifneq ($(CONFIG_LPC17_ETHERNET),y)
|
||||
ifneq ($(CONFIG_LPC17_40_ETHERNET),y)
|
||||
CMN_CSRCS += up_etherstub.c
|
||||
endif
|
||||
endif
|
||||
@@ -94,90 +94,90 @@ endif
|
||||
|
||||
CHIP_ASRCS =
|
||||
|
||||
CHIP_CSRCS = lpc17_allocateheap.c lpc17_clockconfig.c lpc17_clrpend.c
|
||||
CHIP_CSRCS += lpc17_gpio.c lpc17_i2c.c lpc17_irq.c lpc17_lowputc.c
|
||||
CHIP_CSRCS += lpc17_serial.c lpc17_spi.c lpc17_ssp.c lpc17_start.c
|
||||
CHIP_CSRCS = lpc17_40_allocateheap.c lpc17_40_clockconfig.c lpc17_40_clrpend.c
|
||||
CHIP_CSRCS += lpc17_40_gpio.c lpc17_40_i2c.c lpc17_40_irq.c lpc17_40_lowputc.c
|
||||
CHIP_CSRCS += lpc17_40_serial.c lpc17_40_spi.c lpc17_40_ssp.c lpc17_40_start.c
|
||||
|
||||
# Configuration-dependent LPC17xx files
|
||||
|
||||
ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y)
|
||||
CHIP_CSRCS += lpc17_idle.c
|
||||
CHIP_CSRCS += lpc17_40_idle.c
|
||||
endif
|
||||
|
||||
ifneq ($(CONFIG_SCHED_TICKLESS),y)
|
||||
CHIP_CSRCS += lpc17_timerisr.c
|
||||
CHIP_CSRCS += lpc17_40_timerisr.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_BUILD_PROTECTED),y)
|
||||
CHIP_CSRCS += lpc17_userspace.c lpc17_mpuinit.c
|
||||
CHIP_CSRCS += lpc17_40_userspace.c lpc17_40_mpuinit.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_LPC17_EMC),y)
|
||||
CHIP_CSRCS += lpc17_emc.c
|
||||
ifeq ($(CONFIG_LPC17_40_EMC),y)
|
||||
CHIP_CSRCS += lpc17_40_emc.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_LPC17_GPIOIRQ),y)
|
||||
CHIP_CSRCS += lpc17_gpioint.c
|
||||
ifeq ($(CONFIG_LPC17_40_GPIOIRQ),y)
|
||||
CHIP_CSRCS += lpc17_40_gpioint.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_DEBUG_GPIO_INFO),y)
|
||||
CHIP_CSRCS += lpc17_gpiodbg.c
|
||||
CHIP_CSRCS += lpc17_40_gpiodbg.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_LPC17_LCD),y)
|
||||
CHIP_CSRCS += lpc17_lcd.c
|
||||
ifeq ($(CONFIG_LPC17_40_LCD),y)
|
||||
CHIP_CSRCS += lpc17_40_lcd.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_USBDEV),y)
|
||||
CHIP_CSRCS += lpc17_usbdev.c
|
||||
CHIP_CSRCS += lpc17_40_usbdev.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_USBHOST),y)
|
||||
CHIP_CSRCS += lpc17_usbhost.c
|
||||
CHIP_CSRCS += lpc17_40_usbhost.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_LPC17_GPDMA),y)
|
||||
CHIP_CSRCS += lpc17_gpdma.c
|
||||
ifeq ($(CONFIG_LPC17_40_GPDMA),y)
|
||||
CHIP_CSRCS += lpc17_40_gpdma.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_LPC17_SDCARD),y)
|
||||
CHIP_CSRCS += lpc17_sdcard.c
|
||||
ifeq ($(CONFIG_LPC17_40_SDCARD),y)
|
||||
CHIP_CSRCS += lpc17_40_sdcard.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_NET),y)
|
||||
ifeq ($(CONFIG_LPC17_ETHERNET),y)
|
||||
CHIP_CSRCS += lpc17_ethernet.c
|
||||
ifeq ($(CONFIG_LPC17_40_ETHERNET),y)
|
||||
CHIP_CSRCS += lpc17_40_ethernet.c
|
||||
endif
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_CAN),y)
|
||||
CHIP_CSRCS += lpc17_can.c
|
||||
CHIP_CSRCS += lpc17_40_can.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_LPC17_ADC),y)
|
||||
CHIP_CSRCS += lpc17_adc.c
|
||||
ifeq ($(CONFIG_LPC17_40_ADC),y)
|
||||
CHIP_CSRCS += lpc17_40_adc.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_LPC17_DAC),y)
|
||||
CHIP_CSRCS += lpc17_dac.c
|
||||
ifeq ($(CONFIG_LPC17_40_DAC),y)
|
||||
CHIP_CSRCS += lpc17_40_dac.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_LPC17_RTC),y)
|
||||
ifeq ($(CONFIG_LPC17_40_RTC),y)
|
||||
CHIP_CSRCS += lpc176x_rtc.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_LPC17_PWM1),y)
|
||||
CHIP_CSRCS += lpc17_pwm.c
|
||||
ifeq ($(CONFIG_LPC17_40_PWM1),y)
|
||||
CHIP_CSRCS += lpc17_40_pwm.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_LPC17_MCPWM),y)
|
||||
CHIP_CSRCS += lpc17_mcpwm.c
|
||||
ifeq ($(CONFIG_LPC17_40_MCPWM),y)
|
||||
CHIP_CSRCS += lpc17_40_mcpwm.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_LPC17_TMR0),y)
|
||||
CHIP_CSRCS += lpc17_timer.c
|
||||
ifeq ($(CONFIG_LPC17_40_TMR0),y)
|
||||
CHIP_CSRCS += lpc17_40_timer.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_MTD_PROGMEM),y)
|
||||
CHIP_CSRCS += lpc17_progmem.c
|
||||
CHIP_CSRCS += lpc17_40_progmem.c
|
||||
endif
|
||||
@@ -1,5 +1,5 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/lpc17xx/chip.h
|
||||
* arch/arm/src/lpc17xx_40xx/chip.h
|
||||
*
|
||||
* Copyright (C) 2010-2011, 2013, 2018 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
@@ -33,8 +33,8 @@
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LPC17XX_CHIP_H
|
||||
#define __ARCH_ARM_SRC_LPC17XX_CHIP_H
|
||||
#ifndef __ARCH_ARM_SRC_LPC17XX_40XX_CHIP_H
|
||||
#define __ARCH_ARM_SRC_LPC17XX_40XX_CHIP_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
@@ -45,28 +45,28 @@
|
||||
|
||||
/* Include the chip capabilities file */
|
||||
|
||||
#include <arch/lpc17xx/chip.h>
|
||||
#include <arch/lpc17xx_40xx/chip.h>
|
||||
|
||||
/* Include the chip interrupt definition file */
|
||||
|
||||
#include <arch/lpc17xx/irq.h>
|
||||
#include <arch/lpc17xx_40xx/irq.h>
|
||||
|
||||
/* Include the memory map file. Other chip hardware files should then include
|
||||
* this file for the proper setup.
|
||||
*/
|
||||
|
||||
#include "hardware/lpc17_memorymap.h"
|
||||
#include "hardware/lpc17_40_memorymap.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Provide the required number of peripheral interrupt vector definitions as well.
|
||||
* The definition LPC17_IRQ_NEXTINT simply comes from the chip-specific IRQ header
|
||||
* file included by arch/lpc17xx/irq.h.
|
||||
* The definition LPC17_40_IRQ_NEXTINT simply comes from the chip-specific IRQ header
|
||||
* file included by arch/lpc17xx_40xx/irq.h.
|
||||
*/
|
||||
|
||||
#define ARMV7M_PERIPHERAL_INTERRUPTS LPC17_IRQ_NEXTINT
|
||||
#define ARMV7M_PERIPHERAL_INTERRUPTS LPC17_40_IRQ_NEXTINT
|
||||
|
||||
/* Vector Table Offset Register (VECTAB). Redefine the mask defined in
|
||||
* arch/arm/src/armv7-m/nvic.h; The LPC178x/7x User manual definitions
|
||||
@@ -78,4 +78,4 @@
|
||||
#undef NVIC_VECTAB_TBLOFF_MASK
|
||||
#define NVIC_VECTAB_TBLOFF_MASK (0x3fffff00)
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC17XX_CHIP_H */
|
||||
#endif /* __ARCH_ARM_SRC_LPC17XX_40XX_CHIP_H */
|
||||
136
arch/arm/src/lpc17xx_40xx/hardware/lpc176x_memorymap.h
Normal file
136
arch/arm/src/lpc17xx_40xx/hardware/lpc176x_memorymap.h
Normal file
@@ -0,0 +1,136 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/lpc17xx_40xx/hardware/lpc176x_memorymap.h
|
||||
*
|
||||
* Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC176X_MEMORYMAP_H
|
||||
#define __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC176X_MEMORYMAP_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Memory Map ***********************************************************************/
|
||||
|
||||
#define LPC17_40_FLASH_BASE 0x00000000 /* -0x1fffffff: On-chip non-volatile memory */
|
||||
#define LPC17_40_SRAM_BASE 0x10000000 /* -0x10007fff: On-chip SRAM (devices <=32Kb) */
|
||||
#define LPC17_40_ROM_BASE 0x1fff0000 /* -0x1fffffff: 8Kb Boot ROM with flash services */
|
||||
#define LPC17_40_AHBSRAM_BASE 0x20000000 /* -0x3fffffff: On-chip AHB SRAM (devices >32Kb) */
|
||||
# define LPC17_40_SRAM_BANK0 0x2007c000 /* -0x2007ffff: On-chip AHB SRAM Bank0 (devices >=32Kb) */
|
||||
# define LPC17_40_SRAM_BANK1 0x20080000 /* -0x2008ffff: On-chip AHB SRAM Bank1 (devices 64Kb) */
|
||||
#define LPC17_40_GPIO_BASE 0x2009c000 /* -0x2009ffff: GPIO */
|
||||
#define LPC17_40_APB_BASE 0x40000000 /* -0x5fffffff: APB Peripherals */
|
||||
# define LPC17_40_APB0_BASE 0x40000000 /* -0x4007ffff: APB0 Peripherals */
|
||||
# define LPC17_40_APB1_BASE 0x40080000 /* -0x400fffff: APB1 Peripherals */
|
||||
# define LPC17_40_AHB_BASE 0x50000000 /* -0x501fffff: DMA Controller, Ethernet, and USB */
|
||||
#define LPC17_40_CORTEXM3_BASE 0xe0000000 /* -0xe00fffff: (see armv7-m/nvic.h) */
|
||||
#define LPC17_40_SCS_BASE 0xe000e000
|
||||
#define LPC17_40_DEBUGMCU_BASE 0xe0042000
|
||||
|
||||
/* AHB SRAM Bank sizes **************************************************************/
|
||||
|
||||
#define LPC17_40_BANK0_SIZE (16*1024) /* Size of AHB SRAM Bank0 (if present) */
|
||||
#define LPC17_40_BANK1_SIZE (16*1024) /* Size of AHB SRAM Bank1 (if present) */
|
||||
|
||||
/* APB0 Peripherals *****************************************************************/
|
||||
|
||||
#define LPC17_40_WDT_BASE 0x40000000 /* -0x40003fff: Watchdog timer */
|
||||
#define LPC17_40_TMR0_BASE 0x40004000 /* -0x40007fff: Timer 0 */
|
||||
#define LPC17_40_TMR1_BASE 0x40008000 /* -0x4000bfff: Timer 1 */
|
||||
#define LPC17_40_UART0_BASE 0x4000c000 /* -0x4000ffff: UART 0 */
|
||||
#define LPC17_40_UART1_BASE 0x40010000 /* -0x40013fff: UART 1 */
|
||||
/* -0x40017fff: Reserved */
|
||||
#define LPC17_40_PWM1_BASE 0x40018000 /* -0x4001bfff: PWM 1 */
|
||||
#define LPC17_40_I2C0_BASE 0x4001c000 /* -0x4001ffff: I2C 0 */
|
||||
#define LPC17_40_SPI_BASE 0x40020000 /* -0x40023fff: SPI */
|
||||
#define LPC17_40_RTC_BASE 0x40024000 /* -0x40027fff: RTC + backup registers */
|
||||
#define LPC17_40_GPIOINT_BASE 0x40028000 /* -0x4002bfff: GPIO interrupts */
|
||||
#define LPC17_40_PINCONN_BASE 0x4002c000 /* -0x4002ffff: Pin connect block */
|
||||
#define LPC17_40_SSP1_BASE 0x40030000 /* -0x40033fff: SSP 1 */
|
||||
#define LPC17_40_ADC_BASE 0x40034000 /* -0x40037fff: ADC */
|
||||
#define LPC17_40_CANAFRAM_BASE 0x40038000 /* -0x4003bfff: CAN acceptance filter (AF) RAM */
|
||||
#define LPC17_40_CANAF_BASE 0x4003c000 /* -0x4003ffff: CAN acceptance filter (AF) registers */
|
||||
#define LPC17_40_CAN_BASE 0x40040000 /* -0x40043fff: CAN common registers */
|
||||
#define LPC17_40_CAN1_BASE 0x40044000 /* -0x40047fff: CAN controller l */
|
||||
#define LPC17_40_CAN2_BASE 0x40048000 /* -0x4004bfff: CAN controller 2 */
|
||||
/* -0x4005bfff: Reserved */
|
||||
#define LPC17_40_I2C1_BASE 0x4005c000 /* -0x4005ffff: I2C 1 */
|
||||
/* -0x4007ffff: Reserved */
|
||||
|
||||
/* APB1 Peripherals *****************************************************************/
|
||||
|
||||
/* -0x40087fff: Reserved */
|
||||
#define LPC17_40_SSP0_BASE 0x40088000 /* -0x4008bfff: SSP 0 */
|
||||
#define LPC17_40_DAC_BASE 0x4008c000 /* -0x4008ffff: DAC */
|
||||
#define LPC17_40_TMR2_BASE 0x40090000 /* -0x40093fff: Timer 2 */
|
||||
#define LPC17_40_TMR3_BASE 0x40094000 /* -0x40097fff: Timer 3 */
|
||||
#define LPC17_40_UART2_BASE 0x40098000 /* -0x4009bfff: UART 2 */
|
||||
#define LPC17_40_UART3_BASE 0x4009c000 /* -0x4009ffff: UART 3 */
|
||||
#define LPC17_40_I2C2_BASE 0x400a0000 /* -0x400a3fff: I2C 2 */
|
||||
/* -0x400a7fff: Reserved */
|
||||
#define LPC17_40_I2S_BASE 0x400a8000 /* -0x400abfff: I2S */
|
||||
/* -0x400affff: Reserved */
|
||||
#define LPC17_40_RIT_BASE 0x400b0000 /* -0x400b3fff: Repetitive interrupt timer */
|
||||
/* -0x400b7fff: Reserved */
|
||||
#define LPC17_40_MCPWM_BASE 0x400b8000 /* -0x400bbfff: Motor control PWM */
|
||||
#define LPC17_40_QEI_BASE 0x400bc000 /* -0x400bffff: Quadrature encoder interface */
|
||||
/* -0x400fbfff: Reserved */
|
||||
#define LPC17_40_SYSCON_BASE 0x400fc000 /* -0x400fffff: System control */
|
||||
|
||||
/* AHB Peripherals ******************************************************************/
|
||||
|
||||
#define LPC17_40_ETH_BASE 0x50000000 /* -0x50003fff: Ethernet controller */
|
||||
#define LPC17_40_GPDMA_BASE 0x50004000 /* -0x50007fff: GPDMA controller */
|
||||
#define LPC17_40_USB_BASE 0x5000c000 /* -0x5000cfff: USB controller */
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC176X_MEMORYMAP_H */
|
||||
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Block a user