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SAMA5 CAN: Driver is now code complete but still untested
This commit is contained in:
Gregory Nutt
@@ -5841,6 +5841,7 @@
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warnings from GCC (2013-10-21).
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* arch/arm/src/sama5/chip/sam_can.h: SAMA5D3X CAN register definition
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header file (2013-10-21)
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* arch/arm/src/sama5/sam_can.c and .h: Framework for a SAMA5 CAN drvier.
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* arch/arm/src/sama5/sam_can.c and .h: Framework for a SAMA5 CAN driver.
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Initial checkin is the STM32 CAN driver with name changes (2013-10-21).
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* arch/arm/src/sama5/sam_can.c and .h: SAMA5 CAN driver is code complete
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but still untested (2013-10-22).
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@@ -6,11 +6,11 @@
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* Authors:
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* Li Zhuoyi <lzyy.cn@gmail.com>
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* Gregory Nutt <gnutt@nuttx.org>
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* History:
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* History:
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* 2011-07-12: Initial version (Li Zhuoyi)
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* 2011-08-03: Support CAN1/CAN2 (Li Zhuoyi)
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* 2012-01-02: Add support for CAN loopback mode (Gregory Nutt)
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*
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*
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* This file is a part of NuttX:
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*
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* Copyright (C) 2010 Gregory Nutt. All rights reserved.
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@@ -675,7 +675,7 @@ static void can_txint(FAR struct can_dev_s *dev, bool enable)
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can_putreg(priv, LPC17_CAN_IER_OFFSET, regval);
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irqrestore(flags);
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}
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}
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/****************************************************************************
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@@ -1167,13 +1167,13 @@ static int can_bittiming(struct up_dev_s *priv)
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if (ts1 == ts2 && ts1 > 1 && ts2 < CAN_BTR_TSEG2_MAX)
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{
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ts1--;
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ts2++;
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ts2++;
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}
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}
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/* Otherwise, nquanta is CAN_BIT_QUANTA, ts1 is CONFIG_CAN_TSEG1, ts2 is
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* CONFIG_CAN_TSEG2 and we calculate brp to achieve CAN_BIT_QUANTA quanta
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* in the bit time
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* in the bit time
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*/
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else
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@@ -1183,7 +1183,7 @@ static int can_bittiming(struct up_dev_s *priv)
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brp = (nclks + (CAN_BIT_QUANTA/2)) / CAN_BIT_QUANTA;
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DEBUGASSERT(brp >=1 && brp <= CAN_BTR_BRP_MAX);
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}
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sjw = 1;
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canllvdbg("TS1: %d TS2: %d BRP: %d SJW= %d\n", ts1, ts2, brp, sjw);
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@@ -1235,7 +1235,7 @@ FAR struct can_dev_s *lpc17_caninitialize(int port)
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flags = irqsave();
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#ifdef CONFIG_LPC17_CAN1
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#ifdef CONFIG_LPC17_CAN1
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if (port == 1)
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{
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/* Enable power to the CAN module */
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@@ -1262,7 +1262,7 @@ FAR struct can_dev_s *lpc17_caninitialize(int port)
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}
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else
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#endif
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#ifdef CONFIG_LPC17_CAN2
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#ifdef CONFIG_LPC17_CAN2
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if (port == 2)
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{
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/* Enable power to the CAN module */
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+218
-4
@@ -256,10 +256,12 @@ config SAMA5_SSC1
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config SAMA5_CAN0
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bool "CAN controller 0 (CAN0)"
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default n
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select CAN
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config SAMA5_CAN1
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bool "CAN controller 1 (CAN1)"
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default n
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select CAN
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config SAMA5_SHA
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bool "Secure Hash Algorithm (SHA)"
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@@ -1081,13 +1083,224 @@ config SAMA5_EMAC_REGDEBUG
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Enable very low-level register access debug. Depends on DEBUG.
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config SAMA5_EMAC_ISETH0
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bool
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default y if !SAMA5_EMAC || !SAMA5_GMAC_ISETH0
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default n if SAMA5_EMAC && SAMA5_GMAC_ISETH0
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bool
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default y if !SAMA5_EMAC || !SAMA5_GMAC_ISETH0
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default n if SAMA5_EMAC && SAMA5_GMAC_ISETH0
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endmenu # EMAC device driver options
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endif # SAMA5_EMAC
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if SAMA5_CAN0 || SAMA5_CAN1
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menu "CAN device driver options"
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if SAMA5_CAN0
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config SAMA5_CAN0_BAUD
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int "CAN0 BAUD"
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default 250000
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depends on SAMA5_CAN0
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---help---
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CAN0 BAUD rate. Required if SAMA5_CAN0 is defined.
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config SAMA5_CAN0_NRECVMB
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int "Number of receive mailboxes"
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default 1
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range 1 3
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---help---
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The SAMA5 CAN0 peripheral supports 8 mailboxes that can be used for
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sending and receiving messages. Up the three of these can be set
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aside statically for message reception. The remainder can be
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configured dynamically to send CAN messages. Multiple receive
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mailboxes might needed to either (1) receive bursts of messages, or
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(2) to support multiple groups of messages filtered on message ID.
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NOTE: The maximum of 3 is a completely arbitrary design decision
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and can certainly be changed if you need more.
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config SAMA5_CAN0_ADDR0
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hex "Mailbox 0 address"
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---help---
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This setting defines the address for receive mailbox 0. If CAN_EXTID
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is defined, this should be a 29-bit extended CAN address; otherwise
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it should be an 11-bit standard CAN address.
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config SAMA5_CAN0_MASK0
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hex "Mailbox 0 address mask"
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default 0x7fff if !CAN_EXTID
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default 0x1fffffff if CAN_EXTID
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---help---
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This setting defines the address mask for receive mailbox 0. And
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address matching SAMA5_CAN0_ADDR0 under this mask are accepted. The
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default, all ones, forces an exact match. A value of zero will accept
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any address.
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If CAN_EXTID is defined, this should be a 29-bit extended CAN address
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mask; otherwise it should be an 11-bit standard CAN address.
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config SAMA5_CAN0_ADDR1
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hex "Mailbox 1 address"
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---help---
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This setting defines the address for receive mailbox 1. If CAN_EXTID
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is defined, this should be a 29-bit extended CAN address; otherwise
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it should be an 11-bit standard CAN address.
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This setting is ignored if SAMA5_CAN0_NRECVMB is less than 2.
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config SAMA5_CAN0_MASK1
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hex "Mailbox 1 address mask"
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default 0x7fff if !CAN_EXTID
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default 0x1fffffff if CAN_EXTID
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---help---
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This setting defines the address mask for receive mailbox 1. And
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address matching SAMA5_CAN0_ADDR1 under this mask are accepted. The
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default, all ones, forces an exact match. A value of zero will accept
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any address.
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If CAN_EXTID is defined, this should be a 29-bit extended CAN address
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mask; otherwise it should be an 11-bit standard CAN address.
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This setting is ignored if SAMA5_CAN0_NRECVMB is less than 2.
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config SAMA5_CAN0_ADDR2
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hex "Mailbox 2 address"
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---help---
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This setting defines the address for receive mailbox 2. If CAN_EXTID
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is defined, this should be a 29-bit extended CAN address; otherwise
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it should be an 11-bit standard CAN address.
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This setting is ignored if SAMA5_CAN0_NRECVMB is less than 3.
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config SAMA5_CAN0_MASK2
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hex "Mailbox 1 address mask"
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default 0x7fff if !CAN_EXTID
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default 0x1fffffff if CAN_EXTID
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---help---
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This setting defines the address mask for receive mailbox 2. And
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address matching SAMA5_CAN0_ADDR2 under this mask are accepted. The
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default, all ones, forces an exact match. A value of zero will accept
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any address.
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If CAN_EXTID is defined, this should be a 29-bit extended CAN address
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mask; otherwise it should be an 11-bit standard CAN address.
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This setting is ignored if SAMA5_CAN0_NRECVMB is less than 2.
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endif # SAMA5_CAN0
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if SAMA5_CAN1
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config SAMA5_CAN1_BAUD
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int "CAN1 BAUD"
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default 250000
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depends on SAMA5_CAN1
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---help---
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CAN1 BAUD rate. Required if SAMA5_CAN1 is defined.
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config SAMA5_CAN1_NRECVMB
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int "Number of receive mailboxes"
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default 1
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range 1 3
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---help---
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The SAMA5 CAN1 peripheral supports 8 mailboxes that can be used for
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sending and receiving messages. Up the three of these can be set
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aside statically for message reception. The remainder can be
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configured dynamically to send CAN messages. Multiple receive
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mailboxes might needed to either (1) receive bursts of messages, or
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(2) to support multiple groups of messages filtered on message ID.
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NOTE: The maximum of 3 is a completely arbitrary design decision
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and can certainly be changed if you need more.
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config SAMA5_CAN1_ADDR0
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hex "Mailbox 0 address"
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---help---
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This setting defines the address for receive mailbox 0. If CAN_EXTID
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is defined, this should be a 29-bit extended CAN address; otherwise
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it should be an 11-bit standard CAN address.
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config SAMA5_CAN1_MASK0
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hex "Mailbox 0 address mask"
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default 0x7fff if !CAN_EXTID
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default 0x1fffffff if CAN_EXTID
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---help---
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This setting defines the address mask for receive mailbox 0. And
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address matching SAMA5_CAN1_ADDR0 under this mask are accepted. The
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default, all ones, forces an exact match. A value of zero will accept
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any address.
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If CAN_EXTID is defined, this should be a 29-bit extended CAN address
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mask; otherwise it should be an 11-bit standard CAN address.
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config SAMA5_CAN1_ADDR1
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hex "Mailbox 1 address"
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---help---
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This setting defines the address for receive mailbox 1. If CAN_EXTID
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is defined, this should be a 29-bit extended CAN address; otherwise
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it should be an 11-bit standard CAN address.
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This setting is ignored if SAMA5_CAN0_NRECVMB is less than 2.
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config SAMA5_CAN1_MASK1
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hex "Mailbox 1 address mask"
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default 0x7fff if !CAN_EXTID
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default 0x1fffffff if CAN_EXTID
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---help---
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This setting defines the address mask for receive mailbox 1. And
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address matching SAMA5_CAN1_ADDR1 under this mask are accepted. The
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default, all ones, forces an exact match. A value of zero will accept
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any address.
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If CAN_EXTID is defined, this should be a 29-bit extended CAN address
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mask; otherwise it should be an 11-bit standard CAN address.
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This setting is ignored if SAMA5_CAN1_NRECVMB is less than 2.
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config SAMA5_CAN1_ADDR2
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hex "Mailbox 2 address"
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---help---
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This setting defines the address for receive mailbox 2. If CAN_EXTID
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is defined, this should be a 29-bit extended CAN address; otherwise
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it should be an 11-bit standard CAN address.
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This setting is ignored if SAMA5_CAN1_NRECVMB is less than 3.
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config SAMA5_CAN1_MASK2
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hex "Mailbox 2 address mask"
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default 0x7fff if !CAN_EXTID
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default 0x1fffffff if CAN_EXTID
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---help---
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This setting defines the address mask for receive mailbox 2. And
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address matching SAMA5_CAN1_ADDR2 under this mask are accepted. The
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default, all ones, forces an exact match. A value of zero will accept
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any address.
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If CAN_EXTID is defined, this should be a 29-bit extended CAN address
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mask; otherwise it should be an 11-bit standard CAN address.
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This setting is ignored if SAMA5_CAN1_NRECVMB is less than 3.
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endif # SAMA5_CAN1
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config SAMA5_CAN_AUTOBAUD
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bool "Enable auto-baud"
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default n
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depends on EXPERIMENTAL
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---help---
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Enable the SAMA5 auto-baud feature. NOTE: This feature is not yet
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fully implemented.
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config SAMA5_CAN_REGDEBUG
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bool "CAN Register level debug"
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depends on DEBUG
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default n
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---help---
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Output detailed register-level CAN device debug information.
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Requires also DEBUG.
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endmenu # SPI device driver options
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endif # SAMA5_CAN0 || SAMA5_CAN1
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if SAMA5_SPI0 || SAMA5_SPI1
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menu "SPI device driver options"
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@@ -1123,7 +1336,8 @@ config SAMA5_SPI_REGDEBUG
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depends on DEBUG
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default n
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---help---
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Output detailed register-level SPI device debug information. Requires also DEBUG.
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Output detailed register-level SPI device debug information.
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Requires also DEBUG.
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endmenu # SPI device driver options
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endif # SAMA5_SPI0 || SAMA5_SPI1
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@@ -178,6 +178,14 @@ CHIP_CSRCS += sam_gmac.c
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endif
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endif
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ifeq ($(CONFIG_SAMA5_CAN0),y)
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CHIP_CSRCS += sam_can.c
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else
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ifeq ($(CONFIG_SAMA5_CAN1),y)
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CHIP_CSRCS += sam_can.c
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endif
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endif
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ifeq ($(CONFIG_SAMA5_TWI0),y)
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CHIP_CSRCS += sam_twi.c
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else
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@@ -77,14 +77,14 @@
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#define SAM_CAN_MDH_OFFSET 0x0018 /* Mailbox Data High Register */
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#define SAM_CAN_MCR_OFFSET 0x001c /* Mailbox Control Register */
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#define SAM_CAN_MnMR_OFFSET(n) (SAM_CAN_MAILBOX_OFFSET(n)+SAM_CAN_MMR_OFFSET)
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#define SAM_CAN_MnAM_OFFSET(n) (SAM_CAN_MAILBOX_OFFSET(n)+SAM_CAN_MAM_OFFSET)
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#define SAM_CAN_MnID_OFFSET(n) (SAM_CAN_MAILBOX_OFFSET(n)+SAM_CAN_MID_OFFSET)
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#define SAM_CAN_MnFID_OFFSET(n) (SAM_CAN_MAILBOX_OFFSET(n)+SAM_CAN_MFID_OFFSET)
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#define SAM_CAN_MnSR_OFFSET(n) (SAM_CAN_MAILBOX_OFFSET(n)+SAM_CAN_MSR_OFFSET)
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#define SAM_CAN_MnDL_OFFSET(n) (SAM_CAN_MAILBOX_OFFSET(n)+SAM_CAN_MDL_OFFSET)
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#define SAM_CAN_MnDH_OFFSET(n) (SAM_CAN_MAILBOX_OFFSET(n)+SAM_CAN_MDH_OFFSET)
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#define SAM_CAN_MnCR_OFFSET(n) (SAM_CAN_MAILBOX_OFFSET(n)+SAM_CAN_MCR_OFFSET)
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#define SAM_CAN_MnMR_OFFSET(n) (SAM_CAN_MBn_OFFSET(n)+SAM_CAN_MMR_OFFSET)
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#define SAM_CAN_MnAM_OFFSET(n) (SAM_CAN_MBn_OFFSET(n)+SAM_CAN_MAM_OFFSET)
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#define SAM_CAN_MnID_OFFSET(n) (SAM_CAN_MBn_OFFSET(n)+SAM_CAN_MID_OFFSET)
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#define SAM_CAN_MnFID_OFFSET(n) (SAM_CAN_MBn_OFFSET(n)+SAM_CAN_MFID_OFFSET)
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#define SAM_CAN_MnSR_OFFSET(n) (SAM_CAN_MBn_OFFSET(n)+SAM_CAN_MSR_OFFSET)
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#define SAM_CAN_MnDL_OFFSET(n) (SAM_CAN_MBn_OFFSET(n)+SAM_CAN_MDL_OFFSET)
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#define SAM_CAN_MnDH_OFFSET(n) (SAM_CAN_MBn_OFFSET(n)+SAM_CAN_MDH_OFFSET)
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#define SAM_CAN_MnCR_OFFSET(n) (SAM_CAN_MBn_OFFSET(n)+SAM_CAN_MCR_OFFSET)
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/* CAN Register Addresses ***********************************************************/
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@@ -149,7 +149,7 @@
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#define CAN_MR_TEOF (1 << 4) /* Bit 4: Timestamp Messages at each End of Frame */
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#define CAN_MR_TTM (1 << 5) /* Bit 5: Disable/Enable Time Triggered Mode */
|
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#define CAN_MR_TIMFRZ (1 << 6) /* Bit 6: Enable Timer Freeze */
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#define CAN_MR_DRPT (1 << 7) /* Bit 7: Disable Repeat */
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#define CAN_MR_DRPT (1 << 7) /* Bit 7: Disable Repeat */
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/* Interrupt Enable Register, Interrupt Disable Register, Interrupt Mask Register,
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* and Status Register
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||||
@@ -171,7 +171,7 @@
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#define CAN_INT_ERRP (1 << 18) /* Bit 18: Error Passive Mode */
|
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#define CAN_INT_BOFF (1 << 19) /* Bit 19: Bus Off Mode */
|
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#define CAN_INT_SLEEP (1 << 20) /* Bit 20: CAN Controller in Low-power Mode */
|
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#define CAN_INT_WAKEUP (1 << 21) /* Bit 21: Wake-up Interrupt Enable */
|
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#define CAN_INT_WAKEUP (1 << 21) /* Bit 21: Wake-up Interrupt */
|
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#define CAN_INT_TOVF (1 << 22) /* Bit 22: Timer Overflow */
|
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#define CAN_INT_TSTP (1 << 23) /* Bit 23: Timestamp */
|
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#define CAN_INT_CERR (1 << 24) /* Bit 24: Mailbox CRC Error */
|
||||
@@ -179,6 +179,8 @@
|
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#define CAN_INT_AERR (1 << 26) /* Bit 26: Acknowledgment Error */
|
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#define CAN_INT_FERR (1 << 27) /* Bit 27: Form Error */
|
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#define CAN_INT_BERR (1 << 28) /* Bit 28: Bit Error */
|
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#define CAN_INT_ALLERRORS (0x1f000000)
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#define CAN_INT_ALL (0x1fff00ff)
|
||||
|
||||
#define CAN_SR_RBSY (1 << 29) /* Bit 29: Receiver busy */
|
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#define CAN_SR_TBSY (1 << 30) /* Bit 30: Transmitter busy */
|
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@@ -251,7 +253,7 @@
|
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#define CAN_WPMR_WPKEY_SHIFT (8) /* Bits 8-31: CAN Write Protection Key Password */
|
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#define CAN_WPMR_WPKEY_MASK (0xffffff << CAN_WPMR_WPKEY_SHIFT)
|
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# define CAN_WPMR_WPKEY (0x43414e << CAN_WPMR_WPKEY_SHIFT) /* "CAN" in ASCII */
|
||||
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||||
|
||||
/* Write Protect Status Register */
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|
||||
#define CAN_WPSR_WPVS (1 << 0) /* Bit 0: Write Protection Violation Status */
|
||||
@@ -285,6 +287,13 @@
|
||||
# define CAN_MAM_MIDvA(n) ((uint32_t)(n) << CAN_MAM_MIDvA_SHIFT)
|
||||
#define CAN_MAM_MIDE (1 << 29) /* Bit 29: Identifier Version */
|
||||
|
||||
#define CAN_MAM_EXTID_SHIFT (0) /* Bits 0-28: 29-bit extended address */
|
||||
#define CAN_MAM_EXTID_MASK (0x1fffffff << CAN_MAM_EXTID_SHIFT)
|
||||
# define CAN_MAM_EXTID(n) (((uint32_t)(n) << CAN_MAM_EXTID_SHIFT) | CAN_MAM_MIDE)
|
||||
#define CAN_MAM_STDID_SHIFT (18) /* Bits 18-28: 11-bit standard address */
|
||||
#define CAN_MAM_STDID_MASK (0x7ff << CAN_MAM_STDID_SHIFT)
|
||||
# define CAN_MAM_STDIE(n) ((uint32_t)(n) << CAN_MAM_STDID_SHIFT)
|
||||
|
||||
/* Mailbox ID Register */
|
||||
|
||||
#define CAN_MID_MIDvB_SHIFT (0) /* Bits 0-17: Complementary bits for identifier */
|
||||
@@ -295,6 +304,13 @@
|
||||
# define CAN_MID_MIDvA(n) ((uint32_t)(n) << CAN_MID_MIDvA_SHIFT)
|
||||
#define CAN_MID_MIDE (1 << 29) /* Bit 19: Identifier Version */
|
||||
|
||||
#define CAN_MID_EXTID_SHIFT (0) /* Bits 0-28: 29-bit extended address */
|
||||
#define CAN_MID_EXTID_MASK (0x1fffffff << CAN_MID_EXTID_SHIFT)
|
||||
# define CAN_MID_EXTID(n) (((uint32_t)(n) << CAN_MID_EXTID_SHIFT) | CAN_MID_MIDE)
|
||||
#define CAN_MID_STDID_SHIFT (18) /* Bits 18-28: 11-bit standard address */
|
||||
#define CAN_MID_STDID_MASK (0x7ff << CAN_MID_STDIF_SHIFT)
|
||||
# define CAN_MID_STDID(n) ((uint32_t)(n) << CAN_MID_STDIF_SHIFT)
|
||||
|
||||
/* Mailbox Family ID Register */
|
||||
|
||||
#define CAN_MFID_MASK (0x1fffffff)
|
||||
|
||||
+930
-282
File diff suppressed because it is too large
Load Diff
@@ -56,12 +56,44 @@
|
||||
|
||||
/* CAN BAUD */
|
||||
|
||||
#if defined(CONFIG_SAMA5_CAN0) && !defined(CONFIG_CAN0_BAUD)
|
||||
# error "CONFIG_CAN0_BAUD is not defined"
|
||||
#if defined(CONFIG_SAMA5_CAN0) && !defined(CONFIG_SAMA5_CAN0_BAUD)
|
||||
# error "CONFIG_SAMA5_CAN0_BAUD is not defined"
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SAMA5_CAN1) && !defined(CONFIG_CAN1_BAUD)
|
||||
# error "CONFIG_CAN1_BAUD is not defined"
|
||||
#if defined(CONFIG_SAMA5_CAN1) && !defined(CONFIG_SAMA5_CAN1_BAUD)
|
||||
# error "CONFIG_SAMA5_CAN1_BAUD is not defined"
|
||||
#endif
|
||||
|
||||
/* There must be at least one but not more than three receive mailboxes */
|
||||
|
||||
#ifdef CONFIG_SAMA5_CAN0
|
||||
# if !defined(CONFIG_SAMA5_CAN0_NRECVMB) || CONFIG_SAMA5_CAN0_NRECVMB < 1
|
||||
# undef CONFIG_SAMA5_CAN0_NRECVMB
|
||||
# define CONFIG_SAMA5_CAN0_NRECVMB 1
|
||||
# endif
|
||||
# if CONFIG_SAMA5_CAN0_NRECVMB > 3
|
||||
# warning Current implementation only supports up to three receive mailboxes
|
||||
# undef CONFIG_SAMA5_CAN0_NRECVMB
|
||||
# define CONFIG_SAMA5_CAN0_NRECVMB 3
|
||||
# endif
|
||||
#else
|
||||
# undef CONFIG_SAMA5_CAN0_NRECVMB
|
||||
# define CONFIG_SAMA5_CAN0_NRECVMB 0
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SAMA5_CAN1
|
||||
# if !defined(CONFIG_SAMA5_CAN1_NRECVMB) || CONFIG_SAMA5_CAN1_NRECVMB < 1
|
||||
# undef CONFIG_SAMA5_CAN1_NRECVMB
|
||||
# define CONFIG_SAMA5_CAN1_NRECVMB 1
|
||||
# endif
|
||||
# if CONFIG_SAMA5_CAN1_NRECVMB > 3
|
||||
# warning Current implementation only supports up to three receive mailboxes
|
||||
# undef CONFIG_SAMA5_CAN1_NRECVMB
|
||||
# define CONFIG_SAMA5_CAN1_NRECVMB 3
|
||||
# endif
|
||||
#else
|
||||
# undef CONFIG_SAMA5_CAN1_NRECVMB
|
||||
# define CONFIG_SAMA5_CAN1_NRECVMB 0
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
@@ -101,7 +133,7 @@ extern "C" {
|
||||
****************************************************************************/
|
||||
|
||||
struct can_dev_s;
|
||||
FAR struct can_dev_s *sama5_caninitialize(int port);
|
||||
FAR struct can_dev_s *sam_caninitialize(int port);
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
|
||||
+3
-3
@@ -22,7 +22,7 @@ config DEV_ZERO
|
||||
config ARCH_HAVE_RNG
|
||||
bool
|
||||
|
||||
config DEV_RANDOM
|
||||
config DEV_RANDOM
|
||||
bool "Enable /dev/random"
|
||||
default n
|
||||
depends on ARCH_HAVE_RNG
|
||||
@@ -71,7 +71,7 @@ config CAN_NPENDINGRTR
|
||||
The size of the list of pending RTR requests. Default: 4
|
||||
|
||||
config CAN_LOOPBACK
|
||||
bool "CAN extended IDs"
|
||||
bool "CAN loopback mode"
|
||||
default n
|
||||
---help---
|
||||
A CAN driver may or may not support a loopback mode for testing. If the
|
||||
@@ -202,7 +202,7 @@ config RTC_FREQUENCY
|
||||
must be provided. If RTC_HIRES is not defined, RTC_FREQUENCY is
|
||||
assumed to be one Hz.
|
||||
|
||||
config RTC_ALARM
|
||||
config RTC_ALARM
|
||||
bool "RTC Alarm Support"
|
||||
default n
|
||||
depends on RTC
|
||||
|
||||
+2
-4
@@ -335,7 +335,7 @@ EXTERN int can_register(FAR const char *path, FAR struct can_dev_s *dev);
|
||||
* Called from the CAN interrupt handler when new read data is available
|
||||
*
|
||||
* Parameters:
|
||||
* dev - The specifi CAN device
|
||||
* dev - The specific CAN device
|
||||
* hdr - The 16-bit CAN header
|
||||
* data - An array contain the CAN data.
|
||||
*
|
||||
@@ -354,9 +354,7 @@ EXTERN int can_receive(FAR struct can_dev_s *dev, FAR struct can_hdr_s *hdr,
|
||||
* Called from the CAN interrupt handler at the completion of a send operation.
|
||||
*
|
||||
* Parameters:
|
||||
* dev - The specifi CAN device
|
||||
* hdr - The 16-bit CAN header
|
||||
* data - An array contain the CAN data.
|
||||
* dev - The specific CAN device
|
||||
*
|
||||
* Return:
|
||||
* OK on success; a negated errno on failure.
|
||||
|
||||
Reference in New Issue
Block a user