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PIC32: Fix timer 1 source, uart priority, add pre-fetch cache header file
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3636 42af7a65-404d-4744-a932-0658087f49c3
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patacongo
Executable
+176
@@ -0,0 +1,176 @@
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/********************************************************************************************
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* arch/mips/src/pic32mx/pic32mx-che.h
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*
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* Copyright (C) 2011 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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********************************************************************************************/
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#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_CHE_H
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#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_CHE_H
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/********************************************************************************************
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* Included Files
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********************************************************************************************/
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#include <nuttx/config.h>
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#include "pic32mx-memorymap.h"
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/********************************************************************************************
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* Pre-Processor Definitions
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********************************************************************************************/
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/* Register Offsets *************************************************************************/
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#define PIC32MX_CHE_CON_OFFSET 0x0000 /* Pre-fetch cache control register */
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#define PIC32MX_CHE_CONCLR_OFFSET 0x0004 /* Pre-fetch cache control clear register */
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#define PIC32MX_CHE_CONSET_OFFSET 0x0008 /* Pre-fetch cache control set register */
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#define PIC32MX_CHE_CONINV_OFFSET 0x000c /* Pre-fetch cache control invert register */
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#define PIC32MX_CHE_ACC_OFFSET 0x0010 /* Pre-fetch cache access register */
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#define PIC32MX_CHE_ACCCLR_OFFSET 0x0014 /* Pre-fetch cache access clear register */
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#define PIC32MX_CHE_ACCSET_OFFSET 0x0018 /* Pre-fetch cache access set register */
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#define PIC32MX_CHE_ACCINV_OFFSET 0x001c /* Pre-fetch cache access invert register */
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#define PIC32MX_CHE_TAG_OFFSET 0x0020 /* Pre-fetch cache tag register */
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#define PIC32MX_CHE_TAGCLR_OFFSET 0x0024 /* Pre-fetch cache tag clear register */
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#define PIC32MX_CHE_TAGSET_OFFSET 0x0028 /* Pre-fetch cache tag set register */
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#define PIC32MX_CHE_TAGINV_OFFSET 0x002c /* Pre-fetch cache tag invert register */
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#define PIC32MX_CHE_MSK_OFFSET 0x0030 /* Pre-fetch cache tag mask register */
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#define PIC32MX_CHE_MSKCLR_OFFSET 0x0034 /* Pre-fetch cache tag mask clear register */
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#define PIC32MX_CHE_MSKSET_OFFSET 0x0038 /* Pre-fetch cache tag mask set register */
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#define PIC32MX_CHE_MSKINV_OFFSET 0x003c /* Pre-fetch cache tag mask invert register */
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#define PIC32MX_CHE_W0_OFFSET 0x0040 /* Cache word 0 register */
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#define PIC32MX_CHE_W1_OFFSET 0x0050 /* Cache word 1 register */
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#define PIC32MX_CHE_W2_OFFSET 0x0060 /* Cache word 2 register */
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#define PIC32MX_CHE_W3_OFFSET 0x0070 /* Cache word 3 register */
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#define PIC32MX_CHE_LRU_OFFSET 0x0080 /* Cache LRU register */
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#define PIC32MX_CHE_HIT_OFFSET 0x0090 /* Cache hit statistics register */
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#define PIC32MX_CHE_MIS_OFFSET 0x00a0 /* Cache miss statistics register */
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#define PIC32MX_CHE_PFABT_OFFSET 0x00c0 /* Pre-fetch cache abort statistics register */
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/* Register Addresses ***********************************************************************/
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#define PIC32MX_CHE_CON (PIC32MX_CHE_K1BASE+PIC32MX_CHE_CON_OFFSET)
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#define PIC32MX_CHE_CONCLR (PIC32MX_CHE_K1BASE+PIC32MX_CHE_CONCLR_OFFSET)
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#define PIC32MX_CHE_CONSET (PIC32MX_CHE_K1BASE+PIC32MX_CHE_CONSET_OFFSET)
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#define PIC32MX_CHE_CONINV (PIC32MX_CHE_K1BASE+PIC32MX_CHE_CONINV_OFFSET)
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#define PIC32MX_CHE_ACC (PIC32MX_CHE_K1BASE+PIC32MX_CHE_ACC_OFFSET)
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#define PIC32MX_CHE_ACCCLR (PIC32MX_CHE_K1BASE+PIC32MX_CHE_ACCCLR_OFFSET)
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#define PIC32MX_CHE_ACCSET (PIC32MX_CHE_K1BASE+PIC32MX_CHE_ACCSET_OFFSET)
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#define PIC32MX_CHE_ACCINV (PIC32MX_CHE_K1BASE+PIC32MX_CHE_ACCINV_OFFSET)
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#define PIC32MX_CHE_TAG (PIC32MX_CHE_K1BASE+PIC32MX_CHE_TAG_OFFSET)
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#define PIC32MX_CHE_TAGCLR (PIC32MX_CHE_K1BASE+PIC32MX_CHE_TAGCLR_OFFSET)
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#define PIC32MX_CHE_TAGSET (PIC32MX_CHE_K1BASE+PIC32MX_CHE_TAGSET_OFFSET)
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#define PIC32MX_CHE_TAGINV (PIC32MX_CHE_K1BASE+PIC32MX_CHE_TAGINV_OFFSET)
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#define PIC32MX_CHE_MSK (PIC32MX_CHE_K1BASE+PIC32MX_CHE_MSK_OFFSET)
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#define PIC32MX_CHE_MSKCLR (PIC32MX_CHE_K1BASE+PIC32MX_CHE_MSKCLR_OFFSET)
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#define PIC32MX_CHE_MSKSET (PIC32MX_CHE_K1BASE+PIC32MX_CHE_MSKSET_OFFSET)
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#define PIC32MX_CHE_MSKINV (PIC32MX_CHE_K1BASE+PIC32MX_CHE_MSKINV_OFFSET)
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#define PIC32MX_CHE_W0 (PIC32MX_CHE_K1BASE+PIC32MX_CHE_W0_OFFSET)
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#define PIC32MX_CHE_W1 (PIC32MX_CHE_K1BASE+PIC32MX_CHE_W1_OFFSET)
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#define PIC32MX_CHE_W2 (PIC32MX_CHE_K1BASE+PIC32MX_CHE_W2_OFFSET)
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#define PIC32MX_CHE_W3 (PIC32MX_CHE_K1BASE+PIC32MX_CHE_W3_OFFSET)
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#define PIC32MX_CHE_LRU (PIC32MX_CHE_K1BASE+PIC32MX_CHE_LRU_OFFSET)
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#define PIC32MX_CHE_HIT (PIC32MX_CHE_K1BASE+PIC32MX_CHE_HIT_OFFSET)
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#define PIC32MX_CHE_MIS (PIC32MX_CHE_K1BASE+PIC32MX_CHE_MIS_OFFSET)
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#define PIC32MX_CHE_PFABT (PIC32MX_CHE_K1BASE+PIC32MX_CHE_PFABT_OFFSET)
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/* Register Bit-Field Definitions ***********************************************************/
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/* Pre-fetch cache control register */
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#define CHE_CON_PFMWS_SHIFT (0) /* Bits 0-2: xx */
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#define CHE_CON_PFMWS_MASK (7 << CHE_CON_PFMWS_SHIFT)
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#define CHE_CON_PREFEN_SHIFT (4) /* Bits 4-5: xx */
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#define CHE_CON_PREFEN_MASK (3 << CHE_CON_PREFEN_SHIFT)
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#define CHE_CON_DCSZ_SHIFT (8) /* Bits 8-9: xx */
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#define CHE_CON_DCSZ_MASK (3 << CHE_CON_DCSZ_SHIFT)
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#define CHE_CON_CHECOH (1 << 16) /* Bit 16: xx */
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/* Pre-fetch cache access register */
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#define CHE_ACC_CHEIDX_SHIFT (0) /* Bits 0-3: xx */
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#define CHE_ACC_CHEIDX_MASK (15 << CHE_ACC_CHEIDX_SHIFT)
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#define CHE_ACC_CHEWEN (1 << 31) /* Bit 31: xx */
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/* Pre-fetch cache tag register */
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#define CHE_TAG_LTYPE (1 << 1) /* Bit 1: xx */
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#define CHE_TAG_LLOCK (1 << 2) /* Bit 2: xx */
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#define CHE_TAG_LVALID (1 << 3) /* Bit 3: xx */
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#define CHE_TAG_LTAG_SHIFT (4) /* Bits 4-23: xx */
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#define CHE_TAG_LTAG_MASK (0x000fffff << CHE_TAG_LTAG_SHIFT)
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#define CHE_TAG_LTAGBOOT (1 << 31) /* Bit 31: xx */
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/* Pre-fetch cache tag mask register */
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#define CHE_MSK_SHIFT (5) /* Bits 5-15: xx */
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#define CHE_MSK_MASK (0x7ff << CHE_MSK_SHIFT)
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/* Cache word 0-3 register -- 32-bit cache line data */
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/* Cache LRU register */
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#define CHE_LRU_MASK 0x01ffffff /* Bits 0-24 */
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/* Cache hit statistics register -- 32 bit counter value */
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/* Cache miss statistics register -- 32 bit counter value */
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/* Pre-fetch cache abort statistics register -- 32 bit counter value */
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/********************************************************************************************
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* Public Types
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********************************************************************************************/
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#ifndef __ASSEMBLY__
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/********************************************************************************************
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* Inline Functions
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********************************************************************************************/
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/********************************************************************************************
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* Public Function Prototypes
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********************************************************************************************/
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#ifdef __cplusplus
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#define EXTERN extern "C"
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extern "C" {
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#else
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#define EXTERN extern
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#endif
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#undef EXTERN
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#ifdef __cplusplus
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}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_CHE_H */
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File diff suppressed because it is too large
Load Diff
@@ -540,7 +540,7 @@ devconfig2:
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CONFIG_PIC32MX_UPLLIDIV | DEVCFG2_FPLLODIV_DIV1
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devconfig1:
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.long DEVCFG1_FNOSC_POSCPLL | DEVCFG1_POSCMOD_XT | \
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.long DEVCFG1_FNOSC_POSCPLL | DEVCFG1_POSCMOD_HS | \
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CONFIG_PIC32MX_PBDIV | DEVCFG1_FCKSM_NONE | \
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CONFIG_PIC32MX_WDENABLE
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@@ -176,7 +176,7 @@
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# define PIC32MX_DMACH2_K1BASE (PIC32MX_SFR_K1BASE + 0x000831e0)
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# define PIC32MX_DMACH3_K1BASE (PIC32MX_SFR_K1BASE + 0x000832a0)
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/* Prefetch Register Base Address */
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/* Prefetch Cache Register Base Address */
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# define PIC32MX_CHE_K1BASE (PIC32MX_SFR_K1BASE + 0x00084000)
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@@ -145,6 +145,7 @@ struct up_dev_s
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uint8_t irqe; /* Error IRQ associated with this UART (for enable) */
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uint8_t irqrx; /* RX IRQ associated with this UART (for enable) */
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uint8_t irqtx; /* RX IRQ associated with this UART (for enable) */
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uint8_t irqprio; /* Interrupt priority */
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uint8_t ie; /* Interrupts enabled */
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uint8_t parity; /* 0=none, 1=odd, 2=even */
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uint8_t bits; /* Number of bits (5, 6, 7 or 8) */
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@@ -211,6 +212,7 @@ static struct up_dev_s g_uart1priv =
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.irqe = PIC32MX_IRQSRC_U1E,
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.irqrx = PIC32MX_IRQSRC_U1RX,
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.irqtx = PIC32MX_IRQSRC_U1TX,
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.irqprio = CONFIG_PIC32MX_UART1PRIO,
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.parity = CONFIG_UART2_PARITY,
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.bits = CONFIG_UART2_BITS,
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.stopbits2 = CONFIG_UART2_2STOP,
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@@ -244,6 +246,7 @@ static struct up_dev_s g_uart2priv =
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.irqe = PIC32MX_IRQSRC_U2E,
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.irqrx = PIC32MX_IRQSRC_U2RX,
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.irqtx = PIC32MX_IRQSRC_U2TX,
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.irqprio = CONFIG_PIC32MX_UART2PRIO,
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.parity = CONFIG_UART2_PARITY,
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.bits = CONFIG_UART2_BITS,
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.stopbits2 = CONFIG_UART2_2STOP,
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@@ -341,6 +344,9 @@ static int up_setup(struct uart_dev_s *dev)
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priv->bits, priv->stopbits2);
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#endif
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/* Set up the interrupt priority */
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up_prioritize_irq(priv->irq, priv->irqprio);
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return OK;
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}
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@@ -59,28 +59,28 @@
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* Definitions
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****************************************************************************/
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/* Timer Setup **************************************************************/
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/* Select a timer prescale value. Our goal is to select the timer MATCH
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* register value givent the board's periperhal clock frequency and the
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* desired system timer frequency:
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/* Select a timer 1 prescale value. Our goal is to select the timer MATCH
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* register value given the board's SOSC clock frequency and the desired
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* system timer frequency:
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*
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* TIMER1_MATCH = BOARD_PBCLOCK / TIMER1_PRESCALE / CLOCKS_PER_SEC
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* TIMER1_MATCH = BOARD_SOSC_FREQ / TIMER1_PRESCALE / CLOCKS_PER_SEC
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*
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* We want the largest possible value for MATCH that is less than 65,535, the
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* maximum value for the 16-bit timer register:
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*
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* TIMER1_PRESCALE >= BOARD_PBCLOCK / CLOCKS_PER_SEC / 65535
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* TIMER1_PRESCALE >= BOARD_SOSC_FREQ / CLOCKS_PER_SEC / 65535
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*
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* Timer 1 does not have very many options for the perscaler value. So we
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* can pick the best by brute force. Example:
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*
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* BOARD_PBCLOCK = 40000000
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* BOARD_SOSC_FREQ = 32768
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* CLOCKS_PER_SEC = 100
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* OPTIMAL_PRESCALE = 6
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* TIMER1_PRESCALE = 8
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* TIMER1_MATCH = 50,000
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* OPTIMAL_PRESCALE = 1
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* TIMER1_PRESCALE = 1
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* TIMER1_MATCH = 328 -> 99.90 ticks/sec
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*/
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#define OPTIMAL_PRESCALE (BOARD_PBCLOCK / CLOCKS_PER_SEC / 65535)
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#define OPTIMAL_PRESCALE (BOARD_SOSC_FREQ / CLOCKS_PER_SEC / 65535)
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#if OPTIMAL_PRESCALE <= 1
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# define TIMER1_CON_TCKPS TIMER1_CON_TCKPS_1
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# define TIMER1_PRESCALE 1
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@@ -97,7 +97,7 @@
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# error "This timer frequency cannot be represented"
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#endif
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#define TIMER1_MATCH (BOARD_PBCLOCK / TIMER1_PRESCALE / CLOCKS_PER_SEC)
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#define TIMER1_MATCH (BOARD_SOSC_FREQ / TIMER1_PRESCALE / CLOCKS_PER_SEC)
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/****************************************************************************
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* Private Types
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@@ -143,7 +143,7 @@ int up_timerisr(int irq, uint32_t *regs)
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void up_timerinit(void)
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{
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/* Configure and enable TIMER1 -- source internal (TCS=0) */
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/* Configure and enable TIMER1 -- source internal SOSC (TCS=0) */
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putreg32(TIMER1_CON_TCKPS, PIC32MX_TIMER1_CON);
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putreg32(0, PIC32MX_TIMER1_CNT);
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