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arch/arm/src/nrf52: Add watchdog timer drivers. Includes significant updates from Alan Carvalho de Assis <acassis@gmail.com>
This commit is contained in:
Levin Li
Gregory Nutt
@@ -63,6 +63,11 @@ config NRF52_UART0
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select UART0_SERIALDRIVER
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select NRF52_HAVE_UART
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config NRF52_WDT
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bool "Watchdog (WDT)"
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default n
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select WATCHDOG
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endmenu # NRF52 Peripheral Selection
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menu "GPIO Interrupt Configuration"
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@@ -100,3 +100,8 @@ endif
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ifeq ($(CONFIG_NRF52_HAVE_UART),y)
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CHIP_CSRCS += nrf52_serial.c
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endif
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ifeq ($(CONFIG_NRF52_WDT),y)
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CHIP_CSRCS += nrf52_wdt.c
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endif
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@@ -0,0 +1,103 @@
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/***************************************************************************************************
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* arch/arm/src/nrf52/chip/nrf52_wdt.h
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*
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* Copyright (C) 2018 Gregory Nutt. All rights reserved.
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* Author: Alan Carvalho de Assis <acassis@gmail.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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***************************************************************************************************/
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#ifndef __ARCH_ARM_SRC_NRF52_CHIP_NRF52_WDT_H
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#define __ARCH_ARM_SRC_NRF52_CHIP_NRF52_WDT_H
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/***************************************************************************************************
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* Included Files
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***************************************************************************************************/
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#include <nuttx/config.h>
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#include "chip/nrf52_memorymap.h"
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/***************************************************************************************************
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* Pre-processor Definitions
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***************************************************************************************************/
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/* WDT Register Offsets ****************************************************************************/
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/* Registers for the WDT function: */
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#define NRF52_WDT_TASKS_START_OFFSET 0x0000 /* Start the watchdog */
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#define NRF52_WDT_EVENTS_TIMEOUT_OFFSET 0x0100 /* Watchdog timeout */
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#define NRF52_WDT_INTENSET_OFFSET 0x0304 /* Enable interrupt */
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#define NRF52_WDT_INTENCLR_OFFSET 0x0308 /* Disable interrupt */
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#define NRF52_WDT_RUNSTATUS_OFFSET 0x0400 /* Run status */
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#define NRF52_WDT_REQSTATUS_OFFSET 0x0404 /* Request status */
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#define NRF52_WDT_CRV_OFFSET 0x0504 /* Counter reload value */
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#define NRF52_WDT_RREN_OFFSET 0x0508 /* Enable register for reload request registers */
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#define NRF52_WDT_CONFIG_OFFSET 0x050c /* Configuration register */
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#define NRF52_WDT_RR0_OFFSET 0x0600 /* Reload request 0 */
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#define NRF52_WDT_RR1_OFFSET 0x0604 /* Reload request 1 */
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#define NRF52_WDT_RR2_OFFSET 0x0608 /* Reload request 2 */
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#define NRF52_WDT_RR3_OFFSET 0x060c /* Reload request 3 */
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#define NRF52_WDT_RR4_OFFSET 0x0610 /* Reload request 4 */
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#define NRF52_WDT_RR5_OFFSET 0x0614 /* Reload request 5 */
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#define NRF52_WDT_RR6_OFFSET 0x0618 /* Reload request 6 */
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#define NRF52_WDT_RR7_OFFSET 0x061c /* Reload request 7 */
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#define NRF52_WDT_TASKS_START (NRF52_WDT_BASE + NRF52_WDT_TASKS_START_OFFSET)
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#define NRF52_WDT_EVENTS_TIMEOUT (NRF52_WDT_BASE + NRF52_WDT_EVENTS_TIMEOUT_OFFSET)
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#define NRF52_WDT_INTENSET (NRF52_WDT_BASE + NRF52_WDT_INTENSET_OFFSET)
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#define NRF52_WDT_INTENCLR (NRF52_WDT_BASE + NRF52_WDT_INTENCLR_OFFSET)
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#define NRF52_WDT_RUNSTATUS (NRF52_WDT_BASE + NRF52_WDT_RUNSTATUS_OFFSET)
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#define NRF52_WDT_REQSTATUS (NRF52_WDT_BASE + NRF52_WDT_REQSTATUS_OFFSET)
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#define NRF52_WDT_CRV (NRF52_WDT_BASE + NRF52_WDT_CRV_OFFSET)
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#define NRF52_WDT_RREN (NRF52_WDT_BASE + NRF52_WDT_RREN_OFFSET)
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#define NRF52_WDT_CONFIG (NRF52_WDT_BASE + NRF52_WDT_CONFIG_OFFSET)
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#define NRF52_WDT_RR0 (NRF52_WDT_BASE + NRF52_WDT_RR0_OFFSET)
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#define NRF52_WDT_RR1 (NRF52_WDT_BASE + NRF52_WDT_RR1_OFFSET)
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#define NRF52_WDT_RR2 (NRF52_WDT_BASE + NRF52_WDT_RR2_OFFSET)
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#define NRF52_WDT_RR3 (NRF52_WDT_BASE + NRF52_WDT_RR3_OFFSET)
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#define NRF52_WDT_RR4 (NRF52_WDT_BASE + NRF52_WDT_RR4_OFFSET)
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#define NRF52_WDT_RR5 (NRF52_WDT_BASE + NRF52_WDT_RR5_OFFSET)
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#define NRF52_WDT_RR6 (NRF52_WDT_BASE + NRF52_WDT_RR6_OFFSET)
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#define NRF52_WDT_RR7 (NRF52_WDT_BASE + NRF52_WDT_RR7_OFFSET)
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/* WDT Register Addresses **************************************************************************/
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/* UART Register Bitfield Definitions **************************************************************/
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/* ENABLE Register */
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#define NRF52_UART_ENABLE_DISABLE (0)
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#define NRF52_UART_ENABLE_ENABLE (4)
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/* INTENSET Register */
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#define NRF52_UART_INTENSET_RXDRDY (1 << 2)
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#endif /* __ARCH_ARM_SRC_NRF52_CHIP_NRF52_WDT_H */
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,107 @@
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/****************************************************************************
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* arch/arm/src/nrf52/nrf52_wdg.h
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*
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* Copyright (C) 2018 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_NRF52_NRF52_WDG_H
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#define __ARCH_ARM_SRC_NRF52_NRF52_WDG_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#ifdef CONFIG_WATCHDOG
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#define NRF_WDT_RR_VALUE 0x6E524635UL /* Fixed value, don't modify it */
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#define NRF_WDT_TASK_SET 1
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#define WDT_CONFIG_HALT_POS 3
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#define WDT_CONFIG_SLEEP_POS 0
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#define NRF_WDT_INT_TIMEOUT_MASK 1
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#undef EXTERN
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#if defined(__cplusplus)
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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enum wdg_behaviour_e
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{
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WDG_PAUSE = 0,
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WDG_RUN = 1
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};
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/****************************************************************************
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* Name: nrf52_wdg_initialize
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*
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* Description:
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* Initialize the IWDG watchdog time. The watchdog timer is initialized
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* and registers as 'devpath. The initial state of the watchdog time is
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* disabled.
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*
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* Input Parameters:
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* devpath - The full path to the watchdog. This should be of the form
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* /dev/watchdog0
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* behaviour_sleep - The behaviour of watchdog when CPU enter sleep mode
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* behaviour_halt - The behaviour of watchdog when CPU was HALT by
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* debugger
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*
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* Returned Values:
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* None
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*
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****************************************************************************/
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#ifdef CONFIG_NRF52_WDT
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void nrf52_wdg_initialize(FAR const char *devpath, int16_t behaviour_sleep,
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int16_t behaviour_halt);
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#endif
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#undef EXTERN
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#if defined(__cplusplus)
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}
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#endif
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#endif /* CONFIG_WATCHDOG */
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#endif /* __ARCH_ARM_SRC_NRF52_NRF52_WDG_H */
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