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synced 2026-09-20 21:06:58 +08:00
Beginng of support for GMII/RGMII PHYs
This commit is contained in:
Gregory Nutt
@@ -5640,4 +5640,6 @@
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* arch/arm/src/sama5/sam_gmac.c: Initial GMAC driver is really
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just the EMAC driver forced to compile with the GMAC register
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definitions (2013-9-26).
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* arch/arm/src/sama5/sam_gmac.c and include/nuttx/net/gmii.h:
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Beginning of support for GMII/RGMII PHY support (2013-9-26)
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@@ -277,7 +277,7 @@ config SAMA5_GMAC_NRXBUFFERS
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config SAMA5_GMAC_NTXBUFFERS
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int "Number of TX buffers"
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default 1
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default 8
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---help---
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GMAC buffer memory is segmented into full Ethernet packets (size
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NET_BUFSIZE bytes). This setting provides the number of such packets
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@@ -471,7 +471,7 @@ config SAMA5_EMAC_NRXBUFFERS
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config SAMA5_EMAC_NTXBUFFERS
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int "Number of TX buffers"
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default 1
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default 8
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---help---
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EMAC buffer memory is segmented into full Ethernet packets (size
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NET_BUFSIZE bytes). This setting provides the number of such packets
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@@ -483,7 +483,7 @@
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# define GMAC_NCFGR_CLK_DIV32 (2 << GMAC_NCFGR_CLK_SHIFT) /* MCK divided by 32 (MCK up to 80 MHz) */
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# define GMAC_NCFGR_CLK_DIV48 (3 << GMAC_NCFGR_CLK_SHIFT) /* MCK divided by 48 (MCK up to 120 MHz) */
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# define GMAC_NCFGR_CLK_DIV64 (4 << GMAC_NCFGR_CLK_SHIFT) /* MCK divided by 64 (MCK up to 160 MHz) */
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# define GMAC_NCFGR_CLK_DIV96 (5 << GMAC_NCFGR_CLK_SHIFT) /* MCK divided by 64 (MCK up to 240 MHz) */
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# define GMAC_NCFGR_CLK_DIV96 (5 << GMAC_NCFGR_CLK_SHIFT) /* MCK divided by 96 (MCK up to 240 MHz) */
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#define GMAC_NCFGR_DBW_SHIFT (21) /* Bits 21-22: Data Bus Width */
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#define GMAC_NCFGR_DBW_MASK (3 << GMAC_NCFGR_DBW_SHIFT)
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# define GMAC_NCFGR_DBW_32 (0 << GMAC_NCFGR_DBW_SHIFT) /* 32-bit data bus width */
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@@ -94,7 +94,7 @@
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/* Number of buffer for TX */
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#ifndef CONFIG_SAMA5_EMAC_NTXBUFFERS
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# define CONFIG_SAMA5_EMAC_NTXBUFFERS 32
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# define CONFIG_SAMA5_EMAC_NTXBUFFERS 8
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#endif
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#undef CONFIG_SAMA5_EMAC_NBC
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@@ -294,11 +294,13 @@ static struct sam_emac_s g_emac;
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/* Preallocated data */
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/* TX descriptors list */
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static struct emac_txdesc_s g_txdesc[TX_BUFFERS] __attribute__((aligned(8)));
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static struct emac_txdesc_s g_txdesc[CONFIG_SAMA5_EMAC_NTXBUFFERS]
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__attribute__((aligned(8)));
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/* RX descriptors list */
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static struct emac_rxdesc_s g_rxdesc[RX_BUFFERS]__attribute__((aligned(8)));
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static struct emac_rxdesc_s g_rxdesc[CONFIG_SAMA5_EMAC_NRXBUFFERS]
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__attribute__((aligned(8)));
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/* Transmit Buffers
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*
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@@ -75,6 +75,8 @@
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# define SAMA5_GMAC_PHY_LAN8700 1
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# elif defined(CONFIG_ETH0_PHY_KSZ8051)
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# define SAMA5_GMAC_PHY_KSZ8051 1
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# elif defined(CONFIG_ETH0_PHY_KSZ90x1)
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# define SAMA5_GMAC_PHY_KSZ90x1 1
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# else
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# error ETH0 PHY unrecognized
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# endif
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@@ -85,6 +87,8 @@
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# define SAMA5_GMAC_PHY_LAN8700 1
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# elif defined(CONFIG_ETH1_PHY_KSZ8051)
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# define SAMA5_GMAC_PHY_KSZ8051 1
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# elif defined(CONFIG_ETH1_PHY_KSZ90x1)
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# define SAMA5_GMAC_PHY_KSZ90x1 1
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# else
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# error ETH1 PHY unrecognized
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# endif
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@@ -97,6 +101,8 @@
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# define SAMA5_EMAC_PHY_LAN8700 1
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# elif defined(CONFIG_ETH0_PHY_KSZ8051)
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# define SAMA5_EMAC_PHY_KSZ8051 1
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# elif defined(CONFIG_ETH0_PHY_KSZ90x1)
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# define SAMA5_EMAC_PHY_KSZ90x1 1
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# else
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# error ETH0 PHY unrecognized
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# endif
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@@ -107,6 +113,8 @@
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# define SAMA5_EMAC_PHY_LAN8700 1
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# elif defined(CONFIG_ETH1_PHY_KSZ8051)
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# define SAMA5_EMAC_PHY_KSZ8051 1
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# elif defined(CONFIG_ETH1_PHY_KSZ90x1)
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# define SAMA5_EMAC_PHY_KSZ90x1 1
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# else
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# error ETH1 PHY unrecognized
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# endif
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+213
-139
File diff suppressed because it is too large
Load Diff
@@ -200,6 +200,9 @@ config ETH0_PHY_KS8721
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config ETH0_PHY_KSZ8051
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bool "Micrel KSZ8051 PHY"
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config ETH0_PHY_KSZ90x1
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bool "Micrel KSZ9021/31 PHY"
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config ETH0_PHY_DP83848C
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bool "National Semiconduction DP83848C PHY"
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@@ -228,6 +231,9 @@ config ETH1_PHY_KS8721
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config ETH1_PHY_KSZ8051
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bool "Micrel KSZ8051 PHY"
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config ETH1_PHY_KSZ90x1
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bool "Micrel KSZ9021/31 PHY"
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config ETH1_PHY_DP83848C
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bool "National Semiconduction DP83848C PHY"
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@@ -0,0 +1,261 @@
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/*********************************************************************************************
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* include/nuttx/net/gmii.h
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*
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* Copyright (C) 2013 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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*********************************************************************************************/
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#ifndef __INCLUDE_NUTTX_NET_GMII_H
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#define __INCLUDE_NUTTX_NET_GMII_H
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/*********************************************************************************************
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* Included Files
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*********************************************************************************************/
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#include <nuttx/config.h>
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#include <nuttx/net/mii.h>
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/*********************************************************************************************
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* Pre-Processor Definitions
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*********************************************************************************************/
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/* MII register offsets **********************************************************************/
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/* Common MII management registers. The IEEE 802.3 standard specifies a
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* register set for controlling and gathering status from the PHY layer. The
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* registers are collectively known as the MII Management registers and are
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* detailed in Section 22.2.4 of the IEEE 802.3 specification.
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*/
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#define GMII_MCR MII_MCR /* GMII management control */
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#define GMII_MSR MII_MSR /* GMII management status */
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#define GMII_PHYID1 MII_PHYID1 /* PHY ID 1 */
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#define GMII_PHYID2 MII_PHYID2 /* PHY ID 2 */
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#define GMII_ADVERTISE MII_ADVERTISE /* Auto-negotiation advertisement */
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#define GMII_LPA MII_LPA /* Auto-negotiation link partner base page ability */
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#define GMII_EXPANSION MII_EXPANSION /* Auto-negotiation expansion */
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#define GMII_NEXTPAGE MII_NEXTPAGE /* Auto-negotiation next page */
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#define GMII_LPANEXTPAGE MII_LPANEXTPAGE /* Auto-negotiation link partner received next page */
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#define GMII_CTRL1000 9 /* 1000BASE-T control */
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#define GMII_STAT1000 10 /* 1000BASE-T status */
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#define GMII_PSECR 11 /* PSE Control register */
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#define GMII_ERDWR 12 /* Extend Register - Data Write Register */
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#define GMII_ERDRR 13 /* Extend Register - Data Read Register */
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#define GMII_ESTATUS MII_ESTATUS /* Extended MII status register */
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/* Extended Registers: Registers 16-31 may be used for vendor specific abilities */
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/* Micrel KSZ9021/31 Vendor Specific Registers */
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#define GMII_KSZ90x1_RLPBK 17 /* Remote loopback, LED mode */
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#define GMII_KSZ90x1_LINKMD 18 /* LinkMD(c) cable diagnostic */
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#define GMII_KSZ90x1_PMAPCS 19 /* Digital PMA/PCS status */
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#define GMII_KSZ90x1_RXERR 21 /* RXER counter */
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#define GMII_KSZ90x1_ICS 27 /* Interrupt control/status */
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#define GMII_KSZ90x1_DBGCTRL1 28 /* Digital debug control 1 */
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#define GMII_KSZ90x1_PHYCTRL 31 /* PHY control */
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/* Micrel KSZ9021/31 Extended registers */
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#define GMII_KSZ90x1_CCR 256 /* Common control */
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#define GMII_KSZ90x1_SSR 257 /* Strap status */
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#define GMII_KSZ90x1_OMSOR 258 /* Operation mode strap override */
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#define GMII_KSZ90x1_OMSSR 259 /* Operation mode strap status */
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#define GMII_KSZ90x1_RCCPSR 260 /* RGMII clock and control pad skew */
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#define GMII_KSZ90x1_RRDPSR 261 /* RGMII RX data pad skew */
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#define GMII_KSZ90x1_ATR 263 /* Analog test register */
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/* MII register bit settings *****************************************************************/
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/* MII Control register bit definitions */
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#define GMII_MCR_UNIDIR MII_MCR_UNIDIR
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#define GMII_MCR_SPEED1000 MII_MCR_SPEED1000
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#define GMII_MCR_CTST MII_MCR_CTST
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#define GMII_MCR_FULLDPLX MII_MCR_FULLDPLX
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#define GMII_MCR_ANRESTART MII_MCR_ANRESTART
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#define GMII_MCR_ISOLATE MII_MCR_ISOLATE
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#define GMII_MCR_PDOWN MII_MCR_PDOWN
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#define GMII_MCR_ANENABLE MII_MCR_ANENABLE
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#define GMII_MCR_SPEED100 MII_MCR_SPEED100
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#define GMII_MCR_LOOPBACK MII_MCR_LOOPBACK
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#define GMII_MCR_RESET MII_MCR_RESET
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/* MII Status register bit definitions */
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#define GMII_MSR_EXTCAP MII_MSR_EXTCAP
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#define GMII_MSR_JABBERDETECT MII_MSR_JABBERDETECT
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#define GMII_MSR_LINKSTATUS MII_MSR_LINKSTATUS
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#define GMII_MSR_ANEGABLE MII_MSR_ANEGABLE
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#define GMII_MSR_RFAULT MII_MSR_RFAULT
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#define GMII_MSR_ANEGCOMPLETE MII_MSR_ANEGCOMPLETE
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#define GMII_MSR_UNIDIR MII_MSR_UNIDIR
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#define GMII_MSR_MFRAMESUPPRESS MII_MSR_MFRAMESUPPRESS
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#define GMII_MSR_ESTATEN MII_MSR_ESTATEN
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#define GMII_MSR_100BASET2FULL MII_MSR_100BASET2FULL
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#define GMII_MSR_100BASET2HALF MII_MSR_100BASET2HALF
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#define GMII_MSR_10BASETXHALF MII_MSR_10BASETXHALF
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#define GMII_MSR_10BASETXFULL MII_MSR_10BASETXFULL
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#define GMII_MSR_100BASETXHALF MII_MSR_100BASETXHALF
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#define GMII_MSR_100BASETXFULL MII_MSR_100BASETXFULL
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#define GMII_MSR_100BASET4 MII_MSR_100BASET4
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/* MII ID2 register bits */
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#define GMII_PHYID2_OUI MII_PHYID2_OUI
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#define GMII_PHYID2_MODEL MII_PHYID2_MODEL
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#define GMII_PHYID2_REV MII_PHYID2_REV
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/* Advertisement control register bit definitions */
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#define GMII_ADVERTISE_SELECT MII_ADVERTISE_SELECT
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#define GMII_ADVERTISE_CSMA MII_ADVERTISE_CSMA
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#define GMII_ADVERTISE_8023 MII_ADVERTISE_8023
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#define GMII_ADVERTISE_8029 MII_ADVERTISE_8029
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#define GMII_ADVERTISE_8025 MII_ADVERTISE_8025
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#define GMII_ADVERTISE_1394 MII_ADVERTISE_1394
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#define GMII_ADVERTISE_10BASETXHALF MII_ADVERTISE_10BASETXHALF
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#define GMII_ADVERTISE_1000XFULL MII_ADVERTISE_1000XFULL
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#define GMII_ADVERTISE_10BASETXFULL MII_ADVERTISE_10BASETXFULL
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#define GMII_ADVERTISE_1000XHALF MII_ADVERTISE_1000XHALF
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#define GMII_ADVERTISE_100BASETXHALF MII_ADVERTISE_100BASETXHALF
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#define GMII_ADVERTISE_1000XPAUSE MII_ADVERTISE_1000XPAUSE
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#define GMII_ADVERTISE_100BASETXFULL MII_ADVERTISE_100BASETXFULL
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#define GMII_ADVERTISE_1000XASYMPAU MII_ADVERTISE_1000XASYMPAU
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#define GMII_ADVERTISE_100BASET4 MII_ADVERTISE_100BASET4
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#define GMII_ADVERTISE_FDXPAUSE MII_ADVERTISE_FDXPAUSE
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#define GMII_ADVERTISE_ASYMPAUSE MII_ADVERTISE_ASYMPAUSE
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#define GMII_ADVERTISE_RFAULT MII_ADVERTISE_RFAULT
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#define GMII_ADVERTISE_LPACK MII_ADVERTISE_LPACK
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#define GMII_ADVERTISE_NXTPAGE MII_ADVERTISE_NXTPAGE
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/* Link partner ability register bit definitions */
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#define GMII_LPA_SELECT MII_LPA_SELECT
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#define GMII_LPA_CSMA MII_LPA_CSMA
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#define GMII_LPA_8023 MII_LPA_8023
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#define GMII_LPA_8029 MII_LPA_8029
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#define GMII_LPA_8025 MII_LPA_8025
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#define GMII_LPA_8025 MII_LPA_1394
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#define GMII_LPA_1394 MII_LPA_1394
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#define GMII_LPA_10BASETXHALF MII_LPA_10BASETXHALF
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#define GMII_LPA_1000XFULL MII_LPA_1000XFULL
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#define GMII_LPA_1000XFULL MII_LPA_10BASETXFULL
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#define GMII_LPA_10BASETXFULL MII_LPA_10BASETXFULL
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#define GMII_LPA_1000XHALF MII_LPA_1000XHALF
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#define GMII_LPA_100BASETXHALF MII_LPA_100BASETXHALF
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#define GMII_LPA_1000XPAUSE MII_LPA_1000XPAUSE
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#define GMII_LPA_100BASETXFULL MII_LPA_100BASETXFULL
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#define GMII_LPA_1000XASYMPAU MII_LPA_1000XASYMPAU
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#define GMII_LPA_100BASET4 MII_LPA_100BASET4
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#define GMII_LPA_FDXPAUSE MII_LPA_FDXPAUSE
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#define GMII_LPA_ASYMPAUSE MII_LPA_ASYMPAUSE
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#define GMII_LPA_RFAULT MII_LPA_RFAULT
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#define GMII_LPA_LPACK MII_LPA_LPACK
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#define GMII_LPA_NXTPAGE MII_LPA_NXTPAGE
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/* Link partner ability in next page format */
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#define GMII_LPANP_MESSAGE MII_LPANP_MESSAGE
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#define GMII_LPANP_TOGGLE MII_LPANP_TOGGLE
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#define GMII_LPANP_LACK2 MII_LPANP_LACK2
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#define GMII_LPANP_MSGPAGE MII_LPANP_MSGPAGE
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#define GMII_LPANP_LPACK MII_LPANP_LPACK
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#define GMII_LPANP_NXTPAGE MII_LPANP_NXTPAGE
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/* MII Auto-negotiation expansion register bit definitions */
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#define GMII_EXPANSION_ANEGABLE MII_EXPANSION_ANEGABLE
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#define GMII_EXPANSION_PAGERECVD MII_EXPANSION_PAGERECVD
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#define GMII_EXPANSION_ENABLENPAGE MII_EXPANSION_ENABLENPAGE
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#define GMII_EXPANSION_NXTPAGEABLE MII_EXPANSION_NXTPAGEABLE
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#define GMII_EXPANSION_PARFAULTS MII_EXPANSION_PARFAULTS
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/* Auto-negotiation next page advertisement */
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#define GMII_NPADVERTISE_CODE MII_NPADVERTISE_CODE
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#define GMII_NPADVERTISE_TOGGLE MII_NPADVERTISE_TOGGLE
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#define GMII_NPADVERTISE_ACK2 MII_NPADVERTISE_ACK2
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#define GMII_NPADVERTISE_MSGPAGE MII_NPADVERTISE_MSGPAGE
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#define GMII_NPADVERTISE_NXTPAGE MII_NPADVERTISE_NXTPAGE
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/* MMD access control register */
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#define GMII_MMDCONTROL_DEVAD_SHIFT MII_MMDCONTROL_DEVAD_SHIFT
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#define GMII_MMDCONTROL_DEVAD_MASK MII_MMDCONTROL_DEVAD_MASK
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# define GMII_MMDCONTROL_DEVAD(n) MII_MMDCONTROL_DEVAD(n)
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#define GMII_MMDCONTROL_FUNC_SHIFT MII_MMDCONTROL_FUNC_SHIFT
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#define GMII_MMDCONTROL_FUNC_MASK MII_MMDCONTROL_FUNC_MASK
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# define GMII_MMDCONTROL_FUNC_ADDR MII_MMDCONTROL_FUNC_ADDR
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# define GMII_MMDCONTROL_FUNC_NOINCR MII_MMDCONTROL_FUNC_NOINCR
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# define GMII_MMDCONTROL_FUNC_RWINCR MII_MMDCONTROL_FUNC_RWINCR
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# define GMII_MMDCONTROL_FUNC_WINCR MII_MMDCONTROL_FUNC_WINCR
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/* Extended status register */
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#define GMII_ESTATUS_1000BASETHALF MII_ESTATUS_1000BASETHALF
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#define GMII_ESTATUS_1000BASETFULL MII_ESTATUS_1000BASETFULL
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#define GMII_ESTATUS_1000BASEXHALF MII_ESTATUS_1000BASEXHALF
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#define GMII_ESTATUS_1000BASEXFULL MII_ESTATUS_1000BASEXFULL
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/* Extend Register - Data Write Register */
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#define GMII_ERDWR_ADDR_SHIFT (0) /* Bits 0-7: Select extended register address */
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#define GMII_ERDWR_ADDR_MASK (0xff << GMII_ERDWR_ADDR_SHIFT)
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# define GMII_ERDWR_ADDR(n) ((n) << GMII_ERDWR_ADDR_SHIFT)
|
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#define GMII_ERDWR_PAGE (1 << 8) /* Bit 8: Select page for extended register */
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/* Bits 9-14: Reserved */
|
||||
#define GMII_ERDWR_READ (0) /* Bit 15: 0=Read extended register */
|
||||
#define GMII_ERDWR_WRITE (1 << 15) /* Bit 15: 1=Write extended register */
|
||||
|
||||
/* Extend Register - Data Read Register (16-bit data value) */
|
||||
|
||||
/*********************************************************************************************
|
||||
* Type Definitions
|
||||
*********************************************************************************************/
|
||||
|
||||
/*********************************************************************************************
|
||||
* Public Function Prototypes
|
||||
*********************************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
#define EXTERN extern "C"
|
||||
extern "C" {
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
#undef EXTERN
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCLUDE_NUTTX_NET_GMII_H */
|
||||
+26
-19
@@ -1,7 +1,7 @@
|
||||
/****************************************************************************
|
||||
* include/nuttx/net/mii.h
|
||||
*
|
||||
* Copyright (C) 2008-2010, 2012 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2008-2010, 2012-2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@@ -164,21 +164,6 @@
|
||||
#define MII_LAN8720_IMR 0x1e /* Interrupt Mask Register */
|
||||
#define MII_LAN8720_SCSR 0x1f /* PHY Special Control/Status Register */
|
||||
|
||||
/* GMII */
|
||||
|
||||
#define GMII_MCR MII_MCR /* GMII management control */
|
||||
#define GMII_MSR MII_MSR /* GMII management status */
|
||||
#define GMII_PHYID1 MII_PHYID1 /* PHY ID 1 */
|
||||
#define GMII_PHYID2 MII_PHYID2 /* PHY ID 2 */
|
||||
#define GMII_ADVERTISE MII_ADVERTISE /* Auto-negotiation advertisement */
|
||||
#define GMII_LPA MII_LPA /* Auto-negotiation link partner base page ability */
|
||||
#define GMII_EXPANSION MII_EXPANSION /* Auto-negotiation expansion */
|
||||
#define GMII_NEXTPAGE MII_NEXTPAGE /* Auto-negotiation next page */
|
||||
#define GMII_LPANEXTPAGE MII_LPANEXTPAGE /* Auto-negotiation link partner received next page */
|
||||
#define GMII_CTRL1000 0x09 /* 1000BASE-T control */
|
||||
#define GMII_STAT1000 0x0a /* 1000BASE-T status */
|
||||
#define GMII_ESTATUS MII_ESTATUS /* Extended status register */
|
||||
|
||||
/* MII register bit settings ************************************************/
|
||||
|
||||
/* MII Control register bit definitions */
|
||||
@@ -204,6 +189,7 @@
|
||||
#define MII_MSR_RFAULT (1 << 4) /* Bit 4: Remote fault */
|
||||
#define MII_MSR_ANEGCOMPLETE (1 << 5) /* Bit 5: Auto-negotiation complete */
|
||||
#define MII_MSR_MFRAMESUPPRESS (1 << 6) /* Bit 6: Management frame suppression */
|
||||
#define MII_MSR_UNIDIR (1 << 7) /* Bit 7: Unidirectional ability */
|
||||
#define MII_MSR_ESTATEN (1 << 8) /* Bit 8: Extended Status in R15 */
|
||||
#define MII_MSR_100BASET2FULL (1 << 9) /* Bit 9: 100BASE-T2 half duplex able */
|
||||
#define MII_MSR_100BASET2HALF (1 << 10) /* Bit 10: 100BASE-T2 full duplex able */
|
||||
@@ -213,11 +199,12 @@
|
||||
#define MII_MSR_100BASETXFULL (1 << 14) /* Bit 14: 100BASE-TX full duplex able */
|
||||
#define MII_MSR_100BASET4 (1 << 15) /* Bit 15: 100BASE-T4 able */
|
||||
|
||||
/* MII ID1 register bits: Bits 3-18 of the Organizationally Unique identifier (OUI) */
|
||||
/* MII ID2 register bits */
|
||||
|
||||
#define MII_PHYID2_OUI 0xfc00 /* Bits 19-24 of OUI mask */
|
||||
#define MII_PHYID2_MODEL 0x03f0 /* Model number mask */
|
||||
#define MII_PHYID2_REV 0x000f /* Revision number mask */
|
||||
#define MII_PHYID2_OUI 0xfc00 /* Bits 10-15: OUI mask [24:19] */
|
||||
#define MII_PHYID2_MODEL 0x03f0 /* Bits 4-9: Model number mask */
|
||||
#define MII_PHYID2_REV 0x000f /* Bits 0-3: Revision number mask */
|
||||
|
||||
/* Advertisement control register bit definitions */
|
||||
|
||||
@@ -290,6 +277,26 @@
|
||||
#define MII_NPADVERTISE_MSGPAGE (1 << 13) /* Bit 13: Message page */
|
||||
#define MII_NPADVERTISE_NXTPAGE (1 << 15) /* Bit 15: Next page indication */
|
||||
|
||||
/* MMD access control register */
|
||||
|
||||
#define MII_MMDCONTROL_DEVAD_SHIFT (0) /* Bits 0-4: Device address */
|
||||
#define MII_MMDCONTROL_DEVAD_MASK (31 << MII_MMDCONTROL_DEVAD_SHIFT)
|
||||
# define MII_MMDCONTROL_DEVAD(n) ((n) << MII_MMDCONTROL_DEVAD_SHIFT)
|
||||
/* Bits 5-13: Reserved */
|
||||
#define MII_MMDCONTROL_FUNC_SHIFT (14) /* Bits 14-15: Function */
|
||||
#define MII_MMDCONTROL_FUNC_MASK (3 << MII_MMDCONTROL_FUNC_SHIFT)
|
||||
# define MII_MMDCONTROL_FUNC_ADDR (0 << MII_MMDCONTROL_FUNC_SHIFT) /* Address */
|
||||
# define MII_MMDCONTROL_FUNC_NOINCR (1 << MII_MMDCONTROL_FUNC_SHIFT) /* Data, no post increment */
|
||||
# define MII_MMDCONTROL_FUNC_RWINCR (2 << MII_MMDCONTROL_FUNC_SHIFT) /* Data, post incr on reads & writes */
|
||||
# define MII_MMDCONTROL_FUNC_WINCR (3 << MII_MMDCONTROL_FUNC_SHIFT) /* Data, post incr on writes */
|
||||
|
||||
/* Extended status register */
|
||||
/* Bits 0-11: Reserved */
|
||||
#define MII_ESTATUS_1000BASETHALF (1 << 12) /* Bit 12: 1000BASE-T Half Duplex able */
|
||||
#define MII_ESTATUS_1000BASETFULL (1 << 13) /* Bit 13: 1000BASE-T Full Duplex able */
|
||||
#define MII_ESTATUS_1000BASEXHALF (1 << 14) /* Bit 14: 1000BASE-X Half Duplex able */
|
||||
#define MII_ESTATUS_1000BASEXFULL (1 << 15) /* Bit 15: 1000BASE-X Full Duplex able */
|
||||
|
||||
/* MII PHYADDR register bit definitions */
|
||||
|
||||
#define DP83840_PHYADDR_DUPLEX (1 << 7)
|
||||
|
||||
Reference in New Issue
Block a user