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arch/arm64: Supports cluster PMU
Summary: Some processors implement cluster PMUs, such as Cortex-R82. Signed-off-by: wangming9 <wangming9@xiaomi.com>
This commit is contained in:
wangming9
GUIDINGLI
@@ -156,6 +156,19 @@ config ARCH_HAVE_EL3
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runing at EL3 is not necessary and system register for EL3
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is not accessible
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config ARCH_HAVE_CLUSTER_PMU
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bool
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default n
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---help---
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Some processors implement cluster PMUs, such as Cortex-R82
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config ARCH_CLUSTER_PMU
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bool "Enable the cluster PMUs"
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default n
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depends on ARCH_HAVE_CLUSTER_PMU
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---help---
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If the processor supports cluster PMU, can configure cluster PMU
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config ARCH_ARM64_EXCEPTION_LEVEL
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int "Exception level to operate"
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default 1
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@@ -253,6 +266,7 @@ config ARCH_CORTEX_R82
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select ARCH_ICACHE
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select ARCH_HAVE_MPU
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select ARCH_HAVE_FPU
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select ARCH_HAVE_CLUSTER_PMU
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select ARCH_HAVE_TESTSET
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select ARM64_HAVE_NEON
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@@ -96,6 +96,17 @@
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#define SCTLR_SA_BIT BIT(3)
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#define SCTLR_I_BIT BIT(12)
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#define ACTLR_AUX_BIT BIT(9)
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#define ACTLR_CLPORTS_BIT BIT(8)
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#define ACTLR_CLPMU_BIT BIT(7)
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#define ACTLR_TESTR1_BIT BIT(6)
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#define ACTLR_CDBG_BIT BIT(5)
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#define ACTLR_PATCH_BIT BIT(4)
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#define ACTLR_BPRED_BIT BIT(3)
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#define ACTLR_POWER_BIT BIT(2)
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#define ACTLR_DIAGNOSTIC_BIT BIT(1)
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#define ACTLR_REGIONS_BIT BIT(0)
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/* SPSR M[3:0] define
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*
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* Arm® Architecture Registers Armv8, for Armv8-A architecture profile
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@@ -129,6 +129,12 @@ void arm64_boot_el2_init(void)
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SCTLR_SA_BIT); /* Enable SP alignment check */
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write_sysreg(reg, sctlr_el2);
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#ifdef CONFIG_ARCH_CLUSTER_PMU
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reg = read_sysreg(actlr_el2);
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reg |= ACTLR_CLPMU_BIT;
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write_sysreg(reg, actlr_el2);
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#endif
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reg = read_sysreg(hcr_el2);
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reg |= HCR_RW_BIT; /* EL1 Execution state is AArch64 */
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write_sysreg(reg, hcr_el2);
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@@ -42,11 +42,19 @@ void up_perf_init(void *arg)
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{
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g_cpu_freq = (unsigned long)(uintptr_t)arg;
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#ifdef CONFIG_ARCH_CLUSTER_PMU
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pmu_clucntr_control_config(CLUSTERPMCR_EL1_C | CLUSTERPMCR_EL1_P |
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CLUSTERPMCR_EL1_E);
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pmu_clucntr_ovsclr_config(CLUSTERPMOVSCLR_EL1_C);
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pmu_clucntr_irq_disable(CLUSTERPMINTENCLR_EL1_C);
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pmu_clucntr_enable(CLUSTERPMCNTENSET_EL1_C);
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#else
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pmu_ccntr_ccfiltr_config(PMCCFILTR_EL0_NSH);
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pmu_cntr_control_config(PMCR_EL0_C | PMCR_EL0_E);
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pmu_cntr_trap_control(PMUSERENR_EL0_EN);
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pmu_cntr_irq_disable(PMINTENCLR_EL1_C);
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pmu_cntr_enable(PMCNTENSET_EL0_C);
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#endif
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}
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unsigned long up_perf_getfreq(void)
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@@ -56,7 +64,11 @@ unsigned long up_perf_getfreq(void)
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unsigned long up_perf_gettime(void)
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{
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#ifdef CONFIG_ARCH_CLUSTER_PMU
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return pmu_get_cluccntr();
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#else
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return pmu_get_ccntr();
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#endif
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}
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void up_perf_convert(unsigned long elapsed, struct timespec *ts)
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@@ -85,6 +85,41 @@
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#define PMUSERENR_EL0_SW (1ul << 1) /* Software Increment write trap control */
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#define PMUSERENR_EL0_EN (1ul << 0) /* Software can access all PMU registers at EL0 */
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#ifdef CONFIG_ARCH_CLUSTER_PMU
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/* The CORTEX-R82 processor implements the cluster PMU */
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/* CLUSTERPMCR_EL1 */
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#define CLUSTERPMCR_EL1_X (1ul << 4) /* Enable export of events */
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#define CLUSTERPMCR_EL1_C (1ul << 2) /* Cycle counter reset */
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#define CLUSTERPMCR_EL1_P (1ul << 1) /* Event counter reset */
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#define CLUSTERPMCR_EL1_E (1ul << 0) /* All counters that are accessible at Non-secure EL1 are enabled by PMCNTENSET_EL0 */
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/* CLUSTERPMCNTENSET_EL1 */
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#define CLUSTERPMCNTENSET_EL1_C (1ul << 31) /* Enables the cycle counter register */
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/* CLUSTERPMOVSCLR_EL1 */
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#define CLUSTERPMOVSCLR_EL1_C (1ul << 31) /* CLUSTERPMCCNTR_EL0 overflow bit */
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/* CLUSTERPMSELR_EL1 */
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#define CLUSTERPMSELR_EL1_SEL_C (0x1ful << 0) /* When CLUSTERPMSELR_EL0.SEL is 0b11111, it selects the cycle counter */
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/* CLUSTERPMINTENCLR_EL1 */
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#define CLUSTERPMINTENCLR_EL1_C (1ul << 31) /* CLUSTERPMCCNTR_EL0 overflow interrupt request disable bit */
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#define clusterpmcr_el1 s3_0_c15_c5_0
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#define clusterpmcntenset_el1 s3_0_c15_c5_1
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#define clusterpmovsclr_el1 s3_0_c15_c5_4
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#define clusterpmintenclr_el1 s3_0_c15_c5_7
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#define clusterpmccntr_el1 s3_0_c15_c6_0
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#endif
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/****************************************************************************
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* Inline Functions
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****************************************************************************/
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@@ -232,4 +267,162 @@ static inline void pmu_cntr_irq_disable(uint64_t mask)
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write_sysreg(mask, pmintenclr_el1);
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}
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#ifdef CONFIG_ARCH_CLUSTER_PMU
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/****************************************************************************
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* Name: pmu_get_cluccntr
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*
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* Description:
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* Read cluster cycle counter.
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*
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* Return Value:
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* Cycle count.
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*
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****************************************************************************/
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static inline uint64_t pmu_get_cluccntr(void)
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{
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return read_sysreg(clusterpmccntr_el1);
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}
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/****************************************************************************
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* Name: pmu_cntr_control_config
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*
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* Description:
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* Config counters.
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*
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* Parameters:
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* mask - Configuration flags for counters.
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*
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****************************************************************************/
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static inline void pmu_clucntr_control_config(uint64_t mask)
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{
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write_sysreg(mask, clusterpmcr_el1);
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}
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/****************************************************************************
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* Name: pmu_clucntr_enable
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*
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* Description:
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* Enable counters.
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*
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* Parameters:
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* mask - Counters to enable.
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*
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* Note:
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* Enables one or more of the following:
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* event counters (0-30)
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* cycle counter
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*
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****************************************************************************/
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static inline void pmu_clucntr_enable(uint64_t mask)
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{
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write_sysreg(mask, clusterpmcntenset_el1);
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}
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/****************************************************************************
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* Name: pmu_clucntr_ovsclr_config
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*
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* Description:
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* Clear counter overflow bits.
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*
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* Parameters:
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* mask - Corresponds to the counter overflow bit to clear.
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*
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****************************************************************************/
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static inline void pmu_clucntr_ovsclr_config(uint64_t mask)
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{
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write_sysreg(mask, clusterpmovsclr_el1);
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}
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/****************************************************************************
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* Name: pmu_clucntr_select
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*
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* Description:
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* Selects the current event counter or the cycle counter.
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*
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* Parameters:
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* mask - Select counter flag.
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*
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****************************************************************************/
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static inline void pmu_clucntr_select(uint64_t mask)
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{
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write_sysreg(mask, clusterpmselr_el1);
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}
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/****************************************************************************
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* Name: pmu_clucntr_irq_disable
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*
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* Description:
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* Disable counter overflow interrupt request.
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*
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* Parameters:
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* mask - Counter overflow interrupt request bits to clear.
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*
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* Note:
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* Sets overflow interrupt request bits for one or more of the following:
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* event counters (0-30)
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* cycle counter
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*
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****************************************************************************/
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static inline void pmu_clucntr_irq_disable(uint64_t mask)
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{
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write_sysreg(mask, clusterpmintenclr_el1);
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}
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/****************************************************************************
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* Name: pmu_clucntr_get_xevtyper
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*
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* Description:
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* Gets the selected counter type.
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*
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* Return Value:
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* Select the value of the counter type.
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*
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****************************************************************************/
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static inline uint64_t pmu_clucntr_get_xevtyper(void)
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{
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return read_sysreg(clusterpmxevtyper_el1);
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}
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/****************************************************************************
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* Name: pmu_clucntr_set_xevtyper
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*
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* Description:
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* Sets the selected counter type.
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*
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* Parameters:
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* mask - The value of the type counter.
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*
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****************************************************************************/
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static inline void pmu_clucntr_set_xevtyper(uint64_t mask)
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{
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write_sysreg(mask, clusterpmxevtyper_el1);
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}
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/****************************************************************************
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* Name: pmu_clucntr_get_xevcntr
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*
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* Description:
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* Reads the value of the selected counter.
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*
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* Return Value:
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* Select the value of the counter.
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*
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****************************************************************************/
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static inline uint64_t pmu_clucntr_get_xevcntr(void)
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{
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return read_sysreg(clusterpmxevcntr_el1);
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}
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#endif
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#endif /* __ARCH_ARM64_SRC_COMMON_ARM64_PMU_H */
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