mirror of
https://github.com/apache/nuttx.git
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Files needed to make LPC17xx EMAC RAM more configurable
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3141 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
@@ -50,6 +50,7 @@
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#include "up_internal.h"
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#include "lpc17_memorymap.h"
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#include "lpc17_emacram.h"
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/****************************************************************************
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* Private Definitions
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@@ -137,13 +138,13 @@ void up_addregion(void)
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#ifdef LPC17_HAVE_BANK0
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# if defined(CONFIG_NET) && defined(CONFIG_LPC17_ETHERNET) && defined(LPC17_NETHCONTROLLERS)
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# ifdef LPC17_HAVE_BANK1
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mm_addregion((FAR void*)LPC17_SRAM_BANK1, 16*1024);
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mm_addregion((FAR void*)LPC17_SRAM_BANK1, LPC17_BANK1_SIZE);
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# endif
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# else
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# ifdef LPC17_HAVE_BANK1
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mm_addregion((FAR void*)LPC17_SRAM_BANK0, 32*1024);
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mm_addregion((FAR void*)LPC17_SRAM_BANK0, LPC17_BANK0_SIZE+LPC17_BANK1_SIZE);
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# else
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mm_addregion((FAR void*)LPC17_SRAM_BANK0, 16*1024);
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mm_addregion((FAR void*)LPC17_SRAM_BANK0, LPC17_BANK0_SIZE);
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# endif
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# endif
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#endif
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Executable
+196
@@ -0,0 +1,196 @@
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/************************************************************************************
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* arch/arm/src/lpc17xx/lpc17_emacram.h
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*
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* Copyright (C) 2010 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_EMACRAM_H
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#define __ARCH_ARM_SRC_LPC17XX_LPC17_EMACRAM_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#if defined(CONFIG_NET) && defined(CONFIG_LPC17_ETHERNET)
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#include "chip.h"
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#include "lpc17_memorymap.h"
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/* Does this chip have and ethernet controller? */
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#if LPC17_NETHCONTROLLERS > 0
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Configuration ********************************************************************/
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/* Number of Tx descriptors */
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#ifndef CONFIG_NET_NTXDESC
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# define CONFIG_NET_NTXDESC 18
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#endif
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/* Number of Rx descriptors */
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#ifndef CONFIG_NET_NRXDESC
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# define CONFIG_NET_NRXDESC 18
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#endif
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/* All of AHB SRAM, Bank 0 is set aside for EMAC Tx and Rx descriptors. */
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#define LPC17_EMACRAM_BASE LPC17_SRAM_BANK0
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#define LPC17_EMACRAM_SIZE LPC17_BANK0_SIZE
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/* Descriptors Memory Layout ********************************************************/
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/* EMAC DMA RAM and descriptor definitions. The configured number of descriptors
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* will determine the organization and the size of the descriptor and status tables.
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* There is a complex interaction between the maximum packet size (CONFIG_NET_BUFSIZE)
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* and the number of Rx and Tx descriptors that can be suppored (CONFIG_NET_NRXDESC
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* and CONFIG_NET_NTXDESC): Small buffers -> more packets. This is something that
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* needs to be tuned for you system.
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*
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* For a 16Kb SRAM region, here is the relationship:
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*
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* 16384 <= ntx * (pktsize + 8 + 4) + nrx * (pktsize + 8 + 8)
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*
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* If ntx == nrx and pktsize == 424, then you could have
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* ntx = nrx = 18.
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*
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* An example with all of the details:
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*
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* NTXDESC=18 NRXDESC=18 CONFIG_NET_BUFSIZE=420:
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* LPC17_TXDESCTAB_SIZE = 18*8 = 144
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* LPC17_TXSTATTAB_SIZE = 18*4 = 72
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* LPC17_TXTAB_SIZE = 216
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*
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* LPC17_RXDESCTAB_SIZE = 16*8 = 144
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* LPC17_RXSTATTAB_SIZE = 16*8 = 144
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* LPC17_TXTAB_SIZE = 288
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*
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* LPC17_DESCTAB_SIZE = 504
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* LPC17_DESC_BASE = LPC17_SRAM_BANK0 + 0x00004000 - 504
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* = LPC17_SRAM_BANK0 + 0x00003e08
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* LPC17_TXDESC_BASE = LPC17_SRAM_BANK0 + 0x00003e08
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* LPC17_TXSTAT_BASE = LPC17_SRAM_BANK0 + 0x00003e98
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* LPC17_RXDESC_BASE = LPC17_SRAM_BANK0 + 0x00003ee0
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* LPC17_RXSTAT_BASE = LPC17_SRAM_BANK0 + 0x00003f70
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*
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* LPC17_PKTMEM_BASE = LPC17_SRAM_BANK0
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* LPC17_PKTMEM_SIZE = 0x00004000-504 = 0x00003e40
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* LPC17_PKTMEM_END = LPC17_SRAM_BANK0 + 0x00003e08
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* LPC17_MAXPACKET_SIZE = ((420 + 3 + 2) & ~3) = 424
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* LPC17_NTXPKTS = 18
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* LPC17_NRXPKTS = 18
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* LPC17_TXBUFFER_SIZE = 18 * 424 = 0x00001dd0
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* LPC17_RXBUFFER_SIZE = 18 * 424 = 0x00001dd0
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* LPC17_BUFFER_SIZE = 0x00003ba0
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* LPC17_BUFFER_BASE = LPC17_SRAM_BANK0
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* LPC17_TXBUFFER_BASE = LPC17_SRAM_BANK0
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* LPC17_RXBUFFER_BASE = LPC17_SRAM_BANK0 + 0x00001dd0
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* LPC17_BUFFER_END = LPC17_SRAM_BANK0 + 0x00003ba0
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*
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* Then the check LPC17_BUFFER_END < LPC17_PKTMEM_END passes. The amount of
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* unused memory is small: 0x00003e08-0x00003ba0 or about 616 bytes -- not
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* enough for two more packets.
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*
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* [It is also possible, with some effort, to reclaim any unused
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* SRAM for the use in the heap. But that has not yet been pursued.]
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*/
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#define LPC17_TXDESCTAB_SIZE (CONFIG_NET_NTXDESC*LPC17_TXDESC_SIZE)
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#define LPC17_TXSTATTAB_SIZE (CONFIG_NET_NTXDESC*LPC17_TXSTAT_SIZE)
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#define LPC17_TXTAB_SIZE (LPC17_TXDESCTAB_SIZE+LPC17_TXSTATTAB_SIZE)
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#define LPC17_RXDESCTAB_SIZE (CONFIG_NET_NRXDESC*LPC17_RXDESC_SIZE)
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#define LPC17_RXSTATTAB_SIZE (CONFIG_NET_NRXDESC*LPC17_RXSTAT_SIZE)
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#define LPC17_RXTAB_SIZE (LPC17_RXDESCTAB_SIZE+LPC17_RXSTATTAB_SIZE)
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#define LPC17_DESCTAB_SIZE (LPC17_TXTAB_SIZE+LPC17_RXTAB_SIZE)
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/* Descriptor table memory organization. Descriptor tables are packed at
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* the end of AHB SRAM, Bank 0. The beginning of bank 0 is reserved for
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* packet memory.
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*/
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#define LPC17_DESC_BASE (LPC17_EMACRAM_BASE+LPC17_EMACRAM_SIZE-LPC17_DESCTAB_SIZE)
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#define LPC17_TXDESC_BASE LPC17_DESC_BASE
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#define LPC17_TXSTAT_BASE (LPC17_TXDESC_BASE+LPC17_TXDESCTAB_SIZE)
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#define LPC17_RXDESC_BASE (LPC17_TXSTAT_BASE+LPC17_TXSTATTAB_SIZE)
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#define LPC17_RXSTAT_BASE (LPC17_RXDESC_BASE + LPC17_RXDESCTAB_SIZE)
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/* Now carve up the beginning of SRAM for packet memory. The size of a
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* packet buffer is related to the size of the MTU. We'll round sizes up
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* to multiples of 256 bytes.
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*/
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#define LPC17_PKTMEM_BASE LPC17_EMACRAM_BASE
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#define LPC17_PKTMEM_SIZE (LPC17_EMACRAM_SIZE-LPC17_DESCTAB_SIZE)
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#define LPC17_PKTMEM_END (LPC17_EMACRAM_BASE+LPC17_PKTMEM_SIZE)
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#define LPC17_MAXPACKET_SIZE ((CONFIG_NET_BUFSIZE + 3 + 2) & ~3)
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#define LPC17_NTXPKTS CONFIG_NET_NTXDESC
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#define LPC17_NRXPKTS CONFIG_NET_NRXDESC
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#define LPC17_TXBUFFER_SIZE (LPC17_NTXPKTS * LPC17_MAXPACKET_SIZE)
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#define LPC17_RXBUFFER_SIZE (LPC17_NRXPKTS * LPC17_MAXPACKET_SIZE)
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#define LPC17_BUFFER_SIZE (LPC17_TXBUFFER_SIZE + LPC17_RXBUFFER_SIZE)
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#define LPC17_BUFFER_BASE LPC17_PKTMEM_BASE
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#define LPC17_TXBUFFER_BASE LPC17_BUFFER_BASE
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#define LPC17_RXBUFFER_BASE (LPC17_TXBUFFER_BASE + LPC17_TXBUFFER_SIZE)
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#define LPC17_BUFFER_END (LPC17_BUFFER_BASE + LPC17_BUFFER_SIZE)
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#if LPC17_BUFFER_END > LPC17_PKTMEM_END
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# error "Packet memory overlaps descriptor tables"
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#endif
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/************************************************************************************
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* Public Types
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************************************************************************************/
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/************************************************************************************
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* Public Data
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************************************************************************************/
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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#endif /* LPC17_NETHCONTROLLERS > 0 */
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#endif /* CONFIG_NET && CONFIG_LPC17_ETHERNET */
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#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_EMACRAM_H */
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@@ -60,6 +60,7 @@
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#include "up_arch.h"
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#include "lpc17_syscon.h"
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#include "lpc17_ethernet.h"
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#include "lpc17_emacram.h"
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#include "lpc17_internal.h"
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#include <arch/board/board.h>
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@@ -199,126 +200,6 @@
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# endif
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#endif
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/* Descriptors **************************************************************/
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/* EMAC DMA RAM and descriptor definitions. The configured number of
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* descriptors will determine the organization and the size of the
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* descriptor and status tables. There is a complex interaction between
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* the maximum packet size (CONFIG_NET_BUFSIZE) and the number of
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* Rx and Tx descriptors that can be suppored (CONFIG_NET_NRXDESC and
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* CONFIG_NET_NTXDESC): Small buffers -> more packets. This is
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* something that needs to be tuned for you system.
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*
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* For a 16Kb SRAM region, here is the relationship:
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*
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* 16384 <= ntx * (pktsize + 8 + 4) + nrx * (pktsize + 8 + 8)
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*
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* If ntx == nrx and pktsize == 424, then you could have
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* ntx = nrx = 18.
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*
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* An example with all of the details:
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*
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* NTXDESC=18 NRXDESC=18 CONFIG_NET_BUFSIZE=420:
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* LPC17_TXDESCTAB_SIZE = 18*8 = 144
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* LPC17_TXSTATTAB_SIZE = 18*4 = 72
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* LPC17_TXTAB_SIZE = 216
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*
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* LPC17_RXDESCTAB_SIZE = 16*8 = 144
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* LPC17_RXSTATTAB_SIZE = 16*8 = 144
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* LPC17_TXTAB_SIZE = 288
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*
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* LPC17_DESCTAB_SIZE = 504
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* LPC17_DESC_BASE = LPC17_SRAM_BANK0 + 0x00004000 - 504
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* = LPC17_SRAM_BANK0 + 0x00003e08
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* LPC17_TXDESC_BASE = LPC17_SRAM_BANK0 + 0x00003e08
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* LPC17_TXSTAT_BASE = LPC17_SRAM_BANK0 + 0x00003e98
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* LPC17_RXDESC_BASE = LPC17_SRAM_BANK0 + 0x00003ee0
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* LPC17_RXSTAT_BASE = LPC17_SRAM_BANK0 + 0x00003f70
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*
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* LPC17_PKTMEM_BASE = LPC17_SRAM_BANK0
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* LPC17_PKTMEM_SIZE = 0x00004000-504 = 0x00003e40
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* LPC17_PKTMEM_END = LPC17_SRAM_BANK0 + 0x00003e08
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* LPC17_MAXPACKET_SIZE = ((420 + 3 + 2) & ~3) = 424
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* LPC17_NTXPKTS = 18
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* LPC17_NRXPKTS = 18
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* LPC17_TXBUFFER_SIZE = 18 * 424 = 0x00001dd0
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* LPC17_RXBUFFER_SIZE = 18 * 424 = 0x00001dd0
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* LPC17_BUFFER_SIZE = 0x00003ba0
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* LPC17_BUFFER_BASE = LPC17_SRAM_BANK0
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* LPC17_TXBUFFER_BASE = LPC17_SRAM_BANK0
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* LPC17_RXBUFFER_BASE = LPC17_SRAM_BANK0 + 0x00001dd0
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* LPC17_BUFFER_END = LPC17_SRAM_BANK0 + 0x00003ba0
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*
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* Then the check LPC17_BUFFER_END < LPC17_PKTMEM_END passes. The
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* amount of unused memory is small: 0x00003e08-0x00003ba0 or about
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* 616 bytes -- not enough for two more packets.
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*
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* [It is also possible, with some effort, to reclaim any unused
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* SRAM for the use in the heap. But that has not yet been pursued.]
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*/
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#ifndef CONFIG_NET_NTXDESC
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# define CONFIG_NET_NTXDESC 18
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#endif
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#define LPC17_TXDESCTAB_SIZE (CONFIG_NET_NTXDESC*LPC17_TXDESC_SIZE)
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#define LPC17_TXSTATTAB_SIZE (CONFIG_NET_NTXDESC*LPC17_TXSTAT_SIZE)
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#define LPC17_TXTAB_SIZE (LPC17_TXDESCTAB_SIZE+LPC17_TXSTATTAB_SIZE)
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#ifndef CONFIG_NET_NRXDESC
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# define CONFIG_NET_NRXDESC 18
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#endif
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#define LPC17_RXDESCTAB_SIZE (CONFIG_NET_NRXDESC*LPC17_RXDESC_SIZE)
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#define LPC17_RXSTATTAB_SIZE (CONFIG_NET_NRXDESC*LPC17_RXSTAT_SIZE)
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#define LPC17_RXTAB_SIZE (LPC17_RXDESCTAB_SIZE+LPC17_RXSTATTAB_SIZE)
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#define LPC17_DESCTAB_SIZE (LPC17_TXTAB_SIZE+LPC17_RXTAB_SIZE)
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/* All of AHB SRAM, Bank 0 is set aside for EMAC Tx and Rx descriptors. */
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#define LPC17_BANK0_SIZE 0x00004000
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#define LPC17_EMACRAM_BASE LPC17_SRAM_BANK0
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#define LPC17_EMACRAM_SIZE LPC17_BANK0_SIZE
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/* Descriptor table memory organization. Descriptor tables are packed at
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* the end of AHB SRAM, Bank 0. The beginning of bank 0 is reserved for
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* packet memory.
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*/
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#define LPC17_DESC_BASE (LPC17_EMACRAM_BASE+LPC17_EMACRAM_SIZE-LPC17_DESCTAB_SIZE)
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#define LPC17_TXDESC_BASE LPC17_DESC_BASE
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#define LPC17_TXSTAT_BASE (LPC17_TXDESC_BASE+LPC17_TXDESCTAB_SIZE)
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#define LPC17_RXDESC_BASE (LPC17_TXSTAT_BASE+LPC17_TXSTATTAB_SIZE)
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#define LPC17_RXSTAT_BASE (LPC17_RXDESC_BASE + LPC17_RXDESCTAB_SIZE)
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/* Now carve up the beginning of SRAM for packet memory. The size of a
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* packet buffer is related to the size of the MTU. We'll round sizes up
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* to multiples of 256 bytes.
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*/
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#define LPC17_PKTMEM_BASE LPC17_EMACRAM_BASE
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#define LPC17_PKTMEM_SIZE (LPC17_EMACRAM_SIZE-LPC17_DESCTAB_SIZE)
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#define LPC17_PKTMEM_END (LPC17_EMACRAM_BASE+LPC17_PKTMEM_SIZE)
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#define LPC17_MAXPACKET_SIZE ((CONFIG_NET_BUFSIZE + 3 + 2) & ~3)
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#define LPC17_NTXPKTS CONFIG_NET_NTXDESC
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#define LPC17_NRXPKTS CONFIG_NET_NRXDESC
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#define LPC17_TXBUFFER_SIZE (LPC17_NTXPKTS * LPC17_MAXPACKET_SIZE)
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#define LPC17_RXBUFFER_SIZE (LPC17_NRXPKTS * LPC17_MAXPACKET_SIZE)
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#define LPC17_BUFFER_SIZE (LPC17_TXBUFFER_SIZE + LPC17_RXBUFFER_SIZE)
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#define LPC17_BUFFER_BASE LPC17_PKTMEM_BASE
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#define LPC17_TXBUFFER_BASE LPC17_BUFFER_BASE
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#define LPC17_RXBUFFER_BASE (LPC17_TXBUFFER_BASE + LPC17_TXBUFFER_SIZE)
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#define LPC17_BUFFER_END (LPC17_BUFFER_BASE + LPC17_BUFFER_SIZE)
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#if LPC17_BUFFER_END > LPC17_PKTMEM_END
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# error "Packet memory overlaps descriptor tables"
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#endif
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/****************************************************************************
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* Private Types
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****************************************************************************/
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@@ -65,6 +65,11 @@
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#define LPC17_SCS_BASE 0xe000e000
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#define LPC17_DEBUGMCU_BASE 0xe0042000
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/* AHB SRAM Bank sizes **************************************************************/
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#define LPC17_BANK0_SIZE (16*1024) /* Size of AHB SRAM Bank0 (if present) */
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#define LPC17_BANK1_SIZE (16*1024) /* Size of AHB SRAM Bank1 (if present) */
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/* APB0 Peripherals *****************************************************************/
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#define LPC17_WDT_BASE 0x40000000 /* -0x40003fff: Watchdog timer */
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