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!arch/stm32n6: unify non-standard hardware definition prefixes

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BREAKING CHANGE: STM32N6 non-standard hardware definition macros
(IRQ, peripheral-count, SRAM and related) were renamed to the common
STM32_* prefix. Out-of-tree code must update the affected references.

Signed-off-by: raiden00pl <raiden00@railab.me>
This commit is contained in:
raiden00pl
2026-06-17 17:10:28 +08:00
committed by Xiang Xiao
parent 8e3710d0d7
commit e23af454f1
4 changed files with 13 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm/include/stm32n6/chip.h
+3 -3
View File
@@ -52,10 +52,10 @@
* Each bank requires its RCC MEMENR clock enable bit to be set.
*/
#define STM32N6_SRAM_SIZE (4 * 1024 * 1024) /* 4194304 bytes (4 MiB) */
#define STM32_SRAM_SIZE (4 * 1024 * 1024) /* 4194304 bytes (4 MiB) */
#define STM32N6_NPORTS (12) /* GPIO ports A-H (8) + N, O, P, Q (4) */
#define STM32N6_NUSART (1) /* USART1 */
#define STM32_NPORTS (12) /* GPIO ports A-H (8) + N, O, P, Q (4) */
#define STM32_NUSART (1) /* USART1 */
/* NVIC priority levels *****************************************************/
arch/arm/src/stm32n6/stm32_gpio.c
+4 -4
View File
@@ -55,7 +55,7 @@ static spinlock_t g_configgpio_lock = SP_UNLOCKED;
* 8-11). Note that there is no GPIOI-M on this chip.
*/
const uint32_t g_gpiobase[STM32N6_NPORTS] =
const uint32_t g_gpiobase[STM32_NPORTS] =
{
STM32_GPIOA_BASE, /* Port A - index 0 */
STM32_GPIOB_BASE, /* Port B - index 1 */
@@ -110,7 +110,7 @@ int stm32_configgpio(uint32_t cfgset)
/* Verify that this hardware supports the select GPIO port */
port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
if (port >= STM32N6_NPORTS)
if (port >= STM32_NPORTS)
{
return -EINVAL;
}
@@ -318,7 +318,7 @@ void stm32_gpiowrite(uint32_t pinset, bool value)
unsigned int pin;
port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
if (port < STM32N6_NPORTS)
if (port < STM32_NPORTS)
{
/* Get the port base address */
@@ -358,7 +358,7 @@ bool stm32_gpioread(uint32_t pinset)
unsigned int pin;
port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
if (port < STM32N6_NPORTS)
if (port < STM32_NPORTS)
{
/* Get the port base address */
arch/arm/src/stm32n6/stm32_gpio.h
+1 -1
View File
@@ -243,7 +243,7 @@ extern "C"
/* Base addresses for each GPIO block */
EXTERN const uint32_t g_gpiobase[STM32N6_NPORTS];
EXTERN const uint32_t g_gpiobase[STM32_NPORTS];
/****************************************************************************
* Public Function Prototypes
arch/arm/src/stm32n6/stm32_serial.c
+5 -5
View File
@@ -274,7 +274,7 @@ static struct stm32_serial_s g_usart1priv =
/* This table lets us iterate over the configured USARTs */
static struct stm32_serial_s * const
g_uart_devs[STM32N6_NUSART] =
g_uart_devs[STM32_NUSART] =
{
#ifdef CONFIG_STM32N6_USART1_SERIALDRIVER
[0] = &g_usart1priv,
@@ -639,7 +639,7 @@ static void stm32serial_pm_setsuspend(bool suspend)
g_serialpm.serial_suspended = suspend;
for (n = 0; n < STM32N6_NUSART; n++)
for (n = 0; n < STM32_NUSART; n++)
{
struct stm32_serial_s *priv = g_uart_devs[n];
@@ -1559,7 +1559,7 @@ static int stm32serial_pmprepare(struct pm_callback_s *cb, int domain,
* buffers.
*/
for (n = 0; n < STM32N6_NUSART; n++)
for (n = 0; n < STM32_NUSART; n++)
{
struct stm32_serial_s *priv = g_uart_devs[n];
@@ -1629,7 +1629,7 @@ void arm_earlyserialinit(void)
/* Disable all USART interrupts */
for (i = 0; i < STM32N6_NUSART; i++)
for (i = 0; i < STM32_NUSART; i++)
{
if (g_uart_devs[i])
{
@@ -1694,7 +1694,7 @@ void arm_serialinit(void)
strlcpy(devname, "/dev/ttySx", sizeof(devname));
for (i = 0; i < STM32N6_NUSART; i++)
for (i = 0; i < STM32_NUSART; i++)
{
/* Don't create a device for non-configured ports. */