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bl602: Update register defines and drivers

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This commit is contained in:
Brennan Ashton
2020-12-30 23:27:42 -06:00
committed by Xiang Xiao
parent 1473768ffc
commit e062bd08ce
45 changed files with 7734 additions and 7717 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/risc-v/src/bl602/Kconfig
-40
View File
@@ -18,26 +18,6 @@ config BL602_UART0
bool
default n
config BL602_UART0_TX_PIN
int "UART0 tx pin num"
default 16
depends on BL602_UART0
config BL602_UART0_RX_PIN
int "UART0 rx pin num"
default 7
depends on BL602_UART0
config BL602_UART0_RTS_PIN
int "UART0 rts pin num"
default -1
depends on BL602_UART0
config BL602_UART0_CTS_PIN
int "UART0 cts pin num"
default -1
depends on BL602_UART0
config BL602_HAVE_UART1
bool "UART1"
select BL602_UART1
@@ -48,26 +28,6 @@ config BL602_HAVE_UART1
config BL602_UART1
bool
default n
config BL602_UART1_TX_PIN
int "UART1 tx pin num"
default 4
depends on BL602_UART1
config BL602_UART1_RX_PIN
int "UART1 rx pin num"
default 3
depends on BL602_UART1
config BL602_UART1_RTS_PIN
int "UART1 rts pin num"
default -1
depends on BL602_UART1
config BL602_UART1_CTS_PIN
int "UART1 cts pin num"
default -1
depends on BL602_UART1
config BL602_TIMER0
bool "TIMER0"
arch/risc-v/src/bl602/bl602_boot2.h
+16 -24
View File
@@ -33,22 +33,15 @@
/* Partition table error type definition */
#define PT_ERROR_SUCCESS 0 /* Partition table error type:success */
#define PT_ERROR_TABLE_NOT_VALID \
1 /* Partition table error type:entry not found */
#define PT_ERROR_ENTRY_NOT_FOUND \
2 /* Partition table error type:entry not found */
#define PT_ERROR_ENTRY_UPDATE_FAIL \
3 /* Partition table error type:entry update fail */
#define PT_ERROR_CRC32 4 /* Partition table error type:crc32 error */
#define PT_ERROR_PARAMETER \
5 /* Partition table error type:input parameter error */
#define PT_ERROR_FALSH_READ \
6 /* Partition table error type:flash read error */
#define PT_ERROR_FALSH_WRITE \
7 /* Partition table error type:flash write error */
#define PT_ERROR_FALSH_ERASE \
8 /* Partition table error type:flash erase error */
#define PT_ERROR_SUCCESS 0 /* Success */
#define PT_ERROR_TABLE_NOT_VALID 1 /* Table not valid */
#define PT_ERROR_ENTRY_NOT_FOUND 2 /* Entry not found */
#define PT_ERROR_ENTRY_UPDATE_FAIL 3 /* Entry update fail */
#define PT_ERROR_CRC32 4 /* CRC32 error */
#define PT_ERROR_PARAMETER 5 /* Input parameter error */
#define PT_ERROR_FALSH_READ 6 /* Flash read error */
#define PT_ERROR_FALSH_WRITE 7 /* Flash write error */
#define PT_ERROR_FALSH_ERASE 8 /* Flash erase error */
/* Partition id type definition */
@@ -70,10 +63,10 @@
/* Partition table config definition */
struct pt_table_config_s
struct pt_config_s
{
uint32_t magic_code; /* Partition table magic code */
uint16_t version; /* Partition table verdion */
uint16_t version; /* Partition table version */
uint16_t entry_cnt; /* Partition table entry count */
uint32_t age; /* Partition table age */
uint32_t crc32; /* Partition table CRC32 value */
@@ -81,7 +74,7 @@ struct pt_table_config_s
/* Partition table entry config definition */
struct pt_table_entry_config_s
struct pt_entry_config_s
{
uint8_t type; /* Partition entry type */
uint8_t device; /* Partition entry device */
@@ -95,12 +88,11 @@ struct pt_table_entry_config_s
/* Partition table stuff config definition */
struct pt_table_stuff_config_s
struct pt_stuff_config_s
{
struct pt_table_config_s pt_table; /* Partition table */
struct pt_table_entry_config_s
pt_entries[PT_ENTRY_MAX]; /* Partition entries */
uint32_t crc32; /* Partition entries crc32 */
struct pt_config_s table; /* Partition table */
struct pt_entry_config_s entries[PT_ENTRY_MAX]; /* Entries */
uint32_t crc32; /* Entries crc32 */
};
#endif /* __ASSEMBLY__ */
arch/risc-v/src/bl602/bl602_glb.c
+28 -63
View File
@@ -22,87 +22,52 @@
* Included Files
****************************************************************************/
#include "hardware/bl602_glb.h"
#include <nuttx/config.h>
#include <stdint.h>
#include "riscv_arch.h"
#include "hardware/bl602_glb.h"
/****************************************************************************
* Pre-Processor Declarations
****************************************************************************/
#define nop() asm volatile ("nop")
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: bl602_glb_uart_fun_sel
* Name: bl602_swrst_ahb_slave1
*
* Description:
* Select UART signal function.
* SW Reset ahb slave.
*
* Input Parameters:
* sig: UART signal
* fun: UART function
* slave1: reset signal
*
* Returned Value:
* None
*
****************************************************************************/
void bl602_glb_uart_fun_sel(int sig, int fun)
void bl602_swrst_ahb_slave1(uint32_t slave1)
{
uint32_t sig_pos = 0;
uint32_t tmp_val = 0;
tmp_val = getreg32(GLB_BASE + GLB_UART_SIG_SEL_0_OFFSET);
sig_pos = (sig * 4);
/* Clear original val */
tmp_val = tmp_val & (~(0xf << sig_pos));
/* Set new value */
tmp_val = tmp_val | (fun << sig_pos);
putreg32(tmp_val, GLB_BASE + GLB_UART_SIG_SEL_0_OFFSET);
}
/****************************************************************************
* Name: bl602_glb_ahb_slave1_reset
*
* Description:
* Select UART signal function.
*
* Input Parameters:
* sig: UART signal
* fun: UART function
*
* Returned Value:
* None
*
****************************************************************************/
void bl602_glb_ahb_slave1_reset(uint32_t slave1)
{
uint32_t tmp_val = 0;
tmp_val = getreg32(GLB_BASE + GLB_SWRST_CFG1_OFFSET);
tmp_val &= (~(1 << slave1));
putreg32(tmp_val, GLB_BASE + GLB_SWRST_CFG1_OFFSET);
/* It is to prevent glitch, which cannot be accessed via bus immediately
* after certain register operations, so some nop is added
/* To prevent glitch from accessing bus immediately
* after certain register operations, so some nop delay is added
*/
BL_DRV_DUMMY();
tmp_val = getreg32(GLB_BASE + GLB_SWRST_CFG1_OFFSET);
tmp_val |= (1 << slave1);
putreg32(tmp_val, GLB_BASE + GLB_SWRST_CFG1_OFFSET);
/* It is to prevent glitch, which cannot be accessed via bus immediately
* after certain register operations, so some nop is added
*/
BL_DRV_DUMMY();
tmp_val = getreg32(GLB_BASE + GLB_SWRST_CFG1_OFFSET);
tmp_val &= (~(1 << slave1));
putreg32(tmp_val, GLB_BASE + GLB_SWRST_CFG1_OFFSET);
modifyreg32(BL602_SWRST_CFG1, slave1, 0);
nop();
nop();
nop();
nop();
modifyreg32(BL602_SWRST_CFG1, 0, slave1);
nop();
nop();
nop();
nop();
modifyreg32(BL602_SWRST_CFG1, slave1, 0);
}
arch/risc-v/src/bl602/hardware/bl602_clint.h → arch/risc-v/src/bl602/bl602_glb.h
+42 -9
View File
@@ -1,5 +1,5 @@
/****************************************************************************
* arch/risc-v/src/bl602/hardware/bl602_clint.h
* arch/risc-v/src/bl602/bl602_glb.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
@@ -18,23 +18,56 @@
*
****************************************************************************/
#ifndef __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_CLINT_H
#define __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_CLINT_H
#ifndef __ARCH_RISCV_SRC_BL602_BL602_GLB_H
#define __ARCH_RISCV_SRC_BL602_BL602_GLB_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
/****************************************************************************
* Pre-processor Definitions
* Public Data
****************************************************************************/
#define BL602_CLINT_BASE (0x02000000)
#ifndef __ASSEMBLY__
#define BL602_MTIMER_HIGH ((uint32_t *)(BL602_CLINT_BASE + 0xBFFC))
#define BL602_MTIMER_LOW ((uint32_t *)(BL602_CLINT_BASE + 0xBFF8))
#define BL602_MTIMER_CMP ((uint64_t *)(BL602_CLINT_BASE + 0x4000))
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
#endif /* __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_CLINT_H */
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: bl602_swrst_ahb_slave1
*
* Description:
* SW Reset ahb slave.
*
* Input Parameters:
* slave1: reset signal
*
* Returned Value:
* None
*
****************************************************************************/
void bl602_swrst_ahb_slave1(uint32_t slave1);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_RISCV_SRC_BL602_BL602_GLB_H */
arch/risc-v/src/bl602/bl602_gpio.c
+154 -93
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File diff suppressed because it is too large Load Diff
arch/risc-v/src/bl602/bl602_gpio.h
+297
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File diff suppressed because it is too large Load Diff
arch/risc-v/src/bl602/bl602_hbn.c
+10 -8
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@@ -36,7 +36,7 @@
* Select uart clock source.
*
* Input Parameters:
* clk_sel: uart clock type selection
* clk_sel: uart clock type selection, 0 for FCLK or 1 for 160MHz CLK
*
* Returned Value:
* Description of the value returned by this function (if any),
@@ -47,12 +47,14 @@
*
****************************************************************************/
void bl602_hbn_set_uart_clk_sel(int clk_sel)
void bl602_set_uart_clk_sel(int clk_sel)
{
uint32_t tmp_val;
tmp_val = getreg32(HBN_BASE + HBN_GLB_OFFSET);
tmp_val &= ~(1 << 2);
tmp_val |= (clk_sel << 2);
putreg32(tmp_val, HBN_BASE + HBN_GLB_OFFSET);
if (clk_sel)
{
modifyreg32(BL602_HBN_GLB, 0, HBN_GLB_HBN_UART_CLK_SEL);
}
else
{
modifyreg32(BL602_HBN_GLB, HBN_GLB_HBN_UART_CLK_SEL, 0);
}
}
arch/risc-v/src/bl602/bl602_hbn.h
+77
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@@ -0,0 +1,77 @@
/****************************************************************************
* arch/risc-v/src/bl602/bl602_hbn.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISCV_SRC_BL602_BL602_HBN_H
#define __ARCH_RISCV_SRC_BL602_BL602_HBN_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
/****************************************************************************
* Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: bl602_hbn_set_uart_clk_sel
*
* Description:
* Select uart clock source.
*
* Input Parameters:
* clk_sel: uart clock type selection, 0 for FCLK or 1 for 160MHz CLK
*
* Returned Value:
* Description of the value returned by this function (if any),
* including an enumeration of all possible error values.
*
* Assumptions/Limitations:
* Anything else that one might need to know to use this function.
*
****************************************************************************/
void bl602_set_uart_clk_sel(int clk_sel);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_RISCV_SRC_BL602_BL602_HBN_H */
arch/risc-v/src/bl602/bl602_irq.c
+5 -5
View File
@@ -36,7 +36,7 @@
#include "riscv_internal.h"
#include "riscv_arch.h"
#include "hardware/clic.h"
#include "hardware/bl602_clic.h"
#include "chip.h"
@@ -46,22 +46,22 @@
static inline void bl_irq_enable(unsigned int source)
{
putreg8(1, CLIC_HART0_ADDR + CLIC_INTIE + source);
putreg8(1, BL602_CLIC_INTIE + source);
}
static inline void bl_irq_disable(unsigned int source)
{
putreg8(0, CLIC_HART0_ADDR + CLIC_INTIE + source);
putreg8(0, BL602_CLIC_INTIE + source);
}
static inline void bl_irq_pending_set(unsigned int source)
{
putreg8(1, CLIC_HART0_ADDR + CLIC_INTIP + source);
putreg8(1, BL602_CLIC_INTIP + source);
}
static inline void bl_irq_pending_clear(unsigned int source)
{
putreg8(0, CLIC_HART0_ADDR + CLIC_INTIP + source);
putreg8(0, BL602_CLIC_INTIP + source);
}
/****************************************************************************
arch/risc-v/src/bl602/bl602_lowputc.c
+111 -183
View File
File diff suppressed because it is too large Load Diff
arch/risc-v/src/bl602/bl602_lowputc.h
+1 -16
View File
@@ -44,10 +44,6 @@ struct uart_config_s
uint8_t data_bits; /* Number of bits per word */
bool stop_bits; /* true=2 stop bits; false=1 stop bit */
uint8_t parity; /* Parity selection: 0=none, 1=odd, 2=even */
uint8_t tx_pin; /* TX pin */
uint8_t rx_pin; /* RX pin */
uint8_t cts_pin; /* CTS pin */
uint8_t rts_pin; /* RTS pin */
};
#undef EXTERN
@@ -59,20 +55,9 @@ extern "C"
#define EXTERN extern
#endif
EXTERN uint32_t bl602_up_serialin(uint32_t reg_base, int offset);
EXTERN void bl602_up_serialout(uint32_t reg_base, int offset,
uint32_t value);
EXTERN void bl602_up_serialmodify(uint32_t reg_base,
int offset,
uint32_t clearbits,
uint32_t setbits);
EXTERN void bl602_lowsetup(void);
EXTERN void bl602_uart_configure(uint32_t base_addr,
const struct uart_config_s *config);
EXTERN void bl602_uart_configure(const struct uart_config_s *config);
#undef EXTERN
#if defined(__cplusplus)
arch/risc-v/src/bl602/bl602_oneshot_lowerhalf.c
+26 -16
View File
@@ -37,6 +37,7 @@
#include "riscv_internal.h"
#include <hardware/bl602_timer.h>
#include "bl602_tim.h"
#include "bl602_oneshot_lowerhalf.h"
/****************************************************************************
@@ -72,7 +73,7 @@ struct bl602_oneshot_lowerhalf_s
oneshot_callback_t callback; /* Internal handler that receives callback */
FAR void * arg; /* Argument that is passed to the handler */
uint8_t tim; /* timer tim 0,1 */
uint8_t irq; /* IRQ associated with this UART */
uint8_t irq; /* IRQ associated with this timer */
bool started; /* True: Timer has been started */
};
@@ -132,18 +133,27 @@ static int bl602_oneshot_handler(int irq, FAR void *context, FAR void *arg)
/* Clear Interrupt Bits */
uint32_t int_id;
uint32_t tmp_val;
uint32_t tmp_addr;
uint32_t ticr_val;
uint32_t ticr_addr;
int_id = getreg32(TIMER_BASE + TIMER_TMSR2_OFFSET + 4 * priv->tim);
tmp_addr = TIMER_BASE + TIMER_TICR2_OFFSET + 4 * priv->tim;
tmp_val = getreg32(tmp_addr);
if (priv->tim == 0)
{
int_id = getreg32(BL602_TIMER_TMSR2);
ticr_addr = BL602_TIMER_TICR2;
}
else
{
int_id = getreg32(BL602_TIMER_TMSR3);
ticr_addr = BL602_TIMER_TICR3;
}
ticr_val = getreg32(ticr_addr);
/* Comparator 0 match interrupt */
if (((int_id) & (1 << (TIMER_TMSR_0_POS))) != 0)
if ((int_id & TIMER_TMSR2_TMSR_0) != 0)
{
putreg32(tmp_val | (1 << TIMER_TCLR_0_POS), tmp_addr);
putreg32(ticr_val | TIMER_TICR2_TCLR_0, ticr_addr);
callback = priv->callback;
cbarg = priv->arg;
@@ -155,16 +165,16 @@ static int bl602_oneshot_handler(int irq, FAR void *context, FAR void *arg)
/* Comparator 1 match interrupt */
if (((int_id) & (1 << (TIMER_TMSR_1_POS))) != 0)
if ((int_id & TIMER_TMSR2_TMSR_1) != 0)
{
putreg32(tmp_val | (1 << TIMER_TCLR_1_POS), tmp_addr);
putreg32(ticr_val | TIMER_TICR2_TCLR_1, ticr_addr);
}
/* Comparator 2 match interrupt */
if (((int_id) & (1 << (TIMER_TMSR_2_POS))) != 0)
if ((int_id & TIMER_TMSR2_TMSR_2) != 0)
{
putreg32(tmp_val | (1 << TIMER_TCLR_2_POS), tmp_addr);
putreg32(ticr_val | TIMER_TICR2_TCLR_2, ticr_addr);
}
return 0;
@@ -353,7 +363,7 @@ FAR struct oneshot_lowerhalf_s *oneshot_initialize(int chan,
uint16_t resolution)
{
FAR struct bl602_oneshot_lowerhalf_s *priv;
timer_cfg_t timstr;
struct timer_cfg_s timstr;
/* Allocate an instance of the lower half driver */
@@ -372,7 +382,7 @@ FAR struct oneshot_lowerhalf_s *oneshot_initialize(int chan,
priv->lh.ops = &g_oneshot_ops;
priv->freq = TIMER_CLK_FREQ / resolution;
priv->tim = chan;
if (priv->tim == 0)
if (priv->tim == TIMER_CH0)
{
priv->irq = BL602_IRQ_TIMER_CH0;
}
@@ -387,12 +397,12 @@ FAR struct oneshot_lowerhalf_s *oneshot_initialize(int chan,
timstr.clk_src = TIMER_CLKSRC_FCLK; /* Timer clock source */
timstr.pl_trig_src =
TIMER_PRELOAD_TRIG_COMP0; /* Timer count register preload trigger source
* slelect */
* select */
timstr.count_mode = TIMER_COUNT_PRELOAD; /* Timer count mode */
timstr.clock_division =
(TIMER_CLK_DIV * resolution) - 1; /* Timer clock divison value */
(TIMER_CLK_DIV * resolution) - 1; /* Timer clock division value */
timstr.match_val0 = TIMER_MAX_VALUE; /* Timer match 0 value 0 */
timstr.match_val1 = TIMER_MAX_VALUE; /* Timer match 1 value 0 */
arch/risc-v/src/bl602/bl602_serial.c
+132 -165
View File
File diff suppressed because it is too large Load Diff
arch/risc-v/src/bl602/bl602_start.c
+7 -12
View File
@@ -64,15 +64,15 @@
static uint8_t g_idle_stack[BL602_IDLESTACK_SIZE];
/* Dont change the name of varaible, since we refer this
/* Dont change the name of variable, since we refer this
* boot2_partition_table in linker script
*/
static struct
{
uint8_t partition_active_idx;
uint8_t pad[3];
struct pt_table_stuff_config_s table;
uint8_t partition_active_idx;
uint8_t pad[3];
struct pt_stuff_config_s table;
} boot2_partition_table;
/****************************************************************************
@@ -98,8 +98,8 @@ uint32_t boot2_get_flash_addr(void)
extern uint8_t __boot2_flash_cfg_src;
return (uint32_t)(&__boot2_flash_cfg_src +
(sizeof(boot2_partition_table.table.pt_entries[0]) *
boot2_partition_table.table.pt_table.entry_cnt));
(sizeof(boot2_partition_table.table.entries[0]) *
boot2_partition_table.table.table.entry_cnt));
}
/****************************************************************************
@@ -108,8 +108,6 @@ uint32_t boot2_get_flash_addr(void)
void bfl_main(void)
{
uint32_t tmp_val;
/* set interrupt vector */
asm volatile("csrw mtvec, %0" ::"r"((uintptr_t)exception_common + 2));
@@ -120,10 +118,7 @@ void bfl_main(void)
/* HBN Config AON pad input and SMT */
tmp_val = getreg32(HBN_BASE + HBN_IRQ_MODE_OFFSET);
tmp_val = (tmp_val & HBN_REG_AON_PAD_IE_SMT_UMSK) |
(1 << HBN_REG_AON_PAD_IE_SMT_POS);
putreg32(tmp_val, HBN_BASE + HBN_IRQ_MODE_OFFSET);
modifyreg32(BL602_HBN_IRQ_MODE, 0, HBN_IRQ_MODE_REG_AON_PAD_IE_SMT);
#ifdef USE_EARLYSERIALINIT
up_earlyserialinit();
arch/risc-v/src/bl602/bl602_tim.c
+96 -222
View File
File diff suppressed because it is too large Load Diff
arch/risc-v/src/bl602/bl602_tim.h
+513
View File
File diff suppressed because it is too large Load Diff
arch/risc-v/src/bl602/bl602_tim_lowerhalf.c
+19 -16
View File
@@ -37,8 +37,10 @@
#include <arch/board/board.h>
#include "riscv_arch.h"
#include <hardware/bl602_glb.h>
#include <hardware/bl602_timer.h>
#include "hardware/bl602_glb.h"
#include "hardware/bl602_timer.h"
#include "bl602_tim_lowerhalf.h"
#include "bl602_glb.h"
/****************************************************************************
* Pre-processor Definitions
@@ -142,15 +144,15 @@ static int bl602_timer_handler(int irq, void *context, void *arg)
uint32_t tmp_val;
uint32_t tmp_addr;
int_id = getreg32(TIMER_BASE + TIMER_TMSR2_OFFSET + 4 * priv->tim);
tmp_addr = TIMER_BASE + TIMER_TICR2_OFFSET + 4 * priv->tim;
int_id = getreg32(BL602_TIMER_TMSR2 + 4 * priv->tim);
tmp_addr = BL602_TIMER_TICR2 + 4 * priv->tim;
tmp_val = getreg32(tmp_addr);
/* Comparator 0 match interrupt */
if (((int_id) & (1 << (TIMER_TMSR_0_POS))) != 0)
if ((int_id & TIMER_TMSR2_TMSR_0) != 0)
{
putreg32(tmp_val | (1 << TIMER_TCLR_0_POS), tmp_addr);
putreg32(tmp_val | TIMER_TMSR2_TMSR_0, tmp_addr);
if (priv->callback(&next_interval_us, priv->arg))
{
if (next_interval_us > 0)
@@ -173,16 +175,16 @@ static int bl602_timer_handler(int irq, void *context, void *arg)
/* Comparator 1 match interrupt */
if (((int_id) & (1 << (TIMER_TMSR_1_POS))) != 0)
if ((int_id & TIMER_TMSR2_TMSR_1) != 0)
{
putreg32(tmp_val | (1 << TIMER_TCLR_1_POS), tmp_addr);
putreg32(tmp_val | TIMER_TICR2_TCLR_1, tmp_addr);
}
/* Comparator 2 match interrupt */
if (((int_id) & (1 << (TIMER_TMSR_2_POS))) != 0)
if ((int_id & TIMER_TMSR2_TMSR_2) != 0)
{
putreg32(tmp_val | (1 << TIMER_TCLR_2_POS), tmp_addr);
putreg32(tmp_val | TIMER_TICR2_TCLR_2, tmp_addr);
}
return OK;
@@ -337,10 +339,11 @@ static int bl602_tim_settimeout(FAR struct timer_lowerhalf_s *lower,
*
* Input Parameters:
* lower - A pointer the publicly visible representation of the
*"lower-half" driver state structure. callback - The new timer expiration
*function pointer. If this function pointer is NULL, then the
*reset-on-expiration behavior is restored, arg - Argument that will be
*provided in the callback
* "lower-half" driver state structure.
* callback - The new timer expiration function pointer. If this function
* pointer is NULL, then the reset-on-expiration behavior is
* restored.
* arg - Argument that will be provided in the callback
*
* Returned Value:
* The previous timer expiration function pointer or NULL is there was
@@ -389,7 +392,7 @@ static void bl602_tim_setcallback(FAR struct timer_lowerhalf_s *lower,
int bl602_timer_initialize(FAR const char *devpath, int timer)
{
FAR struct bl602_tim_lowerhalf_s *lower;
timer_cfg_t timstr;
struct timer_cfg_s timstr;
switch (timer)
{
@@ -420,7 +423,7 @@ int bl602_timer_initialize(FAR const char *devpath, int timer)
timstr.match_val2 = TIMER_MAX_VALUE; /* Timer match 2 value 0 */
timstr.pre_load_val = TIMER_MAX_VALUE; /* Timer preload value */
bl602_glb_ahb_slave1_reset(BL_AHB_SLAVE1_TMR);
bl602_swrst_ahb_slave1(AHB_SLAVE1_TMR);
bl602_timer_intmask(lower->tim, TIMER_INT_ALL, 1);
arch/risc-v/src/bl602/bl602_tim_lowerhalf.h
+3 -2
View File
@@ -27,7 +27,8 @@
#include <nuttx/config.h>
#include <bl602_tim_lowerhalf.h>
#include "bl602_tim_lowerhalf.h"
#include "bl602_tim.h"
/****************************************************************************
* Public Function Prototypes
@@ -37,6 +38,6 @@
* Name: bl602_timer_initialize
****************************************************************************/
int bl602_timer_initialize(FAR const char *devpath, uint8_t timer);
int bl602_timer_initialize(FAR const char *devpath, int timer);
#endif /* __ARCH_RISCV_SRC_BL602_TIM_LOWERHALF_H */
arch/risc-v/src/bl602/bl602_timerisr.c
+5 -5
View File
@@ -31,7 +31,7 @@
#include <nuttx/arch.h>
#include <nuttx/clock.h>
#include <arch/board/board.h>
#include "hardware/bl602_clint.h"
#include "hardware/bl602_clic.h"
#include "riscv_arch.h"
#include "chip.h"
@@ -61,21 +61,21 @@ static bool g_b_tick_started = false;
static inline uint64_t bl602_clint_time_read(void)
{
uint64_t r = getreg32(BL602_MTIMER_HIGH);
uint64_t r = getreg32(BL602_CLIC_MTIME + 4);
r <<= 32;
r |= getreg32(BL602_MTIMER_LOW);
r |= getreg32(BL602_CLIC_MTIME);
return r;
}
static inline uint64_t bl602_clint_time_cmp_read(void)
{
return getreg64(BL602_MTIMER_CMP);
return getreg64(BL602_CLIC_MTIMECMP);
}
static inline void bl602_clint_time_cmp_write(uint64_t v)
{
putreg64(v, BL602_MTIMER_CMP);
putreg64(v, BL602_CLIC_MTIMECMP);
}
/****************************************************************************
arch/risc-v/src/bl602/hardware/bl602_aon.h
+387
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File diff suppressed because it is too large Load Diff
arch/risc-v/src/bl602/hardware/bl602_cci.h
+69
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@@ -0,0 +1,69 @@
/****************************************************************************
* arch/risc-v/src/bl602/hardware/bl602_cci.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_CCI_H
#define __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_CCI_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "bl602_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define BL602_CCI_CFG_OFFSET 0x000000 /* cci_cfg */
#define BL602_CCI_ADDR_OFFSET 0x000004 /* cci_addr */
#define BL602_CCI_WDATA_OFFSET 0x000008 /* cci_wdata */
#define BL602_CCI_RDATA_OFFSET 0x00000c /* cci_rdata */
#define BL602_CCI_CTL_OFFSET 0x000010 /* cci_ctl */
/* Register definitions *****************************************************/
#define BL602_CCI_CFG (BL602_CCI_BASE + BL602_CCI_CFG_OFFSET)
#define BL602_CCI_ADDR (BL602_CCI_BASE + BL602_CCI_ADDR_OFFSET)
#define BL602_CCI_WDATA (BL602_CCI_BASE + BL602_CCI_WDATA_OFFSET)
#define BL602_CCI_RDATA (BL602_CCI_BASE + BL602_CCI_RDATA_OFFSET)
#define BL602_CCI_CTL (BL602_CCI_BASE + BL602_CCI_CTL_OFFSET)
/* Register bit definitions *************************************************/
#define CCI_CFG_REG_MCCI_CLK_INV (1 << 9)
#define CCI_CFG_REG_SCCI_CLK_INV (1 << 8)
#define CCI_CFG_CFG_CCI1_PRE_READ (1 << 7)
#define CCI_CFG_REG_DIV_M_CCI_SCLK_SHIFT (5)
#define CCI_CFG_REG_DIV_M_CCI_SCLK_MASK (0x03 << CCI_CFG_REG_DIV_M_CCI_SCLK_SHIFT)
#define CCI_CFG_REG_M_CCI_SCLK_EN (1 << 4)
#define CCI_CFG_CCI_MAS_HW_MODE (1 << 3)
#define CCI_CFG_CCI_MAS_SEL_CCI2 (1 << 2)
#define CCI_CFG_CCI_SLV_SEL_CCI2 (1 << 1)
#define CCI_CFG_CCI_EN (1 << 0)
#define CCI_CTL_AHB_STATE_SHIFT (2)
#define CCI_CTL_AHB_STATE_MASK (0x03 << CCI_CTL_AHB_STATE_SHIFT)
#define CCI_CTL_CCI_READ_FLAG (1 << 1)
#define CCI_CTL_CCI_WRITE_FLAG (1 << 0)
#endif /* __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_CCI_H */
arch/risc-v/src/bl602/hardware/bl602_cks.h
+56
View File
@@ -0,0 +1,56 @@
/****************************************************************************
* arch/risc-v/src/bl602/hardware/bl602_cks.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_CKS_H
#define __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_CKS_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "bl602_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define BL602_CKS_CONFIG_OFFSET 0x000000 /* cks_config */
#define BL602_CKS_DATA_IN_OFFSET 0x000004 /* data_in */
#define BL602_CKS_OUT_OFFSET 0x000008 /* cks_out */
/* Register definitions *****************************************************/
#define BL602_CKS_CONFIG (BL602_CKS_BASE + BL602_CKS_CONFIG_OFFSET)
#define BL602_CKS_DATA_IN (BL602_CKS_BASE + BL602_CKS_DATA_IN_OFFSET)
#define BL602_CKS_OUT (BL602_CKS_BASE + BL602_CKS_OUT_OFFSET)
/* Register bit definitions *************************************************/
#define CKS_CONFIG_CR_CKS_BYTE_SWAP (1 << 1)
#define CKS_CKS_CONFIG_CR_CKS_CLR (1 << 0)
#define CKS_DATA_IN_MASK (0xff)
#define CKS_OUT_MASK (0xffff)
#endif /* __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_CKS_H */
arch/risc-v/src/bl602/hardware/bl602_clic.h
+57
View File
@@ -0,0 +1,57 @@
/****************************************************************************
* arch/risc-v/src/bl602/hardware/bl602_clic.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_CLIC_H
#define __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_CLIC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "bl602_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define BL602_CLIC_MSIP_OFFSET 0x0000
#define BL602_CLIC_MTIMECMP_OFFSET 0x4000
#define BL602_CLIC_MTIME_OFFSET 0xbff8
#define BL602_CLIC_INTIP_OFFSET 0x000
#define BL602_CLIC_INTIE_OFFSET 0x400
#define BL602_CLIC_INTCFG_OFFSET 0x800
#define BL602_CLIC_CFG_OFFSET 0xc00
/* Register definitions *****************************************************/
#define BL602_CLIC_MSIP (BL602_CLIC_CTRL_BASE + BL602_CLIC_MSIP_OFFSET)
#define BL602_CLIC_MTIMECMP (BL602_CLIC_CTRL_BASE + BL602_CLIC_MTIMECMP_OFFSET)
#define BL602_CLIC_MTIME (BL602_CLIC_CTRL_BASE + BL602_CLIC_MTIME_OFFSET)
#define BL602_CLIC_INTIP (BL602_CLIC_HART0_BASE + BL602_CLIC_INTIP_OFFSET)
#define BL602_CLIC_INTIE (BL602_CLIC_HART0_BASE + BL602_CLIC_INTIE_OFFSET)
#define BL602_CLIC_INTCFG (BL602_CLIC_HART0_BASE + BL602_CLIC_INTCFG_OFFSET)
#define BL602_CLIC_CFG (BL602_CLIC_HART0_BASE + BL602_CLIC_CFG_OFFSET)
#endif /* __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_CLIC_H */
arch/risc-v/src/bl602/hardware/bl602_common.h
-183
View File
@@ -1,183 +0,0 @@
/****************************************************************************
* arch/risc-v/src/bl602/hardware/bl602_common.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_COMMON_H
#define __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_COMMON_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <stdint.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define BL602_FLASH_XIP_BASE (0x23000000)
#define BL602_FLASH_XIP_END (0x23000000 + 16 * 1024 * 1024)
#define BL602_FLASH_XIP_REMAP0_BASE (0x33000000)
#define BL602_FLASH_XIP_REMAP0_END (0x33000000 + 16 * 1024 * 1024)
#define BL602_FLASH_XIP_REMAP1_BASE (0x43000000)
#define BL602_FLASH_XIP_REMAP1_END (0x43000000 + 16 * 1024 * 1024)
#define BL602_FLASH_XIP_REMAP2_BASE (0x53000000)
#define BL602_FLASH_XIP_REMAP2_END (0x53000000 + 16 * 1024 * 1024)
#define BL602_WRAM_BASE (0x42020000)
#define BL602_WRAM_END (0x42020000 + 176 * 1024)
#define BL602_WRAM_REMAP0_BASE (0x22020000)
#define BL602_WRAM_REMAP0_END (0x22020000 + 176 * 1024)
#define BL602_WRAM_REMAP1_BASE (0x32020000)
#define BL602_WRAM_REMAP1_END (0x32020000 + 176 * 1024)
#define BL602_WRAM_REMAP2_BASE (0x52020000)
#define BL602_WRAM_REMAP2_END (0x52020000 + 176 * 1024)
#define BL602_TCM_BASE (0x22008000)
#define BL602_TCM_END (0x22008000 + (96 + 176) * 1024)
#define BL602_TCM_REMAP0_BASE (0x32008000)
#define BL602_TCM_REMAP0_END (0x32008000 + (96 + 176) * 1024)
#define BL602_TCM_REMAP1_BASE (0x42008000)
#define BL602_TCM_REMAP1_END (0x42008000 + (96 + 176) * 1024)
#define BL602_TCM_REMAP2_BASE (0x52008000)
#define BL602_TCM_REMAP2_END (0x52008000 + (96 + 176) * 1024)
/* BL602 peripherals base address */
#define GLB_BASE (0x40000000)
#define RF_BASE (0x40001000)
/* AUX module base address */
#define GPIP_BASE (0x40002000)
/* Security Debug module base address */
#define SEC_DBG_BASE (0x40003000)
/* Security Engine module base address */
#define SEC_ENG_BASE (0x40004000)
/* Trustzone control security base address */
#define TZC_SEC_BASE (0x40005000)
/* Trustzone control none-security base address */
#define TZC_NSEC_BASE (0x40006000)
#define EF_DATA_BASE (0x40007000)
#define EF_CTRL_BASE (0x40007000)
#define CCI_BASE (0x40008000)
/* L1 cache config base address */
#define L1C_BASE (0x40009000)
#define UART0_BASE (0x4000A000)
#define UART1_BASE (0x4000A100)
#define SPI_BASE (0x4000A200)
#define I2C_BASE (0x4000A300)
#define PWM_BASE (0x4000A400)
#define TIMER_BASE (0x4000A500)
#define IR_BASE (0x4000A600)
#define SF_CTRL_BASE (0x4000B000)
#define SF_CTRL_BUF_BASE (0x4000B700)
#define DMA_BASE (0x4000C000)
#define SDU_BASE (0x4000D000)
/* Power down sleep module base address */
#define PDS_BASE (0x4000E000)
/* Hibernate module base address */
#define HBN_BASE (0x4000F000)
/* Always on module base address */
#define AON_BASE (0x4000F000)
#define HBN_RAM_BASE (0x40010000)
/* Delay for a while */
#define BL_DRV_DUMMY() \
{ \
__asm volatile("nop"); \
__asm volatile("nop"); \
__asm volatile("nop"); \
__asm volatile("nop"); \
}
#define BL_AHB_SLAVE1_GLB 0x00
#define BL_AHB_SLAVE1_RF 0x01
#define BL_AHB_SLAVE1_GPIP_PHY_AGC 0x02
#define BL_AHB_SLAVE1_SEC_DBG 0x03
#define BL_AHB_SLAVE1_SEC 0x04
#define BL_AHB_SLAVE1_TZ1 0x05
#define BL_AHB_SLAVE1_TZ2 0x06
#define BL_AHB_SLAVE1_EFUSE 0x07
#define BL_AHB_SLAVE1_CCI 0x08
#define BL_AHB_SLAVE1_L1C 0x09
#define BL_AHB_SLAVE1_RSVD0A 0x0a
#define BL_AHB_SLAVE1_SFC 0x0b
#define BL_AHB_SLAVE1_DMA 0x0c
#define BL_AHB_SLAVE1_SDU 0x0d
#define BL_AHB_SLAVE1_PDS_HBN_AON_HBNRAM 0x0e
#define BL_AHB_SLAVE1_RSVD0F 0x0f
#define BL_AHB_SLAVE1_UART0 0x10
#define BL_AHB_SLAVE1_UART1 0x11
#define BL_AHB_SLAVE1_SPI 0x12
#define BL_AHB_SLAVE1_I2C 0x13
#define BL_AHB_SLAVE1_PWM 0x14
#define BL_AHB_SLAVE1_TMR 0x15
#define BL_AHB_SLAVE1_IRR 0x16
#define BL_AHB_SLAVE1_CKS 0x17
#define BL_AHB_SLAVE1_MAX 0x18
/* Std driver attribute macro */
#define ATTR_CLOCK_SECTION __attribute__((section(".sclock_rlt_code")))
#define ATTR_CLOCK_CONST_SECTION __attribute__((section(".sclock_rlt_const")))
#define ATTR_TCM_SECTION __attribute__((section(".tcm_code")))
#define ATTR_TCM_CONST_SECTION __attribute__((section(".tcm_const")))
#define ATTR_DTCM_SECTION __attribute__((section(".tcm_data")))
#define ATTR_HSRAM_SECTION __attribute__((section(".hsram_code")))
/****************************************************************************
* Public Types
****************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_COMMON_H */
arch/risc-v/src/bl602/hardware/bl602_dma.h
+254
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File diff suppressed because it is too large Load Diff
arch/risc-v/src/bl602/hardware/bl602_ef.h
+372
View File
File diff suppressed because it is too large Load Diff
arch/risc-v/src/bl602/hardware/bl602_glb.h
+820 -4235
View File
File diff suppressed because it is too large Load Diff
arch/risc-v/src/bl602/hardware/bl602_gpio.h
-501
View File
File diff suppressed because it is too large Load Diff
arch/risc-v/src/bl602/hardware/bl602_gpip.h
+105
View File
@@ -0,0 +1,105 @@
/****************************************************************************
* arch/risc-v/src/bl602/hardware/bl602_gpip.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_GPIP_H
#define __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_GPIP_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "bl602_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define BL602_GPADC_CONFIG_OFFSET 0x000000 /* gpadc_config */
#define BL602_GPADC_DMA_RDATA_OFFSET 0x000004 /* gpadc_dma_rdata */
#define BL602_GPDAC_CONFIG_OFFSET 0x000040 /* gpdac_config */
#define BL602_GPDAC_DMA_CONFIG_OFFSET 0x000044 /* gpdac_dma_config */
#define BL602_GPDAC_DMA_WDATA_OFFSET 0x000048 /* gpdac_dma_wdata */
#define BL602_GPDAC_TX_FIFO_STATUS_OFFSET 0x00004c /* gpdac_tx_fifo_status */
/* Register definitions *****************************************************/
#define BL602_GPADC_CONFIG (BL602_GPIP_BASE + BL602_GPADC_CONFIG_OFFSET)
#define BL602_GPADC_DMA_RDATA (BL602_GPIP_BASE + BL602_GPADC_DMA_RDATA_OFFSET)
#define BL602_GPDAC_CONFIG (BL602_GPIP_BASE + BL602_GPDAC_CONFIG_OFFSET)
#define BL602_GPDAC_DMA_CONFIG (BL602_GPIP_BASE + BL602_GPDAC_DMA_CONFIG_OFFSET)
#define BL602_GPDAC_DMA_WDATA (BL602_GPIP_BASE + BL602_GPDAC_DMA_WDATA_OFFSET)
#define BL602_GPDAC_TX_FIFO_STATUS (BL602_GPIP_BASE + BL602_GPDAC_TX_FIFO_STATUS_OFFSET)
/* Register bit definitions *************************************************/
#define GPADC_CONFIG_RSVD_31_24_SHIFT (24)
#define GPADC_CONFIG_RSVD_31_24_MASK (0xff << GPADC_CONFIG_RSVD_31_24_SHIFT)
#define GPADC_CONFIG_GPADC_FIFO_THL_SHIFT (22)
#define GPADC_CONFIG_GPADC_FIFO_THL_MASK (0x03 << GPADC_CONFIG_GPADC_FIFO_THL_SHIFT)
#define GPADC_CONFIG_GPADC_FIFO_DATA_COUNT_SHIFT (16)
#define GPADC_CONFIG_GPADC_FIFO_DATA_COUNT_MASK (0x3f << GPADC_CONFIG_GPADC_FIFO_DATA_COUNT_SHIFT)
#define GPADC_CONFIG_GPADC_FIFO_UNDERRUN_MASK (1 << 14)
#define GPADC_CONFIG_GPADC_FIFO_OVERRUN_MASK (1 << 13)
#define GPADC_CONFIG_GPADC_RDY_MASK (1 << 12)
#define GPADC_CONFIG_GPADC_FIFO_UNDERRUN_CLR (1 << 10)
#define GPADC_CONFIG_GPADC_FIFO_OVERRUN_CLR (1 << 9)
#define GPADC_CONFIG_GPADC_RDY_CLR (1 << 8)
#define GPADC_CONFIG_GPADC_FIFO_UNDERRUN (1 << 6)
#define GPADC_CONFIG_GPADC_FIFO_OVERRUN (1 << 5)
#define GPADC_CONFIG_GPADC_RDY (1 << 4)
#define GPADC_CONFIG_GPADC_FIFO_FULL (1 << 3)
#define GPADC_CONFIG_GPADC_FIFO_NE (1 << 2)
#define GPADC_CONFIG_GPADC_FIFO_CLR (1 << 1)
#define GPADC_CONFIG_GPADC_DMA_EN (1 << 0)
#define GPADC_DMA_RDATA_RSVD_31_26_SHIFT (26)
#define GPADC_DMA_RDATA_RSVD_31_26_MASK (0x3f << GPADC_DMA_RDATA_RSVD_31_26_SHIFT)
#define GPADC_DMA_RDATA_MASK (0x3ffffff)
#define GPDAC_CONFIG_RSVD_31_24_SHIFT (24)
#define GPDAC_CONFIG_RSVD_31_24_MASK (0xff << GPDAC_CONFIG_RSVD_31_24_SHIFT)
#define GPDAC_CONFIG_GPDAC_CH_B_SEL_SHIFT (20)
#define GPDAC_CONFIG_GPDAC_CH_B_SEL_MASK (0x0f << GPDAC_CONFIG_GPDAC_CH_B_SEL_SHIFT)
#define GPDAC_CONFIG_GPDAC_CH_A_SEL_SHIFT (16)
#define GPDAC_CONFIG_GPDAC_CH_A_SEL_MASK (0x0f << GPDAC_CONFIG_GPDAC_CH_A_SEL_SHIFT)
#define GPDAC_CONFIG_GPDAC_MODE_SHIFT (8)
#define GPDAC_CONFIG_GPDAC_MODE_MASK (0x07 << GPDAC_CONFIG_GPDAC_MODE_SHIFT)
#define GPDAC_CONFIG_DSM_MODE_SHIFT (4)
#define GPDAC_CONFIG_DSM_MODE_MASK (0x03 << GPDAC_CONFIG_DSM_MODE_SHIFT)
#define GPDAC_CONFIG_GPDAC_EN2 (1 << 1)
#define GPDAC_CONFIG_GPDAC_EN (1 << 0)
#define GPDAC_DMA_CONFIG_GPDAC_DMA_FORMAT_SHIFT (4)
#define GPDAC_DMA_CONFIG_GPDAC_DMA_FORMAT_MASK (0x03 << GPDAC_DMA_CONFIG_GPDAC_DMA_FORMAT_SHIFT)
#define GPDAC_DMA_CONFIG_GPDAC_DMA_TX_EN (1 << 0)
#define GPDAC_TX_FIFO_STATUS_TXFIFOWRPTR_SHIFT (8)
#define GPDAC_TX_FIFO_STATUS_TXFIFOWRPTR_MASK (0x03 << GPDAC_TX_FIFO_STATUS_TXFIFOWRPTR_SHIFT)
#define GPDAC_TX_FIFO_STATUS_TXFIFORDPTR_SHIFT (4)
#define GPDAC_TX_FIFO_STATUS_TXFIFORDPTR_MASK (0x07 << GPDAC_TX_FIFO_STATUS_TXFIFORDPTR_SHIFT)
#define GPDAC_TX_FIFO_STATUS_TX_CS_SHIFT (2)
#define GPDAC_TX_FIFO_STATUS_TX_CS_MASK (0x03 << GPDAC_TX_FIFO_STATUS_TX_CS_SHIFT)
#define GPDAC_TX_FIFO_STATUS_TX_FIFO_FULL (1 << 1)
#define GPDAC_TX_FIFO_STATUS_TX_FIFO_EMPTY (1 << 0)
#endif /* __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_GPIP_H */
arch/risc-v/src/bl602/hardware/bl602_hbn.h
+135 -634
View File
File diff suppressed because it is too large Load Diff
arch/risc-v/src/bl602/hardware/bl602_i2c.h
+154
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@@ -0,0 +1,154 @@
/****************************************************************************
* arch/risc-v/src/bl602/hardware/bl602_i2c.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_I2C_H
#define __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_I2C_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "bl602_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define BL602_I2C_CONFIG_OFFSET 0x000000 /* i2c_config */
#define BL602_I2C_INT_STS_OFFSET 0x000004 /* i2c_int_sts */
#define BL602_I2C_SUB_ADDR_OFFSET 0x000008 /* i2c_sub_addr */
#define BL602_I2C_BUS_BUSY_OFFSET 0x00000c /* i2c_bus_busy */
#define BL602_I2C_PRD_START_OFFSET 0x000010 /* i2c_prd_start */
#define BL602_I2C_PRD_STOP_OFFSET 0x000014 /* i2c_prd_stop */
#define BL602_I2C_PRD_DATA_OFFSET 0x000018 /* i2c_prd_data */
#define BL602_I2C_FIFO_CONFIG_0_OFFSET 0x000080 /* i2c_fifo_config_0 */
#define BL602_I2C_FIFO_CONFIG_1_OFFSET 0x000084 /* i2c_fifo_config_1 */
#define BL602_I2C_FIFO_WDATA_OFFSET 0x000088 /* i2c_fifo_wdata */
#define BL602_I2C_FIFO_RDATA_OFFSET 0x00008c /* i2c_fifo_rdata */
/* Register definitions *****************************************************/
#define BL602_I2C_CONFIG (BL602_I2C_BASE + BL602_I2C_CONFIG_OFFSET)
#define BL602_I2C_INT_STS (BL602_I2C_BASE + BL602_I2C_INT_STS_OFFSET)
#define BL602_I2C_SUB_ADDR (BL602_I2C_BASE + BL602_I2C_SUB_ADDR_OFFSET)
#define BL602_I2C_BUS_BUSY (BL602_I2C_BASE + BL602_I2C_BUS_BUSY_OFFSET)
#define BL602_I2C_PRD_START (BL602_I2C_BASE + BL602_I2C_PRD_START_OFFSET)
#define BL602_I2C_PRD_STOP (BL602_I2C_BASE + BL602_I2C_PRD_STOP_OFFSET)
#define BL602_I2C_PRD_DATA (BL602_I2C_BASE + BL602_I2C_PRD_DATA_OFFSET)
#define BL602_I2C_FIFO_CONFIG_0 (BL602_I2C_BASE + BL602_I2C_FIFO_CONFIG_0_OFFSET)
#define BL602_I2C_FIFO_CONFIG_1 (BL602_I2C_BASE + BL602_I2C_FIFO_CONFIG_1_OFFSET)
#define BL602_I2C_FIFO_WDATA (BL602_I2C_BASE + BL602_I2C_FIFO_WDATA_OFFSET)
#define BL602_I2C_FIFO_RDATA (BL602_I2C_BASE + BL602_I2C_FIFO_RDATA_OFFSET)
/* Register bit definitions *************************************************/
#define I2C_CONFIG_CR_I2C_DEG_CNT_SHIFT (28)
#define I2C_CONFIG_CR_I2C_DEG_CNT_MASK (0x0f << I2C_CONFIG_CR_I2C_DEG_CNT_SHIFT)
#define I2C_CONFIG_CR_I2C_PKT_LEN_SHIFT (16)
#define I2C_CONFIG_CR_I2C_PKT_LEN_MASK (0xff << I2C_CONFIG_CR_I2C_PKT_LEN_SHIFT)
#define I2C_CONFIG_CR_I2C_SLV_ADDR_SHIFT (8)
#define I2C_CONFIG_CR_I2C_SLV_ADDR_MASK (0x7f << I2C_CONFIG_CR_I2C_SLV_ADDR_SHIFT)
#define I2C_CONFIG_CR_I2C_SUB_ADDR_BC_SHIFT (5)
#define I2C_CONFIG_CR_I2C_SUB_ADDR_BC_MASK (0x03 << I2C_CONFIG_CR_I2C_SUB_ADDR_BC_SHIFT)
#define I2C_CONFIG_CR_I2C_SUB_ADDR_EN (1 << 4)
#define I2C_CONFIG_CR_I2C_SCL_SYNC_EN (1 << 3)
#define I2C_CONFIG_CR_I2C_DEG_EN (1 << 2)
#define I2C_CONFIG_CR_I2C_PKT_DIR (1 << 1)
#define I2C_CONFIG_CR_I2C_M_EN (1 << 0)
#define I2C_INT_STS_CR_FER_EN (1 << 29)
#define I2C_INT_STS_CR_ARB_EN (1 << 28)
#define I2C_INT_STS_CR_NAK_EN (1 << 27)
#define I2C_INT_STS_CR_RXF_EN (1 << 26)
#define I2C_INT_STS_CR_TXF_EN (1 << 25)
#define I2C_INT_STS_CR_END_EN (1 << 24)
#define I2C_INT_STS_RSVD_21 (1 << 21)
#define I2C_INT_STS_CR_ARB_CLR (1 << 20)
#define I2C_INT_STS_CR_NAK_CLR (1 << 19)
#define I2C_INT_STS_RSVD_18 (1 << 18)
#define I2C_INT_STS_RSVD_17 (1 << 17)
#define I2C_INT_STS_CR_END_CLR (1 << 16)
#define I2C_INT_STS_CR_FER_MASK (1 << 13)
#define I2C_INT_STS_CR_ARB_MASK (1 << 12)
#define I2C_INT_STS_CR_NAK_MASK (1 << 11)
#define I2C_INT_STS_CR_RXF_MASK (1 << 10)
#define I2C_INT_STS_CR_TXF_MASK (1 << 9)
#define I2C_INT_STS_CR_END_MASK (1 << 8)
#define I2C_INT_STS_FER_INT (1 << 5)
#define I2C_INT_STS_ARB_INT (1 << 4)
#define I2C_INT_STS_NAK_INT (1 << 3)
#define I2C_INT_STS_RXF_INT (1 << 2)
#define I2C_INT_STS_TXF_INT (1 << 1)
#define I2C_INT_STS_END_INT (1 << 0)
#define I2C_SUB_ADDR_CR_SUB_ADDR_B3_SHIFT (24)
#define I2C_SUB_ADDR_CR_SUB_ADDR_B3_MASK (0xff << I2C_SUB_ADDR_CR_SUB_ADDR_B3_SHIFT)
#define I2C_SUB_ADDR_CR_SUB_ADDR_B2_SHIFT (16)
#define I2C_SUB_ADDR_CR_SUB_ADDR_B2_MASK (0xff << I2C_SUB_ADDR_CR_SUB_ADDR_B2_SHIFT)
#define I2C_SUB_ADDR_CR_SUB_ADDR_B1_SHIFT (8)
#define I2C_SUB_ADDR_CR_SUB_ADDR_B1_MASK (0xff << I2C_SUB_ADDR_CR_SUB_ADDR_B1_SHIFT)
#define I2C_SUB_ADDR_CR_SUB_ADDR_B0_MASK (0xff)
#define I2C_BUS_BUSY_CR_BUS_BUSY_CLR (1 << 1)
#define I2C_BUS_BUSY_STS_BUS_BUSY (1 << 0)
#define I2C_PRD_START_CR_PRD_S_PH_3_SHIFT (24)
#define I2C_PRD_START_CR_PRD_S_PH_3_MASK (0xff << I2C_PRD_START_CR_PRD_S_PH_3_SHIFT)
#define I2C_PRD_START_CR_PRD_S_PH_2_SHIFT (16)
#define I2C_PRD_START_CR_PRD_S_PH_2_MASK (0xff << I2C_PRD_START_CR_PRD_S_PH_2_SHIFT)
#define I2C_PRD_START_CR_PRD_S_PH_1_SHIFT (8)
#define I2C_PRD_START_CR_PRD_S_PH_1_MASK (0xff << I2C_PRD_START_CR_PRD_S_PH_1_SHIFT)
#define I2C_PRD_START_CR_PRD_S_PH_0_MASK (0xff)
#define I2C_PRD_STOP_CR_PRD_P_PH_3_SHIFT (24)
#define I2C_PRD_STOP_CR_PRD_P_PH_3_MASK (0xff << I2C_PRD_STOP_CR_PRD_P_PH_3_SHIFT)
#define I2C_PRD_STOP_CR_PRD_P_PH_2_SHIFT (16)
#define I2C_PRD_STOP_CR_PRD_P_PH_2_MASK (0xff << I2C_PRD_STOP_CR_PRD_P_PH_2_SHIFT)
#define I2C_PRD_STOP_CR_PRD_P_PH_1_SHIFT (8)
#define I2C_PRD_STOP_CR_PRD_P_PH_1_MASK (0xff << I2C_PRD_STOP_CR_PRD_P_PH_1_SHIFT)
#define I2C_PRD_STOP_CR_PRD_P_PH_0_MASK (0xff)
#define I2C_PRD_DATA_CR_PRD_D_PH_3_SHIFT (24)
#define I2C_PRD_DATA_CR_PRD_D_PH_3_MASK (0xff << I2C_PRD_DATA_CR_PRD_D_PH_3_SHIFT)
#define I2C_PRD_DATA_CR_PRD_D_PH_2_SHIFT (16)
#define I2C_PRD_DATA_CR_PRD_D_PH_2_MASK (0xff << I2C_PRD_DATA_CR_PRD_D_PH_2_SHIFT)
#define I2C_PRD_DATA_CR_PRD_D_PH_1_SHIFT (8)
#define I2C_PRD_DATA_CR_PRD_D_PH_1_MASK (0xff << I2C_PRD_DATA_CR_PRD_D_PH_1_SHIFT)
#define I2C_PRD_DATA_CR_PRD_D_PH_0_MASK (0xff)
#define I2C_FIFO_CONFIG_0_RX_FIFO_UNDERFLOW (1 << 7)
#define I2C_FIFO_CONFIG_0_RX_FIFO_OVERFLOW (1 << 6)
#define I2C_FIFO_CONFIG_0_TX_FIFO_UNDERFLOW (1 << 5)
#define I2C_FIFO_CONFIG_0_TX_FIFO_OVERFLOW (1 << 4)
#define I2C_FIFO_CONFIG_0_RX_FIFO_CLR (1 << 3)
#define I2C_FIFO_CONFIG_0_TX_FIFO_CLR (1 << 2)
#define I2C_FIFO_CONFIG_0_DMA_RX_EN (1 << 1)
#define I2C_FIFO_CONFIG_0_DMA_TX_EN (1 << 0)
#define I2C_FIFO_CONFIG_1_RX_FIFO_TH (1 << 24)
#define I2C_FIFO_CONFIG_1_TX_FIFO_TH (1 << 16)
#define I2C_FIFO_CONFIG_1_RX_FIFO_CNT_SHIFT (8)
#define I2C_FIFO_CONFIG_1_RX_FIFO_CNT_MASK (0x03 << I2C_FIFO_CONFIG_1_RX_FIFO_CNT_SHIFT)
#define I2C_FIFO_CONFIG_1_TX_FIFO_CNT_MASK (0x03)
#endif /* __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_I2C_H */
arch/risc-v/src/bl602/hardware/bl602_ir.h
+155
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@@ -0,0 +1,155 @@
/****************************************************************************
* arch/risc-v/src/bl602/hardware/bl602_sec.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_IR_H
#define __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_IR_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "bl602_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define BL602_IRTX_CONFIG_OFFSET 0x000000 /* irtx_config */
#define BL602_IRTX_INT_STS_OFFSET 0x000004 /* irtx_int_sts */
#define BL602_IRTX_DATA_WORD0_OFFSET 0x000008 /* irtx_data_word0 */
#define BL602_IRTX_DATA_WORD1_OFFSET 0x00000c /* irtx_data_word1 */
#define BL602_IRTX_PULSE_WIDTH_OFFSET 0x000010 /* irtx_pulse_width */
#define BL602_IRTX_PW_OFFSET 0x000014 /* irtx_pw */
#define BL602_IRTX_SWM_PW_0_OFFSET 0x000040 /* irtx_swm_pw_0 */
#define BL602_IRTX_SWM_PW_1_OFFSET 0x000044 /* irtx_swm_pw_1 */
#define BL602_IRTX_SWM_PW_2_OFFSET 0x000048 /* irtx_swm_pw_2 */
#define BL602_IRTX_SWM_PW_3_OFFSET 0x00004c /* irtx_swm_pw_3 */
#define BL602_IRTX_SWM_PW_4_OFFSET 0x000050 /* irtx_swm_pw_4 */
#define BL602_IRTX_SWM_PW_5_OFFSET 0x000054 /* irtx_swm_pw_5 */
#define BL602_IRTX_SWM_PW_6_OFFSET 0x000058 /* irtx_swm_pw_6 */
#define BL602_IRTX_SWM_PW_7_OFFSET 0x00005c /* irtx_swm_pw_7 */
#define BL602_IRRX_CONFIG_OFFSET 0x000080 /* irrx_config */
#define BL602_IRRX_INT_STS_OFFSET 0x000084 /* irrx_int_sts */
#define BL602_IRRX_PW_CONFIG_OFFSET 0x000088 /* irrx_pw_config */
#define BL602_IRRX_DATA_COUNT_OFFSET 0x000090 /* irrx_data_count */
#define BL602_IRRX_DATA_WORD0_OFFSET 0x000094 /* irrx_data_word0 */
#define BL602_IRRX_DATA_WORD1_OFFSET 0x000098 /* irrx_data_word1 */
#define BL602_IRRX_SWM_FIFO_CONFIG_0_OFFSET 0x0000c0 /* irrx_swm_fifo_config_0 */
#define BL602_IRRX_SWM_FIFO_RDATA_OFFSET 0x0000c4 /* irrx_swm_fifo_rdata */
/* Register definitions *****************************************************/
#define BL602_IRTX_CONFIG (BL602_IR_BASE + BL602_IRTX_CONFIG_OFFSET)
#define BL602_IRTX_INT_STS (BL602_IR_BASE + BL602_IRTX_INT_STS_OFFSET)
#define BL602_IRTX_DATA_WORD0 (BL602_IR_BASE + BL602_IRTX_DATA_WORD0_OFFSET)
#define BL602_IRTX_DATA_WORD1 (BL602_IR_BASE + BL602_IRTX_DATA_WORD1_OFFSET)
#define BL602_IRTX_PULSE_WIDTH (BL602_IR_BASE + BL602_IRTX_PULSE_WIDTH_OFFSET)
#define BL602_IRTX_PW (BL602_IR_BASE + BL602_IRTX_PW_OFFSET)
#define BL602_IRTX_SWM_PW_0 (BL602_IR_BASE + BL602_IRTX_SWM_PW_0_OFFSET)
#define BL602_IRTX_SWM_PW_1 (BL602_IR_BASE + BL602_IRTX_SWM_PW_1_OFFSET)
#define BL602_IRTX_SWM_PW_2 (BL602_IR_BASE + BL602_IRTX_SWM_PW_2_OFFSET)
#define BL602_IRTX_SWM_PW_3 (BL602_IR_BASE + BL602_IRTX_SWM_PW_3_OFFSET)
#define BL602_IRTX_SWM_PW_4 (BL602_IR_BASE + BL602_IRTX_SWM_PW_4_OFFSET)
#define BL602_IRTX_SWM_PW_5 (BL602_IR_BASE + BL602_IRTX_SWM_PW_5_OFFSET)
#define BL602_IRTX_SWM_PW_6 (BL602_IR_BASE + BL602_IRTX_SWM_PW_6_OFFSET)
#define BL602_IRTX_SWM_PW_7 (BL602_IR_BASE + BL602_IRTX_SWM_PW_7_OFFSET)
#define BL602_IRRX_CONFIG (BL602_IR_BASE + BL602_IRRX_CONFIG_OFFSET)
#define BL602_IRRX_INT_STS (BL602_IR_BASE + BL602_IRRX_INT_STS_OFFSET)
#define BL602_IRRX_PW_CONFIG (BL602_IR_BASE + BL602_IRRX_PW_CONFIG_OFFSET)
#define BL602_IRRX_DATA_COUNT (BL602_IR_BASE + BL602_IRRX_DATA_COUNT_OFFSET)
#define BL602_IRRX_DATA_WORD0 (BL602_IR_BASE + BL602_IRRX_DATA_WORD0_OFFSET)
#define BL602_IRRX_DATA_WORD1 (BL602_IR_BASE + BL602_IRRX_DATA_WORD1_OFFSET)
#define BL602_IRRX_SWM_FIFO_CONFIG_0 (BL602_IR_BASE + BL602_IRRX_SWM_FIFO_CONFIG_0_OFFSET)
#define BL602_IRRX_SWM_FIFO_RDATA (BL602_IR_BASE + BL602_IRRX_SWM_FIFO_RDATA_OFFSET)
/* Register bit definitions *************************************************/
#define IRTX_CONFIG_CR_DATA_NUM_SHIFT (12)
#define IRTX_CONFIG_CR_DATA_NUM_MASK (0x3f << IRTX_CONFIG_CR_DATA_NUM_SHIFT)
#define IRTX_CONFIG_CR_TAIL_HL_INV (1 << 11)
#define IRTX_CONFIG_CR_TAIL_EN (1 << 10)
#define IRTX_CONFIG_CR_HEAD_HL_INV (1 << 9)
#define IRTX_CONFIG_CR_HEAD_EN (1 << 8)
#define IRTX_CONFIG_CR_LOGIC1_HL_INV (1 << 6)
#define IRTX_CONFIG_CR_LOGIC0_HL_INV (1 << 5)
#define IRTX_CONFIG_CR_DATA_EN (1 << 4)
#define IRTX_CONFIG_CR_SWM_EN (1 << 3)
#define IRTX_CONFIG_CR_MOD_EN (1 << 2)
#define IRTX_CONFIG_CR_OUT_INV (1 << 1)
#define IRTX_CONFIG_CR_EN (1 << 0)
#define IRTX_INT_STS_CR_END_EN (1 << 24)
#define IRTX_INT_STS_CR_END_CLR (1 << 16)
#define IRTX_INT_STS_CR_END_MASK (1 << 8)
#define IRTX_INT_STS_END_INT (1 << 0)
#define IRTX_PULSE_WIDTH_CR_MOD_PH1_W_SHIFT (24)
#define IRTX_PULSE_WIDTH_CR_MOD_PH1_W_MASK (0xff << IRTX_PULSE_WIDTH_CR_MOD_PH1_W_SHIFT)
#define IRTX_PULSE_WIDTH_CR_MOD_PH0_W_SHIFT (16)
#define IRTX_PULSE_WIDTH_CR_MOD_PH0_W_MASK (0xff << IRTX_PULSE_WIDTH_CR_MOD_PH0_W_SHIFT)
#define IRTX_PULSE_WIDTH_CR_PW_UNIT_MASK (0xfff)
#define IRTX_PW_CR_TAIL_PH1_W_SHIFT (28)
#define IRTX_PW_CR_TAIL_PH1_W_MASK (0x0f << IRTX_PW_CR_TAIL_PH1_W_SHIFT)
#define IRTX_PW_CR_TAIL_PH0_W_SHIFT (24)
#define IRTX_PW_CR_TAIL_PH0_W_MASK (0x0f << IRTX_PW_CR_TAIL_PH0_W_SHIFT)
#define IRTX_PW_CR_HEAD_PH1_W_SHIFT (20)
#define IRTX_PW_CR_HEAD_PH1_W_MASK (0x0f << IRTX_PW_CR_HEAD_PH1_W_SHIFT)
#define IRTX_PW_CR_HEAD_PH0_W_SHIFT (16)
#define IRTX_PW_CR_HEAD_PH0_W_MASK (0x0f << IRTX_PW_CR_HEAD_PH0_W_SHIFT)
#define IRTX_PW_CR_LOGIC1_PH1_W_SHIFT (12)
#define IRTX_PW_CR_LOGIC1_PH1_W_MASK (0x0f << IRTX_PW_CR_LOGIC1_PH1_W_SHIFT)
#define IRTX_PW_CR_LOGIC1_PH0_W_SHIFT (8)
#define IRTX_PW_CR_LOGIC1_PH0_W_MASK (0x0f << IRTX_PW_CR_LOGIC1_PH0_W_SHIFT)
#define IRTX_PW_CR_LOGIC0_PH1_W_SHIFT (4)
#define IRTX_PW_CR_LOGIC0_PH1_W_MASK (0x0f << IRTX_PW_CR_LOGIC0_PH1_W_SHIFT)
#define IRTX_PW_CR_LOGIC0_PH0_W_MASK (0x0f)
#define IRRX_CONFIG_CR_DEG_CNT_SHIFT (8)
#define IRRX_CONFIG_CR_DEG_CNT_MASK (0x0f << IRRX_CONFIG_CR_DEG_CNT_SHIFT)
#define IRRX_CONFIG_CR_DEG_EN (1 << 4)
#define IRRX_CONFIG_CR_MODE_SHIFT (2)
#define IRRX_CONFIG_CR_MODE_MASK (0x03 << IRRX_CONFIG_CR_MODE_SHIFT)
#define IRRX_CONFIG_CR_IN_INV (1 << 1)
#define IRRX_CONFIG_CR_EN (1 << 0)
#define IRRX_INT_STS_CR_END_EN (1 << 24)
#define IRRX_INT_STS_CR_END_CLR (1 << 16)
#define IRRX_INT_STS_CR_END_MASK (1 << 8)
#define IRRX_INT_STS_END_INT (1 << 0)
#define IRRX_PW_CONFIG_CR_END_TH_SHIFT (16)
#define IRRX_PW_CONFIG_CR_END_TH_MASK (0xffff << IRRX_PW_CONFIG_CR_END_TH_SHIFT)
#define IRRX_PW_CONFIG_CR_DATA_TH_MASK (0xffff)
#define IRRX_DATA_COUNT_STS_DATA_CNT_MASK (0x7f)
#define IRRX_SWM_FIFO_CONFIG_0_RX_FIFO_CNT_SHIFT (4)
#define IRRX_SWM_FIFO_CONFIG_0_RX_FIFO_CNT_MASK (0x7f << IRRX_SWM_FIFO_CONFIG_0_RX_FIFO_CNT_SHIFT)
#define IRRX_SWM_FIFO_CONFIG_0_RX_FIFO_UNDERFLOW (1 << 3)
#define IRRX_SWM_FIFO_CONFIG_0_RX_FIFO_OVERFLOW (1 << 2)
#define IRRX_SWM_FIFO_CONFIG_0_RX_FIFO_CLR (1 << 0)
#define IRRX_SWM_FIFO_RDATA_RX_FIFO_RDATA_MASK (0xffff)
#endif /* __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_IR_H */
arch/risc-v/src/bl602/hardware/bl602_l1c.h
+90
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@@ -0,0 +1,90 @@
/****************************************************************************
* arch/risc-v/src/bl602/hardware/bl602_l1c.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_L1C_H
#define __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_L1C_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "bl602_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define BL602_L1C_CONFIG_OFFSET 0x000000 /* l1c_config */
#define BL602_L1C_HIT_CNT_LSB_OFFSET 0x000004 /* hit_cnt_lsb */
#define BL602_L1C_HIT_CNT_MSB_OFFSET 0x000008 /* hit_cnt_msb */
#define BL602_L1C_MISS_CNT_OFFSET 0x00000c /* miss_cnt */
#define BL602_L1C_RANGE_OFFSET 0x000010 /* l1c_range */
#define BL602_L1C_BMX_ERR_ADDR_EN_OFFSET 0x000200 /* l1c_bmx_err_addr_en */
#define BL602_L1C_BMX_ERR_ADDR_OFFSET 0x000204 /* l1c_bmx_err_addr */
#define BL602_L1C_IROM1_MISR_DATAOUT_0_OFFSET 0x000208 /* irom1_misr_dataout_0 */
#define BL602_L1C_IROM1_MISR_DATAOUT_1_OFFSET 0x00020c /* irom1_misr_dataout_1 */
#define BL602_L1C_CPU_CLK_GATE_OFFSET 0x000210 /* cpu_clk_gate */
/* Register definitions *****************************************************/
#define BL602_L1C_CONFIG (BL602_L1C_BASE + BL602_L1C_CONFIG_OFFSET)
#define BL602_L1C_HIT_CNT_LSB (BL602_L1C_BASE + BL602_L1C_HIT_CNT_LSB_OFFSET)
#define BL602_L1C_HIT_CNT_MSB (BL602_L1C_BASE + BL602_L1C_HIT_CNT_MSB_OFFSET)
#define BL602_L1C_MISS_CNT (BL602_L1C_BASE + BL602_L1C_MISS_CNT_OFFSET)
#define BL602_L1C_RANGE (BL602_L1C_BASE + BL602_L1C_RANGE_OFFSET)
#define BL602_L1C_BMX_ERR_ADDR_EN (BL602_L1C_BASE + BL602_L1C_BMX_ERR_ADDR_EN_OFFSET)
#define BL602_L1C_BMX_ERR_ADDR (BL602_L1C_BASE + BL602_L1C_BMX_ERR_ADDR_OFFSET)
#define BL602_L1C_IROM1_MISR_DATAOUT_0 (BL602_L1C_BASE + BL602_L1C_IROM1_MISR_DATAOUT_0_OFFSET)
#define BL602_L1C_IROM1_MISR_DATAOUT_1 (BL602_L1C_BASE + BL602_L1C_IROM1_MISR_DATAOUT_1_OFFSET)
#define BL602_L1C_CPU_CLK_GATE (BL602_L1C_BASE + BL602_L1C_CPU_CLK_GATE_OFFSET)
/* Register bit definitions *************************************************/
#define L1C_CONFIG_WRAP_DIS (1 << 26)
#define L1C_CONFIG_EARLY_RESP_DIS (1 << 25)
#define L1C_CONFIG_BMX_BUSY_OPTION_DIS (1 << 24)
#define L1C_CONFIG_BMX_TIMEOUT_EN_SHIFT (20)
#define L1C_CONFIG_BMX_TIMEOUT_EN_MASK (0x0f << L1C_CONFIG_BMX_TIMEOUT_EN_SHIFT)
#define L1C_CONFIG_BMX_ARB_MODE_SHIFT (16)
#define L1C_CONFIG_BMX_ARB_MODE_MASK (0x03 << L1C_CONFIG_BMX_ARB_MODE_SHIFT)
#define L1C_CONFIG_BMX_ERR_EN (1 << 15)
#define L1C_CONFIG_BYPASS (1 << 14)
#define L1C_CONFIG_IROM_2T_ACCESS (1 << 12)
#define L1C_CONFIG_WAY_DIS_SHIFT (8)
#define L1C_CONFIG_WAY_DIS_MASK (0x0f << L1C_CONFIG_WAY_DIS_SHIFT)
#define L1C_CONFIG_INVALID_DONE (1 << 3)
#define L1C_CONFIG_INVALID_EN (1 << 2)
#define L1C_CONFIG_CNT_EN (1 << 1)
#define L1C_CONFIG_CACHEABLE (1 << 0)
#define L1C_BMX_ERR_ADDR_EN_HSEL_OPTION_SHIFT (16)
#define L1C_BMX_ERR_ADDR_EN_HSEL_OPTION_MASK (0x0f << L1C_BMX_ERR_ADDR_EN_HSEL_OPTION_SHIFT)
#define L1C_BMX_ERR_ADDR_EN_BMX_ERR_TZ (1 << 5)
#define L1C_BMX_ERR_ADDR_EN_BMX_ERR_DEC (1 << 4)
#define L1C_BMX_ERR_ADDR_EN_BMX_ERR_ADDR_DIS (1 << 0)
#define L1C_CPU_CLK_GATE_FORCE_E21_CLOCK_ON_2 (1 << 2)
#define L1C_CPU_CLK_GATE_FORCE_E21_CLOCK_ON_1 (1 << 1)
#define L1C_CPU_CLK_GATE_FORCE_E21_CLOCK_ON_0 (1 << 0)
#endif /* __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_L1C_H */
arch/risc-v/src/bl602/hardware/bl602_memorymap.h
+60
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/****************************************************************************
* arch/risc-v/src/bl602/hardware/bl602_memorymap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_MEMORYMAP_H
#define __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_MEMORYMAP_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define BL602_CLIC_CTRL_BASE 0x02000000 /* clic */
#define BL602_CLIC_HART0_BASE 0x02800000 /* clic hart0 */
#define BL602_GLB_BASE 0x40000000 /* glb */
#define BL602_RF_BASE 0x40001000 /* rf */
#define BL602_GPIP_BASE 0x40002000 /* gpip */
#define BL602_SEC_DBG_BASE 0x40003000 /* sec_dbg */
#define BL602_SEC_ENG_BASE 0x40004000 /* sec_eng */
#define BL602_TZC_SEC_BASE 0x40005000 /* tzc_sec */
#define BL602_TZC_NSEC_BASE 0x40006000 /* tzc_nsec */
#define BL602_EF_BASE 0x40007000 /* ef_data_0 / ef_data_1 /ef_ctrl */
#define BL602_CCI_BASE 0x40008000 /* cci */
#define BL602_L1C_BASE 0x40009000 /* l1c */
#define BL602_UART0_BASE 0x4000a000 /* uart0 */
#define BL602_UART1_BASE 0x4000a100 /* uart1 */
#define BL602_SPI_BASE 0x4000a200 /* spi */
#define BL602_I2C_BASE 0x4000a300 /* i2c */
#define BL602_PWM_BASE 0x4000a400 /* pwm */
#define BL602_TIMER_BASE 0x4000a500 /* timer */
#define BL602_IR_BASE 0x4000a600 /* ir */
#define BL602_CKS_BASE 0x4000a000 /* cks (overlaps with UART0?) */
#define BL602_SF_BASE 0x4000b000 /* sf */
#define BL602_DMA_BASE 0x4000c000 /* dma */
#define BL602_PDS_BASE 0x4000e000 /* pds */
#define BL602_HBN_BASE 0x4000f000 /* hbn */
#define BL602_AON_BASE 0x4000f800 /* aon */
#endif /* __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_MEMORYMAP_H */
arch/risc-v/src/bl602/hardware/bl602_pds.h
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arch/risc-v/src/bl602/hardware/bl602_pwm.h
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/****************************************************************************
* arch/risc-v/src/bl602/hardware/bl602_pwm.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_PWM_H
#define __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_PWM_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "bl602_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* PWM0,1,2,3,4 are the same so create this helper for register offsets */
#define BL602_PWM_N_BASE_OFFSET(n) (BL602_PWM_BASE + (BL602_PWM1_BASE_OFFSET - BL602_PWM0_BASE_OFFSET))
/* Register offsets *********************************************************/
#define BL602_PWM_INT_CONFIG_OFFSET 0x000000 /* pwm_int_config */
#define BL602_PWM0_BASE_OFFSET 0x000020 /* pwm0 base */
#define BL602_PWM0_CLKDIV_OFFSET 0x000020 /* pwm0_clkdiv */
#define BL602_PWM0_THRE1_OFFSET 0x000024 /* pwm0_thre1 */
#define BL602_PWM0_THRE2_OFFSET 0x000028 /* pwm0_thre2 */
#define BL602_PWM0_PERIOD_OFFSET 0x00002c /* pwm0_period */
#define BL602_PWM0_CONFIG_OFFSET 0x000030 /* pwm0_config */
#define BL602_PWM0_INTERRUPT_OFFSET 0x000034 /* pwm0_interrupt */
#define BL602_PWM1_BASE_OFFSET 0x000040 /* pwm1 base */
#define BL602_PWM1_CLKDIV_OFFSET 0x000040 /* pwm1_clkdiv */
#define BL602_PWM1_THRE1_OFFSET 0x000044 /* pwm1_thre1 */
#define BL602_PWM1_THRE2_OFFSET 0x000048 /* pwm1_thre2 */
#define BL602_PWM1_PERIOD_OFFSET 0x00004c /* pwm1_period */
#define BL602_PWM1_CONFIG_OFFSET 0x000050 /* pwm1_config */
#define BL602_PWM1_INTERRUPT_OFFSET 0x000054 /* pwm1_interrupt */
#define BL602_PWM2_BASE_OFFSET 0x000060 /* pwm2 base */
#define BL602_PWM2_CLKDIV_OFFSET 0x000060 /* pwm2_clkdiv */
#define BL602_PWM2_THRE1_OFFSET 0x000064 /* pwm2_thre1 */
#define BL602_PWM2_THRE2_OFFSET 0x000068 /* pwm2_thre2 */
#define BL602_PWM2_PERIOD_OFFSET 0x00006c /* pwm2_period */
#define BL602_PWM2_CONFIG_OFFSET 0x000070 /* pwm2_config */
#define BL602_PWM2_INTERRUPT_OFFSET 0x000074 /* pwm2_interrupt */
#define BL602_PWM3_BASE_OFFSET 0x000080 /* pwm3 base */
#define BL602_PWM3_CLKDIV_OFFSET 0x000080 /* pwm3_clkdiv */
#define BL602_PWM3_THRE1_OFFSET 0x000084 /* pwm3_thre1 */
#define BL602_PWM3_THRE2_OFFSET 0x000088 /* pwm3_thre2 */
#define BL602_PWM3_PERIOD_OFFSET 0x00008c /* pwm3_period */
#define BL602_PWM3_CONFIG_OFFSET 0x000090 /* pwm3_config */
#define BL602_PWM3_INTERRUPT_OFFSET 0x000094 /* pwm3_interrupt */
#define BL602_PWM4_BASE_OFFSET 0x0000a0 /* pwm4 base */
#define BL602_PWM4_CLKDIV_OFFSET 0x0000a0 /* pwm4_clkdiv */
#define BL602_PWM4_THRE1_OFFSET 0x0000a4 /* pwm4_thre1 */
#define BL602_PWM4_THRE2_OFFSET 0x0000a8 /* pwm4_thre2 */
#define BL602_PWM4_PERIOD_OFFSET 0x0000ac /* pwm4_period */
#define BL602_PWM4_CONFIG_OFFSET 0x0000b0 /* pwm4_config */
#define BL602_PWM4_INTERRUPT_OFFSET 0x0000b4 /* pwm4_interrupt */
/* Register definitions *****************************************************/
#define BL602_PWM_INT_CONFIG (BL602_PWM_BASE + BL602_PWM_INT_CONFIG_OFFSET)
#define BL602_PWM_N_CLKDIV(n) (BL602_PWM_N_BASE_OFFSET(n) + BL602_PWM0_CLKDIV_OFFSET)
#define BL602_PWM_N_THRE1(n) (BL602_PWM_N_BASE_OFFSET(n) + BL602_PWM0_THRE1_OFFSET)
#define BL602_PWM_N_THRE2(n) (BL602_PWM_N_BASE_OFFSET(n) + BL602_PWM0_THRE2_OFFSET)
#define BL602_PWM_N_PERIOD(n) (BL602_PWM_N_BASE_OFFSET(n) + BL602_PWM0_PERIOD_OFFSET)
#define BL602_PWM_N_CONFIG(n) (BL602_PWM_N_BASE_OFFSET(n) + BL602_PWM0_CONFIG_OFFSET)
#define BL602_PWM_N_INTERRUPT(n) (BL602_PWM_N_BASE_OFFSET(n) + BL602_PWM0_INTERRUPT_OFFSET)
#define BL602_PWM0_CLKDIV BL602_PWM_N_CLKDIV(0)
#define BL602_PWM0_THRE1 BL602_PWM_N_THRE1(0)
#define BL602_PWM0_THRE2 BL602_PWM_N_THRE2(0)
#define BL602_PWM0_PERIOD BL602_PWM_N_PERIOD(0)
#define BL602_PWM0_CONFIG BL602_PWM_N_CONFIG(0)
#define BL602_PWM0_INTERRUPT BL602_PWM_N_INTERRUPT(0)
#define BL602_PWM1_CLKDIV BL602_PWM_N_CLKDIV(1)
#define BL602_PWM1_THRE1 BL602_PWM_N_THRE1(1)
#define BL602_PWM1_THRE2 BL602_PWM_N_THRE2(1)
#define BL602_PWM1_PERIOD BL602_PWM_N_PERIOD(1)
#define BL602_PWM1_CONFIG BL602_PWM_N_CONFIG(1)
#define BL602_PWM1_INTERRUPT BL602_PWM_N_INTERRUPT(1)
#define BL602_PWM2_CLKDIV BL602_PWM_N_CLKDIV(2)
#define BL602_PWM2_THRE1 BL602_PWM_N_THRE1(2)
#define BL602_PWM2_THRE2 BL602_PWM_N_THRE2(2)
#define BL602_PWM2_PERIOD BL602_PWM_N_PERIOD(2)
#define BL602_PWM2_CONFIG BL602_PWM_N_CONFIG(2)
#define BL602_PWM2_INTERRUPT BL602_PWM_N_INTERRUPT(2)
#define BL602_PWM3_CLKDIV BL602_PWM_N_CLKDIV(3)
#define BL602_PWM3_THRE1 BL602_PWM_N_THRE1(3)
#define BL602_PWM3_THRE2 BL602_PWM_N_THRE2(3)
#define BL602_PWM3_PERIOD BL602_PWM_N_PERIOD(3)
#define BL602_PWM3_CONFIG BL602_PWM_N_CONFIG(3)
#define BL602_PWM3_INTERRUPT BL602_PWM_N_INTERRUPT(3)
#define BL602_PWM4_CLKDIV BL602_PWM_N_CLKDIV(4)
#define BL602_PWM4_THRE1 BL602_PWM_N_THRE1(4)
#define BL602_PWM4_THRE2 BL602_PWM_N_THRE2(4)
#define BL602_PWM4_PERIOD BL602_PWM_N_PERIOD(4)
#define BL602_PWM4_CONFIG BL602_PWM_N_CONFIG(4)
#define BL602_PWM4_INTERRUPT BL602_PWM_N_INTERRUPT(4)
/* Register bit definitions *************************************************/
#define INT_CONFIG_PWM_INT_CLEAR_SHIFT (8)
#define INT_CONFIG_PWM_INT_CLEAR_MASK (0x3f << INT_CONFIG_PWM_INT_CLEAR_SHIFT)
#define INT_CONFIG_PWM_INTERRUPT_STS_MASK (0x3f)
#define CLKDIV_PWM_CLK_DIV_MASK (0xffff)
#define THRE1_PWM_THRE1_MASK (0xffff)
#define THRE2_PWM_THRE2_MASK (0xffff)
#define PERIOD_PWM_PERIOD_MASK (0xffff)
#define CONFIG_PWM_STS_TOP (1 << 7)
#define CONFIG_PWM_STOP_EN (1 << 6)
#define CONFIG_PWM_SW_MODE (1 << 5)
#define CONFIG_PWM_SW_FORCE_VAL (1 << 4)
#define CONFIG_PWM_STOP_MODE (1 << 3)
#define CONFIG_PWM_OUT_INV (1 << 2)
#define CONFIG_REG_CLK_SEL_MASK (0x03)
#define INTERRUPT_PWM_INT_ENABLE (1 << 16)
#define INTERRUPT_PWM_INT_PERIOD_CNT_MASK (0xffff)
#endif /* __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_PWM_H */
arch/risc-v/src/bl602/hardware/bl602_rf.h
+1639
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arch/risc-v/src/bl602/hardware/bl602_sec.h
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arch/risc-v/src/bl602/hardware/bl602_sf.h
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arch/risc-v/src/bl602/hardware/bl602_spi.h
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/****************************************************************************
* arch/risc-v/src/bl602/hardware/bl602_spi.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_SPI_H
#define __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_SPI_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "bl602_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define BL602_SPI_CFG_OFFSET 0x000000 /* spi_config */
#define BL602_SPI_INT_STS_OFFSET 0x000004 /* spi_int_sts */
#define BL602_SPI_BUS_BUSY_OFFSET 0x000008 /* spi_bus_busy */
#define BL602_SPI_PRD_0_OFFSET 0x000010 /* spi_prd_0 */
#define BL602_SPI_PRD_1_OFFSET 0x000014 /* spi_prd_1 */
#define BL602_SPI_RXD_IGNR_OFFSET 0x000018 /* spi_rxd_ignr */
#define BL602_SPI_STO_VALUE_OFFSET 0x00001c /* spi_sto_value */
#define BL602_SPI_FIFO_CFG_0_OFFSET 0x000080 /* spi_fifo_config_0 */
#define BL602_SPI_FIFO_CFG_1_OFFSET 0x000084 /* spi_fifo_config_1 */
#define BL602_SPI_FIFO_WDATA_OFFSET 0x000088 /* spi_fifo_wdata */
#define BL602_SPI_FIFO_RDATA_OFFSET 0x00008c /* spi_fifo_rdata */
/* Register definitions *****************************************************/
#define BL602_SPI_CFG (BL602_SPI_BASE + BL602_SPI_CFG_OFFSET)
#define BL602_SPI_INT_STS (BL602_SPI_BASE + BL602_SPI_INT_STS_OFFSET)
#define BL602_SPI_BUS_BUSY (BL602_SPI_BASE + BL602_SPI_BUS_BUSY_OFFSET)
#define BL602_SPI_PRD_0 (BL602_SPI_BASE + BL602_SPI_PRD_0_OFFSET)
#define BL602_SPI_PRD_1 (BL602_SPI_BASE + BL602_SPI_PRD_1_OFFSET)
#define BL602_SPI_RXD_IGNR (BL602_SPI_BASE + BL602_SPI_RXD_IGNR_OFFSET)
#define BL602_SPI_STO_VALUE (BL602_SPI_BASE + BL602_SPI_STO_VALUE_OFFSET)
#define BL602_SPI_FIFO_CFG_0 (BL602_SPI_BASE + BL602_SPI_FIFO_CFG_0_OFFSET)
#define BL602_SPI_FIFO_CFG_1 (BL602_SPI_BASE + BL602_SPI_FIFO_CFG_1_OFFSET)
#define BL602_SPI_FIFO_WDATA (BL602_SPI_BASE + BL602_SPI_FIFO_WDATA_OFFSET)
#define BL602_SPI_FIFO_RDATA (BL602_SPI_BASE + BL602_SPI_FIFO_RDATA_OFFSET)
/* Register bit definitions *************************************************/
#define SPI_CFG_CR_DEG_CNT_SHIFT (12)
#define SPI_CFG_CR_DEG_CNT_MASK (0x0f << SPI_CFG_CR_DEG_CNT_SHIFT)
#define SPI_CFG_CR_DEG_EN (1 << 11)
#define SPI_CFG_CR_M_CONT_EN (1 << 9)
#define SPI_CFG_CR_RXD_IGNR_EN (1 << 8)
#define SPI_CFG_CR_BYTE_INV (1 << 7)
#define SPI_CFG_CR_BIT_INV (1 << 6)
#define SPI_CFG_CR_SCLK_PH (1 << 5)
#define SPI_CFG_CR_SCLK_POL (1 << 4)
#define SPI_CFG_CR_FRAME_SIZE_SHIFT (2)
#define SPI_CFG_CR_FRAME_SIZE_MASK (0x03 << SPI_CFG_CR_FRAME_SIZE_SHIFT)
#define SPI_CFG_CR_S_EN (1 << 1)
#define SPI_CFG_CR_M_EN (1 << 0)
#define SPI_INT_STS_CR_FER_EN (1 << 29)
#define SPI_INT_STS_CR_TXU_EN (1 << 28)
#define SPI_INT_STS_CR_STO_EN (1 << 27)
#define SPI_INT_STS_CR_RXF_EN (1 << 26)
#define SPI_INT_STS_CR_TXF_EN (1 << 25)
#define SPI_INT_STS_CR_END_EN (1 << 24)
#define SPI_INT_STS_RSVD_21 (1 << 21)
#define SPI_INT_STS_CR_TXU_CLR (1 << 20)
#define SPI_INT_STS_CR_STO_CLR (1 << 19)
#define SPI_INT_STS_RSVD_18 (1 << 18)
#define SPI_INT_STS_RSVD_17 (1 << 17)
#define SPI_INT_STS_CR_END_CLR (1 << 16)
#define SPI_INT_STS_CR_FER_MASK (1 << 13)
#define SPI_INT_STS_CR_TXU_MASK (1 << 12)
#define SPI_INT_STS_CR_STO_MASK (1 << 11)
#define SPI_INT_STS_CR_RXF_MASK (1 << 10)
#define SPI_INT_STS_CR_TXF_MASK (1 << 9)
#define SPI_INT_STS_CR_END_MASK (1 << 8)
#define SPI_INT_STS_FER_INT (1 << 5)
#define SPI_INT_STS_TXU_INT (1 << 4)
#define SPI_INT_STS_STO_INT (1 << 3)
#define SPI_INT_STS_RXF_INT (1 << 2)
#define SPI_INT_STS_TXF_INT (1 << 1)
#define SPI_INT_STS_END_INT (1 << 0)
#define SPI_BUS_BUSY_STS_BUS_BUSY (1 << 0)
#define SPI_PRD_0_CR_D_PH_1_SHIFT (24)
#define SPI_PRD_0_CR_D_PH_1_MASK (0xff << SPI_PRD_0_CR_D_PH_1_SHIFT)
#define SPI_PRD_0_CR_D_PH_0_SHIFT (16)
#define SPI_PRD_0_CR_D_PH_0_MASK (0xff << SPI_PRD_0_CR_D_PH_0_SHIFT)
#define SPI_PRD_0_CR_P_SHIFT (8)
#define SPI_PRD_0_CR_P_MASK (0xff << SPI_PRD_0_CR_P_SHIFT)
#define SPI_PRD_0_CR_S_MASK (0xff)
#define SPI_PRD_1_CR_I_MASK (0xff)
#define SPI_RXD_IGNR_CR_IGNR_S_SHIFT (16)
#define SPI_RXD_IGNR_CR_IGNR_S_MASK (0x1f << SPI_RXD_IGNR_CR_RXD_IGNR_S_SHIFT)
#define SPI_RXD_IGNR_CR_IGNR_P_MASK (0x1f)
#define SPI_STO_VALUE_CR_VALUE_MASK (0xfff)
#define SPI_FIFO_CFG_0_RX_UNDERFLOW (1 << 7)
#define SPI_FIFO_CFG_0_RX_OVERFLOW (1 << 6)
#define SPI_FIFO_CFG_0_TX_UNDERFLOW (1 << 5)
#define SPI_FIFO_CFG_0_TX_OVERFLOW (1 << 4)
#define SPI_FIFO_CFG_0_RX_CLR (1 << 3)
#define SPI_FIFO_CFG_0_TX_CLR (1 << 2)
#define SPI_FIFO_CFG_0_DMA_RX_EN (1 << 1)
#define SPI_FIFO_CFG_0_DMA_TX_EN (1 << 0)
#define SPI_FIFO_CFG_1_RX_TH_SHIFT (24)
#define SPI_FIFO_CFG_1_RX_TH_MASK (0x03 << SPI_FIFO_CFG_1_RX_TH_SHIFT)
#define SPI_FIFO_CFG_1_TX_TH_SHIFT (16)
#define SPI_FIFO_CFG_1_TX_TH_MASK (0x03 << SPI_FIFO_CFG_1_TX_TH_SHIFT)
#define SPI_FIFO_CFG_1_RX_CNT_SHIFT (8)
#define SPI_FIFO_CFG_1_RX_CNT_MASK (0x07 << SPI_FIFO_CFG_1_RX_CNT_SHIFT)
#define SPI_FIFO_CFG_1_TX_CNT_MASK (0x07)
#endif /* __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_SPI_H */
arch/risc-v/src/bl602/hardware/bl602_timer.h
+156 -600
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arch/risc-v/src/bl602/hardware/bl602_tzc.h
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/****************************************************************************
* arch/risc-v/src/bl602/hardware/bl602_tzc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_TZC_H
#define __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_TZC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "bl602_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define BL602_SEC_ROM_CTRL_OFFSET 0x000040 /* tzc_rom_ctrl */
#define BL602_SEC_ROM0_R0_OFFSET 0x000044 /* tzc_rom0_r0 */
#define BL602_SEC_ROM0_R1_OFFSET 0x000048 /* tzc_rom0_r1 */
#define BL602_SEC_ROM1_R0_OFFSET 0x00004c /* tzc_rom1_r0 */
#define BL602_SEC_ROM1_R1_OFFSET 0x000050 /* tzc_rom1_r1 */
#define BL602_NSEC_ROM_CTRL_OFFSET 0x000040 /* tzc_rom_ctrl */
#define BL602_NSEC_ROM0_R0_OFFSET 0x000044 /* tzc_rom0_r0 */
#define BL602_NSEC_ROM0_R1_OFFSET 0x000048 /* tzc_rom0_r1 */
#define BL602_NSEC_ROM1_R0_OFFSET 0x00004c /* tzc_rom1_r0 */
#define BL602_NSEC_ROM1_R1_OFFSET 0x000050 /* tzc_rom1_r1 */
/* Register definitions *****************************************************/
#define BL602_SEC_ROM_CTRL (BL602_SEC_BASE + BL602_SEC_ROM_CTRL_OFFSET)
#define BL602_SEC_ROM0_R0 (BL602_SEC_BASE + BL602_SEC_ROM0_R0_OFFSET)
#define BL602_SEC_ROM0_R1 (BL602_SEC_BASE + BL602_SEC_ROM0_R1_OFFSET)
#define BL602_SEC_ROM1_R0 (BL602_SEC_BASE + BL602_SEC_ROM1_R0_OFFSET)
#define BL602_SEC_ROM1_R1 (BL602_SEC_BASE + BL602_SEC_ROM1_R1_OFFSET)
#define BL602_NSEC_ROM_CTRL (BL602_NSEC_BASE + BL602_NSEC_ROM_CTRL_OFFSET)
#define BL602_NSEC_ROM0_R0 (BL602_NSEC_BASE + BL602_NSEC_ROM0_R0_OFFSET)
#define BL602_NSEC_ROM0_R1 (BL602_NSEC_BASE + BL602_NSEC_ROM0_R1_OFFSET)
#define BL602_NSEC_ROM1_R0 (BL602_NSEC_BASE + BL602_NSEC_ROM1_R0_OFFSET)
#define BL602_NSEC_ROM1_R1 (BL602_NSEC_BASE + BL602_NSEC_ROM1_R1_OFFSET)
/* Register bit definitions *************************************************/
#define TZC_SEC_ROM_CTRL_SBOOT_DONE_SHIFT (28)
#define TZC_SEC_ROM_CTRL_SBOOT_DONE_MASK (0x0f << TZC_SEC_ROM_CTRL_SBOOT_DONE_SHIFT)
#define TZC_SEC_ROM_CTRL_ROM1_R1_LOCK (1 << 27)
#define TZC_SEC_ROM_CTRL_ROM1_R0_LOCK (1 << 26)
#define TZC_SEC_ROM_CTRL_ROM0_R1_LOCK (1 << 25)
#define TZC_SEC_ROM_CTRL_ROM0_R0_LOCK (1 << 24)
#define TZC_SEC_ROM_CTRL_ROM1_R1_EN (1 << 19)
#define TZC_SEC_ROM_CTRL_ROM1_R0_EN (1 << 18)
#define TZC_SEC_ROM_CTRL_ROM0_R1_EN (1 << 17)
#define TZC_SEC_ROM_CTRL_ROM0_R0_EN (1 << 16)
#define TZC_SEC_ROM_CTRL_ROM1_R1_ID1_EN (1 << 11)
#define TZC_SEC_ROM_CTRL_ROM1_R0_ID1_EN (1 << 10)
#define TZC_SEC_ROM_CTRL_ROM0_R1_ID1_EN (1 << 9)
#define TZC_SEC_ROM_CTRL_ROM0_R0_ID1_EN (1 << 8)
#define TZC_SEC_ROM_CTRL_ROM1_R1_ID0_EN (1 << 3)
#define TZC_SEC_ROM_CTRL_ROM1_R0_ID0_EN (1 << 2)
#define TZC_SEC_ROM_CTRL_ROM0_R1_ID0_EN (1 << 1)
#define TZC_SEC_ROM_CTRL_ROM0_R0_ID0_EN (1 << 0)
#define TZC_SEC_ROM0_R0_START_SHIFT (16)
#define TZC_SEC_ROM0_R0_START_MASK (0xffff << TZC_SEC_ROM0_R0_START_SHIFT)
#define TZC_SEC_ROM0_R0_END_MASK (0xffff)
#define TZC_SEC_ROM0_R01_START_SHIFT (16)
#define TZC_SEC_ROM0_R01_START_MASK (0xffff << TZC_SEC_ROM0_R01_START_SHIFT)
#define TZC_SEC_ROM0_R01_END_MASK (0xffff)
#define TZC_SEC_ROM1_R0_START_SHIFT (16)
#define TZC_SEC_ROM1_R0_START_MASK (0xffff << TZC_SEC_ROM1_R0_START_SHIFT)
#define TZC_SEC_ROM1_R0_END_MASK (0xffff)
#define TZC_SEC_ROM1_R1_START_SHIFT (16)
#define TZC_SEC_ROM1_R1_START_MASK (0xffff << TZC_SEC_ROM1_R1_START_SHIFT)
#define TZC_SEC_ROM1_R1_END_MASK (0xffff)
#define TZC_NSEC_ROM_CTRL_SBOOT_DONE_SHIFT (28)
#define TZC_NSEC_ROM_CTRL_SBOOT_DONE_MASK (0x0f << TZC_NSEC_ROM_CTRL_SBOOT_DONE_SHIFT)
#define TZC_NSEC_ROM_CTRL_ROM1_R1_LOCK (1 << 27)
#define TZC_NSEC_ROM_CTRL_ROM1_R0_LOCK (1 << 26)
#define TZC_NSEC_ROM_CTRL_ROM0_R1_LOCK (1 << 25)
#define TZC_NSEC_ROM_CTRL_ROM0_R0_LOCK (1 << 24)
#define TZC_NSEC_ROM_CTRL_ROM1_R1_EN (1 << 19)
#define TZC_NSEC_ROM_CTRL_ROM1_R0_EN (1 << 18)
#define TZC_NSEC_ROM_CTRL_ROM0_R1_EN (1 << 17)
#define TZC_NSEC_ROM_CTRL_ROM0_R0_EN (1 << 16)
#define TZC_NSEC_ROM_CTRL_ROM1_R1_ID1_EN (1 << 11)
#define TZC_NSEC_ROM_CTRL_ROM1_R0_ID1_EN (1 << 10)
#define TZC_NSEC_ROM_CTRL_ROM0_R1_ID1_EN (1 << 9)
#define TZC_NSEC_ROM_CTRL_ROM0_R0_ID1_EN (1 << 8)
#define TZC_NSEC_ROM_CTRL_ROM1_R1_ID0_EN (1 << 3)
#define TZC_NSEC_ROM_CTRL_ROM1_R0_ID0_EN (1 << 2)
#define TZC_NSEC_ROM_CTRL_ROM0_R1_ID0_EN (1 << 1)
#define TZC_NSEC_ROM_CTRL_ROM0_R0_ID0_EN (1 << 0)
#define TZC_NSEC_ROM0_R0_START_SHIFT (16)
#define TZC_NSEC_ROM0_R0_START_MASK (0xffff << TZC_NSEC_ROM0_R0_START_SHIFT)
#define TZC_NSEC_ROM0_R0_END_MASK (0xffff)
#define TZC_NSEC_ROM0_R01_START_SHIFT (16)
#define TZC_NSEC_ROM0_R01_START_MASK (0xffff << TZC_NSEC_ROM0_R01_START_SHIFT)
#define TZC_NSEC_ROM0_R01_END_MASK (0xffff)
#define TZC_NSEC_ROM1_R0_START_SHIFT (16)
#define TZC_NSEC_ROM1_R0_START_MASK (0xffff << TZC_NSEC_ROM1_R0_START_SHIFT)
#define TZC_NSEC_ROM1_R0_END_MASK (0xffff)
#define TZC_NSEC_ROM1_R1_START_SHIFT (16)
#define TZC_NSEC_ROM1_R1_START_MASK (0xffff << TZC_NSEC_ROM1_R1_START_SHIFT)
#define TZC_NSEC_ROM1_R1_END_MASK (0xffff)
#endif /* __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_TZC_H */
arch/risc-v/src/bl602/hardware/bl602_uart.h
+166 -642
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arch/risc-v/src/bl602/hardware/clic.h
-43
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@@ -1,43 +0,0 @@
/****************************************************************************
* arch/risc-v/src/bl602/hardware/clic.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISCV_SRC_BL602_HARDWARE_CLIC_H
#define __ARCH_RISCV_SRC_BL602_HARDWARE_CLIC_H
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define CLIC_CTRL_ADDR 0x02000000
#define CLIC_HART0_ADDR 0x02800000
#define CLIC_MSIP 0x0000
#define CLIC_MSIP_size 0x4
#define CLIC_MTIMECMP 0x4000
#define CLIC_MTIMECMP_size 0x8
#define CLIC_MTIME 0xBFF8
#define CLIC_MTIME_size 0x8
#define CLIC_INTIP 0x000
#define CLIC_INTIE 0x400
#define CLIC_INTCFG 0x800
#define CLIC_CFG 0xc00
#endif /* __ARCH_RISCV_SRC_BL602_HARDWARE_CLIC_H */
boards/risc-v/bl602/bl602evb/include/board.h
+9
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@@ -27,10 +27,19 @@
#include <nuttx/config.h>
/* Do not include BL602 header files here. */
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* UART Configuration */
#define BOARD_UART_0_RX_PIN (GPIO_INPUT | GPIO_PULLUP | GPIO_FUNC_UART | GPIO_PIN7)
#define BOARD_UART_0_TX_PIN (GPIO_INPUT | GPIO_PULLUP | GPIO_FUNC_UART | GPIO_PIN16)
#define BOARD_UART_1_RX_PIN (GPIO_INPUT | GPIO_PULLUP | GPIO_FUNC_UART | GPIO_PIN3)
#define BOARD_UART_1_TX_PIN (GPIO_INPUT | GPIO_PULLUP | GPIO_FUNC_UART | GPIO_PIN4)
/****************************************************************************
* Public Types
****************************************************************************/