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More progress on the PIC32MX Ethernet driver

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4282 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
2012-01-08 18:41:49 +00:00
parent 95518c7f3f
commit decac77c65
4 changed files with 433 additions and 282 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm/src/stm32/stm32_serial.c
+1
View File
@@ -124,6 +124,7 @@ struct up_dev_s
const uint32_t rx_gpio; /* U[S]ART RX GPIO pin configuration */
const uint32_t rts_gpio; /* U[S]ART RTS GPIO pin configuration */
const uint32_t cts_gpio; /* U[S]ART CTS GPIO pin configuration */
int (* const vector)(int irq, void *context); /* Interrupt handler */
};
arch/mips/include/pic32mx/chip.h
+56 -56
View File
@@ -545,8 +545,8 @@
# define CHIP_JTAG
#elif defined(CONFIG_ARCH_CHIP_PIC32MX534F064H)
# undef CHIP_PIC32MX3
# define CHIP_PIC32MX4
# undef CHIP_PIC32MX5 1
# undef CHIP_PIC32MX4
# define CHIP_PIC32MX5 1
# undef CHIP_PIC32MX6
# undef CHIP_PIC32MX7
# define CHIP_NPINS 64 /* Package PT,MR */
@@ -574,8 +574,8 @@
# define CHIP_JTAG
#elif defined(CONFIG_ARCH_CHIP_PIC32MX564F064H)
# undef CHIP_PIC32MX3
# define CHIP_PIC32MX4
# undef CHIP_PIC32MX5 1
# undef CHIP_PIC32MX4
# define CHIP_PIC32MX5 1
# undef CHIP_PIC32MX6
# undef CHIP_PIC32MX7
# define CHIP_NPINS 64 /* Package PT,MR */
@@ -603,8 +603,8 @@
# define CHIP_JTAG
#elif defined(CONFIG_ARCH_CHIP_PIC32MX564F128H)
# undef CHIP_PIC32MX3
# define CHIP_PIC32MX4
# undef CHIP_PIC32MX5 1
# undef CHIP_PIC32MX4
# define CHIP_PIC32MX5 1
# undef CHIP_PIC32MX6
# undef CHIP_PIC32MX7
# define CHIP_NPINS 64 /* Package PT,MR */
@@ -632,8 +632,8 @@
# define CHIP_JTAG
#elif defined(CONFIG_ARCH_CHIP_PIC32MX575F256H)
# undef CHIP_PIC32MX3
# define CHIP_PIC32MX4
# undef CHIP_PIC32MX5 1
# undef CHIP_PIC32MX4
# define CHIP_PIC32MX5 1
# undef CHIP_PIC32MX6
# undef CHIP_PIC32MX7
# define CHIP_NPINS 64 /* Package PT,MR */
@@ -661,8 +661,8 @@
# define CHIP_JTAG
#elif defined(CONFIG_ARCH_CHIP_PIC32MX575F512H)
# undef CHIP_PIC32MX3
# define CHIP_PIC32MX4
# undef CHIP_PIC32MX5 1
# undef CHIP_PIC32MX4
# define CHIP_PIC32MX5 1
# undef CHIP_PIC32MX6
# undef CHIP_PIC32MX7
# define CHIP_NPINS 64 /* Package PT,MR */
@@ -690,8 +690,8 @@
# define CHIP_JTAG
#elif defined(CONFIG_ARCH_CHIP_PIC32MX534F064L)
# undef CHIP_PIC32MX3
# define CHIP_PIC32MX4
# undef CHIP_PIC32MX5 1
# undef CHIP_PIC32MX4
# define CHIP_PIC32MX5 1
# undef CHIP_PIC32MX6
# undef CHIP_PIC32MX7
# define CHIP_NPINS 100 /* Package PT,PF,BG */
@@ -719,8 +719,8 @@
# define CHIP_JTAG
#elif defined(CONFIG_ARCH_CHIP_PIC32MX564F064L)
# undef CHIP_PIC32MX3
# define CHIP_PIC32MX4
# undef CHIP_PIC32MX5 1
# undef CHIP_PIC32MX4
# define CHIP_PIC32MX5 1
# undef CHIP_PIC32MX6
# undef CHIP_PIC32MX7
# define CHIP_NPINS 100 /* Package PT,PF,BG */
@@ -748,8 +748,8 @@
# define CHIP_JTAG
#elif defined(CONFIG_ARCH_CHIP_PIC32MX564F128L)
# undef CHIP_PIC32MX3
# define CHIP_PIC32MX4
# undef CHIP_PIC32MX5 1
# undef CHIP_PIC32MX4
# define CHIP_PIC32MX5 1
# undef CHIP_PIC32MX6
# undef CHIP_PIC32MX7
# define CHIP_NPINS 100 /* Package PT,PF,BG */
@@ -777,8 +777,8 @@
# define CHIP_JTAG
#elif defined(CONFIG_ARCH_CHIP_PIC32MX575F256L)
# undef CHIP_PIC32MX3
# define CHIP_PIC32MX4
# undef CHIP_PIC32MX5 1
# undef CHIP_PIC32MX4
# define CHIP_PIC32MX5 1
# undef CHIP_PIC32MX6
# undef CHIP_PIC32MX7
# define CHIP_NPINS 100 /* Package PT,PF,BG */
@@ -806,8 +806,8 @@
# define CHIP_JTAG
#elif defined(CONFIG_ARCH_CHIP_PIC32MX575F512L)
# undef CHIP_PIC32MX3
# define CHIP_PIC32MX4
# undef CHIP_PIC32MX5 1
# undef CHIP_PIC32MX4
# define CHIP_PIC32MX5 1
# undef CHIP_PIC32MX6
# undef CHIP_PIC32MX7
# define CHIP_NPINS 100 /* Package PT,PF,BG */
@@ -835,9 +835,9 @@
# define CHIP_JTAG
#elif defined(CONFIG_ARCH_CHIP_PIC32MX664F064H)
# undef CHIP_PIC32MX3
# define CHIP_PIC32MX4
# undef CHIP_PIC32MX4
# undef CHIP_PIC32MX5
# undef CHIP_PIC32MX6 1
# define CHIP_PIC32MX6 1
# undef CHIP_PIC32MX7
# define CHIP_NPINS 64 /* Package PT,MR */
# define CHIP_MHZ 80 /* 80MHz maximum frequency */
@@ -864,9 +864,9 @@
# define CHIP_JTAG
#elif defined(CONFIG_ARCH_CHIP_PIC32MX664F128H)
# undef CHIP_PIC32MX3
# define CHIP_PIC32MX4
# undef CHIP_PIC32MX4
# undef CHIP_PIC32MX5
# undef CHIP_PIC32MX6 1
# define CHIP_PIC32MX6 1
# undef CHIP_PIC32MX7
# define CHIP_NPINS 64 /* Package PT,MR */
# define CHIP_MHZ 80 /* 80MHz maximum frequency */
@@ -893,9 +893,9 @@
# define CHIP_JTAG
#elif defined(CONFIG_ARCH_CHIP_PIC32MX675F256H)
# undef CHIP_PIC32MX3
# define CHIP_PIC32MX4
# undef CHIP_PIC32MX4
# undef CHIP_PIC32MX5
# undef CHIP_PIC32MX6 1
# define CHIP_PIC32MX6 1
# undef CHIP_PIC32MX7
# define CHIP_NPINS 64 /* Package PT,MR */
# define CHIP_MHZ 80 /* 80MHz maximum frequency */
@@ -922,9 +922,9 @@
# define CHIP_JTAG
#elif defined(CONFIG_ARCH_CHIP_PIC32MX675F512H)
# undef CHIP_PIC32MX3
# define CHIP_PIC32MX4
# undef CHIP_PIC32MX4
# undef CHIP_PIC32MX5
# undef CHIP_PIC32MX6 1
# define CHIP_PIC32MX6 1
# undef CHIP_PIC32MX7
# define CHIP_NPINS 64 /* Package PT,MR */
# define CHIP_MHZ 80 /* 80MHz maximum frequency */
@@ -951,9 +951,9 @@
# define CHIP_JTAG
#elif defined(CONFIG_ARCH_CHIP_PIC32MX695F512H)
# undef CHIP_PIC32MX3
# define CHIP_PIC32MX4
# undef CHIP_PIC32MX4
# undef CHIP_PIC32MX5
# undef CHIP_PIC32MX6 1
# define CHIP_PIC32MX6 1
# undef CHIP_PIC32MX7
# define CHIP_NPINS 64 /* Package PT,MR */
# define CHIP_MHZ 80 /* 80MHz maximum frequency */
@@ -980,9 +980,9 @@
# define CHIP_JTAG
#elif defined(CONFIG_ARCH_CHIP_PIC32MX664F064L)
# undef CHIP_PIC32MX3
# define CHIP_PIC32MX4
# undef CHIP_PIC32MX4
# undef CHIP_PIC32MX5
# undef CHIP_PIC32MX6 1
# define CHIP_PIC32MX6 1
# undef CHIP_PIC32MX7
# define CHIP_NPINS 100 /* Package PT,PF,BG */
# define CHIP_MHZ 80 /* 80MHz maximum frequency */
@@ -1009,9 +1009,9 @@
# define CHIP_JTAG
#elif defined(CONFIG_ARCH_CHIP_PIC32MX664F128L)
# undef CHIP_PIC32MX3
# define CHIP_PIC32MX4
# undef CHIP_PIC32MX4
# undef CHIP_PIC32MX5
# undef CHIP_PIC32MX6 1
# define CHIP_PIC32MX6 1
# undef CHIP_PIC32MX7
# define CHIP_NPINS 100 /* Package PT,PF,BG */
# define CHIP_MHZ 80 /* 80MHz maximum frequency */
@@ -1038,9 +1038,9 @@
# define CHIP_JTAG
#elif defined(CONFIG_ARCH_CHIP_PIC32MX675F256L)
# undef CHIP_PIC32MX3
# define CHIP_PIC32MX4
# undef CHIP_PIC32MX4
# undef CHIP_PIC32MX5
# undef CHIP_PIC32MX6 1
# define CHIP_PIC32MX6 1
# undef CHIP_PIC32MX7
# define CHIP_NPINS 100 /* Package PT,PF,BG */
# define CHIP_MHZ 80 /* 80MHz maximum frequency */
@@ -1067,9 +1067,9 @@
# define CHIP_JTAG
#elif defined(CONFIG_ARCH_CHIP_PIC32MX675F512L)
# undef CHIP_PIC32MX3
# define CHIP_PIC32MX4
# undef CHIP_PIC32MX4
# undef CHIP_PIC32MX5
# undef CHIP_PIC32MX6 1
# define CHIP_PIC32MX6 1
# undef CHIP_PIC32MX7
# define CHIP_NPINS 100 /* Package PT,PF,BG */
# define CHIP_MHZ 80 /* 80MHz maximum frequency */
@@ -1096,9 +1096,9 @@
# define CHIP_JTAG
#elif defined(CONFIG_ARCH_CHIP_PIC32MX695F512L)
# undef CHIP_PIC32MX3
# define CHIP_PIC32MX4
# undef CHIP_PIC32MX4
# undef CHIP_PIC32MX5
# undef CHIP_PIC32MX6 1
# define CHIP_PIC32MX6 1
# undef CHIP_PIC32MX7
# define CHIP_NPINS 100 /* Package PT,PF,BG */
# define CHIP_MHZ 80 /* 80MHz maximum frequency */
@@ -1125,10 +1125,10 @@
# define CHIP_JTAG
#elif defined(CONFIG_ARCH_CHIP_PIC32MX764F128H)
# undef CHIP_PIC32MX3
# define CHIP_PIC32MX4
# undef CHIP_PIC32MX4
# undef CHIP_PIC32MX5
# undef CHIP_PIC32MX6
# undef CHIP_PIC32MX7 1
# define CHIP_PIC32MX7 1
# define CHIP_NPINS 64 /* Package PT,MR */
# define CHIP_MHZ 80 /* 80MHz maximum frequency */
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
@@ -1154,10 +1154,10 @@
# define CHIP_JTAG
#elif defined(CONFIG_ARCH_CHIP_PIC32MX775F256H)
# undef CHIP_PIC32MX3
# define CHIP_PIC32MX4
# undef CHIP_PIC32MX4
# undef CHIP_PIC32MX5
# undef CHIP_PIC32MX6
# undef CHIP_PIC32MX7 1
# define CHIP_PIC32MX7 1
# define CHIP_NPINS 64 /* Package PT,MR */
# define CHIP_MHZ 80 /* 80MHz maximum frequency */
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
@@ -1183,10 +1183,10 @@
# define CHIP_JTAG
#elif defined(CONFIG_ARCH_CHIP_PIC32MX775F512H)
# undef CHIP_PIC32MX3
# define CHIP_PIC32MX4
# undef CHIP_PIC32MX4
# undef CHIP_PIC32MX5
# undef CHIP_PIC32MX6
# undef CHIP_PIC32MX7 1
# define CHIP_PIC32MX7 1
# define CHIP_NPINS 64 /* Package PT,MR */
# define CHIP_MHZ 80 /* 80MHz maximum frequency */
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
@@ -1212,10 +1212,10 @@
# define CHIP_JTAG
#elif defined(CONFIG_ARCH_CHIP_PIC32MX795F512H)
# undef CHIP_PIC32MX3
# define CHIP_PIC32MX4
# undef CHIP_PIC32MX4
# undef CHIP_PIC32MX5
# undef CHIP_PIC32MX6
# undef CHIP_PIC32MX7 1
# define CHIP_PIC32MX7 1
# define CHIP_NPINS 64 /* Package PT,MR */
# define CHIP_MHZ 80 /* 80MHz maximum frequency */
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
@@ -1241,10 +1241,10 @@
# define CHIP_JTAG
#elif defined(CONFIG_ARCH_CHIP_PIC32MX764F128L)
# undef CHIP_PIC32MX3
# define CHIP_PIC32MX4
# undef CHIP_PIC32MX4
# undef CHIP_PIC32MX5
# undef CHIP_PIC32MX6
# undef CHIP_PIC32MX7 1
# define CHIP_PIC32MX7 1
# define CHIP_NPINS 100 /* Package PT,PF,BG */
# define CHIP_MHZ 80 /* 80MHz maximum frequency */
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
@@ -1270,10 +1270,10 @@
# define CHIP_JTAG
#elif defined(CONFIG_ARCH_CHIP_PIC32MX775F256L)
# undef CHIP_PIC32MX3
# define CHIP_PIC32MX4
# undef CHIP_PIC32MX4
# undef CHIP_PIC32MX5
# undef CHIP_PIC32MX6
# undef CHIP_PIC32MX7 1
# define CHIP_PIC32MX7 1
# define CHIP_NPINS 100 /* Package PT,PF,BG */
# define CHIP_MHZ 80 /* 80MHz maximum frequency */
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
@@ -1299,10 +1299,10 @@
# define CHIP_JTAG
#elif defined(CONFIG_ARCH_CHIP_PIC32MX775F512L)
# undef CHIP_PIC32MX3
# define CHIP_PIC32MX4
# undef CHIP_PIC32MX4
# undef CHIP_PIC32MX5
# undef CHIP_PIC32MX6
# undef CHIP_PIC32MX7 1
# define CHIP_PIC32MX7 1
# define CHIP_NPINS 100 /* Package PT,PF,BG */
# define CHIP_MHZ 80 /* 80MHz maximum frequency */
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
@@ -1328,10 +1328,10 @@
# define CHIP_JTAG
#elif defined(CONFIG_ARCH_CHIP_PIC32MX795F512L)
# undef CHIP_PIC32MX3
# define CHIP_PIC32MX4
# undef CHIP_PIC32MX4
# undef CHIP_PIC32MX5
# undef CHIP_PIC32MX6
# undef CHIP_PIC32MX7 1
# define CHIP_PIC32MX7 1
# define CHIP_NPINS 100 /* Package PT,PF,BG */
# define CHIP_MHZ 80 /* 80MHz maximum frequency */
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
arch/mips/src/pic32mx/pic32mx-ethernet.c
+367 -218
View File
File diff suppressed because it is too large Load Diff
arch/mips/src/pic32mx/pic32mx-ethernet.h
+9 -8
View File
@@ -73,9 +73,9 @@
#define PIC32MX_ETH_IENCLR_OFFSET 0x00c8
#define PIC32MX_ETH_IENINV_OFFSET 0x00cc
#define PIC32MX_ETH_IRQ_OFFSET 0x00d0 /* Ethernet Controller Interrupt Request Register */
#define PIC32MX_ETH_IENSET_OFFSET 0x00d4
#define PIC32MX_ETH_IENCLR_OFFSET 0x00d8
#define PIC32MX_ETH_IENINV_OFFSET 0x00dc
#define PIC32MX_ETH_IRQSET_OFFSET 0x00d4
#define PIC32MX_ETH_IRQCLR_OFFSET 0x00d8
#define PIC32MX_ETH_IRQINV_OFFSET 0x00dc
#define PIC32MX_ETH_STAT_OFFSET 0x00e0 /* Ethernet Controller Status Register */
/* RX Filtering Configuration Registers */
@@ -248,9 +248,9 @@
#define PIC32MX_ETH_IENCLR (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_IENCLR_OFFSET)
#define PIC32MX_ETH_IENINV (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_IENINV_OFFSET)
#define PIC32MX_ETH_IRQ (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_IRQ_OFFSET)
#define PIC32MX_ETH_IENSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_IENSET_OFFSET)
#define PIC32MX_ETH_IENCLR (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_IENCLR_OFFSET)
#define PIC32MX_ETH_IENINV (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_IENINV_OFFSET)
#define PIC32MX_ETH_IRQSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_IRQSET_OFFSET)
#define PIC32MX_ETH_IRQCLR (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_IRQCLR_OFFSET)
#define PIC32MX_ETH_IRQINV (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_IRQINV_OFFSET)
#define PIC32MX_ETH_STAT (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_STAT_OFFSET)
/* RX Filtering Configuration Registers */
@@ -441,6 +441,8 @@
#define ETH_INT_RXBUSE (1 << 13) /* Bit 13: Receive BVCI bus error interrupt */
#define ETH_INT_TXBUSE (1 << 14) /* Bit 14: TXBUSEIE: Transmit BVCI bus error interrupt */
/* Bits 15-31: Reserved */
#define ETH_INT_ALLINTS (0x000063ef)
/* Ethernet Controller Status Register */
/* Bits 0-4: Reserved */
@@ -591,7 +593,7 @@
/* Bits 16-31: Reserved */
/* Ethernet Controller MAC Configuration 2 Register */
#define EMAC1_CFG2_FULLDPLX: (1 << 0) /* Bit 0: Full duplex operation */
#define EMAC1_CFG2_FULLDPLX (1 << 0) /* Bit 0: Full duplex operation */
#define EMAC1_CFG2_LENGTHCK (1 << 1) /* Bit 1: Frame length checking */
#define EMAC1_CFG2_HUGEFRM (1 << 2) /* Bit 2: Huge frame enable */
#define EMAC1_CFG2_DELAYCRC (1 << 3) /* Bit 3: Delayed CRC */
@@ -633,7 +635,6 @@
#define EMAC1_MAXF_MASK (0xffff << EMAC1_MAXF_SHIFT)
/* Bits 16-31: Reserved */
/* Ethernet Controller MAC PHY Support Register */
#define EMAC1_SUPP_
/* Bits 0-7: Reserved */
#define EMAC1_SUPP_SPEEDRMII (1 << 8) /* Bit 8: RMII Speed0=10Bps 1=100Bps */
/* Bits 9-10: Reserved */