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Fix nxstyle to stm32l4 files (#721)

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* Fix nxstyle for usbhost, userspace, wdg, rcc, dma, rcc etc
This commit is contained in:
Alan Carvalho de Assis
2020-04-04 12:50:33 -03:00
committed by GitHub
parent 460124629c
commit de188fbe85
10 changed files with 391 additions and 290 deletions
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arch/arm/src/stm32l4/stm32l4_usbhost.h
+33 -30
View File
@@ -1,4 +1,4 @@
/************************************************************************************ /****************************************************************************
* arch/arm/src/stm32l4/stm32l4_usbhost.h * arch/arm/src/stm32l4/stm32l4_usbhost.h
* *
* Copyright (C) 2012, 2014 Gregory Nutt. All rights reserved. * Copyright (C) 2012, 2014 Gregory Nutt. All rights reserved.
@@ -32,14 +32,14 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE. * POSSIBILITY OF SUCH DAMAGE.
* *
************************************************************************************/ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_USBHOST_H #ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_USBHOST_H
#define __ARCH_ARM_SRC_STM32L4_STM32L4_USBHOST_H #define __ARCH_ARM_SRC_STM32L4_STM32L4_USBHOST_H
/************************************************************************************ /****************************************************************************
* Included Files * Included Files
************************************************************************************/ ****************************************************************************/
#include <nuttx/config.h> #include <nuttx/config.h>
#include <nuttx/usb/usbhost.h> #include <nuttx/usb/usbhost.h>
@@ -58,9 +58,9 @@
# error "Unsupported STM32L4 chip" # error "Unsupported STM32L4 chip"
#endif #endif
/************************************************************************************ /****************************************************************************
* Public Types * Public Types
************************************************************************************/ ****************************************************************************/
#ifdef HAVE_USBHOST_TRACE #ifdef HAVE_USBHOST_TRACE
enum usbhost_trace1codes_e enum usbhost_trace1codes_e
@@ -85,7 +85,7 @@ enum usbhost_trace1codes_e
OTGFS_VTRACE1_GINT_PTXFE, /* OTGFS Handle the periodic TxFIFO empty interrupt */ OTGFS_VTRACE1_GINT_PTXFE, /* OTGFS Handle the periodic TxFIFO empty interrupt */
OTGFS_VTRACE1_GINT_HC, /* OTGFS Handle the host channels interrupt */ OTGFS_VTRACE1_GINT_HC, /* OTGFS Handle the host channels interrupt */
OTGFS_VTRACE1_GINT_HPRT, /* OTGFS Handle the host port interrupt */ OTGFS_VTRACE1_GINT_HPRT, /* OTGFS Handle the host port interrupt */
OTGFS_VTRACE1_GINT_HPRT_POCCHNG, /* OTGFS HPRT: Port Over-Current Change*/ OTGFS_VTRACE1_GINT_HPRT_POCCHNG, /* OTGFS HPRT: Port Over-Current Change */
OTGFS_VTRACE1_GINT_HPRT_PCDET, /* OTGFS HPRT: Port Connect Detect */ OTGFS_VTRACE1_GINT_HPRT_PCDET, /* OTGFS HPRT: Port Connect Detect */
OTGFS_VTRACE1_GINT_HPRT_PENCHNG, /* OTGFS HPRT: Port Enable Changed */ OTGFS_VTRACE1_GINT_HPRT_PENCHNG, /* OTGFS HPRT: Port Enable Changed */
OTGFS_VTRACE1_GINT_HPRT_LSDEV, /* OTGFS HPRT: Low Speed Device Connected */ OTGFS_VTRACE1_GINT_HPRT_LSDEV, /* OTGFS HPRT: Low Speed Device Connected */
@@ -139,11 +139,11 @@ enum usbhost_trace1codes_e
#endif #endif
/************************************************************************************ /****************************************************************************
* Public Functions * Public Function Prototypes
************************************************************************************/ ****************************************************************************/
/*
* STM32L4 USB OTG FS Host Driver Support /* STM32L4 USB OTG FS Host Driver Support
* *
* Pre-requisites * Pre-requisites
* *
@@ -157,8 +157,8 @@ enum usbhost_trace1codes_e
* Default 128 (512 bytes) * Default 128 (512 bytes)
* CONFIG_STM32L4_OTGFS_NPTXFIFO_SIZE - Size of the non-periodic Tx FIFO * CONFIG_STM32L4_OTGFS_NPTXFIFO_SIZE - Size of the non-periodic Tx FIFO
* in 32-bit words. Default 96 (384 bytes) * in 32-bit words. Default 96 (384 bytes)
* CONFIG_STM32L4_OTGFS_PTXFIFO_SIZE - Size of the periodic Tx FIFO in 32-bit * CONFIG_STM32L4_OTGFS_PTXFIFO_SIZE - Size of the periodic Tx FIFO in
* words. Default 96 (384 bytes) * 32-bit words. Default 96 (384 bytes)
* CONFIG_STM32L4_OTGFS_SOFINTR - Enable SOF interrupts. Why would you ever * CONFIG_STM32L4_OTGFS_SOFINTR - Enable SOF interrupts. Why would you ever
* want to do that? * want to do that?
* *
@@ -166,9 +166,9 @@ enum usbhost_trace1codes_e
* debug. Depends on CONFIG_DEBUG. * debug. Depends on CONFIG_DEBUG.
*/ */
/************************************************************************************ /****************************************************************************
* Public Functions * Public Function Prototypes
************************************************************************************/ ****************************************************************************/
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__
@@ -181,31 +181,34 @@ extern "C"
#define EXTERN extern #define EXTERN extern
#endif #endif
/*********************************************************************************** /****************************************************************************
* Name: stm32l4_usbhost_vbusdrive * Name: stm32l4_usbhost_vbusdrive
* *
* Description: * Description:
* Enable/disable driving of VBUS 5V output. This function must be provided be * Enable/disable driving of VBUS 5V output. This function must be
* each platform that implements the STM32L4 OTG FS host interface * provided be each platform that implements the STM32L4 OTG FS host
* interface
* *
* "On-chip 5 V VBUS generation is not supported. For this reason, a charge pump * "On-chip 5 V VBUS generation is not supported. For this reason, a charge
* or, if 5 V are available on the application board, a basic power switch, must * pump or, if 5 V are available on the application board, a basic power
* be added externally to drive the 5 V VBUS line. The external charge pump can * switch, must be added externally to drive the 5 V VBUS line. The
* be driven by any GPIO output. When the application decides to power on VBUS * external charge pump can be driven by any GPIO output. When the
* using the chosen GPIO, it must also set the port power bit in the host port * application decides to power on VBUS using the chosen GPIO, it must
* control and status register (PPWR bit in OTG_FS_HPRT). * also set the port power bit in the host port control and status
* register (PPWR bit in OTG_FS_HPRT).
* *
* "The application uses this field to control power to this port, and the core * "The application uses this field to control power to this port, and the
* clears this bit on an over current condition." * core clears this bit on an over current condition."
* *
* Input Parameters: * Input Parameters:
* iface - For future growth to handle multiple USB host interface. Should be zero. * iface - For future growth to handle multiple USB host interface.
* Should be zero.
* enable - true: enable VBUS power; false: disable VBUS power * enable - true: enable VBUS power; false: disable VBUS power
* *
* Returned Value: * Returned Value:
* None * None
* *
***********************************************************************************/ ****************************************************************************/
void stm32l4_usbhost_vbusdrive(int iface, bool enable); void stm32l4_usbhost_vbusdrive(int iface, bool enable);
arch/arm/src/stm32l4/stm32l4_usbhost_trace.c
+90 -45
View File
@@ -80,63 +80,108 @@ struct stm32l4_usbhost_trace_s
static const struct stm32l4_usbhost_trace_s g_trace1[TRACE1_NSTRINGS] = static const struct stm32l4_usbhost_trace_s g_trace1[TRACE1_NSTRINGS] =
{ {
TRENTRY(OTGFS_TRACE1_DEVDISCONN, TR_FMT1, "OTGFS ERROR: Host Port %d. Device disconnected\n"), TRENTRY(OTGFS_TRACE1_DEVDISCONN, TR_FMT1,
TRENTRY(OTGFS_TRACE1_IRQATTACH, TR_FMT1, "OTGFS ERROR: Failed to attach IRQ\n"), "OTGFS ERROR: Host Port %d. Device disconnected\n"),
TRENTRY(OTGFS_TRACE1_TRNSFRFAILED, TR_FMT1, "OTGFS ERROR: Transfer Failed. ret=%d\n"), TRENTRY(OTGFS_TRACE1_IRQATTACH, TR_FMT1,
TRENTRY(OTGFS_TRACE1_SENDSETUP, TR_FMT1, "OTGFS ERROR: ctrl_sendsetup() failed with: %d\n"), "OTGFS ERROR: Failed to attach IRQ\n"),
TRENTRY(OTGFS_TRACE1_SENDDATA, TR_FMT1, "OTGFS ERROR: ctrl_senddata() failed with: %d\n"), TRENTRY(OTGFS_TRACE1_TRNSFRFAILED, TR_FMT1,
TRENTRY(OTGFS_TRACE1_RECVDATA, TR_FMT1, "OTGFS ERROR: ctrl_recvdata() failed with: %d\n"), "OTGFS ERROR: Transfer Failed. ret=%d\n"),
TRENTRY(OTGFS_TRACE1_SENDSETUP, TR_FMT1,
"OTGFS ERROR: ctrl_sendsetup() failed with: %d\n"),
TRENTRY(OTGFS_TRACE1_SENDDATA, TR_FMT1,
"OTGFS ERROR: ctrl_senddata() failed with: %d\n"),
TRENTRY(OTGFS_TRACE1_RECVDATA, TR_FMT1,
"OTGFS ERROR: ctrl_recvdata() failed with: %d\n"),
#ifdef HAVE_USBHOST_TRACE_VERBOSE #ifdef HAVE_USBHOST_TRACE_VERBOSE
TRENTRY(OTGFS_VTRACE1_CONNECTED, TR_FMT1, "OTGFS Host Port %d connected.\n"), TRENTRY(OTGFS_VTRACE1_CONNECTED, TR_FMT1,
TRENTRY(OTGFS_VTRACE1_DISCONNECTED, TR_FMT1, "OTGFS Host Port %d disconnected.\n"), "OTGFS Host Port %d connected.\n"),
TRENTRY(OTGFS_VTRACE1_GINT, TR_FMT1, "OTGFS Handling Interrupt. Entry Point.\n"), TRENTRY(OTGFS_VTRACE1_DISCONNECTED, TR_FMT1,
TRENTRY(OTGFS_VTRACE1_GINT_SOF, TR_FMT1, "OTGFS Handle the start of frame interrupt.\n"), "OTGFS Host Port %d disconnected.\n"),
TRENTRY(OTGFS_VTRACE1_GINT_RXFLVL, TR_FMT1, "OTGFS Handle the RxFIFO non-empty interrupt.\n"), TRENTRY(OTGFS_VTRACE1_GINT, TR_FMT1,
TRENTRY(OTGFS_VTRACE1_GINT_NPTXFE, TR_FMT1, "OTGFS Handle the non-periodic TxFIFO empty interrupt.\n"), "OTGFS Handling Interrupt. Entry Point.\n"),
TRENTRY(OTGFS_VTRACE1_GINT_PTXFE, TR_FMT1, "OTGFS Handle the periodic TxFIFO empty interrupt.\n"), TRENTRY(OTGFS_VTRACE1_GINT_SOF, TR_FMT1,
TRENTRY(OTGFS_VTRACE1_GINT_HC, TR_FMT1, "OTGFS Handle the host channels interrupt.\n"), "OTGFS Handle the start of frame interrupt.\n"),
TRENTRY(OTGFS_VTRACE1_GINT_HPRT, TR_FMT1, "OTGFS Handle the host port interrupt.\n"), TRENTRY(OTGFS_VTRACE1_GINT_RXFLVL, TR_FMT1,
TRENTRY(OTGFS_VTRACE1_GINT_HPRT_POCCHNG, TR_FMT1, "OTGFS HPRT: Port Over-Current Change.\n"), "OTGFS Handle the RxFIFO non-empty interrupt.\n"),
TRENTRY(OTGFS_VTRACE1_GINT_HPRT_PCDET, TR_FMT1, "OTGFS HPRT: Port Connect Detect.\n"), TRENTRY(OTGFS_VTRACE1_GINT_NPTXFE, TR_FMT1,
TRENTRY(OTGFS_VTRACE1_GINT_HPRT_PENCHNG, TR_FMT1, "OTGFS HPRT: Port Enable Changed.\n"), "OTGFS Handle the non-periodic TxFIFO empty interrupt.\n"),
TRENTRY(OTGFS_VTRACE1_GINT_HPRT_LSDEV, TR_FMT1, "OTGFS HPRT: Low Speed Device Connected.\n"), TRENTRY(OTGFS_VTRACE1_GINT_PTXFE, TR_FMT1,
TRENTRY(OTGFS_VTRACE1_GINT_HPRT_FSDEV, TR_FMT1, "OTGFS HPRT: Full Speed Device Connected.\n"), "OTGFS Handle the periodic TxFIFO empty interrupt.\n"),
TRENTRY(OTGFS_VTRACE1_GINT_HPRT_LSFSSW, TR_FMT1, "OTGFS HPRT: Host Switch: LS -> FS.\n"), TRENTRY(OTGFS_VTRACE1_GINT_HC, TR_FMT1,
TRENTRY(OTGFS_VTRACE1_GINT_HPRT_FSLSSW, TR_FMT1, "OTGFS HPRT: Host Switch: FS -> LS.\n"), "OTGFS Handle the host channels interrupt.\n"),
TRENTRY(OTGFS_VTRACE1_GINT_DISC, TR_FMT1, "OTGFS Handle the disconnect detected interrupt.\n"), TRENTRY(OTGFS_VTRACE1_GINT_HPRT, TR_FMT1,
TRENTRY(OTGFS_VTRACE1_GINT_IPXFR, TR_FMT1, "OTGFS Handle the incomplete periodic transfer.\n"), "OTGFS Handle the host port interrupt.\n"),
TRENTRY(OTGFS_VTRACE1_GINT_HPRT_POCCHNG, TR_FMT1,
"OTGFS HPRT: Port Over-Current Change.\n"),
TRENTRY(OTGFS_VTRACE1_GINT_HPRT_PCDET, TR_FMT1,
"OTGFS HPRT: Port Connect Detect.\n"),
TRENTRY(OTGFS_VTRACE1_GINT_HPRT_PENCHNG, TR_FMT1,
"OTGFS HPRT: Port Enable Changed.\n"),
TRENTRY(OTGFS_VTRACE1_GINT_HPRT_LSDEV, TR_FMT1,
"OTGFS HPRT: Low Speed Device Connected.\n"),
TRENTRY(OTGFS_VTRACE1_GINT_HPRT_FSDEV, TR_FMT1,
"OTGFS HPRT: Full Speed Device Connected.\n"),
TRENTRY(OTGFS_VTRACE1_GINT_HPRT_LSFSSW, TR_FMT1,
"OTGFS HPRT: Host Switch: LS -> FS.\n"),
TRENTRY(OTGFS_VTRACE1_GINT_HPRT_FSLSSW, TR_FMT1,
"OTGFS HPRT: Host Switch: FS -> LS.\n"),
TRENTRY(OTGFS_VTRACE1_GINT_DISC, TR_FMT1,
"OTGFS Handle the disconnect detected interrupt.\n"),
TRENTRY(OTGFS_VTRACE1_GINT_IPXFR, TR_FMT1,
"OTGFS Handle the incomplete periodic transfer.\n"),
#endif #endif
}; };
static const struct stm32l4_usbhost_trace_s g_trace2[TRACE2_NSTRINGS] = static const struct stm32l4_usbhost_trace_s g_trace2[TRACE2_NSTRINGS] =
{ {
TRENTRY(OTGFS_TRACE2_CLIP, TR_FMT2, "OTGFS CLIP: chidx: %d buflen: %d\n"), TRENTRY(OTGFS_TRACE2_CLIP, TR_FMT2,
"OTGFS CLIP: chidx: %d buflen: %d\n"),
#ifdef HAVE_USBHOST_TRACE_VERBOSE #ifdef HAVE_USBHOST_TRACE_VERBOSE
TRENTRY(OTGFS_VTRACE2_CHANWAKEUP_IN, TR_FMT2, "OTGFS EP%d(IN) wake up with result: %d\n"), TRENTRY(OTGFS_VTRACE2_CHANWAKEUP_IN, TR_FMT2,
TRENTRY(OTGFS_VTRACE2_CHANWAKEUP_OUT, TR_FMT2, "OTGFS EP%d(OUT) wake up with result: %d\n"), "OTGFS EP%d(IN) wake up with result: %d\n"),
TRENTRY(OTGFS_VTRACE2_CTRLIN, TR_FMT2, "OTGFS CTRL_IN type: %02x req: %02x\n"), TRENTRY(OTGFS_VTRACE2_CHANWAKEUP_OUT, TR_FMT2,
TRENTRY(OTGFS_VTRACE2_CTRLOUT, TR_FMT2, "OTGFS CTRL_OUT type: %02x req: %02x\n"), "OTGFS EP%d(OUT) wake up with result: %d\n"),
TRENTRY(OTGFS_VTRACE2_INTRIN, TR_FMT2, "OTGFS INTR_IN chidx: %02x len: %02x\n"), TRENTRY(OTGFS_VTRACE2_CTRLIN, TR_FMT2,
TRENTRY(OTGFS_VTRACE2_INTROUT, TR_FMT2, "OTGFS INTR_OUT chidx: %02x len: %02x\n"), "OTGFS CTRL_IN type: %02x req: %02x\n"),
TRENTRY(OTGFS_VTRACE2_BULKIN, TR_FMT2, "OTGFS BULK_IN chidx: %02x len: %02x\n"), TRENTRY(OTGFS_VTRACE2_CTRLOUT, TR_FMT2,
TRENTRY(OTGFS_VTRACE2_BULKOUT, TR_FMT2, "OTGFS BULK_OUT chidx: %02x len: %02x\n"), "OTGFS CTRL_OUT type: %02x req: %02x\n"),
TRENTRY(OTGFS_VTRACE2_ISOCIN, TR_FMT2, "OTGFS ISOC_IN chidx: %02x len: %04d\n"), TRENTRY(OTGFS_VTRACE2_INTRIN, TR_FMT2,
TRENTRY(OTGFS_VTRACE2_ISOCOUT, TR_FMT2, "OTGFS ISOC_OUT chidx: %02x req: %02x\n"), "OTGFS INTR_IN chidx: %02x len: %02x\n"),
TRENTRY(OTGFS_VTRACE2_STARTTRANSFER, TR_FMT2, "OTGFS Transfer chidx: %d buflen: %d\n"), TRENTRY(OTGFS_VTRACE2_INTROUT, TR_FMT2,
TRENTRY(OTGFS_VTRACE2_CHANCONF_CTRL_IN, TR_FMT2, "OTGFS Channel configured. chidx: %d: (EP%d,IN ,CTRL)\n"), "OTGFS INTR_OUT chidx: %02x len: %02x\n"),
TRENTRY(OTGFS_VTRACE2_CHANCONF_CTRL_OUT, TR_FMT2, "OTGFS Channel configured. chidx: %d: (EP%d,OUT,CTRL)\n"), TRENTRY(OTGFS_VTRACE2_BULKIN, TR_FMT2,
TRENTRY(OTGFS_VTRACE2_CHANCONF_INTR_IN, TR_FMT2, "OTGFS Channel configured. chidx: %d: (EP%d,IN ,INTR)\n"), "OTGFS BULK_IN chidx: %02x len: %02x\n"),
TRENTRY(OTGFS_VTRACE2_CHANCONF_INTR_OUT, TR_FMT2, "OTGFS Channel configured. chidx: %d: (EP%d,OUT,INTR)\n"), TRENTRY(OTGFS_VTRACE2_BULKOUT, TR_FMT2,
TRENTRY(OTGFS_VTRACE2_CHANCONF_BULK_IN, TR_FMT2, "OTGFS Channel configured. chidx: %d: (EP%d,IN ,BULK)\n"), "OTGFS BULK_OUT chidx: %02x len: %02x\n"),
TRENTRY(OTGFS_VTRACE2_CHANCONF_BULK_OUT, TR_FMT2, "OTGFS Channel configured. chidx: %d: (EP%d,OUT,BULK)\n"), TRENTRY(OTGFS_VTRACE2_ISOCIN, TR_FMT2,
TRENTRY(OTGFS_VTRACE2_CHANCONF_ISOC_IN, TR_FMT2, "OTGFS Channel configured. chidx: %d: (EP%d,IN ,ISOC)\n"), "OTGFS ISOC_IN chidx: %02x len: %04d\n"),
TRENTRY(OTGFS_VTRACE2_CHANCONF_ISOC_OUT, TR_FMT2, "OTGFS Channel configured. chidx: %d: (EP%d,OUT,ISOC)\n"), TRENTRY(OTGFS_VTRACE2_ISOCOUT, TR_FMT2,
TRENTRY(OTGFS_VTRACE2_CHANHALT, TR_FMT2, "OTGFS Channel halted. chidx: %d, reason: %d\n"), "OTGFS ISOC_OUT chidx: %02x req: %02x\n"),
TRENTRY(OTGFS_VTRACE2_STARTTRANSFER, TR_FMT2,
"OTGFS Transfer chidx: %d buflen: %d\n"),
TRENTRY(OTGFS_VTRACE2_CHANCONF_CTRL_IN, TR_FMT2,
"OTGFS Channel configured. chidx: %d: (EP%d,IN ,CTRL)\n"),
TRENTRY(OTGFS_VTRACE2_CHANCONF_CTRL_OUT, TR_FMT2,
"OTGFS Channel configured. chidx: %d: (EP%d,OUT,CTRL)\n"),
TRENTRY(OTGFS_VTRACE2_CHANCONF_INTR_IN, TR_FMT2,
"OTGFS Channel configured. chidx: %d: (EP%d,IN ,INTR)\n"),
TRENTRY(OTGFS_VTRACE2_CHANCONF_INTR_OUT, TR_FMT2,
"OTGFS Channel configured. chidx: %d: (EP%d,OUT,INTR)\n"),
TRENTRY(OTGFS_VTRACE2_CHANCONF_BULK_IN, TR_FMT2,
"OTGFS Channel configured. chidx: %d: (EP%d,IN ,BULK)\n"),
TRENTRY(OTGFS_VTRACE2_CHANCONF_BULK_OUT, TR_FMT2,
"OTGFS Channel configured. chidx: %d: (EP%d,OUT,BULK)\n"),
TRENTRY(OTGFS_VTRACE2_CHANCONF_ISOC_IN, TR_FMT2,
"OTGFS Channel configured. chidx: %d: (EP%d,IN ,ISOC)\n"),
TRENTRY(OTGFS_VTRACE2_CHANCONF_ISOC_OUT, TR_FMT2,
"OTGFS Channel configured. chidx: %d: (EP%d,OUT,ISOC)\n"),
TRENTRY(OTGFS_VTRACE2_CHANHALT, TR_FMT2,
"OTGFS Channel halted. chidx: %d, reason: %d\n"),
#endif #endif
}; };
arch/arm/src/stm32l4/stm32l4_userspace.h
+6 -6
View File
@@ -1,4 +1,4 @@
/************************************************************************************ /****************************************************************************
* arch/arm/src/stm32l4/stm32l4_userspace.h * arch/arm/src/stm32l4/stm32l4_userspace.h
* *
* Copyright (C) 2017 Gregory Nutt. All rights reserved. * Copyright (C) 2017 Gregory Nutt. All rights reserved.
@@ -31,20 +31,20 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE. * POSSIBILITY OF SUCH DAMAGE.
* *
************************************************************************************/ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_USERSPACE_H #ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_USERSPACE_H
#define __ARCH_ARM_SRC_STM32L4_STM32L4_USERSPACE_H #define __ARCH_ARM_SRC_STM32L4_STM32L4_USERSPACE_H
/************************************************************************************ /****************************************************************************
* Included Files * Included Files
************************************************************************************/ ****************************************************************************/
#include <nuttx/config.h> #include <nuttx/config.h>
/************************************************************************************ /****************************************************************************
* Public Function Prototypes * Public Function Prototypes
************************************************************************************/ ****************************************************************************/
/**************************************************************************** /****************************************************************************
* Name: stm32l4_userspace * Name: stm32l4_userspace
arch/arm/src/stm32l4/stm32l4_waste.h
+1 -1
View File
@@ -54,7 +54,7 @@ extern "C"
#endif #endif
/**************************************************************************** /****************************************************************************
* Public Functions * Public Function Prototypes
****************************************************************************/ ****************************************************************************/
/** Waste CPU Time /** Waste CPU Time
arch/arm/src/stm32l4/stm32l4_wdg.h
+3 -3
View File
@@ -63,7 +63,7 @@ extern "C"
#endif #endif
/**************************************************************************** /****************************************************************************
* Public Functions * Public Function Prototypes
****************************************************************************/ ****************************************************************************/
/**************************************************************************** /****************************************************************************
@@ -92,8 +92,8 @@ void stm32l4_iwdginitialize(FAR const char *devpath, uint32_t lsifreq);
* Name: stm32l4_wwdginitialize * Name: stm32l4_wwdginitialize
* *
* Description: * Description:
* Initialize the WWDG watchdog time. The watchdog timer is initialized and * Initialize the WWDG watchdog time. The watchdog timer is initialized
* registers as 'devpath. The initial state of the watchdog time is * and registers as 'devpath. The initial state of the watchdog time is
* disabled. * disabled.
* *
* Input Parameters: * Input Parameters:
arch/arm/src/stm32l4/stm32l4x3xx_rcc.c
+15 -10
View File
@@ -206,7 +206,7 @@ static inline void rcc_enableahb2(void)
#if STM32L4_NPORTS > 4 #if STM32L4_NPORTS > 4
| RCC_AHB2ENR_GPIOEEN | RCC_AHB2ENR_GPIOEEN
#endif #endif
/* These chips have no GPIOF, GPIOG or GPIOI */ /* These chips have no GPIOF, GPIOG or GPIOI */
#if STM32L4_NPORTS > 7 #if STM32L4_NPORTS > 7
| RCC_AHB2ENR_GPIOHEN | RCC_AHB2ENR_GPIOHEN
#endif #endif
@@ -404,7 +404,7 @@ static inline void rcc_enableapb1(void)
putreg32(regval, STM32L4_RCC_APB1ENR1); /* Enable peripherals */ putreg32(regval, STM32L4_RCC_APB1ENR1); /* Enable peripherals */
/* Second APB1 register */ /* Second APB1 register */
regval = getreg32(STM32L4_RCC_APB1ENR2); regval = getreg32(STM32L4_RCC_APB1ENR2);
@@ -454,8 +454,8 @@ static inline void rcc_enableapb2(void)
regval = getreg32(STM32L4_RCC_APB2ENR); regval = getreg32(STM32L4_RCC_APB2ENR);
#if defined(CONFIG_STM32L4_SYSCFG) || defined(CONFIG_STM32L4_COMP) #if defined(CONFIG_STM32L4_SYSCFG) || defined(CONFIG_STM32L4_COMP)
/* System configuration controller, comparators, and voltage reference buffer /* System configuration controller, comparators, and voltage reference
* clock enable * buffer clock enable
*/ */
regval |= RCC_APB2ENR_SYSCFGEN; regval |= RCC_APB2ENR_SYSCFGEN;
@@ -647,7 +647,8 @@ static void stm32l4_stdclockconfig(void)
for (timeout = MSIRDY_TIMEOUT; timeout > 0; timeout--) for (timeout = MSIRDY_TIMEOUT; timeout > 0; timeout--)
{ {
if ((regval = getreg32(STM32L4_RCC_CR)), (regval & RCC_CR_MSIRDY) || ~(regval & RCC_CR_MSION)) if ((regval = getreg32(STM32L4_RCC_CR)), (regval & RCC_CR_MSIRDY) ||
~(regval & RCC_CR_MSION))
{ {
/* If so, then break-out with timeout > 0 */ /* If so, then break-out with timeout > 0 */
@@ -764,8 +765,9 @@ static void stm32l4_stdclockconfig(void)
/* Set the PLL dividers and multipliers to configure the main PLL */ /* Set the PLL dividers and multipliers to configure the main PLL */
regval = (STM32L4_PLLCFG_PLLM | STM32L4_PLLCFG_PLLN | STM32L4_PLLCFG_PLLP regval = (STM32L4_PLLCFG_PLLM | STM32L4_PLLCFG_PLLN |
| STM32L4_PLLCFG_PLLQ | STM32L4_PLLCFG_PLLR); STM32L4_PLLCFG_PLLP | STM32L4_PLLCFG_PLLQ |
STM32L4_PLLCFG_PLLR);
#ifdef STM32L4_PLLCFG_PLLP_ENABLED #ifdef STM32L4_PLLCFG_PLLP_ENABLED
regval |= RCC_PLLCFG_PLLPEN; regval |= RCC_PLLCFG_PLLPEN;
@@ -833,7 +835,7 @@ static void stm32l4_stdclockconfig(void)
regval |= RCC_CR_PLLSAI1ON; regval |= RCC_CR_PLLSAI1ON;
putreg32(regval, STM32L4_RCC_CR); putreg32(regval, STM32L4_RCC_CR);
/* Wait until the PLL is ready */ /* Wait until the PLL is ready */
while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0) while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0)
{ {
@@ -875,7 +877,8 @@ static void stm32l4_stdclockconfig(void)
/* Enable FLASH prefetch, instruction cache, data cache, and 4 wait states */ /* Enable FLASH prefetch, instruction cache, data cache, and 4 wait states */
#ifdef CONFIG_STM32L4_FLASH_PREFETCH #ifdef CONFIG_STM32L4_FLASH_PREFETCH
regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN); regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN |
FLASH_ACR_PRFTEN);
#else #else
regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN); regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN);
#endif #endif
@@ -890,7 +893,8 @@ static void stm32l4_stdclockconfig(void)
/* Wait until the PLL source is used as the system clock source */ /* Wait until the PLL source is used as the system clock source */
while ((getreg32(STM32L4_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL) while ((getreg32(STM32L4_RCC_CFGR) & RCC_CFGR_SWS_MASK) !=
RCC_CFGR_SWS_PLL)
{ {
} }
@@ -911,6 +915,7 @@ static void stm32l4_stdclockconfig(void)
/* ensure Power control is enabled since it is indirectly required /* ensure Power control is enabled since it is indirectly required
* to alter the LSE parameters. * to alter the LSE parameters.
*/ */
stm32l4_pwr_enableclk(true); stm32l4_pwr_enableclk(true);
/* XXX other LSE settings must be made before turning on the oscillator /* XXX other LSE settings must be made before turning on the oscillator
arch/arm/src/stm32l4/stm32l4x5xx_rcc.c
+14 -10
View File
@@ -253,7 +253,6 @@ static inline void rcc_enableahb3(void)
regval |= RCC_AHB3ENR_FSMCEN; regval |= RCC_AHB3ENR_FSMCEN;
#endif #endif
#ifdef CONFIG_STM32L4_QSPI #ifdef CONFIG_STM32L4_QSPI
/* QuadSPI module clock enable */ /* QuadSPI module clock enable */
@@ -403,7 +402,7 @@ static inline void rcc_enableapb1(void)
putreg32(regval, STM32L4_RCC_APB1ENR1); /* Enable peripherals */ putreg32(regval, STM32L4_RCC_APB1ENR1); /* Enable peripherals */
/* Second APB1 register */ /* Second APB1 register */
regval = getreg32(STM32L4_RCC_APB1ENR2); regval = getreg32(STM32L4_RCC_APB1ENR2);
@@ -447,8 +446,8 @@ static inline void rcc_enableapb2(void)
regval = getreg32(STM32L4_RCC_APB2ENR); regval = getreg32(STM32L4_RCC_APB2ENR);
#if defined(CONFIG_STM32L4_SYSCFG) || defined(CONFIG_STM32L4_COMP) #if defined(CONFIG_STM32L4_SYSCFG) || defined(CONFIG_STM32L4_COMP)
/* System configuration controller, comparators, and voltage reference buffer /* System configuration controller, comparators, and voltage reference
* clock enable * buffer clock enable
*/ */
regval |= RCC_APB2ENR_SYSCFGEN; regval |= RCC_APB2ENR_SYSCFGEN;
@@ -638,7 +637,8 @@ static void stm32l4_stdclockconfig(void)
for (timeout = MSIRDY_TIMEOUT; timeout > 0; timeout--) for (timeout = MSIRDY_TIMEOUT; timeout > 0; timeout--)
{ {
if ((regval = getreg32(STM32L4_RCC_CR)), (regval & RCC_CR_MSIRDY) || ~(regval & RCC_CR_MSION)) if ((regval = getreg32(STM32L4_RCC_CR)), (regval & RCC_CR_MSIRDY) ||
~(regval & RCC_CR_MSION))
{ {
/* If so, then break-out with timeout > 0 */ /* If so, then break-out with timeout > 0 */
@@ -755,8 +755,9 @@ static void stm32l4_stdclockconfig(void)
/* Set the PLL dividers and multipliers to configure the main PLL */ /* Set the PLL dividers and multipliers to configure the main PLL */
regval = (STM32L4_PLLCFG_PLLM | STM32L4_PLLCFG_PLLN | STM32L4_PLLCFG_PLLP regval = (STM32L4_PLLCFG_PLLM | STM32L4_PLLCFG_PLLN |
| STM32L4_PLLCFG_PLLQ | STM32L4_PLLCFG_PLLR); STM32L4_PLLCFG_PLLP | STM32L4_PLLCFG_PLLQ |
STM32L4_PLLCFG_PLLR);
#ifdef STM32L4_PLLCFG_PLLP_ENABLED #ifdef STM32L4_PLLCFG_PLLP_ENABLED
regval |= RCC_PLLCFG_PLLPEN; regval |= RCC_PLLCFG_PLLPEN;
@@ -824,7 +825,7 @@ static void stm32l4_stdclockconfig(void)
regval |= RCC_CR_PLLSAI1ON; regval |= RCC_CR_PLLSAI1ON;
putreg32(regval, STM32L4_RCC_CR); putreg32(regval, STM32L4_RCC_CR);
/* Wait until the PLL is ready */ /* Wait until the PLL is ready */
while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0) while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0)
{ {
@@ -866,7 +867,8 @@ static void stm32l4_stdclockconfig(void)
/* Enable FLASH prefetch, instruction cache, data cache, and 4 wait states */ /* Enable FLASH prefetch, instruction cache, data cache, and 4 wait states */
#ifdef CONFIG_STM32L4_FLASH_PREFETCH #ifdef CONFIG_STM32L4_FLASH_PREFETCH
regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN); regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN |
FLASH_ACR_PRFTEN);
#else #else
regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN); regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN);
#endif #endif
@@ -881,7 +883,8 @@ static void stm32l4_stdclockconfig(void)
/* Wait until the PLL source is used as the system clock source */ /* Wait until the PLL source is used as the system clock source */
while ((getreg32(STM32L4_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL) while ((getreg32(STM32L4_RCC_CFGR) & RCC_CFGR_SWS_MASK) !=
RCC_CFGR_SWS_PLL)
{ {
} }
@@ -902,6 +905,7 @@ static void stm32l4_stdclockconfig(void)
/* ensure Power control is enabled since it is indirectly required /* ensure Power control is enabled since it is indirectly required
* to alter the LSE parameters. * to alter the LSE parameters.
*/ */
stm32l4_pwr_enableclk(true); stm32l4_pwr_enableclk(true);
/* XXX other LSE settings must be made before turning on the oscillator /* XXX other LSE settings must be made before turning on the oscillator
arch/arm/src/stm32l4/stm32l4x6xx_rcc.c
+14 -10
View File
@@ -289,7 +289,6 @@ static inline void rcc_enableahb3(void)
regval |= RCC_AHB3ENR_FSMCEN; regval |= RCC_AHB3ENR_FSMCEN;
#endif #endif
#ifdef CONFIG_STM32L4_QSPI #ifdef CONFIG_STM32L4_QSPI
/* QuadSPI module clock enable */ /* QuadSPI module clock enable */
@@ -460,7 +459,7 @@ static inline void rcc_enableapb1(void)
putreg32(regval, STM32L4_RCC_APB1ENR1); /* Enable peripherals */ putreg32(regval, STM32L4_RCC_APB1ENR1); /* Enable peripherals */
/* Second APB1 register */ /* Second APB1 register */
regval = getreg32(STM32L4_RCC_APB1ENR2); regval = getreg32(STM32L4_RCC_APB1ENR2);
@@ -510,8 +509,8 @@ static inline void rcc_enableapb2(void)
regval = getreg32(STM32L4_RCC_APB2ENR); regval = getreg32(STM32L4_RCC_APB2ENR);
#if defined(CONFIG_STM32L4_SYSCFG) || defined(CONFIG_STM32L4_COMP) #if defined(CONFIG_STM32L4_SYSCFG) || defined(CONFIG_STM32L4_COMP)
/* System configuration controller, comparators, and voltage reference buffer /* System configuration controller, comparators, and voltage reference
* clock enable * buffer clock enable
*/ */
regval |= RCC_APB2ENR_SYSCFGEN; regval |= RCC_APB2ENR_SYSCFGEN;
@@ -715,7 +714,8 @@ static void stm32l4_stdclockconfig(void)
for (timeout = MSIRDY_TIMEOUT; timeout > 0; timeout--) for (timeout = MSIRDY_TIMEOUT; timeout > 0; timeout--)
{ {
if ((regval = getreg32(STM32L4_RCC_CR)), (regval & RCC_CR_MSIRDY) || ~(regval & RCC_CR_MSION)) if ((regval = getreg32(STM32L4_RCC_CR)), (regval & RCC_CR_MSIRDY) ||
~(regval & RCC_CR_MSION))
{ {
/* If so, then break-out with timeout > 0 */ /* If so, then break-out with timeout > 0 */
@@ -832,8 +832,9 @@ static void stm32l4_stdclockconfig(void)
/* Set the PLL dividers and multipliers to configure the main PLL */ /* Set the PLL dividers and multipliers to configure the main PLL */
regval = (STM32L4_PLLCFG_PLLM | STM32L4_PLLCFG_PLLN | STM32L4_PLLCFG_PLLP regval = (STM32L4_PLLCFG_PLLM | STM32L4_PLLCFG_PLLN |
| STM32L4_PLLCFG_PLLQ | STM32L4_PLLCFG_PLLR); STM32L4_PLLCFG_PLLP | STM32L4_PLLCFG_PLLQ |
STM32L4_PLLCFG_PLLR);
#ifdef STM32L4_PLLCFG_PLLP_ENABLED #ifdef STM32L4_PLLCFG_PLLP_ENABLED
regval |= RCC_PLLCFG_PLLPEN; regval |= RCC_PLLCFG_PLLPEN;
@@ -901,7 +902,7 @@ static void stm32l4_stdclockconfig(void)
regval |= RCC_CR_PLLSAI1ON; regval |= RCC_CR_PLLSAI1ON;
putreg32(regval, STM32L4_RCC_CR); putreg32(regval, STM32L4_RCC_CR);
/* Wait until the PLL is ready */ /* Wait until the PLL is ready */
while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0) while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0)
{ {
@@ -943,7 +944,8 @@ static void stm32l4_stdclockconfig(void)
/* Enable FLASH prefetch, instruction cache, data cache, and 4 wait states */ /* Enable FLASH prefetch, instruction cache, data cache, and 4 wait states */
#ifdef CONFIG_STM32L4_FLASH_PREFETCH #ifdef CONFIG_STM32L4_FLASH_PREFETCH
regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN); regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN |
FLASH_ACR_PRFTEN);
#else #else
regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN); regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN);
#endif #endif
@@ -958,7 +960,8 @@ static void stm32l4_stdclockconfig(void)
/* Wait until the PLL source is used as the system clock source */ /* Wait until the PLL source is used as the system clock source */
while ((getreg32(STM32L4_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL) while ((getreg32(STM32L4_RCC_CFGR) & RCC_CFGR_SWS_MASK) !=
RCC_CFGR_SWS_PLL)
{ {
} }
@@ -987,6 +990,7 @@ static void stm32l4_stdclockconfig(void)
/* ensure Power control is enabled since it is indirectly required /* ensure Power control is enabled since it is indirectly required
* to alter the LSE parameters. * to alter the LSE parameters.
*/ */
stm32l4_pwr_enableclk(true); stm32l4_pwr_enableclk(true);
/* XXX other LSE settings must be made before turning on the oscillator /* XXX other LSE settings must be made before turning on the oscillator
arch/arm/src/stm32l4/stm32l4xrxx_dma.c
+203 -167
View File
File diff suppressed because it is too large Load Diff
arch/arm/src/stm32l4/stm32l4xrxx_rcc.c
+12 -8
View File
@@ -453,7 +453,7 @@ static inline void rcc_enableapb1(void)
putreg32(regval, STM32L4_RCC_APB1ENR1); /* Enable peripherals */ putreg32(regval, STM32L4_RCC_APB1ENR1); /* Enable peripherals */
/* Second APB1 register */ /* Second APB1 register */
regval = getreg32(STM32L4_RCC_APB1ENR2); regval = getreg32(STM32L4_RCC_APB1ENR2);
@@ -497,8 +497,8 @@ static inline void rcc_enableapb2(void)
regval = getreg32(STM32L4_RCC_APB2ENR); regval = getreg32(STM32L4_RCC_APB2ENR);
#if defined(CONFIG_STM32L4_SYSCFG) || defined(CONFIG_STM32L4_COMP) #if defined(CONFIG_STM32L4_SYSCFG) || defined(CONFIG_STM32L4_COMP)
/* System configuration controller, comparators, and voltage reference buffer /* System configuration controller, comparators, and voltage reference
* clock enable * buffer clock enable
*/ */
regval |= RCC_APB2ENR_SYSCFGEN; regval |= RCC_APB2ENR_SYSCFGEN;
@@ -700,7 +700,9 @@ static void stm32l4_stdclockconfig(void)
for (timeout = MSIRDY_TIMEOUT; timeout > 0; timeout--) for (timeout = MSIRDY_TIMEOUT; timeout > 0; timeout--)
{ {
if ((regval = getreg32(STM32L4_RCC_CR)), (regval & RCC_CR_MSIRDY) || ~(regval & RCC_CR_MSION)) regval = getreg32(STM32L4_RCC_CR);
if ((regval & RCC_CR_MSIRDY) || ~(regval & RCC_CR_MSION))
{ {
/* If so, then break-out with timeout > 0 */ /* If so, then break-out with timeout > 0 */
@@ -821,8 +823,9 @@ static void stm32l4_stdclockconfig(void)
/* Set the PLL dividers and multipliers to configure the main PLL */ /* Set the PLL dividers and multipliers to configure the main PLL */
regval = (STM32L4_PLLCFG_PLLM | STM32L4_PLLCFG_PLLN | STM32L4_PLLCFG_PLLP regval = (STM32L4_PLLCFG_PLLM | STM32L4_PLLCFG_PLLN |
| STM32L4_PLLCFG_PLLQ | STM32L4_PLLCFG_PLLR); STM32L4_PLLCFG_PLLP | STM32L4_PLLCFG_PLLQ |
STM32L4_PLLCFG_PLLR);
#ifdef STM32L4_PLLCFG_PLLP_ENABLED #ifdef STM32L4_PLLCFG_PLLP_ENABLED
regval |= RCC_PLLCFG_PLLPEN; regval |= RCC_PLLCFG_PLLPEN;
@@ -890,7 +893,7 @@ static void stm32l4_stdclockconfig(void)
regval |= RCC_CR_PLLSAI1ON; regval |= RCC_CR_PLLSAI1ON;
putreg32(regval, STM32L4_RCC_CR); putreg32(regval, STM32L4_RCC_CR);
/* Wait until the PLL is ready */ /* Wait until the PLL is ready */
while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0) while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0)
{ {
@@ -955,7 +958,8 @@ static void stm32l4_stdclockconfig(void)
/* Wait until the PLL source is used as the system clock source */ /* Wait until the PLL source is used as the system clock source */
while ((getreg32(STM32L4_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL) while ((getreg32(STM32L4_RCC_CFGR) & RCC_CFGR_SWS_MASK) !=
RCC_CFGR_SWS_PLL)
{ {
} }