mirror of
https://github.com/apache/nuttx.git
synced 2026-05-23 23:28:29 +08:00
Fix nxstyle to stm32l4 files (#721)
* Fix nxstyle for usbhost, userspace, wdg, rcc, dma, rcc etc
This commit is contained in:
Alan Carvalho de Assis
committed by
GitHub
GitHub
parent
460124629c
commit
de188fbe85
@@ -1,4 +1,4 @@
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/************************************************************************************
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/****************************************************************************
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* arch/arm/src/stm32l4/stm32l4_usbhost.h
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*
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* Copyright (C) 2012, 2014 Gregory Nutt. All rights reserved.
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@@ -32,14 +32,14 @@
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_USBHOST_H
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#define __ARCH_ARM_SRC_STM32L4_STM32L4_USBHOST_H
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/************************************************************************************
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/****************************************************************************
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* Included Files
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************************************************************************************/
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****************************************************************************/
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#include <nuttx/config.h>
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#include <nuttx/usb/usbhost.h>
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@@ -58,9 +58,9 @@
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# error "Unsupported STM32L4 chip"
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#endif
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/************************************************************************************
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/****************************************************************************
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* Public Types
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************************************************************************************/
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****************************************************************************/
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#ifdef HAVE_USBHOST_TRACE
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enum usbhost_trace1codes_e
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@@ -85,7 +85,7 @@ enum usbhost_trace1codes_e
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OTGFS_VTRACE1_GINT_PTXFE, /* OTGFS Handle the periodic TxFIFO empty interrupt */
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OTGFS_VTRACE1_GINT_HC, /* OTGFS Handle the host channels interrupt */
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OTGFS_VTRACE1_GINT_HPRT, /* OTGFS Handle the host port interrupt */
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OTGFS_VTRACE1_GINT_HPRT_POCCHNG, /* OTGFS HPRT: Port Over-Current Change*/
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OTGFS_VTRACE1_GINT_HPRT_POCCHNG, /* OTGFS HPRT: Port Over-Current Change */
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OTGFS_VTRACE1_GINT_HPRT_PCDET, /* OTGFS HPRT: Port Connect Detect */
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OTGFS_VTRACE1_GINT_HPRT_PENCHNG, /* OTGFS HPRT: Port Enable Changed */
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OTGFS_VTRACE1_GINT_HPRT_LSDEV, /* OTGFS HPRT: Low Speed Device Connected */
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@@ -139,11 +139,11 @@ enum usbhost_trace1codes_e
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#endif
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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/*
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* STM32L4 USB OTG FS Host Driver Support
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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/* STM32L4 USB OTG FS Host Driver Support
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*
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* Pre-requisites
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*
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@@ -157,8 +157,8 @@ enum usbhost_trace1codes_e
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* Default 128 (512 bytes)
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* CONFIG_STM32L4_OTGFS_NPTXFIFO_SIZE - Size of the non-periodic Tx FIFO
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* in 32-bit words. Default 96 (384 bytes)
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* CONFIG_STM32L4_OTGFS_PTXFIFO_SIZE - Size of the periodic Tx FIFO in 32-bit
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* words. Default 96 (384 bytes)
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* CONFIG_STM32L4_OTGFS_PTXFIFO_SIZE - Size of the periodic Tx FIFO in
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* 32-bit words. Default 96 (384 bytes)
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* CONFIG_STM32L4_OTGFS_SOFINTR - Enable SOF interrupts. Why would you ever
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* want to do that?
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*
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@@ -166,9 +166,9 @@ enum usbhost_trace1codes_e
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* debug. Depends on CONFIG_DEBUG.
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*/
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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#ifndef __ASSEMBLY__
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@@ -181,31 +181,34 @@ extern "C"
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#define EXTERN extern
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#endif
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/***********************************************************************************
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/****************************************************************************
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* Name: stm32l4_usbhost_vbusdrive
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*
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* Description:
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* Enable/disable driving of VBUS 5V output. This function must be provided be
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* each platform that implements the STM32L4 OTG FS host interface
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* Enable/disable driving of VBUS 5V output. This function must be
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* provided be each platform that implements the STM32L4 OTG FS host
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* interface
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*
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* "On-chip 5 V VBUS generation is not supported. For this reason, a charge pump
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* or, if 5 V are available on the application board, a basic power switch, must
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* be added externally to drive the 5 V VBUS line. The external charge pump can
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* be driven by any GPIO output. When the application decides to power on VBUS
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* using the chosen GPIO, it must also set the port power bit in the host port
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* control and status register (PPWR bit in OTG_FS_HPRT).
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* "On-chip 5 V VBUS generation is not supported. For this reason, a charge
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* pump or, if 5 V are available on the application board, a basic power
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* switch, must be added externally to drive the 5 V VBUS line. The
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* external charge pump can be driven by any GPIO output. When the
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* application decides to power on VBUS using the chosen GPIO, it must
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* also set the port power bit in the host port control and status
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* register (PPWR bit in OTG_FS_HPRT).
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*
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* "The application uses this field to control power to this port, and the core
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* clears this bit on an over current condition."
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* "The application uses this field to control power to this port, and the
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* core clears this bit on an over current condition."
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*
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* Input Parameters:
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* iface - For future growth to handle multiple USB host interface. Should be zero.
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* iface - For future growth to handle multiple USB host interface.
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* Should be zero.
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* enable - true: enable VBUS power; false: disable VBUS power
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*
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* Returned Value:
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* None
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*
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***********************************************************************************/
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****************************************************************************/
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void stm32l4_usbhost_vbusdrive(int iface, bool enable);
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@@ -80,63 +80,108 @@ struct stm32l4_usbhost_trace_s
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static const struct stm32l4_usbhost_trace_s g_trace1[TRACE1_NSTRINGS] =
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{
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TRENTRY(OTGFS_TRACE1_DEVDISCONN, TR_FMT1, "OTGFS ERROR: Host Port %d. Device disconnected\n"),
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TRENTRY(OTGFS_TRACE1_IRQATTACH, TR_FMT1, "OTGFS ERROR: Failed to attach IRQ\n"),
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TRENTRY(OTGFS_TRACE1_TRNSFRFAILED, TR_FMT1, "OTGFS ERROR: Transfer Failed. ret=%d\n"),
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TRENTRY(OTGFS_TRACE1_SENDSETUP, TR_FMT1, "OTGFS ERROR: ctrl_sendsetup() failed with: %d\n"),
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TRENTRY(OTGFS_TRACE1_SENDDATA, TR_FMT1, "OTGFS ERROR: ctrl_senddata() failed with: %d\n"),
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TRENTRY(OTGFS_TRACE1_RECVDATA, TR_FMT1, "OTGFS ERROR: ctrl_recvdata() failed with: %d\n"),
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TRENTRY(OTGFS_TRACE1_DEVDISCONN, TR_FMT1,
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"OTGFS ERROR: Host Port %d. Device disconnected\n"),
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TRENTRY(OTGFS_TRACE1_IRQATTACH, TR_FMT1,
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"OTGFS ERROR: Failed to attach IRQ\n"),
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TRENTRY(OTGFS_TRACE1_TRNSFRFAILED, TR_FMT1,
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"OTGFS ERROR: Transfer Failed. ret=%d\n"),
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TRENTRY(OTGFS_TRACE1_SENDSETUP, TR_FMT1,
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"OTGFS ERROR: ctrl_sendsetup() failed with: %d\n"),
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TRENTRY(OTGFS_TRACE1_SENDDATA, TR_FMT1,
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"OTGFS ERROR: ctrl_senddata() failed with: %d\n"),
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TRENTRY(OTGFS_TRACE1_RECVDATA, TR_FMT1,
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"OTGFS ERROR: ctrl_recvdata() failed with: %d\n"),
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#ifdef HAVE_USBHOST_TRACE_VERBOSE
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TRENTRY(OTGFS_VTRACE1_CONNECTED, TR_FMT1, "OTGFS Host Port %d connected.\n"),
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TRENTRY(OTGFS_VTRACE1_DISCONNECTED, TR_FMT1, "OTGFS Host Port %d disconnected.\n"),
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TRENTRY(OTGFS_VTRACE1_GINT, TR_FMT1, "OTGFS Handling Interrupt. Entry Point.\n"),
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TRENTRY(OTGFS_VTRACE1_GINT_SOF, TR_FMT1, "OTGFS Handle the start of frame interrupt.\n"),
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TRENTRY(OTGFS_VTRACE1_GINT_RXFLVL, TR_FMT1, "OTGFS Handle the RxFIFO non-empty interrupt.\n"),
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TRENTRY(OTGFS_VTRACE1_GINT_NPTXFE, TR_FMT1, "OTGFS Handle the non-periodic TxFIFO empty interrupt.\n"),
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TRENTRY(OTGFS_VTRACE1_GINT_PTXFE, TR_FMT1, "OTGFS Handle the periodic TxFIFO empty interrupt.\n"),
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TRENTRY(OTGFS_VTRACE1_GINT_HC, TR_FMT1, "OTGFS Handle the host channels interrupt.\n"),
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TRENTRY(OTGFS_VTRACE1_GINT_HPRT, TR_FMT1, "OTGFS Handle the host port interrupt.\n"),
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TRENTRY(OTGFS_VTRACE1_GINT_HPRT_POCCHNG, TR_FMT1, "OTGFS HPRT: Port Over-Current Change.\n"),
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TRENTRY(OTGFS_VTRACE1_GINT_HPRT_PCDET, TR_FMT1, "OTGFS HPRT: Port Connect Detect.\n"),
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TRENTRY(OTGFS_VTRACE1_GINT_HPRT_PENCHNG, TR_FMT1, "OTGFS HPRT: Port Enable Changed.\n"),
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TRENTRY(OTGFS_VTRACE1_GINT_HPRT_LSDEV, TR_FMT1, "OTGFS HPRT: Low Speed Device Connected.\n"),
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TRENTRY(OTGFS_VTRACE1_GINT_HPRT_FSDEV, TR_FMT1, "OTGFS HPRT: Full Speed Device Connected.\n"),
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TRENTRY(OTGFS_VTRACE1_GINT_HPRT_LSFSSW, TR_FMT1, "OTGFS HPRT: Host Switch: LS -> FS.\n"),
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TRENTRY(OTGFS_VTRACE1_GINT_HPRT_FSLSSW, TR_FMT1, "OTGFS HPRT: Host Switch: FS -> LS.\n"),
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TRENTRY(OTGFS_VTRACE1_GINT_DISC, TR_FMT1, "OTGFS Handle the disconnect detected interrupt.\n"),
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TRENTRY(OTGFS_VTRACE1_GINT_IPXFR, TR_FMT1, "OTGFS Handle the incomplete periodic transfer.\n"),
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TRENTRY(OTGFS_VTRACE1_CONNECTED, TR_FMT1,
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"OTGFS Host Port %d connected.\n"),
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TRENTRY(OTGFS_VTRACE1_DISCONNECTED, TR_FMT1,
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"OTGFS Host Port %d disconnected.\n"),
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TRENTRY(OTGFS_VTRACE1_GINT, TR_FMT1,
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"OTGFS Handling Interrupt. Entry Point.\n"),
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TRENTRY(OTGFS_VTRACE1_GINT_SOF, TR_FMT1,
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"OTGFS Handle the start of frame interrupt.\n"),
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TRENTRY(OTGFS_VTRACE1_GINT_RXFLVL, TR_FMT1,
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"OTGFS Handle the RxFIFO non-empty interrupt.\n"),
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TRENTRY(OTGFS_VTRACE1_GINT_NPTXFE, TR_FMT1,
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"OTGFS Handle the non-periodic TxFIFO empty interrupt.\n"),
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TRENTRY(OTGFS_VTRACE1_GINT_PTXFE, TR_FMT1,
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"OTGFS Handle the periodic TxFIFO empty interrupt.\n"),
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TRENTRY(OTGFS_VTRACE1_GINT_HC, TR_FMT1,
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"OTGFS Handle the host channels interrupt.\n"),
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TRENTRY(OTGFS_VTRACE1_GINT_HPRT, TR_FMT1,
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"OTGFS Handle the host port interrupt.\n"),
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TRENTRY(OTGFS_VTRACE1_GINT_HPRT_POCCHNG, TR_FMT1,
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"OTGFS HPRT: Port Over-Current Change.\n"),
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TRENTRY(OTGFS_VTRACE1_GINT_HPRT_PCDET, TR_FMT1,
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"OTGFS HPRT: Port Connect Detect.\n"),
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TRENTRY(OTGFS_VTRACE1_GINT_HPRT_PENCHNG, TR_FMT1,
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"OTGFS HPRT: Port Enable Changed.\n"),
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TRENTRY(OTGFS_VTRACE1_GINT_HPRT_LSDEV, TR_FMT1,
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"OTGFS HPRT: Low Speed Device Connected.\n"),
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TRENTRY(OTGFS_VTRACE1_GINT_HPRT_FSDEV, TR_FMT1,
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"OTGFS HPRT: Full Speed Device Connected.\n"),
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TRENTRY(OTGFS_VTRACE1_GINT_HPRT_LSFSSW, TR_FMT1,
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"OTGFS HPRT: Host Switch: LS -> FS.\n"),
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TRENTRY(OTGFS_VTRACE1_GINT_HPRT_FSLSSW, TR_FMT1,
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"OTGFS HPRT: Host Switch: FS -> LS.\n"),
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TRENTRY(OTGFS_VTRACE1_GINT_DISC, TR_FMT1,
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"OTGFS Handle the disconnect detected interrupt.\n"),
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TRENTRY(OTGFS_VTRACE1_GINT_IPXFR, TR_FMT1,
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"OTGFS Handle the incomplete periodic transfer.\n"),
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#endif
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};
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static const struct stm32l4_usbhost_trace_s g_trace2[TRACE2_NSTRINGS] =
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{
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TRENTRY(OTGFS_TRACE2_CLIP, TR_FMT2, "OTGFS CLIP: chidx: %d buflen: %d\n"),
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TRENTRY(OTGFS_TRACE2_CLIP, TR_FMT2,
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"OTGFS CLIP: chidx: %d buflen: %d\n"),
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#ifdef HAVE_USBHOST_TRACE_VERBOSE
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TRENTRY(OTGFS_VTRACE2_CHANWAKEUP_IN, TR_FMT2, "OTGFS EP%d(IN) wake up with result: %d\n"),
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TRENTRY(OTGFS_VTRACE2_CHANWAKEUP_OUT, TR_FMT2, "OTGFS EP%d(OUT) wake up with result: %d\n"),
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TRENTRY(OTGFS_VTRACE2_CTRLIN, TR_FMT2, "OTGFS CTRL_IN type: %02x req: %02x\n"),
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TRENTRY(OTGFS_VTRACE2_CTRLOUT, TR_FMT2, "OTGFS CTRL_OUT type: %02x req: %02x\n"),
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TRENTRY(OTGFS_VTRACE2_INTRIN, TR_FMT2, "OTGFS INTR_IN chidx: %02x len: %02x\n"),
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TRENTRY(OTGFS_VTRACE2_INTROUT, TR_FMT2, "OTGFS INTR_OUT chidx: %02x len: %02x\n"),
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TRENTRY(OTGFS_VTRACE2_BULKIN, TR_FMT2, "OTGFS BULK_IN chidx: %02x len: %02x\n"),
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TRENTRY(OTGFS_VTRACE2_BULKOUT, TR_FMT2, "OTGFS BULK_OUT chidx: %02x len: %02x\n"),
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TRENTRY(OTGFS_VTRACE2_ISOCIN, TR_FMT2, "OTGFS ISOC_IN chidx: %02x len: %04d\n"),
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TRENTRY(OTGFS_VTRACE2_ISOCOUT, TR_FMT2, "OTGFS ISOC_OUT chidx: %02x req: %02x\n"),
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TRENTRY(OTGFS_VTRACE2_STARTTRANSFER, TR_FMT2, "OTGFS Transfer chidx: %d buflen: %d\n"),
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TRENTRY(OTGFS_VTRACE2_CHANCONF_CTRL_IN, TR_FMT2, "OTGFS Channel configured. chidx: %d: (EP%d,IN ,CTRL)\n"),
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TRENTRY(OTGFS_VTRACE2_CHANCONF_CTRL_OUT, TR_FMT2, "OTGFS Channel configured. chidx: %d: (EP%d,OUT,CTRL)\n"),
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TRENTRY(OTGFS_VTRACE2_CHANCONF_INTR_IN, TR_FMT2, "OTGFS Channel configured. chidx: %d: (EP%d,IN ,INTR)\n"),
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TRENTRY(OTGFS_VTRACE2_CHANCONF_INTR_OUT, TR_FMT2, "OTGFS Channel configured. chidx: %d: (EP%d,OUT,INTR)\n"),
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TRENTRY(OTGFS_VTRACE2_CHANCONF_BULK_IN, TR_FMT2, "OTGFS Channel configured. chidx: %d: (EP%d,IN ,BULK)\n"),
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TRENTRY(OTGFS_VTRACE2_CHANCONF_BULK_OUT, TR_FMT2, "OTGFS Channel configured. chidx: %d: (EP%d,OUT,BULK)\n"),
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TRENTRY(OTGFS_VTRACE2_CHANCONF_ISOC_IN, TR_FMT2, "OTGFS Channel configured. chidx: %d: (EP%d,IN ,ISOC)\n"),
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TRENTRY(OTGFS_VTRACE2_CHANCONF_ISOC_OUT, TR_FMT2, "OTGFS Channel configured. chidx: %d: (EP%d,OUT,ISOC)\n"),
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TRENTRY(OTGFS_VTRACE2_CHANHALT, TR_FMT2, "OTGFS Channel halted. chidx: %d, reason: %d\n"),
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TRENTRY(OTGFS_VTRACE2_CHANWAKEUP_IN, TR_FMT2,
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"OTGFS EP%d(IN) wake up with result: %d\n"),
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TRENTRY(OTGFS_VTRACE2_CHANWAKEUP_OUT, TR_FMT2,
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"OTGFS EP%d(OUT) wake up with result: %d\n"),
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TRENTRY(OTGFS_VTRACE2_CTRLIN, TR_FMT2,
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"OTGFS CTRL_IN type: %02x req: %02x\n"),
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TRENTRY(OTGFS_VTRACE2_CTRLOUT, TR_FMT2,
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"OTGFS CTRL_OUT type: %02x req: %02x\n"),
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TRENTRY(OTGFS_VTRACE2_INTRIN, TR_FMT2,
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"OTGFS INTR_IN chidx: %02x len: %02x\n"),
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TRENTRY(OTGFS_VTRACE2_INTROUT, TR_FMT2,
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"OTGFS INTR_OUT chidx: %02x len: %02x\n"),
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TRENTRY(OTGFS_VTRACE2_BULKIN, TR_FMT2,
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"OTGFS BULK_IN chidx: %02x len: %02x\n"),
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TRENTRY(OTGFS_VTRACE2_BULKOUT, TR_FMT2,
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"OTGFS BULK_OUT chidx: %02x len: %02x\n"),
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TRENTRY(OTGFS_VTRACE2_ISOCIN, TR_FMT2,
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"OTGFS ISOC_IN chidx: %02x len: %04d\n"),
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TRENTRY(OTGFS_VTRACE2_ISOCOUT, TR_FMT2,
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"OTGFS ISOC_OUT chidx: %02x req: %02x\n"),
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TRENTRY(OTGFS_VTRACE2_STARTTRANSFER, TR_FMT2,
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"OTGFS Transfer chidx: %d buflen: %d\n"),
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TRENTRY(OTGFS_VTRACE2_CHANCONF_CTRL_IN, TR_FMT2,
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"OTGFS Channel configured. chidx: %d: (EP%d,IN ,CTRL)\n"),
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TRENTRY(OTGFS_VTRACE2_CHANCONF_CTRL_OUT, TR_FMT2,
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"OTGFS Channel configured. chidx: %d: (EP%d,OUT,CTRL)\n"),
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TRENTRY(OTGFS_VTRACE2_CHANCONF_INTR_IN, TR_FMT2,
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"OTGFS Channel configured. chidx: %d: (EP%d,IN ,INTR)\n"),
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TRENTRY(OTGFS_VTRACE2_CHANCONF_INTR_OUT, TR_FMT2,
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"OTGFS Channel configured. chidx: %d: (EP%d,OUT,INTR)\n"),
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TRENTRY(OTGFS_VTRACE2_CHANCONF_BULK_IN, TR_FMT2,
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"OTGFS Channel configured. chidx: %d: (EP%d,IN ,BULK)\n"),
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TRENTRY(OTGFS_VTRACE2_CHANCONF_BULK_OUT, TR_FMT2,
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"OTGFS Channel configured. chidx: %d: (EP%d,OUT,BULK)\n"),
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TRENTRY(OTGFS_VTRACE2_CHANCONF_ISOC_IN, TR_FMT2,
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"OTGFS Channel configured. chidx: %d: (EP%d,IN ,ISOC)\n"),
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TRENTRY(OTGFS_VTRACE2_CHANCONF_ISOC_OUT, TR_FMT2,
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"OTGFS Channel configured. chidx: %d: (EP%d,OUT,ISOC)\n"),
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TRENTRY(OTGFS_VTRACE2_CHANHALT, TR_FMT2,
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"OTGFS Channel halted. chidx: %d, reason: %d\n"),
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#endif
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};
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@@ -1,4 +1,4 @@
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/************************************************************************************
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/****************************************************************************
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* arch/arm/src/stm32l4/stm32l4_userspace.h
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*
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* Copyright (C) 2017 Gregory Nutt. All rights reserved.
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@@ -31,20 +31,20 @@
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_USERSPACE_H
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#define __ARCH_ARM_SRC_STM32L4_STM32L4_USERSPACE_H
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||||
/************************************************************************************
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/************************************************************************************
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32l4_userspace
|
||||
|
||||
@@ -54,7 +54,7 @@ extern "C"
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/** Waste CPU Time
|
||||
|
||||
@@ -63,7 +63,7 @@ extern "C"
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
@@ -92,8 +92,8 @@ void stm32l4_iwdginitialize(FAR const char *devpath, uint32_t lsifreq);
|
||||
* Name: stm32l4_wwdginitialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize the WWDG watchdog time. The watchdog timer is initialized and
|
||||
* registers as 'devpath. The initial state of the watchdog time is
|
||||
* Initialize the WWDG watchdog time. The watchdog timer is initialized
|
||||
* and registers as 'devpath. The initial state of the watchdog time is
|
||||
* disabled.
|
||||
*
|
||||
* Input Parameters:
|
||||
|
||||
@@ -206,7 +206,7 @@ static inline void rcc_enableahb2(void)
|
||||
#if STM32L4_NPORTS > 4
|
||||
| RCC_AHB2ENR_GPIOEEN
|
||||
#endif
|
||||
/* These chips have no GPIOF, GPIOG or GPIOI */
|
||||
/* These chips have no GPIOF, GPIOG or GPIOI */
|
||||
#if STM32L4_NPORTS > 7
|
||||
| RCC_AHB2ENR_GPIOHEN
|
||||
#endif
|
||||
@@ -404,7 +404,7 @@ static inline void rcc_enableapb1(void)
|
||||
|
||||
putreg32(regval, STM32L4_RCC_APB1ENR1); /* Enable peripherals */
|
||||
|
||||
/* Second APB1 register */
|
||||
/* Second APB1 register */
|
||||
|
||||
regval = getreg32(STM32L4_RCC_APB1ENR2);
|
||||
|
||||
@@ -454,8 +454,8 @@ static inline void rcc_enableapb2(void)
|
||||
regval = getreg32(STM32L4_RCC_APB2ENR);
|
||||
|
||||
#if defined(CONFIG_STM32L4_SYSCFG) || defined(CONFIG_STM32L4_COMP)
|
||||
/* System configuration controller, comparators, and voltage reference buffer
|
||||
* clock enable
|
||||
/* System configuration controller, comparators, and voltage reference
|
||||
* buffer clock enable
|
||||
*/
|
||||
|
||||
regval |= RCC_APB2ENR_SYSCFGEN;
|
||||
@@ -647,7 +647,8 @@ static void stm32l4_stdclockconfig(void)
|
||||
|
||||
for (timeout = MSIRDY_TIMEOUT; timeout > 0; timeout--)
|
||||
{
|
||||
if ((regval = getreg32(STM32L4_RCC_CR)), (regval & RCC_CR_MSIRDY) || ~(regval & RCC_CR_MSION))
|
||||
if ((regval = getreg32(STM32L4_RCC_CR)), (regval & RCC_CR_MSIRDY) ||
|
||||
~(regval & RCC_CR_MSION))
|
||||
{
|
||||
/* If so, then break-out with timeout > 0 */
|
||||
|
||||
@@ -764,8 +765,9 @@ static void stm32l4_stdclockconfig(void)
|
||||
|
||||
/* Set the PLL dividers and multipliers to configure the main PLL */
|
||||
|
||||
regval = (STM32L4_PLLCFG_PLLM | STM32L4_PLLCFG_PLLN | STM32L4_PLLCFG_PLLP
|
||||
| STM32L4_PLLCFG_PLLQ | STM32L4_PLLCFG_PLLR);
|
||||
regval = (STM32L4_PLLCFG_PLLM | STM32L4_PLLCFG_PLLN |
|
||||
STM32L4_PLLCFG_PLLP | STM32L4_PLLCFG_PLLQ |
|
||||
STM32L4_PLLCFG_PLLR);
|
||||
|
||||
#ifdef STM32L4_PLLCFG_PLLP_ENABLED
|
||||
regval |= RCC_PLLCFG_PLLPEN;
|
||||
@@ -833,7 +835,7 @@ static void stm32l4_stdclockconfig(void)
|
||||
regval |= RCC_CR_PLLSAI1ON;
|
||||
putreg32(regval, STM32L4_RCC_CR);
|
||||
|
||||
/* Wait until the PLL is ready */
|
||||
/* Wait until the PLL is ready */
|
||||
|
||||
while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0)
|
||||
{
|
||||
@@ -875,7 +877,8 @@ static void stm32l4_stdclockconfig(void)
|
||||
/* Enable FLASH prefetch, instruction cache, data cache, and 4 wait states */
|
||||
|
||||
#ifdef CONFIG_STM32L4_FLASH_PREFETCH
|
||||
regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN);
|
||||
regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN |
|
||||
FLASH_ACR_PRFTEN);
|
||||
#else
|
||||
regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN);
|
||||
#endif
|
||||
@@ -890,7 +893,8 @@ static void stm32l4_stdclockconfig(void)
|
||||
|
||||
/* Wait until the PLL source is used as the system clock source */
|
||||
|
||||
while ((getreg32(STM32L4_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL)
|
||||
while ((getreg32(STM32L4_RCC_CFGR) & RCC_CFGR_SWS_MASK) !=
|
||||
RCC_CFGR_SWS_PLL)
|
||||
{
|
||||
}
|
||||
|
||||
@@ -911,6 +915,7 @@ static void stm32l4_stdclockconfig(void)
|
||||
/* ensure Power control is enabled since it is indirectly required
|
||||
* to alter the LSE parameters.
|
||||
*/
|
||||
|
||||
stm32l4_pwr_enableclk(true);
|
||||
|
||||
/* XXX other LSE settings must be made before turning on the oscillator
|
||||
|
||||
@@ -253,7 +253,6 @@ static inline void rcc_enableahb3(void)
|
||||
regval |= RCC_AHB3ENR_FSMCEN;
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef CONFIG_STM32L4_QSPI
|
||||
/* QuadSPI module clock enable */
|
||||
|
||||
@@ -403,7 +402,7 @@ static inline void rcc_enableapb1(void)
|
||||
|
||||
putreg32(regval, STM32L4_RCC_APB1ENR1); /* Enable peripherals */
|
||||
|
||||
/* Second APB1 register */
|
||||
/* Second APB1 register */
|
||||
|
||||
regval = getreg32(STM32L4_RCC_APB1ENR2);
|
||||
|
||||
@@ -447,8 +446,8 @@ static inline void rcc_enableapb2(void)
|
||||
regval = getreg32(STM32L4_RCC_APB2ENR);
|
||||
|
||||
#if defined(CONFIG_STM32L4_SYSCFG) || defined(CONFIG_STM32L4_COMP)
|
||||
/* System configuration controller, comparators, and voltage reference buffer
|
||||
* clock enable
|
||||
/* System configuration controller, comparators, and voltage reference
|
||||
* buffer clock enable
|
||||
*/
|
||||
|
||||
regval |= RCC_APB2ENR_SYSCFGEN;
|
||||
@@ -638,7 +637,8 @@ static void stm32l4_stdclockconfig(void)
|
||||
|
||||
for (timeout = MSIRDY_TIMEOUT; timeout > 0; timeout--)
|
||||
{
|
||||
if ((regval = getreg32(STM32L4_RCC_CR)), (regval & RCC_CR_MSIRDY) || ~(regval & RCC_CR_MSION))
|
||||
if ((regval = getreg32(STM32L4_RCC_CR)), (regval & RCC_CR_MSIRDY) ||
|
||||
~(regval & RCC_CR_MSION))
|
||||
{
|
||||
/* If so, then break-out with timeout > 0 */
|
||||
|
||||
@@ -755,8 +755,9 @@ static void stm32l4_stdclockconfig(void)
|
||||
|
||||
/* Set the PLL dividers and multipliers to configure the main PLL */
|
||||
|
||||
regval = (STM32L4_PLLCFG_PLLM | STM32L4_PLLCFG_PLLN | STM32L4_PLLCFG_PLLP
|
||||
| STM32L4_PLLCFG_PLLQ | STM32L4_PLLCFG_PLLR);
|
||||
regval = (STM32L4_PLLCFG_PLLM | STM32L4_PLLCFG_PLLN |
|
||||
STM32L4_PLLCFG_PLLP | STM32L4_PLLCFG_PLLQ |
|
||||
STM32L4_PLLCFG_PLLR);
|
||||
|
||||
#ifdef STM32L4_PLLCFG_PLLP_ENABLED
|
||||
regval |= RCC_PLLCFG_PLLPEN;
|
||||
@@ -824,7 +825,7 @@ static void stm32l4_stdclockconfig(void)
|
||||
regval |= RCC_CR_PLLSAI1ON;
|
||||
putreg32(regval, STM32L4_RCC_CR);
|
||||
|
||||
/* Wait until the PLL is ready */
|
||||
/* Wait until the PLL is ready */
|
||||
|
||||
while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0)
|
||||
{
|
||||
@@ -866,7 +867,8 @@ static void stm32l4_stdclockconfig(void)
|
||||
/* Enable FLASH prefetch, instruction cache, data cache, and 4 wait states */
|
||||
|
||||
#ifdef CONFIG_STM32L4_FLASH_PREFETCH
|
||||
regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN);
|
||||
regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN |
|
||||
FLASH_ACR_PRFTEN);
|
||||
#else
|
||||
regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN);
|
||||
#endif
|
||||
@@ -881,7 +883,8 @@ static void stm32l4_stdclockconfig(void)
|
||||
|
||||
/* Wait until the PLL source is used as the system clock source */
|
||||
|
||||
while ((getreg32(STM32L4_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL)
|
||||
while ((getreg32(STM32L4_RCC_CFGR) & RCC_CFGR_SWS_MASK) !=
|
||||
RCC_CFGR_SWS_PLL)
|
||||
{
|
||||
}
|
||||
|
||||
@@ -902,6 +905,7 @@ static void stm32l4_stdclockconfig(void)
|
||||
/* ensure Power control is enabled since it is indirectly required
|
||||
* to alter the LSE parameters.
|
||||
*/
|
||||
|
||||
stm32l4_pwr_enableclk(true);
|
||||
|
||||
/* XXX other LSE settings must be made before turning on the oscillator
|
||||
|
||||
@@ -289,7 +289,6 @@ static inline void rcc_enableahb3(void)
|
||||
regval |= RCC_AHB3ENR_FSMCEN;
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef CONFIG_STM32L4_QSPI
|
||||
/* QuadSPI module clock enable */
|
||||
|
||||
@@ -460,7 +459,7 @@ static inline void rcc_enableapb1(void)
|
||||
|
||||
putreg32(regval, STM32L4_RCC_APB1ENR1); /* Enable peripherals */
|
||||
|
||||
/* Second APB1 register */
|
||||
/* Second APB1 register */
|
||||
|
||||
regval = getreg32(STM32L4_RCC_APB1ENR2);
|
||||
|
||||
@@ -510,8 +509,8 @@ static inline void rcc_enableapb2(void)
|
||||
regval = getreg32(STM32L4_RCC_APB2ENR);
|
||||
|
||||
#if defined(CONFIG_STM32L4_SYSCFG) || defined(CONFIG_STM32L4_COMP)
|
||||
/* System configuration controller, comparators, and voltage reference buffer
|
||||
* clock enable
|
||||
/* System configuration controller, comparators, and voltage reference
|
||||
* buffer clock enable
|
||||
*/
|
||||
|
||||
regval |= RCC_APB2ENR_SYSCFGEN;
|
||||
@@ -715,7 +714,8 @@ static void stm32l4_stdclockconfig(void)
|
||||
|
||||
for (timeout = MSIRDY_TIMEOUT; timeout > 0; timeout--)
|
||||
{
|
||||
if ((regval = getreg32(STM32L4_RCC_CR)), (regval & RCC_CR_MSIRDY) || ~(regval & RCC_CR_MSION))
|
||||
if ((regval = getreg32(STM32L4_RCC_CR)), (regval & RCC_CR_MSIRDY) ||
|
||||
~(regval & RCC_CR_MSION))
|
||||
{
|
||||
/* If so, then break-out with timeout > 0 */
|
||||
|
||||
@@ -832,8 +832,9 @@ static void stm32l4_stdclockconfig(void)
|
||||
|
||||
/* Set the PLL dividers and multipliers to configure the main PLL */
|
||||
|
||||
regval = (STM32L4_PLLCFG_PLLM | STM32L4_PLLCFG_PLLN | STM32L4_PLLCFG_PLLP
|
||||
| STM32L4_PLLCFG_PLLQ | STM32L4_PLLCFG_PLLR);
|
||||
regval = (STM32L4_PLLCFG_PLLM | STM32L4_PLLCFG_PLLN |
|
||||
STM32L4_PLLCFG_PLLP | STM32L4_PLLCFG_PLLQ |
|
||||
STM32L4_PLLCFG_PLLR);
|
||||
|
||||
#ifdef STM32L4_PLLCFG_PLLP_ENABLED
|
||||
regval |= RCC_PLLCFG_PLLPEN;
|
||||
@@ -901,7 +902,7 @@ static void stm32l4_stdclockconfig(void)
|
||||
regval |= RCC_CR_PLLSAI1ON;
|
||||
putreg32(regval, STM32L4_RCC_CR);
|
||||
|
||||
/* Wait until the PLL is ready */
|
||||
/* Wait until the PLL is ready */
|
||||
|
||||
while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0)
|
||||
{
|
||||
@@ -943,7 +944,8 @@ static void stm32l4_stdclockconfig(void)
|
||||
/* Enable FLASH prefetch, instruction cache, data cache, and 4 wait states */
|
||||
|
||||
#ifdef CONFIG_STM32L4_FLASH_PREFETCH
|
||||
regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN);
|
||||
regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN |
|
||||
FLASH_ACR_PRFTEN);
|
||||
#else
|
||||
regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN);
|
||||
#endif
|
||||
@@ -958,7 +960,8 @@ static void stm32l4_stdclockconfig(void)
|
||||
|
||||
/* Wait until the PLL source is used as the system clock source */
|
||||
|
||||
while ((getreg32(STM32L4_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL)
|
||||
while ((getreg32(STM32L4_RCC_CFGR) & RCC_CFGR_SWS_MASK) !=
|
||||
RCC_CFGR_SWS_PLL)
|
||||
{
|
||||
}
|
||||
|
||||
@@ -987,6 +990,7 @@ static void stm32l4_stdclockconfig(void)
|
||||
/* ensure Power control is enabled since it is indirectly required
|
||||
* to alter the LSE parameters.
|
||||
*/
|
||||
|
||||
stm32l4_pwr_enableclk(true);
|
||||
|
||||
/* XXX other LSE settings must be made before turning on the oscillator
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -453,7 +453,7 @@ static inline void rcc_enableapb1(void)
|
||||
|
||||
putreg32(regval, STM32L4_RCC_APB1ENR1); /* Enable peripherals */
|
||||
|
||||
/* Second APB1 register */
|
||||
/* Second APB1 register */
|
||||
|
||||
regval = getreg32(STM32L4_RCC_APB1ENR2);
|
||||
|
||||
@@ -497,8 +497,8 @@ static inline void rcc_enableapb2(void)
|
||||
regval = getreg32(STM32L4_RCC_APB2ENR);
|
||||
|
||||
#if defined(CONFIG_STM32L4_SYSCFG) || defined(CONFIG_STM32L4_COMP)
|
||||
/* System configuration controller, comparators, and voltage reference buffer
|
||||
* clock enable
|
||||
/* System configuration controller, comparators, and voltage reference
|
||||
* buffer clock enable
|
||||
*/
|
||||
|
||||
regval |= RCC_APB2ENR_SYSCFGEN;
|
||||
@@ -700,7 +700,9 @@ static void stm32l4_stdclockconfig(void)
|
||||
|
||||
for (timeout = MSIRDY_TIMEOUT; timeout > 0; timeout--)
|
||||
{
|
||||
if ((regval = getreg32(STM32L4_RCC_CR)), (regval & RCC_CR_MSIRDY) || ~(regval & RCC_CR_MSION))
|
||||
regval = getreg32(STM32L4_RCC_CR);
|
||||
|
||||
if ((regval & RCC_CR_MSIRDY) || ~(regval & RCC_CR_MSION))
|
||||
{
|
||||
/* If so, then break-out with timeout > 0 */
|
||||
|
||||
@@ -821,8 +823,9 @@ static void stm32l4_stdclockconfig(void)
|
||||
|
||||
/* Set the PLL dividers and multipliers to configure the main PLL */
|
||||
|
||||
regval = (STM32L4_PLLCFG_PLLM | STM32L4_PLLCFG_PLLN | STM32L4_PLLCFG_PLLP
|
||||
| STM32L4_PLLCFG_PLLQ | STM32L4_PLLCFG_PLLR);
|
||||
regval = (STM32L4_PLLCFG_PLLM | STM32L4_PLLCFG_PLLN |
|
||||
STM32L4_PLLCFG_PLLP | STM32L4_PLLCFG_PLLQ |
|
||||
STM32L4_PLLCFG_PLLR);
|
||||
|
||||
#ifdef STM32L4_PLLCFG_PLLP_ENABLED
|
||||
regval |= RCC_PLLCFG_PLLPEN;
|
||||
@@ -890,7 +893,7 @@ static void stm32l4_stdclockconfig(void)
|
||||
regval |= RCC_CR_PLLSAI1ON;
|
||||
putreg32(regval, STM32L4_RCC_CR);
|
||||
|
||||
/* Wait until the PLL is ready */
|
||||
/* Wait until the PLL is ready */
|
||||
|
||||
while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0)
|
||||
{
|
||||
@@ -955,7 +958,8 @@ static void stm32l4_stdclockconfig(void)
|
||||
|
||||
/* Wait until the PLL source is used as the system clock source */
|
||||
|
||||
while ((getreg32(STM32L4_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL)
|
||||
while ((getreg32(STM32L4_RCC_CFGR) & RCC_CFGR_SWS_MASK) !=
|
||||
RCC_CFGR_SWS_PLL)
|
||||
{
|
||||
}
|
||||
|
||||
|
||||
Reference in New Issue
Block a user