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!arch/stm32u5: use common STM32 Kconfig symbols

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BREAKING CHANGE: STM32U5 Kconfig symbols were renamed from CONFIG_STM32U5_* to CONFIG_STM32_*.
Out-of-tree code must update defconfigs and Kconfig references to the new CONFIG_STM32_* names.
The custom clock option is a special breaking case that does not follow the family-to-common pattern:
CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG was renamed to CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG.

Signed-off-by: raiden00pl <raiden00@railab.me>
This commit is contained in:
raiden00pl
2026-06-24 23:14:35 +08:00
committed by Xiang Xiao
parent 0c41b13966
commit dd0c546eac
43 changed files with 702 additions and 4070 deletions
Download Patch File Download Diff File Expand all files Collapse all files
Documentation/platforms/arm/stm32u5/boards/b-u585i-iot02a/index.rst
+3 -3
View File
@@ -102,9 +102,9 @@ NOTES:
output on USART3, as described above under "Serial Console". The
elevant configuration settings are listed below::
CONFIG_STM32L5_USART3=y
CONFIG_STM32L5_USART3_SERIALDRIVER=y
CONFIG_STM32L5_USART=y
CONFIG_STM32_USART3=y
CONFIG_STM32_USART3_SERIALDRIVER=y
CONFIG_STM32_USART=y
CONFIG_USART3_SERIALDRIVER=y
CONFIG_USART3_SERIAL_CONSOLE=y
arch/arm/Kconfig
+1
View File
@@ -630,6 +630,7 @@ config ARCH_CHIP_STM32L5
config ARCH_CHIP_STM32U5
bool "STMicro STM32 U5"
select ARCH_CHIP_STM32
select ARCH_CORTEXM33
select ARCH_HAVE_MPU
select ARM_HAVE_DSP
arch/arm/include/stm32u5/chip.h
+4 -4
View File
@@ -36,11 +36,11 @@
#if defined(CONFIG_STM32U5_STM32U535XX) || defined(CONFIG_STM32U5_STM32U545XX)
# define STM32_SRAM1_SIZE (0x00030000) /* 192Kb SRAM1 */
# define STM32_SRAM2_SIZE (0x00010000) /* 64kB SRAM2 */
#elif defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32U5_STM32U585XX)
#elif defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32_STM32U585XX)
# define STM32_SRAM1_SIZE (0x00030000) /* 192Kb SRAM1 */
# define STM32_SRAM2_SIZE (0x00010000) /* 64kB SRAM2 */
# define STM32_SRAM3_SIZE (0x00080000) /* 512kB SRAM3 */
#elif defined(CONFIG_STM32U5_STM32U59XX) || defined(CONFIG_STM32U5_STM32U59AXX) || defined(CONFIG_STM32U5_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX)
#elif defined(CONFIG_STM32U5_STM32U59XX) || defined(CONFIG_STM32U5_STM32U59AXX) || defined(CONFIG_STM32_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX)
# define STM32_SRAM1_SIZE (0x000C0000) /* 768Kb SRAM1 */
# define STM32_SRAM2_SIZE (0x00010000) /* 64kB SRAM2 */
# define STM32_SRAM3_SIZE (0x000d0000) /* 832kB SRAM3 */
@@ -49,7 +49,7 @@
# error "Unsupported STM32U5 chip"
#endif
#if defined(CONFIG_STM32U5_STM32U585XX) || defined(CONFIG_STM32U5_STM32U5A5XX)
#if defined(CONFIG_STM32_STM32U585XX) || defined(CONFIG_STM32_STM32U5A5XX)
# define STM32_NFSMC 1 /* Have FSMC memory controller */
# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
# define STM32_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */
@@ -78,7 +78,7 @@
# define STM32_NCRC 1 /* CRC */
# define STM32_NCOMP 2 /* Comparators */
# define STM32_NOPAMP 2 /* Operational Amplifiers */
#endif /* CONFIG_STM32U5_STM32U585XX */
#endif /* CONFIG_STM32_STM32U585XX */
#if defined(CONFIG_STM32U5_STM32U5A5ZJT)
# define STM32_NUSBOTGHS 1 /* USB OTG HS */
arch/arm/include/stm32u5/irq.h
+2 -2
View File
@@ -34,9 +34,9 @@
#include <nuttx/config.h>
#if defined(CONFIG_STM32U5_STM32U535XX) || defined(CONFIG_STM32U5_STM32U545XX) || \
defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32U5_STM32U585XX) || \
defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32_STM32U585XX) || \
defined(CONFIG_STM32U5_STM32U59XX) || defined(CONFIG_STM32U5_STM32U59AXX) || \
defined(CONFIG_STM32U5_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX)
defined(CONFIG_STM32_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX)
# include <arch/stm32u5/stm32u5xx_irq.h>
#else
# error "Unsupported STM32U5 chip"
arch/arm/include/stm32u5/stm32u5xx_irq.h
+4 -4
View File
@@ -131,10 +131,10 @@
#define STM32_IRQ_TIM17 (STM32_IRQ_FIRST + 71) /* 71: TIM17 global interrupt */
#define STM32_IRQ_COMP (STM32_IRQ_FIRST + 72) /* 72: COMP1/COMP2 interrupts */
#if defined(CONFIG_STM32U5_STM32U535XX) || defined(CONFIG_STM32U5_STM32U545XX) || \
defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32U5_STM32U585XX)
defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32_STM32U585XX)
# define STM32_IRQ_OTG_FS (STM32_IRQ_FIRST + 73) /* 73: USB OTG FS global interrupt */
#elif defined(CONFIG_STM32U5_STM32U59XX) || defined(CONFIG_STM32U5_STM32U59AXX) || \
defined(CONFIG_STM32U5_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX)
defined(CONFIG_STM32_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX)
# define STM32_IRQ_OTG_HS (STM32_IRQ_FIRST + 73) /* 73: USB OTG HS global interrupt */
#else
# error "Unsupported STM32U5 chip"
@@ -192,9 +192,9 @@
#define STM32_IRQ_FMAC (STM32_IRQ_FIRST + 124) /* 124: FMAC interrupt */
#if defined(CONFIG_STM32U5_STM32U535XX) || defined(CONFIG_STM32U5_STM32U545XX) || \
defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32U5_STM32U585XX) || \
defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32_STM32U585XX) || \
defined(CONFIG_STM32U5_STM32U59XX) || defined(CONFIG_STM32U5_STM32U59AXX) || \
defined(CONFIG_STM32U5_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX)
defined(CONFIG_STM32_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX)
# define STM32_IRQ_NEXTINTS 125
#else
# error "Unsupported STM32U5 chip"
arch/arm/src/stm32u5/Kconfig
+133 -3504
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File diff suppressed because it is too large Load Diff
arch/arm/src/stm32u5/hardware/stm32_flash.h
+16 -16
View File
@@ -35,7 +35,7 @@
/* Flash size is known from the chip selection:
*
* When CONFIG_STM32U5_FLASH_OVERRIDE_DEFAULT is set the
* When CONFIG_STM32_FLASH_OVERRIDE_DEFAULT is set the
* CONFIG_STM32U5_FLASH_CONFIG_x selects the default FLASH size based on
* the chip part number. This value can be overridden with
* CONFIG_STM32U5_FLASH_OVERRIDE_x
@@ -44,30 +44,30 @@
*/
#if defined(CONFIG_ARCH_CHIP_STM32U585AI)
# if !defined(CONFIG_STM32U5_FLASH_OVERRIDE_DEFAULT) && \
!defined(CONFIG_STM32U5_FLASH_OVERRIDE_C) && \
!defined(CONFIG_STM32U5_FLASH_OVERRIDE_E) && \
!defined(CONFIG_STM32U5_FLASH_CONFIG_C) && \
!defined(CONFIG_STM32U5_FLASH_CONFIG_E)
# define CONFIG_STM32U5_FLASH_OVERRIDE_E
# if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) && \
!defined(CONFIG_STM32_FLASH_OVERRIDE_C) && \
!defined(CONFIG_STM32_FLASH_OVERRIDE_E) && \
!defined(CONFIG_STM32_FLASH_CONFIG_C) && \
!defined(CONFIG_STM32_FLASH_CONFIG_E)
# define CONFIG_STM32_FLASH_OVERRIDE_E
# warning "Flash size not defined defaulting to 512KiB (E)"
# endif
/* Override of the Flash has been chosen */
# if !defined(CONFIG_STM32U5_FLASH_OVERRIDE_DEFAULT)
# undef CONFIG_STM32U5_FLASH_CONFIG_C
# undef CONFIG_STM32U5_FLASH_CONFIG_E
# if defined(CONFIG_STM32U5_FLASH_OVERRIDE_C)
# define CONFIG_STM32U5_FLASH_CONFIG_C
# elif defined(CONFIG_STM32U5_FLASH_OVERRIDE_E)
# define CONFIG_STM32U5_FLASH_CONFIG_E
# if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT)
# undef CONFIG_STM32_FLASH_CONFIG_C
# undef CONFIG_STM32_FLASH_CONFIG_E
# if defined(CONFIG_STM32_FLASH_OVERRIDE_C)
# define CONFIG_STM32_FLASH_CONFIG_C
# elif defined(CONFIG_STM32_FLASH_OVERRIDE_E)
# define CONFIG_STM32_FLASH_CONFIG_E
# endif
# endif
/* Define the valid configuration */
# if defined(CONFIG_STM32U5_FLASH_CONFIG_I) /* 2048 kB */
# if defined(CONFIG_STM32_FLASH_CONFIG_I) /* 2048 kB */
# define STM32_FLASH_NPAGES 256
# define STM32_FLASH_PAGESIZE 8192
# else
@@ -79,7 +79,7 @@
# define STM32_FLASH_SIZE (STM32_FLASH_NPAGES * STM32_FLASH_PAGESIZE)
#endif
#if defined(CONFIG_STM32U5_STM32U5A5XX)
#if defined(CONFIG_STM32_STM32U5A5XX)
# define STM32_FLASH_NPAGES 512
# define STM32_FLASH_PAGESIZE 8192
# define STM32_FLASH_SIZE (STM32_FLASH_NPAGES * STM32_FLASH_PAGESIZE)
arch/arm/src/stm32u5/hardware/stm32_memorymap.h
+2 -2
View File
@@ -51,7 +51,7 @@
# define STM32_SRAM1_BASE 0x20000000 /* 0x20000000-0x2002ffff: 192k SRAM1 */
# define STM32_SRAM2_BASE 0x20030000 /* 0x20030000-0x2003ffff: 64k SRAM2 */
#elif defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32U5_STM32U585XX)
#elif defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32_STM32U585XX)
# define STM32_BOOT_BASE 0x00000000 /* 0x00000000-0x000fffff: Aliased boot memory */
# define STM32_FLASH_BASE 0x08000000 /* 0x08000000-0x081fffff: FLASH memory */
@@ -60,7 +60,7 @@
# define STM32_SRAM3_BASE 0x20040000 /* 0x20040000-0x200bffff: 512k SRAM3 */
#elif defined(CONFIG_STM32U5_STM32U59XX) || defined(CONFIG_STM32U5_STM32U59AXX) || \
defined(CONFIG_STM32U5_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX)
defined(CONFIG_STM32_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX)
# define STM32_BOOT_BASE 0x00000000 /* 0x00000000-0x000fffff: Aliased boot memory */
# define STM32_FLASH_BASE 0x08000000 /* 0x08000000-0x081fffff: FLASH memory */
arch/arm/src/stm32u5/hardware/stm32_pinmap.h
+1 -1
View File
@@ -30,7 +30,7 @@
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32U5_STM32U585XX) || defined(CONFIG_STM32U5_STM32U5A5XX)
#if defined(CONFIG_STM32_STM32U585XX) || defined(CONFIG_STM32_STM32U5A5XX)
# include "hardware/stm32u5xx_pinmap.h"
#else
# error "Unsupported STM32U5 pin map"
arch/arm/src/stm32u5/hardware/stm32_spi.h
+2 -2
View File
@@ -31,9 +31,9 @@
#include "chip.h"
#if defined(CONFIG_STM32U5_STM32U535XX) || defined(CONFIG_STM32U5_STM32U545XX) || \
defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32U5_STM32U585XX) || \
defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32_STM32U585XX) || \
defined(CONFIG_STM32U5_STM32U59XX) || defined(CONFIG_STM32U5_STM32U59AXX) || \
defined(CONFIG_STM32U5_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX)
defined(CONFIG_STM32_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX)
# include "hardware/stm32u5xx_spi.h"
#else
# error "Unsupported STM32U5 chip"
arch/arm/src/stm32u5/hardware/stm32_syscfg.h
+1 -1
View File
@@ -30,7 +30,7 @@
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32U5_STM32U585XX) || defined(CONFIG_STM32U5_STM32U5A5XX)
#if defined(CONFIG_STM32_STM32U585XX) || defined(CONFIG_STM32_STM32U5A5XX)
# include "hardware/stm32u5xx_syscfg.h"
#else
# error "Unsupported STM32U5 chip"
arch/arm/src/stm32u5/hardware/stm32u5xx_rcc.h
+2 -2
View File
@@ -30,9 +30,9 @@
#include <nuttx/config.h>
#if defined(CONFIG_STM32U5_STM32U535XX) || defined(CONFIG_STM32U5_STM32U545XX) || \
defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32U5_STM32U585XX) || \
defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32_STM32U585XX) || \
defined(CONFIG_STM32U5_STM32U59XX) || defined(CONFIG_STM32U5_STM32U59AXX) || \
defined(CONFIG_STM32U5_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX)
defined(CONFIG_STM32_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX)
/****************************************************************************
* Pre-processor Definitions
arch/arm/src/stm32u5/hardware/stm32u5xx_spi.h
+2 -2
View File
@@ -30,9 +30,9 @@
#include <nuttx/config.h>
#if defined(CONFIG_STM32U5_STM32U535XX) || defined(CONFIG_STM32U5_STM32U545XX) || \
defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32U5_STM32U585XX) || \
defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32_STM32U585XX) || \
defined(CONFIG_STM32U5_STM32U59XX) || defined(CONFIG_STM32U5_STM32U59AXX) || \
defined(CONFIG_STM32U5_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX)
defined(CONFIG_STM32_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX)
/****************************************************************************
* Pre-processor Definitions
arch/arm/src/stm32u5/hardware/stm32u5xx_syscfg.h
+2 -2
View File
@@ -31,9 +31,9 @@
#include "chip.h"
#if defined(CONFIG_STM32U5_STM32U535XX) || defined(CONFIG_STM32U5_STM32U545XX) || \
defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32U5_STM32U585XX) || \
defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32_STM32U585XX) || \
defined(CONFIG_STM32U5_STM32U59XX) || defined(CONFIG_STM32U5_STM32U59AXX) || \
defined(CONFIG_STM32U5_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX)
defined(CONFIG_STM32_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX)
/****************************************************************************
* Pre-processor Definitions
arch/arm/src/stm32u5/stm32_allocateheap.c
+11 -11
View File
@@ -60,7 +60,7 @@
* FSMC. In order to use FSMC SRAM, the following additional things need to
* be present in the NuttX configuration file:
*
* CONFIG_STM32U5_FSMC=y : Enables the FSMC
* CONFIG_STM32_FSMC=y : Enables the FSMC
* CONFIG_STM32U5_FSMC_SRAM=y : Indicates that SRAM is available via the
* FSMC (as opposed to an LCD or FLASH).
* CONFIG_HEAP2_BASE : The base address of the SRAM in the FSMC
@@ -71,7 +71,7 @@
* include the additional regions.
*/
#ifndef CONFIG_STM32U5_FSMC
#ifndef CONFIG_STM32_FSMC
# undef CONFIG_STM32U5_FSMC_SRAM
#endif
@@ -121,16 +121,16 @@
* that we have been asked to add to the heap.
*/
#if CONFIG_MM_REGIONS < defined(CONFIG_STM32U5_SRAM2_HEAP) + \
defined(CONFIG_STM32U5_SRAM3_HEAP) + \
defined(CONFIG_STM32U5_SRAM5_HEAP) + \
#if CONFIG_MM_REGIONS < defined(CONFIG_STM32_SRAM2_HEAP) + \
defined(CONFIG_STM32_SRAM3_HEAP) + \
defined(CONFIG_STM32_SRAM5_HEAP) + \
defined(CONFIG_STM32U5_FSMC_SRAM_HEAP) + 1
# error "You need more memory manager regions to support selected heap components"
#endif
#if CONFIG_MM_REGIONS > defined(CONFIG_STM32U5_SRAM2_HEAP) + \
defined(CONFIG_STM32U5_SRAM3_HEAP) + \
defined(CONFIG_STM32U5_SRAM5_HEAP) + \
#if CONFIG_MM_REGIONS > defined(CONFIG_STM32_SRAM2_HEAP) + \
defined(CONFIG_STM32_SRAM3_HEAP) + \
defined(CONFIG_STM32_SRAM5_HEAP) + \
defined(CONFIG_STM32U5_FSMC_SRAM_HEAP) + 1
# warning "CONFIG_MM_REGIONS large enough but I do not know what some of the region(s) are"
#endif
@@ -319,7 +319,7 @@ void up_allocate_kheap(void **heap_start, size_t *heap_size)
#if CONFIG_MM_REGIONS > 1
void arm_addregion(void)
{
#ifdef CONFIG_STM32U5_SRAM2_HEAP
#ifdef CONFIG_STM32_SRAM2_HEAP
# if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
@@ -339,7 +339,7 @@ void arm_addregion(void)
#endif /* SRAM2 */
#ifdef CONFIG_STM32U5_SRAM3_HEAP
#ifdef CONFIG_STM32_SRAM3_HEAP
# if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
@@ -359,7 +359,7 @@ void arm_addregion(void)
#endif /* SRAM3 */
#ifdef CONFIG_STM32U5_SRAM5_HEAP
#ifdef CONFIG_STM32_SRAM5_HEAP
# if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
arch/arm/src/stm32u5/stm32_dbgmcu.h
+1 -1
View File
@@ -31,7 +31,7 @@
#include "chip.h"
#if defined(CONFIG_STM32U5_STM32U585XX) || defined(CONFIG_STM32U5_STM32U5A5XX)
#if defined(CONFIG_STM32_STM32U585XX) || defined(CONFIG_STM32_STM32U5A5XX)
# include "hardware/stm32u5xx_dbgmcu.h"
#else
# error "Unsupported STM32U5 chip"
arch/arm/src/stm32u5/stm32_exti.h
+1 -1
View File
@@ -141,7 +141,7 @@ int stm32_exti_wakeup(bool risingedge, bool fallingedge, bool event,
*
****************************************************************************/
#ifdef CONFIG_STM32U5_COMP
#ifdef CONFIG_STM32_COMP
int stm32_exti_comp(int cmp, bool risingedge, bool fallingedge,
bool event, xcpt_t func, void *arg);
#endif
arch/arm/src/stm32u5/stm32_flash.c
+3 -3
View File
@@ -50,13 +50,13 @@
#include "stm32_flash.h"
#include "arm_internal.h"
#if !defined(CONFIG_STM32U5_STM32U585XX)
#elif !defined(CONFIG_STM32U5_STM32U5A5XX)
#if !defined(CONFIG_STM32_STM32U585XX)
#elif !defined(CONFIG_STM32_STM32U5A5XX)
#else
# error "Unrecognized STM32 chip"
#endif
#if !defined(CONFIG_STM32U5_FLASH_OVERRIDE_DEFAULT)
#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT)
# warning "Flash Configuration has been overridden - make sure it is correct"
#endif
arch/arm/src/stm32u5/stm32_gpio.h
+1 -1
View File
@@ -39,7 +39,7 @@
#include "chip.h"
#if defined(CONFIG_STM32U5_STM32U585XX) || defined(CONFIG_STM32U5_STM32U5A5XX)
#if defined(CONFIG_STM32_STM32U585XX) || defined(CONFIG_STM32_STM32U5A5XX)
# include "hardware/stm32_gpio.h"
#else
# error "Unsupported STM32U5 chip"
arch/arm/src/stm32u5/stm32_i2c.c
+48 -48
View File
@@ -172,28 +172,28 @@
*
* To use this driver, enable the following configuration variable:
*
* CONFIG_STM32U5_I2C
* CONFIG_STM32_I2C
*
* and one or more interfaces:
*
* CONFIG_STM32U5_I2C1
* CONFIG_STM32U5_I2C2
* CONFIG_STM32U5_I2C3
* CONFIG_STM32U5_I2C4
* CONFIG_STM32_I2C1
* CONFIG_STM32_I2C2
* CONFIG_STM32_I2C3
* CONFIG_STM32_I2C4
*
* To configure the ISR timeout using fixed values
* (CONFIG_STM32U5_I2C_DYNTIMEO=n):
* (CONFIG_STM32_I2C_DYNTIMEO=n):
*
* CONFIG_STM32U5_I2CTIMEOSEC (Timeout in seconds)
* CONFIG_STM32U5_I2CTIMEOMS (Timeout in milliseconds)
* CONFIG_STM32U5_I2CTIMEOTICKS (Timeout in ticks)
* CONFIG_STM32_I2CTIMEOSEC (Timeout in seconds)
* CONFIG_STM32_I2CTIMEOMS (Timeout in milliseconds)
* CONFIG_STM32_I2CTIMEOTICKS (Timeout in ticks)
*
* To configure the ISR timeout using dynamic values
* (CONFIG_STM32U5_I2C_DYNTIMEO=y):
* (CONFIG_STM32_I2C_DYNTIMEO=y):
*
* CONFIG_STM32U5_I2C_DYNTIMEO_USECPERBYTE
* CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE
* (Timeout in microseconds per byte)
* CONFIG_STM32U5_I2C_DYNTIMEO_STARTSTOP
* CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP
* (Timeout for start/stop inmilliseconds)
*
* Debugging output enabled with:
@@ -273,8 +273,8 @@
/* At least one I2C peripheral must be enabled */
#if defined(CONFIG_STM32U5_I2C1) || defined(CONFIG_STM32U5_I2C2) || \
defined(CONFIG_STM32U5_I2C3) || defined(CONFIG_STM32U5_I2C4)
#if defined(CONFIG_STM32_I2C1) || defined(CONFIG_STM32_I2C2) || \
defined(CONFIG_STM32_I2C3) || defined(CONFIG_STM32_I2C4)
/****************************************************************************
* Pre-processor Definitions
@@ -286,25 +286,25 @@
/* Interrupt wait timeout in seconds and milliseconds */
#if !defined(CONFIG_STM32U5_I2CTIMEOSEC) && !defined(CONFIG_STM32U5_I2CTIMEOMS)
# define CONFIG_STM32U5_I2CTIMEOSEC 0
# define CONFIG_STM32U5_I2CTIMEOMS 500 /* Default is 500 milliseconds */
#if !defined(CONFIG_STM32_I2CTIMEOSEC) && !defined(CONFIG_STM32_I2CTIMEOMS)
# define CONFIG_STM32_I2CTIMEOSEC 0
# define CONFIG_STM32_I2CTIMEOMS 500 /* Default is 500 milliseconds */
# warning "Using Default 500 Ms Timeout"
#elif !defined(CONFIG_STM32U5_I2CTIMEOSEC)
# define CONFIG_STM32U5_I2CTIMEOSEC 0 /* User provided milliseconds */
#elif !defined(CONFIG_STM32U5_I2CTIMEOMS)
# define CONFIG_STM32U5_I2CTIMEOMS 0 /* User provided seconds */
#elif !defined(CONFIG_STM32_I2CTIMEOSEC)
# define CONFIG_STM32_I2CTIMEOSEC 0 /* User provided milliseconds */
#elif !defined(CONFIG_STM32_I2CTIMEOMS)
# define CONFIG_STM32_I2CTIMEOMS 0 /* User provided seconds */
#endif
/* Interrupt wait time timeout in system timer ticks */
#ifndef CONFIG_STM32U5_I2CTIMEOTICKS
# define CONFIG_STM32U5_I2CTIMEOTICKS \
(SEC2TICK(CONFIG_STM32U5_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32U5_I2CTIMEOMS))
#ifndef CONFIG_STM32_I2CTIMEOTICKS
# define CONFIG_STM32_I2CTIMEOTICKS \
(SEC2TICK(CONFIG_STM32_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32_I2CTIMEOMS))
#endif
#ifndef CONFIG_STM32U5_I2C_DYNTIMEO_STARTSTOP
# define CONFIG_STM32U5_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32U5_I2CTIMEOTICKS)
#ifndef CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP
# define CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32_I2CTIMEOTICKS)
#endif
/* Macros to convert a I2C pin to a GPIO output */
@@ -472,9 +472,9 @@ static inline
void stm32_i2c_modifyreg32(struct stm32_i2c_priv_s *priv,
uint8_t offset, uint32_t clearbits,
uint32_t setbits);
#ifdef CONFIG_STM32U5_I2C_DYNTIMEO
#ifdef CONFIG_STM32_I2C_DYNTIMEO
static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs);
#endif /* CONFIG_STM32U5_I2C_DYNTIMEO */
#endif /* CONFIG_STM32_I2C_DYNTIMEO */
static inline
int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv);
static inline
@@ -518,7 +518,7 @@ static int stm32_i2c_pm_prepare(struct pm_callback_s *cb, int domain,
* Private Data
****************************************************************************/
#ifdef CONFIG_STM32U5_I2C1
#ifdef CONFIG_STM32_I2C1
static const struct stm32_i2c_config_s stm32_i2c1_config =
{
.base = STM32_I2C1_BASE,
@@ -554,7 +554,7 @@ static struct stm32_i2c_priv_s stm32_i2c1_priv =
};
#endif
#ifdef CONFIG_STM32U5_I2C2
#ifdef CONFIG_STM32_I2C2
static const struct stm32_i2c_config_s stm32_i2c2_config =
{
.base = STM32_I2C2_BASE,
@@ -590,7 +590,7 @@ static struct stm32_i2c_priv_s stm32_i2c2_priv =
};
#endif
#ifdef CONFIG_STM32U5_I2C3
#ifdef CONFIG_STM32_I2C3
static const struct stm32_i2c_config_s stm32_i2c3_config =
{
.base = STM32_I2C3_BASE,
@@ -626,7 +626,7 @@ static struct stm32_i2c_priv_s stm32_i2c3_priv =
};
#endif
#ifdef CONFIG_STM32U5_I2C4
#ifdef CONFIG_STM32_I2C4
static const struct stm32_i2c_config_s stm32_i2c4_config =
{
.base = STM32_I2C4_BASE,
@@ -759,7 +759,7 @@ void stm32_i2c_modifyreg32(struct stm32_i2c_priv_s *priv,
*
****************************************************************************/
#ifdef CONFIG_STM32U5_I2C_DYNTIMEO
#ifdef CONFIG_STM32_I2C_DYNTIMEO
static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs)
{
size_t bytecount = 0;
@@ -776,7 +776,7 @@ static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs)
* factor.
*/
return USEC2TICK(CONFIG_STM32U5_I2C_DYNTIMEO_USECPERBYTE * bytecount);
return USEC2TICK(CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE * bytecount);
}
#endif
@@ -834,12 +834,12 @@ int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv)
{
/* Wait until either the transfer is complete or the timeout expires */
#ifdef CONFIG_STM32U5_I2C_DYNTIMEO
#ifdef CONFIG_STM32_I2C_DYNTIMEO
ret = nxsem_tickwait_uninterruptible(&priv->sem_isr,
stm32_i2c_toticks(priv->msgc, priv->msgv));
#else
ret = nxsem_tickwait_uninterruptible(&priv->sem_isr,
CONFIG_STM32U5_I2CTIMEOTICKS);
CONFIG_STM32_I2CTIMEOTICKS);
#endif
if (ret < 0)
{
@@ -878,10 +878,10 @@ int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv)
/* Get the timeout value */
#ifdef CONFIG_STM32U5_I2C_DYNTIMEO
#ifdef CONFIG_STM32_I2C_DYNTIMEO
timeout = stm32_i2c_toticks(priv->msgc, priv->msgv);
#else
timeout = CONFIG_STM32U5_I2CTIMEOTICKS;
timeout = CONFIG_STM32_I2CTIMEOTICKS;
#endif
/* Signal the interrupt handler that we are waiting. NOTE: Interrupts
@@ -1023,10 +1023,10 @@ void stm32_i2c_sem_waitstop(struct stm32_i2c_priv_s *priv)
/* Select a timeout */
#ifdef CONFIG_STM32U5_I2C_DYNTIMEO
timeout = USEC2TICK(CONFIG_STM32U5_I2C_DYNTIMEO_STARTSTOP);
#ifdef CONFIG_STM32_I2C_DYNTIMEO
timeout = USEC2TICK(CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP);
#else
timeout = CONFIG_STM32U5_I2CTIMEOTICKS;
timeout = CONFIG_STM32_I2CTIMEOTICKS;
#endif
/* Wait as stop might still be in progress */
@@ -2367,7 +2367,7 @@ static int stm32_i2c_init(struct stm32_i2c_priv_s *priv)
/* Enable power and reset the peripheral */
#ifdef CONFIG_STM32U5_I2C4
#ifdef CONFIG_STM32_I2C4
if (priv->config->base == STM32_I2C4_BASE)
{
modifyreg32(STM32_RCC_APB1ENR2, 0, priv->config->clk_bit);
@@ -2452,7 +2452,7 @@ static int stm32_i2c_deinit(struct stm32_i2c_priv_s *priv)
/* Disable clocking */
#ifdef CONFIG_STM32U5_I2C4
#ifdef CONFIG_STM32_I2C4
if (priv->config->base == STM32_I2C4_BASE)
{
modifyreg32(STM32_RCC_APB1ENR2, priv->config->clk_bit, 0);
@@ -2957,22 +2957,22 @@ struct i2c_master_s *stm32_i2cbus_initialize(int port)
switch (port)
{
#ifdef CONFIG_STM32U5_I2C1
#ifdef CONFIG_STM32_I2C1
case 1:
priv = (struct stm32_i2c_priv_s *)&stm32_i2c1_priv;
break;
#endif
#ifdef CONFIG_STM32U5_I2C2
#ifdef CONFIG_STM32_I2C2
case 2:
priv = (struct stm32_i2c_priv_s *)&stm32_i2c2_priv;
break;
#endif
#ifdef CONFIG_STM32U5_I2C3
#ifdef CONFIG_STM32_I2C3
case 3:
priv = (struct stm32_i2c_priv_s *)&stm32_i2c3_priv;
break;
#endif
#ifdef CONFIG_STM32U5_I2C4
#ifdef CONFIG_STM32_I2C4
case 4:
priv = (struct stm32_i2c_priv_s *)&stm32_i2c4_priv;
break;
@@ -3058,4 +3058,4 @@ int stm32_i2cbus_uninitialize(struct i2c_master_s *dev)
return OK;
}
#endif /* CONFIG_STM32U5_I2C1 || CONFIG_STM32U5_I2C2 || CONFIG_STM32U5_I2C3 || CONFIG_STM32U5_I2C4 */
#endif /* CONFIG_STM32_I2C1 || CONFIG_STM32_I2C2 || CONFIG_STM32_I2C3 || CONFIG_STM32_I2C4 */
arch/arm/src/stm32u5/stm32_i2c.h
+4 -4
View File
@@ -41,10 +41,10 @@
* seconds per byte value must be provided as well.
*/
#ifdef CONFIG_STM32U5_I2C_DYNTIMEO
# if CONFIG_STM32U5_I2C_DYNTIMEO_USECPERBYTE < 1
# warning "Ignoring CONFIG_STM32U5_I2C_DYNTIMEO because of CONFIG_STM32U5_I2C_DYNTIMEO_USECPERBYTE"
# undef CONFIG_STM32U5_I2C_DYNTIMEO
#ifdef CONFIG_STM32_I2C_DYNTIMEO
# if CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE < 1
# warning "Ignoring CONFIG_STM32_I2C_DYNTIMEO because of CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE"
# undef CONFIG_STM32_I2C_DYNTIMEO
# endif
#endif
arch/arm/src/stm32u5/stm32_idle.c
+1 -1
View File
@@ -92,7 +92,7 @@ void up_idle(void)
/* Sleep until an interrupt occurs to save power. */
#if !(defined(CONFIG_DEBUG_SYMBOLS) && defined(CONFIG_STM32U5_DISABLE_IDLE_SLEEP_DURING_DEBUG))
#if !(defined(CONFIG_DEBUG_SYMBOLS) && defined(CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG))
BEGIN_IDLE();
asm("WFI");
END_IDLE();
arch/arm/src/stm32u5/stm32_lse.c
+10 -10
View File
@@ -42,9 +42,9 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1,
#define LSERDY_TIMEOUT (500 * CONFIG_BOARD_LOOPSPERMSEC)
#ifdef CONFIG_STM32U5_RTC_LSECLOCK_START_DRV_CAPABILITY
# if CONFIG_STM32U5_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \
CONFIG_STM32U5_RTC_LSECLOCK_START_DRV_CAPABILITY > 3
#ifdef CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY
# if CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \
CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY > 3
# error "Invalid LSE drive capability setting"
# endif
#endif
@@ -53,7 +53,7 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1,
* Private Data
****************************************************************************/
#ifdef CONFIG_STM32U5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY
#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY
static const uint32_t drives[4] =
{
RCC_BDCR_LSEDRV_LOW,
@@ -80,7 +80,7 @@ void stm32_rcc_enablelse(void)
bool writable;
uint32_t regval;
volatile int32_t timeout;
#ifdef CONFIG_STM32U5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY
#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY
volatile int32_t drive = 0;
#endif
@@ -108,19 +108,19 @@ void stm32_rcc_enablelse(void)
regval |= RCC_BDCR_LSEON;
#ifdef CONFIG_STM32U5_RTC_LSECLOCK_START_DRV_CAPABILITY
#ifdef CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY
/* Set start-up drive capability for LSE oscillator. LSE must be OFF
* to change drive strength.
*/
regval &= ~(RCC_BDCR_LSEDRV_MASK | RCC_BDCR_LSEON);
regval |= CONFIG_STM32U5_RTC_LSECLOCK_START_DRV_CAPABILITY <<
regval |= CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY <<
RCC_BDCR_LSEDRV_SHIFT;
putreg32(regval, STM32_RCC_BDCR);
regval |= RCC_BDCR_LSEON;
#endif
#ifdef CONFIG_STM32U5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY
#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY
do
{
regval &= ~(RCC_BDCR_LSEDRV_MASK | RCC_BDCR_LSEON);
@@ -148,7 +148,7 @@ void stm32_rcc_enablelse(void)
}
}
#ifdef CONFIG_STM32U5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY
#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY
if (timeout != 0)
{
break;
@@ -177,7 +177,7 @@ void stm32_rcc_enablelse(void)
}
}
#ifdef CONFIG_STM32U5_RTC_LSECLOCK_LOWER_RUN_DRV_CAPABILITY
#ifdef CONFIG_STM32_RTC_LSECLOCK_LOWER_RUN_DRV_CAPABILITY
/* Set running drive capability for LSE oscillator. */
arch/arm/src/stm32u5/stm32_rcc.c
+5 -5
View File
@@ -83,7 +83,7 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1,
*
****************************************************************************/
#if defined(CONFIG_STM32U5_PWR) && defined(CONFIG_STM32U5_RTC)
#if defined(CONFIG_STM32_PWR) && defined(CONFIG_STM32_RTC)
static inline void rcc_resetbkp(void)
{
bool init_stat;
@@ -148,7 +148,7 @@ static inline void rcc_resetbkp(void)
* and enable peripheral clocking for all peripherals enabled in the NuttX
* configuration file.
*
* If CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG is defined, then
* If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then
* clocking will be enabled by an externally provided, board-specific
* function called stm32_board_clockconfig().
*
@@ -171,7 +171,7 @@ void stm32_clockconfig(void)
rcc_resetbkp();
#endif
#if defined(CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG)
#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG)
/* Invoke Board Custom Clock Configuration */
@@ -205,7 +205,7 @@ void stm32_clockconfig(void)
* stm32_clockconfig()
* reset the currently enabled peripheral clocks.
*
* If CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG is defined, then
* If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then
* clocking will be enabled by an externally provided, board-specific
* function called stm32_board_clockconfig().
*
@@ -220,7 +220,7 @@ void stm32_clockconfig(void)
#ifdef CONFIG_PM
void stm32_clockenable(void)
{
#if defined(CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG)
#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG)
/* Invoke Board Custom Clock Configuration */
arch/arm/src/stm32u5/stm32_rcc.h
+5 -5
View File
@@ -32,7 +32,7 @@
#include "arm_internal.h"
#include "chip.h"
#if defined(CONFIG_STM32U5_STM32U585XX) || defined(CONFIG_STM32U5_STM32U5A5XX)
#if defined(CONFIG_STM32_STM32U585XX) || defined(CONFIG_STM32_STM32U5A5XX)
# include "hardware/stm32u5xx_rcc.h"
#else
# error "Unsupported STM32U5 chip"
@@ -97,7 +97,7 @@ static inline void stm32_mcoconfig(uint32_t source)
* and enable peripheral clocking for all periperipherals enabled in the
* NuttX configuration file.
*
* If CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG is defined, then
* If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then
* clocking will be enabled by an externally provided, board-specific
* function called stm32_board_clockconfig().
*
@@ -120,7 +120,7 @@ void stm32_clockconfig(void);
*
****************************************************************************/
#ifdef CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG
#ifdef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG
void stm32_board_clockconfig(void);
#endif
@@ -135,7 +135,7 @@ void stm32_board_clockconfig(void);
*
****************************************************************************/
#ifndef CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG
#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG
void stm32_stdclockconfig(void);
#endif
@@ -152,7 +152,7 @@ void stm32_stdclockconfig(void);
* stm32_clockconfig(): It does not reset any devices, and it does not
* reset the currently enabled peripheral clocks.
*
* If CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG is defined, then
* If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then
* clocking will be enabled by an externally provided, board-specific
* function called stm32_board_clockconfig().
*
arch/arm/src/stm32u5/stm32_serial.c
+48 -48
View File
@@ -82,14 +82,14 @@
*/
# if defined(CONFIG_USART2_RXDMA) || defined(CONFIG_USART3_RXDMA)
# if !defined(CONFIG_STM32U5_DMA1) && !defined(CONFIG_STM32U5_DMAMUX)
# error STM32U5 USART2/3 receive DMA requires CONFIG_STM32U5_DMA1
# if !defined(CONFIG_STM32_DMA1) && !defined(CONFIG_STM32_DMAMUX)
# error STM32U5 USART2/3 receive DMA requires CONFIG_STM32_DMA1
# endif
# endif
# if defined(CONFIG_UART4_RXDMA) || defined(CONFIG_UART5_RXDMA)
# if !defined(CONFIG_STM32U5_DMA2) && !defined(CONFIG_STM32U5_DMAMUX)
# error STM32U5 UART4/5 receive DMA requires CONFIG_STM32U5_DMA2
# if !defined(CONFIG_STM32_DMA2) && !defined(CONFIG_STM32_DMAMUX)
# error STM32U5 UART4/5 receive DMA requires CONFIG_STM32_DMA2
# endif
# endif
@@ -116,7 +116,7 @@
/* UART2-5 have no alternate channels without DMAMUX */
# ifndef CONFIG_STM32U5_HAVE_DMAMUX
# ifndef CONFIG_STM32_HAVE_DMAMUX
# define DMAMAP_USART2_RX DMACHAN_USART2_RX
# define DMAMAP_USART3_RX DMACHAN_USART3_RX
# define DMAMAP_UART4_RX DMACHAN_UART4_RX
@@ -149,11 +149,11 @@
* can be individually invalidated.
*/
# if !defined(CONFIG_STM32U5_SERIAL_RXDMA_BUFFER_SIZE) || \
CONFIG_STM32U5_SERIAL_RXDMA_BUFFER_SIZE == 0
# if !defined(CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE) || \
CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE == 0
# define RXDMA_BUFFER_SIZE 32
# else
# define RXDMA_BUFFER_SIZE ((CONFIG_STM32U5_SERIAL_RXDMA_BUFFER_SIZE + 31) & ~31)
# define RXDMA_BUFFER_SIZE ((CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE + 31) & ~31)
# endif
/* DMA priority */
@@ -185,8 +185,8 @@
/* Power management definitions */
#if defined(CONFIG_PM) && !defined(CONFIG_STM32U5_PM_SERIAL_ACTIVITY)
# define CONFIG_STM32U5_PM_SERIAL_ACTIVITY 10
#if defined(CONFIG_PM) && !defined(CONFIG_STM32_PM_SERIAL_ACTIVITY)
# define CONFIG_STM32_PM_SERIAL_ACTIVITY 10
#endif
/* Keep track if a Break was set
@@ -200,7 +200,7 @@
* See stm32serial_restoreusartint where the masking is done.
*/
#ifdef CONFIG_STM32U5_SERIALBRK_BSDCOMPAT
#ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT
# define USART_CR1_IE_BREAK_INPROGRESS_SHFTS 15
# define USART_CR1_IE_BREAK_INPROGRESS (1 << USART_CR1_IE_BREAK_INPROGRESS_SHFTS)
#endif
@@ -395,7 +395,7 @@ static const struct uart_ops_s g_uart_dma_ops =
/* I/O buffers */
#ifdef CONFIG_STM32U5_LPUART1_SERIALDRIVER
#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER
static char g_lpuart1rxbuffer[CONFIG_LPUART1_RXBUFSIZE];
static char g_lpuart1txbuffer[CONFIG_LPUART1_TXBUFSIZE];
# ifdef CONFIG_LPUART1_RXDMA
@@ -403,7 +403,7 @@ static char g_lpuart1rxfifo[RXDMA_BUFFER_SIZE];
# endif
#endif
#ifdef CONFIG_STM32U5_USART1_SERIALDRIVER
#ifdef CONFIG_STM32_USART1_SERIALDRIVER
static char g_usart1rxbuffer[CONFIG_USART1_RXBUFSIZE];
static char g_usart1txbuffer[CONFIG_USART1_TXBUFSIZE];
# ifdef CONFIG_USART1_RXDMA
@@ -411,7 +411,7 @@ static char g_usart1rxfifo[RXDMA_BUFFER_SIZE];
# endif
#endif
#ifdef CONFIG_STM32U5_USART2_SERIALDRIVER
#ifdef CONFIG_STM32_USART2_SERIALDRIVER
static char g_usart2rxbuffer[CONFIG_USART2_RXBUFSIZE];
static char g_usart2txbuffer[CONFIG_USART2_TXBUFSIZE];
# ifdef CONFIG_USART2_RXDMA
@@ -419,7 +419,7 @@ static char g_usart2rxfifo[RXDMA_BUFFER_SIZE];
# endif
#endif
#ifdef CONFIG_STM32U5_USART3_SERIALDRIVER
#ifdef CONFIG_STM32_USART3_SERIALDRIVER
static char g_usart3rxbuffer[CONFIG_USART3_RXBUFSIZE];
static char g_usart3txbuffer[CONFIG_USART3_TXBUFSIZE];
# ifdef CONFIG_USART3_RXDMA
@@ -427,7 +427,7 @@ static char g_usart3rxfifo[RXDMA_BUFFER_SIZE];
# endif
#endif
#ifdef CONFIG_STM32U5_UART4_SERIALDRIVER
#ifdef CONFIG_STM32_UART4_SERIALDRIVER
static char g_uart4rxbuffer[CONFIG_UART4_RXBUFSIZE];
static char g_uart4txbuffer[CONFIG_UART4_TXBUFSIZE];
# ifdef CONFIG_UART4_RXDMA
@@ -435,7 +435,7 @@ static char g_uart4rxfifo[RXDMA_BUFFER_SIZE];
# endif
#endif
#ifdef CONFIG_STM32U5_UART5_SERIALDRIVER
#ifdef CONFIG_STM32_UART5_SERIALDRIVER
static char g_uart5rxbuffer[CONFIG_UART5_RXBUFSIZE];
static char g_uart5txbuffer[CONFIG_UART5_TXBUFSIZE];
# ifdef CONFIG_UART5_RXDMA
@@ -445,7 +445,7 @@ static char g_uart5rxfifo[RXDMA_BUFFER_SIZE];
/* This describes the state of the STM32 USART1 ports. */
#ifdef CONFIG_STM32U5_LPUART1_SERIALDRIVER
#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER
static struct stm32_serial_s g_lpuart1priv =
{
.dev =
@@ -505,7 +505,7 @@ static struct stm32_serial_s g_lpuart1priv =
};
#endif
#ifdef CONFIG_STM32U5_USART1_SERIALDRIVER
#ifdef CONFIG_STM32_USART1_SERIALDRIVER
static struct stm32_serial_s g_usart1priv =
{
.dev =
@@ -567,7 +567,7 @@ static struct stm32_serial_s g_usart1priv =
/* This describes the state of the STM32 USART2 port. */
#ifdef CONFIG_STM32U5_USART2_SERIALDRIVER
#ifdef CONFIG_STM32_USART2_SERIALDRIVER
static struct stm32_serial_s g_usart2priv =
{
.dev =
@@ -629,7 +629,7 @@ static struct stm32_serial_s g_usart2priv =
/* This describes the state of the STM32 USART3 port. */
#ifdef CONFIG_STM32U5_USART3_SERIALDRIVER
#ifdef CONFIG_STM32_USART3_SERIALDRIVER
static struct stm32_serial_s g_usart3priv =
{
.dev =
@@ -691,7 +691,7 @@ static struct stm32_serial_s g_usart3priv =
/* This describes the state of the STM32 UART4 port. */
#ifdef CONFIG_STM32U5_UART4_SERIALDRIVER
#ifdef CONFIG_STM32_UART4_SERIALDRIVER
static struct stm32_serial_s g_uart4priv =
{
.dev =
@@ -753,7 +753,7 @@ static struct stm32_serial_s g_uart4priv =
/* This describes the state of the STM32 UART5 port. */
#ifdef CONFIG_STM32U5_UART5_SERIALDRIVER
#ifdef CONFIG_STM32_UART5_SERIALDRIVER
static struct stm32_serial_s g_uart5priv =
{
.dev =
@@ -818,22 +818,22 @@ static struct stm32_serial_s g_uart5priv =
static struct stm32_serial_s * const
g_uart_devs[STM32_NLPUART + STM32_NUSART + STM32_NUART] =
{
#ifdef CONFIG_STM32U5_LPUART1_SERIALDRIVER
#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER
[0] = &g_lpuart1priv,
#endif
#ifdef CONFIG_STM32U5_USART1_SERIALDRIVER
#ifdef CONFIG_STM32_USART1_SERIALDRIVER
[1] = &g_usart1priv,
#endif
#ifdef CONFIG_STM32U5_USART2_SERIALDRIVER
#ifdef CONFIG_STM32_USART2_SERIALDRIVER
[2] = &g_usart2priv,
#endif
#ifdef CONFIG_STM32U5_USART3_SERIALDRIVER
#ifdef CONFIG_STM32_USART3_SERIALDRIVER
[3] = &g_usart3priv,
#endif
#ifdef CONFIG_STM32U5_UART4_SERIALDRIVER
#ifdef CONFIG_STM32_UART4_SERIALDRIVER
[4] = &g_uart4priv,
#endif
#ifdef CONFIG_STM32U5_UART5_SERIALDRIVER
#ifdef CONFIG_STM32_UART5_SERIALDRIVER
[5] = &g_uart5priv,
#endif
};
@@ -1125,7 +1125,7 @@ static void stm32serial_setformat(struct uart_dev_s *dev)
regval = stm32serial_getreg(priv, STM32_USART_CR3_OFFSET);
regval &= ~(USART_CR3_CTSE | USART_CR3_RTSE);
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32U5_FLOWCONTROL_BROKEN)
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32_FLOWCONTROL_BROKEN)
if (priv->iflow && (priv->rts_gpio != 0))
{
regval |= USART_CR3_RTSE;
@@ -1329,37 +1329,37 @@ static void stm32serial_setapbclock(struct uart_dev_s *dev, bool on)
{
default:
return;
#ifdef CONFIG_STM32U5_LPUART1_SERIALDRIVER
#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER
case STM32_LPUART1_BASE:
rcc_en = RCC_APB1ENR2_LPUART1EN;
regaddr = STM32_RCC_APB1ENR2;
break;
#endif
#ifdef CONFIG_STM32U5_USART1_SERIALDRIVER
#ifdef CONFIG_STM32_USART1_SERIALDRIVER
case STM32_USART1_BASE:
rcc_en = RCC_APB2ENR_USART1EN;
regaddr = STM32_RCC_APB2ENR;
break;
#endif
#ifdef CONFIG_STM32U5_USART2_SERIALDRIVER
#ifdef CONFIG_STM32_USART2_SERIALDRIVER
case STM32_USART2_BASE:
rcc_en = RCC_APB1ENR1_USART2EN;
regaddr = STM32_RCC_APB1ENR1;
break;
#endif
#ifdef CONFIG_STM32U5_USART3_SERIALDRIVER
#ifdef CONFIG_STM32_USART3_SERIALDRIVER
case STM32_USART3_BASE:
rcc_en = RCC_APB1ENR1_USART3EN;
regaddr = STM32_RCC_APB1ENR1;
break;
#endif
#ifdef CONFIG_STM32U5_UART4_SERIALDRIVER
#ifdef CONFIG_STM32_UART4_SERIALDRIVER
case STM32_UART4_BASE:
rcc_en = RCC_APB1ENR1_UART4EN;
regaddr = STM32_RCC_APB1ENR1;
break;
#endif
#ifdef CONFIG_STM32U5_UART5_SERIALDRIVER
#ifdef CONFIG_STM32_UART5_SERIALDRIVER
case STM32_UART5_BASE:
rcc_en = RCC_APB1ENR1_UART5EN;
regaddr = STM32_RCC_APB1ENR1;
@@ -1428,7 +1428,7 @@ static int stm32serial_setup(struct uart_dev_s *dev)
{
uint32_t config = priv->rts_gpio;
#ifdef CONFIG_STM32U5_FLOWCONTROL_BROKEN
#ifdef CONFIG_STM32_FLOWCONTROL_BROKEN
/* Instead of letting hw manage this pin, we will bitbang */
config = (config & ~GPIO_MODE_MASK) | GPIO_OUTPUT;
@@ -1779,8 +1779,8 @@ static int stm32serial_interrupt(int irq, void *context, void *arg)
/* Report serial activity to the power management logic */
#if defined(CONFIG_PM) && CONFIG_STM32U5_PM_SERIAL_ACTIVITY > 0
pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32U5_PM_SERIAL_ACTIVITY);
#if defined(CONFIG_PM) && CONFIG_STM32_PM_SERIAL_ACTIVITY > 0
pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32_PM_SERIAL_ACTIVITY);
#endif
/* Loop until there are no characters to be transferred or,
@@ -1923,7 +1923,7 @@ static int stm32serial_ioctl(struct file *filep, int cmd,
break;
#endif
#ifdef CONFIG_STM32U5_USART_SINGLEWIRE
#ifdef CONFIG_STM32_USART_SINGLEWIRE
case TIOCSSINGLEWIRE:
{
uint32_t cr1;
@@ -2001,7 +2001,7 @@ static int stm32serial_ioctl(struct file *filep, int cmd,
break;
#endif
#ifdef CONFIG_STM32U5_USART_INVERT
#ifdef CONFIG_STM32_USART_INVERT
case TIOCSINVERT:
{
uint32_t cr1;
@@ -2052,7 +2052,7 @@ static int stm32serial_ioctl(struct file *filep, int cmd,
break;
#endif
#ifdef CONFIG_STM32U5_USART_SWAP
#ifdef CONFIG_STM32_USART_SWAP
case TIOCSSWAP:
{
uint32_t cr1;
@@ -2189,8 +2189,8 @@ static int stm32serial_ioctl(struct file *filep, int cmd,
break;
#endif /* CONFIG_SERIAL_TERMIOS */
#ifdef CONFIG_STM32U5_USART_BREAKS
# ifdef CONFIG_STM32U5_SERIALBRK_BSDCOMPAT
#ifdef CONFIG_STM32_USART_BREAKS
# ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT
case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */
{
irqstate_t flags;
@@ -2418,7 +2418,7 @@ static bool stm32serial_rxflowcontrol(struct uart_dev_s *dev,
(struct stm32_serial_s *)dev->priv;
#if defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) && \
defined(CONFIG_STM32U5_FLOWCONTROL_BROKEN)
defined(CONFIG_STM32_FLOWCONTROL_BROKEN)
if (priv->iflow && (priv->rts_gpio != 0))
{
/* Assert/de-assert nRTS set it high resume/stop sending */
@@ -2770,7 +2770,7 @@ static void stm32serial_txint(struct uart_dev_s *dev, bool enable)
}
# endif
# ifdef CONFIG_STM32U5_SERIALBRK_BSDCOMPAT
# ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT
if (priv->ie & USART_CR1_IE_BREAK_INPROGRESS)
{
leave_critical_section(flags);
@@ -3111,7 +3111,7 @@ void arm_serialinit(void)
#if CONSOLE_UART > 0
uart_register("/dev/console", &g_uart_devs[CONSOLE_UART - 1]->dev);
#ifndef CONFIG_STM32U5_SERIAL_DISABLE_REORDERING
#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING
/* If not disabled, register the console UART to ttyS0 and exclude
* it from initializing it further down
*/
@@ -3140,7 +3140,7 @@ void arm_serialinit(void)
continue;
}
#ifndef CONFIG_STM32U5_SERIAL_DISABLE_REORDERING
#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING
/* Don't create a device for the console - we did that above */
if (g_uart_devs[i]->dev.isconsole)
arch/arm/src/stm32u5/stm32_spi.c
+59 -59
View File
@@ -74,8 +74,8 @@
#include "stm32_gpio.h"
#include "stm32_spi.h"
#if defined(CONFIG_STM32U5_SPI1) || defined(CONFIG_STM32U5_SPI2) || \
defined(CONFIG_STM32U5_SPI3)
#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \
defined(CONFIG_STM32_SPI3)
/****************************************************************************
* Pre-processor Definitions
@@ -85,19 +85,19 @@
/* SPI interrupts */
#ifdef CONFIG_STM32U5_SPI_INTERRUPTS
#ifdef CONFIG_STM32_SPI_INTERRUPTS
# error "Interrupt driven SPI not yet supported"
#endif
/* Can't have both interrupt driven SPI and SPI DMA */
#if defined(CONFIG_STM32U5_SPI_INTERRUPTS) && defined(CONFIG_STM32U5_SPI_DMA)
#if defined(CONFIG_STM32_SPI_INTERRUPTS) && defined(CONFIG_STM32_SPI_DMA)
# error "Cannot enable both interrupt mode and DMA mode for SPI"
#endif
/* SPI DMA priority */
#ifdef CONFIG_STM32U5_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
# if defined(CONFIG_SPI_DMAPRIO)
# define SPI_DMA_PRIO CONFIG_SPI_DMAPRIO
@@ -135,21 +135,21 @@
# define SPIDMA_BUF_ALIGN
# endif
# if defined(CONFIG_STM32U5_SPI1_DMA_BUFFER) && \
CONFIG_STM32U5_SPI1_DMA_BUFFER > 0
# define SPI1_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32U5_SPI1_DMA_BUFFER)
# if defined(CONFIG_STM32_SPI1_DMA_BUFFER) && \
CONFIG_STM32_SPI1_DMA_BUFFER > 0
# define SPI1_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI1_DMA_BUFFER)
# define SPI1_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN
# endif
# if defined(CONFIG_STM32U5_SPI2_DMA_BUFFER) && \
CONFIG_STM32U5_SPI2_DMA_BUFFER > 0
# define SPI2_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32U5_SPI2_DMA_BUFFER)
# if defined(CONFIG_STM32_SPI2_DMA_BUFFER) && \
CONFIG_STM32_SPI2_DMA_BUFFER > 0
# define SPI2_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI2_DMA_BUFFER)
# define SPI2_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN
# endif
# if defined(CONFIG_STM32U5_SPI3_DMA_BUFFER) && \
CONFIG_STM32U5_SPI3_DMA_BUFFER > 0
# define SPI3_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32U5_SPI3_DMA_BUFFER)
# if defined(CONFIG_STM32_SPI3_DMA_BUFFER) && \
CONFIG_STM32_SPI3_DMA_BUFFER > 0
# define SPI3_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI3_DMA_BUFFER)
# define SPI3_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN
# endif
@@ -160,15 +160,15 @@
* - support for all kernel clock configuration
*/
#if defined(CONFIG_STM32U5_SPI1)
#if defined(CONFIG_STM32_SPI1)
# define SPI1_KERNEL_CLOCK_FREQ STM32_PCLK2_FREQUENCY
#endif
#if defined(CONFIG_STM32U5_SPI2)
#if defined(CONFIG_STM32_SPI2)
# define SPI2_KERNEL_CLOCK_FREQ STM32_PCLK1_FREQUENCY
#endif
#if defined(CONFIG_STM32U5_SPI3)
#if defined(CONFIG_STM32_SPI3)
# define SPI3_KERNEL_CLOCK_FREQ STM32_PCLK3_FREQUENCY
#endif
@@ -190,7 +190,7 @@ struct stm32_spidev_s
uint32_t spibase; /* SPIn base address */
uint32_t spiclock; /* Clocking for the SPI module */
uint8_t spiirq; /* SPI IRQ number */
#ifdef CONFIG_STM32U5_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
volatile uint8_t rxresult; /* Result of the RX DMA */
volatile uint8_t txresult; /* Result of the RX DMA */
#ifdef CONFIG_SPI_TRIGGER
@@ -240,7 +240,7 @@ static inline void spi_dumpregs(struct stm32_spidev_s *priv);
/* DMA support */
#ifdef CONFIG_STM32U5_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
static int spi_dmarxwait(struct stm32_spidev_s *priv);
static int spi_dmatxwait(struct stm32_spidev_s *priv);
static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv);
@@ -306,7 +306,7 @@ static int spi_pm_prepare(struct pm_callback_s *cb, int domain,
* Private Data
****************************************************************************/
#ifdef CONFIG_STM32U5_SPI1
#ifdef CONFIG_STM32_SPI1
static const struct spi_ops_s g_sp1iops =
{
.lock = spi_lock,
@@ -355,7 +355,7 @@ static struct stm32_spidev_s g_spi1dev =
.spibase = STM32_SPI1_BASE,
.spiclock = SPI1_KERNEL_CLOCK_FREQ,
.spiirq = STM32_IRQ_SPI1,
#ifdef CONFIG_STM32U5_SPI1_DMA
#ifdef CONFIG_STM32_SPI1_DMA
.rxch = DMAMAP_SPI1_RX,
.txch = DMAMAP_SPI1_TX,
# if defined(SPI1_DMABUFSIZE_ADJUSTED)
@@ -370,15 +370,15 @@ static struct stm32_spidev_s g_spi1dev =
#ifdef CONFIG_PM
.pm_cb.prepare = spi_pm_prepare,
#endif
#ifdef CONFIG_STM32U5_SPI1_COMMTYPE
.config = CONFIG_STM32U5_SPI1_COMMTYPE,
#ifdef CONFIG_STM32_SPI1_COMMTYPE
.config = CONFIG_STM32_SPI1_COMMTYPE,
#else
.config = FULL_DUPLEX,
#endif
};
#endif /* CONFIG_STM32U5_SPI1 */
#endif /* CONFIG_STM32_SPI1 */
#ifdef CONFIG_STM32U5_SPI2
#ifdef CONFIG_STM32_SPI2
static const struct spi_ops_s g_sp2iops =
{
.lock = spi_lock,
@@ -427,7 +427,7 @@ static struct stm32_spidev_s g_spi2dev =
.spibase = STM32_SPI2_BASE,
.spiclock = SPI2_KERNEL_CLOCK_FREQ,
.spiirq = STM32_IRQ_SPI2,
#ifdef CONFIG_STM32U5_SPI2_DMA
#ifdef CONFIG_STM32_SPI2_DMA
.rxch = DMAMAP_SPI2_RX,
.txch = DMAMAP_SPI2_TX,
# if defined(SPI2_DMABUFSIZE_ADJUSTED)
@@ -442,15 +442,15 @@ static struct stm32_spidev_s g_spi2dev =
#ifdef CONFIG_PM
.pm_cb.prepare = spi_pm_prepare,
#endif
#ifdef CONFIG_STM32U5_SPI2_COMMTYPE
.config = CONFIG_STM32U5_SPI2_COMMTYPE,
#ifdef CONFIG_STM32_SPI2_COMMTYPE
.config = CONFIG_STM32_SPI2_COMMTYPE,
#else
.config = FULL_DUPLEX,
#endif
};
#endif /* CONFIG_STM32U5_SPI2 */
#endif /* CONFIG_STM32_SPI2 */
#ifdef CONFIG_STM32U5_SPI3
#ifdef CONFIG_STM32_SPI3
static const struct spi_ops_s g_sp3iops =
{
.lock = spi_lock,
@@ -499,7 +499,7 @@ static struct stm32_spidev_s g_spi3dev =
.spibase = STM32_SPI3_BASE,
.spiclock = SPI3_KERNEL_CLOCK_FREQ,
.spiirq = STM32_IRQ_SPI3,
#ifdef CONFIG_STM32U5_SPI3_DMA
#ifdef CONFIG_STM32_SPI3_DMA
.rxch = DMAMAP_SPI3_RX,
.txch = DMAMAP_SPI3_TX,
# if defined(SPI3_DMABUFSIZE_ADJUSTED)
@@ -514,13 +514,13 @@ static struct stm32_spidev_s g_spi3dev =
#ifdef CONFIG_PM
.pm_cb.prepare = spi_pm_prepare,
#endif
#ifdef CONFIG_STM32U5_SPI3_COMMTYPE
.config = CONFIG_STM32U5_SPI3_COMMTYPE,
#ifdef CONFIG_STM32_SPI3_COMMTYPE
.config = CONFIG_STM32_SPI3_COMMTYPE,
#else
.config = FULL_DUPLEX,
#endif
};
#endif /* CONFIG_STM32U5_SPI3 */
#endif /* CONFIG_STM32_SPI3 */
/****************************************************************************
* Private Functions
@@ -840,7 +840,7 @@ static int spi_interrupt(int irq, void *context, void *arg)
spi_modifyreg(priv, STM32_SPI_IER_OFFSET, SPI_IER_EOTIE, 0);
/* Set result and release wait semaphore */
#ifdef CONFIG_STM32U5_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
priv->txresult = 0x80;
nxsem_post(&priv->txsem);
#endif
@@ -857,7 +857,7 @@ static int spi_interrupt(int irq, void *context, void *arg)
*
****************************************************************************/
#ifdef CONFIG_STM32U5_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
static int spi_dmarxwait(struct stm32_spidev_s *priv)
{
int ret;
@@ -897,7 +897,7 @@ static int spi_dmarxwait(struct stm32_spidev_s *priv)
*
****************************************************************************/
#ifdef CONFIG_STM32U5_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
static int spi_dmatxwait(struct stm32_spidev_s *priv)
{
int ret;
@@ -946,7 +946,7 @@ static int spi_dmatxwait(struct stm32_spidev_s *priv)
*
****************************************************************************/
#ifdef CONFIG_STM32U5_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv)
{
nxsem_post(&priv->rxsem);
@@ -961,7 +961,7 @@ static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv)
*
****************************************************************************/
#ifdef CONFIG_STM32U5_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg)
{
struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg;
@@ -981,7 +981,7 @@ static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg)
*
****************************************************************************/
#ifdef CONFIG_STM32U5_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
static void spi_dmarxsetup(struct stm32_spidev_s *priv,
void *rxbuffer, void *rxdummy,
size_t nwords, stm32_dmacfg_t *dmacfg)
@@ -1043,7 +1043,7 @@ static void spi_dmarxsetup(struct stm32_spidev_s *priv,
*
****************************************************************************/
#ifdef CONFIG_STM32U5_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
static void spi_dmatxsetup(struct stm32_spidev_s *priv,
const void *txbuffer, const void *txdummy,
size_t nwords, stm32_dmacfg_t *dmacfg)
@@ -1103,7 +1103,7 @@ static void spi_dmatxsetup(struct stm32_spidev_s *priv,
*
****************************************************************************/
#ifdef CONFIG_STM32U5_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
static void spi_dmarxstart(struct stm32_spidev_s *priv)
{
/* Can't receive in tx only mode */
@@ -1127,7 +1127,7 @@ static void spi_dmarxstart(struct stm32_spidev_s *priv)
*
****************************************************************************/
#ifdef CONFIG_STM32U5_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
static void spi_dmatxstart(struct stm32_spidev_s *priv)
{
/* Can't transmit in rx only mode */
@@ -1662,9 +1662,9 @@ static uint32_t spi_send(struct spi_dev_s *dev, uint32_t wd)
*
****************************************************************************/
#if !defined(CONFIG_STM32U5_SPI_DMA) || defined(CONFIG_STM32U5_DMACAPABLE) || \
defined(CONFIG_STM32U5_SPI_DMATHRESHOLD)
#if !defined(CONFIG_STM32U5_SPI_DMA)
#if !defined(CONFIG_STM32_SPI_DMA) || defined(CONFIG_STM32_DMACAPABLE) || \
defined(CONFIG_STM32_SPI_DMATHRESHOLD)
#if !defined(CONFIG_STM32_SPI_DMA)
static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
void *rxbuffer, size_t nwords)
#else
@@ -1753,8 +1753,8 @@ static void spi_exchange_nodma(struct spi_dev_s *dev,
}
}
#endif /* !CONFIG_STM32U5_SPI_DMA || CONFIG_STM32U5_DMACAPABLE ||
* CONFIG_STM32U5_SPI_DMATHRESHOLD
#endif /* !CONFIG_STM32_SPI_DMA || CONFIG_STM32_DMACAPABLE ||
* CONFIG_STM32_SPI_DMATHRESHOLD
*/
/****************************************************************************
@@ -1778,7 +1778,7 @@ static void spi_exchange_nodma(struct spi_dev_s *dev,
*
****************************************************************************/
#ifdef CONFIG_STM32U5_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
void *rxbuffer, size_t nwords)
{
@@ -1796,12 +1796,12 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
size_t nbytes = (priv->nbits > 8) ? nwords << 1 : nwords;
#ifdef CONFIG_STM32U5_SPI_DMATHRESHOLD
#ifdef CONFIG_STM32_SPI_DMATHRESHOLD
/* If this is a small SPI transfer, then let spi_exchange_nodma() do the
* work.
*/
if (nbytes <= CONFIG_STM32U5_SPI_DMATHRESHOLD)
if (nbytes <= CONFIG_STM32_SPI_DMATHRESHOLD)
{
spi_exchange_nodma(dev, txbuffer, rxbuffer, nwords);
return;
@@ -1865,7 +1865,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
spi_dmatxsetup(priv, txbuffer, &txdummy, nwords, &txdmacfg);
spi_dmarxsetup(priv, rxbuffer, (uint16_t *)rxdummy, nwords, &rxdmacfg);
#ifdef CONFIG_STM32U5_DMACAPABLE
#ifdef CONFIG_STM32_DMACAPABLE
/* Test for DMA capability of only callers buffers, internal buffers are
* guaranteed capable.
@@ -1995,7 +1995,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
priv->trigarmed = false;
#endif
}
#endif /* CONFIG_STM32U5_SPI_DMA */
#endif /* CONFIG_STM32_SPI_DMA */
/****************************************************************************
* Name: spi_trigger
@@ -2016,7 +2016,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
#ifdef CONFIG_SPI_TRIGGER
static int spi_trigger(struct spi_dev_s *dev)
{
#ifdef CONFIG_STM32U5_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev;
if (!priv->trigarmed)
@@ -2250,7 +2250,7 @@ static void spi_bus_initialize(struct stm32_spidev_s *priv)
spi_putreg(priv, STM32_SPI_CRCPOLY_OFFSET, 7);
#ifdef CONFIG_STM32U5_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
/* Get DMA channels. NOTE: stm32_dmachannel() will always assign the DMA
* channel. If the channel is not available, then stm32_dmachannel() will
* block and wait until the channel becomes available. WARNING: If you
@@ -2332,7 +2332,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus)
struct stm32_spidev_s *priv = NULL;
irqstate_t flags = enter_critical_section();
#ifdef CONFIG_STM32U5_SPI1
#ifdef CONFIG_STM32_SPI1
if (bus == 1)
{
/* Select SPI1 */
@@ -2357,7 +2357,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus)
}
else
#endif
#ifdef CONFIG_STM32U5_SPI2
#ifdef CONFIG_STM32_SPI2
if (bus == 2)
{
/* Select SPI2 */
@@ -2382,7 +2382,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus)
}
else
#endif
#ifdef CONFIG_STM32U5_SPI3
#ifdef CONFIG_STM32_SPI3
if (bus == 3)
{
/* Select SPI3 */
@@ -2415,5 +2415,5 @@ struct spi_dev_s *stm32_spibus_initialize(int bus)
return (struct spi_dev_s *)priv;
}
#endif /* CONFIG_STM32U5_SPI1 || CONFIG_STM32U5_SPI2 || CONFIG_STM32U5_SPI3
#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 || CONFIG_STM32_SPI3
*/
arch/arm/src/stm32u5/stm32_spi.h
+6 -6
View File
@@ -114,21 +114,21 @@ struct spi_slave_ctrlr_s *stm32_spi_slave_initialize(int bus);
*
****************************************************************************/
#ifdef CONFIG_STM32U5_SPI1
#ifdef CONFIG_STM32_SPI1
void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid,
bool selected);
uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid);
int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd);
#endif
#ifdef CONFIG_STM32U5_SPI2
#ifdef CONFIG_STM32_SPI2
void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid,
bool selected);
uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid);
int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd);
#endif
#ifdef CONFIG_STM32U5_SPI3
#ifdef CONFIG_STM32_SPI3
void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid,
bool selected);
uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid);
@@ -156,17 +156,17 @@ int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd);
****************************************************************************/
#ifdef CONFIG_SPI_CALLBACK
#ifdef CONFIG_STM32U5_SPI1
#ifdef CONFIG_STM32_SPI1
int stm32_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback,
void *arg);
#endif
#ifdef CONFIG_STM32U5_SPI2
#ifdef CONFIG_STM32_SPI2
int stm32_spi2register(struct spi_dev_s *dev, spi_mediachange_t callback,
void *arg);
#endif
#ifdef CONFIG_STM32U5_SPI3
#ifdef CONFIG_STM32_SPI3
int stm32_spi3register(struct spi_dev_s *dev, spi_mediachange_t callback,
void *arg);
#endif
arch/arm/src/stm32u5/stm32_start.c
+1 -1
View File
@@ -131,7 +131,7 @@ void __start(void)
("sub r10, sp, %0" : : "r" (CONFIG_IDLETHREAD_STACKSIZE - 64) :);
#endif
#ifdef CONFIG_STM32U5_SRAM2_INIT
#ifdef CONFIG_STM32_SRAM2_INIT
/* The SRAM2 region is parity checked, but upon power up, it will be in
* a random state and probably invalid with respect to parity, potentially
* generating faults if accessed. If elected, we will write zeros to the
arch/arm/src/stm32u5/stm32_tim.c
+123 -123
View File
File diff suppressed because it is too large Load Diff
arch/arm/src/stm32u5/stm32_tim_lowerhalf.c
+28 -28
View File
@@ -41,12 +41,12 @@
#include "stm32_tim.h"
#if defined(CONFIG_TIMER) && \
(defined(CONFIG_STM32U5_TIM1) || defined(CONFIG_STM32U5_TIM2) || \
defined(CONFIG_STM32U5_TIM3) || defined(CONFIG_STM32U5_TIM4) || \
defined(CONFIG_STM32U5_TIM5) || defined(CONFIG_STM32U5_TIM6) || \
defined(CONFIG_STM32U5_TIM7) || defined(CONFIG_STM32U5_TIM8) || \
defined(CONFIG_STM32U5_TIM15) || defined(CONFIG_STM32U5_TIM16) || \
defined(CONFIG_STM32U5_TIM17))
(defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \
defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \
defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \
defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \
defined(CONFIG_STM32_TIM15) || defined(CONFIG_STM32_TIM16) || \
defined(CONFIG_STM32_TIM17))
/****************************************************************************
* Pre-processor Definitions
@@ -118,7 +118,7 @@ static const struct timer_ops_s g_timer_ops =
.ioctl = NULL,
};
#ifdef CONFIG_STM32U5_TIM1
#ifdef CONFIG_STM32_TIM1
static struct stm32_lowerhalf_s g_tim1_lowerhalf =
{
.ops = &g_timer_ops,
@@ -126,7 +126,7 @@ static struct stm32_lowerhalf_s g_tim1_lowerhalf =
};
#endif
#ifdef CONFIG_STM32U5_TIM2
#ifdef CONFIG_STM32_TIM2
static struct stm32_lowerhalf_s g_tim2_lowerhalf =
{
.ops = &g_timer_ops,
@@ -134,7 +134,7 @@ static struct stm32_lowerhalf_s g_tim2_lowerhalf =
};
#endif
#ifdef CONFIG_STM32U5_TIM3
#ifdef CONFIG_STM32_TIM3
static struct stm32_lowerhalf_s g_tim3_lowerhalf =
{
.ops = &g_timer_ops,
@@ -142,7 +142,7 @@ static struct stm32_lowerhalf_s g_tim3_lowerhalf =
};
#endif
#ifdef CONFIG_STM32U5_TIM4
#ifdef CONFIG_STM32_TIM4
static struct stm32_lowerhalf_s g_tim4_lowerhalf =
{
.ops = &g_timer_ops,
@@ -150,7 +150,7 @@ static struct stm32_lowerhalf_s g_tim4_lowerhalf =
};
#endif
#ifdef CONFIG_STM32U5_TIM5
#ifdef CONFIG_STM32_TIM5
static struct stm32_lowerhalf_s g_tim5_lowerhalf =
{
.ops = &g_timer_ops,
@@ -158,7 +158,7 @@ static struct stm32_lowerhalf_s g_tim5_lowerhalf =
};
#endif
#ifdef CONFIG_STM32U5_TIM6
#ifdef CONFIG_STM32_TIM6
static struct stm32_lowerhalf_s g_tim6_lowerhalf =
{
.ops = &g_timer_ops,
@@ -166,7 +166,7 @@ static struct stm32_lowerhalf_s g_tim6_lowerhalf =
};
#endif
#ifdef CONFIG_STM32U5_TIM7
#ifdef CONFIG_STM32_TIM7
static struct stm32_lowerhalf_s g_tim7_lowerhalf =
{
.ops = &g_timer_ops,
@@ -174,7 +174,7 @@ static struct stm32_lowerhalf_s g_tim7_lowerhalf =
};
#endif
#ifdef CONFIG_STM32U5_TIM8
#ifdef CONFIG_STM32_TIM8
static struct stm32_lowerhalf_s g_tim8_lowerhalf =
{
.ops = &g_timer_ops,
@@ -182,7 +182,7 @@ static struct stm32_lowerhalf_s g_tim8_lowerhalf =
};
#endif
#ifdef CONFIG_STM32U5_TIM15
#ifdef CONFIG_STM32_TIM15
static struct stm32_lowerhalf_s g_tim15_lowerhalf =
{
.ops = &g_timer_ops,
@@ -190,7 +190,7 @@ static struct stm32_lowerhalf_s g_tim15_lowerhalf =
};
#endif
#ifdef CONFIG_STM32U5_TIM16
#ifdef CONFIG_STM32_TIM16
static struct stm32_lowerhalf_s g_tim16_lowerhalf =
{
.ops = &g_timer_ops,
@@ -198,7 +198,7 @@ static struct stm32_lowerhalf_s g_tim16_lowerhalf =
};
#endif
#ifdef CONFIG_STM32U5_TIM17
#ifdef CONFIG_STM32_TIM17
static struct stm32_lowerhalf_s g_tim17_lowerhalf =
{
.ops = &g_timer_ops,
@@ -503,66 +503,66 @@ int stm32_timer_initialize(const char *devpath, int timer)
switch (timer)
{
#ifdef CONFIG_STM32U5_TIM1
#ifdef CONFIG_STM32_TIM1
case 1:
lower = &g_tim1_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32U5_TIM2
#ifdef CONFIG_STM32_TIM2
case 2:
lower = &g_tim2_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32U5_TIM3
#ifdef CONFIG_STM32_TIM3
case 3:
lower = &g_tim3_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32U5_TIM4
#ifdef CONFIG_STM32_TIM4
case 4:
lower = &g_tim4_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32U5_TIM5
#ifdef CONFIG_STM32_TIM5
case 5:
lower = &g_tim5_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32U5_TIM6
#ifdef CONFIG_STM32_TIM6
case 6:
lower = &g_tim6_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32U5_TIM7
#ifdef CONFIG_STM32_TIM7
case 7:
lower = &g_tim7_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32U5_TIM8
#ifdef CONFIG_STM32_TIM8
case 8:
lower = &g_tim8_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32U5_TIM15
#ifdef CONFIG_STM32_TIM15
case 15:
lower = &g_tim15_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32U5_TIM16
#ifdef CONFIG_STM32_TIM16
case 16:
lower = &g_tim16_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32U5_TIM17
#ifdef CONFIG_STM32_TIM17
case 17:
lower = &g_tim17_lowerhalf;
break;
arch/arm/src/stm32u5/stm32_uart.h
+52 -52
View File
@@ -32,7 +32,7 @@
#include "chip.h"
#if defined(CONFIG_STM32U5_STM32U585XX) || defined(CONFIG_STM32U5_STM32U5A5XX)
#if defined(CONFIG_STM32_STM32U585XX) || defined(CONFIG_STM32_STM32U5A5XX)
# include "hardware/stm32_uart.h"
#else
# error "Unsupported STM32U5 chip"
@@ -46,63 +46,63 @@
* device.
*/
#if !defined(CONFIG_STM32U5_HAVE_UART5)
# undef CONFIG_STM32U5_UART5
#if !defined(CONFIG_STM32_HAVE_UART5)
# undef CONFIG_STM32_UART5
#endif
#if !defined(CONFIG_STM32U5_HAVE_UART4)
# undef CONFIG_STM32U5_UART4
#if !defined(CONFIG_STM32_HAVE_UART4)
# undef CONFIG_STM32_UART4
#endif
#if !defined(CONFIG_STM32U5_HAVE_USART3)
# undef CONFIG_STM32U5_USART3
#if !defined(CONFIG_STM32_HAVE_USART3)
# undef CONFIG_STM32_USART3
#endif
#if !defined(CONFIG_STM32U5_HAVE_USART2)
# undef CONFIG_STM32U5_USART2
#if !defined(CONFIG_STM32_HAVE_USART2)
# undef CONFIG_STM32_USART2
#endif
#if !defined(CONFIG_STM32U5_HAVE_USART1)
# undef CONFIG_STM32U5_USART1
#if !defined(CONFIG_STM32_HAVE_USART1)
# undef CONFIG_STM32_USART1
#endif
#if !defined(CONFIG_STM32U5_HAVE_LPUART1)
# undef CONFIG_STM32U5_LPUART1
#if !defined(CONFIG_STM32_HAVE_LPUART1)
# undef CONFIG_STM32_LPUART1
#endif
/* Sanity checks */
#if !defined(CONFIG_STM32U5_LPUART1)
# undef CONFIG_STM32U5_LPUART1_SERIALDRIVER
# undef CONFIG_STM32U5_LPUART1_1WIREDRIVER
#if !defined(CONFIG_STM32_LPUART1)
# undef CONFIG_STM32_LPUART1_SERIALDRIVER
# undef CONFIG_STM32_LPUART1_1WIREDRIVER
#endif
#if !defined(CONFIG_STM32U5_USART1)
# undef CONFIG_STM32U5_USART1_SERIALDRIVER
# undef CONFIG_STM32U5_USART1_1WIREDRIVER
#if !defined(CONFIG_STM32_USART1)
# undef CONFIG_STM32_USART1_SERIALDRIVER
# undef CONFIG_STM32_USART1_1WIREDRIVER
#endif
#if !defined(CONFIG_STM32U5_USART2)
# undef CONFIG_STM32U5_USART2_SERIALDRIVER
# undef CONFIG_STM32U5_USART2_1WIREDRIVER
#if !defined(CONFIG_STM32_USART2)
# undef CONFIG_STM32_USART2_SERIALDRIVER
# undef CONFIG_STM32_USART2_1WIREDRIVER
#endif
#if !defined(CONFIG_STM32U5_USART3)
# undef CONFIG_STM32U5_USART3_SERIALDRIVER
# undef CONFIG_STM32U5_USART3_1WIREDRIVER
#if !defined(CONFIG_STM32_USART3)
# undef CONFIG_STM32_USART3_SERIALDRIVER
# undef CONFIG_STM32_USART3_1WIREDRIVER
#endif
#if !defined(CONFIG_STM32U5_UART4)
# undef CONFIG_STM32U5_UART4_SERIALDRIVER
# undef CONFIG_STM32U5_UART4_1WIREDRIVER
#if !defined(CONFIG_STM32_UART4)
# undef CONFIG_STM32_UART4_SERIALDRIVER
# undef CONFIG_STM32_UART4_1WIREDRIVER
#endif
#if !defined(CONFIG_STM32U5_UART5)
# undef CONFIG_STM32U5_UART5_SERIALDRIVER
# undef CONFIG_STM32U5_UART5_1WIREDRIVER
#if !defined(CONFIG_STM32_UART5)
# undef CONFIG_STM32_UART5_SERIALDRIVER
# undef CONFIG_STM32_UART5_1WIREDRIVER
#endif
/* Is there a USART enabled? */
#if defined(CONFIG_STM32U5_LPUART1) || defined(CONFIG_STM32U5_USART1) || \
defined(CONFIG_STM32U5_USART2) || defined(CONFIG_STM32U5_USART3) || \
defined(CONFIG_STM32U5_UART4) || defined(CONFIG_STM32U5_UART5)
#if defined(CONFIG_STM32_LPUART1) || defined(CONFIG_STM32_USART1) || \
defined(CONFIG_STM32_USART2) || defined(CONFIG_STM32_USART3) || \
defined(CONFIG_STM32_UART4) || defined(CONFIG_STM32_UART5)
# define HAVE_UART 1
#endif
/* Is there a serial console? */
#if defined(CONFIG_LPUART1_SERIAL_CONSOLE) && defined(CONFIG_STM32U5_LPUART1_SERIALDRIVER)
#if defined(CONFIG_LPUART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_LPUART1_SERIALDRIVER)
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
@@ -110,7 +110,7 @@
# undef CONFIG_UART5_SERIAL_CONSOLE
# define CONSOLE_UART 1
# define HAVE_CONSOLE 1
#elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32U5_USART1_SERIALDRIVER)
#elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART1_SERIALDRIVER)
# undef CONFIG_LPUART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
@@ -118,28 +118,28 @@
# undef CONFIG_UART5_SERIAL_CONSOLE
# define CONSOLE_UART 2
# define HAVE_CONSOLE 1
#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32U5_USART2_SERIALDRIVER)
#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART2_SERIALDRIVER)
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# define CONSOLE_UART 3
# define HAVE_CONSOLE 1
#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_STM32U5_USART3_SERIALDRIVER)
#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART3_SERIALDRIVER)
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# define CONSOLE_UART 4
# define HAVE_CONSOLE 1
#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_STM32U5_UART4_SERIALDRIVER)
#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART4_SERIALDRIVER)
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# define CONSOLE_UART 5
# define HAVE_CONSOLE 1
#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_STM32U5_UART5_SERIALDRIVER)
#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART5_SERIALDRIVER)
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
@@ -170,27 +170,27 @@
/* Disable the DMA configuration on all unused USARTs */
#ifndef CONFIG_STM32U5_LPUART1_SERIALDRIVER
#ifndef CONFIG_STM32_LPUART1_SERIALDRIVER
# undef CONFIG_LPUART1_RXDMA
#endif
#ifndef CONFIG_STM32U5_USART1_SERIALDRIVER
#ifndef CONFIG_STM32_USART1_SERIALDRIVER
# undef CONFIG_USART1_RXDMA
#endif
#ifndef CONFIG_STM32U5_USART2_SERIALDRIVER
#ifndef CONFIG_STM32_USART2_SERIALDRIVER
# undef CONFIG_USART2_RXDMA
#endif
#ifndef CONFIG_STM32U5_USART3_SERIALDRIVER
#ifndef CONFIG_STM32_USART3_SERIALDRIVER
# undef CONFIG_USART3_RXDMA
#endif
#ifndef CONFIG_STM32U5_UART4_SERIALDRIVER
#ifndef CONFIG_STM32_UART4_SERIALDRIVER
# undef CONFIG_UART4_RXDMA
#endif
#ifndef CONFIG_STM32U5_UART5_SERIALDRIVER
#ifndef CONFIG_STM32_UART5_SERIALDRIVER
# undef CONFIG_UART5_RXDMA
#endif
@@ -223,17 +223,17 @@
/* Is DMA used on all (enabled) USARTs */
#define SERIAL_HAVE_ONLY_DMA 1
#if defined(CONFIG_STM32U5_LPUART1_SERIALDRIVER) && !defined(CONFIG_LPUART1_RXDMA)
#if defined(CONFIG_STM32_LPUART1_SERIALDRIVER) && !defined(CONFIG_LPUART1_RXDMA)
# undef SERIAL_HAVE_ONLY_DMA
#elif defined(CONFIG_STM32U5_USART1_SERIALDRIVER) && !defined(CONFIG_USART1_RXDMA)
#elif defined(CONFIG_STM32_USART1_SERIALDRIVER) && !defined(CONFIG_USART1_RXDMA)
# undef SERIAL_HAVE_ONLY_DMA
#elif defined(CONFIG_STM32U5_USART2_SERIALDRIVER) && !defined(CONFIG_USART2_RXDMA)
#elif defined(CONFIG_STM32_USART2_SERIALDRIVER) && !defined(CONFIG_USART2_RXDMA)
# undef SERIAL_HAVE_ONLY_DMA
#elif defined(CONFIG_STM32U5_USART3_SERIALDRIVER) && !defined(CONFIG_USART3_RXDMA)
#elif defined(CONFIG_STM32_USART3_SERIALDRIVER) && !defined(CONFIG_USART3_RXDMA)
# undef SERIAL_HAVE_ONLY_DMA
#elif defined(CONFIG_STM32U5_UART4_SERIALDRIVER) && !defined(CONFIG_UART4_RXDMA)
#elif defined(CONFIG_STM32_UART4_SERIALDRIVER) && !defined(CONFIG_UART4_RXDMA)
# undef SERIAL_HAVE_ONLY_DMA
#elif defined(CONFIG_STM32U5_UART5_SERIALDRIVER) && !defined(CONFIG_UART5_RXDMA)
#elif defined(CONFIG_STM32_UART5_SERIALDRIVER) && !defined(CONFIG_UART5_RXDMA)
# undef SERIAL_HAVE_ONLY_DMA
#endif
arch/arm/src/stm32u5/stm32u5xx_rcc.c
+80 -80
View File
@@ -60,7 +60,7 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1,
/* Determine if board wants to use HSI48 as 48 MHz oscillator. */
#if defined(CONFIG_STM32U5_HAVE_HSI48) && defined(STM32_USE_CLK48)
#if defined(CONFIG_STM32_HAVE_HSI48) && defined(STM32_USE_CLK48)
# if STM32_CLK48_SEL == RCC_CCIPR_CLK48SEL_HSI48
# define STM32_USE_HSI48
# endif
@@ -96,51 +96,51 @@ static inline void rcc_enableahb1(void)
regval |= RCC_AHB1ENR_GPDMA1EN;
#endif
#ifdef CONFIG_STM32U5_CORDIC
#ifdef CONFIG_STM32_CORDIC
regval |= RCC_AHB1ENR_CORDIC;
#endif
#ifdef CONFIG_STM32U5_FMAC
#ifdef CONFIG_STM32_FMAC
regval |= RCC_AHB1ENR_FMACEN;
#endif
#ifdef CONFIG_STM32U5_MDF1
#ifdef CONFIG_STM32_MDF1
regval |= RCC_AHB1ENR_MDF1EN;
#endif
#ifdef CONFIG_STM32U5_FLASH
#ifdef CONFIG_STM32_FLASH
regval |= RCC_AHB1ENR_FLASHEN;
#endif
#ifdef CONFIG_STM32U5_CRC
#ifdef CONFIG_STM32_CRC
regval |= RCC_AHB1ENR_CRCEN;
#endif
#ifdef CONFIG_STM32U5_TSC
#ifdef CONFIG_STM32_TSC
regval |= RCC_AHB1ENR_TSCEN;
#endif
#ifdef CONFIG_STM32U5_RAMCFG
#ifdef CONFIG_STM32_RAMCFG
regval |= RCC_AHB1ENR_RAMCFGEN;
#endif
#ifdef CONFIG_STM32U5_DMA2D
#ifdef CONFIG_STM32_DMA2D
regval |= RCC_AHB1ENR_DMA2DEN;
#endif
#ifdef CONFIG_STM32U5_GTZC1
#ifdef CONFIG_STM32_GTZC1
regval |= RCC_AHB1ENR_GTZC1EN;
#endif
#ifdef CONFIG_STM32U5_BKPSRAM
#ifdef CONFIG_STM32_BKPSRAM
regval |= RCC_AHB1ENR_BKPSRAMEN;
#endif
#ifdef CONFIG_STM32U5_DCACHE1
#ifdef CONFIG_STM32_DCACHE1
regval |= RCC_AHB1ENR_DCACHE1EN;
#endif
#ifdef CONFIG_STM32U5_SRAM1
#ifdef CONFIG_STM32_SRAM1
regval |= RCC_AHB1ENR_SRAM1EN;
#endif
@@ -194,51 +194,51 @@ static inline void rcc_enableahb2(void)
);
#endif
#if defined(CONFIG_STM32U5_ADC1)
#if defined(CONFIG_STM32_ADC1)
regval |= RCC_AHB2ENR1_ADC1EN;
#endif
#if defined(CONFIG_STM32U5_DCMI_PSSI)
#if defined(CONFIG_STM32_DCMI_PSSI)
regval |= RCC_AHB2ENR1_DCMI_PSSIEN;
#endif
#ifdef CONFIG_STM32U5_OTGHS
#ifdef CONFIG_STM32_OTGHS
regval |= RCC_AHB2ENR1_OTGEN;
#endif
#ifdef CONFIG_STM32U5_OTGHS
#ifdef CONFIG_STM32_OTGHS
regval |= RCC_AHB2ENR1_OTGPHYEN;
#endif
#ifdef CONFIG_STM32U5_AES
#ifdef CONFIG_STM32_AES
regval |= RCC_AHB2ENR1_AESEN;
#endif
#ifdef CONFIG_STM32U5_HASH
#ifdef CONFIG_STM32_HASH
regval |= RCC_AHB2ENR1_HASHEN
#endif
#ifdef CONFIG_STM32U5_RNG
#ifdef CONFIG_STM32_RNG
regval |= RCC_AHB2ENR1_RNGEN;
#endif
#ifdef CONFIG_STM32U5_PKA
#ifdef CONFIG_STM32_PKA
regval |= RCC_AHB2ENR_PKAEN;
#endif
#ifdef CONFIG_STM32U5_SAES
#ifdef CONFIG_STM32_SAES
regval |= RCC_AHB2ENR1_SAES;
#endif
#ifdef CONFIG_STM32U5_OCTOSPIM
#ifdef CONFIG_STM32_OCTOSPIM
regval |= RCC_AHB2ENR1_OCTOSPIM;
#endif
#ifdef CONFIG_STM32U5_OTFDEC1
#ifdef CONFIG_STM32_OTFDEC1
regval |= RCC_AHB2ENR1_OTFDEC1;
#endif
#ifdef CONFIG_STM32U5_OTFDEC2
#ifdef CONFIG_STM32_OTFDEC2
regval |= RCC_AHB2ENR1_OTFDEC2;
#endif
@@ -250,11 +250,11 @@ static inline void rcc_enableahb2(void)
regval |= RCC_AHB2ENR1_SDMMC2EN;
#endif
#ifdef CONFIG_STM32U5_SRAM2
#ifdef CONFIG_STM32_SRAM2
regval |= RCC_AHB2ENR1_SRAM2EN;
#endif
#ifdef CONFIG_STM32U5_SRAM3
#ifdef CONFIG_STM32_SRAM3
regval |= RCC_AHB2ENR1_SRAM3EN;
#endif
@@ -262,19 +262,19 @@ static inline void rcc_enableahb2(void)
regval = getreg32(STM32_RCC_AHB2ENR2);
#ifdef CONFIG_STM32U5_FSMC
#ifdef CONFIG_STM32_FSMC
regval |= RCC_AHB2ENR2_FSMCEN;
#endif
#ifdef CONFIG_STM32U5_OCTOSPI1
#ifdef CONFIG_STM32_OCTOSPI1
regval |= RCC_AHB2ENR2_OCTOSPI1EN;
#endif
#ifdef CONFIG_STM32U5_OCTOSPI2
#ifdef CONFIG_STM32_OCTOSPI2
regval |= RCC_AHB2ENR2_OCTOSPI2EN;
#endif
#ifdef CONFIG_STM32U5_SRAM5
#ifdef CONFIG_STM32_SRAM5
regval |= RCC_AHB2ENR2_SRAM5EN;
#endif
@@ -299,31 +299,31 @@ static inline void rcc_enableahb3(void)
regval = getreg32(STM32_RCC_AHB3ENR);
#ifdef CONFIG_STM32U5_LPGPIO1
#ifdef CONFIG_STM32_LPGPIO1
regval |= RCC_AHB3ENR_LPGPIO1EN;
#endif
#ifdef CONFIG_STM32U5_PWR
#ifdef CONFIG_STM32_PWR
regval |= RCC_AHB3ENR_PWREN;
#endif
#ifdef CONFIG_STM32U5_ADC4
#ifdef CONFIG_STM32_ADC4
regval |= RCC_AHB3ENR_ADC4EN;
#endif
#ifdef CONFIG_STM32U5_DAC1
#ifdef CONFIG_STM32_DAC1
regval |= RCC_AHB3ENR_DAC1EN;
#endif
#ifdef CONFIG_STM32U5_LPDMA1
#ifdef CONFIG_STM32_LPDMA1
regval |= RCC_AHB3ENR_LPDMA1EN;
#endif
#ifdef CONFIG_STM32U5_ADF1
#ifdef CONFIG_STM32_ADF1
regval |= RCC_AHB3ENR_ADF1EN;
#endif
#ifdef CONFIG_STM32U5_GTZC2
#ifdef CONFIG_STM32_GTZC2
regval |= RCC_AHB3ENR_GTZC2EN;
#endif
@@ -352,63 +352,63 @@ static inline void rcc_enableapb1(void)
regval = getreg32(STM32_RCC_APB1ENR1);
#ifdef CONFIG_STM32U5_TIM2
#ifdef CONFIG_STM32_TIM2
regval |= RCC_APB1ENR1_TIM2EN;
#endif
#ifdef CONFIG_STM32U5_TIM3
#ifdef CONFIG_STM32_TIM3
regval |= RCC_APB1ENR1_TIM3EN;
#endif
#ifdef CONFIG_STM32U5_TIM4
#ifdef CONFIG_STM32_TIM4
regval |= RCC_APB1ENR1_TIM4EN;
#endif
#ifdef CONFIG_STM32U5_TIM5
#ifdef CONFIG_STM32_TIM5
regval |= RCC_APB1ENR1_TIM5EN;
#endif
#ifdef CONFIG_STM32U5_TIM6
#ifdef CONFIG_STM32_TIM6
regval |= RCC_APB1ENR1_TIM6EN;
#endif
#ifdef CONFIG_STM32U5_TIM7
#ifdef CONFIG_STM32_TIM7
regval |= RCC_APB1ENR1_TIM7EN;
#endif
#ifdef CONFIG_STM32U5_WWDG
#ifdef CONFIG_STM32_WWDG
regval |= RCC_APB1ENR1_WWDGEN;
#endif
#ifdef CONFIG_STM32U5_SPI2
#ifdef CONFIG_STM32_SPI2
regval |= RCC_APB1ENR1_SPI2EN;
#endif
#ifdef CONFIG_STM32U5_USART2
#ifdef CONFIG_STM32_USART2
regval |= RCC_APB1ENR1_USART2EN;
#endif
#ifdef CONFIG_STM32U5_USART3
#ifdef CONFIG_STM32_USART3
regval |= RCC_APB1ENR1_USART3EN;
#endif
#ifdef CONFIG_STM32U5_UART4
#ifdef CONFIG_STM32_UART4
regval |= RCC_APB1ENR1_UART4EN;
#endif
#ifdef CONFIG_STM32U5_UART5
#ifdef CONFIG_STM32_UART5
regval |= RCC_APB1ENR1_UART5EN;
#endif
#ifdef CONFIG_STM32U5_I2C1
#ifdef CONFIG_STM32_I2C1
regval |= RCC_APB1ENR1_I2C1EN;
#endif
#ifdef CONFIG_STM32U5_I2C2
#ifdef CONFIG_STM32_I2C2
regval |= RCC_APB1ENR1_I2C2EN;
#endif
#ifdef CONFIG_STM32U5_CRS
#ifdef CONFIG_STM32_CRS
regval |= RCC_APB1ENR1_CRSEN;
#endif
@@ -418,19 +418,19 @@ static inline void rcc_enableapb1(void)
regval = getreg32(STM32_RCC_APB1ENR2);
#ifdef CONFIG_STM32U5_I2C4
#ifdef CONFIG_STM32_I2C4
regval |= RCC_APB1ENR2_I2C4EN;
#endif
#ifdef CONFIG_STM32U5_LPTIM2
#ifdef CONFIG_STM32_LPTIM2
regval |= RCC_APB1ENR2_LPTIM2EN;
#endif
#ifdef CONFIG_STM32U5_FDCAN1
#ifdef CONFIG_STM32_FDCAN1
regval |= RCC_APB1ENR2_FDCAN1EN;
#endif
#ifdef CONFIG_STM32U5_UCPD1
#ifdef CONFIG_STM32_UCPD1
regval |= RCC_APB1ENR2_UCPD1EN;
#endif
@@ -455,39 +455,39 @@ static inline void rcc_enableapb2(void)
regval = getreg32(STM32_RCC_APB2ENR);
#ifdef CONFIG_STM32U5_TIM1
#ifdef CONFIG_STM32_TIM1
regval |= RCC_APB2ENR_TIM1EN;
#endif
#ifdef CONFIG_STM32U5_SPI1
#ifdef CONFIG_STM32_SPI1
regval |= RCC_APB2ENR_SPI1EN;
#endif
#ifdef CONFIG_STM32U5_TIM8
#ifdef CONFIG_STM32_TIM8
regval |= RCC_APB2ENR_TIM8EN;
#endif
#ifdef CONFIG_STM32U5_USART1
#ifdef CONFIG_STM32_USART1
regval |= RCC_APB2ENR_USART1EN;
#endif
#ifdef CONFIG_STM32U5_TIM15
#ifdef CONFIG_STM32_TIM15
regval |= RCC_APB2ENR_TIM15EN;
#endif
#ifdef CONFIG_STM32U5_TIM16
#ifdef CONFIG_STM32_TIM16
regval |= RCC_APB2ENR_TIM16EN;
#endif
#ifdef CONFIG_STM32U5_TIM17
#ifdef CONFIG_STM32_TIM17
regval |= RCC_APB2ENR_TIM17EN;
#endif
#ifdef CONFIG_STM32U5_SAI1
#ifdef CONFIG_STM32_SAI1
regval |= RCC_APB2ENR_SAI1EN;
#endif
#ifdef CONFIG_STM32U5_SAI2
#ifdef CONFIG_STM32_SAI2
regval |= RCC_APB2ENR_SAI2EN;
#endif
@@ -512,15 +512,15 @@ static inline void rcc_enableapb3(void)
regval = getreg32(STM32_RCC_APB3ENR);
#ifdef CONFIG_STM32U5_SYSCFG
#ifdef CONFIG_STM32_SYSCFG
regval |= RCC_APB3ENR_SYSCFGEN;
#endif
#ifdef CONFIG_STM32U5_SPI3
#ifdef CONFIG_STM32_SPI3
regval |= RCC_APB3ENR_SPI3EN;
#endif
#ifdef CONFIG_STM32U5_LPUART1
#ifdef CONFIG_STM32_LPUART1
regval |= RCC_APB3ENR_LPUART1EN;
#endif
@@ -528,31 +528,31 @@ static inline void rcc_enableapb3(void)
regval |= RCC_APB3ENR_I2C3EN;
#endif
#ifdef CONFIG_STM32U5_LPTIM1
#ifdef CONFIG_STM32_LPTIM1
regval |= RCC_APB3ENR_LPTIM1EN;
#endif
#ifdef CONFIG_STM32U5_LPTIM3
#ifdef CONFIG_STM32_LPTIM3
regval |= RCC_APB3ENR_LPTIM3EN;
#endif
#ifdef CONFIG_STM32U5_LPTIM4
#ifdef CONFIG_STM32_LPTIM4
regval |= RCC_APB3ENR_LPTIM4EN;
#endif
#ifdef CONFIG_STM32U5_OPAMP
#ifdef CONFIG_STM32_OPAMP
regval |= RCC_APB3ENR_OPAMPEN;
#endif
#ifdef CONFIG_STM32U5_COMP
#ifdef CONFIG_STM32_COMP
regval |= RCC_APB3ENR_COMPEN;
#endif
#ifdef CONFIG_STM32U5_VREF
#ifdef CONFIG_STM32_VREF
regval |= RCC_APB3ENR_VREFEN;
#endif
#ifdef CONFIG_STM32U5_RTCAPB
#ifdef CONFIG_STM32_RTCAPB
regval |= RCC_APB3ENR_RTCAPBEN;
#endif
@@ -604,7 +604,7 @@ void stm32_rcc_enableperipherals(void)
* power clocking modes!
****************************************************************************/
#ifndef CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG
#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG
void stm32_stdclockconfig(void)
{
uint32_t regval;
@@ -742,9 +742,9 @@ void stm32_stdclockconfig(void)
regval |= STM32_RCC_CFGR3_PPRE3;
putreg32(regval, STM32_RCC_CFGR3);
#ifdef CONFIG_STM32U5_RTC_HSECLOCK
#ifdef CONFIG_STM32_RTC_HSECLOCK
# error stm32_stdclockconfig() currently doesn not support CONFIG_STM32U5_RTC_HSECLOCK
# error stm32_stdclockconfig() currently doesn not support CONFIG_STM32_RTC_HSECLOCK
#endif
@@ -799,7 +799,7 @@ void stm32_stdclockconfig(void)
{
}
#if defined(CONFIG_STM32U5_IWDG) || defined(CONFIG_STM32U5_RTC_LSICLOCK)
#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_STM32_RTC_LSICLOCK)
/* Low speed internal clock source LSI */
stm32_rcc_enablelsi();
boards/arm/stm32u5/b-u585i-iot02a/configs/nsh/defconfig
+5 -4
View File
@@ -11,6 +11,7 @@ CONFIG_ARCH="arm"
CONFIG_ARCH_BOARD="b-u585i-iot02a"
CONFIG_ARCH_BOARD_B_U585I_IOT02A=y
CONFIG_ARCH_CHIP="stm32u5"
CONFIG_ARCH_CHIP_STM32=y
CONFIG_ARCH_CHIP_STM32U585AI=y
CONFIG_ARCH_CHIP_STM32U5=y
CONFIG_ARCH_INTERRUPTSTACK=2048
@@ -45,10 +46,10 @@ CONFIG_READLINE_TABCOMPLETION=y
CONFIG_RR_INTERVAL=200
CONFIG_SCHED_WAITPID=y
CONFIG_STACK_COLORATION=y
CONFIG_STM32U5_PWR=y
CONFIG_STM32U5_SPI1=y
CONFIG_STM32U5_SRAM3=y
CONFIG_STM32U5_USART1=y
CONFIG_STM32_PWR=y
CONFIG_STM32_SPI1=y
CONFIG_STM32_SRAM3=y
CONFIG_STM32_USART1=y
CONFIG_SYSTEM_NSH=y
CONFIG_SYSTEM_SPITOOL=y
CONFIG_SYSTEM_STACKMONITOR=y
boards/arm/stm32u5/b-u585i-iot02a/src/CMakeLists.txt
+1 -1
View File
@@ -22,7 +22,7 @@
set(SRCS stm32_boot.c stm32_bringup.c stm32_spi.c)
if(CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG)
if(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG)
list(APPEND SRCS stm32_clockconfig.c)
endif()
boards/arm/stm32u5/b-u585i-iot02a/src/Makefile
+1 -1
View File
@@ -25,7 +25,7 @@
ASRCS =
CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c
ifeq ($(CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG),y)
ifeq ($(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG),y)
CSRCS += stm32_clockconfig.c
endif
boards/arm/stm32u5/b-u585i-iot02a/src/stm32_clockconfig.c
+2 -2
View File
@@ -38,12 +38,12 @@
* NuttX in the Non-Secure domain together with TrustedFirmware-M (TFM).
* In this setup the clock configuration is done by TFM, not by NuttX.
* Thus, the board's configuration sets
* CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG to avoid the standard clock
* CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG to avoid the standard clock
* config logic to run and instead do just nothing in this function.
*
****************************************************************************/
#if defined(CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG)
#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG)
void stm32_board_clockconfig(void)
{
}
boards/arm/stm32u5/b-u585i-iot02a/src/stm32_spi.c
+9 -9
View File
@@ -41,7 +41,7 @@
#include "b-u585i-iot02a.h"
#include <arch/board/board.h>
#ifdef CONFIG_STM32U5_SPI
#ifdef CONFIG_STM32_SPI
/****************************************************************************
* Public Functions
@@ -64,7 +64,7 @@ void stm32_spidev_initialize(void)
* architecture.
*/
#ifdef CONFIG_STM32U5_SPI1
#ifdef CONFIG_STM32_SPI1
stm32_configgpio(GPIO_SPI1_NSS);
#endif
}
@@ -95,7 +95,7 @@ void stm32_spidev_initialize(void)
*
****************************************************************************/
#ifdef CONFIG_STM32U5_SPI1
#ifdef CONFIG_STM32_SPI1
void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid,
bool selected)
{
@@ -111,7 +111,7 @@ uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid)
}
#endif
#ifdef CONFIG_STM32U5_SPI2
#ifdef CONFIG_STM32_SPI2
void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid,
bool selected)
{
@@ -125,7 +125,7 @@ uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid)
}
#endif
#ifdef CONFIG_STM32U5_SPI3
#ifdef CONFIG_STM32_SPI3
void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid,
bool selected)
{
@@ -162,25 +162,25 @@ uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid)
****************************************************************************/
#ifdef CONFIG_SPI_CMDDATA
#ifdef CONFIG_STM32U5_SPI1
#ifdef CONFIG_STM32_SPI1
int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd)
{
return -ENODEV;
}
#endif
#ifdef CONFIG_STM32U5_SPI2
#ifdef CONFIG_STM32_SPI2
int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd)
{
return -ENODEV;
}
#endif
#ifdef CONFIG_STM32U5_SPI3
#ifdef CONFIG_STM32_SPI3
int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd)
{
return -ENODEV;
}
#endif
#endif /* CONFIG_SPI_CMDDATA */
#endif /* CONFIG_STM32U5_SPI */
#endif /* CONFIG_STM32_SPI */
boards/arm/stm32u5/nucleo-u5a5zj-q/configs/nsh/defconfig
+9 -8
View File
@@ -12,6 +12,7 @@ CONFIG_ARCH="arm"
CONFIG_ARCH_BOARD="nucleo-u5a5zj-q"
CONFIG_ARCH_BOARD_NUCLEO_U5A5ZJ_Q=y
CONFIG_ARCH_CHIP="stm32u5"
CONFIG_ARCH_CHIP_STM32=y
CONFIG_ARCH_CHIP_STM32U5=y
CONFIG_ARCH_CHIP_STM32U5A5ZJT=y
CONFIG_ARCH_INTERRUPTSTACK=2048
@@ -47,14 +48,14 @@ CONFIG_READLINE_TABCOMPLETION=y
CONFIG_RR_INTERVAL=200
CONFIG_SCHED_WAITPID=y
CONFIG_STACK_COLORATION=y
CONFIG_STM32U5_PWR=y
CONFIG_STM32U5_SRAM2=y
CONFIG_STM32U5_SRAM2_HEAP=y
CONFIG_STM32U5_SRAM3=y
CONFIG_STM32U5_SRAM3_HEAP=y
CONFIG_STM32U5_SRAM5=y
CONFIG_STM32U5_SRAM5_HEAP=y
CONFIG_STM32U5_USART1=y
CONFIG_STM32_PWR=y
CONFIG_STM32_SRAM2=y
CONFIG_STM32_SRAM2_HEAP=y
CONFIG_STM32_SRAM3=y
CONFIG_STM32_SRAM3_HEAP=y
CONFIG_STM32_SRAM5=y
CONFIG_STM32_SRAM5_HEAP=y
CONFIG_STM32_USART1=y
CONFIG_SYSTEM_NSH=y
CONFIG_SYSTEM_NSH_STACKSIZE=2048
CONFIG_SYSTEM_TEE=y
boards/arm/stm32u5/nucleo-u5a5zj-q/src/CMakeLists.txt
+1 -1
View File
@@ -22,7 +22,7 @@
set(SRCS stm32_boot.c stm32_bringup.c stm32_spi.c)
if(CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG)
if(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG)
list(APPEND SRCS stm32_clockconfig.c)
endif()
boards/arm/stm32u5/nucleo-u5a5zj-q/src/Makefile
+1 -1
View File
@@ -25,7 +25,7 @@
ASRCS =
CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c
ifeq ($(CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG),y)
ifeq ($(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG),y)
CSRCS += stm32_clockconfig.c
endif
boards/arm/stm32u5/nucleo-u5a5zj-q/src/stm32_clockconfig.c
+2 -2
View File
@@ -38,12 +38,12 @@
* NuttX in the Non-Secure domain together with TrustedFirmware-M (TFM).
* In this setup the clock configuration is done by TFM, not by NuttX.
* Thus, the board's configuration sets
* CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG to avoid the standard clock
* CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG to avoid the standard clock
* config logic to run and instead do just nothing in this function.
*
****************************************************************************/
#if defined(CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG)
#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG)
void stm32_board_clockconfig(void)
{
}
boards/arm/stm32u5/nucleo-u5a5zj-q/src/stm32_spi.c
+9 -9
View File
@@ -41,7 +41,7 @@
#include "nucleo-u5a5zj-q.h"
#include <arch/board/board.h>
#ifdef CONFIG_STM32U5_SPI
#ifdef CONFIG_STM32_SPI
/****************************************************************************
* Public Functions
@@ -64,7 +64,7 @@ void stm32_spidev_initialize(void)
* architecture.
*/
#ifdef CONFIG_STM32U5_SPI1
#ifdef CONFIG_STM32_SPI1
stm32_configgpio(GPIO_SPI1_NSS);
#endif
}
@@ -95,7 +95,7 @@ void stm32_spidev_initialize(void)
*
****************************************************************************/
#ifdef CONFIG_STM32U5_SPI1
#ifdef CONFIG_STM32_SPI1
void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid,
bool selected)
{
@@ -111,7 +111,7 @@ uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid)
}
#endif
#ifdef CONFIG_STM32U5_SPI2
#ifdef CONFIG_STM32_SPI2
void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid,
bool selected)
{
@@ -125,7 +125,7 @@ uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid)
}
#endif
#ifdef CONFIG_STM32U5_SPI3
#ifdef CONFIG_STM32_SPI3
void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid,
bool selected)
{
@@ -162,25 +162,25 @@ uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid)
****************************************************************************/
#ifdef CONFIG_SPI_CMDDATA
#ifdef CONFIG_STM32U5_SPI1
#ifdef CONFIG_STM32_SPI1
int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd)
{
return -ENODEV;
}
#endif
#ifdef CONFIG_STM32U5_SPI2
#ifdef CONFIG_STM32_SPI2
int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd)
{
return -ENODEV;
}
#endif
#ifdef CONFIG_STM32U5_SPI3
#ifdef CONFIG_STM32_SPI3
int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd)
{
return -ENODEV;
}
#endif
#endif /* CONFIG_SPI_CMDDATA */
#endif /* CONFIG_STM32U5_SPI */
#endif /* CONFIG_STM32_SPI */