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Revert "arm64: refine the fatal handler"

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This reverts commit 291d5a2acc.
This commit is contained in:
Xiang Xiao
2024-09-24 00:32:34 -07:00
committed by Alan C. Assis
parent 9e8df3b3fa
commit dc6eeba453
4 changed files with 318 additions and 638 deletions
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arch/arm64/src/common/arm64_fatal.c
+274 -476
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File diff suppressed because it is too large Load Diff
arch/arm64/src/common/arm64_fatal.h
+13 -145
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@@ -21,6 +21,12 @@
#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_FATAL_H #ifndef __ARCH_ARM64_SRC_COMMON_ARM64_FATAL_H
#define __ARCH_ARM64_SRC_COMMON_ARM64_FATAL_H #define __ARCH_ARM64_SRC_COMMON_ARM64_FATAL_H
/* Fatal error APIs */
#define K_ERR_CPU_EXCEPTION (0)
#define K_ERR_CPU_MODE32 (1)
#define K_ERR_SPURIOUS_IRQ (2)
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__
/**************************************************************************** /****************************************************************************
@@ -37,123 +43,6 @@
* Pre-processor Definitions * Pre-processor Definitions
****************************************************************************/ ****************************************************************************/
#define ESR_ELX_EC_UNKNOWN (0x00)
#define ESR_ELX_EC_WFX (0x01)
/* Unallocated EC: 0x02 */
#define ESR_ELX_EC_CP15_32 (0x03)
#define ESR_ELX_EC_CP15_64 (0x04)
#define ESR_ELX_EC_CP14_MR (0x05)
#define ESR_ELX_EC_CP14_LS (0x06)
#define ESR_ELX_EC_FP_ASIMD (0x07)
#define ESR_ELX_EC_CP10_ID (0x08) /* EL2 only */
#define ESR_ELX_EC_PAC (0x09) /* EL2 and above */
/* Unallocated EC: 0x0A - 0x0B */
#define ESR_ELX_EC_CP14_64 (0x0C)
#define ESR_ELX_EC_BTI (0x0D)
#define ESR_ELX_EC_ILL (0x0E)
/* Unallocated EC: 0x0F - 0x10 */
#define ESR_ELX_EC_SVC32 (0x11)
#define ESR_ELX_EC_HVC32 (0x12) /* EL2 only */
#define ESR_ELX_EC_SMC32 (0x13) /* EL2 and above */
/* Unallocated EC: 0x14 */
#define ESR_ELX_EC_SVC64 (0x15)
#define ESR_ELX_EC_HVC64 (0x16) /* EL2 and above */
#define ESR_ELX_EC_SMC64 (0x17) /* EL2 and above */
#define ESR_ELX_EC_SYS64 (0x18)
#define ESR_ELX_EC_SVE (0x19)
#define ESR_ELX_EC_ERET (0x1a) /* EL2 only */
/* Unallocated EC: 0x1B */
#define ESR_ELX_EC_FPAC (0x1C) /* EL1 and above */
#define ESR_ELX_EC_SME (0x1D)
/* Unallocated EC: 0x1D - 0x1E */
#define ESR_ELX_EC_IMP_DEF (0x1f) /* EL3 only */
#define ESR_ELX_EC_IABT_LOW (0x20)
#define ESR_ELX_EC_IABT_CUR (0x21)
#define ESR_ELX_EC_PC_ALIGN (0x22)
/* Unallocated EC: 0x23 */
#define ESR_ELX_EC_DABT_LOW (0x24)
#define ESR_ELX_EC_DABT_CUR (0x25)
#define ESR_ELX_EC_SP_ALIGN (0x26)
#define ESR_ELX_EC_MOPS (0x27)
#define ESR_ELX_EC_FP_EXC32 (0x28)
/* Unallocated EC: 0x29 - 0x2B */
#define ESR_ELX_EC_FP_EXC64 (0x2C)
/* Unallocated EC: 0x2D - 0x2E */
#define ESR_ELX_EC_SERROR (0x2F)
#define ESR_ELX_EC_BREAKPT_LOW (0x30)
#define ESR_ELX_EC_BREAKPT_CUR (0x31)
#define ESR_ELX_EC_SOFTSTP_LOW (0x32)
#define ESR_ELX_EC_SOFTSTP_CUR (0x33)
#define ESR_ELX_EC_WATCHPT_LOW (0x34)
#define ESR_ELX_EC_WATCHPT_CUR (0x35)
/* Unallocated EC: 0x36 - 0x37 */
#define ESR_ELX_EC_BKPT32 (0x38)
/* Unallocated EC: 0x39 */
#define ESR_ELX_EC_VECTOR32 (0x3A) /* EL2 only */
/* Unallocated EC: 0x3B */
#define ESR_ELX_EC_BRK64 (0x3C)
/* Unallocated EC: 0x3D - 0x3F */
#define ESR_ELX_EC_MAX (0x3F)
#define ESR_ELX_EC_SHIFT (26)
#define ESR_ELX_EC_WIDTH (6)
#define ESR_ELX_EC_MASK (0x3F << ESR_ELX_EC_SHIFT)
#define ESR_ELX_EC(esr) (((esr) & ESR_ELX_EC_MASK) \
>> ESR_ELX_EC_SHIFT)
/* Shared ISS fault status code(IFSC/DFSC) for Data/Instruction aborts */
#define ESR_ELX_FSC (0x3F)
#define ESR_ELX_FSC_TYPE (0x3C)
#define ESR_ELX_FSC_LEVEL (0x03)
#define ESR_ELX_FSC_EXTABT (0x10)
#define ESR_ELX_FSC_MTE (0x11)
#define ESR_ELX_FSC_SERROR (0x11)
#define ESR_ELX_FSC_ACCESS (0x08)
#define ESR_ELX_FSC_FAULT (0x04)
#define ESR_ELX_FSC_PERM (0x0C)
#define ESR_ELX_FSC_SEA_TTW0 (0x14)
#define ESR_ELX_FSC_SEA_TTW1 (0x15)
#define ESR_ELX_FSC_SEA_TTW2 (0x16)
#define ESR_ELX_FSC_SEA_TTW3 (0x17)
#define ESR_ELX_FSC_SECC (0x18)
#define ESR_ELX_FSC_SECC_TTW0 (0x1c)
#define ESR_ELX_FSC_SECC_TTW1 (0x1d)
#define ESR_ELX_FSC_SECC_TTW2 (0x1e)
#define ESR_ELX_FSC_SECC_TTW3 (0x1f)
#define DBG_ESR_EVT(x) (((x) >> 27) & 0x7)
#define DBG_ESR_EVT_HWBP (0x0)
#define DBG_ESR_EVT_HWSS (0x1)
#define DBG_ESR_EVT_HWWP (0x2)
#define DBG_ESR_EVT_BRK (0x6)
#define __builtin_unreachable() \ #define __builtin_unreachable() \
do \ do \
{ \ { \
@@ -162,49 +51,28 @@
} while (true) } while (true)
/**************************************************************************** /****************************************************************************
* Public Type Declarations * Public Data
****************************************************************************/ ****************************************************************************/
typedef int (*fatal_handle_func_t)(struct regs_context *regs,
uint64_t far, uint64_t esr);
/**************************************************************************** /****************************************************************************
* Public Function Prototypes * Public Function Prototypes
****************************************************************************/ ****************************************************************************/
/**************************************************************************** /****************************************************************************
* Name: arm64_fatal_handler * Name: arm64_fatal_error
* *
* Description: * Description:
* Fatal handle for arm64 * fatal error handle for arm64
* Input Parameters: * Input Parameters:
* reason: error reason
* reg: exception stack reg context * reg: exception stack reg context
* *
* Returned Value: None * Returned Value:
* If the function return, the exception has been handled
* *
****************************************************************************/ ****************************************************************************/
void arm64_fatal_handler(struct regs_context *reg); void arm64_fatal_error(unsigned int reason, struct regs_context * reg);
void arm64_dump_fatal(struct regs_context * reg);
/****************************************************************************
* Name: arm64_register_debug_hook
*
* Description:
* Register a hook function for DEBUG event
* Input Parameters:
* nr: DEBUG event
* DBG_ESR_EVT_HWBP : Hardware BreakPoint
* DBG_ESR_EVT_HWSS : Hardware SingleStep
* DBG_ESR_EVT_HWWP : Hardware WatchPoint
* DBG_ESR_EVT_BRK : Brk instruction trigger
* fn: hook function
*
* Returned Value: none
*
****************************************************************************/
void arm64_register_debug_hook(int nr, fatal_handle_func_t fn);
#endif /* __ASSEMBLY__ */ #endif /* __ASSEMBLY__ */
arch/arm64/src/common/arm64_vector_table.S
+4 -4
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@@ -216,25 +216,25 @@ SECTION_SUBSEC_FUNC(exc_vector_table,_vector_table_section,_vector_table)
.align 7 .align 7
arm64_enter_exception x0, x1 arm64_enter_exception x0, x1
b arm64_mode32_handler b arm64_mode32_error
/* Lower EL using AArch32 / IRQ */ /* Lower EL using AArch32 / IRQ */
.align 7 .align 7
arm64_enter_exception x0, x1 arm64_enter_exception x0, x1
b arm64_mode32_handler b arm64_mode32_error
/* Lower EL using AArch32 / FIQ */ /* Lower EL using AArch32 / FIQ */
.align 7 .align 7
arm64_enter_exception x0, x1 arm64_enter_exception x0, x1
b arm64_mode32_handler b arm64_mode32_error
/* Lower EL using AArch32 / SError */ /* Lower EL using AArch32 / SError */
.align 7 .align 7
arm64_enter_exception x0, x1 arm64_enter_exception x0, x1
b arm64_mode32_handler b arm64_mode32_error
/* Restore Corruptible Registers and exception context /* Restore Corruptible Registers and exception context
* from the task stack. * from the task stack.
arch/arm64/src/common/arm64_vectors.S
+27 -13
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@@ -355,13 +355,16 @@ save_context:
b arm64_exit_exception b arm64_exit_exception
exc_handle: exc_handle:
mov x0, sp arm64_exception_context_save x0 x1 sp
mov x0, #K_ERR_CPU_EXCEPTION
mov x1, sp
/* void arm64_fatal_handler(struct regs_context * reg); /* void arm64_fatal_error(unsigned int reason, const uint64_t *regs)
* x0 = Exception stack frame * x0 = reason
* x1 = Exception stack frame
*/ */
bl arm64_fatal_handler bl arm64_fatal_error
/* Return here only in case of recoverable error */ /* Return here only in case of recoverable error */
@@ -442,20 +445,28 @@ irq_context_switch:
irq_exit: irq_exit:
b arm64_exit_exception b arm64_exit_exception
/* TODO: if the arm64_fatal_handler return success, maybe need context switch */ /* TODO: if the arm64_fatal_error return success, maybe need context switch */
GTEXT(arm64_serror_handler) GTEXT(arm64_serror_handler)
SECTION_FUNC(text, arm64_serror_handler) SECTION_FUNC(text, arm64_serror_handler)
mov x0, sp arm64_exception_context_save x0 x1 sp
bl arm64_fatal_handler
mov x0, #K_ERR_CPU_EXCEPTION
mov x1, sp
bl arm64_fatal_error
/* Return here only in case of recoverable error */ /* Return here only in case of recoverable error */
b arm64_exit_exception b arm64_exit_exception
GTEXT(arm64_mode32_handler) GTEXT(arm64_mode32_error)
SECTION_FUNC(text, arm64_mode32_handler) SECTION_FUNC(text, arm64_mode32_error)
mov x0, sp arm64_exception_context_save x0 x1 sp
bl arm64_fatal_handler
mov x1, sp
mov x0, #K_ERR_CPU_MODE32
bl arm64_fatal_error
/* Return here only in case of recoverable error */ /* Return here only in case of recoverable error */
b arm64_exit_exception b arm64_exit_exception
@@ -463,9 +474,12 @@ SECTION_FUNC(text, arm64_mode32_handler)
GTEXT(arm64_fiq_handler) GTEXT(arm64_fiq_handler)
SECTION_FUNC(text, arm64_fiq_handler) SECTION_FUNC(text, arm64_fiq_handler)
#ifndef CONFIG_ARM64_DECODEFIQ #ifndef CONFIG_ARM64_DECODEFIQ
arm64_exception_context_save x0 x1 sp
mov x0, sp mov x1, sp
bl arm64_fatal_handler mov x0, #K_ERR_SPURIOUS_IRQ /* K_ERR_SPURIOUS_IRQ */
bl arm64_fatal_error
/* Return here only in case of recoverable error */ /* Return here only in case of recoverable error */