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Revert "arm64: refine the fatal handler"
This reverts commit 291d5a2acc.
This commit is contained in:
Xiang Xiao
committed by
Alan C. Assis
Alan C. Assis
parent
9e8df3b3fa
commit
dc6eeba453
+274
-476
File diff suppressed because it is too large
Load Diff
@@ -21,6 +21,12 @@
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#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_FATAL_H
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#define __ARCH_ARM64_SRC_COMMON_ARM64_FATAL_H
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/* Fatal error APIs */
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#define K_ERR_CPU_EXCEPTION (0)
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#define K_ERR_CPU_MODE32 (1)
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#define K_ERR_SPURIOUS_IRQ (2)
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#ifndef __ASSEMBLY__
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/****************************************************************************
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@@ -37,123 +43,6 @@
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* Pre-processor Definitions
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****************************************************************************/
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#define ESR_ELX_EC_UNKNOWN (0x00)
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#define ESR_ELX_EC_WFX (0x01)
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/* Unallocated EC: 0x02 */
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#define ESR_ELX_EC_CP15_32 (0x03)
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#define ESR_ELX_EC_CP15_64 (0x04)
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#define ESR_ELX_EC_CP14_MR (0x05)
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#define ESR_ELX_EC_CP14_LS (0x06)
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#define ESR_ELX_EC_FP_ASIMD (0x07)
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#define ESR_ELX_EC_CP10_ID (0x08) /* EL2 only */
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#define ESR_ELX_EC_PAC (0x09) /* EL2 and above */
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/* Unallocated EC: 0x0A - 0x0B */
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#define ESR_ELX_EC_CP14_64 (0x0C)
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#define ESR_ELX_EC_BTI (0x0D)
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#define ESR_ELX_EC_ILL (0x0E)
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/* Unallocated EC: 0x0F - 0x10 */
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#define ESR_ELX_EC_SVC32 (0x11)
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#define ESR_ELX_EC_HVC32 (0x12) /* EL2 only */
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#define ESR_ELX_EC_SMC32 (0x13) /* EL2 and above */
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/* Unallocated EC: 0x14 */
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#define ESR_ELX_EC_SVC64 (0x15)
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#define ESR_ELX_EC_HVC64 (0x16) /* EL2 and above */
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#define ESR_ELX_EC_SMC64 (0x17) /* EL2 and above */
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#define ESR_ELX_EC_SYS64 (0x18)
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#define ESR_ELX_EC_SVE (0x19)
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#define ESR_ELX_EC_ERET (0x1a) /* EL2 only */
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/* Unallocated EC: 0x1B */
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#define ESR_ELX_EC_FPAC (0x1C) /* EL1 and above */
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#define ESR_ELX_EC_SME (0x1D)
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/* Unallocated EC: 0x1D - 0x1E */
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#define ESR_ELX_EC_IMP_DEF (0x1f) /* EL3 only */
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#define ESR_ELX_EC_IABT_LOW (0x20)
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#define ESR_ELX_EC_IABT_CUR (0x21)
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#define ESR_ELX_EC_PC_ALIGN (0x22)
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/* Unallocated EC: 0x23 */
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#define ESR_ELX_EC_DABT_LOW (0x24)
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#define ESR_ELX_EC_DABT_CUR (0x25)
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#define ESR_ELX_EC_SP_ALIGN (0x26)
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#define ESR_ELX_EC_MOPS (0x27)
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#define ESR_ELX_EC_FP_EXC32 (0x28)
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/* Unallocated EC: 0x29 - 0x2B */
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#define ESR_ELX_EC_FP_EXC64 (0x2C)
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/* Unallocated EC: 0x2D - 0x2E */
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#define ESR_ELX_EC_SERROR (0x2F)
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#define ESR_ELX_EC_BREAKPT_LOW (0x30)
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#define ESR_ELX_EC_BREAKPT_CUR (0x31)
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#define ESR_ELX_EC_SOFTSTP_LOW (0x32)
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#define ESR_ELX_EC_SOFTSTP_CUR (0x33)
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#define ESR_ELX_EC_WATCHPT_LOW (0x34)
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#define ESR_ELX_EC_WATCHPT_CUR (0x35)
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/* Unallocated EC: 0x36 - 0x37 */
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#define ESR_ELX_EC_BKPT32 (0x38)
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/* Unallocated EC: 0x39 */
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#define ESR_ELX_EC_VECTOR32 (0x3A) /* EL2 only */
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/* Unallocated EC: 0x3B */
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#define ESR_ELX_EC_BRK64 (0x3C)
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/* Unallocated EC: 0x3D - 0x3F */
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#define ESR_ELX_EC_MAX (0x3F)
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#define ESR_ELX_EC_SHIFT (26)
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#define ESR_ELX_EC_WIDTH (6)
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#define ESR_ELX_EC_MASK (0x3F << ESR_ELX_EC_SHIFT)
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#define ESR_ELX_EC(esr) (((esr) & ESR_ELX_EC_MASK) \
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>> ESR_ELX_EC_SHIFT)
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/* Shared ISS fault status code(IFSC/DFSC) for Data/Instruction aborts */
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#define ESR_ELX_FSC (0x3F)
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#define ESR_ELX_FSC_TYPE (0x3C)
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#define ESR_ELX_FSC_LEVEL (0x03)
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#define ESR_ELX_FSC_EXTABT (0x10)
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#define ESR_ELX_FSC_MTE (0x11)
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#define ESR_ELX_FSC_SERROR (0x11)
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#define ESR_ELX_FSC_ACCESS (0x08)
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#define ESR_ELX_FSC_FAULT (0x04)
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#define ESR_ELX_FSC_PERM (0x0C)
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#define ESR_ELX_FSC_SEA_TTW0 (0x14)
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#define ESR_ELX_FSC_SEA_TTW1 (0x15)
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#define ESR_ELX_FSC_SEA_TTW2 (0x16)
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#define ESR_ELX_FSC_SEA_TTW3 (0x17)
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#define ESR_ELX_FSC_SECC (0x18)
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#define ESR_ELX_FSC_SECC_TTW0 (0x1c)
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#define ESR_ELX_FSC_SECC_TTW1 (0x1d)
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#define ESR_ELX_FSC_SECC_TTW2 (0x1e)
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#define ESR_ELX_FSC_SECC_TTW3 (0x1f)
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#define DBG_ESR_EVT(x) (((x) >> 27) & 0x7)
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#define DBG_ESR_EVT_HWBP (0x0)
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#define DBG_ESR_EVT_HWSS (0x1)
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#define DBG_ESR_EVT_HWWP (0x2)
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#define DBG_ESR_EVT_BRK (0x6)
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#define __builtin_unreachable() \
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do \
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{ \
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@@ -162,49 +51,28 @@
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} while (true)
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/****************************************************************************
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* Public Type Declarations
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* Public Data
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****************************************************************************/
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typedef int (*fatal_handle_func_t)(struct regs_context *regs,
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uint64_t far, uint64_t esr);
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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/****************************************************************************
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* Name: arm64_fatal_handler
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* Name: arm64_fatal_error
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*
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* Description:
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* Fatal handle for arm64
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* fatal error handle for arm64
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* Input Parameters:
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* reason: error reason
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* reg: exception stack reg context
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*
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* Returned Value: None
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* If the function return, the exception has been handled
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* Returned Value:
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*
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****************************************************************************/
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void arm64_fatal_handler(struct regs_context *reg);
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/****************************************************************************
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* Name: arm64_register_debug_hook
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*
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* Description:
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* Register a hook function for DEBUG event
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* Input Parameters:
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* nr: DEBUG event
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* DBG_ESR_EVT_HWBP : Hardware BreakPoint
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* DBG_ESR_EVT_HWSS : Hardware SingleStep
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* DBG_ESR_EVT_HWWP : Hardware WatchPoint
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* DBG_ESR_EVT_BRK : Brk instruction trigger
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* fn: hook function
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*
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* Returned Value: none
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*
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****************************************************************************/
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void arm64_register_debug_hook(int nr, fatal_handle_func_t fn);
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void arm64_fatal_error(unsigned int reason, struct regs_context * reg);
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void arm64_dump_fatal(struct regs_context * reg);
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#endif /* __ASSEMBLY__ */
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@@ -216,25 +216,25 @@ SECTION_SUBSEC_FUNC(exc_vector_table,_vector_table_section,_vector_table)
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.align 7
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arm64_enter_exception x0, x1
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b arm64_mode32_handler
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b arm64_mode32_error
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/* Lower EL using AArch32 / IRQ */
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.align 7
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arm64_enter_exception x0, x1
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b arm64_mode32_handler
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b arm64_mode32_error
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/* Lower EL using AArch32 / FIQ */
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.align 7
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arm64_enter_exception x0, x1
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b arm64_mode32_handler
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b arm64_mode32_error
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/* Lower EL using AArch32 / SError */
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.align 7
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arm64_enter_exception x0, x1
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b arm64_mode32_handler
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b arm64_mode32_error
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/* Restore Corruptible Registers and exception context
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* from the task stack.
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@@ -355,13 +355,16 @@ save_context:
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b arm64_exit_exception
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exc_handle:
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mov x0, sp
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arm64_exception_context_save x0 x1 sp
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mov x0, #K_ERR_CPU_EXCEPTION
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mov x1, sp
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/* void arm64_fatal_handler(struct regs_context * reg);
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* x0 = Exception stack frame
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/* void arm64_fatal_error(unsigned int reason, const uint64_t *regs)
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* x0 = reason
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* x1 = Exception stack frame
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*/
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bl arm64_fatal_handler
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bl arm64_fatal_error
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/* Return here only in case of recoverable error */
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@@ -442,20 +445,28 @@ irq_context_switch:
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irq_exit:
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b arm64_exit_exception
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/* TODO: if the arm64_fatal_handler return success, maybe need context switch */
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/* TODO: if the arm64_fatal_error return success, maybe need context switch */
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GTEXT(arm64_serror_handler)
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SECTION_FUNC(text, arm64_serror_handler)
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mov x0, sp
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bl arm64_fatal_handler
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arm64_exception_context_save x0 x1 sp
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mov x0, #K_ERR_CPU_EXCEPTION
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mov x1, sp
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bl arm64_fatal_error
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/* Return here only in case of recoverable error */
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b arm64_exit_exception
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GTEXT(arm64_mode32_handler)
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SECTION_FUNC(text, arm64_mode32_handler)
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mov x0, sp
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bl arm64_fatal_handler
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GTEXT(arm64_mode32_error)
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SECTION_FUNC(text, arm64_mode32_error)
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arm64_exception_context_save x0 x1 sp
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mov x1, sp
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mov x0, #K_ERR_CPU_MODE32
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bl arm64_fatal_error
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/* Return here only in case of recoverable error */
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b arm64_exit_exception
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@@ -463,9 +474,12 @@ SECTION_FUNC(text, arm64_mode32_handler)
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GTEXT(arm64_fiq_handler)
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SECTION_FUNC(text, arm64_fiq_handler)
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#ifndef CONFIG_ARM64_DECODEFIQ
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arm64_exception_context_save x0 x1 sp
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mov x0, sp
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bl arm64_fatal_handler
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mov x1, sp
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mov x0, #K_ERR_SPURIOUS_IRQ /* K_ERR_SPURIOUS_IRQ */
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bl arm64_fatal_error
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/* Return here only in case of recoverable error */
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