mirror of
https://github.com/apache/nuttx.git
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xtensa/esp32s3: Add SPI RAM/PSRAM Support
This commit is contained in:
Alan C. Assis
committed by
Petro Karashchenko
Petro Karashchenko
parent
700e09103a
commit
dc1b6776b9
@@ -298,6 +298,11 @@ config ESP32S3_RUN_IRAM
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menu "ESP32-S3 Peripheral Selection"
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config ESP32S3_SPIRAM
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bool "SPI RAM Support"
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default n
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select ARCH_HAVE_HEAP2
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config ESP32S3_UART
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bool
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default n
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@@ -331,6 +336,119 @@ config ESP32S3_UART2
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select UART2_SERIALDRIVER
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select ARCH_HAVE_SERIAL_TERMIOS
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menu "SPI RAM Config"
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depends on ESP32S3_SPIRAM
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choice ESP32S3_SPIRAM_MODE
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prompt "Mode (QUAD/OCT) of SPI RAM chip"
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default ESP32S3_SPIRAM_MODE_QUAD
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config ESP32S3_SPIRAM_MODE_QUAD
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bool "Quad Mode PSRAM"
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config ESP32S3_SPIRAM_MODE_OCT
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bool "Octal Mode PSRAM"
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endchoice # ESP32S3_SPIRAM_MODE
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config ESP32S3_DEFAULT_PSRAM_CLK_IO
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int "PSRAM CLK pin"
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default 30
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config ESP32S3_DEFAULT_PSRAM_CS_IO
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int "PSRAM CS pin"
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default 26
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choice ESP32S3_SPIRAM_TYPE
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prompt "Type of SPI RAM chip in use"
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default ESP32S3_SPIRAM_TYPE_AUTO
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config ESP32S3_SPIRAM_TYPE_AUTO
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bool "Auto-detect"
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config ESP32S3_SPIRAM_TYPE_ESPPSRAM16
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bool "ESP-PSRAM16 or APS1604"
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config ESP32S3_SPIRAM_TYPE_ESPPSRAM32
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bool "ESP-PSRAM32 or IS25WP032"
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config ESP32S3_SPIRAM_TYPE_ESPPSRAM64
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bool "ESP-PSRAM64, LY68L6400 or APS6408"
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endchoice # ESP32S3_SPIRAM_TYPE
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config ESP32S3_SPIRAM_SIZE
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int
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default -1 if ESP32S3_SPIRAM_TYPE_AUTO
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default 2097152 if ESP32S3_SPIRAM_TYPE_ESPPSRAM16
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default 4194304 if ESP32S3_SPIRAM_TYPE_ESPPSRAM32
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default 8388608 if ESP32S3_SPIRAM_TYPE_ESPPSRAM64
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default 16777216 if ESP32S3_SPIRAM_TYPE_ESPPSRAM128
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default 33554432 if ESP32S3_SPIRAM_TYPE_ESPPSRAM256
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default 0
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config ESP32S3_SPIRAM_FETCH_INSTRUCTIONS
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bool "Cache fetch instructions from SPI RAM"
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default n
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---help---
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If enabled, instruction in flash will be copied into SPIRAM.
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If ESP32S3_SPIRAM_RODATA is also enabled, you can run the instruction
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when erasing or programming the flash.
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config ESP32S3_SPIRAM_RODATA
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bool "Cache load read only data from SPI RAM"
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default n
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---help---
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If enabled, rodata in flash will be copied into SPIRAM.
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If ESP32S3_ESP32S2_SPIRAM_FETCH_INSTRUCTIONS is also enabled,
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you can run the instruction when erasing or programming the
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flash.
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choice ESP32S3_SPIRAM_SPEED
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prompt "Set RAM clock speed"
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default ESP32S3_SPIRAM_SPEED_40M
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---help---
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Select the speed for the SPI RAM chip.
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config ESP32S3_SPIRAM_SPEED_40M
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bool "40MHz clock speed"
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config ESP32S3_SPIRAM_SPEED_80M
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bool "80MHz clock speed"
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config ESP32S3_SPIRAM_SPEED_120M
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bool "120MHz clock speed"
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endchoice # ESP32S3_SPIRAM_SPEED
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config ESP32S3_SPIRAM_SPEED
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int
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default 120 if ESP32S3_SPIRAM_SPEED_120M
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default 80 if ESP32S3_SPIRAM_SPEED_80M
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default 40 if ESP32S3_SPIRAM_SPEED_40M
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config ESP32S3_SPIRAM_BOOT_INIT
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bool "Initialize SPI RAM during startup"
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depends on ESP32S3_SPIRAM
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default y
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---help---
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If this is enabled, the SPI RAM will be enabled during initial
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boot. Unless you have specific requirements, you'll want to leave
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this enabled so memory allocated during boot-up can also be
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placed in SPI RAM.
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config ESP32S3_SPIRAM_IGNORE_NOTFOUND
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bool "Ignore PSRAM when not found"
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default n
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depends on ESP32S3_SPIRAM_BOOT_INIT && !BOOT_SDRAM_DATA
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---help---
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Normally, if psram initialization is enabled during compile time
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but not found at runtime, it is seen as an error making the CPU
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panic. If this is enabled, booting will complete but no PSRAM
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will be available.
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endmenu #SPI RAM Config
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config ESP32S3_TIMER0
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bool "54-bit Timer 0 (Group 0 Timer 0)"
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default n
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@@ -117,3 +117,7 @@ CHIP_CSRCS += esp32s3_spiflash_mtd.c
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endif
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endif
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ifeq ($(CONFIG_ESP32S3_SPIRAM),y)
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CHIP_CSRCS += esp32s3_spiram.c
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CHIP_CSRCS += esp32s3_psram.c
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endif
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,130 @@
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/****************************************************************************
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* arch/xtensa/src/esp32s3/esp32s3_psram.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#ifndef __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_PSRAM_H
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#define __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_PSRAM_H
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#define PSRAM_SIZE_2MB (2 * 1024 * 1024)
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#define PSRAM_SIZE_4MB (4 * 1024 * 1024)
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#define PSRAM_SIZE_8MB (8 * 1024 * 1024)
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#define PSRAM_SIZE_16MB (16 * 1024 * 1024)
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#define PSRAM_SIZE_32MB (32 * 1024 * 1024)
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#define PSRAM_CACHE_S80M 1
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#define PSRAM_CACHE_S40M 2
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#define PSRAM_CACHE_MAX 3
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#define SPIRAM_WRAP_MODE_16B 0
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#define SPIRAM_WRAP_MODE_32B 1
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#define SPIRAM_WRAP_MODE_64B 2
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#define SPIRAM_WRAP_MODE_DISABLE 3
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/* See the TRM, chapter PID/MPU/MMU, header 'External RAM' for the
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* definitions of these modes. Important is that NORMAL works with the app
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* CPU cache disabled, but gives huge cache coherency issues when both app
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* and pro CPU are enabled. LOWHIGH and EVENODD do not have these coherency
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* issues but cannot be used when the app CPU cache is disabled.
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*/
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#define PSRAM_VADDR_MODE_NORMAL 0 /* App and Pro CPU use their own flash
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* cache for external RAM access
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*/
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#define PSRAM_VADDR_MODE_LOWHIGH 1 /* App and Pro CPU share external RAM caches:
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* pro CPU has low 2M, app CPU has high 2M
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*/
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#define PSRAM_VADDR_MODE_EVENODD 2 /* App and Pro CPU share external RAM caches:
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* pro CPU does even 32yte ranges, app does
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* odd ones.
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*/
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/****************************************************************************
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* Public Functions Prototypes
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****************************************************************************/
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/****************************************************************************
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* Name: psram_get_physical_size
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*
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* Description:
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* Get the physical psram size in bytes.
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*
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****************************************************************************/
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int psram_get_physical_size(uint32_t *out_size_bytes);
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/****************************************************************************
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* Name: psram_get_available_size
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*
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* Description:
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* Get the available physical psram size in bytes.
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*
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* If ECC is enabled, available PSRAM size will be 15/16 times its
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* physical size. If not, it equals to the physical psram size.
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* Note: For now ECC is only enabled on ESP32S3 Octal PSRAM
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*
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* Input Parameters:
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* out_size_bytes - availabe physical psram size in bytes.
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*
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* Returned Value:
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* 0 if success or a negative value if fail.
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*
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****************************************************************************/
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int psram_get_available_size(uint32_t *out_size_bytes);
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/****************************************************************************
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* Name: psram_get_available_size
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*
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* Description:
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* Enable psram cache
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*
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* Esp-idf uses this to initialize cache for psram, mapping it into the
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* main memory address space.
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*
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* Input Parameters:
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* mode - SPI mode to access psram in.
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* vaddrmode - Mode the psram cache works in.
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*
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* Returned Value:
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* 0 if success or a negative value if fail.
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*
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****************************************************************************/
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int psram_enable(int mode, int vaddrmode);
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/****************************************************************************
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* Name: psram_get_cs_io
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*
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* Description:
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* Get the psram CS IO
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*
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* Returned Value:
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* The psram CS IO pin.
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*
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****************************************************************************/
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uint8_t psram_get_cs_io(void);
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#endif /* __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_PSRAM_H */
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@@ -0,0 +1,383 @@
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/****************************************************************************
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* arch/xtensa/src/esp32s3/esp32s3_spiram.c
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include <stdbool.h>
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#include <errno.h>
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#include <debug.h>
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#include <string.h>
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#include <sys/param.h>
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#include <nuttx/config.h>
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#include <nuttx/spinlock.h>
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#include "xtensa.h"
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#include "xtensa_attr.h"
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#include "esp32s3_psram.h"
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#include "esp32s3_spiram.h"
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#include "hardware/esp32s3_soc.h"
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#include "hardware/esp32s3_cache_memory.h"
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#include "hardware/esp32s3_extmem.h"
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#include "hardware/esp32s3_iomux.h"
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#define PSRAM_MODE PSRAM_VADDR_MODE_NORMAL
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#if defined(CONFIG_ESP32S3_SPIRAM)
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#if defined(CONFIG_ESP32S3_SPIRAM_SPEED_40M)
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# define PSRAM_SPEED PSRAM_CACHE_S40M
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#else /* #if CONFIG_ESP32S3_SPIRAM_SPEED_80M */
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# define PSRAM_SPEED PSRAM_CACHE_S80M
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#endif
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static bool g_spiram_inited;
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/* These variables are in bytes */
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static uint32_t g_allocable_vaddr_start;
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static uint32_t g_allocable_vaddr_end;
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static DRAM_ATTR uint32_t g_mapped_vaddr_start;
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/* Let's export g_mapped_size to export heap */
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DRAM_ATTR uint32_t g_mapped_size;
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static uint32_t g_instruction_in_spiram;
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static uint32_t g_rodata_in_spiram;
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#if defined(CONFIG_ESP32S3_SPIRAM_FETCH_INSTRUCTIONS)
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static int g_instr_flash2spiram_offs;
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static uint32_t g_instr_start_page;
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static uint32_t g_instr_end_page;
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#endif
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#if defined(CONFIG_ESP32S3_SPIRAM_RODATA)
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static int g_rodata_flash2spiram_offs;
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static uint32_t g_rodata_start_page;
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static uint32_t g_rodata_end_page;
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#endif
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#if defined(CONFIG_ESP32S3_SPIRAM_FETCH_INSTRUCTIONS) || \
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defined(CONFIG_ES32S3_SPIRAM_RODATA)
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static uint32_t page0_mapped;
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static uint32_t page0_page = INVALID_PHY_PAGE;
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#endif
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/****************************************************************************
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* ROM Function Prototypes
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****************************************************************************/
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extern void cache_writeback_all(void);
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extern uint32_t cache_suspend_dcache(void);
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extern void cache_resume_dcache(uint32_t val);
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extern int cache_dbus_mmu_set(uint32_t ext_ram, uint32_t vaddr,
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uint32_t paddr, uint32_t psize,
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uint32_t num, uint32_t fixed);
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/* Initially map all psram physical address to virtual address.
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* If psram physical size is larger than virtual address range, then only
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* map the virtual address range.
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*/
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void IRAM_ATTR esp_spiram_init_cache(void)
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{
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uint32_t regval;
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int ret = psram_get_available_size(&g_mapped_size);
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if (ret != OK)
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{
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abort();
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}
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merr("Mapped size = %d\n", g_mapped_size);
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if ((SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW) < g_mapped_size)
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{
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/* Decide these logics when there's a real PSRAM with larger size */
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merr("Virtual address not enough for PSRAM!");
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abort();
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}
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g_mapped_vaddr_start = SOC_EXTRAM_DATA_HIGH - g_mapped_size;
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/* Suspend DRAM Case during configuration */
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cache_suspend_dcache();
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cache_dbus_mmu_set(MMU_ACCESS_SPIRAM, g_mapped_vaddr_start,
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0, 64, g_mapped_size >> 16, 0);
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regval = getreg32(EXTMEM_DCACHE_CTRL1_REG);
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regval &= ~EXTMEM_DCACHE_SHUT_CORE0_BUS;
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putreg32(regval, EXTMEM_DCACHE_CTRL1_REG);
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#if defined(CONFIG_SMP)
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regval = getreg32(EXTMEM_DCACHE_CTRL1_REG);
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regval &= ~EXTMEM_DCACHE_SHUT_CORE1_BUS;
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putreg32(regval, EXTMEM_DCACHE_CTRL1_REG);
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#endif
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cache_resume_dcache(0);
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/* Currently no non-heap stuff on ESP32S3 */
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g_allocable_vaddr_start = g_mapped_vaddr_start;
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g_allocable_vaddr_end = SOC_EXTRAM_DATA_HIGH;
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}
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/* Simple RAM test. Writes a word every 32 bytes. Takes about a second
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* to complete for 4MiB. Returns true when RAM seems OK, false when test
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* fails. WARNING: Do not run this before the 2nd cpu has been initialized
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* (in a two-core system) or after the heap allocator has taken ownership
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* of the memory.
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*/
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bool esp_spiram_test(void)
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{
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volatile int *spiram = (volatile int *)g_mapped_vaddr_start;
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size_t s = g_mapped_size;
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size_t p;
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int errct = 0;
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int initial_err = -1;
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for (p = 0; p < (s / sizeof(int)); p += 8)
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{
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spiram[p] = p ^ 0xaaaaaaaa;
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}
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for (p = 0; p < (s / sizeof(int)); p += 8)
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{
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if (spiram[p] != (p ^ 0xaaaaaaaa))
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{
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errct++;
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if (errct == 1)
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{
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initial_err = p * sizeof(int);
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}
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if (errct < 4)
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{
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merr("SPI SRAM error@%08x:%08x/%08x \n", &spiram[p], spiram[p],
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p ^ 0xaaaaaaaa);
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}
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}
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}
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if (errct != 0)
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{
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merr("SPI SRAM memory test fail. %d/%d writes failed, first @ %X\n",
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errct, s / 32, initial_err + SOC_EXTRAM_DATA_LOW);
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return false;
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}
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else
|
||||
{
|
||||
minfo("SPI SRAM memory test OK!");
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
uint32_t esp_spiram_instruction_access_enabled(void)
|
||||
{
|
||||
return g_instruction_in_spiram;
|
||||
}
|
||||
|
||||
uint32_t esp_spiram_rodata_access_enabled(void)
|
||||
{
|
||||
return g_rodata_in_spiram;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_ESP32S3_SPIRAM_FETCH_INSTRUCTIONS)
|
||||
int esp_spiram_enable_instruction_access(void)
|
||||
{
|
||||
/* `pages_for_flash` will be overwritten, however it influences the psram
|
||||
* size to be added to the heap allocator.
|
||||
*/
|
||||
|
||||
abort();
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ESP32S3_SPIRAM_RODATA)
|
||||
int esp_spiram_enable_rodata_access(void)
|
||||
{
|
||||
/* `pages_for_flash` will be overwritten, however it influences the psram
|
||||
* size to be added to the heap allocator.
|
||||
*/
|
||||
|
||||
abort();
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ESP32S3_SPIRAM_FETCH_INSTRUCTIONS)
|
||||
void instruction_flash_page_info_init(void)
|
||||
{
|
||||
uint32_t instr_page_cnt = ((uint32_t)&_instruction_reserved_end -
|
||||
SOC_IROM_LOW + MMU_PAGE_SIZE - 1) /
|
||||
MMU_PAGE_SIZE;
|
||||
|
||||
g_instr_start_page = *(volatile uint32_t *)(DR_REG_MMU_TABLE +
|
||||
CACHE_IROM_MMU_START);
|
||||
g_instr_start_page &= MMU_ADDRESS_MASK;
|
||||
g_instr_end_page = g_instr_start_page + instr_page_cnt - 1;
|
||||
}
|
||||
|
||||
uint32_t IRAM_ATTR instruction_flash_start_page_get(void)
|
||||
{
|
||||
return g_instr_start_page;
|
||||
}
|
||||
|
||||
uint32_t IRAM_ATTR instruction_flash_end_page_get(void)
|
||||
{
|
||||
return g_instr_end_page;
|
||||
}
|
||||
|
||||
int IRAM_ATTR instruction_flash2spiram_offset(void)
|
||||
{
|
||||
return g_instr_flash2spiram_offs;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ESP32_SPIRAM_RODATA)
|
||||
void rodata_flash_page_info_init(void)
|
||||
{
|
||||
uint32_t rodata_page_cnt = ((uint32_t)&_rodata_reserved_end -
|
||||
((uint32_t)&_rodata_reserved_start &
|
||||
~ (MMU_PAGE_SIZE - 1)) + MMU_PAGE_SIZE - 1) /
|
||||
MMU_PAGE_SIZE;
|
||||
|
||||
g_rodata_start_page = *(volatile uint32_t *)(DR_REG_MMU_TABLE +
|
||||
CACHE_DROM_MMU_START);
|
||||
g_rodata_start_page &= MMU_ADDRESS_MASK;
|
||||
g_rodata_end_page = g_rodata_start_page + rodata_page_cnt - 1;
|
||||
}
|
||||
|
||||
uint32_t IRAM_ATTR rodata_flash_start_page_get(void)
|
||||
{
|
||||
return g_rodata_start_page;
|
||||
}
|
||||
|
||||
uint32_t IRAM_ATTR rodata_flash_end_page_get(void)
|
||||
{
|
||||
return g_rodata_end_page;
|
||||
}
|
||||
|
||||
int IRAM_ATTR g_rodata_flash2spiram_offset(void)
|
||||
{
|
||||
return g_rodata_flash2spiram_offs;
|
||||
}
|
||||
#endif
|
||||
|
||||
int esp_spiram_init(void)
|
||||
{
|
||||
int r;
|
||||
uint32_t psram_physical_size = 0;
|
||||
|
||||
r = psram_enable(PSRAM_SPEED, PSRAM_MODE);
|
||||
if (r != OK)
|
||||
{
|
||||
merr("SPI RAM enabled but initialization failed. Bailing out.\n");
|
||||
return r;
|
||||
}
|
||||
|
||||
g_spiram_inited = true;
|
||||
|
||||
r = psram_get_physical_size(&psram_physical_size);
|
||||
if (r != OK)
|
||||
{
|
||||
abort();
|
||||
}
|
||||
|
||||
#if defined(CONFIG_ESP32S3_SPIRAM_SIZE) && (CONFIG_ESP32S3_SPIRAM_SIZE != -1)
|
||||
if (psram_physical_size != CONFIG_ESP32S3_SPIRAM_SIZE)
|
||||
{
|
||||
merr("Expected %dMB chip but found %dMB chip. Bailing out..",
|
||||
(CONFIG_ESP32S3_SPIRAM_SIZE / 1024 / 1024),
|
||||
(psram_physical_size / 1024 / 1024));
|
||||
return ;
|
||||
}
|
||||
#endif
|
||||
|
||||
minfo("Found %dMB SPI RAM device\n", psram_physical_size / (1024 * 1024));
|
||||
minfo("Speed: %dMHz\n", CONFIG_ESP32S3_SPIRAM_SPEED);
|
||||
minfo("Initialized, cache is in %s mode.\n",
|
||||
(PSRAM_MODE == PSRAM_VADDR_MODE_EVENODD) ?
|
||||
"even/odd (2-core)" :
|
||||
(PSRAM_MODE == PSRAM_VADDR_MODE_LOWHIGH) ?
|
||||
"low/high (2-core)" :
|
||||
(PSRAM_MODE == PSRAM_VADDR_MODE_NORMAL) ?
|
||||
"normal (1-core)" : "ERROR");
|
||||
return OK;
|
||||
}
|
||||
|
||||
size_t esp_spiram_get_size(void)
|
||||
{
|
||||
if (!g_spiram_inited)
|
||||
{
|
||||
merr("SPI RAM not initialized");
|
||||
abort();
|
||||
}
|
||||
|
||||
uint32_t size = 0; /* in bytes */
|
||||
int ret = psram_get_available_size(&size);
|
||||
|
||||
return ret == OK ? size : 0;
|
||||
}
|
||||
|
||||
/* Before flushing the cache, if psram is enabled as a memory-mapped thing,
|
||||
* we need to write back the data in the cache to the psram first, otherwise
|
||||
* it will get lost. For now, we just read 64/128K of random PSRAM memory to
|
||||
* do this.
|
||||
*/
|
||||
|
||||
void IRAM_ATTR esp_spiram_writeback_cache(void)
|
||||
{
|
||||
cache_writeback_all();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief If SPI RAM(PSRAM) has been initialized
|
||||
*
|
||||
* @return true SPI RAM has been initialized successfully
|
||||
* @return false SPI RAM hasn't been initialized or initialized failed
|
||||
*/
|
||||
|
||||
bool esp_spiram_is_initialized(void)
|
||||
{
|
||||
return g_spiram_inited;
|
||||
}
|
||||
|
||||
uint8_t esp_spiram_get_cs_io(void)
|
||||
{
|
||||
return psram_get_cs_io();
|
||||
}
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,206 @@
|
||||
/****************************************************************************
|
||||
* arch/xtensa/src/esp32s3/esp32s3_spiram.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_SPIRAM_H
|
||||
#define __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_SPIRAM_H
|
||||
|
||||
#include <stddef.h>
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/* @brief Initialize spiram interface/hardware. Normally called from
|
||||
* cpu_start.c.
|
||||
*
|
||||
* @return ESP_OK on success
|
||||
*/
|
||||
|
||||
int esp_spiram_init(void);
|
||||
|
||||
/**
|
||||
* @brief Configure Cache/MMU for access to external SPI RAM.
|
||||
*
|
||||
* Normally this function is called from cpu_start, if
|
||||
* CONFIG_SPIRAM_BOOT_INIT option is enabled. Applications which need to
|
||||
* enable SPI RAM at run time can disable CONFIG_SPIRAM_BOOT_INIT, and
|
||||
* call this function later.
|
||||
*
|
||||
* @attention this function must be called with flash cache disabled.
|
||||
*/
|
||||
|
||||
void esp_spiram_init_cache(void);
|
||||
|
||||
/**
|
||||
* @brief Memory test for SPI RAM. Should be called after SPI RAM is
|
||||
* initialized and (in case of a dual-core system) the app CPU is online.
|
||||
* This test overwrites the memory with crap, so do not call after e.g. the
|
||||
* heap allocator has stored important stuff in SPI RAM.
|
||||
*
|
||||
* @return true on success, false on failed memory test
|
||||
*/
|
||||
|
||||
bool esp_spiram_test(void);
|
||||
|
||||
/**
|
||||
* @brief Add the initialized SPI RAM to the heap allocator.
|
||||
*/
|
||||
|
||||
int esp_spiram_add_to_heapalloc(void);
|
||||
|
||||
/**
|
||||
* @brief Get the available physical size of the attached SPI RAM chip
|
||||
*
|
||||
* @note If ECC is enabled, the available physical size would be smaller
|
||||
* than the physical size. See `CONFIG_SPIRAM_ECC_ENABLE`
|
||||
*
|
||||
* @return Size in bytes, or 0 if no external RAM chip support compiled in.
|
||||
*/
|
||||
|
||||
size_t esp_spiram_get_size(void);
|
||||
|
||||
/**
|
||||
* @brief Force a writeback of the data in the SPI RAM cache. This is to be
|
||||
* called whenever cache is disabled, because disabling cache on the ESP32
|
||||
* discards the data in the SPI RAM cache.
|
||||
*
|
||||
* This is meant for use from within the SPI flash code.
|
||||
*/
|
||||
|
||||
void esp_spiram_writeback_cache(void);
|
||||
|
||||
/**
|
||||
* @brief If SPI RAM(PSRAM) has been initialized
|
||||
*
|
||||
* @return
|
||||
* - true SPI RAM has been initialized successfully
|
||||
* - false SPI RAM hasn't been initialized or initialized failed
|
||||
*/
|
||||
|
||||
bool esp_spiram_is_initialized(void);
|
||||
|
||||
/**
|
||||
* @brief get psram CS IO
|
||||
*
|
||||
* This interface should be called after PSRAM is enabled, otherwise it will
|
||||
* return an invalid value -1/0xff.
|
||||
*
|
||||
* @return psram CS IO or -1/0xff if psram not enabled
|
||||
*/
|
||||
|
||||
uint8_t esp_spiram_get_cs_io(void);
|
||||
|
||||
/**
|
||||
* @brief Reserve a pool of internal memory for specific DMA/internal
|
||||
* allocations
|
||||
*
|
||||
* @param size Size of reserved pool in bytes
|
||||
*
|
||||
* @return
|
||||
* - ESP_OK on success
|
||||
* - ESP_ERR_NO_MEM when no memory available for pool
|
||||
*/
|
||||
|
||||
int esp_spiram_reserve_dma_pool(size_t size);
|
||||
|
||||
/**
|
||||
* @brief If SPI RAM(PSRAM) has been initialized
|
||||
*
|
||||
* @return
|
||||
* - true SPI RAM has been initialized successfully
|
||||
* - false SPI RAM hasn't been initialized or initialized failed
|
||||
*/
|
||||
|
||||
bool esp_spiram_is_initialized(void);
|
||||
|
||||
#if defined(CONFIG_ESP32S3_SPIRAM_FETCH_INSTRUCTIONS)
|
||||
|
||||
extern int _instruction_reserved_start;
|
||||
extern int _instruction_reserved_end;
|
||||
|
||||
/**
|
||||
* @brief Get the start page number of the instruction in SPI flash
|
||||
*
|
||||
* @return start page number
|
||||
*/
|
||||
|
||||
uint32_t instruction_flash_start_page_get(void);
|
||||
|
||||
/**
|
||||
* @brief Get the end page number of the instruction in SPI flash
|
||||
*
|
||||
* @return end page number
|
||||
*/
|
||||
|
||||
uint32_t instruction_flash_end_page_get(void);
|
||||
|
||||
/**
|
||||
* @brief Get the offset of instruction from SPI flash to SPI RAM
|
||||
*
|
||||
* @return instruction offset
|
||||
*/
|
||||
|
||||
int instruction_flash2spiram_offset(void);
|
||||
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SPIRAM_RODATA)
|
||||
|
||||
extern int _rodata_reserved_start;
|
||||
extern int _rodata_reserved_end;
|
||||
|
||||
/**
|
||||
* @brief Get the start page number of the rodata in SPI flash
|
||||
*
|
||||
* @return start page number
|
||||
*/
|
||||
|
||||
uint32_t rodata_flash_start_page_get(void);
|
||||
|
||||
/**
|
||||
* @brief Get the end page number of the rodata in SPI flash
|
||||
*
|
||||
* @return end page number
|
||||
*/
|
||||
|
||||
uint32_t rodata_flash_end_page_get(void);
|
||||
|
||||
/**
|
||||
* @brief Get the offset number of rodata from SPI flash to SPI RAM
|
||||
*
|
||||
* @return rodata offset
|
||||
*/
|
||||
|
||||
int rodata_flash2spiram_offset(void);
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -37,6 +37,7 @@
|
||||
#include "esp32s3_lowputc.h"
|
||||
#include "esp32s3_clockconfig.h"
|
||||
#include "esp32s3_region.h"
|
||||
#include "esp32s3_spiram.h"
|
||||
#include "esp32s3_wdt.h"
|
||||
#include "hardware/esp32s3_cache_memory.h"
|
||||
#include "hardware/esp32s3_system.h"
|
||||
@@ -285,6 +286,22 @@ void noreturn_function IRAM_ATTR __esp32s3_start(void)
|
||||
|
||||
showprogress('A');
|
||||
|
||||
#if defined(CONFIG_ESP32S3_SPIRAM_BOOT_INIT)
|
||||
if (esp_spiram_init() != OK)
|
||||
{
|
||||
# if defined(ESP32S3_SPIRAM_IGNORE_NOTFOUND)
|
||||
mwarn("SPIRAM Initialization failed!\n");
|
||||
# else
|
||||
PANIC();
|
||||
# endif
|
||||
}
|
||||
else
|
||||
{
|
||||
esp_spiram_init_cache();
|
||||
esp_spiram_test();
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Initialize onboard resources */
|
||||
|
||||
esp32s3_board_initialize();
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,378 @@
|
||||
/*****************************************************************************
|
||||
* arch/xtensa/src/esp32s3/rom/esp32s3_opi_flash.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_XTENSA_SRC_ESP32S3_ROM_ESP32S3_OPI_FLASH_H
|
||||
#define __ARCH_XTENSA_SRC_ESP32S3_ROM_ESP32S3_OPI_FLASH_H
|
||||
|
||||
/*****************************************************************************
|
||||
* Included Files
|
||||
*****************************************************************************/
|
||||
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint8_t mode;
|
||||
uint8_t cmd_bit_len;
|
||||
uint16_t cmd;
|
||||
uint32_t addr;
|
||||
uint8_t addr_bit_len;
|
||||
uint8_t dummy_bit_len;
|
||||
uint8_t data_bit_len;
|
||||
uint8_t cs_sel: 4;
|
||||
uint8_t is_pe: 4;
|
||||
} esp_rom_opiflash_cmd_t;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint8_t addr_bit_len;
|
||||
uint8_t dummy_bit_len;
|
||||
uint16_t cmd;
|
||||
uint8_t cmd_bit_len;
|
||||
uint8_t var_dummy_en;
|
||||
} esp_rom_opiflash_spi0rd_t;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
esp_rom_opiflash_cmd_t rdid;
|
||||
esp_rom_opiflash_cmd_t rdsr;
|
||||
esp_rom_opiflash_cmd_t wren;
|
||||
esp_rom_opiflash_cmd_t se;
|
||||
esp_rom_opiflash_cmd_t be64k;
|
||||
esp_rom_opiflash_cmd_t read;
|
||||
esp_rom_opiflash_cmd_t pp;
|
||||
esp_rom_opiflash_spi0rd_t cache_rd_cmd;
|
||||
} esp_rom_opiflash_def_t;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint16_t cmd; /* !< Command value */
|
||||
uint16_t cmd_bit_len; /* !< Command byte length */
|
||||
uint32_t *addr; /* !< Point to address value */
|
||||
uint32_t addr_bit_len; /* !< Address byte length */
|
||||
uint32_t *tx_data; /* !< Point to send data buffer */
|
||||
uint32_t tx_data_bit_len; /* !< Send data byte length. */
|
||||
uint32_t *rx_data; /* !< Point to recevie data buffer */
|
||||
uint32_t rx_data_bit_len; /* !< Recevie Data byte length. */
|
||||
uint32_t dummy_bit_len;
|
||||
} esp_rom_spi_cmd_t;
|
||||
|
||||
#define ESP_ROM_OPIFLASH_MUX_TAKE()
|
||||
#define ESP_ROM_OPIFLASH_MUX_GIVE()
|
||||
#define ESP_ROM_OPIFLASH_SEL_CS0 (BIT(0))
|
||||
#define ESP_ROM_OPIFLASH_SEL_CS1 (BIT(1))
|
||||
|
||||
/* Definition of MX25UM25645G Octa Flash
|
||||
* SPI status register
|
||||
*/
|
||||
|
||||
#define ESP_ROM_SPIFLASH_BUSY_FLAG BIT0
|
||||
#define ESP_ROM_SPIFLASH_WRENABLE_FLAG BIT1
|
||||
#define ESP_ROM_SPIFLASH_BP0 BIT2
|
||||
#define ESP_ROM_SPIFLASH_BP1 BIT3
|
||||
#define ESP_ROM_SPIFLASH_BP2 BIT4
|
||||
#define ESP_ROM_SPIFLASH_WR_PROTECT (ESP_ROM_SPIFLASH_BP0 | ESP_ROM_SPIFLASH_BP1 | ESP_ROM_SPIFLASH_BP2)
|
||||
#define ESP_ROM_SPIFLASH_QE BIT9
|
||||
|
||||
#define FLASH_OP_MODE_RDCMD_DOUT 0x3B
|
||||
#define ESP_ROM_FLASH_SECTOR_SIZE 0x1000
|
||||
#define ESP_ROM_FLASH_BLOCK_SIZE_64K 0x10000
|
||||
#define ESP_ROM_FLASH_PAGE_SIZE 256
|
||||
|
||||
/* FLASH commands */
|
||||
|
||||
#define ROM_FLASH_CMD_RDID 0x9F
|
||||
#define ROM_FLASH_CMD_WRSR 0x01
|
||||
#define ROM_FLASH_CMD_WRSR2 0x31 /* Not all SPI flash uses this command */
|
||||
#define ROM_FLASH_CMD_WREN 0x06
|
||||
#define ROM_FLASH_CMD_WRDI 0x04
|
||||
#define ROM_FLASH_CMD_RDSR 0x05
|
||||
#define ROM_FLASH_CMD_RDSR2 0x35 /* Not all SPI flash uses this command */
|
||||
#define ROM_FLASH_CMD_ERASE_SEC 0x20
|
||||
#define ROM_FLASH_CMD_ERASE_BLK_32K 0x52
|
||||
#define ROM_FLASH_CMD_ERASE_BLK_64K 0xD8
|
||||
#define ROM_FLASH_CMD_OTPEN 0x3A /* Enable OTP mode, not all SPI flash uses this command */
|
||||
#define ROM_FLASH_CMD_RSTEN 0x66
|
||||
#define ROM_FLASH_CMD_RST 0x99
|
||||
|
||||
#define ROM_FLASH_CMD_SE4B 0x21
|
||||
#define ROM_FLASH_CMD_SE4B_OCT 0xDE21
|
||||
#define ROM_FLASH_CMD_BE4B 0xDC
|
||||
#define ROM_FLASH_CMD_BE4B_OCT 0x23DC
|
||||
#define ROM_FLASH_CMD_RSTEN_OCT 0x9966
|
||||
#define ROM_FLASH_CMD_RST_OCT 0x6699
|
||||
|
||||
#define ROM_FLASH_CMD_FSTRD4B_STR 0x13EC
|
||||
#define ROM_FLASH_CMD_FSTRD4B_DTR 0x11EE
|
||||
#define ROM_FLASH_CMD_FSTRD4B 0x0C
|
||||
#define ROM_FLASH_CMD_PP4B 0x12
|
||||
#define ROM_FLASH_CMD_PP4B_OCT 0xED12
|
||||
|
||||
#define ROM_FLASH_CMD_RDID_OCT 0x609F
|
||||
#define ROM_FLASH_CMD_WREN_OCT 0xF906
|
||||
#define ROM_FLASH_CMD_RDSR_OCT 0xFA05
|
||||
#define ROM_FLASH_CMD_RDCR2 0x71
|
||||
#define ROM_FLASH_CMD_RDCR2_OCT 0x8E71
|
||||
#define ROM_FLASH_CMD_WRCR2 0x72
|
||||
#define ROM_FLASH_CMD_WRCR2_OCT 0x8D72
|
||||
|
||||
/* Definitions for GigaDevice GD25LX256E Flash */
|
||||
|
||||
#define ROM_FLASH_CMD_RDFSR_GD 0x70
|
||||
#define ROM_FLASH_CMD_RD_GD 0x03
|
||||
#define ROM_FLASH_CMD_RD4B_GD 0x13
|
||||
#define ROM_FLASH_CMD_FSTRD_GD 0x0B
|
||||
#define ROM_FLASH_CMD_FSTRD4B_GD 0x0C
|
||||
#define ROM_FLASH_CMD_FSTRD_OOUT_GD 0x8B
|
||||
#define ROM_FLASH_CMD_FSTRD4B_OOUT_GD 0x7C
|
||||
#define ROM_FLASH_CMD_FSTRD_OIOSTR_GD 0xCB
|
||||
#define ROM_FLASH_CMD_FSTRD4B_OIOSTR_GD 0xCC
|
||||
#define ROM_FLASH_CMD_FSTRD4B_OIODTR_GD 0xFD
|
||||
|
||||
#define ROM_FLASH_CMD_PP_GD 0x02
|
||||
#define ROM_FLASH_CMD_PP4B_GD 0x12
|
||||
#define ROM_FLASH_CMD_PP_OOUT_GD 0x82
|
||||
#define ROM_FLASH_CMD_PP4B_OOUT_GD 0x84
|
||||
#define ROM_FLASH_CMD_PP_OIO_GD 0xC2
|
||||
#define ROM_FLASH_CMD_PP4B_OIOSTR_GD 0x8E
|
||||
|
||||
#define ROM_FLASH_CMD_SE_GD 0x20
|
||||
#define ROM_FLASH_CMD_SE4B_GD 0x21
|
||||
#define ROM_FLASH_CMD_BE32K_GD 0x52
|
||||
#define ROM_FLASH_CMD_BE32K4B_GD 0x5C
|
||||
#define ROM_FLASH_CMD_BE64K_GD 0xD8
|
||||
#define ROM_FLASH_CMD_BE64K4B_GD 0xDC
|
||||
|
||||
#define ROM_FLASH_CMD_EN4B_GD 0xB7
|
||||
#define ROM_FLASH_CMD_DIS4B_GD 0xE9
|
||||
|
||||
extern const esp_rom_opiflash_def_t *rom_opiflash_cmd_def;
|
||||
|
||||
/**
|
||||
* @brief init legacy driver for Octal Flash
|
||||
*/
|
||||
|
||||
void esp_rom_opiflash_legacy_driver_init(const esp_rom_opiflash_def_t
|
||||
*flash_cmd_def);
|
||||
|
||||
/**
|
||||
* @brief Config the spi user command
|
||||
* @param spi_num spi port
|
||||
* @param pcmd pointer to accept the spi command struct
|
||||
*/
|
||||
|
||||
void esp_rom_spi_cmd_config(int spi_num, esp_rom_spi_cmd_t *pcmd);
|
||||
|
||||
/**
|
||||
* @brief Start a spi user command sequence
|
||||
* @param spi_num spi port
|
||||
* @param rx_buf buffer pointer to receive data
|
||||
* @param rx_len receive data length in byte
|
||||
* @param cs_en_mask decide which cs to use, 0 for cs0, 1 for cs1
|
||||
* @param is_write_erase to indicate whether this is a write or erase
|
||||
* operation, since the CPU would check permission
|
||||
*/
|
||||
|
||||
void esp_rom_spi_cmd_start(int spi_num, uint8_t *rx_buf, uint16_t rx_len,
|
||||
uint8_t cs_en_mask, bool is_write_erase);
|
||||
|
||||
/**
|
||||
* @brief Config opi flash pads according to efuse settings.
|
||||
*/
|
||||
|
||||
void esp_rom_opiflash_pin_config(void);
|
||||
|
||||
/**
|
||||
* @brief Set SPI read/write operation mode
|
||||
* @param spi_num spi port
|
||||
* @param mode Flash Read Mode
|
||||
*/
|
||||
|
||||
void esp_rom_spi_set_op_mode(int spi_num, esp_rom_spiflash_read_mode_t mode);
|
||||
|
||||
/**
|
||||
* @brief Set data swap mode in DTR(DDR) mode
|
||||
* @param spi_num spi port
|
||||
* @param wr_swap to decide whether to swap fifo data in dtr write operation
|
||||
* @param rd_swap to decide whether to swap fifo data in dtr read operation
|
||||
*/
|
||||
|
||||
void esp_rom_spi_set_dtr_swap_mode(int spi, bool wr_swap, bool rd_swap);
|
||||
|
||||
/**
|
||||
* @brief to send reset command in spi/opi-str/opi-dtr mode(for MX25UM25645G)
|
||||
* @param spi_num spi port
|
||||
*/
|
||||
|
||||
void esp_rom_opiflash_mode_reset(int spi_num);
|
||||
|
||||
/**
|
||||
* @brief To execute a flash operation command
|
||||
* @param spi_num spi port
|
||||
* @param mode Flash Read Mode
|
||||
* @param cmd data to send in command field
|
||||
* @param cmd_bit_len bit length of command field
|
||||
* @param addr data to send in address field
|
||||
* @param addr_bit_len bit length of address field
|
||||
* @param dummy_bits bit length of dummy field
|
||||
* @param mosi_data data buffer to be sent in mosi field
|
||||
* @param mosi_bit_len bit length of data buffer to be sent in mosi field
|
||||
* @param miso_data data buffer to accept data in miso field
|
||||
* @param miso_bit_len bit length of data buffer to accept data in miso field
|
||||
* @param cs_mark decide which cs pin to use. 0: cs0, 1: cs1
|
||||
* @param is_write_erase_operation to indicate whether this a write or erase
|
||||
* flash operation
|
||||
*/
|
||||
|
||||
void esp_rom_opiflash_exec_cmd(int spi_num, esp_rom_spiflash_read_mode_t mode,
|
||||
uint32_t cmd, int cmd_bit_len,
|
||||
uint32_t addr, int addr_bit_len,
|
||||
int dummy_bits,
|
||||
uint8_t *mosi_data, int mosi_bit_len,
|
||||
uint8_t *miso_data, int miso_bit_len,
|
||||
uint32_t cs_mask,
|
||||
bool is_write_erase_operation);
|
||||
|
||||
/**
|
||||
* @brief send reset command to opi flash
|
||||
* @param spi_num spi port
|
||||
* @param mode Flash Operation Mode
|
||||
*/
|
||||
|
||||
void esp_rom_opiflash_soft_reset(int spi_num,
|
||||
esp_rom_spiflash_read_mode_t mode);
|
||||
|
||||
/**
|
||||
* @brief to read opi flash ID
|
||||
* @note command format would be defined in initialization
|
||||
* @param[out] out_id buffer to accept id
|
||||
* @return flash operation result
|
||||
*/
|
||||
|
||||
esp_rom_spiflash_result_t esp_rom_opiflash_read_id(uint8_t *out_id);
|
||||
|
||||
/**
|
||||
* @brief to read opi flash status register
|
||||
* @note command format would be defined in initialization
|
||||
* @return opi flash status value
|
||||
*/
|
||||
|
||||
uint8_t esp_rom_opiflash_rdsr(void);
|
||||
|
||||
/**
|
||||
* @brief wait opi flash status register to be idle
|
||||
* @note command format would be defined in initialization
|
||||
* @return flash operation result
|
||||
*/
|
||||
|
||||
esp_rom_spiflash_result_t esp_rom_opiflash_wait_idle(void);
|
||||
|
||||
/**
|
||||
* @brief to erase flash sector
|
||||
* @note command format would be defined in initialization
|
||||
* @param sector_num the sector to be erased
|
||||
* @return flash operation result
|
||||
*/
|
||||
|
||||
esp_rom_spiflash_result_t
|
||||
esp_rom_opiflash_erase_sector(uint32_t sector_num);
|
||||
|
||||
/**
|
||||
* @brief to erase flash block
|
||||
* @note command format would be defined in initialization
|
||||
* @param block_num the block to be erased
|
||||
* @return flash operation result
|
||||
*/
|
||||
|
||||
esp_rom_spiflash_result_t
|
||||
esp_rom_opiflash_erase_block_64k(uint32_t block_num);
|
||||
|
||||
/**
|
||||
* @brief to erase a flash area define by start address and length
|
||||
* @note command format would be defined in initialization
|
||||
* @param start_addr the start address to be erased
|
||||
* @param area_len the erea length to be erased
|
||||
* @return flash operation result
|
||||
*/
|
||||
|
||||
esp_rom_spiflash_result_t esp_rom_opiflash_erase_area(uint32_t start_addr,
|
||||
uint32_t area_len);
|
||||
|
||||
/**
|
||||
* @brief to read data from opi flash
|
||||
* @note command format would be defined in initialization
|
||||
* @param flash_addr flash address to read data from
|
||||
* @param data_addr data buffer to accept the data
|
||||
* @param len data length to be read
|
||||
* @return flash operation result
|
||||
*/
|
||||
|
||||
esp_rom_spiflash_result_t esp_rom_opiflash_read(uint32_t flash_addr,
|
||||
void *data_addr,
|
||||
int len);
|
||||
|
||||
/**
|
||||
* @brief to write data to opi flash
|
||||
* @note command format would be defined in initialization
|
||||
* @param flash_addr flash address to write data to
|
||||
* @param data_addr data buffer to write to flash
|
||||
* @param len data length to write
|
||||
* @return flash operation result
|
||||
*/
|
||||
|
||||
esp_rom_spiflash_result_t esp_rom_opiflash_write(uint32_t flash_addr,
|
||||
const uint32_t *data_addr,
|
||||
int len);
|
||||
|
||||
/**
|
||||
* @brief send WREN command
|
||||
* @note command format would be defined in initialization
|
||||
* @param arg not used, set to NULL
|
||||
* @return flash operation result
|
||||
*/
|
||||
|
||||
esp_rom_spiflash_result_t esp_rom_opiflash_wren(void *arg);
|
||||
|
||||
/**
|
||||
* @brief to configure SPI0 read flash command format for cache
|
||||
* @note command format would be defined in initialization
|
||||
*
|
||||
*/
|
||||
|
||||
void
|
||||
esp_rom_opiflash_cache_mode_config(esp_rom_spiflash_read_mode_t mode,
|
||||
const esp_rom_opiflash_spi0rd_t *cache);
|
||||
|
||||
esp_rom_spiflash_result_t esp_rom_opiflash_read_raw(uint32_t flash_addr,
|
||||
uint8_t *buf, int len);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ARCH_XTENSA_SRC_ESP32S3_ROM_ESP32S3_OPI_FLASH_H */
|
||||
@@ -384,7 +384,7 @@ PROVIDE( Cache_WriteBack_Addr = 0x400016c8 );
|
||||
PROVIDE( Cache_Invalidate_ICache_All = 0x400016d4 );
|
||||
PROVIDE( cache_invalidate_dcache_all = 0x400016e0 );
|
||||
PROVIDE( Cache_Clean_All = 0x400016ec );
|
||||
PROVIDE( Cache_WriteBack_All = 0x400016f8 );
|
||||
PROVIDE( cache_writeback_all = 0x400016f8 );
|
||||
PROVIDE( Cache_Mask_All = 0x40001704 );
|
||||
PROVIDE( Cache_UnMask_Dram0 = 0x40001710 );
|
||||
PROVIDE( Cache_Suspend_ICache_Autoload = 0x4000171c );
|
||||
@@ -442,7 +442,7 @@ PROVIDE( Cache_Occupy_ICache_MEMORY = 0x40001980 );
|
||||
PROVIDE( Cache_Occupy_DCache_MEMORY = 0x4000198c );
|
||||
PROVIDE( Cache_MMU_Init = 0x40001998 );
|
||||
PROVIDE( Cache_Ibus_MMU_Set = 0x400019a4 );
|
||||
PROVIDE( Cache_Dbus_MMU_Set = 0x400019b0 );
|
||||
PROVIDE( cache_dbus_mmu_set = 0x400019b0 );
|
||||
PROVIDE( Cache_Count_Flash_Pages = 0x400019bc );
|
||||
PROVIDE( Cache_Flash_To_SPIRAM_Copy = 0x400019c8 );
|
||||
PROVIDE( Cache_Travel_Tag_Memory = 0x400019d4 );
|
||||
|
||||
Reference in New Issue
Block a user