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Finishes basic UART and serial console code for NUC120

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5661 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
2013-02-22 17:53:47 +00:00
parent 0c948a5bf1
commit dbad14380b
6 changed files with 1330 additions and 19 deletions
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arch/arm/src/nuc1xx/chip/nuc_uart.h
+15 -6
View File
@@ -136,10 +136,12 @@
#define UART_IER_DMA_TX_EN (1 << 14) /* Bit 14: TX DMA enable (UART0/1) */
#define UART_IER_DMA_RX_EN (1 << 15) /* Bit 15: RX DMA enable (UART0/1) */
#define UART_IER_ALLIE (0x0000f87f)
/* UART FIFO control register */
#define UART_FCR_RFR (1 << 1) /* Bit 1: RX filed software reset */
#define UART_FCR_TFR (1 << 2) /* Bit 2: TX field softweare reset */
#define UART_FCR_RFR (1 << 1) /* Bit 1: RX FIFO software reset */
#define UART_FCR_TFR (1 << 2) /* Bit 2: TX FIFO software reset */
#define UART_FCR_FRITL_SHIFT (4) /* Bits 4-7: RX FIFO interrupt trigger level */
#define UART_FCR_FRITL_MASK (15 << UART_FCR_FRITL_SHIFT)
# define UART_FCR_FRITL_1 (0 << UART_FCR_FRITL_SHIFT)
@@ -188,6 +190,10 @@
/* UART FIFO status register */
#define UART0_FIFO_DEPTH 64
#define UART1_FIFO_DEPTH 16
#define UART2_FIFO_DEPTH 16
#define UART_FSR_RX_OVER_IF (1 << 0) /* Bit 0: RX overflow error interrupt flag */
#define UART_FSR_RS485_ADD_DETF (1 << 3) /* Bit 3: RS-485 address byte detection flag */
#define UART_FSR_PEF (1 << 4) /* Bit 4: Parity error flag */
@@ -195,7 +201,7 @@
#define UART_FSR_BIF (1 << 6) /* Bit 6: Break interrupt flag */
#define UART_FSR_RX_POINTER_SHIFT (8) /* Bits 8-13: RX FIFO pointer */
#define UART_FSR_RX_POINTER_MASK (0x3f << UART_FSR_RX_POINTER_SHIFT)
#define UART_FSR_RX_EMPTY (1 << 14) /* Bit 14: Receiver FIFO emtpy */
#define UART_FSR_RX_EMPTY (1 << 14) /* Bit 14: Receiver FIFO empty */
#define UART_FSR_TX_POINTER_SHIFT (16) /* Bits 16-21: TX FIFO pointer */
#define UART_FSR_TX_POINTER_MASK (0x3f << UART_FSR_TX_POINTER_SHIFT)
#define UART_FSR_TX_EMPTY (1 << 22) /* Bit 22: Transmitter FIFO empty flag */
@@ -203,9 +209,8 @@
#define UART_FSR_TE_FLAG (1 << 28) /* Bit 28: Transmitter empty flag */
/* UART interrupt status register */
#define UART_ISR_
#define UART_ISR_RDA_IF (1 << 0) /* Bit 0: Receive data avaiable interrupt flag */
#define UART_ISR_RDA_IF (1 << 0) /* Bit 0: Receive data available interrupt flag */
#define UART_ISR_THRE_IF (1 << 1) /* Bit 1: Transmit holding register empty interrupt flag */
#define UART_ISR_RLS_IF (1 << 2) /* Bit 2: Receive line status interrupt flag */
#define UART_ISR_MODEM_IF (1 << 3) /* Bit 3: Modem interrupt flag (UART0/1) */
@@ -230,16 +235,20 @@
#define UART_TOR_TOIC_SHIFT (0) /* Bits 0-7: Time out interrupt comparator */
#define UART_TOR_TOIC_MASK (0xff << UART_TOR_TOIC_SHIFT)
# define UART_TOR_TOIC(t) ((t) << UART_TOR_TOIC_SHIFT)
#define UART_TOR_DLY_SHIFT (8) /* Bits 8-15: TX delay time value */
#define UART_TOR_DLY_MASK (0xff << UART_TOR_DLY_SHIFT)
# define UART_TOR_DLY(d) ((d) << UART_TOR_DLY_SHIFT)
/* UART BAUD rate divisor register */
#define UART_BAUD_BRD_SHIFT (0) /* Bits 0-15: Baud rate divider */
#define UART_BAUD_BRD_MASK (0xffff << UART_BAUD_BRD_SHIFT)
# define UART_BAUD_BRD(b) ((b) << UART_BAUD_BRD_SHIFT)
#define UART_BAUD_DIVIDER_X_SHIFT (24) /* Bits 24-27: Divider X */
#define UART_BAUD_DIVIDER_X_MASK (15 << UART_BAUD_DIVIDER_X_SHIFT)
#define UART_BAUD_DIV_X_OINE (1 << 28) /* Bit 28: Divider X equals one */
# define UART_BAUD_DIVIDER_X(x) ((x) << UART_BAUD_DIVIDER_X_SHIFT)
#define UART_BAUD_DIV_X_ONE (1 << 28) /* Bit 28: Divider X equals one */
#define UART_BAUD_DIV_X_EN (1 << 29) /* Bit 29: Divider X enable */
/* UART IrDA control register */
arch/arm/src/nuc1xx/nuc_config.h
+7 -4
View File
@@ -72,16 +72,19 @@
#ifndef CONFIG_NUC_UART0
# undef CONFIG_UART0_SERIAL_CONSOLE
# undef CONFIG_UART0_FLOW_CONTROL
# undef CONFIG_UART0_IRDAMODE
# undef CONFIG_UART0_RS485MODE
#endif
#ifndef CONFIG_NUC_UART1
# undef CONFIG_UART1_SERIAL_CONSOLE
# undef CONFIG_UART1_FLOW_CONTROL
# undef CONFIG_UART1_IRDAMODE
# undef CONFIG_UART1_RS485MODE
#endif
#undef CONFIG_UART2_FLOW_CONTROL /* UART2 does not support flow control */
#ifndef CONFIG_NUC_UART2
# undef CONFIG_UART2_SERIAL_CONSOLE
# undef CONFIG_UART2_IRDAMODE
@@ -95,20 +98,20 @@
#if defined(CONFIG_UART0_SERIAL_CONSOLE)
# undef CONFIG_UART1_SERIAL_CONSOLE
# undef CONFIG_UART2_SERIAL_CONSOLE
# define HAVE_CONSOLE 1
# define HAVE_SERIAL_CONSOLE 1
#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
# undef CONFIG_UART0_SERIAL_CONSOLE
# undef CONFIG_UART2_SERIAL_CONSOLE
# define HAVE_CONSOLE 1
# define HAVE_SERIAL_CONSOLE 1
#elif defined(CONFIG_UART2_SERIAL_CONSOLE)
# undef CONFIG_UART0_SERIAL_CONSOLE
# undef CONFIG_UART1_SERIAL_CONSOLE
# define HAVE_CONSOLE 1
# define HAVE_SERIAL_CONSOLE 1
#else
# undef CONFIG_UART0_SERIAL_CONSOLE
# undef CONFIG_UART1_SERIAL_CONSOLE
# undef CONFIG_UART2_SERIAL_CONSOLE
# undef HAVE_CONSOLE
# undef HAVE_SERIAL_CONSOLE
#endif
/************************************************************************************
arch/arm/src/nuc1xx/nuc_lowputc.c
+231 -9
View File
@@ -57,14 +57,32 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Here we assume that the default clock source for the UART modules is
* the external high speed crystal.
*/
/* Get the serial console UART configuration */
#ifdef HAVE_SERIAL_CONSOLE
# if defined(CONFIG_UART0_SERIAL_CONSOLE)
# define NUC_CONSOLE_BASE NUC_UART0_BASE
# define NUC_CONSOLE_BAUD CONFIG_UART0_BAUD
# define NUC_CONSOLE_BITS CONFIG_UART0_BITS
# define NUC_CONSOLE_PARITY CONFIG_UART0_PARITY
# define NUC_CONSOLE_2STOP CONFIG_UART0_2STOP
# if defined(CONFIG_UART1_SERIAL_CONSOLE)
# define NUC_CONSOLE_BASE NUC_UART1_BASE
# define NUC_CONSOLE_BAUD CONFIG_UART1_BAUD
# define NUC_CONSOLE_BITS CONFIG_UART1_BITS
# define NUC_CONSOLE_PARITY CONFIG_UART1_PARITY
# define NUC_CONSOLE_2STOP CONFIG_UART1_2STOP
# elif defined(CONFIG_UART2_SERIAL_CONSOLE)
# define NUC_CONSOLE_BASE NUC_UART2_BASE
# define NUC_CONSOLE_BAUD CONFIG_UART2_BAUD
# define NUC_CONSOLE_BITS CONFIG_UART2_BITS
# define NUC_CONSOLE_PARITY CONFIG_UART2_PARITY
# define NUC_CONSOLE_2STOP CONFIG_UART2_2STOP
# endif
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
@@ -82,6 +100,81 @@ void nuc_lowsetup(void)
#ifdef HAVE_UART
uint32_t regval;
/* Configure UART GPIO pins.
*
* Basic UART0 TX/RX requires that GPIOB MFP bits 0 and 1 be set. If flow
* control is enabled, then GPIOB MFP bits 3 and 4 must also be set and ALT
* MFP bits 11, 13, and 14 must be cleared.
*/
#if defined(CONFIG_NUC_UART0) || defined(CONFIG_NUC_UART1)
regval = getreg32(NUC_GCR_GPB_MFP);
#ifdef CONFIG_NUC_UART0
#ifdef CONFIG_UART0_FLOW_CONTROL
regval |= (GCR_GPB_MFP0 | GCR_GPB_MFP1 | GCR_GPB_MFP2| GCR_GPB_MFP3);
#else
regval |= (GCR_GPB_MFP0 | GCR_GPB_MFP1);
#endif
#endif /* CONFIG_NUC_UART0 */
/* Basic UART1 TX/RX requires that GPIOB MFP bits 4 and 5 be set. If flow
* control is enabled, then GPIOB MFP bits 6 and 7 must also be set and ALT
* MFP bit 11 must be cleared.
*/
#ifdef CONFIG_NUC_UART1
#ifdef CONFIG_UART1_FLOW_CONTROL
regval |= (GCR_GPB_MFP4 | GCR_GPB_MFP5 | GCR_GPB_MFP6| GCR_GPB_MFP7)
#else
regval |= (GCR_GPB_MFP4 | GCR_GPB_MFP5);
#endif
#endif /* CONFIG_NUC_UART1 */
putreg32(regval, NUC_GCR_GPB_MFP);
#if defined(CONFIG_UART0_FLOW_CONTROL) || defined(CONFIG_UART1_FLOW_CONTROL)
regval = getreg32(NUC_GCR_ALT_MFP);
regval &= ~GCR_ALT_MFP_EBI_EN;
#ifdef CONFIG_UART0_FLOW_CONTROL
regval &= ~(GCR_ALT_MFP_EBI_NWRL_EN | GCR_ALT_MFP_EBI_NWRH_WN);
#endif
putreg32(NUC_GCR_ALT_MFP);
#endif /* CONFIG_UART0_FLOW_CONTROL || CONFIG_UART1_FLOW_CONTROL */
#endif /* CONFIG_NUC_UART0 || CONFIG_NUC_UART1 */
/* UART1 TX/RX support requires that GPIOD bits 14 and 15 be set. UART2
* does not support flow control.
*/
#ifdef CONFIG_NUC_UART2
regval = getreg32(NUC_GCR_GPD_MFP);
regval |= (GCR_GPD_MFP14 | GCR_GPD_MFP15);
putreg32(regval, NUC_GCR_GPD_MFP);
#endif /* CONFIG_NUC_UART2 */
/* Reset the UART peripheral(s) */
regval = getreg32(NUC_GCR_IPRSTC2);
#ifdef CONFIG_NUC_UART0
regval |= GCR_IPRSTC2_UART0_RST;
putreg32(regval, NUC_GCR_IPRSTC2);
regval &= ~GCR_IPRSTC2_UART0_RST;
putreg32(regval, NUC_GCR_IPRSTC2);
#endif
#ifdef CONFIG_NUC_UART1
regval |= GCR_IPRSTC2_UART1_RST;
putreg32(regval, NUC_GCR_IPRSTC2);
regval &= ~GCR_IPRSTC2_UART1_RST;
putreg32(regval, NUC_GCR_IPRSTC2);
#endif
#ifdef CONFIG_NUC_UART2
regval |= GCR_IPRSTC2_UART2_RST;
putreg32(regval, NUC_GCR_IPRSTC2);
regval &= ~GCR_IPRSTC2_UART2_RST;
putreg32(regval, NUC_GCR_IPRSTC2);
#endif
/* Configure the UART clock source
*
* Here we assume that the UART clock source is the external high speed
@@ -105,11 +198,140 @@ void nuc_lowsetup(void)
putreg32(regval, NUC_CLK_APBCLK);
/* Configure UART GPIO pins */
#warning "Missing logic"
/* Configure the console UART */
#warning "Missing logic"
#ifdef HAVE_SERIAL_CONSOLE
/* Reset the TX FIFO */
regval = getreg32(NUC_CONSOLE_BASE + NUC_UART_FCR_OFFSET
regval |= UART_FCR_TFR
putreg32(regval, NUC_CONSOLE_BASE + NUC_UART_FCR_OFFSET);
/* Reset the RX FIFO */
regval = getreg32(NUC_CONSOLE_BASE + NUC_UART_FCR_OFFSET
regval |= UART_FCR_RFR
putreg32(regval, NUC_CONSOLE_BASE + NUC_UART_FCR_OFFSET);
/* Set Rx Trigger Level */
regval &= ~UART_FCR_FRITL_MASK;
regval |= UART_FCR_FRITL_4;
putreg32(regval, NUC_CONSOLE_BASE + NUC_UART_FCR_OFFSET);
/* Set Parity & Data bits and Stop bits */
regval = 0;
#if NUC_CONSOLE_BITS == 5
regval |= UART_LCR_WLS_5;
#elif NUC_CONSOLE_BITS == 6
regval |= UART_LCR_WLS_6;
#elif NUC_CONSOLE_BITS == 7
regval |= UART_LCR_WLS_7;
#elif NUC_CONSOLE_BITS == 8
regval |= UART_LCR_WLS_8;
#else
error "Unknown console UART data width"
#endif
#if NUC_CONSOLE_PARITY == 1
regval |= UART_LCR_PBE;
#elif NUC_CONSOLE_PARITY == 2
regval |= (UART_LCR_PBE | UART_LCR_EPE);
#endif
#if NUC_CONSOLE_2STOP != 0
revgval |= UART_LCR_NSB;
#endif
putreg32(regval, NUC_CONSOLE_BASE + NUC_UART_LCR_OFFSET);
/* Set Time-Out values */
regval = UART_TOR_TOIC(40) | UART_TOR_DLY(0);
putreg32(regval, NUC_CONSOLE_BASE + NUC_UART_TOR_OFFSET);
/* Set the baud */
nuc_setbaud(CONSOLE_BASE, CONSOLE_BAUD);
#endif /* HAVE_SERIAL_CONSOLE */
#endif /* HAVE_UART */
}
}
/****************************************************************************
* Name: nuc_setbaud
*
* Description:
* Set the BAUD divxisor for the selected UART
*
* Mode DIV_X_EN DIV_X_ONE Divider X BRD (Baud rate equation)
* -------------------------------------------------------------
* 0 Disable 0 B A UART_CLK / [16 * (A+2)]
* 1 Enable 0 B A UART_CLK / [(B+1) * (A+2)] , B must >= 8
* 2 Enable 1 Don't care A UART_CLK / (A+2), A must >=3
*
* Here we assume that the default clock source for the UART modules is
* the external high speed crystal.
*
*****************************************************************************/
#ifdef HAVE_UART
void nuc_setbaud(uintptr_t base, uint32_t baud)
{
uint32_t regval;
uint32_t clksperbit;
uint32_t brd;
uint32_t divx;
regval = getreg32(base + NUC_UART_BAUD_OFFSET);
/* Source Clock mod 16 < 3 => Using Divider X = 16 (MODE#0) */
clksperbit = BOARD_HIGHSPEED_XTAL_FREQUENCY / baud;
if ((clksperbit & 15) < 3)
{
regval &= ~(UART_BAUD_DIV_X_ONE | UART_BAUD_DIV_X_EN);
brd = (clksperbit >> 4) - 2;
}
/* Source Clock mod 16 >3 => Up 5% Error BaudRate */
else
{
/* Try to Set Divider X = 1 (MODE#2)*/
regval |= (UART_BAUD_DIV_X_ONE | UART_BAUD_DIV_X_EN);
brd = clksperbit - 2;
/* Check if the divxider exceeds the range */
if (clksperbit > 0xffff)
{
/* Try to Set Divider X up 10 (MODE#1) */
regval &= ~UART_BAUD_DIV_X_ONE;
for (divx = 8; divx <16; divx++)
{
brd = (clksperbit % (divx+1))
if (brd < 3)
{
regval &= ~UART_BAUD_DIVIDER_X_MASK;
regval |= UART_BAUD_DIVIDER_X(divx);
brd -= 2;
break;
}
}
}
}
regval &= ~UART_BAUD_BRD_MASK;
regval &= define UART_BAUD_BRD(brd);
putreg32(regval, base + NUC_UART_BAUD_OFFSET);
}
#endif /* HAVE_UART */
arch/arm/src/nuc1xx/nuc_lowputc.h
+21
View File
@@ -79,6 +79,27 @@ extern "C"
void nuc_lowsetup(void);
/****************************************************************************
* Name: nuc_setbaud
*
* Description:
* Set the BAUD divxisor for the selected UART
*
* Mode DIV_X_EN DIV_X_ONE Divider X BRD (Baud rate equation)
* -------------------------------------------------------------
* 0 Disable 0 B A UART_CLK / [16 * (A+2)]
* 1 Enable 0 B A UART_CLK / [(B+1) * (A+2)] , B must >= 8
* 2 Enable 1 Don't care A UART_CLK / (A+2), A must >=3
*
* Here we assume that the default clock source for the UART modules is
* the external high speed crystal.
*
*****************************************************************************/
#ifdef HAVE_UART
void nuc_setbaud(uintptr_t base, uint32_t baud)
#endif
#undef EXTERN
#if defined(__cplusplus)
}
arch/arm/src/nuc1xx/nuc_serial.c
+988
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File diff suppressed because it is too large Load Diff
arch/arm/src/nuc1xx/nuc_serial.h
+68
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@@ -0,0 +1,68 @@
/************************************************************************************
* arch/arm/src/nuc1xx/nuc_serial.h
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_NUC1XX_NUC_SERIAL_H
#define __ARCH_ARM_SRC_NUC1XX_NUC_SERIAL_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "nuc_config.h"
#include "chip/nuc_uart.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
/************************************************************************************
* Inline Functions
************************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
#endif /* __ARCH_ARM_SRC_NUC1XX_NUC_SERIAL_H */