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Documentation/risc-v/esp32[c6]: Add LP_UART support docs

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Add LPUART support doc for esp32c6

Signed-off-by: Eren Terzioglu <eren.terzioglu@espressif.com>
This commit is contained in:
Eren Terzioglu
2025-06-26 17:51:20 +02:00
committed by Xiang Xiao
parent 1c48c0cba7
commit d8f241b29d
4 changed files with 7 additions and 8 deletions
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Documentation/platforms/risc-v/esp32c6/index.rst
+1 -1
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@@ -362,7 +362,7 @@ SPIFLASH Yes
SPIRAM No SPIRAM No
Temp. Sensor No Temp. Sensor No
Timers Yes Timers Yes
UART Yes UART Yes LPUART supported
USB Serial Yes USB Serial Yes
Watchdog Yes Watchdog Yes
Wi-Fi Yes Wi-Fi Yes
arch/risc-v/src/common/espressif/Make.defs
+1 -1
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@@ -178,7 +178,7 @@ endif
ESP_HAL_3RDPARTY_REPO = esp-hal-3rdparty ESP_HAL_3RDPARTY_REPO = esp-hal-3rdparty
ifndef ESP_HAL_3RDPARTY_VERSION ifndef ESP_HAL_3RDPARTY_VERSION
ESP_HAL_3RDPARTY_VERSION = e9a78c811578545e2bc673862d885a15bd6cbf67 ESP_HAL_3RDPARTY_VERSION = 98dad3d9b4607df319eca4a7baf50545cda0b1a2
endif endif
ifndef ESP_HAL_3RDPARTY_URL ifndef ESP_HAL_3RDPARTY_URL
arch/risc-v/src/common/espressif/esp_lowputc.c
+4 -6
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@@ -56,6 +56,8 @@
# include "soc/uart_pins.h" # include "soc/uart_pins.h"
# include "hal/rtc_io_hal.h" # include "hal/rtc_io_hal.h"
# include "soc/uart_periph.h" # include "soc/uart_periph.h"
# include "driver/rtc_io.h"
# include "io_mux.h"
#endif #endif
/**************************************************************************** /****************************************************************************
@@ -271,11 +273,7 @@ static void esp_lowputc_lp_uart_config_io(const struct esp_uart_s *priv,
DEBUGASSERT(lp_pin != -1); DEBUGASSERT(lp_pin != -1);
#if SOC_LP_IO_CLOCK_IS_INDEPENDENT #if SOC_LP_IO_CLOCK_IS_INDEPENDENT
RTCIO_RCC_ATOMIC() io_mux_enable_lp_io_clock(lp_pin, true);
{
rtcio_ll_enable_io_clock(true);
}
#endif #endif
rtcio_hal_function_select(lp_pin, RTCIO_LL_FUNC_RTC); rtcio_hal_function_select(lp_pin, RTCIO_LL_FUNC_RTC);
rtcio_hal_set_direction(pin, direction); rtcio_hal_set_direction(pin, direction);
@@ -283,7 +281,7 @@ static void esp_lowputc_lp_uart_config_io(const struct esp_uart_s *priv,
const uart_periph_sig_t *upin = const uart_periph_sig_t *upin =
&uart_periph_signal[LP_UART_NUM_0].pins[idx]; &uart_periph_signal[LP_UART_NUM_0].pins[idx];
#if !SOC_LP_GPIO_MATRIX_SUPPORTED #if !SOC_LP_GPIO_MATRIX_SUPPORTED
rtcio_hal_iomux_func_sel(lp_pin, upin->iomux_func); rtc_gpio_iomux_func_sel(pin, upin->iomux_func);
#else #else
/* ToDo: Add LP UART for LP GPIO Matrix supported devices (e.g ESP32-P4) */ /* ToDo: Add LP UART for LP GPIO Matrix supported devices (e.g ESP32-P4) */
#endif /* SOC_LP_GPIO_MATRIX_SUPPORTED */ #endif /* SOC_LP_GPIO_MATRIX_SUPPORTED */
arch/risc-v/src/esp32c6/hal_esp32c6.mk
+1
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@@ -131,6 +131,7 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)esp_clk_tree_common.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)esp_clk_tree_common.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)esp_clk_tree.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)esp_clk_tree.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)cpu_region_protect.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)cpu_region_protect.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)io_mux.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)ocode_init.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)ocode_init.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)pmu_init.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)pmu_init.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)pmu_param.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)pmu_param.c