mirror of
https://github.com/apache/nuttx.git
synced 2026-05-20 20:44:39 +08:00
Merged nuttx/nuttx into master
This commit is contained in:
Marc Rechté
@@ -438,7 +438,7 @@ o pthreads (sched/pthreads)
|
||||
serve as cancellation points. They are, however, simple wrappers around nanosleep
|
||||
which is a true cancellation point.
|
||||
NOTE 02: system() is actually implemented in apps/ as part of NSH. It cannot be
|
||||
a cancellation point either.
|
||||
a cancellation point.
|
||||
NOTE 03: sigpause() is a user-space function in the C library and cannot serve as
|
||||
cancellation points. It is, however, a simple wrapper around sigsuspend()
|
||||
which is a true cancellation point.
|
||||
|
||||
@@ -43,6 +43,8 @@
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <arch/kinetis/kinetis_mcg.h>
|
||||
#include <arch/kinetis/kinetis_sim.h>
|
||||
#include <arch/kinetis/kinetis_pmc.h>
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
|
||||
@@ -76,7 +76,7 @@
|
||||
* KINETIS_MCG_HAS_PLL_INTERNAL_MODE - Has PEI mode or PBI mode
|
||||
* KINETIS_MCG_HAS_RESET_IS_BLPI - Has Reset clock mode is BLPI
|
||||
*
|
||||
* MCD Register Configuration
|
||||
* MCG Register Configuration
|
||||
*
|
||||
* KINETIS_MCG_HAS_C1 - SoC has C1 Register
|
||||
* KINETIS_MCG_HAS_C1_IREFS - SoC has C1[IREFS]
|
||||
@@ -289,7 +289,7 @@
|
||||
# undef KINETIS_MCG_HAS_PLL_INTERNAL_MODE /* Has PEI mode or PBI mode */
|
||||
# undef KINETIS_MCG_HAS_RESET_IS_BLPI /* Has Reset clock mode is BLPI */
|
||||
|
||||
/* MCD Register Configuration */
|
||||
/* MCG Register Configuration */
|
||||
|
||||
# define KINETIS_MCG_HAS_C1 1 /* SoC has C1 Register */
|
||||
# define KINETIS_MCG_HAS_C1_IREFS 1 /* SoC has C1[IREFS] */
|
||||
@@ -371,7 +371,7 @@
|
||||
# undef KINETIS_MCG_HAS_PLL_INTERNAL_MODE /* Has PEI mode or PBI mode */
|
||||
# undef KINETIS_MCG_HAS_RESET_IS_BLPI /* Has Reset clock mode is BLPI */
|
||||
|
||||
/* MCD Register Configuration */
|
||||
/* MCG Register Configuration */
|
||||
|
||||
# define KINETIS_MCG_HAS_C1 1 /* SoC has C1 Register */
|
||||
# define KINETIS_MCG_HAS_C1_IREFS 1 /* SoC has C1[IREFS] */
|
||||
@@ -448,7 +448,7 @@
|
||||
|
||||
/* Verified to Document Number: Document Number: K66P144M180SF5RMV2 Rev. 2, May 2015 */
|
||||
|
||||
# define KINETIS_MCG_VERSION KINETIS_K_MCG_VERSION_06
|
||||
# define KINETIS_MCG_VERSION KINETIS_MCG_VERSION_06
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||||
|
||||
/* MCG Configuration Parameters */
|
||||
|
||||
@@ -463,7 +463,7 @@
|
||||
# undef KINETIS_MCG_HAS_PLL_INTERNAL_MODE /* Has PEI mode or PBI mode */
|
||||
# undef KINETIS_MCG_HAS_RESET_IS_BLPI /* Has Reset clock mode is BLPI */
|
||||
|
||||
/* MCD Register Configuration */
|
||||
/* MCG Register Configuration */
|
||||
|
||||
# define KINETIS_MCG_HAS_C1 1 /* SoC has C1 Register */
|
||||
# define KINETIS_MCG_HAS_C1_IREFS 1 /* SoC has C1[IREFS] */
|
||||
@@ -544,7 +544,7 @@
|
||||
# undef KINETIS_MCG_HAS_PLL_INTERNAL_MODE /* Has PEI mode or PBI mode */
|
||||
# undef KINETIS_MCG_HAS_RESET_IS_BLPI /* Has Reset clock mode is BLPI */
|
||||
|
||||
/* MCD Register Configuration */
|
||||
/* MCG Register Configuration */
|
||||
|
||||
# define KINETIS_MCG_HAS_C1 1 /* SoC has C1 Register */
|
||||
# define KINETIS_MCG_HAS_C1_IREFS 1 /* SoC has C1[IREFS] */
|
||||
|
||||
@@ -0,0 +1,324 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/include/kinetis/kinetis_pmc.h
|
||||
*
|
||||
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_INCLUDE_KINETIS_KINETIS_PMC_H
|
||||
#define __ARCH_ARM_INCLUDE_KINETIS_KINETIS_PMC_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Note: It is envisioned that in the long term as a chip is added. The author of
|
||||
* the new chip definitions will either find the exact configuration in an existing
|
||||
* chip define and add the new chip to it Or add the PMC feature configuration
|
||||
* #defines to the chip ifdef list below. In either case the author should mark
|
||||
* it as "Verified to Document Number:" taken from the reference manual.
|
||||
*
|
||||
* To maintain backward compatibility to the version of NuttX prior to
|
||||
* 2/22/2017, the catch all KINETIS_PMC_VERSION_UKN configuration is assigned
|
||||
* to all the chips that did not have any conditional compilation based on
|
||||
* KINETIS_K64 or KINETIS_K66. This is a "No worse" than the original code solution.
|
||||
* N.B. Each original chip "if"definitions have been left intact so that the
|
||||
* complete legacy definitions prior to 2/22/2017 may be filled in completely when
|
||||
* vetted.
|
||||
*/
|
||||
|
||||
/* PMC Register Configuration
|
||||
*
|
||||
* KINETIS_PMC_HAS_REGSC - SoC has REGSC Register
|
||||
* KINETIS_PMC_HAS_REGSC_ACKISO - SoC has REGSC[ACKISO]
|
||||
* KINETIS_PMC_HAS_REGSC_VLPRS - SoC has REGSC[VLPRS]
|
||||
* KINETIS_PMC_HAS_REGSC_VLPO - SoC has REGSC[VLPO]
|
||||
* KINETIS_PMC_HAS_REGSC_REGFPM - SoC has REGSC[REGFPM]
|
||||
* KINETIS_PMC_HAS_REGSC_BGEN - SoC has REGSC[BGEN]
|
||||
* KINETIS_PMC_HAS_REGSC_TRAMPO - SoC has REGSC[TRAMPO]
|
||||
* KINETIS_PMC_HAS_REGSC_REGONS - SoC has REGSC[REGONS]
|
||||
*/
|
||||
|
||||
/* Describe the version of the PMC
|
||||
*
|
||||
* These defines are not related to any NXP reference but are merely
|
||||
* a way to label the versions we are using
|
||||
*/
|
||||
|
||||
#define KINETIS_PMC_VERSION_UKN -1 /* What was in nuttx prior to 2/22/2017 */
|
||||
#define KINETIS_PMC_VERSION_01 1 /* Verified Document Number: K60P144M150SF3RM Rev. 3, November 2014 */
|
||||
#define KINETIS_PMC_VERSION_04 4 /* Verified to Document Numbers:
|
||||
* K20P64M72SF1RM Rev. 1.1, Dec 2012
|
||||
* K64P144M120SF5RM Rev. 2, January 2014
|
||||
* K66P144M180SF5RMV2 Rev. 2, May 2015 */
|
||||
|
||||
/* MK20DX/DN---VLH5
|
||||
*
|
||||
* ------------- ------ --- ------- ------ ------- ------ ----- ----
|
||||
* PART NUMBER CPU PIN PACKAGE TOTAL PROGRAM EEPROM SRAM GPIO
|
||||
* FREQ CNT FLASH FLASH
|
||||
* ------------- ------ --- ------- ------ ------- ------ ----- ----
|
||||
* MK20DN32VLH5 50 MHz 64 LQFP 32 KB 32 KB — 8 KB 40
|
||||
* MK20DX32VLH5 50 MHz 64 LQFP 64 KB 32 KB 2 KB 8 KB 40
|
||||
* MK20DN64VLH5 50 MHz 64 LQFP 64 KB 64 KB — 16 KB 40
|
||||
* MK20DX64VLH5 50 MHz 64 LQFP 96 KB 64 KB 2 KB 16 KB 40
|
||||
* MK20DN128VLH5 50 MHz 64 LQFP 128 KB 128 KB — 16 KB 40
|
||||
* MK20DX128VLH5 50 MHz 64 LQFP 160 KB 128 KB 2 KB 16 KB 40
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_MK20DN32VLH5) || \
|
||||
defined(CONFIG_ARCH_CHIP_MK20DX32VLH5) || \
|
||||
defined(CONFIG_ARCH_CHIP_MK20DN64VLH5) || \
|
||||
defined(CONFIG_ARCH_CHIP_MK20DX64VLH5) || \
|
||||
defined(CONFIG_ARCH_CHIP_MK20DN128VLH5) || \
|
||||
defined(CONFIG_ARCH_CHIP_MK20DX128VLH5)
|
||||
|
||||
# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN
|
||||
|
||||
/* MK20DX---VLH7
|
||||
*
|
||||
* ------------- ------ --- ------- ------ ------- ------ ----- ----
|
||||
* PART NUMBER CPU PIN PACKAGE TOTAL PROGRAM EEPROM SRAM GPIO
|
||||
* FREQ CNT FLASH FLASH
|
||||
* ------------- ------ --- ------- ------ ------- ------ ----- ----
|
||||
* MK20DX64VLH7 72 MHz 64 LQFP 96 KB 64 KB 2 KB 16 KB 40
|
||||
* MK20DX128VLH7 72 MHz 64 LQFP 160 KB 128 KB 2 KB 32 KB 40
|
||||
* MK20DX256VLH7 72 MHz 64 LQFP 288 KB 256 KB 2 KB 64 KB 40
|
||||
* ------------- ------ --- ------- ------ ------- ------ ----- ----
|
||||
*/
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_MK20DX64VLH7) || defined(CONFIG_ARCH_CHIP_MK20DX128VLH7) || \
|
||||
defined(CONFIG_ARCH_CHIP_MK20DX256VLH7)
|
||||
|
||||
/* Verified to Document Number: K20P64M72SF1RM Rev. 1.1, Dec 2012 */
|
||||
|
||||
# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_04
|
||||
|
||||
/* PMC Register Configuration */
|
||||
|
||||
# define KINETIS_PMC_HAS_REGSC 1 /* SoC has REGSC Register */
|
||||
# define KINETIS_PMC_HAS_REGSC_ACKISO 1 /* SoC has REGSC[ACKISO] */
|
||||
# undef KINETIS_PMC_HAS_REGSC_VLPRS /* SoC has REGSC[VLPRS] */
|
||||
# undef KINETIS_PMC_HAS_REGSC_VLPO /* SoC has REGSC[VLPO] */
|
||||
# undef KINETIS_PMC_HAS_REGSC_REGFPM /* SoC has REGSC[REGFPM] */
|
||||
# define KINETIS_PMC_HAS_REGSC_BGEN 1 /* SoC has REGSC[BGEN] */
|
||||
# undef KINETIS_PMC_HAS_REGSC_TRAMPO /* SoC has REGSC[TRAMPO] */
|
||||
# define KINETIS_PMC_HAS_REGSC_REGONS 1 /* SoC has REGSC[REGONS] */
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_MK40X64VFX50) || defined(CONFIG_ARCH_CHIP_MK40X64VLH50) || \
|
||||
defined(CONFIG_ARCH_CHIP_MK40X64VLK50) || defined(CONFIG_ARCH_CHIP_MK40X64VMB50)
|
||||
|
||||
# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_MK40X128VFX50) || defined(CONFIG_ARCH_CHIP_MK40X128VLH50) || \
|
||||
defined(CONFIG_ARCH_CHIP_MK40X128VLK50) || defined(CONFIG_ARCH_CHIP_MK40X128VMB50) || \
|
||||
defined(CONFIG_ARCH_CHIP_MK40X128VLL50) || defined(CONFIG_ARCH_CHIP_MK40X128VML50) || \
|
||||
defined(CONFIG_ARCH_CHIP_MK40X128VFX72) || defined(CONFIG_ARCH_CHIP_MK40X128VLH72) || \
|
||||
defined(CONFIG_ARCH_CHIP_MK40X128VLK72) || defined(CONFIG_ARCH_CHIP_MK40X128VMB72) || \
|
||||
defined(CONFIG_ARCH_CHIP_MK40X128VLL72) || defined(CONFIG_ARCH_CHIP_MK40X128VML72)
|
||||
|
||||
# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_MK40X256VLK72) || defined(CONFIG_ARCH_CHIP_MK40X256VMB72) || \
|
||||
defined(CONFIG_ARCH_CHIP_MK40X256VLL72) || defined(CONFIG_ARCH_CHIP_MK40X256VML72)
|
||||
|
||||
# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_MK40X128VLQ100) || defined(CONFIG_ARCH_CHIP_MK40X128VMD100)
|
||||
|
||||
# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_MK40X256VLQ100) || defined(CONFIG_ARCH_CHIP_MK40X256VMD100)
|
||||
|
||||
# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_MK40N512VLK100) || defined(CONFIG_ARCH_CHIP_MK40N512VMB100) || \
|
||||
defined(CONFIG_ARCH_CHIP_MK40N512VLL100) || defined(CONFIG_ARCH_CHIP_MK40N512VML100) || \
|
||||
defined(CONFIG_ARCH_CHIP_MK40N512VLQ100) || defined(CONFIG_ARCH_CHIP_MK40N512VMD100)
|
||||
|
||||
# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_MK60N256VLL100)
|
||||
|
||||
# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_MK60X256VLL100)
|
||||
|
||||
# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_MK60N512VLL100)
|
||||
|
||||
# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_MK60N256VML100)
|
||||
|
||||
# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_MK60X256VML100)
|
||||
|
||||
# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_MK60N512VML100)
|
||||
|
||||
# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_MK60N256VLQ100)
|
||||
|
||||
# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_MK60X256VLQ100)
|
||||
|
||||
# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_MK60N512VLQ100)
|
||||
|
||||
# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_MK60N256VMD100)
|
||||
|
||||
# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_MK60X256VMD100)
|
||||
|
||||
# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_MK60N512VMD100)
|
||||
|
||||
# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_MK60FN1M0VLQ12)
|
||||
|
||||
/* Verified to Document Number: K60P144M100SF2V2RM Rev. 2 Jun 2012 */
|
||||
|
||||
# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_01
|
||||
|
||||
/* PMC Register Configuration */
|
||||
|
||||
# define KINETIS_PMC_HAS_REGSC 1 /* SoC has REGSC Register */
|
||||
# define KINETIS_PMC_HAS_REGSC_ACKISO 1 /* SoC has REGSC[ACKISO] */
|
||||
# undef KINETIS_PMC_HAS_REGSC_VLPRS /* SoC has REGSC[VLPRS] */
|
||||
# undef KINETIS_PMC_HAS_REGSC_VLPO /* SoC has REGSC[VLPO] */
|
||||
# undef KINETIS_PMC_HAS_REGSC_REGFPM /* SoC has REGSC[REGFPM] */
|
||||
# undef KINETIS_PMC_HAS_REGSC_BGEN /* SoC has REGSC[BGEN] */
|
||||
# undef KINETIS_PMC_HAS_REGSC_TRAMPO /* SoC has REGSC[TRAMPO] */
|
||||
# define KINETIS_PMC_HAS_REGSC_REGONS 1 /* SoC has REGSC[REGONS] */
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_MK64FN1M0VLL12) || defined(CONFIG_ARCH_CHIP_MK64FX512VLL12) || \
|
||||
defined(CONFIG_ARCH_CHIP_MK64FX512VDC12) || defined(CONFIG_ARCH_CHIP_MK64FN1M0VDC12) || \
|
||||
defined(CONFIG_ARCH_CHIP_MK64FX512VLQ12) || defined(CONFIG_ARCH_CHIP_MK64FN1M0VLQ12) || \
|
||||
defined(CONFIG_ARCH_CHIP_MK64FX512VMD12) || defined(CONFIG_ARCH_CHIP_MK64FN1M0VMD12)
|
||||
|
||||
/* Verified to Document Number: K64P144M120SF5RM Rev. 2, January 2014 */
|
||||
|
||||
# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_04
|
||||
|
||||
/* PMC Register Configuration */
|
||||
|
||||
# define KINETIS_PMC_HAS_REGSC 1 /* SoC has REGSC Register */
|
||||
# define KINETIS_PMC_HAS_REGSC_ACKISO 1 /* SoC has REGSC[ACKISO] */
|
||||
# undef KINETIS_PMC_HAS_REGSC_VLPRS /* SoC has REGSC[VLPRS] */
|
||||
# undef KINETIS_PMC_HAS_REGSC_VLPO /* SoC has REGSC[VLPO] */
|
||||
# undef KINETIS_PMC_HAS_REGSC_REGFPM /* SoC has REGSC[REGFPM] */
|
||||
# define KINETIS_PMC_HAS_REGSC_BGEN 1 /* SoC has REGSC[BGEN] */
|
||||
# undef KINETIS_PMC_HAS_REGSC_TRAMPO /* SoC has REGSC[TRAMPO] */
|
||||
# define KINETIS_PMC_HAS_REGSC_REGONS 1 /* SoC has REGSC[REGONS] */
|
||||
|
||||
/* MK66F N/X 1M0/2M0 V MD/LQ 18
|
||||
*
|
||||
* --------------- ------- --- ------- ------- ------ ------ ------ -----
|
||||
* PART NUMBER CPU PIN PACKAGE TOTAL PROGRAM EEPROM SRAM GPIO
|
||||
* FREQ CNT FLASH FLASH
|
||||
* --------------- ------- --- ------- ------- ------ ------ ------ -----
|
||||
* MK66FN2M0VMD18 180 MHz 144 MAPBGA 2 MB — — KB 260 KB 100
|
||||
* MK66FX1M0VMD18 180 MHz 144 MAPBGA 1.25 MB 1 MB 4 KB 256 KB 100
|
||||
* MK66FN2M0VLQ18 180 MHz 144 LQFP 2 MB — — KB 260 KB 100
|
||||
* MK66FX1M0VLQ18 180 MHz 144 LQFP 1.25 MB 1 MB 4 KB 256 KB 100
|
||||
*/
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_MK66FN2M0VMD18) || defined(CONFIG_ARCH_CHIP_MK66FX1M0VMD18) || \
|
||||
defined(CONFIG_ARCH_CHIP_MK66FN2M0VLQ18) || defined(CONFIG_ARCH_CHIP_MK66FX1M0VLQ18)
|
||||
|
||||
/* Verified to Document Number: Document Number: K66P144M180SF5RMV2 Rev. 2, May 2015 */
|
||||
|
||||
# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_04
|
||||
|
||||
/* PMC Register Configuration */
|
||||
|
||||
# define KINETIS_PMC_HAS_REGSC 1 /* SoC has REGSC Register */
|
||||
# define KINETIS_PMC_HAS_REGSC_ACKISO 1 /* SoC has REGSC[ACKISO] */
|
||||
# undef KINETIS_PMC_HAS_REGSC_VLPRS /* SoC has REGSC[VLPRS] */
|
||||
# undef KINETIS_PMC_HAS_REGSC_VLPO /* SoC has REGSC[VLPO] */
|
||||
# undef KINETIS_PMC_HAS_REGSC_REGFPM /* SoC has REGSC[REGFPM] */
|
||||
# define KINETIS_PMC_HAS_REGSC_BGEN 1 /* SoC has REGSC[BGEN] */
|
||||
# undef KINETIS_PMC_HAS_REGSC_TRAMPO /* SoC has REGSC[TRAMPO] */
|
||||
# define KINETIS_PMC_HAS_REGSC_REGONS 1 /* SoC has REGSC[REGONS] */
|
||||
|
||||
#else
|
||||
# error "Unsupported Kinetis chip"
|
||||
#endif
|
||||
|
||||
/* Use the catch all configuration for the PMC based on the implementations in nuttx prior 2/3/2017 */
|
||||
|
||||
#if KINETIS_PMC_VERSION == KINETIS_PMC_VERSION_UKN
|
||||
|
||||
/* PMC Register Configuration */
|
||||
|
||||
# define KINETIS_PMC_HAS_REGSC 1 /* SoC has REGSC Register */
|
||||
# undef KINETIS_PMC_HAS_REGSC_ACKISO /* SoC has REGSC[ACKISO] */
|
||||
# define KINETIS_PMC_HAS_REGSC_VLPRS 1 /* SoC has REGSC[VLPRS] */
|
||||
# undef KINETIS_PMC_HAS_REGSC_VLPO /* SoC has REGSC[VLPO] */
|
||||
# undef KINETIS_PMC_HAS_REGSC_REGFPM /* SoC has REGSC[REGFPM] */
|
||||
# undef KINETIS_PMC_HAS_REGSC_BGEN /* SoC has REGSC[BGEN] */
|
||||
# define KINETIS_PMC_HAS_REGSC_TRAMPO 1 /* SoC has REGSC[TRAMPO] */
|
||||
# define KINETIS_PMC_HAS_REGSC_REGONS 1 /* SoC has REGSC[REGONS] */
|
||||
|
||||
#endif
|
||||
|
||||
#if !defined(KINETIS_PMC_VERSION)
|
||||
# error "No KINETIS_PMC_VERSION defined!"
|
||||
#endif
|
||||
|
||||
#if defined(KINETIS_PMC_HAS_C5_PRDIV)
|
||||
# define KINETIS_PMC_C5_PRDIV_MASK ((1 << (KINETIS_PMC_C5_PRDIV_BITS))-1)
|
||||
#endif
|
||||
|
||||
#if defined(KINETIS_PMC_HAS_C7_OSCSEL)
|
||||
# define KINETIS_PMC_C7_OSCSEL_MASK ((1 << (KINETIS_PMC_C7_OSCSEL_BITS))-1)
|
||||
#endif
|
||||
|
||||
#endif /* __ARCH_ARM_INCLUDE_KINETIS_KINETIS_PMC_H */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -232,7 +232,9 @@
|
||||
|
||||
/* LLWU Control and Status Register */
|
||||
|
||||
#define LLWU_CS_ACKISO (1 << 7) /* Bit 7: Acknowledge Isolation */
|
||||
#if !defined(KINETIS_PMC_HAS_REGSC_ACKISO)
|
||||
# define LLWU_CS_ACKISO (1 << 7) /* Bit 7: Acknowledge Isolation */
|
||||
#endif
|
||||
/* Bits 2-6: Reserved */
|
||||
#define LLWU_CS_FLTEP (1 << 1) /* Bit 1: Digital Filter on External Pin */
|
||||
#define LLWU_CS_FLTR (1 << 0) /* Bit 0: Digital Filter on RESET Pin */
|
||||
|
||||
@@ -78,22 +78,33 @@
|
||||
|
||||
#define PMC_LVDSC2_LVWV_SHIFT (0) /* Bits 0-1: Low-Voltage Warning Voltage Select */
|
||||
#define PMC_LVDSC2_LVWV_MASK (3 << PMC_LVDSC2_LVWV_SHIFT)
|
||||
# define PMC_LVDSC2_LVWV_ LOW (0 << PMC_LVDSC2_LVWV_SHIFT) /* Low trip point selected (VLVW = VLVW1H/L) */
|
||||
# define PMC_LVDSC2_LVWV_ MID1 (1 << PMC_LVDSC2_LVWV_SHIFT) /* Mid 1 trip point selected (VLVW = VLVW2H/L) */
|
||||
# define PMC_LVDSC2_LVWV_ MID2 (2 << PMC_LVDSC2_LVWV_SHIFT) /* Mid 2 trip point selected (VLVW = VLVW3H/L) */
|
||||
# define PMC_LVDSC2_LVWV_ HIGH (3 << PMC_LVDSC2_LVWV_SHIFT) /* High trip point selected (VLVW = VLVW4H/L) */
|
||||
# define PMC_LVDSC2_LVWV_LOW (0 << PMC_LVDSC2_LVWV_SHIFT) /* Low trip point selected (VLVW = VLVW1H/L) */
|
||||
# define PMC_LVDSC2_LVWV_MID1 (1 << PMC_LVDSC2_LVWV_SHIFT) /* Mid 1 trip point selected (VLVW = VLVW2H/L) */
|
||||
# define PMC_LVDSC2_LVWV_MID2 (2 << PMC_LVDSC2_LVWV_SHIFT) /* Mid 2 trip point selected (VLVW = VLVW3H/L) */
|
||||
# define PMC_LVDSC2_LVWV_HIGH (3 << PMC_LVDSC2_LVWV_SHIFT) /* High trip point selected (VLVW = VLVW4H/L) */
|
||||
/* Bits 2-4: Reserved */
|
||||
#define PMC_LVDSC2_LVWIE (1 << 5) /* Bit 5: Low-Voltage Warning Interrupt Enable */
|
||||
#define PMC_LVDSC2_LVWACK (1 << 6) /* Bit 6: Low-Voltage Warning Acknowledge */
|
||||
#define PMC_LVDSC2_LVWF (1 << 7) /* Bit 7: Low-Voltage Warning Flag */
|
||||
|
||||
/* Regulator Status and Control Register */
|
||||
|
||||
#define PMC_REGSC_BGBE (1 << 0) /* Bit 0: Bandgap Buffer Enable */
|
||||
/* Bit 1: Reserved */
|
||||
#define PMC_REGSC_REGONS (1 << 2) /* Bit 2: Regulator in Run Regulation Status */
|
||||
#define PMC_REGSC_VLPRS (1 << 3) /* Bit 3: Very Low Power Run Status */
|
||||
#define PMC_REGSC_TRAMPO (1 << 4) /* Bit 4: For devices with FlexNVM: Traditional RAM Power Option */
|
||||
#if defined(KINETIS_PMC_HAS_REGSC_REGONS)
|
||||
# define PMC_REGSC_REGONS (1 << 2) /* Bit 2: Regulator in Run Regulation Status */
|
||||
#endif
|
||||
#if defined(KINETIS_PMC_HAS_REGSC_ACKISO)
|
||||
# define PMC_REGSC_ACKISO (1 << 3) /* Bit 3: Acknowledge Isolation */
|
||||
#endif
|
||||
#if defined(KINETIS_PMC_HAS_REGSC_VLPRS)
|
||||
# define PMC_REGSC_VLPRS (1 << 3) /* Bit 3: Very Low Power Run Status */
|
||||
#endif
|
||||
#if defined(KINETIS_PMC_HAS_REGSC_BGEN)
|
||||
# define PMC_REGSC_BGEN (1 << 4) /* Bit 4: Bandgap Enable In VLPx Operation */
|
||||
#endif
|
||||
#if defined(KINETIS_PMC_HAS_REGSC_TRAMPO)
|
||||
# define PMC_REGSC_TRAMPO (1 << 4) /* Bit 4: For devices with FlexNVM: Traditional RAM Power Option */
|
||||
#endif
|
||||
/* Bits 5-7: Reserved */
|
||||
|
||||
/************************************************************************************
|
||||
|
||||
+1188
-447
File diff suppressed because it is too large
Load Diff
@@ -45,6 +45,7 @@
|
||||
#include "chip/kinetis_mcg.h"
|
||||
#include "chip/kinetis_sim.h"
|
||||
#include "chip/kinetis_fmc.h"
|
||||
#include "chip/kinetis_pmc.h"
|
||||
#include "chip/kinetis_llwu.h"
|
||||
#include "chip/kinetis_pinmux.h"
|
||||
|
||||
@@ -191,7 +192,9 @@ static inline void kinesis_portclocks(void)
|
||||
|
||||
void kinetis_pllconfig(void)
|
||||
{
|
||||
#if defined(SIM_SCGC4_LLWU)
|
||||
uint32_t regval32;
|
||||
#endif
|
||||
uint8_t regval8;
|
||||
|
||||
#if defined(BOARD_MCG_C2)
|
||||
@@ -228,16 +231,25 @@ void kinetis_pllconfig(void)
|
||||
MCG_C2_RANGE_VHIGH | MCG_C2_EREFS, KINETIS_MCG_C2);
|
||||
# endif
|
||||
#endif /* defined(BOARD_MCG_C2) */
|
||||
|
||||
#if defined(SIM_SCGC4_LLWU)
|
||||
/* Released latched state of oscillator and GPIO */
|
||||
|
||||
regval32 = getreg32(KINETIS_SIM_SCGC4);
|
||||
regval32 |= SIM_SCGC4_LLWU;
|
||||
putreg32(regval32, KINETIS_SIM_SCGC4);
|
||||
#endif
|
||||
|
||||
#if defined(LLWU_CS_ACKISO)
|
||||
regval8 = getreg8(KINETIS_LLWU_CS);
|
||||
regval8 |= LLWU_CS_ACKISO;
|
||||
putreg8(regval8, KINETIS_LLWU_CS);
|
||||
#endif
|
||||
|
||||
#if defined(PMC_REGSC_ACKISO)
|
||||
regval8 = getreg8(KINETIS_PMC_REGSC);
|
||||
regval8 |= PMC_REGSC_ACKISO;
|
||||
putreg8(regval8, KINETIS_PMC_REGSC);
|
||||
#endif
|
||||
|
||||
/* Select external oscillator and Reference Divider and clear IREFS to
|
||||
* start the external oscillator.
|
||||
|
||||
@@ -2010,6 +2010,11 @@ static void kinetis_reset(struct kinetis_driver_s *priv)
|
||||
int kinetis_netinitialize(int intf)
|
||||
{
|
||||
struct kinetis_driver_s *priv;
|
||||
#ifdef CONFIG_NET_ETHERNET
|
||||
uint32_t uidl;
|
||||
uint32_t uidml;
|
||||
uint8_t *mac;
|
||||
#endif
|
||||
uint32_t regval;
|
||||
|
||||
/* Get the interface structure associated with this interface number. */
|
||||
@@ -2157,9 +2162,9 @@ int kinetis_netinitialize(int intf)
|
||||
* 1st octet)
|
||||
*/
|
||||
|
||||
uint32_t uidl = getreg32(KINETIS_SIM_UIDL);
|
||||
uint32_t uidml = getreg32(KINETIS_SIM_UIDML);
|
||||
uint8_t *mac = priv->dev.d_mac.ether_addr_octet;
|
||||
uidl = getreg32(KINETIS_SIM_UIDL);
|
||||
uidml = getreg32(KINETIS_SIM_UIDML);
|
||||
mac = priv->dev.d_mac.ether_addr_octet;
|
||||
|
||||
uidml |= 0x00000200;
|
||||
uidml &= 0x0000FEFF;
|
||||
|
||||
@@ -4396,10 +4396,11 @@ void up_usbinitialize(void)
|
||||
* easier.
|
||||
*/
|
||||
#if 1
|
||||
#warning "This code needs to be driven by BOARD_ settings and SIM_SOPT2[PLLFLLSE] needs to be set globally"
|
||||
/* 1: Select clock source */
|
||||
|
||||
regval = getreg32(KINETIS_SIM_SOPT2);
|
||||
regval |= SIM_SOPT2_PLLFLLSEL | SIM_SOPT2_USBSRC;
|
||||
regval |= SIM_SOPT2_PLLFLLSEL_MCGPLLCLK | SIM_SOPT2_USBSRC;
|
||||
putreg32(regval, KINETIS_SIM_SOPT2);
|
||||
|
||||
regval = getreg32(KINETIS_SIM_CLKDIV2);
|
||||
|
||||
@@ -1,7 +1,7 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/stm32f7/up_allocateheap.c
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2015, 2017 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@@ -57,10 +57,12 @@
|
||||
#include "up_arch.h"
|
||||
#include "up_internal.h"
|
||||
#include "stm32_mpuinit.h"
|
||||
#include "stm32_dtcm.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Internal SRAM is available in all members of the STM32 family. The
|
||||
* following definitions must be provided to specify the size and
|
||||
* location of internal(system) SRAM:
|
||||
@@ -92,6 +94,20 @@
|
||||
#define SRAM2_START STM32_SRAM2_BASE
|
||||
#define SRAM2_END (SRAM2_START + STM32F7_SRAM2_SIZE)
|
||||
|
||||
/* The STM32 F7 has DTCM memory */
|
||||
|
||||
#undef HAVE_DTCM
|
||||
#define HAVE_DTCM 1
|
||||
#if !defined(DTCM_START) || !defined(DTCM_END)
|
||||
# undef HAVE_DTCM
|
||||
#endif
|
||||
|
||||
/* DTCM to be excluded from the main heap. */
|
||||
|
||||
#ifdef CONFIG_STM32F7_DTCMEXCLUDE
|
||||
# undef HAVE_DTCM
|
||||
#endif
|
||||
|
||||
/* We can't possibly have FSMC SRAM if the FSMC is not enabled */
|
||||
|
||||
#ifndef CONFIG_STM32F7_FSMC
|
||||
@@ -110,7 +126,7 @@
|
||||
# endif
|
||||
#endif
|
||||
|
||||
/* There are 3 possible heap configurations:
|
||||
/* There are 4 possible heap configurations:
|
||||
*
|
||||
* Configuration 1. System SRAM1 (only)
|
||||
* CONFIG_MM_REGIONS == 1
|
||||
@@ -118,9 +134,18 @@
|
||||
* Configuration 2. System SRAM1 and SRAM2
|
||||
* CONFIG_MM_REGIONS == 2
|
||||
* CONFIG_STM32F7_FSMC_SRAM NOT defined
|
||||
* Configuration 3. System SRAM1 and SRAM2 and FSMC SRAM
|
||||
* Configuration 3. System SRAM1 and SRAM2 and DTCM
|
||||
* CONFIG_MM_REGIONS == 3
|
||||
* CONFIG_STM32F7_FSMC_SRAM undefined
|
||||
* HAVE_DTCM defined
|
||||
* Configuration 4. System SRAM1 and SRAM2 and FSMC SRAM
|
||||
* CONFIG_MM_REGIONS == 3
|
||||
* CONFIG_STM32F7_FSMC_SRAM defined
|
||||
* HAVE_DTCM undefined
|
||||
* Configuration 5. System SRAM1 and SRAM2 and DTCM and FSMC SRAM
|
||||
* CONFIG_MM_REGIONS == 4
|
||||
* CONFIG_STM32F7_FSMC_SRAM defined
|
||||
* HAVE_DTCM defined
|
||||
*
|
||||
* Let's make sure that all definitions are consistent before doing
|
||||
* anything else
|
||||
@@ -128,24 +153,48 @@
|
||||
|
||||
#if CONFIG_MM_REGIONS < 2
|
||||
# ifdef CONFIG_STM32F7_FSMC_SRAM
|
||||
# warning FSMC SRAM and SRAM2 excluded from the heap
|
||||
# else
|
||||
# warning "SRAM2 excluded from the heap"
|
||||
# warning "FSMC SRAM excluded from the heap"
|
||||
# undef CONFIG_STM32F7_FSMC_SRAM
|
||||
# endif
|
||||
# ifdef HAVE_DTCM
|
||||
# warning "DTCM excluded from the heap"
|
||||
# undef HAVE_DTCM
|
||||
# endif
|
||||
# warning "SRAM2 excluded from the heap"
|
||||
#elif CONFIG_MM_REGIONS < 3
|
||||
# ifdef CONFIG_STM32F7_FSMC_SRAM
|
||||
# warning FSMC SRAM excluded from the heap
|
||||
# warning "FSMC SRAM excluded from the heap"
|
||||
# undef CONFIG_STM32F7_FSMC_SRAM
|
||||
# endif
|
||||
# ifdef HAVE_DTCM
|
||||
# warning "DTCM excluded from the heap"
|
||||
# undef HAVE_DTCM
|
||||
# endif
|
||||
#elif CONFIG_MM_REGIONS < 4
|
||||
# ifndef CONFIG_STM32F7_FSMC_SRAM
|
||||
# error CONFIG_MM_REGIONS > 2 but I do not know what some of the region(s) are
|
||||
# if defined(CONFIG_STM32F7_FSMC_SRAM) && defined(HAVE_DTCM)
|
||||
# warning "CONFIG_MM_REGIONS == 3 but have both FSMC SRAM and DTCM. DTCM excluded from the heap."
|
||||
# undef HAVE_DTCM
|
||||
# elif !defined(CONFIG_STM32F7_FSMC_SRAM) && !defined(HAVE_DTCM)
|
||||
# error "CONFIG_MM_REGIONS == 3 but I do not know what some of the region(s) are"
|
||||
# undef CONFIG_MM_REGIONS
|
||||
# define CONFIG_MM_REGIONS 2
|
||||
# endif
|
||||
#elif CONFIG_MM_REGIONS < 5
|
||||
# if !defined(CONFIG_STM32F7_FSMC_SRAM) && !defined(HAVE_DTCM)
|
||||
# error "CONFIG_MM_REGIONS == 4 but I do not know what some of the region(s) are"
|
||||
# undef CONFIG_MM_REGIONS
|
||||
# define CONFIG_MM_REGIONS 2
|
||||
# elif !defined(CONFIG_STM32F7_FSMC_SRAM) || !defined(HAVE_DTCM)
|
||||
# error "CONFIG_MM_REGIONS == 4 but I do not know what some of the region(s) are"
|
||||
# undef CONFIG_MM_REGIONS
|
||||
# define CONFIG_MM_REGIONS 3
|
||||
# endif
|
||||
#else
|
||||
# error CONFIG_MM_REGIONS > 3 but I do not know what some of the region(s) are
|
||||
# error "CONFIG_MM_REGIONS > 4 but I do not know what some of the region(s) are"
|
||||
# undef CONFIG_MM_REGIONS
|
||||
# ifdef CONFIG_STM32F7_FSMC_SRAM
|
||||
# if defined(CONFIG_STM32F7_FSMC_SRAM) && defined(HAVE_DTCM)
|
||||
# define CONFIG_MM_REGIONS 4
|
||||
# elif defined(CONFIG_STM32F7_FSMC_SRAM) || defined(HAVE_DTCM)
|
||||
# define CONFIG_MM_REGIONS 3
|
||||
# else
|
||||
# define CONFIG_MM_REGIONS 2
|
||||
@@ -338,6 +387,24 @@ void up_addregion(void)
|
||||
|
||||
kumm_addregion((FAR void *)SRAM2_START, SRAM2_END-SRAM2_START);
|
||||
|
||||
#ifdef HAVE_DTCM
|
||||
#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
|
||||
|
||||
/* Allow user-mode access to the DTCM heap */
|
||||
|
||||
stm32_mpu_uheap((uintptr_t)DTCM_START, DTCM_END-DTCM_START);
|
||||
|
||||
#endif
|
||||
|
||||
/* Colorize the heap for debug */
|
||||
|
||||
up_heap_color((FAR void *)DTCM_START, DTCM_END-DTCM_START);
|
||||
|
||||
/* Add the DTCM user heap region. */
|
||||
|
||||
kumm_addregion((FAR void *)DTCM_START, DTCM_END-DTCM_START);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F7_FSMC_SRAM
|
||||
#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
|
||||
|
||||
|
||||
@@ -69,19 +69,11 @@
|
||||
# define COMP_CSR_INMSEL_VREF (3 << COMP_CSR_INMSEL_SHIFT) /* VREFINT */
|
||||
# define COMP_CSR_INMSEL_DAC1 (4 << COMP_CSR_INMSEL_SHIFT) /* DAC Channel1 */
|
||||
# define COMP_CSR_INMSEL_DAC2 (5 << COMP_CSR_INMSEL_SHIFT) /* DAC Channel2 */
|
||||
# define COMP_CSR_INMSEL_PIN1 (6 << COMP_CSR_INMSEL_SHIFT) /* Input minus pin 1 */
|
||||
# define COMP_CSR_INMSEL_PIN2 (7 << COMP_CSR_INMSEL_SHIFT) /* Input minus pin 2 */
|
||||
# define COMP1_CSR_INMSEL_PB1 (6 << COMP_CSR_INMSEL_SHIFT) /* PB1 */
|
||||
# define COMP1_CSR_INMSEL_PC4 (7 << COMP_CSR_INMSEL_SHIFT) /* PC4 */
|
||||
# define COMP2_CSR_INMSEL_PB3 (6 << COMP_CSR_INMSEL_SHIFT) /* PB3 */
|
||||
# define COMP2_CSR_INMSEL_PB7 (7 << COMP_CSR_INMSEL_SHIFT) /* PB7 */
|
||||
# define COMP_CSR_INMSEL_PIN1 (6 << COMP_CSR_INMSEL_SHIFT) /* Input minus pin 1: COMP1=PB1; COMP2=PB3 */
|
||||
# define COMP_CSR_INMSEL_PIN2 (7 << COMP_CSR_INMSEL_SHIFT) /* Input minus pin 2: COMP1=PC4; COMP2=PB7 */
|
||||
#define COMP_CSR_INPSEL_MASK (1 << 7) /* Bit 7: Input plus selection bit */
|
||||
# define COMP1_CSR_INPSEL_PIN1 (0)
|
||||
# define COMP1_CSR_INPSEL_PIN2 COMP_CSR_INPSEL_MASK
|
||||
# define COMP1_CSR_INPSEL_PC5 (0)
|
||||
# define COMP1_CSR_INPSEL_PB2 COMP_CSR_INPSEL_MASK
|
||||
# define COMP2_CSR_INPSEL_PB4 (0)
|
||||
# define COMP2_CSR_INPSEL_PB6 COMP_CSR_INPSEL_MASK
|
||||
# define COMP_CSR_INPSEL_PIN1 (0) /* Input plus pin 1: COMP1=PC5; COMP2=PB4 */
|
||||
# define COMP_CSR_INPSEL_PIN2 COMP_CSR_INPSEL_MASK /* Input plus pin 1: COMP1=PB2; COMP2=PB6 */
|
||||
#define COMP2_CSR_WINMODE (1 << 9) /* Bit 9: Windows mode selection bit (COMP2 only) */
|
||||
# define COMP2_CSR_WINMODE_NOCONN (0) /* Comparator 2 input not connected to Comparator 1 */
|
||||
# define COMP2_CSR_WINMODE_CONN COMP2_CSR_WINMODE /* Comparator 2 input connected to Comparator 1 */
|
||||
|
||||
@@ -107,18 +107,18 @@ int stm32l4_compconfig(int cmp, const struct stm32l4_comp_config_s *cfg)
|
||||
{
|
||||
case STM32L4_COMP_INP_PIN_1:
|
||||
stm32l4_configgpio(cmp == STM32L4_COMP1 ? GPIO_COMP1_INP_1 : GPIO_COMP2_INP_1);
|
||||
regval |= COMP1_CSR_INPSEL_PIN1;
|
||||
regval |= COMP_CSR_INPSEL_PIN1;
|
||||
break;
|
||||
|
||||
case STM32L4_COMP_INP_PIN_2:
|
||||
stm32l4_configgpio(cmp == STM32L4_COMP1 ? GPIO_COMP1_INP_2 : GPIO_COMP2_INP_2);
|
||||
regval |= COMP1_CSR_INPSEL_PIN2;
|
||||
regval |= COMP_CSR_INPSEL_PIN2;
|
||||
break;
|
||||
|
||||
#if defined(CONFIG_STM32L4_STM32L4X3)
|
||||
case STM32L4_COMP_INP_PIN_3:
|
||||
stm32l4_configgpio(cmp == STM32L4_COMP1 ? GPIO_COMP1_INP_3 : GPIO_COMP2_INP_3);
|
||||
regval |= COMP1_CSR_INPSEL_PIN3;
|
||||
regval |= COMP_CSR_INPSEL_PIN3;
|
||||
break;
|
||||
#endif
|
||||
|
||||
|
||||
@@ -852,7 +852,6 @@ CONFIG_LIBM=y
|
||||
# CONFIG_LIBC_ARCH_STRNCPY is not set
|
||||
# CONFIG_LIBC_ARCH_STRLEN is not set
|
||||
# CONFIG_LIBC_ARCH_STRNLEN is not set
|
||||
# CONFIG_LIBC_ARCH_BZERO is not set
|
||||
# CONFIG_LIBC_ARCH_ELF is not set
|
||||
# CONFIG_ARMV7M_MEMCPY is not set
|
||||
# CONFIG_NOPRINTF_FIELDWIDTH is not set
|
||||
|
||||
@@ -726,7 +726,6 @@ CONFIG_LIB_HOMEDIR="/"
|
||||
# CONFIG_LIBC_ARCH_STRNCPY is not set
|
||||
# CONFIG_LIBC_ARCH_STRLEN is not set
|
||||
# CONFIG_LIBC_ARCH_STRNLEN is not set
|
||||
# CONFIG_LIBC_ARCH_BZERO is not set
|
||||
# CONFIG_LIBC_ARCH_ELF is not set
|
||||
# CONFIG_ARMV7M_MEMCPY is not set
|
||||
# CONFIG_NOPRINTF_FIELDWIDTH is not set
|
||||
|
||||
@@ -1176,7 +1176,6 @@ CONFIG_LIB_HOMEDIR="/"
|
||||
# CONFIG_LIBC_ARCH_STRNCPY is not set
|
||||
# CONFIG_LIBC_ARCH_STRLEN is not set
|
||||
# CONFIG_LIBC_ARCH_STRNLEN is not set
|
||||
# CONFIG_LIBC_ARCH_BZERO is not set
|
||||
# CONFIG_LIBC_ARCH_ELF is not set
|
||||
# CONFIG_ARMV7M_MEMCPY is not set
|
||||
# CONFIG_NOPRINTF_FIELDWIDTH is not set
|
||||
|
||||
@@ -709,7 +709,6 @@ CONFIG_NUNGET_CHARS=2
|
||||
# CONFIG_LIBC_ARCH_STRNCPY is not set
|
||||
# CONFIG_LIBC_ARCH_STRLEN is not set
|
||||
# CONFIG_LIBC_ARCH_STRNLEN is not set
|
||||
# CONFIG_LIBC_ARCH_BZERO is not set
|
||||
# CONFIG_LIBC_ARCH_ELF is not set
|
||||
# CONFIG_ARMV7M_MEMCPY is not set
|
||||
# CONFIG_NOPRINTF_FIELDWIDTH is not set
|
||||
|
||||
@@ -916,7 +916,6 @@ CONFIG_ARCH_LOWPUTC=y
|
||||
# CONFIG_LIBC_ARCH_STRNCPY is not set
|
||||
# CONFIG_LIBC_ARCH_STRLEN is not set
|
||||
# CONFIG_LIBC_ARCH_STRNLEN is not set
|
||||
# CONFIG_LIBC_ARCH_BZERO is not set
|
||||
# CONFIG_LIBC_ARCH_ELF is not set
|
||||
# CONFIG_ARMV7M_MEMCPY is not set
|
||||
|
||||
|
||||
@@ -802,7 +802,6 @@ CONFIG_ARCH_LOWPUTC=y
|
||||
# CONFIG_LIBC_ARCH_STRNCPY is not set
|
||||
# CONFIG_LIBC_ARCH_STRLEN is not set
|
||||
# CONFIG_LIBC_ARCH_STRNLEN is not set
|
||||
# CONFIG_LIBC_ARCH_BZERO is not set
|
||||
# CONFIG_LIBC_ARCH_ELF is not set
|
||||
# CONFIG_ARMV7M_MEMCPY is not set
|
||||
|
||||
|
||||
@@ -923,7 +923,6 @@ CONFIG_LIB_HOMEDIR="/"
|
||||
# CONFIG_LIBC_ARCH_STRNCPY is not set
|
||||
# CONFIG_LIBC_ARCH_STRLEN is not set
|
||||
# CONFIG_LIBC_ARCH_STRNLEN is not set
|
||||
# CONFIG_LIBC_ARCH_BZERO is not set
|
||||
# CONFIG_LIBC_ARCH_ELF is not set
|
||||
# CONFIG_ARMV7M_MEMCPY is not set
|
||||
# CONFIG_NOPRINTF_FIELDWIDTH is not set
|
||||
|
||||
@@ -1139,7 +1139,6 @@ CONFIG_LIB_HOMEDIR="/"
|
||||
# CONFIG_LIBC_ARCH_STRNCPY is not set
|
||||
# CONFIG_LIBC_ARCH_STRLEN is not set
|
||||
# CONFIG_LIBC_ARCH_STRNLEN is not set
|
||||
# CONFIG_LIBC_ARCH_BZERO is not set
|
||||
# CONFIG_LIBC_ARCH_ELF is not set
|
||||
# CONFIG_ARMV7M_MEMCPY is not set
|
||||
# CONFIG_NOPRINTF_FIELDWIDTH is not set
|
||||
|
||||
@@ -976,7 +976,6 @@ CONFIG_LIB_HOMEDIR="/"
|
||||
# CONFIG_LIBC_ARCH_STRNCPY is not set
|
||||
# CONFIG_LIBC_ARCH_STRLEN is not set
|
||||
# CONFIG_LIBC_ARCH_STRNLEN is not set
|
||||
# CONFIG_LIBC_ARCH_BZERO is not set
|
||||
# CONFIG_LIBC_ARCH_ELF is not set
|
||||
# CONFIG_ARMV7M_MEMCPY is not set
|
||||
# CONFIG_NOPRINTF_FIELDWIDTH is not set
|
||||
|
||||
@@ -747,7 +747,7 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
|
||||
# Memory Management
|
||||
#
|
||||
# CONFIG_MM_SMALL is not set
|
||||
CONFIG_MM_REGIONS=2
|
||||
CONFIG_MM_REGIONS=3
|
||||
# CONFIG_ARCH_HAVE_HEAP2 is not set
|
||||
# CONFIG_GRAN is not set
|
||||
|
||||
|
||||
@@ -734,7 +734,7 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
|
||||
# Memory Management
|
||||
#
|
||||
# CONFIG_MM_SMALL is not set
|
||||
CONFIG_MM_REGIONS=2
|
||||
CONFIG_MM_REGIONS=3
|
||||
# CONFIG_ARCH_HAVE_HEAP2 is not set
|
||||
# CONFIG_GRAN is not set
|
||||
|
||||
|
||||
@@ -760,7 +760,6 @@ CONFIG_ARCH_LOWPUTC=y
|
||||
# CONFIG_LIBC_ARCH_STRNCPY is not set
|
||||
# CONFIG_LIBC_ARCH_STRLEN is not set
|
||||
# CONFIG_LIBC_ARCH_STRNLEN is not set
|
||||
# CONFIG_LIBC_ARCH_BZERO is not set
|
||||
# CONFIG_LIBC_ARCH_ELF is not set
|
||||
# CONFIG_ARMV7M_MEMCPY is not set
|
||||
|
||||
|
||||
@@ -235,6 +235,11 @@
|
||||
#define GPIO_USART3_CTS GPIO_USART3_CTS_2 /* PD11 */
|
||||
#define GPIO_USART3_RTS GPIO_USART3_RTS_2 /* PD12 */
|
||||
|
||||
/* USART6: */
|
||||
|
||||
#define GPIO_USART6_RX GPIO_USART6_RX_2 /* PG9 */
|
||||
#define GPIO_USART6_TX GPIO_USART6_TX_1 /* PC6 */
|
||||
|
||||
/* CAN: */
|
||||
|
||||
#define GPIO_CAN1_RX GPIO_CAN1_RX_2 /* PB8 */
|
||||
|
||||
@@ -944,7 +944,6 @@ CONFIG_LIB_HOMEDIR="/"
|
||||
# CONFIG_LIBC_ARCH_STRNCPY is not set
|
||||
# CONFIG_LIBC_ARCH_STRLEN is not set
|
||||
# CONFIG_LIBC_ARCH_STRNLEN is not set
|
||||
# CONFIG_LIBC_ARCH_BZERO is not set
|
||||
# CONFIG_LIBC_ARCH_ELF is not set
|
||||
# CONFIG_ARMV7M_MEMCPY is not set
|
||||
# CONFIG_NOPRINTF_FIELDWIDTH is not set
|
||||
|
||||
@@ -937,7 +937,6 @@ CONFIG_LIB_HOMEDIR="/"
|
||||
# CONFIG_LIBC_ARCH_STRNCPY is not set
|
||||
# CONFIG_LIBC_ARCH_STRLEN is not set
|
||||
# CONFIG_LIBC_ARCH_STRNLEN is not set
|
||||
# CONFIG_LIBC_ARCH_BZERO is not set
|
||||
# CONFIG_LIBC_ARCH_ELF is not set
|
||||
# CONFIG_ARMV7M_MEMCPY is not set
|
||||
# CONFIG_NOPRINTF_FIELDWIDTH is not set
|
||||
|
||||
@@ -48,6 +48,11 @@ ifeq ($(CONFIG_ARCH_BUTTONS),y)
|
||||
CSRCS += stm32_buttons.c
|
||||
endif
|
||||
|
||||
|
||||
ifeq ($(CONFIG_STM32_FSMC),y)
|
||||
CSRCS += stm32_sram.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_STM32_OTGFS),y)
|
||||
CSRCS += stm32_usb.c
|
||||
endif
|
||||
|
||||
@@ -190,6 +190,36 @@
|
||||
|
||||
int stm32_bringup(void);
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_stram_configure
|
||||
*
|
||||
* Description:
|
||||
* Initialize to access external SRAM. SRAM will be visible at the FSMC Bank
|
||||
* NOR/SRAM2 base address (0x64000000)
|
||||
*
|
||||
* General transaction rules. The requested AHB transaction data size can be 8-,
|
||||
* 16- or 32-bit wide whereas the SRAM has a fixed 16-bit data width. Some simple
|
||||
* transaction rules must be followed:
|
||||
*
|
||||
* Case 1: AHB transaction width and SRAM data width are equal
|
||||
* There is no issue in this case.
|
||||
* Case 2: AHB transaction size is greater than the memory size
|
||||
* In this case, the FSMC splits the AHB transaction into smaller consecutive
|
||||
* memory accesses in order to meet the external data width.
|
||||
* Case 3: AHB transaction size is smaller than the memory size.
|
||||
* SRAM supports the byte select feature.
|
||||
* a) FSMC allows write transactions accessing the right data through its
|
||||
* byte lanes (NBL[1:0])
|
||||
* b) Read transactions are allowed (the controller reads the entire memory
|
||||
* word and uses the needed byte only). The NBL[1:0] are always kept low
|
||||
* during read transactions.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifdef CONFIG_STM32_FSMC
|
||||
void stm32_stram_configure(void);
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_usb_configure
|
||||
*
|
||||
|
||||
@@ -63,6 +63,12 @@
|
||||
|
||||
void stm32_boardinitialize(void)
|
||||
{
|
||||
#ifdef CONFIG_STM32_FSMC
|
||||
/* If the FSMC is enabled, then enable SRAM access */
|
||||
|
||||
stm32_stram_configure();
|
||||
#endif
|
||||
|
||||
/* Initialize USB if the 1) OTG FS controller is in the configuration and 2)
|
||||
* disabled, and 3) the weak function stm32_usb_configure() has been brought
|
||||
* into the build. Presumeably either CONFIG_USBDEV or CONFIG_USBHOST is also
|
||||
|
||||
@@ -0,0 +1,262 @@
|
||||
/************************************************************************************
|
||||
* configs/olimex-stm32-p407/src/stm32_sram.c
|
||||
*
|
||||
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <debug.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "up_arch.h"
|
||||
|
||||
#include "stm32.h"
|
||||
#include "stm3240g-eval.h"
|
||||
|
||||
#ifdef CONFIG_STM32_FSMC
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
#if STM32_NGPIO_PORTS < 6
|
||||
# error "Required GPIO ports not enabled"
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_USART3) || defined(CONFIG_STM32_USART6)
|
||||
# error "USART3 and USART6 conflict with use of SRAM"
|
||||
#endif
|
||||
|
||||
/* SRAM Timing
|
||||
* REVIST: These were ported from the STM3240G-EVAL and have not been verified on
|
||||
* this platform.
|
||||
*/
|
||||
|
||||
#define SRAM_ADDRESS_SETUP_TIME 3
|
||||
#define SRAM_ADDRESS_HOLD_TIME 0
|
||||
#define SRAM_DATA_SETUP_TIME 6
|
||||
#define SRAM_BUS_TURNAROUND_DURATION 1
|
||||
#define SRAM_CLK_DIVISION 0
|
||||
#define SRAM_DATA_LATENCY 0
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Private Data
|
||||
************************************************************************************/
|
||||
|
||||
/* GPIOs Configuration **************************************************************
|
||||
*---------------------+------------------+------------------+-----------------+
|
||||
* GPIO FSMC NOTE |GPIO FSMC NOTE|GPIO FSMC NOTE|GPIO FSMC NOTE|
|
||||
*---------------------+------------------+------------------+-----------------+
|
||||
* PD0 FSMC_D2 |PE0 FSMC_NBL0 |PF0 FSMC_A0 |PG0 FSMC_A10 |
|
||||
* PD1 FSMC_D3 |PE1 FSMC_NBL1 |PF1 FSMC_A1 |PG1 FSMC_A11 |
|
||||
* | |PF2 FSMC_A2 |PG2 FSMC_A12 |
|
||||
* | |PF3 FSMC_A3 |PG3 FSMC_A13 |
|
||||
* PD4 FSMC_NOE 2 | |PF4 FSMC_A4 |PG4 FSMC_A14 |
|
||||
* PD5 FSMC_NWE | |PF5 FSMC_A5 |PG5 FSMC_A15 |
|
||||
* | | | |
|
||||
* PD7 FSMC_NE1/NCE2 |PE7 FSMC_D4 | | |
|
||||
* PD8 FSMC_D13 1 |PE8 FSMC_D5 | | |
|
||||
* PD9 FSMC_D14 1 |PE9 FSMC_D6 | | |
|
||||
* PD10 FSMC_D15 1 |PE10 FSMC_D7 | | |
|
||||
* PD11 FSMC_A16 1 |PE11 FSMC_D8 | | |
|
||||
* PD12 FSMC_A17 |PE12 FSMC_D9 |PF12 FSMC_A6 | |
|
||||
* |PE13 FSMC_D10 |PF13 FSMC_A7 | |
|
||||
* PD14 FSMC_D0 |PE14 FSMC_D11 |PF14 FSMC_A8 | |
|
||||
* PD15 FSMC_D1 |PE15 FSMC_D12 |PF15 FSMC_A9 | |
|
||||
*---------------------+------------------+------------------+-----------------+
|
||||
*
|
||||
* NOTES:
|
||||
* (1) Shared with USART3: PD8=USART3_TX PD9=USART3_RX PD11=USART3_CTS
|
||||
* PD12=USART3_RTS
|
||||
* (2) Shared with USB: PD4=USB_HS_FAULT
|
||||
*/
|
||||
|
||||
/* SRAM GPIO configuration */
|
||||
|
||||
static const uint32_t g_sramconfig[] =
|
||||
{
|
||||
/* Address configuration: FSMC_A0-FSMC_A17 */
|
||||
|
||||
GPIO_FSMC_A0, GPIO_FSMC_A1 , GPIO_FSMC_A2, GPIO_FSMC_A3, GPIO_FSMC_A4 , GPIO_FSMC_A5,
|
||||
GPIO_FSMC_A6, GPIO_FSMC_A7, GPIO_FSMC_A8, GPIO_FSMC_A9, GPIO_FSMC_A10, GPIO_FSMC_A11,
|
||||
GPIO_FSMC_A12, GPIO_FSMC_A13, GPIO_FSMC_A14, GPIO_FSMC_A15, GPIO_FSMC_A16, GPIO_FSMC_A17,
|
||||
|
||||
/* Data Configuration: FSMC_D0-FSMC_D15 */
|
||||
|
||||
GPIO_FSMC_D0, GPIO_FSMC_D1 , GPIO_FSMC_D2, GPIO_FSMC_D3, GPIO_FSMC_D4 , GPIO_FSMC_D5,
|
||||
GPIO_FSMC_D6, GPIO_FSMC_D7, GPIO_FSMC_D8, GPIO_FSMC_D9, GPIO_FSMC_D10, GPIO_FSMC_D11,
|
||||
GPIO_FSMC_D12, GPIO_FSMC_D13, GPIO_FSMC_D14, GPIO_FSMC_D15
|
||||
|
||||
/* Control Signals:
|
||||
*
|
||||
* /CS = PD7, FSMC_NE1
|
||||
* /OE = PD4, FSMC_NOE
|
||||
* /WE = PD5, FSMC_NWE
|
||||
* /BHE = PE0, FSMC_NBL0
|
||||
* /BHL = PE1, PSMC_NBL1
|
||||
*/
|
||||
|
||||
GPIO_FSMC_NE1, GPIO_FSMC_NOE, GPIO_FSMC_NWE, GPIO_FSMC_NBL0, GPIO_FSMC_NBL1
|
||||
};
|
||||
#define NSRAM_CONFIG (sizeof(g_sramconfig)/sizeof(uint32_t))
|
||||
|
||||
/************************************************************************************
|
||||
* Private Functions
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_enablefsmc
|
||||
*
|
||||
* Description:
|
||||
* Enable clocking to the FSMC module
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
static void stm32_enablefsmc(void)
|
||||
{
|
||||
uint32_t regval;
|
||||
|
||||
/* Enable AHB clocking to the FSMC */
|
||||
|
||||
regval = getreg32( STM32_RCC_AHB3ENR);
|
||||
regval |= RCC_AHB3ENR_FSMCEN;
|
||||
putreg32(regval, STM32_RCC_AHB3ENR);
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_sramgpios
|
||||
*
|
||||
* Description:
|
||||
* Configure SRAM GPIO pins
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
static void stm32_sramgpios(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
/* Configure SRAM GPIOs */
|
||||
|
||||
for (i = 0; i < NSRAM_CONFIG; i++)
|
||||
{
|
||||
stm32_configgpio(g_sramconfig[i]);
|
||||
}
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_stram_configure
|
||||
*
|
||||
* Description:
|
||||
* Initialize to access external SRAM. SRAM will be visible at the FSMC Bank
|
||||
* NOR/SRAM2 base address (0x64000000)
|
||||
*
|
||||
* General transaction rules. The requested AHB transaction data size can be 8-,
|
||||
* 16- or 32-bit wide whereas the SRAM has a fixed 16-bit data width. Some simple
|
||||
* transaction rules must be followed:
|
||||
*
|
||||
* Case 1: AHB transaction width and SRAM data width are equal
|
||||
* There is no issue in this case.
|
||||
* Case 2: AHB transaction size is greater than the memory size
|
||||
* In this case, the FSMC splits the AHB transaction into smaller consecutive
|
||||
* memory accesses in order to meet the external data width.
|
||||
* Case 3: AHB transaction size is smaller than the memory size.
|
||||
* SRAM supports the byte select feature.
|
||||
* a) FSMC allows write transactions accessing the right data through its
|
||||
* byte lanes (NBL[1:0])
|
||||
* b) Read transactions are allowed (the controller reads the entire memory
|
||||
* word and uses the needed byte only). The NBL[1:0] are always kept low
|
||||
* during read transactions.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
void stm32_stram_configure(void)
|
||||
{
|
||||
/* Configure GPIO pins */
|
||||
|
||||
stm32_extmemgpios(g_sramconfig, NSRAM_CONFIG); /* SRAM-specific control lines */
|
||||
|
||||
/* Enable AHB clocking to the FSMC */
|
||||
|
||||
stm32_enablefsmc();
|
||||
|
||||
/* Bank1 NOR/SRAM control register configuration
|
||||
*
|
||||
* Bank enable : Not yet
|
||||
* Data address mux : Disabled
|
||||
* Memory Type : PSRAM
|
||||
* Data bus width : 16-bits
|
||||
* Flash access : Disabled
|
||||
* Burst access mode : Disabled
|
||||
* Polarity : Low
|
||||
* Wrapped burst mode : Disabled
|
||||
* Write timing : Before state
|
||||
* Write enable : Yes
|
||||
* Wait signal : Disabled
|
||||
* Extended mode : Disabled
|
||||
* Asynchronous wait : Disabled
|
||||
* Write burst : Disabled
|
||||
*/
|
||||
|
||||
putreg32((FSMC_BCR_PSRAM | FSMC_BCR_MWID16 | FSMC_BCR_WREN), STM32_FSMC_BCR2);
|
||||
|
||||
/* Bank1 NOR/SRAM timing register configuration */
|
||||
|
||||
putreg32((FSMC_BTR_ADDSET(SRAM_ADDRESS_SETUP_TIME) | FSMC_BTR_ADDHLD(SRAM_ADDRESS_HOLD_TIME) |
|
||||
FSMC_BTR_DATAST(SRAM_DATA_SETUP_TIME) | FSMC_BTR_BUSTURN(SRAM_BUS_TURNAROUND_DURATION) |
|
||||
FSMC_BTR_CLKDIV(SRAM_CLK_DIVISION) | FSMC_BTR_DATLAT(SRAM_DATA_LATENCY) |
|
||||
FSMC_BTR_ACCMODA),
|
||||
STM32_FSMC_BTR2);
|
||||
|
||||
/* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */
|
||||
|
||||
putreg32(0xffffffff, STM32_FSMC_BWTR2); /* Extended mode not used */
|
||||
|
||||
/* Enable the bank */
|
||||
|
||||
putreg32((FSMC_BCR_MBKEN | FSMC_BCR_PSRAM | FSMC_BCR_MWID16 | FSMC_BCR_WREN), STM32_FSMC_BCR2);
|
||||
}
|
||||
|
||||
#endif /* CONFIG_STM32_FSMC */
|
||||
@@ -687,7 +687,6 @@ CONFIG_LIB_HOMEDIR="/"
|
||||
# CONFIG_LIBC_ARCH_STRNCPY is not set
|
||||
# CONFIG_LIBC_ARCH_STRLEN is not set
|
||||
# CONFIG_LIBC_ARCH_STRNLEN is not set
|
||||
# CONFIG_LIBC_ARCH_BZERO is not set
|
||||
# CONFIG_LIBC_ARCH_ELF is not set
|
||||
# CONFIG_ARMV7M_MEMCPY is not set
|
||||
# CONFIG_NOPRINTF_FIELDWIDTH is not set
|
||||
|
||||
@@ -684,7 +684,6 @@ CONFIG_LIB_HOMEDIR="/"
|
||||
# CONFIG_LIBC_ARCH_STRNCPY is not set
|
||||
# CONFIG_LIBC_ARCH_STRLEN is not set
|
||||
# CONFIG_LIBC_ARCH_STRNLEN is not set
|
||||
# CONFIG_LIBC_ARCH_BZERO is not set
|
||||
# CONFIG_LIBC_ARCH_ELF is not set
|
||||
# CONFIG_ARMV7M_MEMCPY is not set
|
||||
# CONFIG_NOPRINTF_FIELDWIDTH is not set
|
||||
|
||||
@@ -831,7 +831,6 @@ CONFIG_NUNGET_CHARS=2
|
||||
# CONFIG_LIBC_ARCH_STRNCPY is not set
|
||||
# CONFIG_LIBC_ARCH_STRLEN is not set
|
||||
# CONFIG_LIBC_ARCH_STRNLEN is not set
|
||||
# CONFIG_LIBC_ARCH_BZERO is not set
|
||||
# CONFIG_LIBC_ARCH_ELF is not set
|
||||
# CONFIG_ARMV7M_MEMCPY is not set
|
||||
# CONFIG_NOPRINTF_FIELDWIDTH is not set
|
||||
|
||||
@@ -910,7 +910,6 @@ CONFIG_NUNGET_CHARS=2
|
||||
# CONFIG_LIBC_ARCH_STRNCPY is not set
|
||||
# CONFIG_LIBC_ARCH_STRLEN is not set
|
||||
# CONFIG_LIBC_ARCH_STRNLEN is not set
|
||||
# CONFIG_LIBC_ARCH_BZERO is not set
|
||||
# CONFIG_LIBC_ARCH_ELF is not set
|
||||
# CONFIG_ARMV7A_MEMCPY is not set
|
||||
# CONFIG_NOPRINTF_FIELDWIDTH is not set
|
||||
|
||||
@@ -859,7 +859,6 @@ CONFIG_NUNGET_CHARS=2
|
||||
# CONFIG_LIBC_ARCH_STRNCPY is not set
|
||||
# CONFIG_LIBC_ARCH_STRLEN is not set
|
||||
# CONFIG_LIBC_ARCH_STRNLEN is not set
|
||||
# CONFIG_LIBC_ARCH_BZERO is not set
|
||||
# CONFIG_LIBC_ARCH_ELF is not set
|
||||
# CONFIG_ARMV7A_MEMCPY is not set
|
||||
# CONFIG_NOPRINTF_FIELDWIDTH is not set
|
||||
|
||||
@@ -782,7 +782,6 @@ CONFIG_LIB_HOMEDIR="/"
|
||||
# CONFIG_LIBC_ARCH_STRNCPY is not set
|
||||
# CONFIG_LIBC_ARCH_STRLEN is not set
|
||||
# CONFIG_LIBC_ARCH_STRNLEN is not set
|
||||
# CONFIG_LIBC_ARCH_BZERO is not set
|
||||
CONFIG_LIBC_ARCH_ELF=y
|
||||
# CONFIG_ARMV7A_MEMCPY is not set
|
||||
# CONFIG_NOPRINTF_FIELDWIDTH is not set
|
||||
|
||||
@@ -1243,7 +1243,6 @@ CONFIG_LIB_HOMEDIR="/"
|
||||
# CONFIG_LIBC_ARCH_STRNCPY is not set
|
||||
# CONFIG_LIBC_ARCH_STRLEN is not set
|
||||
# CONFIG_LIBC_ARCH_STRNLEN is not set
|
||||
# CONFIG_LIBC_ARCH_BZERO is not set
|
||||
# CONFIG_LIBC_ARCH_ELF is not set
|
||||
# CONFIG_ARMV7A_MEMCPY is not set
|
||||
# CONFIG_NOPRINTF_FIELDWIDTH is not set
|
||||
|
||||
@@ -831,7 +831,6 @@ CONFIG_LIB_HOMEDIR="/"
|
||||
# CONFIG_LIBC_ARCH_STRNCPY is not set
|
||||
# CONFIG_LIBC_ARCH_STRLEN is not set
|
||||
# CONFIG_LIBC_ARCH_STRNLEN is not set
|
||||
# CONFIG_LIBC_ARCH_BZERO is not set
|
||||
CONFIG_LIBC_ARCH_ELF=y
|
||||
# CONFIG_ARMV7A_MEMCPY is not set
|
||||
# CONFIG_NOPRINTF_FIELDWIDTH is not set
|
||||
|
||||
@@ -1247,7 +1247,6 @@ CONFIG_LIB_HOMEDIR="/"
|
||||
# CONFIG_LIBC_ARCH_STRNCPY is not set
|
||||
# CONFIG_LIBC_ARCH_STRLEN is not set
|
||||
# CONFIG_LIBC_ARCH_STRNLEN is not set
|
||||
# CONFIG_LIBC_ARCH_BZERO is not set
|
||||
# CONFIG_LIBC_ARCH_ELF is not set
|
||||
# CONFIG_ARMV7A_MEMCPY is not set
|
||||
# CONFIG_NOPRINTF_FIELDWIDTH is not set
|
||||
|
||||
@@ -1239,7 +1239,6 @@ CONFIG_LIBM=y
|
||||
# CONFIG_LIBC_ARCH_STRNCPY is not set
|
||||
# CONFIG_LIBC_ARCH_STRLEN is not set
|
||||
# CONFIG_LIBC_ARCH_STRNLEN is not set
|
||||
# CONFIG_LIBC_ARCH_BZERO is not set
|
||||
# CONFIG_LIBC_ARCH_ELF is not set
|
||||
# CONFIG_ARMV7A_MEMCPY is not set
|
||||
# CONFIG_NOPRINTF_FIELDWIDTH is not set
|
||||
|
||||
@@ -986,7 +986,6 @@ CONFIG_LIB_HOMEDIR="/"
|
||||
# CONFIG_LIBC_ARCH_STRNCPY is not set
|
||||
# CONFIG_LIBC_ARCH_STRLEN is not set
|
||||
# CONFIG_LIBC_ARCH_STRNLEN is not set
|
||||
# CONFIG_LIBC_ARCH_BZERO is not set
|
||||
# CONFIG_LIBC_ARCH_ELF is not set
|
||||
# CONFIG_ARMV7M_MEMCPY is not set
|
||||
# CONFIG_NOPRINTF_FIELDWIDTH is not set
|
||||
|
||||
@@ -819,7 +819,6 @@ CONFIG_LIB_HOMEDIR="/"
|
||||
# CONFIG_LIBC_ARCH_STRNCPY is not set
|
||||
# CONFIG_LIBC_ARCH_STRLEN is not set
|
||||
# CONFIG_LIBC_ARCH_STRNLEN is not set
|
||||
# CONFIG_LIBC_ARCH_BZERO is not set
|
||||
# CONFIG_LIBC_ARCH_ELF is not set
|
||||
# CONFIG_ARMV7M_MEMCPY is not set
|
||||
# CONFIG_NOPRINTF_FIELDWIDTH is not set
|
||||
|
||||
@@ -829,7 +829,6 @@ CONFIG_LIB_HOMEDIR="/"
|
||||
# CONFIG_LIBC_ARCH_STRNCPY is not set
|
||||
# CONFIG_LIBC_ARCH_STRLEN is not set
|
||||
# CONFIG_LIBC_ARCH_STRNLEN is not set
|
||||
# CONFIG_LIBC_ARCH_BZERO is not set
|
||||
# CONFIG_LIBC_ARCH_ELF is not set
|
||||
# CONFIG_ARMV7M_MEMCPY is not set
|
||||
# CONFIG_NOPRINTF_FIELDWIDTH is not set
|
||||
|
||||
@@ -741,7 +741,6 @@ CONFIG_MODLIB_BUFFERINCR=32
|
||||
# CONFIG_LIBC_ARCH_STRNCPY is not set
|
||||
# CONFIG_LIBC_ARCH_STRLEN is not set
|
||||
# CONFIG_LIBC_ARCH_STRNLEN is not set
|
||||
# CONFIG_LIBC_ARCH_BZERO is not set
|
||||
CONFIG_LIBC_ARCH_ELF=y
|
||||
# CONFIG_ARMV7M_MEMCPY is not set
|
||||
# CONFIG_NOPRINTF_FIELDWIDTH is not set
|
||||
|
||||
@@ -950,7 +950,6 @@ CONFIG_LIB_HOMEDIR="/"
|
||||
# CONFIG_LIBC_ARCH_STRNCPY is not set
|
||||
# CONFIG_LIBC_ARCH_STRLEN is not set
|
||||
# CONFIG_LIBC_ARCH_STRNLEN is not set
|
||||
# CONFIG_LIBC_ARCH_BZERO is not set
|
||||
# CONFIG_LIBC_ARCH_ELF is not set
|
||||
# CONFIG_ARMV7M_MEMCPY is not set
|
||||
# CONFIG_NOPRINTF_FIELDWIDTH is not set
|
||||
|
||||
@@ -989,7 +989,6 @@ CONFIG_LIB_HOMEDIR="/"
|
||||
# CONFIG_LIBC_ARCH_STRNCPY is not set
|
||||
# CONFIG_LIBC_ARCH_STRLEN is not set
|
||||
# CONFIG_LIBC_ARCH_STRNLEN is not set
|
||||
# CONFIG_LIBC_ARCH_BZERO is not set
|
||||
# CONFIG_LIBC_ARCH_ELF is not set
|
||||
# CONFIG_ARMV7M_MEMCPY is not set
|
||||
# CONFIG_NOPRINTF_FIELDWIDTH is not set
|
||||
|
||||
@@ -822,7 +822,6 @@ CONFIG_LIB_HOMEDIR="/"
|
||||
# CONFIG_LIBC_ARCH_STRNCPY is not set
|
||||
# CONFIG_LIBC_ARCH_STRLEN is not set
|
||||
# CONFIG_LIBC_ARCH_STRNLEN is not set
|
||||
# CONFIG_LIBC_ARCH_BZERO is not set
|
||||
# CONFIG_LIBC_ARCH_ELF is not set
|
||||
# CONFIG_ARMV7M_MEMCPY is not set
|
||||
# CONFIG_NOPRINTF_FIELDWIDTH is not set
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user