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Merge branch 'master' into timerfixes
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@@ -129,7 +129,7 @@ irqstate_t enter_critical_section(void)
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/* We are in an interrupt handler. How can this happen?
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*
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* 1. We were not in a critical section when the interrupt
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* occurred. In this case:
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* occurred. In this case, the interrupt was entered with:
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*
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* g_cpu_irqlock = SP_UNLOCKED.
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* g_cpu_nestcount = 0
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@@ -152,6 +152,11 @@ irqstate_t enter_critical_section(void)
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* g_cpu_irqlock = SP_LOCKED.
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* g_cpu_nestcount > 0
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* The bit in g_cpu_irqset for this CPU hould be zero
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*
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* NOTE: However, the interrupt entry conditions can change due
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* to previous processing by the interrupt handler that may
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* instantiate a new thread that has irqcount > 0 and may then
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* set the bit in g_cpu_irqset and g_cpu_irqlock = SP_LOCKED
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*/
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/* Handle nested calls to enter_critical_section() from the same
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@@ -165,19 +170,29 @@ irqstate_t enter_critical_section(void)
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g_cpu_nestcount[cpu] < UINT8_MAX);
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g_cpu_nestcount[cpu]++;
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}
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/* This is the first call to enter_critical_section from the
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* interrupt handler.
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*/
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else
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{
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/* First call to enter_critical_section. Test assumptions, then
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* wait until we have the lock.
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/* Make sure that the g_cpu_irqlock() was not already set
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* by previous logic on this CPU that was executed by the
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* interrupt handler.
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*/
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DEBUGASSERT((g_cpu_irqset & (1 << cpu)) == 0);
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if ((g_cpu_irqset & (1 << cpu)) == 0)
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{
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/* Wait until we can get the spinlock (meaning that we are
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* no longer in the critical section).
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*/
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/* Wait until we can get the spinlock (meaning that we are no
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* longer in the critical section).
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*/
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spin_lock(&g_cpu_irqlock);
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}
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/* In any event, the nesting count is now one */
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spin_lock(&g_cpu_irqlock);
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g_cpu_nestcount[cpu] = 1;
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}
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}
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