Mirrors_Framework/nuttx
1
0
Fork 0
mirror of https://github.com/apache/nuttx.git synced 2026-06-06 16:50:55 +08:00
Code Issues Actions Packages Projects Releases Wiki Activity

Merged nuttx/nuttx into master

Browse Source
This commit is contained in:
Mateusz Szafoni
2016-06-27 09:31:55 +02:00
parent ae19ca45e0 b16fdaf155
commit d58bbeaca5
40 changed files with 1617 additions and 810 deletions
Download Patch File Download Diff File Expand all files Collapse all files
ChangeLog
+54
View File
@@ -12117,3 +12117,57 @@
(2016-06-21).
* drivers/syslog: Extend SYSLOG logic so that we can send SYSLOG output
to a file. Not verified on initial commit (2016-06-21).
* arch/arm/src/stm32l4: Add some CAN mode IOCTL calls. These will be
useful for device autotest when the application boots. They are
redundant with the CONFIG_CAN_LOOPBACK option, which can now just be
interpreted as a default setting. From Sebastien Lorquet (2016-06-22).
* drivers/syslog: syslog_dev_flush() needs to check if the inode is a
mountpoint before calling the flush() method. Noted by David Sidrane
(2016-06-22).
* arch/arm/src/stm32f7: Adds SDMMC1 for stm32F7 74-75. From Lok Tep
(2016-06-22).
* drivers/syslog: SYSLOG character device channel will now expand LF to
CR-LF. Controllable with a configuration option (2016-06-22).
* arch/arm/src/stm32l4: Implementation of loopback IOCTLs. From
Sebastien Lorquet (2016-06-22).
* Documentation: Add SYSLOG documentation to the porting guide
(2016-06-22).
* configs/stm32f746g-disco: Removed knsh configuration it failed to
refresh (via tools/refresh.sh). I assume that it is a hand-edited
configuration and, hence, must be removed from the repository
(2016-06-23).
* arch/arm/arc/sam34: DAC bugfix: DACC_WPMR_WPKEY_MASK -> DACC_WPMR_WPKEY.
Timer bugfix: Fix ops check in TCIOC_STOP. From Wolfgang Reissnegge
(2016-06-23).
* arch/arm/src/stm32: Port STM32L4 CAN IOCTLs to STM32. From Sebastien
Lorquet (2016-06-24).
* configs/Konfig:Add configuration logic to include a Kconfig file in
each custom configuration. Includes adding a dummy custom board
configuration directory. A consequence of this that each custom board
directory will now need to contain a Kconfig file. NOTE also that
the new board directory does not take effect in the configuration
menus until the NEXT time you run 'make menuconfig' (2016-06-24).
* drivers/ioexpander: Add support for a very simple GPIO driver. It
supports only pre-conrigured input and output pins and only basic
input and output operations (2016-06-24).
* arch/arm/src/lpc43xx: Correct auto-negotiation mode in the LPC43xx
Ethernet. From Alexander Vasiljev (2016-06-24)
* arch/arm/src/samv7: TWIHS Driver improved and GPIO-Driver fixed for
Open-Drain Pins
- sam_gpioread: Now the actual line level from the pin is read back.
This is extremely important for Open-Drain Pins, which can be used
bidirectionally
- Re-Implemented twi_reset-function and enhanced it so it can be
called from inside the driver (see next point)
- Glitch-Filter: Added a configuration option to enable the twi-built-
in glitch filter
- Added a "Single Master Mode": In EMC Testing the TWI-Bus got stuck
because the TWI-Master detected a Multi-Master access (but there is
no second master). With the option "Single Master" we detect these
events and automatically trigger a twi_reset. We also do an
automatic recovery if a slave got stuck (SDA stays low).
With the above changes I²C-Bus reliability in harsh environments (eg.
EMC) is greatly improved. The small change in the GPIO-Driver was
necessary because otherwise you cannot read back the correct line
status of Open-Drain Outputs and this is needed by the twi_reset
function. From Michael Spahlinger (2016-06-24)
Makefile.win
+1 -1
View File
@@ -484,7 +484,7 @@ config: context apps_preconfig
$(Q) set APPSDIR=$(patsubst "%",%,${CONFIG_APPS_DIR})& kconfig-conf Kconfig
oldconfig: context apps_preconfig
$(Q) context set APPSDIR=$(patsubst "%",%,${CONFIG_APPS_DIR})& kconfig-conf --oldconfig Kconfig
$(Q) set APPSDIR=$(patsubst "%",%,${CONFIG_APPS_DIR})& kconfig-conf --oldconfig Kconfig
olddefconfig: context apps_preconfig
$(Q) set APPSDIR=$(patsubst "%",%,${CONFIG_APPS_DIR})& kconfig-conf --olddefconfig Kconfig
TODO
+2 -1
View File
@@ -938,6 +938,7 @@ o Network (net/, drivers/net)
TM4C YES YES
eZ80 NO NO
LPC17xx YES YES (not tested)
LPC43xx YES YES (not tested)
DMxxx NIC NO NO
PIC32 NO NO
RGMP ??? ???
@@ -1602,7 +1603,7 @@ o Build system
Priority: Low.
Title: NATIVE WINDOWS BUILD BROKEN
Description: The way that apps/ no generates Kmenu files depends on changes added
Description: The way that apps/ now generates Kmenu files depends on changes added
to apps/tools/mkkconfig.sh. Similar changes need to be made to
apps/tools/mkkconfig.bat to restore the Windows Native build.
UPDATE: The mkkconfig.bat script has been updated and appears to work.
arch/arm/Kconfig
+1
View File
@@ -213,6 +213,7 @@ config ARCH_CHIP_SAMV7
select ARCH_HAVE_RAMFUNCS
select ARCH_HAVE_TICKLESS
select ARMV7M_HAVE_STACKCHECK
select ARCH_HAVE_I2CRESET
---help---
Atmel SAMV7 (ARM Cortex-M7) architectures
arch/arm/src/lpc43xx/lpc43_ethernet.c
+4 -3
View File
@@ -3392,6 +3392,9 @@ static int lpc43_phyinit(FAR struct lpc43_ethmac_s *priv)
priv->mbps100 = 1;
}
#endif
#endif
#else /* Auto-negotion not selected */
#ifdef CONFIG_LPC43_ETHFD
priv->mbps100 = 1;
@@ -3400,11 +3403,9 @@ static int lpc43_phyinit(FAR struct lpc43_ethmac_s *priv)
#ifdef CONFIG_LPC43_ETH100MBPS
priv->fduplex = 1;
#endif
#endif
/* However we got here, commit to the hardware */
phyval = 0;
if (priv->mbps100)
{
phyval |= MII_MCR_FULLDPLX;
arch/arm/src/samv7/Kconfig
+69
View File
@@ -957,16 +957,85 @@ config SAMV7_TWIHS0_FREQUENCY
default 100000
depends on SAMV7_TWIHS0
config SAMV7_TWIHS0_GLITCH_FILTER
int "TWIHS0 Glitch Filter Time"
default 1
range 0 7
depends on SAMV7_TWIHS0
---help---
Apply filtering on TWIHS Inputs. Given number is the maximum pulse width
(defined in peripheral CLKs) of spikes to be suppressed by the input filter.
Setting this value to zero will disable glitch filtering.
config SAMV7_TWIHS0_SINGLE_MASTER
bool "TWIHS0 Single Master Mode"
default y
depends on SAMV7_TWIHS0
depends on I2C_RESET
---help---
Enables a mode, where errors on the I2C-Bus (e.g. by EMC or
stuck slaves) are automatically handled by the driver.
In an error-case the I2C-Bus is reset so further communication
on the bus can take place.
This option is default on because the TWI-Driver can't handle
Multi-Master I2C anyways.
config SAMV7_TWIHS1_FREQUENCY
int "TWIHS1 Frequency"
default 100000
depends on SAMV7_TWIHS1
config SAMV7_TWIHS1_GLITCH_FILTER
int "TWIHS1 Glitch Filter Time"
default 1
range 0 7
depends on SAMV7_TWIHS1
---help---
Apply filtering on TWIHS Inputs. Given number is the maximum pulse width
(defined in peripheral CLKs) of spikes to be suppressed by the input filter.
Setting this value to zero will disable glitch filtering.
config SAMV7_TWIHS1_SINGLE_MASTER
bool "TWIHS1 Single Master Mode"
default y
depends on SAMV7_TWIHS1
depends on I2C_RESET
---help---
Enables a mode, where errors on the I2C-Bus (e.g. by EMC or
stuck slaves) are automatically handled by the driver.
In an error-case the I2C-Bus is reset so further communication
on the bus can take place.
This option is default on because the TWI-Driver can't handle
Multi-Master I2C anyways.
config SAMV7_TWIHS2_FREQUENCY
int "TWIHS2 Frequency"
default 100000
depends on SAMV7_TWIHS2
config SAMV7_TWIHS2_GLITCH_FILTER
int "TWIHS2 Glitch Filter Time"
default 1
range 0 7
depends on SAMV7_TWIHS2
---help---
Apply filtering on TWIHS Inputs. Given number is the maximum pulse width
(defined in peripheral CLKs) of spikes to be suppressed by the input filter.
Setting this value to zero will disable glitch filtering.
config SAMV7_TWIHS2_SINGLE_MASTER
bool "TWIHS2 Single Master Mode"
default y
depends on SAMV7_TWIHS2
depends on I2C_RESET
---help---
Enables a mode, where errors on the I2C-Bus (e.g. by EMC or
stuck slaves) are automatically handled by the driver.
In an error-case the I2C-Bus is reset so further communication
on the bus can take place.
This option is default on because the TWI-Driver can't handle
Multi-Master I2C anyways.
config SAMV7_TWIHS_REGDEBUG
bool "TWIHS register level debug"
depends on DEBUG_I2C_INFO
arch/arm/src/samv7/sam_gpio.c
+4 -8
View File
@@ -543,15 +543,11 @@ bool sam_gpioread(gpio_pinset_t pinset)
uint32_t pin = sam_gpio_pinmask(pinset);
uint32_t regval;
if ((pinset & GPIO_MODE_MASK) == GPIO_OUTPUT)
{
regval = getreg32(base + SAM_PIO_ODSR_OFFSET);
}
else
{
regval = getreg32(base + SAM_PIO_PDSR_OFFSET);
}
/* Always read the Pin Data Status Register. Otherwise an Open-Drain
* Output pin will not be read back correctly.
*/
regval = getreg32(base + SAM_PIO_PDSR_OFFSET);
return (regval & pin) != 0;
}
arch/arm/src/samv7/sam_twihs.c
+173 -57
View File
@@ -116,13 +116,13 @@
#define TWIHS_MAX_FREQUENCY 66000000 /* Maximum TWIHS frequency */
/* Macros to convert a I2C pin to a PIO open-drain output */
/* Macros to convert a I2C pin to a GPIO open-drain output */
#define I2C_INPUT (PIO_INPUT | PIO_CFG_PULLUP)
#define I2C_OUTPUT (PIO_OUTPUT | PIO_CFG_OPENDRAIN | PIO_OUTPUT_SET)
#define I2C_INPUT (GPIO_INPUT | GPIO_CFG_PULLUP)
#define I2C_OUTPUT (GPIO_OUTPUT | GPIO_CFG_OPENDRAIN | GPIO_OUTPUT_SET)
#define MKI2C_INPUT(p) (((p) & (PIO_PORT_MASK | PIO_PIN_MASK)) | I2C_INPUT)
#define MKI2C_OUTPUT(p) (((p) & (PIO_PORT_MASK | PIO_PIN_MASK)) | I2C_OUTPUT)
#define MKI2C_INPUT(p) (((p) & (GPIO_PORT_MASK | GPIO_PIN_MASK)) | I2C_INPUT)
#define MKI2C_OUTPUT(p) (((p) & (GPIO_PORT_MASK | GPIO_PIN_MASK)) | I2C_OUTPUT)
/****************************************************************************
* Private Types
@@ -134,6 +134,8 @@ struct twi_attr_s
uint8_t twi; /* TWIHS device number (for debug output) */
uint8_t pid; /* TWIHS peripheral ID */
uint16_t irq; /* IRQ number for this TWIHS bus */
uint8_t glitchfltr; /* Pulse width of a glich to be suppressed by the filter */
uint8_t s_master; /* Single-Master Mode active */
gpio_pinset_t sclcfg; /* TWIHS CK pin configuration (SCL in I2C-ese) */
gpio_pinset_t sdacfg; /* TWIHS D pin configuration (SDA in I2C-ese) */
uintptr_t base; /* Base address of TWIHS registers */
@@ -219,6 +221,7 @@ static void twi_startmessage(struct twi_dev_s *priv, struct i2c_msg_s *msg);
static int twi_transfer(FAR struct i2c_master_s *dev,
FAR struct i2c_msg_s *msgs, int count);
#ifdef CONFIG_I2C_RESET
static int twi_reset_internal(FAR struct i2c_master_s *dev);
static int twi_reset(FAR struct i2c_master_s * dev);
#endif
@@ -237,6 +240,12 @@ static const struct twi_attr_s g_twi0attr =
.twi = 0,
.pid = SAM_PID_TWIHS0,
.irq = SAM_IRQ_TWIHS0,
.glitchfltr = CONFIG_SAMV7_TWIHS0_GLITCH_FILTER,
#ifdef CONFIG_SAMV7_TWIHS0_SINGLE_MASTER
.s_master = 1,
#else
.s_master = 0,
#endif
.sclcfg = GPIO_TWIHS0_CK,
.sdacfg = GPIO_TWIHS0_D,
.base = SAM_TWIHS0_BASE,
@@ -252,6 +261,12 @@ static const struct twi_attr_s g_twi1attr =
.twi = 1,
.pid = SAM_PID_TWIHS1,
.irq = SAM_IRQ_TWIHS1,
.glitchfltr = CONFIG_SAMV7_TWIHS1_GLITCH_FILTER,
#ifdef CONFIG_SAMV7_TWIHS1_SINGLE_MASTER
.s_master = 1,
#else
.s_master = 0,
#endif
.sclcfg = GPIO_TWIHS1_CK,
.sdacfg = GPIO_TWIHS1_D,
.base = SAM_TWIHS1_BASE,
@@ -267,6 +282,12 @@ static const struct twi_attr_s g_twi2attr =
.twi = 2,
.pid = SAM_PID_TWIHS2,
.irq = SAM_IRQ_TWIHS2,
.glitchfltr = CONFIG_SAMV7_TWIHS2_GLITCH_FILTER,
#ifdef CONFIG_SAMV7_TWIHS0_SINGLE_MASTER
.s_master = 1,
#else
.s_master = 0,
#endif
.sclcfg = GPIO_TWIHS2_CK,
.sdacfg = GPIO_TWIHS2_D,
.base = SAM_TWIHS2_BASE,
@@ -312,7 +333,7 @@ static void twi_takesem(sem_t *sem)
* awakened by a signal.
*/
ASSERT(errno == EINTR);
DEBUGASSERT(errno == EINTR);
}
}
@@ -494,6 +515,24 @@ static int twi_wait(struct twi_dev_s *priv, unsigned int size)
* all further interrupts for the TWIHS have been disabled.
*/
/* Check if an Arbitration Lost has occured */
if (priv->result == -EUSERS)
{
/* Something bad happened on the bus so force a reset */
priv->result = twi_reset_internal(&priv->dev);
/* Although the reset was successful tell the higher driver that it's
* transfer has failed and should be repeated.
*/
if (priv->result == OK)
{
priv->result = -EIO;
}
}
return priv->result;
}
@@ -607,6 +646,20 @@ static int twi_interrupt(struct twi_dev_s *priv)
}
}
/* If Single-Master Mode is enabled and we lost arbitration (someone else or
* an EMC-Pulse did something on the bus) something went very wrong. So we end
* the current transfer with an EUSERS. The wait function will then reset
* the bus so further communication can take place.
*/
else if ((priv->attr->s_master) && ((pending & TWIHS_INT_ARBLST) != 0))
{
/* Wake up the thread with an Arbitration Lost error indication */
i2cllerr("ERROR: TWIHS%d Arbitration Lost\n");
twi_wakeup(priv, -EUSERS);
}
/* Check for errors. We must check for errors *before* checking TXRDY or
* TXCMP because the error can be signaled in combination with TXRDY or
* TXCOMP.
@@ -856,6 +909,7 @@ static int twi_transfer(FAR struct i2c_master_s *dev,
struct twi_dev_s *priv = (struct twi_dev_s *)dev;
irqstate_t flags;
unsigned int size;
uint32_t sr;
int i;
int ret;
@@ -891,6 +945,22 @@ static int twi_transfer(FAR struct i2c_master_s *dev,
twi_setfrequency(priv, msgs->frequency);
/* When we are in Single Master Mode check if the bus is ready (no stuck
* DATA or CLK line).
* Otherwise initiate a bus reset.
*/
if (priv->attr->s_master)
{
sr = twi_getrel(priv, SAM_TWIHS_SR_OFFSET);
if (((sr & TWIHS_INT_SDA) == 0) || ((sr & TWIHS_INT_SCL) == 0))
{
ret = twi_reset_internal(&priv->dev);
if (ret != OK)
goto errout;
}
}
/* Initiate the transfer. The rest will be handled from interrupt
* logic. Interrupts must be disabled to prevent re-entrance from the
* interrupt level.
@@ -904,46 +974,46 @@ static int twi_transfer(FAR struct i2c_master_s *dev,
*/
ret = twi_wait(priv, size);
leave_critical_section(flags);
errout:
if (ret < 0)
{
i2cerr("ERROR: Transfer failed: %d\n", ret);
}
leave_critical_section(flags);
twi_givesem(&priv->exclsem);
return ret;
}
/************************************************************************************
* Name: twi_reset
*
* Description:
* Perform an I2C bus reset in an attempt to break loose stuck I2C devices.
*
* Input Parameters:
* dev - Device-specific state data
*
* Returned Value:
* Zero (OK) on success; a negated errno value on failure.
*
************************************************************************************/
* Name: twi_reset_internal
*
* Description:
* Perform an I2C bus reset in an attempt to break loose stuck I2C devices.
* This function can be called from inside the driver while the TWIHS device is
* already locked, so we must not handle any semapores inside.
* To initiate a bus reset from outside the driver use twi_reset(dev).
*
* Input Parameters:
* dev - Device-specific state data
*
* Returned Value:
* Zero (OK) on success; a negated errno value on failure.
*
************************************************************************************/
#ifdef CONFIG_I2C_RESET
static int twi_reset(FAR struct i2c_master_s *dev)
static int twi_reset_internal(FAR struct i2c_master_s *dev)
{
struct twi_dev_s *priv = (struct twi_dev_s *)dev;
unsigned int clockcnt;
unsigned int stretchcnt;
uint32_t sclpin;
uint32_t sdapin;
uint8_t wait_us;
int ret;
ASSERT(priv);
/* Get exclusive access to the TWIHS device */
twi_takesem(&priv->exclsem);
/* Disable TWIHS interrupts */
up_disable_irq(priv->attr->irq);
@@ -960,28 +1030,31 @@ static int twi_reset(FAR struct i2c_master_s *dev)
sam_configgpio(sclpin);
sam_configgpio(sdapin);
/* Peripheral clocking must be enabled in order to read valid data from
* the output pin (clocking is enabled automatically for pins configured
* as inputs).
*/
sam_pio_forceclk(sclpin, true);
sam_pio_forceclk(sdapin, true);
/* Clock the bus until any slaves currently driving it low let it float.
* Reading from the output will return the actual sensed level on the
* SDA pin (not the level that we wrote).
*/
/* Set the wait-time according to the TWI-Bus-Frequency */
if (priv->frequency >= 330000)
{
wait_us = 3;
}
else
{
wait_us = 10;
}
clockcnt = 0;
while (sam_pioread(sdapin) == false)
while (sam_gpioread(sdapin) == false)
{
/* Give up if we have tried too hard */
if (clockcnt++ > 10)
{
ret = -ETIMEDOUT;
goto errout_with_lock;
goto errout;
}
/* Sniff to make sure that clock stretching has finished. SCL should
@@ -991,55 +1064,85 @@ static int twi_reset(FAR struct i2c_master_s *dev)
*/
stretchcnt = 0;
while (sam_pioread(sclpin) == false)
while (sam_gpioread(sclpin) == false)
{
/* Give up if we have tried too hard */
if (stretchcnt++ > 10)
{
ret = -EAGAIN;
goto errout_with_lock;
goto errout;
}
up_udelay(10);
up_udelay(wait_us);
}
/* Drive SCL low */
sam_piowrite(sclpin, false);
up_udelay(10);
sam_gpiowrite(sclpin, false);
up_udelay(wait_us);
/* Drive SCL high (floating) again */
sam_piowrite(sclpin, true);
up_udelay(10);
sam_gpiowrite(sclpin, true);
up_udelay(wait_us);
}
/* Generate a start followed by a stop to reset slave
* state machines.
*/
sam_piowrite(sdapin, false);
up_udelay(10);
sam_piowrite(sclpin, false);
up_udelay(10);
sam_gpiowrite(sdapin, false);
up_udelay(wait_us);
sam_gpiowrite(sclpin, false);
up_udelay(wait_us);
sam_piowrite(sclpin, true);
up_udelay(10);
sam_piowrite(sdapin, true);
up_udelay(10);
/* Clocking is no longer forced */
sam_pio_forceclk(sclpin, false);
sam_pio_forceclk(sdapin, false);
sam_gpiowrite(sclpin, true);
up_udelay(wait_us);
sam_gpiowrite(sdapin, true);
up_udelay(wait_us);
/* Re-initialize the port hardware */
twi_hw_initialize(priv, priv->frequency);
ret = OK;
errout_with_lock:
errout:
return ret;
}
#endif /* CONFIG_I2C_RESET */
/************************************************************************************
* Name: twi_reset
*
* Description:
* Perform an I2C bus reset in an attempt to break loose stuck I2C devices.
* This function can be called from outside the driver, so lock the TWIHS Device
* and then let the internal reset function do the work.
*
* Input Parameters:
* dev - Device-specific state data
*
* Returned Value:
* Zero (OK) on success; a negated errno value on failure.
*
************************************************************************************/
#ifdef CONFIG_I2C_RESET
static int twi_reset(FAR struct i2c_master_s *dev)
{
struct twi_dev_s *priv = (struct twi_dev_s *)dev;
int ret;
DEBUGASSERT(priv != NULL);
/* Get exclusive access to the TWIHS device */
twi_takesem(&priv->exclsem);
/* Do the reset-procedure */
ret = twi_reset_internal(dev);
/* Release our lock on the bus */
@@ -1217,6 +1320,19 @@ static void twi_hw_initialize(struct twi_dev_s *priv, uint32_t frequency)
regval |= PMC_PCR_PID(priv->attr->pid) | PMC_PCR_CMD | PMC_PCR_EN;
twi_putabs(priv, SAM_PMC_PCR, regval);
/* Set the TWIHS Input Filters */
if (priv->attr->glitchfltr)
{
regval = TWIHS_FILTR_FILT | TWIHS_FILTR_THRES(priv->attr->glitchfltr);
}
else
{
regval = 0;
}
twi_putrel(priv, SAM_TWIHS_FILTR_OFFSET, regval);
/* Set the initial TWIHS data transfer frequency */
priv->frequency = 0;
arch/arm/src/stm32f7/Kconfig
+84
View File
@@ -1215,12 +1215,16 @@ config STM32F7_SDMMC1
bool "SDMMC1"
default n
select ARCH_HAVE_SDIO
select ARCH_HAVE_SDIOWAIT_WRCOMPLETE
select SDIO_PREFLIGHT
config STM32F7_SDMMC2
bool "SDMMC2"
default n
depends on STM32F7_HAVE_SDMMC2
select ARCH_HAVE_SDIO
select ARCH_HAVE_SDIOWAIT_WRCOMPLETE
select SDIO_PREFLIGHT
config STM32F7_SPDIFRX
bool "SPDIFRX"
@@ -1710,6 +1714,86 @@ config STM32F7_I2C_DUTY16_9
endmenu # "I2C Configuration"
config STM32F7_SDMMC_XFRDEBUG
bool "SDMMC transfer debug"
depends on DEBUG_FS_INFO && (STM32F7_SDMMC1 || STM32F7_SDMMC2)
default n
---help---
Enable special debug instrumentation analyze SDMMC data transfers.
This logic is as non-invasive as possible: It samples SDMMC
registers at key points in the data transfer and then dumps all of
the registers at the end of the transfer. If DEBUG_DMA is also
enabled, then DMA register will be collected as well. Requires also
DEBUG_FS and CONFIG_DEBUG_INFO.
menu "SDMMC1 Configuration"
depends on STM32F7_SDMMC1
config SDMMC1_DMA
bool "Support DMA data transfers on SDMMC1"
default y if STM32F7_DMA2
depends on STM32F7_DMA2
---help---
Support DMA data transfers on SDMMC1. Requires STM32F7_SDMMC1 and config STM32F7_DMA2.
config SDMMC1_PRI
hex "SDMMC1 interrupt priority"
default 128
depends on ARCH_IRQPRIO && EXPERIMENTAL
---help---
Select SDMMC1 interrupt priority. Default: 128.
config SDMMC1_DMAPRIO
hex "SDMMC1 DMA priority"
default 0x00010000
---help---
Select SDMMC1 DMA prority.
Options are: 0x00000000 low, 0x00010000 medium,
0x00020000 high, 0x00030000 very high. Default: medium.
config SDMMC1_WIDTH_D1_ONLY
bool "Use D1 only on SDMMC1"
default n
---help---
Select 1-bit transfer mode. Default: 4-bit transfer mode.
endmenu # "SDMMC1 Configuration"
menu "SDMMC2 Configuration"
depends on STM32F7_SDMMC2
config SDMMC2_DMA
bool "Support DMA data transfers on SDMMC2"
default y if STM32F7_DMA2
depends on STM32F7_DMA2
---help---
Support DMA data transfers on SDMMC2. Requires STM32F7_SDMMC2 and config STM32F7_DMA2.
config SDMMC2_PRI
hex "SDMMC2 interrupt priority"
default 128
depends on ARCH_IRQPRIO && EXPERIMENTAL
---help---
Select SDMMC2 interrupt priority. Default: 128.
config SDMMC2_DMAPRIO
hex "SDMMC2 DMA priority"
default 0x00010000
---help---
Select SDMMC1 DMA prority.
Options are: 0x00000000 low, 0x00010000 medium,
0x00020000 high, 0x00030000 very high. Default: medium.
config SDMMC2_WIDTH_D1_ONLY
bool "Use D1 only on SDMMC2"
default n
---help---
Select 1-bit transfer mode. Default: 4-bit transfer mode.
endmenu # "SDMMC2 Configuration"
config STM32F7_CUSTOM_CLOCKCONFIG
bool "Custom clock configuration"
default n
arch/arm/src/stm32f7/chip/stm32_sdmmc.h
+5 -3
View File
@@ -2,7 +2,8 @@
* arch/arm/src/stm32f7/chip/stm32_sdmmc.h
*
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* Authors: Gregory Nutt <gnutt@nuttx.org>
* David Sidrane <david_s5@nscdg.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -43,8 +44,9 @@
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
# include "stm32f74xx75xx_sdmmc.h"
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \
defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
# include "stm32f74xx77xx_sdmmc.h"
#else
# error "Unsupported STM32 F7 part"
#endif
arch/arm/src/stm32f7/chip/stm32f74xx75xx_rcc.h
+2 -2
View File
@@ -574,7 +574,7 @@
# define RCC_PLLI2SCFGR_PLLI2SN(n) ((uint32_t)(n) << RCC_PLLI2SCFGR_PLLI2SN_SHIFT)
#define RCC_PLLI2SCFGR_PLLI2SP_SHIFT (16) /* Bits 16-17: PLLI2S division factor for SPDIFRX clock */
#define RCC_PLLI2SCFGR_PLLI2SP_MASK (3 << RCC_PLLI2SCFGR_PLLI2SP_SHIFT)
# define RCC_PLLI2SCFGR_PLLI2SP(n) ((uint32_t)(n) << RCC_PLLI2SCFGR_PLLI2SP_SHIFT)
# define RCC_PLLI2SCFGR_PLLI2SP(n) ((((n)>>1)-1) << RCC_PLLI2SCFGR_PLLI2SP_SHIFT)
#define RCC_PLLI2SCFGR_PLLI2SQ_SHIFT (24) /* Bits 24-27: PLLI2S division factor for SAIs clock */
#define RCC_PLLI2SCFGR_PLLI2SQ_MASK (15 << RCC_PLLI2SCFGR_PLLI2SQ_SHIFT)
# define RCC_PLLI2SCFGR_PLLI2SQ(n) ((uint32_t)(n) << RCC_PLLI2SCFGR_PLLI2SQ_SHIFT)
@@ -589,7 +589,7 @@
# define RCC_PLLSAICFGR_PLLSAIN(n) ((n) << RCC_PLLSAICFGR_PLLSAIN_SHIFT)
#define RCC_PLLSAICFGR_PLLSAIP_SHIFT (16) /* Bits 16-17: PLLSAI division factor for 48MHz clock */
#define RCC_PLLSAICFGR_PLLSAIP_MASK (3 << RCC_PLLSAICFGR_PLLSAIP_SHIFT)
# define RCC_PLLSAICFGR_PLLSAIP(n) ((n) << RCC_PLLSAICFGR_PLLSAIP_SHIFT)
# define RCC_PLLSAICFGR_PLLSAIP(n) ((((n)>>1)-1) << RCC_PLLSAICFGR_PLLSAIP_SHIFT)
#define RCC_PLLSAICFGR_PLLSAIQ_SHIFT (24) /* Bits 24-27: PLLSAI division factor for SAI clock */
#define RCC_PLLSAICFGR_PLLSAIQ_MASK (0x0F << RCC_PLLSAICFGR_PLLSAIQ_SHIFT)
# define RCC_PLLSAICFGR_PLLSAIQ(n) ((n) << RCC_PLLSAICFGR_PLLSAIQ_SHIFT)
arch/arm/src/stm32f7/chip/stm32f74xx75xx_sdmmc.h
-268
View File
@@ -1,268 +0,0 @@
/************************************************************************************
* arch/arm/src/stm32f7/chip/stm32_sdmmc.h
*
* Copyright (C) 2009, 2011-2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XX_SDMMC_H
#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XX_SDMMC_H
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Register Offsets *****************************************************************/
#define STM32_SDMMC1_POWER_OFFSET 0x0000 /* SDIO power control register */
#define STM32_SDMMC1_CLKCR_OFFSET 0x0004 /* SDI clock control register */
#define STM32_SDMMC1_ARG_OFFSET 0x0008 /* SDIO argument register */
#define STM32_SDMMC1_CMD_OFFSET 0x000c /* SDIO command register */
#define STM32_SDMMC1_RESPCMD_OFFSET 0x0010 /* SDIO command response register */
#define STM32_SDMMC1_RESP_OFFSET(n) (0x0010+4*(n))
#define STM32_SDMMC1_RESP1_OFFSET 0x0014 /* SDIO response 1 register */
#define STM32_SDMMC1_RESP2_OFFSET 0x0018 /* SDIO response 2 register */
#define STM32_SDMMC1_RESP3_OFFSET 0x001c /* SDIO response 3 register */
#define STM32_SDMMC1_RESP4_OFFSET 0x0020 /* SDIO response 4 register */
#define STM32_SDMMC1_DTIMER_OFFSET 0x0024 /* SDIO data timer register */
#define STM32_SDMMC1_DLEN_OFFSET 0x0028 /* SDIO data length register */
#define STM32_SDMMC1_DCTRL_OFFSET 0x002c /* SDIO data control register */
#define STM32_SDMMC1_DCOUNT_OFFSET 0x0030 /* SDIO data counter register */
#define STM32_SDMMC1_STA_OFFSET 0x0034 /* SDIO status register */
#define STM32_SDMMC1_ICR_OFFSET 0x0038 /* SDIO interrupt clear register */
#define STM32_SDMMC1_MASK_OFFSET 0x003c /* SDIO mask register */
#define STM32_SDMMC1_FIFOCNT_OFFSET 0x0048 /* SDIO FIFO counter register */
#define STM32_SDMMC1_FIFO_OFFSET 0x0080 /* SDIO data FIFO register */
/* Register Addresses ***************************************************************/
#define STM32_SDMMC1_POWER (STM32_SDMMC1_BASE+STM32_SDMMC1_POWER_OFFSET)
#define STM32_SDMMC1_CLKCR (STM32_SDMMC1_BASE+STM32_SDMMC1_CLKCR_OFFSET)
#define STM32_SDMMC1_ARG (STM32_SDMMC1_BASE+STM32_SDMMC1_ARG_OFFSET)
#define STM32_SDMMC1_CMD (STM32_SDMMC1_BASE+STM32_SDMMC1_CMD_OFFSET)
#define STM32_SDMMC1_RESPCMD (STM32_SDMMC1_BASE+STM32_SDMMC1_RESPCMD_OFFSET)
#define STM32_SDMMC1_RESP(n) (STM32_SDMMC1_BASE+STM32_SDMMC1_RESP_OFFSET(n))
#define STM32_SDMMC1_RESP1 (STM32_SDMMC1_BASE+STM32_SDMMC1_RESP1_OFFSET)
#define STM32_SDMMC1_RESP2 (STM32_SDMMC1_BASE+STM32_SDMMC1_RESP2_OFFSET)
#define STM32_SDMMC1_RESP3 (STM32_SDMMC1_BASE+STM32_SDMMC1_RESP3_OFFSET)
#define STM32_SDMMC1_RESP4 (STM32_SDMMC1_BASE+STM32_SDMMC1_RESP4_OFFSET)
#define STM32_SDMMC1_DTIMER (STM32_SDMMC1_BASE+STM32_SDMMC1_DTIMER_OFFSET)
#define STM32_SDMMC1_DLEN (STM32_SDMMC1_BASE+STM32_SDMMC1_DLEN_OFFSET)
#define STM32_SDMMC1_DCTRL (STM32_SDMMC1_BASE+STM32_SDMMC1_DCTRL_OFFSET)
#define STM32_SDMMC1_DCOUNT (STM32_SDMMC1_BASE+STM32_SDMMC1_DCOUNT_OFFSET)
#define STM32_SDMMC1_STA (STM32_SDMMC1_BASE+STM32_SDMMC1_STA_OFFSET)
#define STM32_SDMMC1_ICR (STM32_SDMMC1_BASE+STM32_SDMMC1_ICR_OFFSET)
#define STM32_SDMMC1_MASK (STM32_SDMMC1_BASE+STM32_SDMMC1_MASK_OFFSET)
#define STM32_SDMMC1_FIFOCNT (STM32_SDMMC1_BASE+STM32_SDMMC1_FIFOCNT_OFFSET)
#define STM32_SDMMC1_FIFO (STM32_SDMMC1_BASE+STM32_SDMMC1_FIFO_OFFSET)
/* Register Bitfield Definitions ****************************************************/
#define SDIO_POWER_PWRCTRL_SHIFT (0) /* Bits 0-1: Power supply control bits */
#define SDIO_POWER_PWRCTRL_MASK (3 << SDIO_POWER_PWRCTRL_SHIFT)
# define SDIO_POWER_PWRCTRL_OFF (0 << SDIO_POWER_PWRCTRL_SHIFT) /* 00: Power-off: card clock stopped */
# define SDIO_POWER_PWRCTRL_PWRUP (2 << SDIO_POWER_PWRCTRL_SHIFT) /* 10: Reserved power-up */
# define SDIO_POWER_PWRCTRL_ON (3 << SDIO_POWER_PWRCTRL_SHIFT) /* 11: Power-on: card is clocked */
#define SDIO_POWER_RESET (0) /* Reset value */
#define SDIO_CLKCR_CLKDIV_SHIFT (0) /* Bits 7-0: Clock divide factor */
#define SDIO_CLKCR_CLKDIV_MASK (0xff << SDIO_CLKCR_CLKDIV_SHIFT)
#define SDIO_CLKCR_CLKEN (1 << 8) /* Bit 8: Clock enable bit */
#define SDIO_CLKCR_PWRSAV (1 << 9) /* Bit 9: Power saving configuration bit */
#define SDIO_CLKCR_BYPASS (1 << 10) /* Bit 10: Clock divider bypass enable bit */
#define SDIO_CLKCR_WIDBUS_SHIFT (11) /* Bits 12-11: Wide bus mode enable bits */
#define SDIO_CLKCR_WIDBUS_MASK (3 << SDIO_CLKCR_WIDBUS_SHIFT)
# define SDIO_CLKCR_WIDBUS_D1 (0 << SDIO_CLKCR_WIDBUS_SHIFT) /* 00: Default (SDIO_D0) */
# define SDIO_CLKCR_WIDBUS_D4 (1 << SDIO_CLKCR_WIDBUS_SHIFT) /* 01: 4-wide (SDIO_D[3:0]) */
# define SDIO_CLKCR_WIDBUS_D8 (2 << SDIO_CLKCR_WIDBUS_SHIFT) /* 10: 8-wide (SDIO_D[7:0]) */
#define SDIO_CLKCR_NEGEDGE (1 << 13) /* Bit 13: SDIO_CK dephasing selection bit */
#define SDIO_CLKCR_HWFC_EN (1 << 14) /* Bit 14: HW Flow Control enable */
#define SDIO_CLKCR_RESET (0) /* Reset value */
#define SDIO_ARG_RESET (0) /* Reset value */
#define SDIO_CLKCR_CLKEN_BB (STM32_SDMMC1_CLKCR_BB + (8 * 4))
#define SDIO_CLKCR_PWRSAV_BB (STM32_SDMMC1_CLKCR_BB + (9 * 4))
#define SDIO_CLKCR_BYPASS_BB (STM32_SDMMC1_CLKCR_BB + (10 * 4))
#define SDIO_CLKCR_NEGEDGE_BB (STM32_SDMMC1_CLKCR_BB + (13 * 4))
#define SDIO_CLKCR_HWFC_EN_BB (STM32_SDMMC1_CLKCR_BB + (14 * 4))
#define SDIO_CMD_CMDINDEX_SHIFT (0)
#define SDIO_CMD_CMDINDEX_MASK (0x3f << SDIO_CMD_CMDINDEX_SHIFT)
#define SDIO_CMD_WAITRESP_SHIFT (6) /* Bits 7-6: Wait for response bits */
#define SDIO_CMD_WAITRESP_MASK (3 << SDIO_CMD_WAITRESP_SHIFT)
# define SDIO_CMD_NORESPONSE (0 << SDIO_CMD_WAITRESP_SHIFT) /* 00/10: No response */
# define SDIO_CMD_SHORTRESPONSE (1 << SDIO_CMD_WAITRESP_SHIFT) /* 01: Short response */
# define SDIO_CMD_LONGRESPONSE (3 << SDIO_CMD_WAITRESP_SHIFT) /* 11: Long response */
#define SDIO_CMD_WAITINT (1 << 8) /* Bit 8: CPSM waits for interrupt request */
#define SDIO_CMD_WAITPEND (1 << 9) /* Bit 9: CPSM Waits for ends of data transfer */
#define SDIO_CMD_CPSMEN (1 << 10) /* Bit 10: Command path state machine enable */
#define SDIO_CMD_SUSPEND (1 << 11) /* Bit 11: SD I/O suspend command */
#define SDIO_CMD_ENDCMD (1 << 12) /* Bit 12: Enable CMD completion */
#define SDIO_CMD_NIEN (1 << 13) /* Bit 13: not Interrupt Enable */
#define SDIO_CMD_ATACMD (1 << 14) /* Bit 14: CE-ATA command */
#define SDIO_CMD_RESET (0) /* Reset value */
#define SDIO_CMD_WAITINT_BB (STM32_SDMMC1_CMD_BB + (8 * 4))
#define SDIO_CMD_WAITPEND_BB (STM32_SDMMC1_CMD_BB + (9 * 4))
#define SDIO_CMD_CPSMEN_BB (STM32_SDMMC1_CMD_BB + (10 * 4))
#define SDIO_CMD_SUSPEND_BB (STM32_SDMMC1_CMD_BB + (11 * 4))
#define SDIO_CMD_ENCMD_BB (STM32_SDMMC1_CMD_BB + (12 * 4))
#define SDIO_CMD_NIEN_BB (STM32_SDMMC1_CMD_BB + (13 * 4))
#define SDIO_CMD_ATACMD_BB (STM32_SDMMC1_CMD_BB + (14 * 4))
#define SDIO_RESPCMD_SHIFT (0)
#define SDIO_RESPCMD_MASK (0x3f << SDIO_RESPCMD_SHIFT)
#define SDIO_DTIMER_RESET (0) /* Reset value */
#define SDIO_DLEN_SHIFT (0)
#define SDIO_DLEN_MASK (0x01ffffff << SDIO_DLEN_SHIFT)
#define SDIO_DLEN_RESET (0) /* Reset value */
#define SDIO_DCTRL_DTEN (1 << 0) /* Bit 0: Data transfer enabled bit */
#define SDIO_DCTRL_DTDIR (1 << 1) /* Bit 1: Data transfer direction */
#define SDIO_DCTRL_DTMODE (1 << 2) /* Bit 2: Data transfer mode */
#define SDIO_DCTRL_DMAEN (1 << 3) /* Bit 3: DMA enable bit */
#define SDIO_DCTRL_DBLOCKSIZE_SHIFT (4) /* Bits 7-4: Data block size */
#define SDIO_DCTRL_DBLOCKSIZE_MASK (15 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
# define SDIO_DCTRL_1BYTE (0 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
# define SDIO_DCTRL_2BYTES (1 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
# define SDIO_DCTRL_4BYTES (2 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
# define SDIO_DCTRL_8BYTES (3 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
# define SDIO_DCTRL_16BYTES (4 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
# define SDIO_DCTRL_32BYTES (5 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
# define SDIO_DCTRL_64BYTES (6 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
# define SDIO_DCTRL_128BYTES (7 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
# define SDIO_DCTRL_256BYTES (8 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
# define SDIO_DCTRL_512BYTES (9 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
# define SDIO_DCTRL_1KBYTE (10 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
# define SDIO_DCTRL_2KBYTES (11 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
# define SDIO_DCTRL_4KBYTES (12 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
# define SDIO_DCTRL_8KBYTES (13 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
# define SDIO_DCTRL_16KBYTES (14 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
#define SDIO_DCTRL_RWSTART (1 << 8) /* Bit 8: Read wait start */
#define SDIO_DCTRL_RWSTOP (1 << 9) /* Bit 9: Read wait stop */
#define SDIO_DCTRL_RWMOD (1 << 10) /* Bit 10: Read wait mode */
#define SDIO_DCTRL_SDIOEN (1 << 11) /* Bit 11: SD I/O enable functions */
#define SDIO_DCTRL_RESET (0) /* Reset value */
#define SDIO_DCTRL_DTEN_BB (STM32_SDMMC1_DCTRL_BB + (0 * 4))
#define SDIO_DCTRL_DTDIR_BB (STM32_SDMMC1_DCTRL_BB + (1 * 4))
#define SDIO_DCTRL_DTMODE_BB (STM32_SDMMC1_DCTRL_BB + (2 * 4))
#define SDIO_DCTRL_DMAEN_BB (STM32_SDMMC1_DCTRL_BB + (3 * 4))
#define SDIO_DCTRL_RWSTART_BB (STM32_SDMMC1_DCTRL_BB + (8 * 4))
#define SDIO_DCTRL_RWSTOP_BB (STM32_SDMMC1_DCTRL_BB + (9 * 4))
#define SDIO_DCTRL_RWMOD_BB (STM32_SDMMC1_DCTRL_BB + (10 * 4))
#define SDIO_DCTRL_SDIOEN_BB (STM32_SDMMC1_DCTRL_BB + (11 * 4))
#define SDIO_DATACOUNT_SHIFT (0)
#define SDIO_DATACOUNT_MASK (0x01ffffff << SDIO_DATACOUNT_SHIFT)
#define SDIO_STA_CCRCFAIL (1 << 0) /* Bit 0: Command response CRC fail */
#define SDIO_STA_DCRCFAIL (1 << 1) /* Bit 1: Data block CRC fail */
#define SDIO_STA_CTIMEOUT (1 << 2) /* Bit 2: Command response timeout */
#define SDIO_STA_DTIMEOUT (1 << 3) /* Bit 3: Data timeout */
#define SDIO_STA_TXUNDERR (1 << 4) /* Bit 4: Transmit FIFO underrun error */
#define SDIO_STA_RXOVERR (1 << 5) /* Bit 5: Received FIFO overrun error */
#define SDIO_STA_CMDREND (1 << 6) /* Bit 6: Command response received */
#define SDIO_STA_CMDSENT (1 << 7) /* Bit 7: Command sent */
#define SDIO_STA_DATAEND (1 << 8) /* Bit 8: Data end */
#define SDIO_STA_STBITERR (1 << 9) /* Bit 9: Start bit not detected */
#define SDIO_STA_DBCKEND (1 << 10) /* Bit 10: Data block sent/received */
#define SDIO_STA_CMDACT (1 << 11) /* Bit 11: Command transfer in progress */
#define SDIO_STA_TXACT (1 << 12) /* Bit 12: Data transmit in progress */
#define SDIO_STA_RXACT (1 << 13) /* Bit 13: Data receive in progress */
#define SDIO_STA_TXFIFOHE (1 << 14) /* Bit 14: Transmit FIFO half empty */
#define SDIO_STA_RXFIFOHF (1 << 15) /* Bit 15: Receive FIFO half full */
#define SDIO_STA_TXFIFOF (1 << 16) /* Bit 16: Transmit FIFO full */
#define SDIO_STA_RXFIFOF (1 << 17) /* Bit 17: Receive FIFO full */
#define SDIO_STA_TXFIFOE (1 << 18) /* Bit 18: Transmit FIFO empty */
#define SDIO_STA_RXFIFOE (1 << 19) /* Bit 19: Receive FIFO empty */
#define SDIO_STA_TXDAVL (1 << 20) /* Bit 20: Data available in transmit FIFO */
#define SDIO_STA_RXDAVL (1 << 21) /* Bit 21: Data available in receive FIFO */
#define SDIO_STA_SDIOIT (1 << 22) /* Bit 22: SDIO interrupt received */
#define SDIO_STA_CEATAEND (1 << 23) /* Bit 23: CMD6 CE-ATA command completion */
#define SDIO_ICR_CCRCFAILC (1 << 0) /* Bit 0: CCRCFAIL flag clear bit */
#define SDIO_ICR_DCRCFAILC (1 << 1) /* Bit 1: DCRCFAIL flag clear bit */
#define SDIO_ICR_CTIMEOUTC (1 << 2) /* Bit 2: CTIMEOUT flag clear bit */
#define SDIO_ICR_DTIMEOUTC (1 << 3) /* Bit 3: DTIMEOUT flag clear bit */
#define SDIO_ICR_TXUNDERRC (1 << 4) /* Bit 4: TXUNDERR flag clear bit */
#define SDIO_ICR_RXOVERRC (1 << 5) /* Bit 5: RXOVERR flag clear bit */
#define SDIO_ICR_CMDRENDC (1 << 6) /* Bit 6: CMDREND flag clear bit */
#define SDIO_ICR_CMDSENTC (1 << 7) /* Bit 7: CMDSENT flag clear bit */
#define SDIO_ICR_DATAENDC (1 << 8) /* Bit 8: DATAEND flag clear bit */
#define SDIO_ICR_STBITERRC (1 << 9) /* Bit 9: STBITERR flag clear bit */
#define SDIO_ICR_DBCKENDC (1 << 10) /* Bit 10: DBCKEND flag clear bit */
#define SDIO_ICR_SDIOITC (1 << 22) /* Bit 22: SDIOIT flag clear bit */
#define SDIO_ICR_CEATAENDC (1 << 23) /* Bit 23: CEATAEND flag clear bit */
#define SDIO_ICR_RESET 0x00c007ff
#define SDIO_ICR_STATICFLAGS 0x000005ff
#define SDIO_MASK_CCRCFAILIE (1 << 0) /* Bit 0: Command CRC fail interrupt enable */
#define SDIO_MASK_DCRCFAILIE (1 << 1) /* Bit 1: Data CRC fail interrupt enable */
#define SDIO_MASK_CTIMEOUTIE (1 << 2) /* Bit 2: Command timeout interrupt enable */
#define SDIO_MASK_DTIMEOUTIE (1 << 3) /* Bit 3: Data timeout interrupt enable */
#define SDIO_MASK_TXUNDERRIE (1 << 4) /* Bit 4: Tx FIFO underrun error interrupt enable */
#define SDIO_MASK_RXOVERRIE (1 << 5) /* Bit 5: Rx FIFO overrun error interrupt enable */
#define SDIO_MASK_CMDRENDIE (1 << 6) /* Bit 6: Command response received interrupt enable */
#define SDIO_MASK_CMDSENTIE (1 << 7) /* Bit 7: Command sent interrupt enable */
#define SDIO_MASK_DATAENDIE (1 << 8) /* Bit 8: Data end interrupt enable */
#define SDIO_MASK_STBITERRIE (1 << 9) /* Bit 9: Start bit error interrupt enable */
#define SDIO_MASK_DBCKENDIE (1 << 10) /* Bit 10: Data block end interrupt enable */
#define SDIO_MASK_CMDACTIE (1 << 11) /* Bit 11: Command acting interrupt enable */
#define SDIO_MASK_TXACTIE (1 << 12) /* Bit 12: Data transmit acting interrupt enable */
#define SDIO_MASK_RXACTIE (1 << 13) /* Bit 13: Data receive acting interrupt enable */
#define SDIO_MASK_TXFIFOHEIE (1 << 14) /* Bit 14: Tx FIFO half empty interrupt enable */
#define SDIO_MASK_RXFIFOHFIE (1 << 15) /* Bit 15: Rx FIFO half full interrupt enable */
#define SDIO_MASK_TXFIFOFIE (1 << 16) /* Bit 16: Tx FIFO full interrupt enable */
#define SDIO_MASK_RXFIFOFIE (1 << 17) /* Bit 17: Rx FIFO full interrupt enable */
#define SDIO_MASK_TXFIFOEIE (1 << 18) /* Bit 18: Tx FIFO empty interrupt enable */
#define SDIO_MASK_RXFIFOEIE (1 << 19) /* Bit 19: Rx FIFO empty interrupt enable */
#define SDIO_MASK_TXDAVLIE (1 << 20) /* Bit 20: Data available in Tx FIFO interrupt enable */
#define SDIO_MASK_RXDAVLIE (1 << 21) /* Bit 21: Data available in Rx FIFO interrupt enable */
#define SDIO_MASK_SDIOITIE (1 << 22) /* Bit 22: SDIO mode interrupt received interrupt enable */
#define SDIO_MASK_CEATAENDIE (1 << 23) /* Bit 23: CE-ATA command completion interrupt enable */
#define SDIO_MASK_RESET (0)
#define SDIO_FIFOCNT_SHIFT (0)
#define SDIO_FIFOCNT_MASK (0x01ffffff << SDIO_FIFOCNT_SHIFT)
#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XX_SDMMC_H */
arch/arm/src/stm32f7/chip/stm32f74xx77xx_sdmmc.h
+224
View File
@@ -0,0 +1,224 @@
/* arch/arm/src/stm32f7/chip/stm32f74xx77xx_sdmmc.h
*
* Copyright (C) 2009, 2011-2016 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
* David Sidrane <david_s5@nscdg.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX77XX_SDMMC_H
#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX77XX_SDMMC_H
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Register Offsets *****************************************************************/
#define STM32_SDMMC_POWER_OFFSET 0x0000 /* SDMMC power control register */
#define STM32_SDMMC_CLKCR_OFFSET 0x0004 /* SDMMC clock control register */
#define STM32_SDMMC_ARG_OFFSET 0x0008 /* SDMMC argument register */
#define STM32_SDMMC_CMD_OFFSET 0x000c /* SDMMC command register */
#define STM32_SDMMC_RESPCMD_OFFSET 0x0010 /* SDMMC command response register */
#define STM32_SDMMC_RESP_OFFSET(n) (0x0010+4*(n))
#define STM32_SDMMC_RESP1_OFFSET 0x0014 /* SDMMC response 1 register */
#define STM32_SDMMC_RESP2_OFFSET 0x0018 /* SDMMC response 2 register */
#define STM32_SDMMC_RESP3_OFFSET 0x001c /* SDMMC response 3 register */
#define STM32_SDMMC_RESP4_OFFSET 0x0020 /* SDMMC response 4 register */
#define STM32_SDMMC_DTIMER_OFFSET 0x0024 /* SDMMC data timer register */
#define STM32_SDMMC_DLEN_OFFSET 0x0028 /* SDMMC data length register */
#define STM32_SDMMC_DCTRL_OFFSET 0x002c /* SDMMC data control register */
#define STM32_SDMMC_DCOUNT_OFFSET 0x0030 /* SDMMC data counter register */
#define STM32_SDMMC_STA_OFFSET 0x0034 /* SDMMC status register */
#define STM32_SDMMC_ICR_OFFSET 0x0038 /* SDMMC interrupt clear register */
#define STM32_SDMMC_MASK_OFFSET 0x003c /* SDMMC mask register */
#define STM32_SDMMC_FIFOCNT_OFFSET 0x0048 /* SDMMC FIFO counter register */
#define STM32_SDMMC_FIFO_OFFSET 0x0080 /* SDMMC data FIFO register */
/* Register Bitfield Definitions ****************************************************/
#define STM32_SDMMC_POWER_PWRCTRL_SHIFT (0) /* Bits 0-1: Power supply control bits */
#define STM32_SDMMC_POWER_PWRCTRL_MASK (3 << STM32_SDMMC_POWER_PWRCTRL_SHIFT)
# define STM32_SDMMC_POWER_PWRCTRL_OFF (0 << STM32_SDMMC_POWER_PWRCTRL_SHIFT) /* 00: Power-off: card clock stopped */
# define STM32_SDMMC_POWER_PWRCTRL_PWRUP (2 << STM32_SDMMC_POWER_PWRCTRL_SHIFT) /* 10: Reserved power-up */
# define STM32_SDMMC_POWER_PWRCTRL_ON (3 << STM32_SDMMC_POWER_PWRCTRL_SHIFT) /* 11: Power-on: card is clocked */
#define STM32_SDMMC_POWER_RESET (0) /* Reset value */
#define STM32_SDMMC_CLKCR_CLKDIV_SHIFT (0) /* Bits 7-0: Clock divide factor */
#define STM32_SDMMC_CLKCR_CLKDIV_MASK (0xff << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
#define STM32_SDMMC_CLKCR_CLKEN (1 << 8) /* Bit 8: Clock enable bit */
#define STM32_SDMMC_CLKCR_PWRSAV (1 << 9) /* Bit 9: Power saving configuration bit */
#define STM32_SDMMC_CLKCR_BYPASS (1 << 10) /* Bit 10: Clock divider bypass enable bit */
#define STM32_SDMMC_CLKCR_WIDBUS_SHIFT (11) /* Bits 12-11: Wide bus mode enable bits */
#define STM32_SDMMC_CLKCR_WIDBUS_MASK (3 << STM32_SDMMC_CLKCR_WIDBUS_SHIFT)
# define STM32_SDMMC_CLKCR_WIDBUS_D1 (0 << STM32_SDMMC_CLKCR_WIDBUS_SHIFT) /* 00: Default (STM32_SDMMC_D0) */
# define STM32_SDMMC_CLKCR_WIDBUS_D4 (1 << STM32_SDMMC_CLKCR_WIDBUS_SHIFT) /* 01: 4-wide (STM32_SDMMC_D[3:0]) */
# define STM32_SDMMC_CLKCR_WIDBUS_D8 (2 << STM32_SDMMC_CLKCR_WIDBUS_SHIFT) /* 10: 8-wide (STM32_SDMMC_D[7:0]) */
#define STM32_SDMMC_CLKCR_NEGEDGE (1 << 13) /* Bit 13: STM32_SDMMC_CK dephasing selection bit */
#define STM32_SDMMC_CLKCR_HWFC_EN (1 << 14) /* Bit 14: HW Flow Control enable */
#define STM32_SDMMC_CLKCR_RESET (0) /* Reset value */
#define STM32_SDMMC_ARG_RESET (0) /* Reset value */
#define STM32_SDMMC_CMD_CMDINDEX_SHIFT (0)
#define STM32_SDMMC_CMD_CMDINDEX_MASK (0x3f << STM32_SDMMC_CMD_CMDINDEX_SHIFT)
#define STM32_SDMMC_CMD_WAITRESP_SHIFT (6) /* Bits 7-6: Wait for response bits */
#define STM32_SDMMC_CMD_WAITRESP_MASK (3 << STM32_SDMMC_CMD_WAITRESP_SHIFT)
# define STM32_SDMMC_CMD_NORESPONSE (0 << STM32_SDMMC_CMD_WAITRESP_SHIFT) /* 00/10: No response */
# define STM32_SDMMC_CMD_SHORTRESPONSE (1 << STM32_SDMMC_CMD_WAITRESP_SHIFT) /* 01: Short response */
# define STM32_SDMMC_CMD_LONGRESPONSE (3 << STM32_SDMMC_CMD_WAITRESP_SHIFT) /* 11: Long response */
#define STM32_SDMMC_CMD_WAITINT (1 << 8) /* Bit 8: CPSM waits for interrupt request */
#define STM32_SDMMC_CMD_WAITPEND (1 << 9) /* Bit 9: CPSM Waits for ends of data transfer */
#define STM32_SDMMC_CMD_CPSMEN (1 << 10) /* Bit 10: Command path state machine enable */
#define STM32_SDMMC_CMD_SUSPEND (1 << 11) /* Bit 11: SD I/O suspend command */
#define STM32_SDMMC_CMD_ENDCMD (1 << 12) /* Bit 12: Enable CMD completion */
#define STM32_SDMMC_CMD_NIEN (1 << 13) /* Bit 13: not Interrupt Enable */
#define STM32_SDMMC_CMD_ATACMD (1 << 14) /* Bit 14: CE-ATA command */
#define STM32_SDMMC_CMD_RESET (0) /* Reset value */
#define STM32_SDMMC_RESPCMD_SHIFT (0)
#define STM32_SDMMC_RESPCMD_MASK (0x3f << STM32_SDMMC_RESPCMD_SHIFT)
#define STM32_SDMMC_DTIMER_RESET (0) /* Reset value */
#define STM32_SDMMC_DLEN_SHIFT (0)
#define STM32_SDMMC_DLEN_MASK (0x01ffffff << STM32_SDMMC_DLEN_SHIFT)
#define STM32_SDMMC_DLEN_RESET (0) /* Reset value */
#define STM32_SDMMC_DCTRL_DTEN (1 << 0) /* Bit 0: Data transfer enabled bit */
#define STM32_SDMMC_DCTRL_DTDIR (1 << 1) /* Bit 1: Data transfer direction */
#define STM32_SDMMC_DCTRL_DTMODE (1 << 2) /* Bit 2: Data transfer mode */
#define STM32_SDMMC_DCTRL_DMAEN (1 << 3) /* Bit 3: DMA enable bit */
#define STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT (4) /* Bits 7-4: Data block size */
#define STM32_SDMMC_DCTRL_DBLOCKSIZE_MASK (15 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT)
# define STM32_SDMMC_DCTRL_1BYTE (0 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT)
# define STM32_SDMMC_DCTRL_2BYTES (1 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT)
# define STM32_SDMMC_DCTRL_4BYTES (2 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT)
# define STM32_SDMMC_DCTRL_8BYTES (3 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT)
# define STM32_SDMMC_DCTRL_16BYTES (4 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT)
# define STM32_SDMMC_DCTRL_32BYTES (5 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT)
# define STM32_SDMMC_DCTRL_64BYTES (6 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT)
# define STM32_SDMMC_DCTRL_128BYTES (7 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT)
# define STM32_SDMMC_DCTRL_256BYTES (8 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT)
# define STM32_SDMMC_DCTRL_512BYTES (9 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT)
# define STM32_SDMMC_DCTRL_1KBYTE (10 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT)
# define STM32_SDMMC_DCTRL_2KBYTES (11 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT)
# define STM32_SDMMC_DCTRL_4KBYTES (12 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT)
# define STM32_SDMMC_DCTRL_8KBYTES (13 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT)
# define STM32_SDMMC_DCTRL_16KBYTES (14 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT)
#define STM32_SDMMC_DCTRL_RWSTART (1 << 8) /* Bit 8: Read wait start */
#define STM32_SDMMC_DCTRL_RWSTOP (1 << 9) /* Bit 9: Read wait stop */
#define STM32_SDMMC_DCTRL_RWMOD (1 << 10) /* Bit 10: Read wait mode */
#define STM32_SDMMC_DCTRL_SDIOEN (1 << 11) /* Bit 11: SD I/O enable functions */
#define STM32_SDMMC_DCTRL_RESET (0) /* Reset value */
#define STM32_SDMMC_DCOUNT_SHIFT (0)
#define STM32_SDMMC_DCOUNT_MASK (0x01ffffff << STM32_SDMMC_DCOUNT_SHIFT)
#define STM32_SDMMC_STA_CCRCFAIL (1 << 0) /* Bit 0: Command response CRC fail */
#define STM32_SDMMC_STA_DCRCFAIL (1 << 1) /* Bit 1: Data block CRC fail */
#define STM32_SDMMC_STA_CTIMEOUT (1 << 2) /* Bit 2: Command response timeout */
#define STM32_SDMMC_STA_DTIMEOUT (1 << 3) /* Bit 3: Data timeout */
#define STM32_SDMMC_STA_TXUNDERR (1 << 4) /* Bit 4: Transmit FIFO underrun error */
#define STM32_SDMMC_STA_RXOVERR (1 << 5) /* Bit 5: Received FIFO overrun error */
#define STM32_SDMMC_STA_CMDREND (1 << 6) /* Bit 6: Command response received */
#define STM32_SDMMC_STA_CMDSENT (1 << 7) /* Bit 7: Command sent */
#define STM32_SDMMC_STA_DATAEND (1 << 8) /* Bit 8: Data end */
#define STM32_SDMMC_STA_STBITERR (1 << 9) /* Bit 9: Start bit not detected */
#define STM32_SDMMC_STA_DBCKEND (1 << 10) /* Bit 10: Data block sent/received */
#define STM32_SDMMC_STA_CMDACT (1 << 11) /* Bit 11: Command transfer in progress */
#define STM32_SDMMC_STA_TXACT (1 << 12) /* Bit 12: Data transmit in progress */
#define STM32_SDMMC_STA_RXACT (1 << 13) /* Bit 13: Data receive in progress */
#define STM32_SDMMC_STA_TXFIFOHE (1 << 14) /* Bit 14: Transmit FIFO half empty */
#define STM32_SDMMC_STA_RXFIFOHF (1 << 15) /* Bit 15: Receive FIFO half full */
#define STM32_SDMMC_STA_TXFIFOF (1 << 16) /* Bit 16: Transmit FIFO full */
#define STM32_SDMMC_STA_RXFIFOF (1 << 17) /* Bit 17: Receive FIFO full */
#define STM32_SDMMC_STA_TXFIFOE (1 << 18) /* Bit 18: Transmit FIFO empty */
#define STM32_SDMMC_STA_RXFIFOE (1 << 19) /* Bit 19: Receive FIFO empty */
#define STM32_SDMMC_STA_TXDAVL (1 << 20) /* Bit 20: Data available in transmit FIFO */
#define STM32_SDMMC_STA_RXDAVL (1 << 21) /* Bit 21: Data available in receive FIFO */
#define STM32_SDMMC_STA_SDIOIT (1 << 22) /* Bit 22: SDIO interrupt received */
#define STM32_SDMMC_STA_CEATAEND (1 << 23) /* Bit 23: CMD6 CE-ATA command completion */
#define STM32_SDMMC_ICR_CCRCFAILC (1 << 0) /* Bit 0: CCRCFAIL flag clear bit */
#define STM32_SDMMC_ICR_DCRCFAILC (1 << 1) /* Bit 1: DCRCFAIL flag clear bit */
#define STM32_SDMMC_ICR_CTIMEOUTC (1 << 2) /* Bit 2: CTIMEOUT flag clear bit */
#define STM32_SDMMC_ICR_DTIMEOUTC (1 << 3) /* Bit 3: DTIMEOUT flag clear bit */
#define STM32_SDMMC_ICR_TXUNDERRC (1 << 4) /* Bit 4: TXUNDERR flag clear bit */
#define STM32_SDMMC_ICR_RXOVERRC (1 << 5) /* Bit 5: RXOVERR flag clear bit */
#define STM32_SDMMC_ICR_CMDRENDC (1 << 6) /* Bit 6: CMDREND flag clear bit */
#define STM32_SDMMC_ICR_CMDSENTC (1 << 7) /* Bit 7: CMDSENT flag clear bit */
#define STM32_SDMMC_ICR_DATAENDC (1 << 8) /* Bit 8: DATAEND flag clear bit */
#define STM32_SDMMC_ICR_STBITERRC (1 << 9) /* Bit 9: STBITERR flag clear bit */
#define STM32_SDMMC_ICR_DBCKENDC (1 << 10) /* Bit 10: DBCKEND flag clear bit */
#define STM32_SDMMC_ICR_SDIOITC (1 << 22) /* Bit 22: SDIOIT flag clear bit */
#define STM32_SDMMC_ICR_CEATAENDC (1 << 23) /* Bit 23: CEATAEND flag clear bit */
#define STM32_SDMMC_ICR_RESET 0x00c007ff
#define STM32_SDMMC_ICR_STATICFLAGS 0x000005ff
#define STM32_SDMMC_MASK_CCRCFAILIE (1 << 0) /* Bit 0: Command CRC fail interrupt enable */
#define STM32_SDMMC_MASK_DCRCFAILIE (1 << 1) /* Bit 1: Data CRC fail interrupt enable */
#define STM32_SDMMC_MASK_CTIMEOUTIE (1 << 2) /* Bit 2: Command timeout interrupt enable */
#define STM32_SDMMC_MASK_DTIMEOUTIE (1 << 3) /* Bit 3: Data timeout interrupt enable */
#define STM32_SDMMC_MASK_TXUNDERRIE (1 << 4) /* Bit 4: Tx FIFO underrun error interrupt enable */
#define STM32_SDMMC_MASK_RXOVERRIE (1 << 5) /* Bit 5: Rx FIFO overrun error interrupt enable */
#define STM32_SDMMC_MASK_CMDRENDIE (1 << 6) /* Bit 6: Command response received interrupt enable */
#define STM32_SDMMC_MASK_CMDSENTIE (1 << 7) /* Bit 7: Command sent interrupt enable */
#define STM32_SDMMC_MASK_DATAENDIE (1 << 8) /* Bit 8: Data end interrupt enable */
#define STM32_SDMMC_MASK_STBITERRIE (1 << 9) /* Bit 9: Start bit error interrupt enable */
#define STM32_SDMMC_MASK_DBCKENDIE (1 << 10) /* Bit 10: Data block end interrupt enable */
#define STM32_SDMMC_MASK_CMDACTIE (1 << 11) /* Bit 11: Command acting interrupt enable */
#define STM32_SDMMC_MASK_TXACTIE (1 << 12) /* Bit 12: Data transmit acting interrupt enable */
#define STM32_SDMMC_MASK_RXACTIE (1 << 13) /* Bit 13: Data receive acting interrupt enable */
#define STM32_SDMMC_MASK_TXFIFOHEIE (1 << 14) /* Bit 14: Tx FIFO half empty interrupt enable */
#define STM32_SDMMC_MASK_RXFIFOHFIE (1 << 15) /* Bit 15: Rx FIFO half full interrupt enable */
#define STM32_SDMMC_MASK_TXFIFOFIE (1 << 16) /* Bit 16: Tx FIFO full interrupt enable */
#define STM32_SDMMC_MASK_RXFIFOFIE (1 << 17) /* Bit 17: Rx FIFO full interrupt enable */
#define STM32_SDMMC_MASK_TXFIFOEIE (1 << 18) /* Bit 18: Tx FIFO empty interrupt enable */
#define STM32_SDMMC_MASK_RXFIFOEIE (1 << 19) /* Bit 19: Rx FIFO empty interrupt enable */
#define STM32_SDMMC_MASK_TXDAVLIE (1 << 20) /* Bit 20: Data available in Tx FIFO interrupt enable */
#define STM32_SDMMC_MASK_RXDAVLIE (1 << 21) /* Bit 21: Data available in Rx FIFO interrupt enable */
#define STM32_SDMMC_MASK_SDIOITIE (1 << 22) /* Bit 22: SDIO mode interrupt received interrupt enable */
#define STM32_SDMMC_MASK_CEATAENDIE (1 << 23) /* Bit 23: CE-ATA command completion interrupt enable */
#define STM32_SDMMC_MASK_RESET (0)
#define STM32_SDMMC_FIFOCNT_SHIFT (0)
#define STM32_SDMMC_FIFOCNT_MASK (0x0ffffff << STM32_SDMMC_FIFOCNT_SHIFT)
#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX77XX_SDMMC_H */
arch/arm/src/stm32f7/chip/stm32f76xx77xx_pinmap.h
+1 -1
View File
@@ -943,7 +943,7 @@
#define GPIO_SDMMC2_CMD (GPIO_ALT|GPIO_AF11|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN7)
#define GPIO_SDMMC2_D0_1 (GPIO_ALT|GPIO_AF10|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN14)
#define GPIO_SDMMC2_D1_1 (GPIO_ALT|GPIO_AF10|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN15)
#define GPIO_SDMMC2_D2_1 (GPIO_ALT|GPIO_AF10|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN)
#define GPIO_SDMMC2_D2_1 (GPIO_ALT|GPIO_AF10|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN3)
#define GPIO_SDMMC2_D3_1 (GPIO_ALT|GPIO_AF10|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN4)
#define GPIO_SDMMC2_D0_2 (GPIO_ALT|GPIO_AF11|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN9)
#define GPIO_SDMMC2_D1_2 (GPIO_ALT|GPIO_AF11|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN10)
arch/arm/src/stm32f7/chip/stm32f76xx77xx_rcc.h
+2 -2
View File
@@ -595,7 +595,7 @@
# define RCC_PLLI2SCFGR_PLLI2SN(n) ((uint32_t)(n) << RCC_PLLI2SCFGR_PLLI2SN_SHIFT)
#define RCC_PLLI2SCFGR_PLLI2SP_SHIFT (16) /* Bits 16-17: PLLI2S division factor for SPDIFRX clock */
#define RCC_PLLI2SCFGR_PLLI2SP_MASK (3 << RCC_PLLI2SCFGR_PLLI2SP_SHIFT)
# define RCC_PLLI2SCFGR_PLLI2SP(n) ((uint32_t)(n) << RCC_PLLI2SCFGR_PLLI2SP_SHIFT)
# define RCC_PLLI2SCFGR_PLLI2SP(n) ((((n)>>1)-1) << RCC_PLLI2SCFGR_PLLI2SP_SHIFT)
#define RCC_PLLI2SCFGR_PLLI2SQ_SHIFT (24) /* Bits 24-27: PLLI2S division factor for SAIs clock */
#define RCC_PLLI2SCFGR_PLLI2SQ_MASK (15 << RCC_PLLI2SCFGR_PLLI2SQ_SHIFT)
# define RCC_PLLI2SCFGR_PLLI2SQ(n) ((uint32_t)(n) << RCC_PLLI2SCFGR_PLLI2SQ_SHIFT)
@@ -610,7 +610,7 @@
# define RCC_PLLSAICFGR_PLLSAIN(n) ((n) << RCC_PLLSAICFGR_PLLSAIN_SHIFT)
#define RCC_PLLSAICFGR_PLLSAIP_SHIFT (16) /* Bits 16-17: PLLSAI division factor for 48MHz clock */
#define RCC_PLLSAICFGR_PLLSAIP_MASK (3 << RCC_PLLSAICFGR_PLLSAIP_SHIFT)
# define RCC_PLLSAICFGR_PLLSAIP(n) ((n) << RCC_PLLSAICFGR_PLLSAIP_SHIFT)
# define RCC_PLLSAICFGR_PLLSAIP(n) ((((n)>>1)-1) << RCC_PLLSAICFGR_PLLSAIP_SHIFT)
#define RCC_PLLSAICFGR_PLLSAIQ_SHIFT (24) /* Bits 24-27: PLLSAI division factor for SAI clock */
#define RCC_PLLSAICFGR_PLLSAIQ_MASK (0x0F << RCC_PLLSAICFGR_PLLSAIQ_SHIFT)
# define RCC_PLLSAICFGR_PLLSAIQ(n) ((n) << RCC_PLLSAICFGR_PLLSAIQ_SHIFT)
arch/arm/src/stm32f7/stm32_allocateheap.c
+1
View File
@@ -41,6 +41,7 @@
#include <sys/types.h>
#include <stdint.h>
#include <string.h>
#include <assert.h>
#include <debug.h>
arch/arm/src/stm32f7/stm32_irq.c
+1 -1
View File
@@ -656,7 +656,7 @@ int up_prioritize_irq(int irq, int priority)
uint32_t regval;
int shift;
DEBUGASSERT(irq >= STM32_IRQ_MEMFAULT && irq < STM32_IRQ_NIRQS &&
DEBUGASSERT(irq >= STM32_IRQ_MEMFAULT && irq < NR_IRQS &&
(unsigned)priority <= NVIC_SYSH_PRIORITY_MIN);
if (irq < STM32_IRQ_FIRST)
arch/arm/src/stm32f7/stm32_sdmmc.c
+728 -389
View File
File diff suppressed because it is too large Load Diff
arch/arm/src/stm32f7/stm32_sdmmc.h
+2 -2
View File
@@ -40,13 +40,13 @@
* Included Files
************************************************************************************/
#include "chip/stm32_sdmmc.h"
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdbool.h>
#include "chip.h"
#include "chip/stm32_sdmmc.h"
/************************************************************************************
* Public Functions
arch/sim/include/.gitignore
+1
View File
@@ -1,2 +1,3 @@
/board
/chip
configs/Kconfig
+8 -23
View File
@@ -1265,25 +1265,19 @@ config ARCH_BOARD_CUSTOM
endchoice
if !ARCH_BOARD_CUSTOM
config ARCH_BOARD_CUSTOM_DIR
string
default "configs/dummy"
config ARCH_BOARD_CUSTOM_DIR_RELPATH
bool
default y
endif # !ARCH_BOARD_CUSTOM
if ARCH_BOARD_CUSTOM
menu "Custom Board Configuration"
config ARCH_BOARD_CUSTOM_NAME
string "Custom board name"
default ""
---help---
This is a name for the board. It is not used except to return the
information via the NSH uname command.
config ARCH_BOARD_CUSTOM_DIR
string "Custom board directory"
default "configs/dummy"
default ""
---help---
If the custom board configuration is selected, then it is necessary
to also tell the build system where it can find the board directory
@@ -1300,12 +1294,6 @@ config ARCH_BOARD_CUSTOM_DIR_RELPATH
---help---
Specifies that the board directory is relative to the NuttX directory.
config ARCH_BOARD_CUSTOM_NAME
string "Custom board name"
---help---
This is a name for the board. It is not used except to return the
information via the NSH uname command.
config BOARD_CUSTOM_LEDS
bool "Custom board LEDs"
default n
@@ -1858,9 +1846,6 @@ endif
if ARCH_BOARD_SIM
source "configs/sim/Kconfig"
endif
if ARCH_BOARD_CUSTOM
source "$ARCH_BOARD_CUSTOM_DIR/Kconfig"
endif
config BOARD_CRASHDUMP
bool "Enable Board level logging of crash dumps"
configs/dummy/Kconfig
-4
View File
@@ -1,4 +0,0 @@
#
# For a description of the syntax of this configuration file,
# see the file kconfig-language.txt in the NuttX tools repository.
#
configs/mirtoo/nsh/defconfig
+9 -1
View File
@@ -319,6 +319,8 @@ CONFIG_RAM_SIZE=32768
#
CONFIG_ARCH_BOARD_MIRTOO=y
# CONFIG_ARCH_BOARD_CUSTOM is not set
CONFIG_ARCH_BOARD_CUSTOM_DIR="configs/dummy"
CONFIG_ARCH_BOARD_CUSTOM_DIR_RELPATH=y
CONFIG_ARCH_BOARD="mirtoo"
#
@@ -326,12 +328,12 @@ CONFIG_ARCH_BOARD="mirtoo"
#
CONFIG_ARCH_HAVE_LEDS=y
CONFIG_ARCH_LEDS=y
CONFIG_NSH_MMCSDMINOR=0
#
# Board-Specific Options
#
CONFIG_MIRTOO_RELEASE=2
# CONFIG_BOARD_CRASHDUMP is not set
# CONFIG_LIB_BOARDCTL is not set
#
@@ -470,7 +472,12 @@ CONFIG_DEV_NULL=y
# CONFIG_VIDEO_DEVICES is not set
# CONFIG_BCH is not set
# CONFIG_INPUT is not set
#
# IO Expander/GPIO Support
#
# CONFIG_IOEXPANDER is not set
# CONFIG_DEV_GPIO is not set
#
# LCD Driver Support
@@ -833,6 +840,7 @@ CONFIG_NSH_DISABLE_UNAME=y
# CONFIG_NSH_DISABLE_USLEEP is not set
CONFIG_NSH_DISABLE_WGET=y
CONFIG_NSH_DISABLE_XD=y
CONFIG_NSH_MMCSDMINOR=0
#
# Configure Command Options
configs/mirtoo/nxffs/defconfig
+9 -1
View File
@@ -324,6 +324,8 @@ CONFIG_RAM_SIZE=32768
#
CONFIG_ARCH_BOARD_MIRTOO=y
# CONFIG_ARCH_BOARD_CUSTOM is not set
CONFIG_ARCH_BOARD_CUSTOM_DIR="configs/dummy"
CONFIG_ARCH_BOARD_CUSTOM_DIR_RELPATH=y
CONFIG_ARCH_BOARD="mirtoo"
#
@@ -331,12 +333,12 @@ CONFIG_ARCH_BOARD="mirtoo"
#
CONFIG_ARCH_HAVE_LEDS=y
CONFIG_ARCH_LEDS=y
CONFIG_NSH_MMCSDMINOR=0
#
# Board-Specific Options
#
CONFIG_MIRTOO_RELEASE=2
# CONFIG_BOARD_CRASHDUMP is not set
CONFIG_LIB_BOARDCTL=y
# CONFIG_BOARDCTL_UNIQUEID is not set
# CONFIG_BOARDCTL_TSCTEST is not set
@@ -477,7 +479,12 @@ CONFIG_SPI=y
# CONFIG_VIDEO_DEVICES is not set
# CONFIG_BCH is not set
# CONFIG_INPUT is not set
#
# IO Expander/GPIO Support
#
# CONFIG_IOEXPANDER is not set
# CONFIG_DEV_GPIO is not set
#
# LCD Driver Support
@@ -899,6 +906,7 @@ CONFIG_NSH_DISABLE_UNAME=y
# CONFIG_NSH_DISABLE_USLEEP is not set
CONFIG_NSH_DISABLE_WGET=y
# CONFIG_NSH_DISABLE_XD is not set
CONFIG_NSH_MMCSDMINOR=0
#
# Configure Command Options
configs/nucleo-144/include/board.h
+58 -3
View File
@@ -127,8 +127,8 @@
#define CONFIG_STM32F7_PLLSAI 1
#define STM32_RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN(192)
#define STM32_RCC_PLLSAICFGR_PLLSAIP RCC_PLLSAICFGR_PLLSAIP(2)
#define STM32_RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ(2)
#define STM32_RCC_PLLSAICFGR_PLLSAIP RCC_PLLSAICFGR_PLLSAIP(8)
#define STM32_RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ(4)
#define STM32_RCC_PLLSAICFGR_PLLSAIR RCC_PLLSAICFGR_PLLSAIR(2)
/* Configure Dedicated Clock Configuration Register */
@@ -167,7 +167,7 @@
#define STM32_RCC_DCKCFGR2_I2C4SRC RCC_DCKCFGR2_I2C4SEL_HSI
#define STM32_RCC_DCKCFGR2_LPTIM1SRC RCC_DCKCFGR2_LPTIM1SEL_APB
#define STM32_RCC_DCKCFGR2_CECSRC RCC_DCKCFGR2_CECSEL_HSI
#define STM32_RCC_DCKCFGR2_CK48MSRC RCC_DCKCFGR2_CK48MSEL_PLLSAI
#define STM32_RCC_DCKCFGR2_CK48MSRC RCC_DCKCFGR2_CK48MSEL_PLL
#define STM32_RCC_DCKCFGR2_SDMMCSRC RCC_DCKCFGR2_SDMMCSEL_48MHZ
#define STM32_RCC_DCKCFGR2_SDMMC2SRC RCC_DCKCFGR2_SDMMC2SEL_48MHZ
#define STM32_RCC_DCKCFGR2_DSISRC RCC_DCKCFGR2_DSISEL_48MHZ
@@ -216,6 +216,61 @@
#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY)
#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY)
/* SDMMC dividers. Note that slower clocking is required when DMA is disabled
* in order to avoid RX overrun/TX underrun errors due to delayed responses
* to service FIFOs in interrupt driven mode. These values have not been
* tuned!!!
*
* SDMMCCLK=48MHz, SDMMC_CK=SDMMCCLK/(118+2)=400 KHz
*/
#define STM32_SDMMC_INIT_CLKDIV (118 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
/* DMA ON: SDMMCCLK=48MHz, SDMMC_CK=SDMMCCLK/(1+2)=16 MHz
* DMA OFF: SDMMCCLK=48MHz, SDMMC_CK=SDMMCCLK/(2+2)=12 MHz
*/
#ifdef CONFIG_SDIO_DMA
# define STM32_SDMMC_MMCXFR_CLKDIV (1 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
#else
# define STM32_SDMMC_MMCXFR_CLKDIV (2 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
#endif
/* DMA ON: SDMMCCLK=48MHz, SDMMC_CK=SDMMCCLK/(1+2)=16 MHz
* DMA OFF: SDMMCCLK=48MHz, SDMMC_CK=SDMMCCLK/(2+2)=12 MHz
*/
#ifdef CONFIG_SDIO_DMA
# define STM32_SDMMC_SDXFR_CLKDIV (1 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
#else
# define STM32_SDMMC_SDXFR_CLKDIV (2 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
#endif
#if defined(CONFIG_STM32F7_SDMMC2)
# define GPIO_SDMMC2_D0 GPIO_SDMMC2_D0_1
# define GPIO_SDMMC2_D1 GPIO_SDMMC2_D1_1
# define GPIO_SDMMC2_D2 GPIO_SDMMC2_D2_1
# define GPIO_SDMMC2_D3 GPIO_SDMMC2_D3_1
#endif
/* DMA Channl/Stream Selections *****************************************************/
/* Stream selections are arbitrary for now but might become important in the future
* if we set aside more DMA channels/streams.
*
* SDMMC DMA is on DMA2
*
* SDMMC1 DMA
* DMAMAP_SDMMC1_1 = Channel 4, Stream 3
* DMAMAP_SDMMC1_2 = Channel 4, Stream 6
*
* SDMMC2 DMA
* DMAMAP_SDMMC2_1 = Channel 11, Stream 0
* DMAMAP_SDMMC3_2 = Channel 11, Stream 5
*/
#define DMAMAP_SDMMC1 DMAMAP_SDMMC1_1
#define DMAMAP_SDMMC2 DMAMAP_SDMMC2_1
/* FLASH wait states
*
* --------- ---------- -----------
configs/nucleo-144/src/Makefile
+1 -1
View File
@@ -60,7 +60,7 @@ ifeq ($(CONFIG_ADC),y)
CSRCS += stm32_adc.c
endif
ifeq ($(HAVE_SDIO),y)
ifeq ($(CONFIG_MMCSD),y)
CSRCS += stm32_sdio.c
endif
configs/nucleo-144/src/nucleo-144.h
+51 -2
View File
@@ -128,8 +128,45 @@
#define NUCLEO_SPI_BUS3_CS2 10
#define NUCLEO_SPI_BUS3_CS3 11
#if defined(CONFIG_STM32_SDIO)
#define GPIO_SDIO_NCD (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI | GPIO_PORTB | GPIO_PIN15)
#if defined(CONFIG_STM32F7_SDMMC1) || defined(CONFIG_STM32F7_SDMMC2)
# define HAVE_SDIO
#endif
#if defined(CONFIG_DISABLE_MOUNTPOINT) || !defined(CONFIG_MMCSD_SDIO)
# undef HAVE_SDIO
#endif
#define SDIO_SLOTNO 0 /* Only one slot */
#ifdef HAVE_SDIO
# if defined(CONFIG_STM32F7_SDMMC1)
# define GPIO_SDMMC1_NCD (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI | GPIO_PORTC | GPIO_PIN11)
# endif
# if defined(CONFIG_NSH_MMCSDSLOTNO) && (CONFIG_NSH_MMCSDSLOTNO != 0)
# warning "Only one MMC/SD slot, slot 0"
# define CONFIG_NSH_MMCSDSLOTNO SDIO_SLOTNO
# endif
# if defined(CONFIG_NSH_MMCSDMINOR)
# define SDIO_MINOR CONFIG_NSH_MMCSDMINOR
# else
# define SDIO_MINOR 0
# endif
/* SD card bringup does not work if performed on the IDLE thread because it
* will cause waiting. Use either:
*
* CONFIG_LIB_BOARDCTL=y, OR
* CONFIG_BOARD_INITIALIZE=y && CONFIG_BOARD_INITTHREAD=y
*/
# if defined(CONFIG_BOARD_INITIALIZE) && !defined(CONFIG_LIB_BOARDCTL) && \
!defined(CONFIG_BOARD_INITTHREAD)
# warning SDIO initialization cannot be perfomed on the IDLE thread
# undef HAVE_SDIO
# endif
#endif
/************************************************************************************
@@ -196,5 +233,17 @@ int stm32_dma_alloc_init(void);
int board_adc_initialize(void);
#endif
/****************************************************************************
* Name: stm32_sdio_initialize
*
* Description:
* Called at application startup time to initialize the SCMMC functionality.
*
****************************************************************************/
#ifdef CONFIG_MMCSD
int stm32_sdio_initialize(void);
#endif
#endif /* __ASSEMBLY__ */
#endif /* __CONFIGS_NUCLEO_144_SRC_NUCLEO_144_H */
configs/nucleo-144/src/stm32_appinitialize.c
+1
View File
@@ -42,6 +42,7 @@
#include <nuttx/config.h>
#include <sys/types.h>
#include <debug.h>
#include <syslog.h>
#include "nucleo-144.h"
configs/nucleo-144/src/stm32_sdio.c
+11 -8
View File
@@ -47,10 +47,13 @@
#include <nuttx/sdio.h>
#include <nuttx/mmcsd.h>
#include "stm32.h"
#include "chip.h"
#include "nucleo-144.h"
#include "stm32_gpio.h"
#include "stm32_sdmmc.h"
#ifdef CONFIG_MMCSD
#ifdef HAVE_SDIO
/****************************************************************************
* Pre-processor Definitions
@@ -61,7 +64,7 @@
/* Card detections requires card support and a card detection GPIO */
#define HAVE_NCD 1
#if !defined(CONFIG_STM32_SDIO) || !defined(GPIO_SDIO_NCD)
#if !defined(GPIO_SDMMC1_NCD)
# undef HAVE_NCD
#endif
@@ -91,8 +94,8 @@ static int stm32_ncd_interrupt(int irq, FAR void *context)
{
bool present;
present = !stm32_gpioread(GPIO_SDIO_NCD);
if (present != g_sd_inserted)
present = !stm32_gpioread(GPIO_SDMMC1_NCD);
if (g_sdio_dev && present != g_sd_inserted)
{
sdio_mediachange(g_sdio_dev, present);
g_sd_inserted = present;
@@ -125,11 +128,11 @@ int stm32_sdio_initialize(void)
/* Configure the card detect GPIO */
stm32_configgpio(GPIO_SDIO_NCD);
stm32_configgpio(GPIO_SDMMC1_NCD);
/* Register an interrupt handler for the card detect pin */
stm32_gpiosetevent(GPIO_SDIO_NCD, true, true, true, stm32_ncd_interrupt);
stm32_gpiosetevent(GPIO_SDMMC1_NCD, true, true, true, stm32_ncd_interrupt);
#endif
/* Mount the SDIO-based MMC/SD block driver */
@@ -160,7 +163,7 @@ int stm32_sdio_initialize(void)
#ifdef HAVE_NCD
/* Use SD card detect pin to check if a card is g_sd_inserted */
cd_status = !stm32_gpioread(GPIO_SDIO_NCD);
cd_status = !stm32_gpioread(GPIO_SDMMC1_NCD);
finfo("Card detect : %d\n", cd_status);
sdio_mediachange(g_sdio_dev, cd_status);
configs/pcblogic-pic32mx/nsh/defconfig
+9 -1
View File
@@ -319,16 +319,18 @@ CONFIG_RAM_SIZE=32768
CONFIG_ARCH_BOARD_PCBLOGICPIC32MX=y
# CONFIG_ARCH_BOARD_UBW32 is not set
# CONFIG_ARCH_BOARD_CUSTOM is not set
CONFIG_ARCH_BOARD_CUSTOM_DIR="configs/dummy"
CONFIG_ARCH_BOARD_CUSTOM_DIR_RELPATH=y
CONFIG_ARCH_BOARD="pcblogic-pic32mx"
#
# Common Board Options
#
CONFIG_NSH_MMCSDMINOR=0
#
# Board-Specific Options
#
# CONFIG_BOARD_CRASHDUMP is not set
# CONFIG_LIB_BOARDCTL is not set
#
@@ -467,7 +469,12 @@ CONFIG_DEV_NULL=y
# CONFIG_VIDEO_DEVICES is not set
# CONFIG_BCH is not set
# CONFIG_INPUT is not set
#
# IO Expander/GPIO Support
#
# CONFIG_IOEXPANDER is not set
# CONFIG_DEV_GPIO is not set
#
# LCD Driver Support
@@ -846,6 +853,7 @@ CONFIG_NSH_DISABLE_LOSMART=y
# CONFIG_NSH_DISABLE_USLEEP is not set
# CONFIG_NSH_DISABLE_WGET is not set
# CONFIG_NSH_DISABLE_XD is not set
CONFIG_NSH_MMCSDMINOR=0
#
# Configure Command Options
configs/pic32mx-starterkit/nsh/defconfig
+10 -2
View File
@@ -319,6 +319,8 @@ CONFIG_RAM_SIZE=131072
CONFIG_ARCH_BOARD_PIC32MX_STARTERKIT=y
# CONFIG_ARCH_BOARD_PIC32MX7MMB is not set
# CONFIG_ARCH_BOARD_CUSTOM is not set
CONFIG_ARCH_BOARD_CUSTOM_DIR="configs/dummy"
CONFIG_ARCH_BOARD_CUSTOM_DIR_RELPATH=y
CONFIG_ARCH_BOARD="pic32mx-starterkit"
#
@@ -326,12 +328,11 @@ CONFIG_ARCH_BOARD="pic32mx-starterkit"
#
CONFIG_ARCH_HAVE_LEDS=y
CONFIG_ARCH_LEDS=y
CONFIG_NSH_MMCSDMINOR=0
CONFIG_NSH_MMCSDSLOTNO=0
#
# Board-Specific Options
#
# CONFIG_BOARD_CRASHDUMP is not set
CONFIG_LIB_BOARDCTL=y
# CONFIG_BOARDCTL_UNIQUEID is not set
# CONFIG_BOARDCTL_TSCTEST is not set
@@ -476,7 +477,12 @@ CONFIG_DEV_NULL=y
# CONFIG_VIDEO_DEVICES is not set
# CONFIG_BCH is not set
# CONFIG_INPUT is not set
#
# IO Expander/GPIO Support
#
# CONFIG_IOEXPANDER is not set
# CONFIG_DEV_GPIO is not set
#
# LCD Driver Support
@@ -909,6 +915,8 @@ CONFIG_NSH_DISABLE_LOSMART=y
# CONFIG_NSH_DISABLE_USLEEP is not set
# CONFIG_NSH_DISABLE_WGET is not set
# CONFIG_NSH_DISABLE_XD is not set
CONFIG_NSH_MMCSDMINOR=0
CONFIG_NSH_MMCSDSLOTNO=0
#
# Configure Command Options
configs/pic32mx-starterkit/nsh2/defconfig
+10 -2
View File
@@ -329,6 +329,8 @@ CONFIG_RAM_SIZE=131072
CONFIG_ARCH_BOARD_PIC32MX_STARTERKIT=y
# CONFIG_ARCH_BOARD_PIC32MX7MMB is not set
# CONFIG_ARCH_BOARD_CUSTOM is not set
CONFIG_ARCH_BOARD_CUSTOM_DIR="configs/dummy"
CONFIG_ARCH_BOARD_CUSTOM_DIR_RELPATH=y
CONFIG_ARCH_BOARD="pic32mx-starterkit"
#
@@ -336,12 +338,11 @@ CONFIG_ARCH_BOARD="pic32mx-starterkit"
#
CONFIG_ARCH_HAVE_LEDS=y
CONFIG_ARCH_LEDS=y
CONFIG_NSH_MMCSDMINOR=0
CONFIG_NSH_MMCSDSLOTNO=0
#
# Board-Specific Options
#
# CONFIG_BOARD_CRASHDUMP is not set
CONFIG_LIB_BOARDCTL=y
# CONFIG_BOARDCTL_UNIQUEID is not set
# CONFIG_BOARDCTL_TSCTEST is not set
@@ -486,7 +487,12 @@ CONFIG_DEV_NULL=y
# CONFIG_VIDEO_DEVICES is not set
# CONFIG_BCH is not set
# CONFIG_INPUT is not set
#
# IO Expander/GPIO Support
#
# CONFIG_IOEXPANDER is not set
# CONFIG_DEV_GPIO is not set
#
# LCD Driver Support
@@ -1092,6 +1098,8 @@ CONFIG_NSH_DISABLE_LOSMART=y
# CONFIG_NSH_DISABLE_USLEEP is not set
# CONFIG_NSH_DISABLE_WGET is not set
# CONFIG_NSH_DISABLE_XD is not set
CONFIG_NSH_MMCSDMINOR=0
CONFIG_NSH_MMCSDSLOTNO=0
#
# Configure Command Options
configs/pic32mx7mmb/nsh/defconfig
+11 -3
View File
@@ -337,6 +337,8 @@ CONFIG_RAM_SIZE=131072
# CONFIG_ARCH_BOARD_PIC32MX_STARTERKIT is not set
CONFIG_ARCH_BOARD_PIC32MX7MMB=y
# CONFIG_ARCH_BOARD_CUSTOM is not set
CONFIG_ARCH_BOARD_CUSTOM_DIR="configs/dummy"
CONFIG_ARCH_BOARD_CUSTOM_DIR_RELPATH=y
CONFIG_ARCH_BOARD="pic32mx7mmb"
#
@@ -344,13 +346,11 @@ CONFIG_ARCH_BOARD="pic32mx7mmb"
#
CONFIG_ARCH_HAVE_LEDS=y
CONFIG_ARCH_LEDS=y
CONFIG_NSH_MMCSDMINOR=0
CONFIG_NSH_MMCSDSLOTNO=0
CONFIG_NSH_MMCSDSPIPORTNO=1
#
# Board-Specific Options
#
# CONFIG_BOARD_CRASHDUMP is not set
CONFIG_LIB_BOARDCTL=y
# CONFIG_BOARDCTL_UNIQUEID is not set
CONFIG_BOARDCTL_USBDEVCTRL=y
@@ -505,7 +505,12 @@ CONFIG_SPI=y
# CONFIG_VIDEO_DEVICES is not set
# CONFIG_BCH is not set
# CONFIG_INPUT is not set
#
# IO Expander/GPIO Support
#
# CONFIG_IOEXPANDER is not set
# CONFIG_DEV_GPIO is not set
#
# LCD Driver Support
@@ -1155,6 +1160,9 @@ CONFIG_NSH_DISABLE_LOSMART=y
# CONFIG_NSH_DISABLE_USLEEP is not set
# CONFIG_NSH_DISABLE_WGET is not set
# CONFIG_NSH_DISABLE_XD is not set
CONFIG_NSH_MMCSDMINOR=0
CONFIG_NSH_MMCSDSLOTNO=0
CONFIG_NSH_MMCSDSPIPORTNO=1
#
# Configure Command Options
configs/pic32mz-starterkit/nsh/defconfig
+10 -2
View File
@@ -244,6 +244,8 @@ CONFIG_RAM_SIZE=131072
#
CONFIG_ARCH_BOARD_PIC32MZ_STARTERKIT=y
# CONFIG_ARCH_BOARD_CUSTOM is not set
CONFIG_ARCH_BOARD_CUSTOM_DIR="configs/dummy"
CONFIG_ARCH_BOARD_CUSTOM_DIR_RELPATH=y
CONFIG_ARCH_BOARD="pic32mz-starterkit"
#
@@ -253,12 +255,11 @@ CONFIG_ARCH_HAVE_LEDS=y
CONFIG_ARCH_LEDS=y
CONFIG_ARCH_HAVE_BUTTONS=y
# CONFIG_ARCH_BUTTONS is not set
CONFIG_NSH_MMCSDMINOR=0
CONFIG_NSH_MMCSDSLOTNO=0
#
# Board-Specific Options
#
# CONFIG_BOARD_CRASHDUMP is not set
CONFIG_LIB_BOARDCTL=y
# CONFIG_BOARDCTL_UNIQUEID is not set
# CONFIG_BOARDCTL_TSCTEST is not set
@@ -403,7 +404,12 @@ CONFIG_DEV_NULL=y
# CONFIG_VIDEO_DEVICES is not set
# CONFIG_BCH is not set
# CONFIG_INPUT is not set
#
# IO Expander/GPIO Support
#
# CONFIG_IOEXPANDER is not set
# CONFIG_DEV_GPIO is not set
#
# LCD Driver Support
@@ -836,6 +842,8 @@ CONFIG_NSH_DISABLE_LOSMART=y
# CONFIG_NSH_DISABLE_USLEEP is not set
# CONFIG_NSH_DISABLE_WGET is not set
# CONFIG_NSH_DISABLE_XD is not set
CONFIG_NSH_MMCSDMINOR=0
CONFIG_NSH_MMCSDSLOTNO=0
#
# Configure Command Options
configs/sure-pic32mx/nsh/defconfig
+9 -1
View File
@@ -318,6 +318,8 @@ CONFIG_RAM_SIZE=32768
#
CONFIG_ARCH_BOARD_SUREPIC32MX=y
# CONFIG_ARCH_BOARD_CUSTOM is not set
CONFIG_ARCH_BOARD_CUSTOM_DIR="configs/dummy"
CONFIG_ARCH_BOARD_CUSTOM_DIR_RELPATH=y
CONFIG_ARCH_BOARD="sure-pic32mx"
#
@@ -328,13 +330,13 @@ CONFIG_ARCH_LEDS=y
CONFIG_ARCH_HAVE_BUTTONS=y
# CONFIG_ARCH_BUTTONS is not set
CONFIG_ARCH_HAVE_IRQBUTTONS=y
CONFIG_NSH_MMCSDMINOR=0
#
# Board-Specific Options
#
CONFIG_ARCH_DBDP11215=y
# CONFIG_ARCH_DBDP11212 is not set
# CONFIG_BOARD_CRASHDUMP is not set
CONFIG_LIB_BOARDCTL=y
# CONFIG_BOARDCTL_UNIQUEID is not set
# CONFIG_BOARDCTL_TSCTEST is not set
@@ -479,7 +481,12 @@ CONFIG_DEV_NULL=y
# CONFIG_VIDEO_DEVICES is not set
# CONFIG_BCH is not set
# CONFIG_INPUT is not set
#
# IO Expander/GPIO Support
#
# CONFIG_IOEXPANDER is not set
# CONFIG_DEV_GPIO is not set
#
# LCD Driver Support
@@ -860,6 +867,7 @@ CONFIG_NSH_DISABLE_LOSMART=y
# CONFIG_NSH_DISABLE_USLEEP is not set
# CONFIG_NSH_DISABLE_WGET is not set
# CONFIG_NSH_DISABLE_XD is not set
CONFIG_NSH_MMCSDMINOR=0
#
# Configure Command Options
configs/sure-pic32mx/usbnsh/defconfig
+9 -1
View File
@@ -319,6 +319,8 @@ CONFIG_RAM_SIZE=32768
#
CONFIG_ARCH_BOARD_SUREPIC32MX=y
# CONFIG_ARCH_BOARD_CUSTOM is not set
CONFIG_ARCH_BOARD_CUSTOM_DIR="configs/dummy"
CONFIG_ARCH_BOARD_CUSTOM_DIR_RELPATH=y
CONFIG_ARCH_BOARD="sure-pic32mx"
#
@@ -329,13 +331,13 @@ CONFIG_ARCH_LEDS=y
CONFIG_ARCH_HAVE_BUTTONS=y
# CONFIG_ARCH_BUTTONS is not set
CONFIG_ARCH_HAVE_IRQBUTTONS=y
CONFIG_NSH_MMCSDMINOR=0
#
# Board-Specific Options
#
CONFIG_ARCH_DBDP11215=y
# CONFIG_ARCH_DBDP11212 is not set
# CONFIG_BOARD_CRASHDUMP is not set
CONFIG_LIB_BOARDCTL=y
# CONFIG_BOARDCTL_UNIQUEID is not set
CONFIG_BOARDCTL_USBDEVCTRL=y
@@ -481,7 +483,12 @@ CONFIG_DEV_NULL=y
# CONFIG_VIDEO_DEVICES is not set
# CONFIG_BCH is not set
# CONFIG_INPUT is not set
#
# IO Expander/GPIO Support
#
# CONFIG_IOEXPANDER is not set
# CONFIG_DEV_GPIO is not set
#
# LCD Driver Support
@@ -902,6 +909,7 @@ CONFIG_NSH_DISABLE_LOSMART=y
# CONFIG_NSH_DISABLE_USLEEP is not set
# CONFIG_NSH_DISABLE_WGET is not set
# CONFIG_NSH_DISABLE_XD is not set
CONFIG_NSH_MMCSDMINOR=0
#
# Configure Command Options
configs/ubw32/nsh/defconfig
+10 -2
View File
@@ -319,6 +319,8 @@ CONFIG_RAM_SIZE=32768
# CONFIG_ARCH_BOARD_PCBLOGICPIC32MX is not set
CONFIG_ARCH_BOARD_UBW32=y
# CONFIG_ARCH_BOARD_CUSTOM is not set
CONFIG_ARCH_BOARD_CUSTOM_DIR="configs/dummy"
CONFIG_ARCH_BOARD_CUSTOM_DIR_RELPATH=y
CONFIG_ARCH_BOARD="ubw32"
#
@@ -329,12 +331,11 @@ CONFIG_ARCH_LEDS=y
CONFIG_ARCH_HAVE_BUTTONS=y
# CONFIG_ARCH_BUTTONS is not set
CONFIG_ARCH_HAVE_IRQBUTTONS=y
CONFIG_NSH_MMCSDMINOR=0
CONFIG_NSH_MMCSDSLOTNO=0
#
# Board-Specific Options
#
# CONFIG_BOARD_CRASHDUMP is not set
CONFIG_LIB_BOARDCTL=y
# CONFIG_BOARDCTL_UNIQUEID is not set
# CONFIG_BOARDCTL_TSCTEST is not set
@@ -479,7 +480,12 @@ CONFIG_DEV_NULL=y
# CONFIG_VIDEO_DEVICES is not set
# CONFIG_BCH is not set
# CONFIG_INPUT is not set
#
# IO Expander/GPIO Support
#
# CONFIG_IOEXPANDER is not set
# CONFIG_DEV_GPIO is not set
#
# LCD Driver Support
@@ -881,6 +887,8 @@ CONFIG_NSH_DISABLE_LOSMART=y
# CONFIG_NSH_DISABLE_USLEEP is not set
# CONFIG_NSH_DISABLE_WGET is not set
# CONFIG_NSH_DISABLE_XD is not set
CONFIG_NSH_MMCSDMINOR=0
CONFIG_NSH_MMCSDSLOTNO=0
#
# Configure Command Options
drivers/ioexpander/gpio.c
+11 -8
View File
@@ -86,7 +86,7 @@ static const struct file_operations g_gpio_output_ops =
{
gpio_open, /* open */
gpio_close, /* close */
NULL, /* read */
gpio_read, /* read */
gpio_write, /* write */
NULL, /* seek */
gpio_ioctl /* ioctl */
@@ -183,12 +183,13 @@ static int gpio_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
*/
case GPIO_WRITE:
if (dev->output)
if (dev->gp_output)
{
FAR struct gpio_output_dev_s *outdev =
(FAR struct gpio_output_dev_s *)dev;
DEBUGASSERT(outdev->gpout_write != NULL);
DEBUGASSERT(outdev->gpout_write != NULL &&
((arg == 0UL) || (arg == 1UL)));
ret = outdev->gpout_write(outdev, (int)arg);
}
else
@@ -204,7 +205,7 @@ static int gpio_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
*/
case GPIO_READ:
if (dev->output)
if (dev->gp_output)
{
FAR struct gpio_output_dev_s *outdev =
(FAR struct gpio_output_dev_s *)dev;
@@ -242,9 +243,10 @@ int gpio_input_register(FAR struct gpio_input_dev_s *dev, int minor)
{
char devname[16];
DEBUGASSERT((unsigned int)minor < 100);
snprintf(devname, 16, "/dev/gpin%u", (unsigned int)minor);
DEBUGASSERT(dev != NULL && !dev->gpin_output && dev->gpin_read != NULL &&
(unsigned int)minor < 100);
snprintf(devname, 16, "/dev/gpin%u", (unsigned int)minor);
return register_driver(devname, &g_gpio_input_ops, 0444, dev);
}
@@ -260,9 +262,10 @@ int gpio_output_register(FAR struct gpio_output_dev_s *dev, int minor)
{
char devname[16];
DEBUGASSERT((unsigned int)minor < 100);
snprintf(devname, 16, "/dev/gpout%u", (unsigned int)minor);
DEBUGASSERT(dev != NULL && dev->gpout_output && dev->gpout_read != NULL &&
dev->gpout_write != NULL &&(unsigned int)minor < 100);
snprintf(devname, 16, "/dev/gpout%u", (unsigned int)minor);
return register_driver(devname, &g_gpio_output_ops, 0222, dev);
}
include/nuttx/ioexpander/gpio.h
+20 -6
View File
@@ -70,27 +70,41 @@
struct gpio_common_dev_s
{
bool output;
uint8_t unused[3];
bool gp_output;
uint8_t gp_unused[3];
};
/* The interface to a GPIO input pin */
struct gpio_input_dev_s
{
bool output;
uint8_t unused[3];
/* Common fields */
bool gpin_output;
uint8_t gpin_unused[3];
/* Fields unique to input pins */
CODE int (*gpin_read)(FAR struct gpio_input_dev_s *dev);
/* Lower-half private definitions may follow */
};
/* The interface to a GPIO input pin */
struct gpio_output_dev_s
{
bool output;
uint8_t unused[3];
/* Common fields */
bool gpout_output;
uint8_t gpout_unused[3];
/* Fields unique to output pins */
CODE int (*gpout_read)(FAR struct gpio_output_dev_s *dev);
CODE int (*gpout_write)(FAR struct gpio_output_dev_s *dev, int value);
/* Lower-half private definitions may follow */
};
/****************************************************************************
tools/README.txt
+1 -1
View File
@@ -580,7 +580,7 @@ refresh.sh
This is a bash script that automatics refreshing of board default
configuration (defconfig) files. It does not do anything special
thet you cannot do manually, but is useful for me when I have to
that you cannot do manually, but is useful for me when I have to
update dozens of confuration files.
Configuration files have to be updated because over time, the