mirror of
https://github.com/apache/nuttx.git
synced 2026-05-23 14:58:13 +08:00
STM32H5 I2C Driver
Added I2C driver for the STM32H5. This driver uses the STM32H7 I2C driver as a base. The primary difference is setclock dynamically sets the I2C TIMINGR register instead of using hardcoded values. This allows the I2C peripherals to use any of the input clocks and set to any speed 0-1MHz. Additionally, Kconfig options were made available to set the Digital Noise Filter (DNF), Analog Noise Filter, I2C Clock source (i2c_ker_ck), as well as set i2c rise/fall times which are crucial to timing. Care must be taken when setting the clock source and filters, as not all settings are compatible with all i2c clock frequencies.
This commit is contained in:
Kyle Wilson
Xiang Xiao
@@ -366,6 +366,30 @@ config STM32H5_LPUART1
|
||||
select ARCH_HAVE_SERIAL_TERMIOS
|
||||
select STM32H5_USART
|
||||
|
||||
config STM32H5_I2C
|
||||
bool
|
||||
default n
|
||||
|
||||
config STM32H5_I2C1
|
||||
bool "I2C1"
|
||||
default n
|
||||
select STM32H5_I2C
|
||||
|
||||
config STM32H5_I2C2
|
||||
bool "I2C2"
|
||||
default n
|
||||
select STM32H5_I2C
|
||||
|
||||
config STM32H5_I2C3
|
||||
bool "I2C3"
|
||||
default n
|
||||
select STM32H5_I2C
|
||||
|
||||
config STM32H5_I2C4
|
||||
bool "I2C4"
|
||||
default n
|
||||
select STM32H5_I2C
|
||||
|
||||
endmenu
|
||||
|
||||
|
||||
@@ -1061,4 +1085,212 @@ config STM32H5_NO_PHY
|
||||
|
||||
endmenu # Ethernet MAC Configuration
|
||||
|
||||
|
||||
menu "I2C Configuration"
|
||||
depends on STM32H5_I2C
|
||||
|
||||
menu "Clock Selection"
|
||||
|
||||
choice
|
||||
depends on STM32H5_I2C1
|
||||
prompt "I2C1 Input Clock Selection"
|
||||
default STM32H5_I2C1_CLK_PCLK1
|
||||
config STM32H5_I2C1_CLK_CSI
|
||||
bool "CSI"
|
||||
config STM32H5_I2C1_CLK_HSI
|
||||
bool "HSI"
|
||||
config STM32H5_I2C1_CLK_PCLK1
|
||||
bool "PCLK1"
|
||||
config STM32H5_I2C1_CLK_PLL3R
|
||||
bool "PLL3R"
|
||||
endchoice
|
||||
choice
|
||||
depends on STM32H5_I2C2
|
||||
prompt "I2C2 Input Clock Selection"
|
||||
default STM32H5_I2C2_CLK_PCLK1
|
||||
config STM32H5_I2C2_CLK_CSI
|
||||
bool "CSI"
|
||||
config STM32H5_I2C2_CLK_HSI
|
||||
bool "HSI"
|
||||
config STM32H5_I2C2_CLK_PCLK1
|
||||
bool "PCLK1"
|
||||
config STM32H5_I2C2_CLK_PLL3R
|
||||
bool "PLL3R"
|
||||
endchoice
|
||||
choice
|
||||
depends on STM32H5_I2C3
|
||||
prompt "I2C3 Input Clock Selection"
|
||||
default STM32H5_I2C3_CLK_PCLK3
|
||||
config STM32H5_I2C3_CLK_CSI
|
||||
bool "CSI"
|
||||
config STM32H5_I2C3_CLK_HSI
|
||||
bool "HSI"
|
||||
config STM32H5_I2C3_CLK_PCLK3
|
||||
bool "PCLK3"
|
||||
config STM32H5_I2C3_CLK_PLL3R
|
||||
bool "PLL3R"
|
||||
endchoice
|
||||
choice
|
||||
depends on STM32H5_I2C4
|
||||
prompt "I2C4 Input Clock Selection"
|
||||
default STM32H5_I2C4_CLK_PCLK3
|
||||
config STM32H5_I2C4_CLK_CSI
|
||||
bool "CSI"
|
||||
config STM32H5_I2C4_CLK_HSI
|
||||
bool "HSI"
|
||||
config STM32H5_I2C4_CLK_PCLK3
|
||||
bool "PCLK3"
|
||||
config STM32H5_I2C4_CLK_PLL3R
|
||||
bool "PLL3R"
|
||||
endchoice
|
||||
|
||||
endmenu
|
||||
|
||||
menu "Rise/Fall Override"
|
||||
config STM32H5_I2C1_RF_OVERRIDE
|
||||
bool "I2C1"
|
||||
default n
|
||||
depends on STM32H5_I2C1
|
||||
config STM32H5_I2C2_RF_OVERRIDE
|
||||
bool "I2C2"
|
||||
default n
|
||||
depends on STM32H5_I2C2
|
||||
config STM32H5_I2C3_RF_OVERRIDE
|
||||
bool "I2C3"
|
||||
default n
|
||||
depends on STM32H5_I2C3
|
||||
config STM32H5_I2C4_RF_OVERRIDE
|
||||
bool "I2C4"
|
||||
default n
|
||||
depends on STM32H5_I2C4
|
||||
|
||||
menu "Rise/Fall Values"
|
||||
config STM32H5_I2C1_RISE
|
||||
int "I2C1 Rise Time (ns)"
|
||||
range 0 1000
|
||||
default 20
|
||||
depends on STM32H5_I2C1_RF_OVERRIDE
|
||||
config STM32H5_I2C1_FALL
|
||||
int "I2C1 Fall Time (ns)"
|
||||
range 0 300
|
||||
default 20
|
||||
depends on STM32H5_I2C1_RF_OVERRIDE
|
||||
config STM32H5_I2C2_RISE
|
||||
int "I2C2 Rise Time (ns)"
|
||||
range 0 1000
|
||||
default 20
|
||||
depends on STM32H5_I2C2_RF_OVERRIDE
|
||||
config STM32H5_I2C2_FALL
|
||||
int "I2C2 Fall Time (ns)"
|
||||
range 0 300
|
||||
default 20
|
||||
depends on STM32H5_I2C2_RF_OVERRIDE
|
||||
config STM32H5_I2C3_RISE
|
||||
int "I2C3 Rise Time (ns)"
|
||||
range 0 1000
|
||||
default 20
|
||||
depends on STM32H5_I2C3_RF_OVERRIDE
|
||||
config STM32H5_I2C3_FALL
|
||||
int "I2C3 Fall Time (ns)"
|
||||
range 0 300
|
||||
default 20
|
||||
depends on STM32H5_I2C3_RF_OVERRIDE
|
||||
config STM32H5_I2C4_RISE
|
||||
int "I2C4 Rise Time (ns)"
|
||||
range 0 1000
|
||||
default 20
|
||||
depends on STM32H5_I2C4_RF_OVERRIDE
|
||||
config STM32H5_I2C4_FALL
|
||||
int "I2C4 Fall Time (ns)"
|
||||
range 0 300
|
||||
default 20
|
||||
depends on STM32H5_I2C4_RF_OVERRIDE
|
||||
endmenu
|
||||
endmenu
|
||||
|
||||
menu "Filtering"
|
||||
|
||||
menu "Digital Filters"
|
||||
config STM32H5_I2C1_DNF
|
||||
int "I2C1 Digital Noise Filter"
|
||||
range 0 15
|
||||
default 0
|
||||
depends on STM32H5_I2C1
|
||||
config STM32H5_I2C2_DNF
|
||||
int "I2C2 Digital Noise Filter"
|
||||
range 0 15
|
||||
default 0
|
||||
depends on STM32H5_I2C2
|
||||
config STM32H5_I2C3_DNF
|
||||
int "I2C3 Digital Noise Filter"
|
||||
range 0 15
|
||||
default 0
|
||||
depends on STM32H5_I2C3
|
||||
config STM32H5_I2C4_DNF
|
||||
int "I2C4 Digital Noise Filter"
|
||||
range 0 15
|
||||
default 0
|
||||
depends on STM32H5_I2C4
|
||||
endmenu
|
||||
|
||||
menu "Analog Filters"
|
||||
config STM32H5_I2C1_ANFOFF
|
||||
int "Turn off I2C1 Analog Filter (0=on, 1=off)"
|
||||
default 1
|
||||
range 0 1
|
||||
depends on STM32H5_I2C1
|
||||
|
||||
config STM32H5_I2C2_ANFOFF
|
||||
int "Turn off I2C2 Analog Filter (0=on, 1=off)"
|
||||
default 1
|
||||
range 0 1
|
||||
depends on STM32H5_I2C2
|
||||
|
||||
config STM32H5_I2C3_ANFOFF
|
||||
int "Turn off I2C3 Analog Filter (0=on, 1=off)"
|
||||
default 1
|
||||
range 0 1
|
||||
depends on STM32H5_I2C3
|
||||
|
||||
config STM32H5_I2C4_ANFOFF
|
||||
int "Turn off I2C4 Analog Filter (0=on, 1=off)"
|
||||
default 1
|
||||
range 0 1
|
||||
depends on STM32H5_I2C4
|
||||
endmenu
|
||||
|
||||
endmenu
|
||||
|
||||
config STM32H5_I2C_DYNTIMEO
|
||||
bool "Use dynamic timeouts"
|
||||
default n
|
||||
depends on STM32H5_I2C
|
||||
|
||||
config STM32H5_I2C_DYNTIMEO_USECPERBYTE
|
||||
int "Timeout Microseconds per Byte"
|
||||
default 500
|
||||
depends on STM32H5_I2C_DYNTIMEO
|
||||
|
||||
config STM32H5_I2C_DYNTIMEO_STARTSTOP
|
||||
int "Timeout for Start/Stop (Milliseconds)"
|
||||
default 1000
|
||||
depends on STM32H5_I2C_DYNTIMEO
|
||||
|
||||
config STM32H5_I2CTIMEOSEC
|
||||
int "Timeout seconds"
|
||||
default 0
|
||||
depends on STM32H5_I2C
|
||||
|
||||
config STM32H5_I2CTIMEOMS
|
||||
int "Timeout Milliseconds"
|
||||
default 500
|
||||
depends on STM32H5_I2C && !STM32H5_I2C_DYNTIMEO
|
||||
|
||||
config STM32H5_I2CTIMEOTICKS
|
||||
int "Timeout for Done and Stop (ticks)"
|
||||
default 500
|
||||
depends on STM32H5_I2C && !STM32H5_I2C_DYNTIMEO
|
||||
|
||||
endmenu # "I2C Configuration"
|
||||
|
||||
endif # ARCH_CHIP_STM32H5
|
||||
|
||||
@@ -44,6 +44,10 @@ ifeq ($(CONFIG_TIMER),y)
|
||||
CHIP_CSRCS += stm32h5_tim_lowerhalf.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_STM32H5_I2C),y)
|
||||
CHIP_CSRCS += stm32_i2c.c
|
||||
endif
|
||||
|
||||
# Required chip type specific files
|
||||
|
||||
ifeq ($(CONFIG_STM32H5_STM32H5XXXX),y)
|
||||
|
||||
@@ -100,6 +100,42 @@
|
||||
|
||||
#define GPIO_MCO_0 (GPIO_ALT|GPIO_AF0|GPIO_PORTA|GPIO_PIN8)
|
||||
|
||||
/* I2C */
|
||||
|
||||
#define GPIO_I2C1_SDA_1 (GPIO_ALT|GPIO_AF4|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN7)
|
||||
#define GPIO_I2C1_SDA_2 (GPIO_ALT|GPIO_AF4|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN9)
|
||||
#define GPIO_I2C1_SCL_1 (GPIO_ALT|GPIO_AF4|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN6)
|
||||
#define GPIO_I2C1_SCL_2 (GPIO_ALT|GPIO_AF4|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN8)
|
||||
#define GPIO_I2C1_SMBA_1 (GPIO_ALT|GPIO_AF4|GPIO_PORTB|GPIO_PIN5)
|
||||
|
||||
#define GPIO_I2C2_SDA_1 (GPIO_ALT|GPIO_AF4|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN11)
|
||||
#define GPIO_I2C2_SDA_2 (GPIO_ALT|GPIO_AF4|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN12)
|
||||
#define GPIO_I2C2_SDA_3 (GPIO_ALT|GPIO_AF4|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN3)
|
||||
#define GPIO_I2C2_SDA_4 (GPIO_ALT|GPIO_AF4|GPIO_OPENDRAIN|GPIO_PORTH|GPIO_PIN5)
|
||||
#define GPIO_I2C2_SCL_1 (GPIO_ALT|GPIO_AF4|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN10)
|
||||
#define GPIO_I2C2_SCL_2 (GPIO_ALT|GPIO_AF4|GPIO_OPENDRAIN|GPIO_PORTF|GPIO_PIN1)
|
||||
#define GPIO_I2C2_SCL_3 (GPIO_ALT|GPIO_AF4|GPIO_OPENDRAIN|GPIO_PORTH|GPIO_PIN4)
|
||||
#define GPIO_I2C2_SMBA_1 (GPIO_ALT|GPIO_AF4|GPIO_PORTH|GPIO_PIN6)
|
||||
|
||||
#define GPIO_I2C3_SDA_1 (GPIO_ALT|GPIO_AF4|GPIO_OPENDRAIN|GPIO_PORTC|GPIO_PIN9)
|
||||
#define GPIO_I2C3_SDA_2 (GPIO_ALT|GPIO_AF4|GPIO_OPENDRAIN|GPIO_PORTH|GPIO_PIN8)
|
||||
#define GPIO_I2C3_SCL_1 (GPIO_ALT|GPIO_AF4|GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN8)
|
||||
#define GPIO_I2C3_SCL_2 (GPIO_ALT|GPIO_AF4|GPIO_OPENDRAIN|GPIO_PORTH|GPIO_PIN7)
|
||||
#define GPIO_I2C3_SMBA_1 (GPIO_ALT|GPIO_AF4|GPIO_PORTA|GPIO_PIN9)
|
||||
#define GPIO_I2C3_SMBA_2 (GPIO_ALT|GPIO_AF4|GPIO_PORTH|GPIO_PIN9)
|
||||
|
||||
#define GPIO_I2C4_SDA_1 (GPIO_ALT|GPIO_AF6|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN7)
|
||||
#define GPIO_I2C4_SDA_2 (GPIO_ALT|GPIO_AF6|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN9)
|
||||
#define GPIO_I2C4_SDA_3 (GPIO_ALT|GPIO_AF4|GPIO_OPENDRAIN|GPIO_PORTD|GPIO_PIN13)
|
||||
#define GPIO_I2C4_SDA_4 (GPIO_ALT|GPIO_AF4|GPIO_OPENDRAIN|GPIO_PORTF|GPIO_PIN15)
|
||||
#define GPIO_I2C4_SCL_1 (GPIO_ALT|GPIO_AF6|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN6)
|
||||
#define GPIO_I2C4_SCL_2 (GPIO_ALT|GPIO_AF6|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN8)
|
||||
#define GPIO_I2C4_SCL_3 (GPIO_ALT|GPIO_AF4|GPIO_OPENDRAIN|GPIO_PORTD|GPIO_PIN12)
|
||||
#define GPIO_I2C4_SCL_4 (GPIO_ALT|GPIO_AF4|GPIO_OPENDRAIN|GPIO_PORTF|GPIO_PIN5)
|
||||
#define GPIO_I2C4_SMBA_1 (GPIO_ALT|GPIO_AF6|GPIO_PORTB|GPIO_PIN5)
|
||||
#define GPIO_I2C4_SMBA_2 (GPIO_ALT|GPIO_AF4|GPIO_PORTD|GPIO_PIN11)
|
||||
#define GPIO_I2C4_SMBA_3 (GPIO_ALT|GPIO_AF4|GPIO_PORTF|GPIO_PIN13)
|
||||
|
||||
/* JTAG */
|
||||
|
||||
#define GPIO_JTCK_SWCLK_0 (GPIO_ALT|GPIO_AF0|GPIO_PORTA|GPIO_PIN14)
|
||||
|
||||
@@ -27,74 +27,74 @@
|
||||
|
||||
/* Register Offsets *********************************************************/
|
||||
|
||||
#define STM32_I2CCR1_OFFSET 0x0000 /* Control register 1 (32-bit) */
|
||||
#define STM32_I2CCR2_OFFSET 0x0004 /* Control register 2 (32-bit) */
|
||||
#define STM32_I2COAR1_OFFSET 0x0008 /* Own address register 1 (16-bit) */
|
||||
#define STM32_I2COAR2_OFFSET 0x000c /* Own address register 2 (16-bit) */
|
||||
#define STM32_I2CTIMINGR_OFFSET 0x0010 /* Timing register */
|
||||
#define STM32_I2CTIMEOUTR_OFFSET 0x0014 /* Timeout register */
|
||||
#define STM32_I2CISR_OFFSET 0x0018 /* Interrupt and Status register */
|
||||
#define STM32_I2CICR_OFFSET 0x001c /* Interrupt clear register */
|
||||
#define STM32_I2CPECR_OFFSET 0x0020 /* Packet error checking register */
|
||||
#define STM32_I2CRXDR_OFFSET 0x0024 /* Receive data register */
|
||||
#define STM32_I2CTXDR_OFFSET 0x0028 /* Transmit data register */
|
||||
#define STM32_I2C_CR1_OFFSET 0x0000 /* Control register 1 (32-bit) */
|
||||
#define STM32_I2C_CR2_OFFSET 0x0004 /* Control register 2 (32-bit) */
|
||||
#define STM32_I2C_OAR1_OFFSET 0x0008 /* Own address register 1 (16-bit) */
|
||||
#define STM32_I2C_OAR2_OFFSET 0x000c /* Own address register 2 (16-bit) */
|
||||
#define STM32_I2C_TIMINGR_OFFSET 0x0010 /* Timing register */
|
||||
#define STM32_I2C_TIMEOUTR_OFFSET 0x0014 /* Timeout register */
|
||||
#define STM32_I2C_ISR_OFFSET 0x0018 /* Interrupt and Status register */
|
||||
#define STM32_I2C_ICR_OFFSET 0x001c /* Interrupt clear register */
|
||||
#define STM32_I2C_PECR_OFFSET 0x0020 /* Packet error checking register */
|
||||
#define STM32_I2C_RXDR_OFFSET 0x0024 /* Receive data register */
|
||||
#define STM32_I2C_TXDR_OFFSET 0x0028 /* Transmit data register */
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#if STM32H5_NI2C > 0
|
||||
# define STM32_I2C1_CR1 (STM32_I2C1_BASE+STM32_I2CCR1_OFFSET)
|
||||
# define STM32_I2C1_CR2 (STM32_I2C1_BASE+STM32_I2CCR2_OFFSET)
|
||||
# define STM32_I2C1_OAR1 (STM32_I2C1_BASE+STM32_I2COAR1_OFFSET)
|
||||
# define STM32_I2C1_OAR2 (STM32_I2C1_BASE+STM32_I2COAR2_OFFSET)
|
||||
# define STM32_I2C1_TIMINGR (STM32_I2C1_BASE+STM32_I2CTIMINGR_OFFSET)
|
||||
# define STM32_I2C1_TIMEOUTR (STM32_I2C1_BASE+STM32_I2CTIMEOUTR_OFFSET)
|
||||
# define STM32_I2C1_ISR (STM32_I2C1_BASE+STM32_I2CISR_OFFSET)
|
||||
# define STM32_I2C1_ICR (STM32_I2C1_BASE+STM32_I2CICR_OFFSET)
|
||||
# define STM32_I2C1_PECR (STM32_I2C1_BASE+STM32_I2CPECR_OFFSET)
|
||||
# define STM32_I2C1_RXDR (STM32_I2C1_BASE+STM32_I2CRXDR_OFFSET)
|
||||
# define STM32_I2C1_TXDR (STM32_I2C1_BASE+STM32_I2CTXDR_OFFSET)
|
||||
# define STM32_I2C1_CR1 (STM32_I2C1_BASE+STM32_I2C_CR1_OFFSET)
|
||||
# define STM32_I2C1_CR2 (STM32_I2C1_BASE+STM32_I2C_CR2_OFFSET)
|
||||
# define STM32_I2C1_OAR1 (STM32_I2C1_BASE+STM32_I2C_OAR1_OFFSET)
|
||||
# define STM32_I2C1_OAR2 (STM32_I2C1_BASE+STM32_I2C_OAR2_OFFSET)
|
||||
# define STM32_I2C1_TIMINGR (STM32_I2C1_BASE+STM32_I2C_TIMINGR_OFFSET)
|
||||
# define STM32_I2C1_TIMEOUTR (STM32_I2C1_BASE+STM32_I2C_TIMEOUTR_OFFSET)
|
||||
# define STM32_I2C1_ISR (STM32_I2C1_BASE+STM32_I2C_ISR_OFFSET)
|
||||
# define STM32_I2C1_ICR (STM32_I2C1_BASE+STM32_I2C_ICR_OFFSET)
|
||||
# define STM32_I2C1_PECR (STM32_I2C1_BASE+STM32_I2C_PECR_OFFSET)
|
||||
# define STM32_I2C1_RXDR (STM32_I2C1_BASE+STM32_I2C_RXDR_OFFSET)
|
||||
# define STM32_I2C1_TXDR (STM32_I2C1_BASE+STM32_I2C_TXDR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32H5_NI2C > 1
|
||||
# define STM32_I2C2_CR1 (STM32_I2C2_BASE+STM32_I2CCR1_OFFSET)
|
||||
# define STM32_I2C2_CR2 (STM32_I2C2_BASE+STM32_I2CCR2_OFFSET)
|
||||
# define STM32_I2C2_OAR1 (STM32_I2C2_BASE+STM32_I2COAR1_OFFSET)
|
||||
# define STM32_I2C2_OAR2 (STM32_I2C2_BASE+STM32_I2COAR2_OFFSET)
|
||||
# define STM32_I2C2_TIMINGR (STM32_I2C2_BASE+STM32_I2CTIMINGR_OFFSET)
|
||||
# define STM32_I2C2_TIMEOUTR (STM32_I2C2_BASE+STM32_I2CTIMEOUTR_OFFSET)
|
||||
# define STM32_I2C2_ISR (STM32_I2C2_BASE+STM32_I2CISR_OFFSET)
|
||||
# define STM32_I2C2_ICR (STM32_I2C2_BASE+STM32_I2CICR_OFFSET)
|
||||
# define STM32_I2C2_PECR (STM32_I2C2_BASE+STM32_I2CPECR_OFFSET)
|
||||
# define STM32_I2C2_RXDR (STM32_I2C2_BASE+STM32_I2CRXDR_OFFSET)
|
||||
# define STM32_I2C2_TXDR (STM32_I2C2_BASE+STM32_I2CTXDR_OFFSET)
|
||||
# define STM32_I2C2_CR1 (STM32_I2C2_BASE+STM32_I2C_CR1_OFFSET)
|
||||
# define STM32_I2C2_CR2 (STM32_I2C2_BASE+STM32_I2C_CR2_OFFSET)
|
||||
# define STM32_I2C2_OAR1 (STM32_I2C2_BASE+STM32_I2C_OAR1_OFFSET)
|
||||
# define STM32_I2C2_OAR2 (STM32_I2C2_BASE+STM32_I2C_OAR2_OFFSET)
|
||||
# define STM32_I2C2_TIMINGR (STM32_I2C2_BASE+STM32_I2C_TIMINGR_OFFSET)
|
||||
# define STM32_I2C2_TIMEOUTR (STM32_I2C2_BASE+STM32_I2C_TIMEOUTR_OFFSET)
|
||||
# define STM32_I2C2_ISR (STM32_I2C2_BASE+STM32_I2C_ISR_OFFSET)
|
||||
# define STM32_I2C2_ICR (STM32_I2C2_BASE+STM32_I2C_ICR_OFFSET)
|
||||
# define STM32_I2C2_PECR (STM32_I2C2_BASE+STM32_I2C_PECR_OFFSET)
|
||||
# define STM32_I2C2_RXDR (STM32_I2C2_BASE+STM32_I2C_RXDR_OFFSET)
|
||||
# define STM32_I2C2_TXDR (STM32_I2C2_BASE+STM32_I2C_TXDR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32H5_NI2C > 2
|
||||
# define STM32_I2C3_CR1 (STM32_I2C3_BASE+STM32_I2CCR1_OFFSET)
|
||||
# define STM32_I2C3_CR2 (STM32_I2C3_BASE+STM32_I2CCR2_OFFSET)
|
||||
# define STM32_I2C3_OAR1 (STM32_I2C3_BASE+STM32_I2COAR1_OFFSET)
|
||||
# define STM32_I2C3_OAR2 (STM32_I2C3_BASE+STM32_I2COAR2_OFFSET)
|
||||
# define STM32_I2C3_TIMINGR (STM32_I2C3_BASE+STM32_I2CTIMINGR_OFFSET)
|
||||
# define STM32_I2C3_TIMEOUTR (STM32_I2C3_BASE+STM32_I2CTIMEOUTR_OFFSET)
|
||||
# define STM32_I2C3_ISR (STM32_I2C3_BASE+STM32_I2CISR_OFFSET)
|
||||
# define STM32_I2C3_ICR (STM32_I2C3_BASE+STM32_I2CICR_OFFSET)
|
||||
# define STM32_I2C3_PECR (STM32_I2C3_BASE+STM32_I2CPECR_OFFSET)
|
||||
# define STM32_I2C3_RXDR (STM32_I2C3_BASE+STM32_I2CRXDR_OFFSET)
|
||||
# define STM32_I2C3_TXDR (STM32_I2C3_BASE+STM32_I2CTXDR_OFFSET)
|
||||
# define STM32_I2C3_CR1 (STM32_I2C3_BASE+STM32_I2C_CR1_OFFSET)
|
||||
# define STM32_I2C3_CR2 (STM32_I2C3_BASE+STM32_I2C_CR2_OFFSET)
|
||||
# define STM32_I2C3_OAR1 (STM32_I2C3_BASE+STM32_I2C_OAR1_OFFSET)
|
||||
# define STM32_I2C3_OAR2 (STM32_I2C3_BASE+STM32_I2C_OAR2_OFFSET)
|
||||
# define STM32_I2C3_TIMINGR (STM32_I2C3_BASE+STM32_I2C_TIMINGR_OFFSET)
|
||||
# define STM32_I2C3_TIMEOUTR (STM32_I2C3_BASE+STM32_I2C_TIMEOUTR_OFFSET)
|
||||
# define STM32_I2C3_ISR (STM32_I2C3_BASE+STM32_I2C_ISR_OFFSET)
|
||||
# define STM32_I2C3_ICR (STM32_I2C3_BASE+STM32_I2C_ICR_OFFSET)
|
||||
# define STM32_I2C3_PECR (STM32_I2C3_BASE+STM32_I2C_PECR_OFFSET)
|
||||
# define STM32_I2C3_RXDR (STM32_I2C3_BASE+STM32_I2C_RXDR_OFFSET)
|
||||
# define STM32_I2C3_TXDR (STM32_I2C3_BASE+STM32_I2C_TXDR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32H5_NI2C > 3
|
||||
# define STM32_I2C4_CR1 (STM32_I2C4_BASE+STM32_I2CCR1_OFFSET)
|
||||
# define STM32_I2C4_CR2 (STM32_I2C4_BASE+STM32_I2CCR2_OFFSET)
|
||||
# define STM32_I2C4_OAR1 (STM32_I2C4_BASE+STM32_I2COAR1_OFFSET)
|
||||
# define STM32_I2C4_OAR2 (STM32_I2C4_BASE+STM32_I2COAR2_OFFSET)
|
||||
# define STM32_I2C4_TIMINGR (STM32_I2C4_BASE+STM32_I2CTIMINGR_OFFSET)
|
||||
# define STM32_I2C4_TIMEOUTR (STM32_I2C4_BASE+STM32_I2CTIMEOUTR_OFFSET)
|
||||
# define STM32_I2C4_ISR (STM32_I2C4_BASE+STM32_I2CISR_OFFSET)
|
||||
# define STM32_I2C4_ICR (STM32_I2C4_BASE+STM32_I2CICR_OFFSET)
|
||||
# define STM32_I2C4_PECR (STM32_I2C4_BASE+STM32_I2CPECR_OFFSET)
|
||||
# define STM32_I2C4_RXDR (STM32_I2C4_BASE+STM32_I2CRXDR_OFFSET)
|
||||
# define STM32_I2C4_TXDR (STM32_I2C4_BASE+STM32_I2CTXDR_OFFSET)
|
||||
# define STM32_I2C4_CR1 (STM32_I2C4_BASE+STM32_I2C_CR1_OFFSET)
|
||||
# define STM32_I2C4_CR2 (STM32_I2C4_BASE+STM32_I2C_CR2_OFFSET)
|
||||
# define STM32_I2C4_OAR1 (STM32_I2C4_BASE+STM32_I2C_OAR1_OFFSET)
|
||||
# define STM32_I2C4_OAR2 (STM32_I2C4_BASE+STM32_I2C_OAR2_OFFSET)
|
||||
# define STM32_I2C4_TIMINGR (STM32_I2C4_BASE+STM32_I2C_TIMINGR_OFFSET)
|
||||
# define STM32_I2C4_TIMEOUTR (STM32_I2C4_BASE+STM32_I2C_TIMEOUTR_OFFSET)
|
||||
# define STM32_I2C4_ISR (STM32_I2C4_BASE+STM32_I2C_ISR_OFFSET)
|
||||
# define STM32_I2C4_ICR (STM32_I2C4_BASE+STM32_I2C_ICR_OFFSET)
|
||||
# define STM32_I2C4_PECR (STM32_I2C4_BASE+STM32_I2C_PECR_OFFSET)
|
||||
# define STM32_I2C4_RXDR (STM32_I2C4_BASE+STM32_I2C_RXDR_OFFSET)
|
||||
# define STM32_I2C4_TXDR (STM32_I2C4_BASE+STM32_I2C_TXDR_OFFSET)
|
||||
#endif
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
@@ -119,12 +119,12 @@
|
||||
#define I2C_CR1_RXDMAEN (1 << 15) /* Bit 15: DMA reception requests enable */
|
||||
#define I2C_CR1_SBC (1 << 16) /* Bit 16: Slave byte control */
|
||||
#define I2C_CR1_NOSTRETCH (1 << 17) /* Bit 17: Clock stretching disable */
|
||||
#define I2C_CR1_WUPEN (1 << 18) /* Bit 18: Wakeup from STOP enable */
|
||||
#define I2C_CR1_GCEN (1 << 19) /* Bit 19: General call enable */
|
||||
#define I2C_CR1_SMBHEN (1 << 20) /* Bit 20: SMBus Host address enable */
|
||||
#define I2C_CR1_SMBDEN (1 << 21) /* Bit 21: SMBus Device Default address enable */
|
||||
#define I2C_CR1_ALERTEN (1 << 22) /* Bit 22: SMBus alert enable */
|
||||
#define I2C_CR1_PECEN (1 << 23) /* Bit 23: PEC enable */
|
||||
#define I2C_CR1_FMP (1 << 24) /* Bit 24: FMP enable */
|
||||
|
||||
/* Control register 2 */
|
||||
|
||||
@@ -204,6 +204,18 @@
|
||||
# define I2C_TIMEOUTR_B(n) ((n) << I2C_TIMEOUTR_B_SHIFT)
|
||||
#define I2C_TIMEOUTR_TEXTEN (1 << 31) /* Bits 31: Extended clock timeout enable */
|
||||
|
||||
/* Fields unique to the Interrupt and Status register */
|
||||
|
||||
#define I2C_ISR_TXE (1 << 0) /* Bit 0: Transmit data register empty (transmitters) */
|
||||
#define I2C_ISR_TXIS (1 << 1) /* Bit 1: Transmit interrupt status (transmitters) */
|
||||
#define I2C_ISR_RXNE (1 << 2) /* Bit 2: Receive data register not empty (receivers) */
|
||||
#define I2C_ISR_TC (1 << 6) /* Bit 6: Transfer Complete (master) */
|
||||
#define I2C_ISR_TCR (1 << 7) /* Bit 7: Transfer Complete Reload */
|
||||
#define I2C_ISR_BUSY (1 << 15) /* Bit 15: Bus busy */
|
||||
#define I2C_ISR_DIR (1 << 16) /* Bit 16: Transfer direction (slave) */
|
||||
#define I2C_ISR_ADDCODE_SHIFT (17) /* Bits 17-23: Address match code (slave) */
|
||||
#define I2C_ISR_ADDCODE_MASK (0x7f << I2C_ISR_ADDCODE_SHIFT)
|
||||
|
||||
/* Interrupt and Status register and interrupt clear register */
|
||||
|
||||
/* Common interrupt bits */
|
||||
@@ -218,18 +230,6 @@
|
||||
#define I2C_INT_TIMEOUT (1 << 12) /* Bit 12: Timeout or tLOW detection flag */
|
||||
#define I2C_INT_ALERT (1 << 13) /* Bit 13: SMBus alert */
|
||||
|
||||
/* Fields unique to the Interrupt and Status register */
|
||||
|
||||
#define I2C_ISR_TXE (1 << 0) /* Bit 0: Transmit data register empty (transmitters) */
|
||||
#define I2C_ISR_TXIS (1 << 1) /* Bit 1: Transmit interrupt status (transmitters) */
|
||||
#define I2C_ISR_RXNE (1 << 2) /* Bit 2: Receive data register not empty (receivers) */
|
||||
#define I2C_ISR_TC (1 << 6) /* Bit 6: Transfer Complete (master) */
|
||||
#define I2C_ISR_TCR (1 << 7) /* Bit 7: Transfer Complete Reload */
|
||||
#define I2C_ISR_BUSY (1 << 15) /* Bit 15: Bus busy */
|
||||
#define I2C_ISR_DIR (1 << 16) /* Bit 16: Transfer direction (slave) */
|
||||
#define I2C_ISR_ADDCODE_SHIFT (17) /* Bits 17-23: Address match code (slave) */
|
||||
#define I2C_ISR_ADDCODE_MASK (0x7f << I2C_ISR_ADDCODE_SHIFT)
|
||||
|
||||
#define I2C_ISR_ERRORMASK (I2C_INT_BERR | I2C_INT_ARLO | I2C_INT_OVR | I2C_INT_PECERR | I2C_INT_TIMEOUT)
|
||||
|
||||
#define I2C_ICR_CLEARMASK (I2C_INT_ADDR | I2C_INT_NACK | I2C_INT_STOP | I2C_INT_BERR | I2C_INT_ARLO \
|
||||
|
||||
@@ -42,4 +42,5 @@
|
||||
#include "stm32_rcc.h"
|
||||
#include "stm32_uart.h"
|
||||
#include "stm32_lowputc.h"
|
||||
#include "stm32_i2c.h"
|
||||
#endif /* __ARCH_ARM_SRC_STM32H5_STM32_H */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,89 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/stm32h5/stm32_i2c.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32H5_STM32_I2C_H
|
||||
#define __ARCH_ARM_SRC_STM32H5_STM32_I2C_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <nuttx/i2c/i2c_master.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "hardware/stm32h5xxx_i2c.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* If a dynamic timeout is selected, then a non-negative, non-zero micro-
|
||||
* seconds per byte value must be provided as well.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_STM32H5_I2C_DYNTIMEO
|
||||
# if CONFIG_STM32H5_I2C_DYNTIMEO_USECPERBYTE < 1
|
||||
# warning "Ignoring CONFIG_STM32H5_I2C_DYNTIMEO because of CONFIG_STM32H5_I2C_DYNTIMEO_USECPERBYTE"
|
||||
# undef CONFIG_STM32H5_I2C_DYNTIMEO
|
||||
# endif
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_i2cbus_initialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize the selected I2C port. And return a unique instance of struct
|
||||
* struct i2c_master_s. This function may be called to obtain multiple
|
||||
* instances of the interface, each of which may be set up with a
|
||||
* different frequency and slave address.
|
||||
*
|
||||
* Input Parameters:
|
||||
* Port number (for hardware that has multiple I2C interfaces)
|
||||
*
|
||||
* Returned Value:
|
||||
* Valid I2C device structure reference on success; a NULL on failure
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
struct i2c_master_s *stm32_i2cbus_initialize(int port);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_i2cbus_uninitialize
|
||||
*
|
||||
* Description:
|
||||
* De-initialize the selected I2C port, and power down the device.
|
||||
*
|
||||
* Input Parameters:
|
||||
* Device structure as returned by the stm32_i2cbus_initialize()
|
||||
*
|
||||
* Returned Value:
|
||||
* OK on success, ERROR when internal reference count mismatch or dev
|
||||
* points to invalid hardware device.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int stm32_i2cbus_uninitialize(struct i2c_master_s *dev);
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32H5_STM32_I2C_H */
|
||||
Reference in New Issue
Block a user