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arch/arm/src/tiva/cc13xx/cc13x2_v1_trim.c and cc13x2_cc26x2_v1_rom.c: Review and modified for coding style. Now pass tools/nxstyle wihout complaint.
This commit is contained in:
@@ -1,10 +1,11 @@
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/************************************************************************************
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/****************************************************************************
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* arch/arm/src/tiva/cc13xx/cc13x2_cc26x2_v1_rom.c
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*
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* Copyright (C) 2019 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* This is a port of TI's setup_rom.c file which has a fully compatible BSD license:
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* This is a port of TI's setup_rom.c file which has a fully compatible BSD
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* license:
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*
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* Copyright (c) 2015-2017, Texas Instruments Incorporated
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* All rights reserved.
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@@ -36,11 +37,11 @@
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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****************************************************************************/
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/************************************************************************************
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/****************************************************************************
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* Included Files
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************************************************************************************/
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****************************************************************************/
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#include <stdint.h>
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@@ -59,13 +60,13 @@
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#include "cc13xx/cc13x2_cc26x2_v1_rom.h"
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/************************************************************************************
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/****************************************************************************
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* Public Functions
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************************************************************************************/
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****************************************************************************/
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/************************************************************************************
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/****************************************************************************
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* Name: rom_setup_stepvaddrtrimto
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************************************************************************************/
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****************************************************************************/
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void rom_setup_stepvaddrtrimto(uint32_t tocode)
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{
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@@ -74,37 +75,41 @@ void rom_setup_stepvaddrtrimto(uint32_t tocode)
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int32_t current_trim;
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target_trim =
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rom_signextend_vddrtrim(tocode &
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(ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_MASK >>
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ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_SHIFT));
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rom_signextend_vddrtrim(tocode & (ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_MASK >>
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ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_SHIFT));
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current_trim =
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rom_signextend_vddrtrim((getreg16(TIVA_ADI3_REFSYS_DCDCCTL0) &
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ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_MASK) >>
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ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_SHIFT);
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ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_MASK) >>
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ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_SHIFT);
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if (target_trim != current_trim)
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{
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pmctl_regsetctrl =
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(getreg32(TIVA_AON_PMCTL_RESETCTL) &
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~AON_PMCTL_RESETCTL_MCU_WARM_RESET);
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pmctl_regsetctrl = (getreg32(TIVA_AON_PMCTL_RESETCTL) &
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~AON_PMCTL_RESETCTL_MCU_WARM_RESET);
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if (pmctl_regsetctrl & AON_PMCTL_RESETCTL_VDDR_LOSS_EN)
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{
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putreg32(pmctl_regsetctrl & ~AON_PMCTL_RESETCTL_VDDR_LOSS_EN,
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TIVA_AON_PMCTL_RESETCTL);
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(void)getreg32(TIVA_AON_RTC_SYNC); /* Wait for VDDR_LOSS_EN
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* setting to propagate */
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TIVA_AON_PMCTL_RESETCTL);
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/* Wait for VDDR_LOSS_EN setting to propagate */
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(void)getreg32(TIVA_AON_RTC_SYNC);
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}
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while (target_trim != current_trim)
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{
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(void)getreg32(TIVA_AON_RTC_SYNCLF); /* Wait for next edge
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* on SCLK_LF (positive
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* or negative) */
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/* Wait for next edge on SCLK_LF (positive or negative) */
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(void)getreg32(TIVA_AON_RTC_SYNCLF);
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if (target_trim > current_trim)
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current_trim++;
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{
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current_trim++;
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}
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else
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current_trim--;
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{
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current_trim--;
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}
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putreg8(((getreg8(TIVA_ADI3_REFSYS_DCDCCTL0) &
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~ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_MASK) |
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@@ -114,32 +119,32 @@ void rom_setup_stepvaddrtrimto(uint32_t tocode)
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TIVA_ADI3_REFSYS_DCDCCTL0);
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}
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(void)getreg32(TIVA_AON_RTC_SYNCLF); /* Wait for next edge on
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* SCLK_LF (positive or
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* negative) */
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/* Wait for next edge on SCLK_LF (positive or negative) */
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if (pmctl_regsetctrl & AON_PMCTL_RESETCTL_VDDR_LOSS_EN)
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(void)getreg32(TIVA_AON_RTC_SYNCLF);
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if ((pmctl_regsetctrl & AON_PMCTL_RESETCTL_VDDR_LOSS_EN) != 0)
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{
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(void)getreg32(TIVA_AON_RTC_SYNCLF); /* Wait for next edge
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* on SCLK_LF (positive
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* or negative) */
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/* Wait for next edge on SCLK_LF (positive or negative) */
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(void)getreg32(TIVA_AON_RTC_SYNCLF); /* Wait for next edge
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* on SCLK_LF (positive
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* or negative) */
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(void)getreg32(TIVA_AON_RTC_SYNCLF);
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/* Wait for next edge on SCLK_LF (positive or negative) */
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(void)getreg32(TIVA_AON_RTC_SYNCLF);
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putreg32(pmctl_regsetctrl, TIVA_AON_PMCTL_RESETCTL);
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(void)getreg32(TIVA_AON_RTC_SYNC); /* And finally wait for
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* VDDR_LOSS_EN setting to
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* propagate */
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/* And finally wait for VDDR_LOSS_EN setting to propagate */
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(void)getreg32(TIVA_AON_RTC_SYNC);
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}
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}
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}
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/************************************************************************************
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/****************************************************************************
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* Name: rom_setup_coldreset_from_shutdown_cfg1
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************************************************************************************/
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****************************************************************************/
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void rom_setup_coldreset_from_shutdown_cfg1(uint32_t ccfg_modeconf)
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{
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@@ -147,15 +152,17 @@ void rom_setup_coldreset_from_shutdown_cfg1(uint32_t ccfg_modeconf)
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uint32_t clrbits;
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/* Check for CC1352 boost mode The combination VDDR_EXT_LOAD=0 and
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* VDDS_BOD_LEVEL=1 is defined to select boost mode */
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* VDDS_BOD_LEVEL=1 is defined to select boost mode
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*/
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if (((ccfg_modeconf & CCFG_MODE_CONF_VDDR_EXT_LOAD) == 0) &&
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((ccfg_modeconf & CCFG_MODE_CONF_VDDS_BOD_LEVEL) != 0))
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if ((ccfg_modeconf & CCFG_MODE_CONF_VDDR_EXT_LOAD) == 0 &&
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(ccfg_modeconf & CCFG_MODE_CONF_VDDS_BOD_LEVEL) != 0)
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{
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/* Set VDDS_BOD trim - using masked write {MASK8:DATA8} - TRIM_VDDS_BOD
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* is bits[7:3] of ADI3..REFSYSCTL1 - Needs a positive transition on
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* BOD_BG_TRIM_EN (bit[7] of REFSYSCTL3) to latch new VDDS BOD. Set to 0
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* first to guarantee a positive transition. */
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* first to guarantee a positive transition.
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*/
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putreg8(ADI3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN,
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TIVA_ADI3_REFSYS_CLR + TIVA_ADI3_REFSYS_REFSYSCTL3_OFFSET);
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@@ -166,25 +173,26 @@ void rom_setup_coldreset_from_shutdown_cfg1(uint32_t ccfg_modeconf)
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putreg16((ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_MASK << 8) |
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(ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_31),
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TIVA_ADI3_REFSYS_MASK8B + (TIVA_ADI3_REFSYS_REFSYSCTL1_OFFSET * 2));
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TIVA_ADI3_REFSYS_MASK8B +
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(TIVA_ADI3_REFSYS_REFSYSCTL1_OFFSET * 2));
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putreg8(ADI3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN,
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TIVA_ADI3_REFSYS_SET + TIVA_ADI3_REFSYS_REFSYSCTL3_OFFSET);
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rom_setup_stepvaddrtrimto((getreg32(TIVA_FCFG1_VOLT_TRIM) &
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FCFG1_VOLT_TRIM_VDDR_TRIM_HH_MASK) >>
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FCFG1_VOLT_TRIM_VDDR_TRIM_HH_SHIFT);
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FCFG1_VOLT_TRIM_VDDR_TRIM_HH_MASK) >>
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FCFG1_VOLT_TRIM_VDDR_TRIM_HH_SHIFT);
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}
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/* 1. Do not allow DCDC to be enabled if in external regulator mode.
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* Preventing this by setting both the RECHARGE and the ACTIVE bits bit in
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* the CCFG_MODE_CONF copy register (ccfg_modeconf). 2. Adjusted battery
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* monitor low limit in internal regulator mode. This is done by setting
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* AON_BATMON_FLASHPUMPP0_LOWLIM=0 in internal regulator mode.
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* Preventing this by setting both the RECHARGE and the ACTIVE bits bit
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* in the CCFG_MODE_CONF copy register (ccfg_modeconf).
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* 2. Adjusted battery monitor low limit in internal regulator mode. This
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* is done by setting AON_BATMON_FLASHPUMPP0_LOWLIM=0 in internal
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* regulator mode.
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*/
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if (getreg32(TIVA_AON_PMCTL_PWRCTL) &
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AON_PMCTL_PWRCTL_EXT_REG_MODE)
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if ((getreg32(TIVA_AON_PMCTL_PWRCTL) & AON_PMCTL_PWRCTL_EXT_REG_MODE) != 0)
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{
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ccfg_modeconf |= (CCFG_MODE_CONF_DCDC_RECHARGE |
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CCFG_MODE_CONF_DCDC_ACTIVE);
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File diff suppressed because it is too large
Load Diff
@@ -279,7 +279,7 @@ void __start(void)
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showprogress('E');
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#endif
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#ifdef CONFIG_TIVA_CC26X2_POWERLIB /* REVISIT */
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#ifdef CONFIG_TIVA_CC26X2_POWERLIB /* REVISIT: Used with CC13x2 as well. */
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/* Initialize the Power Manager internal state. This must be called prior
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* to any other Power API.
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*/
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