fix some code style

2026-05-28 03:45:50 +08:00 · 2020-12-22 17:41:41 +08:00
parent 12258d72d2
commit d354a2f19f
43 changed files with 5073 additions and 6127 deletions
@@ -1,6 +1,9 @@
 /****************************************************************************
 * arch/risc-v/include/bl602/chip.h
 *
 * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved.
 * Author: Gregory Nutt <gnutt@nuttx.org>
 *
 * Licensed to the Apache Software Foundation (ASF) under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.  The
@@ -1,6 +1,9 @@
 /****************************************************************************
 * arch/risc-v/include/bl602/irq.h
 *
 * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved.
 * Author: Gregory Nutt <gnutt@nuttx.org>
 *
 * Licensed to the Apache Software Foundation (ASF) under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.  The
@@ -1,6 +1,9 @@
 ############################################################################
 # arch/risc-v/src/bl602/Make.defs
 #
 #   Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved.
 #   Author: Gregory Nutt <gnutt@nuttx.org>
 #
 # Licensed to the Apache Software Foundation (ASF) under one or more
 # contributor license agreements.  See the NOTICE file distributed with
 # this work for additional information regarding copyright ownership.  The
@@ -46,11 +49,14 @@ endif
 # Specify our C code within this directory to be included
 CHIP_CSRCS  = bl602_allocateheap.c
 CHIP_CSRCS += bl602_idle.c bl602_irq.c bl602_irq_dispatch.c
-CHIP_CSRCS += bl602_serial.c bl602_lowputc.c
+CHIP_CSRCS += bl602_serial.c bl602_lowputc.c bl602_tim.c
 CHIP_CSRCS += bl602_start.c bl602_timerisr.c
 ifeq ($(CONFIG_TIMER),y)
-CHIP_CSRCS  += bl602_tim.c bl602_tim_lowerhalf.c bl602_oneshot_lowerhalf.c
+CHIP_CSRCS  += bl602_tim_lowerhalf.c
 endif
 ifeq ($(CONFIG_ONESHOT),y)
 CHIP_CSRCS  += bl602_oneshot_lowerhalf.c
 endif
 CHIP_CSRCS += bl602_glb.c bl602_gpio.c bl602_hbn.c
@@ -1,6 +1,9 @@
 /****************************************************************************
 * arch/risc-v/src/bl602/bl602_allocateheap.c
 *
 * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved.
 * Author: Gregory Nutt <gnutt@nuttx.org>
 *
 * Licensed to the Apache Software Foundation (ASF) under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.  The
@@ -1,6 +1,9 @@
 /****************************************************************************
 * arch/risc-v/src/bl602/bl602_boot2.h
 *
 * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved.
 * Author: Gregory Nutt <gnutt@nuttx.org>
 *
 * Licensed to the Apache Software Foundation (ASF) under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.  The
@@ -31,45 +34,42 @@
 * Pre-processor Definitions
 ****************************************************************************/
 /* Partition table error type definition */
 #define PT_ERROR_SUCCESS 0 /* Partition table error type:success */
 #define PT_ERROR_TABLE_NOT_VALID \
  1 /* Partition table error type:entry not found */
 #define PT_ERROR_ENTRY_NOT_FOUND \
  2 /* Partition table error type:entry not found */
 #define PT_ERROR_ENTRY_UPDATE_FAIL \
  3                      /* Partition table error type:entry update fail */
 #define PT_ERROR_CRC32 4 /* Partition table error type:crc32 error */
 #define PT_ERROR_PARAMETER \
  5 /* Partition table error type:input parameter error */
 #define PT_ERROR_FALSH_READ \
  6 /* Partition table error type:flash read error */
 #define PT_ERROR_FALSH_WRITE \
  7 /* Partition table error type:flash write error */
 #define PT_ERROR_FALSH_ERASE \
  8 /* Partition table error type:flash erase error */
 /* Partition id type definition */
 #define PT_TABLE_ID_0       0 /* Partition table ID 0 */
 #define PT_TABLE_ID_1       1 /* Partition table ID 1 */
 #define PT_TABLE_ID_INVALID 2 /* Partition table ID invalid */
 /* Partition id type definition */
 #define PT_ENTRY_FW_CPU0 0  /* Partition entry type:CPU0 firmware */
 #define PT_ENTRY_FW_CPU1 1  /* Partition entry type:CPU1 firmware */
 #define PT_ENTRY_MAX     16 /* Partition entry type:Max */
 /****************************************************************************
 * Public Types
 ****************************************************************************/
 #ifndef __ASSEMBLY__
 /* Partition table error type definition */
 enum pt_table_error_e
 {
  PT_ERROR_SUCCESS,           /* Partition table error type:success */
  PT_ERROR_TABLE_NOT_VALID,   /* Partition table error type:entry not found */
  PT_ERROR_ENTRY_NOT_FOUND,   /* Partition table error type:entry not found */
  PT_ERROR_ENTRY_UPDATE_FAIL, /* Partition table error type:entry update fail
                               */
  PT_ERROR_CRC32,       /* Partition table error type:crc32 error */
  PT_ERROR_PARAMETER,   /* Partition table error type:input parameter error */
  PT_ERROR_FALSH_READ,  /* Partition table error type:flash read error */
  PT_ERROR_FALSH_WRITE, /* Partition table error type:flash write error */
  PT_ERROR_FALSH_ERASE  /* Partition table error type:flash erase error */
 };
 /* Partition id type definition */
 enum pt_table_id_e
 {
  PT_TABLE_ID_0,       /* Partition table ID 0 */
  PT_TABLE_ID_1,       /* Partition table ID 1 */
  PT_TABLE_ID_INVALID, /* Partition table ID invalid */
 };
 /* Partition id type definition */
 enum pt_table_entry_type_e
 {
  PT_ENTRY_FW_CPU0,  /* Partition entry type:CPU0 firmware */
  PT_ENTRY_FW_CPU1,  /* Partition entry type:CPU1 firmware */
  PT_ENTRY_MAX = 16, /* Partition entry type:Max */
 };
 /* Partition table config definition */
@@ -1,6 +1,9 @@
 /****************************************************************************
 * arch/risc-v/src/bl602/bl602_config.h
 *
 * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved.
 * Author: Gregory Nutt <gnutt@nuttx.org>
 *
 * Licensed to the Apache Software Foundation (ASF) under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.  The
@@ -1,6 +1,9 @@
 /****************************************************************************
 * arch/risc-v/src/bl602/bl602_entry.S
 *
 * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved.
 * Author: Gregory Nutt <gnutt@nuttx.org>
 *
 * Licensed to the Apache Software Foundation (ASF) under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.  The
@@ -24,121 +27,128 @@
 #include <arch/csr.h>
-	.section .init
+    .section .init
-	.globl bl602_start
+    .globl bl602_start
-	.globl __start
+    .globl __start
-	.type bl602_start,@function
+    .type bl602_start,@function
 __start:
 bl602_start:
-	.cfi_startproc
+    .cfi_startproc
-	.cfi_undefined ra
+    .cfi_undefined ra
-  .option push
+    .option push
-  .option norelax
+    .option norelax
  /*disable IRQ*/
-	li t0, MSTATUS_MIE
+    li t0, MSTATUS_MIE
-	csrc mstatus, t0
+    csrc mstatus, t0
-	la gp, __global_pointer$
+    la gp, __global_pointer$
 .option pop
-	la sp, _sp_main
+    la sp, _sp_main
 #ifndef RUN_IN_RAM
 	/* Load boot2 partition address */
-	la a0, __boot2_pt_addr_src
+    /* Load boot2 partition address */
 	la a1, __boot2_pt_addr_start
 	la a2, __boot2_pt_addr_end
 	bgeu a1, a2, 2f
-1:
+    la a0, __boot2_pt_addr_src
-	lw t0, (a0)
+    la a1, __boot2_pt_addr_start
-	sw t0, (a1)
+    la a2, __boot2_pt_addr_end
-	addi a0, a0, 4
+    bgeu a1, a2, bl602_entry_load_boot2_partiton_address_end
 	addi a1, a1, 4
 	bltu a1, a2, 1b
-2:
+bl602_entry_load_boot2_partiton_address_loop:
-	/* Load boot2 flashCfg address */
+    lw t0, (a0)
    sw t0, (a1)
    addi a0, a0, 4
    addi a1, a1, 4
    bltu a1, a2, bl602_entry_load_boot2_partiton_address_loop
-	jal boot2_get_flash_addr
+bl602_entry_load_boot2_partiton_address_end:
 	la a1, __boot2_flash_cfg_start
 	la a2, __boot2_flash_cfg_end
 	bgeu a1, a2, 2f
-1:
+    /* Load boot2 flashCfg address */
 	lw t0, (a0)
 	sw t0, (a1)
 	addi a0, a0, 4
 	addi a1, a1, 4
 	bltu a1, a2, 1b
-2:
+    jal boot2_get_flash_addr
    la a1, __boot2_flash_cfg_start
    la a2, __boot2_flash_cfg_end
    bgeu a1, a2, bl602_entry_load_boot2_flashcfg_address_end
 bl602_entry_load_boot2_flashcfg_address_loop:
    lw t0, (a0)
    sw t0, (a1)
    addi a0, a0, 4
    addi a1, a1, 4
    bltu a1, a2, bl602_entry_load_boot2_flashcfg_address_loop
 bl602_entry_load_boot2_flashcfg_address_end:
 #endif
 	/* Load data section */
-	la a0, _data_load
+    /* Load data section */
 	la a1, _data_run
 	la a2, _data_run_end
 	bgeu a1, a2, 2f
-1:
+    la a0, _data_load
-	lw t0, (a0)
+    la a1, _data_run
-	sw t0, (a1)
+    la a2, _data_run_end
-	addi a0, a0, 4
+    bgeu a1, a2, bl602_entry_load_data_section_end
 	addi a1, a1, 4
 	bltu a1, a2, 1b
-2:
+bl602_entry_load_data_section_loop:
-	/* Clear bss section */
+    lw t0, (a0)
    sw t0, (a1)
    addi a0, a0, 4
    addi a1, a1, 4
    bltu a1, a2, bl602_entry_load_data_section_loop
-	la a0, __bss_start
+bl602_entry_load_data_section_end:
 	la a1, __bss_end
 	bgeu a0, a1, 3f
-1:
+    /* Clear bss section */
 	sw zero, (a0)
 	addi a0, a0, 4
 	bltu a0, a1, 1b
-	/* Clear bss section */
+    la a0, __bss_start
    la a1, __bss_end
    bgeu a0, a1, bl602_entry_zero_bss_end
-	la a0, __wifi_bss_start
+bl602_entry_zero_bss_loop:
-	la a1, __wifi_bss_end
+    sw zero, (a0)
-	bgeu a0, a1, 3f
+    addi a0, a0, 4
    bltu a0, a1, bl602_entry_zero_bss_loop
 bl602_entry_zero_bss_end:
-1:
+    /* Clear bss section */
-	sw zero, (a0)
+
-	addi a0, a0, 4
+    la a0, __wifi_bss_start
-	bltu a0, a1, 1b
+    la a1, __wifi_bss_end
    bgeu a0, a1, bl602_entry_zero_wifi_bss_end
 bl602_entry_zero_wifi_bss_loop:
    sw zero, (a0)
    addi a0, a0, 4
    bltu a0, a1, bl602_entry_zero_wifi_bss_loop
 bl602_entry_zero_wifi_bss_end:
 3:
 #ifndef __riscv_float_abi_soft
 	/* Enable FPU */
 	li t0, MSTATUS_FS
 	csrs mstatus, t0
 	csrr t1, mstatus
 	and t1, t1, t0
 	beqz t1, 1f
 	fssr x0
-1:
+    /* Enable FPU */
    li t0, MSTATUS_FS
    csrs mstatus, t0
    csrr t1, mstatus
    and t1, t1, t0
    beqz t1, bl602_entry_enable_fpu_end
    fssr x0
 bl602_entry_enable_fpu_end:
 #endif
-	auipc ra, 0
+    auipc ra, 0
-	addi sp, sp, -16
+    addi sp, sp, -16
-	sw ra, 8(sp)
+    sw ra, 8(sp)
-	/* argc = argv = 0 */
+    /* argc = argv = 0 */
-	li a0, 0
+    li a0, 0
-	li a1, 0
+    li a1, 0
-	call bfl_main
+    call bfl_main
-1:
+bl602_entry_deadloop:
-	j 1b
+    j bl602_entry_deadloop
-	.cfi_endproc
+    .cfi_endproc
@@ -1,6 +1,9 @@
 /****************************************************************************
 * arch/risc-v/src/bl602/bl602_glb.c
 *
 * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved.
 * Author: Gregory Nutt <gnutt@nuttx.org>
 *
 * Licensed to the Apache Software Foundation (ASF) under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.  The
@@ -23,13 +26,14 @@
 ****************************************************************************/
 #include "hardware/bl602_glb.h"
 #include "riscv_arch.h"
 /****************************************************************************
 * Public Functions
 ****************************************************************************/
 /****************************************************************************
- * Name: glb_uart_fun_sel
+ * Name: bl602_glb_uart_fun_sel
 *
 * Description:
 *   Select UART signal function.
@@ -43,12 +47,13 @@
 *
 ****************************************************************************/
-void glb_uart_fun_sel(enum glb_uart_sig_e sig, enum glb_uart_sig_fun_e fun)
+void bl602_glb_uart_fun_sel(int sig, int fun)
 {
  uint32_t sig_pos = 0;
  uint32_t tmp_val = 0;
-  tmp_val = BL_RD_REG(GLB_BASE, GLB_UART_SIG_SEL_0);
+  tmp_val = getreg32(GLB_BASE + GLB_UART_SIG_SEL_0_OFFSET);
  sig_pos = (sig * 4);
  /* Clear original val */
@@ -58,11 +63,11 @@ void glb_uart_fun_sel(enum glb_uart_sig_e sig, enum glb_uart_sig_fun_e fun)
  /* Set new value */
  tmp_val = tmp_val | (fun << sig_pos);
-  BL_WR_REG(GLB_BASE, GLB_UART_SIG_SEL_0, tmp_val);
+  putreg32(tmp_val, GLB_BASE + GLB_UART_SIG_SEL_0_OFFSET);
 }
 /****************************************************************************
- * Name: glb_ahb_slave1_reset
+ * Name: bl602_glb_ahb_slave1_reset
 *
 * Description:
 *   Select UART signal function.
@@ -76,20 +81,31 @@ void glb_uart_fun_sel(enum glb_uart_sig_e sig, enum glb_uart_sig_fun_e fun)
 *
 ****************************************************************************/
-void glb_ahb_slave1_reset(enum bl_ahb_slave1_e slave1)
+void bl602_glb_ahb_slave1_reset(uint32_t slave1)
 {
  uint32_t tmp_val = 0;
-  tmp_val = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG1);
+  tmp_val = getreg32(GLB_BASE + GLB_SWRST_CFG1_OFFSET);
  tmp_val &= (~(1 << slave1));
-  BL_WR_REG(GLB_BASE, GLB_SWRST_CFG1, tmp_val);
+  putreg32(tmp_val, GLB_BASE + GLB_SWRST_CFG1_OFFSET);
  BL_DRV_DUMMY;
  tmp_val = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG1);
  tmp_val |= (1 << slave1);
  BL_WR_REG(GLB_BASE, GLB_SWRST_CFG1, tmp_val);
  BL_DRV_DUMMY;
  tmp_val = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG1);
  tmp_val &= (~(1 << slave1));
  BL_WR_REG(GLB_BASE, GLB_SWRST_CFG1, tmp_val);
 }
  /* It is to prevent glitch, which cannot be accessed via bus immediately
   * after certain register operations, so some nop is added
   */
  BL_DRV_DUMMY();
  tmp_val = getreg32(GLB_BASE + GLB_SWRST_CFG1_OFFSET);
  tmp_val |= (1 << slave1);
  putreg32(tmp_val, GLB_BASE + GLB_SWRST_CFG1_OFFSET);
  /* It is to prevent glitch, which cannot be accessed via bus immediately
   * after certain register operations, so some nop is added
   */
  BL_DRV_DUMMY();
  tmp_val = getreg32(GLB_BASE + GLB_SWRST_CFG1_OFFSET);
  tmp_val &= (~(1 << slave1));
  putreg32(tmp_val, GLB_BASE + GLB_SWRST_CFG1_OFFSET);
 }
@@ -1,6 +1,9 @@
 /****************************************************************************
 * arch/risc-v/src/bl602/bl602_gpio.c
 *
 * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved.
 * Author: Gregory Nutt <gnutt@nuttx.org>
 *
 * Licensed to the Apache Software Foundation (ASF) under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.  The
@@ -25,13 +28,14 @@
 #include <stdint.h>
 #include "hardware/bl602_gpio.h"
 #include "hardware/bl602_glb.h"
 #include "riscv_arch.h"
 /****************************************************************************
 * Public Functions
 ****************************************************************************/
 /****************************************************************************
- * Name: gpio_init
+ * Name: bl602_gpio_init
 *
 * Description:
 *   Init a gpio pin.
@@ -48,7 +52,7 @@
 *
 ****************************************************************************/
-void gpio_init(struct gpio_cfg_s *cfg)
+void bl602_gpio_init(struct gpio_cfg_s *cfg)
 {
  uint8_t   gpio_pin = cfg->gpio_pin;
  uint32_t *p_out;
@@ -66,7 +70,7 @@ void gpio_init(struct gpio_cfg_s *cfg)
  tmp_out &= (~(1 << pos));
  *p_out = tmp_out;
-  tmp_val = BL_RD_WORD(GLB_BASE + GLB_GPIO_OFFSET + gpio_pin / 2 * 4);
+  tmp_val = getreg32(GLB_BASE + GLB_GPIO_OFFSET + gpio_pin / 2 * 4);
  if (gpio_pin % 2 == 0)
    {
@@ -74,32 +78,33 @@ void gpio_init(struct gpio_cfg_s *cfg)
      if (cfg->gpio_mode == GPIO_MODE_OUTPUT)
        {
-          tmp_val = BL_CLR_REG_BIT(tmp_val, GLB_REG_GPIO_0_IE);
+          tmp_val = tmp_val & GLB_REG_GPIO_0_IE_UMSK;
          tmp_out |= (1 << pos);
        }
      else
        {
-          tmp_val = BL_SET_REG_BIT(tmp_val, GLB_REG_GPIO_0_IE);
+          tmp_val = tmp_val | (1 << GLB_REG_GPIO_0_IE_POS);
        }
      /* Set pull up or down */
-      tmp_val = BL_CLR_REG_BIT(tmp_val, GLB_REG_GPIO_0_PU);
+      tmp_val &= GLB_REG_GPIO_0_PU_UMSK;
-      tmp_val = BL_CLR_REG_BIT(tmp_val, GLB_REG_GPIO_0_PD);
+      tmp_val &= GLB_REG_GPIO_0_PD_UMSK;
      if (cfg->pull_type == GPIO_PULL_UP)
        {
-          tmp_val = BL_SET_REG_BIT(tmp_val, GLB_REG_GPIO_0_PU);
+          tmp_val = tmp_val | (1 << GLB_REG_GPIO_0_PU_POS);
        }
      else if (cfg->pull_type == GPIO_PULL_DOWN)
        {
-          tmp_val = BL_SET_REG_BIT(tmp_val, GLB_REG_GPIO_0_PD);
+          tmp_val = tmp_val | (1 << GLB_REG_GPIO_0_PD_POS);
        }
-      tmp_val = BL_SET_REG_BITS_VAL(tmp_val, GLB_REG_GPIO_0_DRV, cfg->drive);
+      tmp_val = (tmp_val & GLB_REG_GPIO_0_DRV_UMSK) |
-      tmp_val =
+                (cfg->drive << GLB_REG_GPIO_0_DRV_POS);
-        BL_SET_REG_BITS_VAL(tmp_val, GLB_REG_GPIO_0_SMT, cfg->smt_ctrl);
+      tmp_val = (tmp_val & GLB_REG_GPIO_0_SMT_UMSK) |
-      tmp_val =
+                (cfg->smt_ctrl << GLB_REG_GPIO_0_SMT_POS);
-        BL_SET_REG_BITS_VAL(tmp_val, GLB_REG_GPIO_0_FUNC_SEL, cfg->gpio_fun);
+      tmp_val = (tmp_val & GLB_REG_GPIO_0_FUNC_SEL_UMSK) |
                (cfg->gpio_fun << GLB_REG_GPIO_0_FUNC_SEL_POS);
    }
  else
    {
@@ -107,36 +112,36 @@ void gpio_init(struct gpio_cfg_s *cfg)
      if (cfg->gpio_mode == GPIO_MODE_OUTPUT)
        {
-          tmp_val = BL_CLR_REG_BIT(tmp_val, GLB_REG_GPIO_1_IE);
+          tmp_val &= GLB_REG_GPIO_1_IE_UMSK;
          tmp_out |= (1 << pos);
        }
      else
        {
-          tmp_val = BL_SET_REG_BIT(tmp_val, GLB_REG_GPIO_1_IE);
+          tmp_val = tmp_val | (1 << GLB_REG_GPIO_1_IE_POS);
        }
      /* Set pull up or down */
-      tmp_val = BL_CLR_REG_BIT(tmp_val, GLB_REG_GPIO_1_PU);
+      tmp_val &= GLB_REG_GPIO_1_PU_UMSK;
-      tmp_val = BL_CLR_REG_BIT(tmp_val, GLB_REG_GPIO_1_PD);
+      tmp_val &= GLB_REG_GPIO_1_PD_UMSK;
      if (cfg->pull_type == GPIO_PULL_UP)
        {
-          tmp_val = BL_SET_REG_BIT(tmp_val, GLB_REG_GPIO_1_PU);
+          tmp_val = tmp_val | (1 << GLB_REG_GPIO_1_PU_POS);
        }
      else if (cfg->pull_type == GPIO_PULL_DOWN)
        {
-          tmp_val = BL_SET_REG_BIT(tmp_val, GLB_REG_GPIO_1_PD);
+          tmp_val = tmp_val | (1 << GLB_REG_GPIO_1_PD_POS);
        }
-      tmp_val = BL_SET_REG_BITS_VAL(tmp_val, GLB_REG_GPIO_1_DRV, cfg->drive);
+      tmp_val = (tmp_val & GLB_REG_GPIO_1_DRV_UMSK) |
-      tmp_val =
+                (cfg->drive << GLB_REG_GPIO_1_DRV_POS);
-        BL_SET_REG_BITS_VAL(tmp_val, GLB_REG_GPIO_1_SMT, cfg->smt_ctrl);
+      tmp_val = (tmp_val & GLB_REG_GPIO_1_SMT_UMSK) |
-      tmp_val =
+                (cfg->smt_ctrl << GLB_REG_GPIO_1_SMT_POS);
-        BL_SET_REG_BITS_VAL(tmp_val, GLB_REG_GPIO_1_FUNC_SEL, cfg->gpio_fun);
+      tmp_val = (tmp_val & GLB_REG_GPIO_1_FUNC_SEL_UMSK) |
                (cfg->gpio_fun << GLB_REG_GPIO_1_FUNC_SEL_POS);
    }
-  BL_WR_WORD(GLB_BASE + GLB_GPIO_OFFSET + gpio_pin / 2 * 4, tmp_val);
+  putreg32(tmp_val, GLB_BASE + GLB_GPIO_OFFSET + gpio_pin / 2 * 4);
  *p_out = tmp_out;
 }
@@ -1,6 +1,8 @@
 /****************************************************************************
- * <Relative path to the file>
+ * arch/risc-v/src/bl602/bl602_hbn.c
- * <Optional one line file description>
+ *
 * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved.
 * Author: Gregory Nutt <gnutt@nuttx.org>
 *
 * Licensed to the Apache Software Foundation (ASF) under one or more
 * contributor license agreements.  See the NOTICE file distributed with
@@ -24,13 +26,14 @@
 ****************************************************************************/
 #include "hardware/bl602_hbn.h"
 #include "riscv_arch.h"
 /****************************************************************************
 * Public Functions
 ****************************************************************************/
 /****************************************************************************
- * Name: hbn_set_uart_clk_sel
+ * Name: bl602_hbn_set_uart_clk_sel
 *
 * Description:
 *   Select uart clock source.
@@ -47,12 +50,12 @@
 *
 ****************************************************************************/
-void hbn_set_uart_clk_sel(enum hbn_uart_clk_type_e clk_sel)
+void bl602_hbn_set_uart_clk_sel(int clk_sel)
 {
  uint32_t tmp_val;
-  tmp_val = BL_RD_REG(HBN_BASE, HBN_GLB);
+  tmp_val = getreg32(HBN_BASE + HBN_GLB_OFFSET);
-  tmp_val = BL_SET_REG_BITS_VAL(tmp_val, HBN_UART_CLK_SEL, clk_sel);
+  tmp_val &= ~(1 << 2);
-  BL_WR_REG(HBN_BASE, HBN_GLB, tmp_val);
+  tmp_val |= (clk_sel << 2);
  putreg32(tmp_val, HBN_BASE + HBN_GLB_OFFSET);
 }
@@ -1,6 +1,9 @@
 /****************************************************************************
 * arch/risc-v/src/bl602/bl602_head.S
 *
 * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved.
 * Author: Gregory Nutt <gnutt@nuttx.org>
 *
 * Licensed to the Apache Software Foundation (ASF) under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.  The
@@ -34,6 +37,7 @@
 /****************************************************************************
 * Name: exception_common
 ****************************************************************************/
 .align 8
 exception_common:
@@ -1,6 +1,9 @@
 /****************************************************************************
 * arch/risc-v/src/bl602/bl602_idle.c
 *
 * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved.
 * Author: Gregory Nutt <gnutt@nuttx.org>
 *
 * Licensed to the Apache Software Foundation (ASF) under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.  The
@@ -65,4 +68,3 @@ void up_idle(void)
 #endif
 }
@@ -1,6 +1,9 @@
 /****************************************************************************
 * arch/risc-v/src/bl602/bl602_irq.c
 *
 * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved.
 * Author: Gregory Nutt <gnutt@nuttx.org>
 *
 * Licensed to the Apache Software Foundation (ASF) under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.  The
@@ -46,22 +49,22 @@
 static inline void bl_irq_enable(unsigned int source)
 {
-  *(volatile uint8_t *)(CLIC_HART0_ADDR + CLIC_INTIE + source) = 1;
+  putreg8(1, CLIC_HART0_ADDR + CLIC_INTIE + source);
 }
 static inline void bl_irq_disable(unsigned int source)
 {
-  *(volatile uint8_t *)(CLIC_HART0_ADDR + CLIC_INTIE + source) = 0;
+  putreg8(0, CLIC_HART0_ADDR + CLIC_INTIE + source);
 }
 static inline void bl_irq_pending_set(unsigned int source)
 {
-  *(volatile uint8_t *)(CLIC_HART0_ADDR + CLIC_INTIP + source) = 1;
+  putreg8(1, CLIC_HART0_ADDR + CLIC_INTIP + source);
 }
 static inline void bl_irq_pending_clear(unsigned int source)
 {
-  *(volatile uint8_t *)(CLIC_HART0_ADDR + CLIC_INTIP + source) = 0;
+  putreg8(0, CLIC_HART0_ADDR + CLIC_INTIP + source);
 }
 /****************************************************************************
@@ -122,7 +125,7 @@ void up_disable_irq(int irq)
    }
  else if (irq == BL602_IRQ_MTIMER)
    {
-      *(volatile uint8_t *)CLIC_TIMER_ENABLE_ADDRESS = 0;
+      putreg8(0, CLIC_TIMER_ENABLE_ADDRESS);
      /* Read mstatus & clear machine timer interrupt enable in mie */
@@ -155,7 +158,7 @@ void up_enable_irq(int irq)
    }
  else if (irq == BL602_IRQ_MTIMER)
    {
-      *(volatile uint8_t *)CLIC_TIMER_ENABLE_ADDRESS = 1;
+      putreg8(1, CLIC_TIMER_ENABLE_ADDRESS);
      /* Read mstatus & set machine timer interrupt enable in mie */
@@ -255,4 +258,3 @@ irqstate_t up_irq_enable(void)
  asm volatile("csrrs %0, mstatus, %1" : "=r"(oldstat) : "r"(MSTATUS_MIE));
  return oldstat;
 }
@@ -1,6 +1,9 @@
 /****************************************************************************
 * arch/risc-v/src/bl602/bl602_irq_dispatch.c
 *
 * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved.
 * Author: Gregory Nutt <gnutt@nuttx.org>
 *
 * Licensed to the Apache Software Foundation (ASF) under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.  The
@@ -103,4 +106,3 @@ void *bl602_dispatch_irq(uint32_t vector, uint32_t *regs)
  return regs;
 }
@@ -1,6 +1,9 @@
 /****************************************************************************
 * boards/risc-v/bl602/evb/src/bl602_lowputc.c
 *
 * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved.
 * Author: Gregory Nutt <gnutt@nuttx.org>
 *
 * Licensed to the Apache Software Foundation (ASF) under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.  The
@@ -54,6 +57,7 @@
 ****************************************************************************/
 /* Select UART parameters for the selected console */
 #ifdef HAVE_SERIAL_CONSOLE
 #if defined(CONFIG_UART0_SERIAL_CONSOLE)
 #define BL602_CONSOLE_IDX    0
@@ -144,9 +148,9 @@ static void uart_gpio_init(uint8_t id,
                           uint8_t cts_pin,
                           uint8_t rts_pin)
 {
-  struct gpio_cfg_s       cfg;
+  struct gpio_cfg_s cfg;
-  enum glb_uart_sig_fun_e tx_sigfun;
+  int               tx_sigfun;
-  enum glb_uart_sig_fun_e rx_sigfun;
+  int               rx_sigfun;
  cfg.drive    = 1;
  cfg.smt_ctrl = 1;
@@ -155,12 +159,12 @@ static void uart_gpio_init(uint8_t id,
  cfg.gpio_pin  = rx_pin;
  cfg.gpio_mode = GPIO_MODE_AF;
  cfg.pull_type = GPIO_PULL_UP;
-  gpio_init(&cfg);
+  bl602_gpio_init(&cfg);
  cfg.gpio_pin  = tx_pin;
  cfg.gpio_mode = GPIO_MODE_AF;
  cfg.pull_type = GPIO_PULL_UP;
-  gpio_init(&cfg);
+  bl602_gpio_init(&cfg);
  /* select uart gpio function */
@@ -175,61 +179,86 @@ static void uart_gpio_init(uint8_t id,
      rx_sigfun = GLB_UART_SIG_FUN_UART1_RXD;
    }
-  glb_uart_fun_sel(tx_pin % 8, tx_sigfun);
+  bl602_glb_uart_fun_sel(tx_pin % 8, tx_sigfun);
-  glb_uart_fun_sel(rx_pin % 8, rx_sigfun);
+  bl602_glb_uart_fun_sel(rx_pin % 8, rx_sigfun);
 }
-static void bl602_enable_uart_clk(uint8_t                  enable,
+static void bl602_enable_uart_clk(uint8_t enable, int clk_sel, uint8_t div)
                                  enum hbn_uart_clk_type_e clk_sel,
                                  uint8_t                  div)
 {
  uint32_t tmp_val;
  /* disable UART clock first */
-  tmp_val = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2);
+  bl602_up_serialmodify(GLB_BASE, GLB_CLK_CFG2_OFFSET, (1 << 4), 0);
  tmp_val = BL_CLR_REG_BIT(tmp_val, GLB_UART_CLK_EN);
  BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmp_val);
  /* Set div */
-  tmp_val = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2);
+  bl602_up_serialmodify(GLB_BASE, GLB_CLK_CFG2_OFFSET, 0x7, div);
  tmp_val = BL_SET_REG_BITS_VAL(tmp_val, GLB_UART_CLK_DIV, div);
  BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmp_val);
  /* Select clock source for uart */
-  hbn_set_uart_clk_sel(clk_sel);
+  bl602_hbn_set_uart_clk_sel(clk_sel);
  /* Set enable or disable */
-  tmp_val = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2);
+  tmp_val = bl602_up_serialin(GLB_BASE, GLB_CLK_CFG2_OFFSET);
  if (enable)
    {
-      tmp_val = BL_SET_REG_BIT(tmp_val, GLB_UART_CLK_EN);
+      tmp_val |= (1 << 4);
    }
  else
    {
-      tmp_val = BL_CLR_REG_BIT(tmp_val, GLB_UART_CLK_EN);
+      tmp_val &= ~(1 << 4);
    }
-  BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmp_val);
+  bl602_up_serialout(GLB_BASE, GLB_CLK_CFG2_OFFSET, tmp_val);
 }
 /****************************************************************************
 * Public Functions
 ****************************************************************************/
 uint32_t bl602_up_serialin(uint32_t reg_base, int offset)
 {
  return getreg32(reg_base + offset);
 }
 void bl602_up_serialout(uint32_t reg_base, int offset, uint32_t value)
 {
  putreg32(value, reg_base + offset);
 }
 void bl602_up_serialmodify(uint32_t reg_base,
                           int      offset,
                           uint32_t clearbits,
                           uint32_t setbits)
 {
  modifyreg32(reg_base + offset, clearbits, setbits);
 }
 /****************************************************************************
 * Name: bl602_data_setbits
 ****************************************************************************/
 static uint32_t bl602_data_setbits(uint32_t data,
                                   uint32_t start,
                                   uint32_t len,
                                   uint32_t value)
 {
  return (((data) & ~((~((~0) << (len))) << (start))) |
          (((value) & ((~((~0) << (len))))) << (start)));
 }
 void bl602_uart_configure(uint32_t                    uartbase,
                          const struct uart_config_s *config)
 {
-  uint32_t             tmp_val;
+  uint32_t tmp_val;
-  uint32_t             div        = 0;
+  uint32_t div        = 0;
-  uint32_t             fraction   = 0;
+  uint32_t fraction   = 0;
-  uint32_t             tmp_tx_cfg = 0;
+  uint32_t tmp_tx_cfg = 0;
-  uint32_t             tmp_rx_cfg = 0;
+  uint32_t tmp_rx_cfg = 0;
-  enum uart_databits_e data_bits;
+  int      data_bits;
-  enum uart_stopbits_e stop_bits;
+  int      stop_bits;
  bl602_enable_uart_clk(1, HBN_UART_CLK_160M, 3);
@@ -241,18 +270,12 @@ void bl602_uart_configure(uint32_t                    uartbase,
  /* Disable all interrupt */
-  tmp_val = BL_RD_REG(uartbase, UART_INT_MASK);
+  bl602_up_serialmodify(uartbase, UART_INT_MASK_OFFSET, 0, 0xff);
  tmp_val |= 0xff;
  BL_WR_REG(uartbase, UART_INT_MASK, tmp_val);
  /* Disable uart before config */
-  tmp_val = BL_RD_REG(uartbase, UART_UTX_CONFIG);
+  bl602_up_serialmodify(uartbase, UART_UTX_CONFIG_OFFSET, 1, 0);
-  BL_WR_REG(
+  bl602_up_serialmodify(uartbase, UART_URX_CONFIG_OFFSET, 1, 0);
    uartbase, UART_UTX_CONFIG, BL_CLR_REG_BIT(tmp_val, UART_CR_UTX_EN));
  tmp_val = BL_RD_REG(uartbase, UART_URX_CONFIG);
  BL_WR_REG(
    uartbase, UART_URX_CONFIG, BL_CLR_REG_BIT(tmp_val, UART_CR_URX_EN));
  /* cal the baud rate divisor */
@@ -265,31 +288,32 @@ void bl602_uart_configure(uint32_t                    uartbase,
  /* set the baud rate register value */
-  BL_WR_REG(
+  bl602_up_serialout(uartbase,
-    uartbase, UART_BIT_PRD, ((div - 1) << 0x10) | ((div - 1) & 0xffff));
+                     UART_BIT_PRD_OFFSET,
                     ((div - 1) << 0x10) | ((div - 1) & 0xffff));
  /* configure parity type */
-  tmp_tx_cfg = BL_RD_REG(uartbase, UART_UTX_CONFIG);
+  tmp_tx_cfg = bl602_up_serialin(uartbase, UART_UTX_CONFIG_OFFSET);
-  tmp_rx_cfg = BL_RD_REG(uartbase, UART_URX_CONFIG);
+  tmp_rx_cfg = bl602_up_serialin(uartbase, UART_URX_CONFIG_OFFSET);
  switch (config->parity)
    {
    case UART_PARITY_NONE:
-      tmp_tx_cfg = BL_CLR_REG_BIT(tmp_tx_cfg, UART_CR_UTX_PRT_EN);
+      tmp_tx_cfg &= ~(1 << 4);
-      tmp_rx_cfg = BL_CLR_REG_BIT(tmp_rx_cfg, UART_CR_URX_PRT_EN);
+      tmp_rx_cfg &= ~(1 << 4);
      break;
    case UART_PARITY_ODD:
-      tmp_tx_cfg = BL_SET_REG_BIT(tmp_tx_cfg, UART_CR_UTX_PRT_EN);
+      tmp_tx_cfg |= 1 << 4;
-      tmp_tx_cfg = BL_SET_REG_BIT(tmp_tx_cfg, UART_CR_UTX_PRT_SEL);
+      tmp_tx_cfg |= 1 << 5;
-      tmp_rx_cfg = BL_SET_REG_BIT(tmp_rx_cfg, UART_CR_URX_PRT_EN);
+      tmp_rx_cfg |= 1 << 4;
-      tmp_rx_cfg = BL_SET_REG_BIT(tmp_rx_cfg, UART_CR_URX_PRT_SEL);
+      tmp_rx_cfg |= 1 << 5;
      break;
    case UART_PARITY_EVEN:
-      tmp_tx_cfg = BL_SET_REG_BIT(tmp_tx_cfg, UART_CR_UTX_PRT_EN);
+      tmp_tx_cfg |= 1 << 4;
-      tmp_tx_cfg = BL_CLR_REG_BIT(tmp_tx_cfg, UART_CR_UTX_PRT_SEL);
+      tmp_tx_cfg &= ~(1 << 5);
-      tmp_rx_cfg = BL_SET_REG_BIT(tmp_rx_cfg, UART_CR_URX_PRT_EN);
+      tmp_rx_cfg |= 1 << 4;
-      tmp_rx_cfg = BL_CLR_REG_BIT(tmp_rx_cfg, UART_CR_URX_PRT_SEL);
+      tmp_rx_cfg &= ~(1 << 5);
      break;
    default:
      break;
@@ -323,78 +347,61 @@ void bl602_uart_configure(uint32_t                    uartbase,
  /* Configure data bits */
-  tmp_tx_cfg =
+  tmp_tx_cfg = bl602_data_setbits(tmp_tx_cfg, 8, 3, (data_bits + 4));
-    BL_SET_REG_BITS_VAL(tmp_tx_cfg, UART_CR_UTX_BIT_CNT_D, (data_bits + 4));
+  tmp_rx_cfg = bl602_data_setbits(tmp_tx_cfg, 8, 3, (data_bits + 4));
  tmp_rx_cfg =
    BL_SET_REG_BITS_VAL(tmp_rx_cfg, UART_CR_URX_BIT_CNT_D, (data_bits + 4));
  /* Configure tx stop bits */
-  tmp_tx_cfg =
+  tmp_tx_cfg = bl602_data_setbits(tmp_tx_cfg, 12, 2, (stop_bits + 1));
    BL_SET_REG_BITS_VAL(tmp_tx_cfg, UART_CR_UTX_BIT_CNT_P, (stop_bits + 1));
  /* Configure tx cts flow control function */
  if (config->oflow_ctl)
    {
-      tmp_tx_cfg = BL_SET_REG_BIT(tmp_tx_cfg, UART_CR_UTX_CTS_EN);
+      tmp_tx_cfg |= 1 << 1;
    }
  else
    {
-      tmp_tx_cfg = BL_CLR_REG_BIT(tmp_tx_cfg, UART_CR_UTX_CTS_EN);
+      tmp_tx_cfg &= ~(1 << 1);
    }
  /* Disable rx input de-glitch function */
-  tmp_rx_cfg = BL_CLR_REG_BIT(tmp_rx_cfg, UART_CR_URX_DEG_EN);
+  tmp_rx_cfg &= ~(1 << 11);
  if (config->iflow_ctl)
    {
-      tmp_tx_cfg = BL_SET_REG_BIT(tmp_tx_cfg, UART_CR_URX_RTS_SW_MODE);
+      tmp_rx_cfg |= 1 << 1;
    }
  else
    {
-      tmp_rx_cfg = BL_CLR_REG_BIT(tmp_rx_cfg, UART_CR_URX_RTS_SW_MODE);
+      tmp_rx_cfg &= ~(1 << 1);
    }
  /* Write back */
-  BL_WR_REG(uartbase, UART_UTX_CONFIG, tmp_tx_cfg);
+  bl602_up_serialout(uartbase, UART_UTX_CONFIG_OFFSET, tmp_tx_cfg);
-  BL_WR_REG(uartbase, UART_URX_CONFIG, tmp_rx_cfg);
+  bl602_up_serialout(uartbase, UART_URX_CONFIG_OFFSET, tmp_rx_cfg);
  /* Configure LSB-first */
-  tmp_tx_cfg = BL_RD_REG(uartbase, UART_DATA_CONFIG);
+  bl602_up_serialmodify(uartbase, UART_DATA_CONFIG_OFFSET, 1, 0);
  tmp_tx_cfg = BL_CLR_REG_BIT(tmp_tx_cfg, UART_CR_UART_BIT_INV);
  BL_WR_REG(uartbase, UART_DATA_CONFIG, tmp_tx_cfg);
  /* Enable tx free run mode */
-  tmp_val = BL_RD_REG(uartbase, UART_UTX_CONFIG);
+  bl602_up_serialmodify(uartbase, UART_UTX_CONFIG_OFFSET, 0, 1 << 2);
  BL_WR_REG(
    uartbase, UART_UTX_CONFIG, BL_SET_REG_BIT(tmp_val, UART_CR_UTX_FRM_EN));
  /* Deal with uart fifo configure register */
-  tmp_val = BL_RD_REG(uartbase, UART_FIFO_CONFIG_1);
+  tmp_val = bl602_up_serialin(uartbase, UART_FIFO_CONFIG_1_OFFSET);
-
+  tmp_val = bl602_data_setbits(tmp_val, UART_TX_FIFO_TH_POS, 5, 0x10 - 1);
-  /* Configure dma tx fifo threshold */
+  tmp_val = bl602_data_setbits(tmp_val, UART_RX_FIFO_TH_POS, 5, 0x10 - 1);
-
+  bl602_up_serialout(uartbase, UART_FIFO_CONFIG_1_OFFSET, tmp_val);
  tmp_val = BL_SET_REG_BITS_VAL(tmp_val, UART_TX_FIFO_TH, 0x10 - 1);
  /* Configure dma rx fifo threshold */
  tmp_val = BL_SET_REG_BITS_VAL(tmp_val, UART_RX_FIFO_TH, 0x10 - 1);
  BL_WR_REG(uartbase, UART_FIFO_CONFIG_1, tmp_val);
  /* Enable UART tx rx unit */
-  tmp_val = BL_RD_REG(uartbase, UART_UTX_CONFIG);
+  bl602_up_serialmodify(uartbase, UART_UTX_CONFIG_OFFSET, 0, 1);
-  BL_WR_REG(
+  bl602_up_serialmodify(uartbase, UART_URX_CONFIG_OFFSET, 0, 1);
    uartbase, UART_UTX_CONFIG, BL_SET_REG_BIT(tmp_val, UART_CR_UTX_EN));
  tmp_val = BL_RD_REG(uartbase, UART_URX_CONFIG);
  BL_WR_REG(
    uartbase, UART_URX_CONFIG, BL_SET_REG_BIT(tmp_val, UART_CR_URX_EN));
 }
 /****************************************************************************
@@ -411,11 +418,12 @@ void up_lowputc(char ch)
  /* Wait for FIFO */
  while (
-    BL_GET_REG_BITS_VAL(BL_RD_REG(BL602_CONSOLE_BASE, UART_FIFO_CONFIG_1),
+    ((bl602_up_serialin(BL602_CONSOLE_BASE, UART_FIFO_CONFIG_1_OFFSET)) >>
-                        UART_TX_FIFO_CNT) == 0)
+     (UART_TX_FIFO_CNT_POS)) &
    (~((~0) << (6))))
    ;
-  BL_WR_BYTE(BL602_CONSOLE_BASE + UART_FIFO_WDATA_OFFSET, ch);
+  bl602_up_serialout(BL602_CONSOLE_BASE, UART_FIFO_WDATA_OFFSET, ch);
 #endif /* HAVE_CONSOLE */
 }
@@ -428,4 +436,3 @@ void bl602_lowsetup(void)
 #endif /* HAVE_SERIAL_CONSOLE */
 }
@@ -1,6 +1,9 @@
 /**
 * incubator-nuttx/arch/risc-v/src/bl602/bl602_lowputc.h
 *
 * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved.
 * Author: Gregory Nutt <gnutt@nuttx.org>
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
@@ -31,15 +34,6 @@
 #ifndef __ASSEMBLY__
 #undef EXTERN
 #if defined(__cplusplus)
 #define EXTERN extern "C"
 extern "C"
 {
 #else
 #define EXTERN extern
 #endif
 struct uart_config_s
 {
  uint8_t  idx;       /* Uart idx */
@@ -55,13 +49,28 @@ struct uart_config_s
  uint8_t  rts_pin;   /* RTS pin */
 };
-/****************************************************************************
+#undef EXTERN
- * Name: bl602_lowsetup
+#if defined(__cplusplus)
- ****************************************************************************/
+#define EXTERN extern "C"
 extern "C"
 {
 #else
 #define EXTERN extern
 #endif
 EXTERN uint32_t bl602_up_serialin(uint32_t reg_base, int offset);
 EXTERN void bl602_up_serialout(uint32_t reg_base, int offset,
                                  uint32_t value);
 EXTERN void bl602_up_serialmodify(uint32_t reg_base,
                                  int offset,
                                  uint32_t clearbits,
                                  uint32_t setbits);
 EXTERN void bl602_lowsetup(void);
-EXTERN void bl602_uart_configure(uint32_t                    base_addr,
+EXTERN void bl602_uart_configure(uint32_t base_addr,
                                 const struct uart_config_s *config);
 #undef EXTERN
@@ -1,8 +1,8 @@
 /****************************************************************************
- *  arch/arm/src/bl602/bl602_oneshot_lowerhalf.c
+ * arch/arm/src/bl602/bl602_oneshot_lowerhalf.c
 *
- *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2016 Gregory Nutt. All rights reserved.
- *   Authors: Gregory Nutt <gnutt@nuttx.org>
+ * Authors: Gregory Nutt <gnutt@nuttx.org>
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
@@ -48,9 +48,17 @@
 #include <nuttx/kmalloc.h>
 #include <nuttx/timers/oneshot.h>
 #include "riscv_arch.h"
 #include "riscv_internal.h"
 #include <hardware/bl602_timer.h>
 #include "bl602_oneshot_lowerhalf.h"
 /****************************************************************************
 * Pre-processor Definitions
 ****************************************************************************/
 /* Private definetions */
 #define TIMER_MAX_VALUE (0xFFFFFFFF)
 #define TIMER_CLK_DIV   (160)
 #define TIMER_CLK_FREQ  (160000000UL / (TIMER_CLK_DIV))
@@ -142,15 +150,15 @@ static int bl602_oneshot_handler(int irq, FAR void *context, FAR void *arg)
  uint32_t tmp_val;
  uint32_t tmp_addr;
-  int_id   = BL_RD_WORD(TIMER_BASE + TIMER_TMSR2_OFFSET + 4 * priv->tim);
+  int_id   = getreg32(TIMER_BASE + TIMER_TMSR2_OFFSET + 4 * priv->tim);
  tmp_addr = TIMER_BASE + TIMER_TICR2_OFFSET + 4 * priv->tim;
-  tmp_val  = BL_RD_WORD(tmp_addr);
+  tmp_val  = getreg32(tmp_addr);
  /* Comparator 0 match interrupt */
-  if (BL_IS_REG_BIT_SET(int_id, TIMER_TMSR_0))
+  if (((int_id) & (1 << (TIMER_TMSR_0_POS))) != 0)
    {
-      BL_WR_WORD(tmp_addr, BL_SET_REG_BIT(tmp_val, TIMER_TCLR_0));
+      putreg32(tmp_val | (1 << TIMER_TCLR_0_POS), tmp_addr);
      callback = priv->callback;
      cbarg    = priv->arg;
@@ -162,16 +170,16 @@ static int bl602_oneshot_handler(int irq, FAR void *context, FAR void *arg)
  /* Comparator 1 match interrupt */
-  if (BL_IS_REG_BIT_SET(int_id, TIMER_TMSR_1))
+  if (((int_id) & (1 << (TIMER_TMSR_1_POS))) != 0)
    {
-      BL_WR_WORD(tmp_addr, BL_SET_REG_BIT(tmp_val, TIMER_TCLR_1));
+      putreg32(tmp_val | (1 << TIMER_TCLR_1_POS), tmp_addr);
    }
  /* Comparator 2 match interrupt */
-  if (BL_IS_REG_BIT_SET(int_id, TIMER_TMSR_2))
+  if (((int_id) & (1 << (TIMER_TMSR_2_POS))) != 0)
    {
-      BL_WR_WORD(tmp_addr, BL_SET_REG_BIT(tmp_val, TIMER_TCLR_2));
+      putreg32(tmp_val | (1 << TIMER_TCLR_2_POS), tmp_addr);
    }
  return 0;
@@ -265,14 +273,14 @@ static int bl602_start(FAR struct oneshot_lowerhalf_s *lower,
  usec = (uint64_t)ts->tv_sec * USEC_PER_SEC +
         (uint64_t)(ts->tv_nsec / NSEC_PER_USEC);
-  timer_setcompvalue(
+  bl602_timer_setcompvalue(
    priv->tim, TIMER_COMP_ID_0, usec / (TIMER_CLK_FREQ / priv->freq));
-  timer_setpreloadvalue(priv->tim, 0);
+  bl602_timer_setpreloadvalue(priv->tim, 0);
  irq_attach(priv->irq, bl602_oneshot_handler, (void *)priv);
  up_enable_irq(priv->irq);
-  timer_intmask(priv->tim, TIMER_INT_COMP_0, 0);
+  bl602_timer_intmask(priv->tim, TIMER_INT_COMP_0, 0);
-  timer_enable(priv->tim);
+  bl602_timer_enable(priv->tim);
  priv->started = true;
  leave_critical_section(flags);
@@ -319,10 +327,10 @@ static int bl602_cancel(FAR struct oneshot_lowerhalf_s *lower,
    {
      flags = enter_critical_section();
-      timer_disable(priv->tim);
+      bl602_timer_disable(priv->tim);
      priv->started = false;
      up_disable_irq(priv->irq);
-      timer_intmask(priv->tim, TIMER_INT_COMP_0, 1);
+      bl602_timer_intmask(priv->tim, TIMER_INT_COMP_0, 1);
      priv->callback = NULL;
      priv->arg      = NULL;
@@ -399,22 +407,21 @@ FAR struct oneshot_lowerhalf_s *oneshot_initialize(int      chan,
  timstr.count_mode = TIMER_COUNT_PRELOAD; /* Timer count mode */
  timstr.clock_division =
-    (TIMER_CLK_DIV * resolution) - 1;  /* Timer clock divison value */
+    (TIMER_CLK_DIV * resolution) - 1; /* Timer clock divison value */
-  timstr.match_val0  = TIMER_MAX_VALUE; /* Timer match 0 value 0 */
+  timstr.match_val0 = TIMER_MAX_VALUE; /* Timer match 0 value 0 */
-  timstr.match_val1  = TIMER_MAX_VALUE; /* Timer match 1 value 0 */
+  timstr.match_val1 = TIMER_MAX_VALUE; /* Timer match 1 value 0 */
-  timstr.match_val2  = TIMER_MAX_VALUE; /* Timer match 2 value 0 */
+  timstr.match_val2 = TIMER_MAX_VALUE; /* Timer match 2 value 0 */
  timstr.pre_load_val = TIMER_MAX_VALUE; /* Timer preload value */
-  timer_intmask(chan, TIMER_INT_ALL, 1);
+  bl602_timer_intmask(chan, TIMER_INT_ALL, 1);
  /* timer disable */
-  timer_disable(chan);
+  bl602_timer_disable(chan);
-  timer_init(&timstr);
+  bl602_timer_init(&timstr);
  return &priv->lh;
 }
@@ -1,8 +1,8 @@
 /****************************************************************************
 * arch/risc-v/src/bl602/bl602_oneshot.h
 *
- *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2016 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
+ * Author: Gregory Nutt <gnutt@nuttx.org>
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
@@ -71,6 +71,7 @@
 * Public Types
 ****************************************************************************/
 #ifndef __ASSEMBLY__
 /* This describes the callback function that will be invoked when the oneshot
 * timer expires.  The oneshot fires, the client will receive:
 *
@@ -208,5 +209,6 @@ int bl602_oneshot_cancel(struct bl602_oneshot_s *oneshot,
 }
 #endif
 #endif /* __ASSEMBLY__ */
 #endif /* CONFIG_BL602_ONESHOT */
 #endif /* __ARCH_ARM_SRC_BL602_ONESHOT_H */
@@ -1,6 +1,9 @@
 /****************************************************************************
 * arch/risc-v/src/bl602/bl602_serial.c
 *
 * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved.
 * Author: Gregory Nutt <gnutt@nuttx.org>
 *
 * Licensed to the Apache Software Foundation (ASF) under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.  The
@@ -312,15 +315,15 @@ static int __uart_interrupt(int irq, FAR void *context, FAR void *arg)
  uint32_t         tmp_val   = 0;
  uint32_t         mask_val  = 0;
-  tmp_val  = BL_RD_REG(uart_priv->uartbase, UART_INT_STS);
+  tmp_val  = bl602_up_serialin(uart_priv->uartbase, UART_INT_STS_OFFSET);
-  mask_val = BL_RD_REG(uart_priv->uartbase, UART_INT_MASK);
+  mask_val = bl602_up_serialin(uart_priv->uartbase, UART_INT_MASK_OFFSET);
  /* Length of uart rx data transfer arrived interrupt */
-  if (BL_IS_REG_BIT_SET(tmp_val, UART_URX_END_INT) &&
+  if ((tmp_val & (1 << UART_URX_END_INT_POS)) &&
-      !BL_IS_REG_BIT_SET(mask_val, UART_CR_URX_END_MASK))
+      !(mask_val & (1 << UART_CR_URX_END_MASK_POS)))
    {
-      BL_WR_REG(uart_priv->uartbase, UART_INT_CLEAR, 0x2);
+      bl602_up_serialout(uart_priv->uartbase, UART_INT_CLEAR_OFFSET, 0x2);
      /* Receive Data ready */
@@ -329,8 +332,8 @@ static int __uart_interrupt(int irq, FAR void *context, FAR void *arg)
  /* Tx fifo ready interrupt,auto-cleared when data is pushed */
-  if (BL_IS_REG_BIT_SET(tmp_val, UART_UTX_FIFO_INT) &&
+  if ((tmp_val & (1 << UART_UTX_FIFO_INT_POS)) &&
-      !BL_IS_REG_BIT_SET(mask_val, UART_CR_UTX_FIFO_MASK))
+      !(mask_val & (1 << UART_CR_UTX_FIFO_MASK_POS)))
    {
      /* Transmit data request interrupt */
@@ -339,8 +342,8 @@ static int __uart_interrupt(int irq, FAR void *context, FAR void *arg)
  /* Rx fifo ready interrupt,auto-cleared when data is popped */
-  if (BL_IS_REG_BIT_SET(tmp_val, UART_URX_FIFO_INT) &&
+  if ((tmp_val & (1 << UART_URX_FIFO_INT_POS)) &&
-      !BL_IS_REG_BIT_SET(mask_val, UART_CR_URX_FIFO_MASK))
+      !(mask_val & (1 << UART_CR_URX_FIFO_MASK_POS)))
    {
      /* Receive Data ready */
@@ -378,20 +381,12 @@ static int up_setup(struct uart_dev_s *dev)
 static void up_shutdown(struct uart_dev_s *dev)
 {
  uint32_t         tmp_val;
  struct up_dev_s *uart_priv = (struct up_dev_s *)dev->priv;
  /* Disable uart before config */
-  tmp_val = BL_RD_REG(uart_priv->uartbase, UART_UTX_CONFIG);
+  bl602_up_serialmodify(uart_priv->uartbase, UART_UTX_CONFIG_OFFSET, 1, 0);
-  BL_WR_REG(uart_priv->uartbase,
+  bl602_up_serialmodify(uart_priv->uartbase, UART_URX_CONFIG_OFFSET, 1, 0);
            UART_UTX_CONFIG,
            BL_CLR_REG_BIT(tmp_val, UART_CR_UTX_EN));
  tmp_val = BL_RD_REG(uart_priv->uartbase, UART_URX_CONFIG);
  BL_WR_REG(uart_priv->uartbase,
            UART_URX_CONFIG,
            BL_CLR_REG_BIT(tmp_val, UART_CR_URX_EN));
 }
 /****************************************************************************
@@ -446,6 +441,16 @@ static void up_detach(struct uart_dev_s *dev)
  irq_detach(priv->irq);
 }
 /****************************************************************************
 * Name: bl602_data_getbits
 ****************************************************************************/
 static uint32_t
 bl602_data_getbits(uint32_t data, uint32_t start, uint32_t len)
 {
  return (((data) >> (start)) & (~((~0) << (len))));
 }
 /****************************************************************************
 * Name: up_ioctl
 *
@@ -613,9 +618,11 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
               * implement TCSADRAIN / TCSAFLUSH
               */
-              tmp_val = BL_RD_REG(priv->uartbase, UART_INT_MASK);
+              tmp_val =
                bl602_up_serialin(priv->uartbase, UART_INT_MASK_OFFSET);
              bl602_uart_configure(priv->uartbase, &config);
-              BL_WR_REG(priv->uartbase, UART_INT_MASK, tmp_val);
+              bl602_up_serialout(
                priv->uartbase, UART_INT_MASK_OFFSET, tmp_val);
            }
        }
      while (0);
@@ -654,10 +661,12 @@ static int up_receive(struct uart_dev_s *dev, unsigned int *status)
  /* if uart fifo cnts > 0 */
-  if (BL_GET_REG_BITS_VAL(BL_RD_REG(priv->uartbase, UART_FIFO_CONFIG_1),
+  if (bl602_data_getbits(
-                          UART_RX_FIFO_CNT) > 0)
+        bl602_up_serialin(priv->uartbase, UART_FIFO_CONFIG_1_OFFSET),
        UART_RX_FIFO_CNT_POS,
        6) > 0)
    {
-      rxdata = BL_RD_BYTE(priv->uartbase + UART_FIFO_RDATA_OFFSET);
+      rxdata = bl602_up_serialin(priv->uartbase, UART_FIFO_RDATA_OFFSET);
    }
  else
    {
@@ -683,18 +692,18 @@ static void up_rxint(struct uart_dev_s *dev, bool enable)
  if (enable)
    {
 #ifndef CONFIG_SUPPRESS_SERIAL_INTS
-      tmp_val = BL_RD_REG(priv->uartbase, UART_INT_MASK);
+      tmp_val = bl602_up_serialin(priv->uartbase, UART_INT_MASK_OFFSET);
      tmp_val &= ~(1 << UART_INT_RX_FIFO_REQ);
      tmp_val &= ~(1 << UART_INT_RX_END);
-      BL_WR_REG(priv->uartbase, UART_INT_MASK, tmp_val);
+      bl602_up_serialout(priv->uartbase, UART_INT_MASK_OFFSET, tmp_val);
 #endif
    }
  else
    {
-      tmp_val = BL_RD_REG(priv->uartbase, UART_INT_MASK);
+      tmp_val = bl602_up_serialin(priv->uartbase, UART_INT_MASK_OFFSET);
      tmp_val |= (1 << UART_INT_RX_FIFO_REQ);
      tmp_val |= (1 << UART_INT_RX_END);
-      BL_WR_REG(priv->uartbase, UART_INT_MASK, tmp_val);
+      bl602_up_serialout(priv->uartbase, UART_INT_MASK_OFFSET, tmp_val);
    }
  leave_critical_section(flags);
@@ -714,8 +723,10 @@ static bool up_rxavailable(struct uart_dev_s *dev)
  /* Return true is data is available in the receive data buffer */
-  uint32_t rxcnt = BL_GET_REG_BITS_VAL(
+  uint32_t rxcnt = bl602_data_getbits(
-    BL_RD_REG(priv->uartbase, UART_FIFO_CONFIG_1), UART_RX_FIFO_CNT);
+    bl602_up_serialin(priv->uartbase, UART_FIFO_CONFIG_1_OFFSET),
    UART_RX_FIFO_CNT_POS,
    6);
  return rxcnt != 0;
 }
@@ -734,11 +745,13 @@ static void up_send(struct uart_dev_s *dev, int ch)
  /* Wait for FIFO */
-  while (BL_GET_REG_BITS_VAL(BL_RD_REG(priv->uartbase, UART_FIFO_CONFIG_1),
+  while (bl602_data_getbits(
-                             UART_TX_FIFO_CNT) == 0)
+           bl602_up_serialin(priv->uartbase, UART_FIFO_CONFIG_1_OFFSET),
           UART_TX_FIFO_CNT_POS,
           6) == 0)
    ;
-  BL_WR_BYTE(priv->uartbase + UART_FIFO_WDATA_OFFSET, ch);
+  bl602_up_serialout(priv->uartbase, UART_FIFO_WDATA_OFFSET, ch);
 }
 /****************************************************************************
@@ -762,9 +775,9 @@ static void up_txint(struct uart_dev_s *dev, bool enable)
 #ifndef CONFIG_SUPPRESS_SERIAL_INTS
      /* Enable the TX interrupt */
-      tmp_val = BL_RD_REG(priv->uartbase, UART_INT_MASK);
+      tmp_val = bl602_up_serialin(priv->uartbase, UART_INT_MASK_OFFSET);
      tmp_val &= ~(1 << UART_INT_TX_FIFO_REQ);
-      BL_WR_REG(priv->uartbase, UART_INT_MASK, tmp_val);
+      bl602_up_serialout(priv->uartbase, UART_INT_MASK_OFFSET, tmp_val);
      /* Fake a TX interrupt here by just calling uart_xmitchars() with
       * interrupts disabled (note this may recurse).
@@ -777,9 +790,9 @@ static void up_txint(struct uart_dev_s *dev, bool enable)
    {
      /* Disable the TX interrupt */
-      tmp_val = BL_RD_REG(priv->uartbase, UART_INT_MASK);
+      tmp_val = bl602_up_serialin(priv->uartbase, UART_INT_MASK_OFFSET);
      tmp_val |= (1 << UART_INT_TX_FIFO_REQ);
-      BL_WR_REG(priv->uartbase, UART_INT_MASK, tmp_val);
+      bl602_up_serialout(priv->uartbase, UART_INT_MASK_OFFSET, tmp_val);
    }
  leave_critical_section(flags);
@@ -799,8 +812,9 @@ static bool up_txready(struct uart_dev_s *dev)
  /* Return TRUE if the TX FIFO is not full */
-  uint32_t txcnt = BL_GET_REG_BITS_VAL(
+  uint32_t txcnt =
-    BL_RD_REG(priv->uartbase, UART_FIFO_CONFIG_1), UART_TX_FIFO_CNT);
+    bl602_up_serialin(priv->uartbase, UART_FIFO_CONFIG_1_OFFSET);
  txcnt = (txcnt & UART_TX_FIFO_CNT_MSK) >> UART_TX_FIFO_CNT_POS;
  return (txcnt != 0);
 }
@@ -819,8 +833,10 @@ static bool up_txempty(struct uart_dev_s *dev)
  /* Return TRUE if the TX is pending */
-  uint32_t txcnt = BL_GET_REG_BITS_VAL(
+  uint32_t txcnt = bl602_data_getbits(
-    BL_RD_REG(priv->uartbase, UART_FIFO_CONFIG_1), UART_TX_FIFO_CNT);
+    bl602_up_serialin(priv->uartbase, UART_FIFO_CONFIG_1_OFFSET),
    UART_TX_FIFO_CNT_POS,
    6);
  return (txcnt == 0);
 }
@@ -983,4 +999,3 @@ int up_putc(int ch)
 }
 #endif /* USE_SERIALDRIVER */
@@ -1,6 +1,9 @@
 /****************************************************************************
 * arch/risc-v/src/bl602/bl602_init.c
 *
 * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved.
 * Author: Gregory Nutt <gnutt@nuttx.org>
 *
 * Licensed to the Apache Software Foundation (ASF) under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.  The
@@ -29,6 +32,7 @@
 #include <arch/board/board.h>
 #include "riscv_arch.h"
 #include "riscv_internal.h"
 #include "chip.h"
@@ -45,18 +49,6 @@
 #define showprogress(c)
 #endif
 #define PARTITION_BOOT2_RAM_ADDR_ACTIVE (0x42049C00)
 #define PARTITION_HEADER_BOOT2_RAM_ADDR (0x42049C04)
 #define PARTITION_BOOT2_FLASH_HEADER    (0x42049d14)
 #define PARTITION_BOOT2_FLASH_CONFIG    (0x42049d18)
 #define PARTITION_MAGIC                 (0x54504642)
 #define PARTITION_FW_PART_NAME          "FW"
 #define PARTITION_FW_PART_HEADER_SIZE   (0x1000)
 /* TODO use header file from project */
 #define FW_XIP_ADDRESS (0x23000000)
 #define BL602_IDLESTACK_SIZE (CONFIG_IDLETHREAD_STACKSIZE & ~3)
 /****************************************************************************
@@ -73,7 +65,7 @@
 * address.
 */
-static uint8_t idle_stack[BL602_IDLESTACK_SIZE];
+static uint8_t g_idle_stack[BL602_IDLESTACK_SIZE];
 /* Dont change the name of varaible, since we refer this
 * boot2_partition_table in linker script
@@ -90,7 +82,7 @@ static struct
 * Public Data
 ****************************************************************************/
-uint32_t g_idle_topstack = (uintptr_t)idle_stack + BL602_IDLESTACK_SIZE;
+uint32_t g_idle_topstack = (uintptr_t)g_idle_stack + BL602_IDLESTACK_SIZE;
 /****************************************************************************
 * Public Functions
@@ -131,9 +123,10 @@ void bfl_main(void)
  /* HBN Config AON pad input and SMT */
-  tmp_val = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+  tmp_val = getreg32(HBN_BASE + HBN_IRQ_MODE_OFFSET);
-  tmp_val = BL_SET_REG_BITS_VAL(tmp_val, HBN_REG_AON_PAD_IE_SMT, 1);
+  tmp_val = (tmp_val & HBN_REG_AON_PAD_IE_SMT_UMSK) |
-  BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmp_val);
+            (1 << HBN_REG_AON_PAD_IE_SMT_POS);
  putreg32(tmp_val, HBN_BASE + HBN_IRQ_MODE_OFFSET);
 #ifdef USE_EARLYSERIALINIT
  up_earlyserialinit();
@@ -152,4 +145,3 @@ void bfl_main(void)
  while (1)
    ;
 }
@@ -1,5 +1,8 @@
 /****************************************************************************
- * boards/risc-v/bl602/evb/src/bl602_lowerhalf.c
+ * arch/risc-v/src/bl602/bl602_tim_lowerhalf.c
 *
 * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved.
 * Author: Gregory Nutt <gnutt@nuttx.org>
 *
 * Licensed to the Apache Software Foundation (ASF) under one or more
 * contributor license agreements.  See the NOTICE file distributed with
@@ -35,6 +38,7 @@
 #include <nuttx/timers/timer.h>
 #include <arch/board/board.h>
 #include "riscv_arch.h"
 #include <hardware/bl602_glb.h>
 #include <hardware/bl602_timer.h>
@@ -50,7 +54,7 @@
 * Private Types
 ****************************************************************************/
-struct bl602_lowerhalf_s
+struct bl602_tim_lowerhalf_s
 {
  FAR const struct timer_ops_s *ops; /* Lower half operations */
@@ -69,15 +73,15 @@ static int bl602_timer_handler(int irq, void *context, void *arg);
 /* "Lower half" driver methods */
-static int  bl602_start(FAR struct timer_lowerhalf_s *lower);
+static int  bl602_tim_start(FAR struct timer_lowerhalf_s *lower);
-static int  bl602_stop(FAR struct timer_lowerhalf_s *lower);
+static int  bl602_tim_stop(FAR struct timer_lowerhalf_s *lower);
-static int  bl602_getstatus(FAR struct timer_lowerhalf_s *lower,
+static int  bl602_tim_getstatus(FAR struct timer_lowerhalf_s *lower,
-                            FAR struct timer_status_s *   status);
+                                FAR struct timer_status_s *   status);
-static int  bl602_settimeout(FAR struct timer_lowerhalf_s *lower,
+static int  bl602_tim_settimeout(FAR struct timer_lowerhalf_s *lower,
-                             uint32_t                      timeout);
+                                 uint32_t                      timeout);
-static void bl602_setcallback(FAR struct timer_lowerhalf_s *lower,
+static void bl602_tim_setcallback(FAR struct timer_lowerhalf_s *lower,
-                              tccb_t                        callback,
+                                  tccb_t                        callback,
-                              FAR void *                    arg);
+                                  FAR void *                    arg);
 /****************************************************************************
 * Private Data
@@ -87,16 +91,16 @@ static void bl602_setcallback(FAR struct timer_lowerhalf_s *lower,
 static const struct timer_ops_s g_timer_ops =
 {
-  .start       = bl602_start,
+  .start       = bl602_tim_start,
-  .stop        = bl602_stop,
+  .stop        = bl602_tim_stop,
-  .getstatus   = bl602_getstatus,
+  .getstatus   = bl602_tim_getstatus,
-  .settimeout  = bl602_settimeout,
+  .settimeout  = bl602_tim_settimeout,
-  .setcallback = bl602_setcallback,
+  .setcallback = bl602_tim_setcallback,
  .ioctl       = NULL,
 };
 #ifdef CONFIG_BL602_TIMER0
-static struct bl602_lowerhalf_s g_tim1_lowerhalf =
+static struct bl602_tim_lowerhalf_s g_tim1_lowerhalf =
 {
  .ops = &g_timer_ops,
  .irq = BL602_IRQ_TIMER_CH0,
@@ -105,7 +109,7 @@ static struct bl602_lowerhalf_s g_tim1_lowerhalf =
 #endif
 #ifdef CONFIG_BL602_TIMER1
-static struct bl602_lowerhalf_s g_tim2_lowerhalf =
+static struct bl602_tim_lowerhalf_s g_tim2_lowerhalf =
 {
  .ops = &g_timer_ops,
  .irq = BL602_IRQ_TIMER_CH1,
@@ -131,8 +135,9 @@ static struct bl602_lowerhalf_s g_tim2_lowerhalf =
 static int bl602_timer_handler(int irq, void *context, void *arg)
 {
-  FAR struct bl602_lowerhalf_s *priv = (FAR struct bl602_lowerhalf_s *)arg;
+  FAR struct bl602_tim_lowerhalf_s *priv =
-  uint32_t                      next_interval_us = 0;
+    (FAR struct bl602_tim_lowerhalf_s *)arg;
  uint32_t next_interval_us = 0;
  /* Clear Interrupt Bits */
@@ -140,54 +145,54 @@ static int bl602_timer_handler(int irq, void *context, void *arg)
  uint32_t tmp_val;
  uint32_t tmp_addr;
-  int_id   = BL_RD_WORD(TIMER_BASE + TIMER_TMSR2_OFFSET + 4 * priv->tim);
+  int_id   = getreg32(TIMER_BASE + TIMER_TMSR2_OFFSET + 4 * priv->tim);
  tmp_addr = TIMER_BASE + TIMER_TICR2_OFFSET + 4 * priv->tim;
-  tmp_val  = BL_RD_WORD(tmp_addr);
+  tmp_val  = getreg32(tmp_addr);
  /* Comparator 0 match interrupt */
-  if (BL_IS_REG_BIT_SET(int_id, TIMER_TMSR_0))
+  if (((int_id) & (1 << (TIMER_TMSR_0_POS))) != 0)
    {
-      BL_WR_WORD(tmp_addr, BL_SET_REG_BIT(tmp_val, TIMER_TCLR_0));
+      putreg32(tmp_val | (1 << TIMER_TCLR_0_POS), tmp_addr);
      if (priv->callback(&next_interval_us, priv->arg))
        {
          if (next_interval_us > 0)
            {
              /* Set a value to the alarm */
-              timer_disable(priv->tim);
+              bl602_timer_disable(priv->tim);
-              timer_setcompvalue(
+              bl602_timer_setcompvalue(
                priv->tim, TIMER_COMP_ID_0, next_interval_us);
-              timer_setpreloadvalue(priv->tim, 0);
+              bl602_timer_setpreloadvalue(priv->tim, 0);
-              timer_enable(priv->tim);
+              bl602_timer_enable(priv->tim);
            }
        }
      else
        {
-          timer_disable(priv->tim);
+          bl602_timer_disable(priv->tim);
-          timer_setpreloadvalue(priv->tim, 0);
+          bl602_timer_setpreloadvalue(priv->tim, 0);
        }
    }
  /* Comparator 1 match interrupt */
-  if (BL_IS_REG_BIT_SET(int_id, TIMER_TMSR_1))
+  if (((int_id) & (1 << (TIMER_TMSR_1_POS))) != 0)
    {
-      BL_WR_WORD(tmp_addr, BL_SET_REG_BIT(tmp_val, TIMER_TCLR_1));
+      putreg32(tmp_val | (1 << TIMER_TCLR_1_POS), tmp_addr);
    }
  /* Comparator 2 match interrupt */
-  if (BL_IS_REG_BIT_SET(int_id, TIMER_TMSR_2))
+  if (((int_id) & (1 << (TIMER_TMSR_2_POS))) != 0)
    {
-      BL_WR_WORD(tmp_addr, BL_SET_REG_BIT(tmp_val, TIMER_TCLR_2));
+      putreg32(tmp_val | (1 << TIMER_TCLR_2_POS), tmp_addr);
    }
  return OK;
 }
 /****************************************************************************
- * Name: bl602_start
+ * Name: bl602_tim_start
 *
 * Description:
 *   Start the timer, resetting the time to the current timeout,
@@ -201,9 +206,10 @@ static int bl602_timer_handler(int irq, void *context, void *arg)
 *
 ****************************************************************************/
-static int bl602_start(FAR struct timer_lowerhalf_s *lower)
+static int bl602_tim_start(FAR struct timer_lowerhalf_s *lower)
 {
-  FAR struct bl602_lowerhalf_s *priv = (FAR struct bl602_lowerhalf_s *)lower;
+  FAR struct bl602_tim_lowerhalf_s *priv =
    (FAR struct bl602_tim_lowerhalf_s *)lower;
  if (!priv->started)
    {
@@ -212,11 +218,11 @@ static int bl602_start(FAR struct timer_lowerhalf_s *lower)
          return -EPERM;
        }
-      timer_setpreloadvalue(priv->tim, 0);
+      bl602_timer_setpreloadvalue(priv->tim, 0);
      irq_attach(priv->irq, bl602_timer_handler, (void *)priv);
      up_enable_irq(priv->irq);
-      timer_intmask(priv->tim, TIMER_INT_COMP_0, 0);
+      bl602_timer_intmask(priv->tim, TIMER_INT_COMP_0, 0);
-      timer_enable(priv->tim);
+      bl602_timer_enable(priv->tim);
      priv->started = true;
      return OK;
    }
@@ -227,7 +233,7 @@ static int bl602_start(FAR struct timer_lowerhalf_s *lower)
 }
 /****************************************************************************
- * Name: bl602_stop
+ * Name: bl602_tim_stop
 *
 * Description:
 *   Stop the timer
@@ -241,18 +247,19 @@ static int bl602_start(FAR struct timer_lowerhalf_s *lower)
 *
 ****************************************************************************/
-static int bl602_stop(FAR struct timer_lowerhalf_s *lower)
+static int bl602_tim_stop(FAR struct timer_lowerhalf_s *lower)
 {
-  FAR struct bl602_lowerhalf_s *priv = (FAR struct bl602_lowerhalf_s *)lower;
+  FAR struct bl602_tim_lowerhalf_s *priv =
    (FAR struct bl602_tim_lowerhalf_s *)lower;
  /* timer disable */
  if (priv->started)
    {
-      timer_disable(priv->tim);
+      bl602_timer_disable(priv->tim);
      priv->started = false;
      up_disable_irq(priv->irq);
-      timer_intmask(priv->tim, TIMER_INT_COMP_0, 1);
+      bl602_timer_intmask(priv->tim, TIMER_INT_COMP_0, 1);
      return OK;
    }
@@ -262,7 +269,7 @@ static int bl602_stop(FAR struct timer_lowerhalf_s *lower)
 }
 /****************************************************************************
- * Name: bl602_getstatus
+ * Name: bl602_tim_getstatus
 *
 * Description:
 *   get timer status
@@ -277,14 +284,15 @@ static int bl602_stop(FAR struct timer_lowerhalf_s *lower)
 *
 ****************************************************************************/
-static int bl602_getstatus(FAR struct timer_lowerhalf_s *lower,
+static int bl602_tim_getstatus(FAR struct timer_lowerhalf_s *lower,
-                           FAR struct timer_status_s *   status)
+                               FAR struct timer_status_s *   status)
 {
-  FAR struct bl602_lowerhalf_s *priv = (FAR struct bl602_lowerhalf_s *)lower;
+  FAR struct bl602_tim_lowerhalf_s *priv =
-  uint32_t                      current_count;
+    (FAR struct bl602_tim_lowerhalf_s *)lower;
  uint32_t current_count;
  status->timeout = timer_getcompvalue(priv->tim, TIMER_COMP_ID_0);
-  current_count   = timer_getcountervalue(priv->tim);
+  current_count   = bl602_timer_getcountervalue(priv->tim);
  if (current_count < status->timeout)
    {
      status->timeleft = status->timeout - current_count;
@@ -298,7 +306,7 @@ static int bl602_getstatus(FAR struct timer_lowerhalf_s *lower,
 }
 /****************************************************************************
- * Name: bl602_settimeout
+ * Name: bl602_tim_settimeout
 *
 * Description:
 *   Set a new timeout value (and reset the timer)
@@ -313,18 +321,19 @@ static int bl602_getstatus(FAR struct timer_lowerhalf_s *lower,
 *
 ****************************************************************************/
-static int bl602_settimeout(FAR struct timer_lowerhalf_s *lower,
+static int bl602_tim_settimeout(FAR struct timer_lowerhalf_s *lower,
-                            uint32_t                      timeout)
+                                uint32_t                      timeout)
 {
-  FAR struct bl602_lowerhalf_s *priv = (FAR struct bl602_lowerhalf_s *)lower;
+  FAR struct bl602_tim_lowerhalf_s *priv =
    (FAR struct bl602_tim_lowerhalf_s *)lower;
-  timer_setcompvalue(priv->tim, TIMER_COMP_ID_0, timeout);
+  bl602_timer_setcompvalue(priv->tim, TIMER_COMP_ID_0, timeout);
  return OK;
 }
 /****************************************************************************
- * Name: bl602_setcallback
+ * Name: bl602_tim_setcallback
 *
 * Description:
 *   Call this user provided timeout handler.
@@ -342,12 +351,13 @@ static int bl602_settimeout(FAR struct timer_lowerhalf_s *lower,
 *
 ****************************************************************************/
-static void bl602_setcallback(FAR struct timer_lowerhalf_s *lower,
+static void bl602_tim_setcallback(FAR struct timer_lowerhalf_s *lower,
-                              tccb_t                        callback,
+                                  tccb_t                        callback,
-                              FAR void *                    arg)
+                                  FAR void *                    arg)
 {
-  struct bl602_lowerhalf_s *priv  = (FAR struct bl602_lowerhalf_s *)lower;
+  struct bl602_tim_lowerhalf_s *priv =
-  irqstate_t                    flags = enter_critical_section();
+    (FAR struct bl602_tim_lowerhalf_s *)lower;
  irqstate_t flags = enter_critical_section();
  /* Save the new callback */
@@ -381,8 +391,8 @@ static void bl602_setcallback(FAR struct timer_lowerhalf_s *lower,
 int bl602_timer_initialize(FAR const char *devpath, int timer)
 {
-  FAR struct bl602_lowerhalf_s *lower;
+  FAR struct bl602_tim_lowerhalf_s *lower;
-  timer_cfg_t                   timstr;
+  timer_cfg_t                       timstr;
  switch (timer)
    {
@@ -413,15 +423,15 @@ int bl602_timer_initialize(FAR const char *devpath, int timer)
  timstr.match_val2     = TIMER_MAX_VALUE;     /* Timer match 2 value 0 */
  timstr.pre_load_val   = TIMER_MAX_VALUE;     /* Timer preload value */
-  glb_ahb_slave1_reset(BL_AHB_SLAVE1_TMR);
+  bl602_glb_ahb_slave1_reset(BL_AHB_SLAVE1_TMR);
-  timer_intmask(lower->tim, TIMER_INT_ALL, 1);
+  bl602_timer_intmask(lower->tim, TIMER_INT_ALL, 1);
  /* timer disable */
-  timer_disable(lower->tim);
+  bl602_timer_disable(lower->tim);
-  timer_init(&timstr);
+  bl602_timer_init(&timstr);
  /* Initialize the elements of lower half state structure */
@@ -448,4 +458,3 @@ int bl602_timer_initialize(FAR const char *devpath, int timer)
  return OK;
 }
@@ -1,6 +1,9 @@
 /**
 * incubator-nuttx/arch/risc-v/src/bl602/bl602_lowerhalf.h
 *
 * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved.
 * Author: Gregory Nutt <gnutt@nuttx.org>
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
@@ -1,6 +1,9 @@
 /****************************************************************************
 * arch/risc-v/src/bl602/bl602_timerisr.c
 *
 * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved.
 * Author: Gregory Nutt <gnutt@nuttx.org>
 *
 * Licensed to the Apache Software Foundation (ASF) under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.  The
@@ -31,7 +34,7 @@
 #include <nuttx/arch.h>
 #include <nuttx/clock.h>
 #include <arch/board/board.h>
-
+#include "hardware/bl602_clint.h"
 #include "riscv_arch.h"
 #include "chip.h"
@@ -40,21 +43,14 @@
 * Pre-processor Definitions
 ****************************************************************************/
-#define TICK_COUNT         (10 * 1000 * 1000 / TICK_PER_SEC)
+/* Private definetions: mtimer frequency */
-#define CLINT_BASE_ADDRESS 0x02000000
+#define TICK_COUNT (10 * 1000 * 1000 / TICK_PER_SEC)
 #define getreg64(a)    (*(volatile uint64_t *)(a))
 #define putreg64(v, a) (*(volatile uint64_t *)(a) = (v))
 /****************************************************************************
 * Private Data
 ****************************************************************************/
-static bool _b_tick_started = false;
+static bool g_b_tick_started = false;
 #define MTIMER_HIGH (CLINT_BASE_ADDRESS + 0xBFFC)
 #define MTIMER_LOW  (CLINT_BASE_ADDRESS + 0xBFF8)
 #define MTIMER_CMP  (CLINT_BASE_ADDRESS + 0x4000)
 /****************************************************************************
 * Private Functions
@@ -68,21 +64,21 @@ static bool _b_tick_started = false;
 static inline uint64_t bl602_clint_time_read(void)
 {
-  uint64_t r = getreg32(MTIMER_HIGH);
+  uint64_t r = getreg32(BL602_MTIMER_HIGH);
  r <<= 32;
-  r |= getreg32(MTIMER_LOW);
+  r |= getreg32(BL602_MTIMER_LOW);
  return r;
 }
 static inline uint64_t bl602_clint_time_cmp_read(void)
 {
-  return getreg64(MTIMER_CMP);
+  return getreg64(BL602_MTIMER_CMP);
 }
 static inline void bl602_clint_time_cmp_write(uint64_t v)
 {
-  putreg64(v, MTIMER_CMP);
+  putreg64(v, BL602_MTIMER_CMP);
 }
 /****************************************************************************
@@ -96,10 +92,10 @@ static void bl602_reload_mtimecmp(void)
  uint64_t current;
  uint64_t next;
-  if (!_b_tick_started)
+  if (!g_b_tick_started)
    {
-      _b_tick_started = true;
+      g_b_tick_started = true;
-      current         = bl602_clint_time_read();
+      current          = bl602_clint_time_read();
    }
  else
    {
@@ -154,4 +150,3 @@ void up_timer_initialize(void)
  up_enable_irq(BL602_IRQ_MTIMER);
 }
@@ -1,6 +1,9 @@
 /****************************************************************************
 * arch/risc-v/src/bl602/bl602_vectors.S
 *
 * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved.
 * Author: Gregory Nutt <gnutt@nuttx.org>
 *
 * Licensed to the Apache Software Foundation (ASF) under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.  The
@@ -1,6 +1,9 @@
 /****************************************************************************
 * arch/risc-v/include/bl602/chip.h
 *
 * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved.
 * Author: Gregory Nutt <gnutt@nuttx.org>
 *
 * Licensed to the Apache Software Foundation (ASF) under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.  The
@@ -0,0 +1,43 @@
 /****************************************************************************
 * arch/risc-v/src/bl602/hardware/bl602_clint.h
 *
 * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved.
 * Author: Gregory Nutt <gnutt@nuttx.org>
 *
 * Licensed to the Apache Software Foundation (ASF) under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.  The
 * ASF licenses this file to you under the Apache License, Version 2.0 (the
 * "License"); you may not use this file except in compliance with the
 * License.  You may obtain a copy of the License at
 *
 *   http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
 * License for the specific language governing permissions and limitations
 * under the License.
 *
 ****************************************************************************/
 #ifndef __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_CLINT_H
 #define __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_CLINT_H
 /****************************************************************************
 * Included Files
 ****************************************************************************/
 #include <stdint.h>
 /****************************************************************************
 * Pre-processor Definitions
 ****************************************************************************/
 #define BL602_CLINT_BASE (0x02000000)
 #define BL602_MTIMER_HIGH ((uint32_t *)(BL602_CLINT_BASE + 0xBFFC))
 #define BL602_MTIMER_LOW  ((uint32_t *)(BL602_CLINT_BASE + 0xBFF8))
 #define BL602_MTIMER_CMP  ((uint64_t *)(BL602_CLINT_BASE + 0x4000))
 #endif /* __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_CLINT_H */
@@ -1,6 +1,9 @@
 /****************************************************************************
 * arch/risc-v/src/bl602/hardware/bl602_common.h
 *
 * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved.
 * Author: Gregory Nutt <gnutt@nuttx.org>
 *
 * Licensed to the Apache Software Foundation (ASF) under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.  The
@@ -31,131 +34,126 @@
 * Pre-processor Definitions
 ****************************************************************************/
-#define BL602_FLASH_XIP_BASE        0x23000000
+#define BL602_FLASH_XIP_BASE        (0x23000000)
 #define BL602_FLASH_XIP_END         (0x23000000 + 16 * 1024 * 1024)
-#define BL602_FLASH_XIP_REMAP0_BASE 0x33000000
+#define BL602_FLASH_XIP_REMAP0_BASE (0x33000000)
 #define BL602_FLASH_XIP_REMAP0_END  (0x33000000 + 16 * 1024 * 1024)
-#define BL602_FLASH_XIP_REMAP1_BASE 0x43000000
+#define BL602_FLASH_XIP_REMAP1_BASE (0x43000000)
 #define BL602_FLASH_XIP_REMAP1_END  (0x43000000 + 16 * 1024 * 1024)
-#define BL602_FLASH_XIP_REMAP2_BASE 0x53000000
+#define BL602_FLASH_XIP_REMAP2_BASE (0x53000000)
 #define BL602_FLASH_XIP_REMAP2_END  (0x53000000 + 16 * 1024 * 1024)
-#define BL602_WRAM_BASE        0x42020000
+#define BL602_WRAM_BASE        (0x42020000)
 #define BL602_WRAM_END         (0x42020000 + 176 * 1024)
-#define BL602_WRAM_REMAP0_BASE 0x22020000
+#define BL602_WRAM_REMAP0_BASE (0x22020000)
 #define BL602_WRAM_REMAP0_END  (0x22020000 + 176 * 1024)
-#define BL602_WRAM_REMAP1_BASE 0x32020000
+#define BL602_WRAM_REMAP1_BASE (0x32020000)
 #define BL602_WRAM_REMAP1_END  (0x32020000 + 176 * 1024)
-#define BL602_WRAM_REMAP2_BASE 0x52020000
+#define BL602_WRAM_REMAP2_BASE (0x52020000)
 #define BL602_WRAM_REMAP2_END  (0x52020000 + 176 * 1024)
-#define BL602_TCM_BASE        0x22008000
+#define BL602_TCM_BASE        (0x22008000)
 #define BL602_TCM_END         (0x22008000 + (96 + 176) * 1024)
-#define BL602_TCM_REMAP0_BASE 0x32008000
+#define BL602_TCM_REMAP0_BASE (0x32008000)
 #define BL602_TCM_REMAP0_END  (0x32008000 + (96 + 176) * 1024)
-#define BL602_TCM_REMAP1_BASE 0x42008000
+#define BL602_TCM_REMAP1_BASE (0x42008000)
 #define BL602_TCM_REMAP1_END  (0x42008000 + (96 + 176) * 1024)
-#define BL602_TCM_REMAP2_BASE 0x52008000
+#define BL602_TCM_REMAP2_BASE (0x52008000)
 #define BL602_TCM_REMAP2_END  (0x52008000 + (96 + 176) * 1024)
 /* BL602 peripherals base address */
-#define GLB_BASE ((uint32_t)0x40000000)
+#define GLB_BASE (0x40000000)
-#define RF_BASE  ((uint32_t)0x40001000)
+#define RF_BASE  (0x40001000)
 /* AUX module base address */
-#define GPIP_BASE ((uint32_t)0x40002000)
+#define GPIP_BASE (0x40002000)
 /* Security Debug module base address */
-#define SEC_DBG_BASE ((uint32_t)0x40003000)
+#define SEC_DBG_BASE (0x40003000)
 /* Security Engine module base address */
-#define SEC_ENG_BASE ((uint32_t)0x40004000)
+#define SEC_ENG_BASE (0x40004000)
 /* Trustzone control security base address */
-#define TZC_SEC_BASE ((uint32_t)0x40005000)
+#define TZC_SEC_BASE (0x40005000)
 /* Trustzone control none-security base address */
-#define TZC_NSEC_BASE ((uint32_t)0x40006000)
+#define TZC_NSEC_BASE (0x40006000)
-#define EF_DATA_BASE  ((uint32_t)0x40007000)
+#define EF_DATA_BASE  (0x40007000)
-#define EF_CTRL_BASE  ((uint32_t)0x40007000)
+#define EF_CTRL_BASE  (0x40007000)
-#define CCI_BASE      ((uint32_t)0x40008000)
+#define CCI_BASE      (0x40008000)
 /* L1 cache config base address */
-#define L1C_BASE         ((uint32_t)0x40009000)
+#define L1C_BASE         (0x40009000)
-#define UART0_BASE       ((uint32_t)0x4000A000)
+#define UART0_BASE       (0x4000A000)
-#define UART1_BASE       ((uint32_t)0x4000A100)
+#define UART1_BASE       (0x4000A100)
-#define SPI_BASE         ((uint32_t)0x4000A200)
+#define SPI_BASE         (0x4000A200)
-#define I2C_BASE         ((uint32_t)0x4000A300)
+#define I2C_BASE         (0x4000A300)
-#define PWM_BASE         ((uint32_t)0x4000A400)
+#define PWM_BASE         (0x4000A400)
-#define TIMER_BASE       ((uint32_t)0x4000A500)
+#define TIMER_BASE       (0x4000A500)
-#define IR_BASE          ((uint32_t)0x4000A600)
+#define IR_BASE          (0x4000A600)
-#define SF_CTRL_BASE     ((uint32_t)0x4000B000)
+#define SF_CTRL_BASE     (0x4000B000)
-#define SF_CTRL_BUF_BASE ((uint32_t)0x4000B700)
+#define SF_CTRL_BUF_BASE (0x4000B700)
-#define DMA_BASE         ((uint32_t)0x4000C000)
+#define DMA_BASE         (0x4000C000)
-#define SDU_BASE         ((uint32_t)0x4000D000)
+#define SDU_BASE         (0x4000D000)
 /* Power down sleep module base address */
-#define PDS_BASE ((uint32_t)0x4000E000)
+#define PDS_BASE (0x4000E000)
 /* Hibernate module base address */
-#define HBN_BASE ((uint32_t)0x4000F000)
+#define HBN_BASE (0x4000F000)
 /* Always on module base address */
-#define AON_BASE     ((uint32_t)0x4000F000)
+#define AON_BASE     (0x4000F000)
-#define HBN_RAM_BASE ((uint32_t)0x40010000)
+#define HBN_RAM_BASE (0x40010000)
-#define BL_RD_WORD(addr)       (*((volatile uint32_t *)(addr)))
+/* Delay for a while */
-#define BL_WR_WORD(addr, val)  ((*(volatile uint32_t *)(addr)) = (val))
+
-#define BL_RD_SHORT(addr)      (*((volatile uint16_t *)(addr)))
+#define BL_DRV_DUMMY() \
 #define BL_WR_SHORT(addr, val) ((*(volatile uint16_t *)(addr)) = (val))
 #define BL_RD_BYTE(addr)       (*((volatile uint8_t *)(addr)))
 #define BL_WR_BYTE(addr, val)  ((*(volatile uint8_t *)(addr)) = (val))
 #define BL_RDWD_FRM_BYTEP(p) \
  ((p[3] << 24) | (p[2] << 16) | (p[1] << 8) | (p[0]))
 #define BL_WRWD_TO_BYTEP(p, val) \
  { \
-    p[0] = val & 0xff; \
+    __asm volatile("nop"); \
-    p[1] = (val >> 8) & 0xff; \
+    __asm volatile("nop"); \
-    p[2] = (val >> 16) & 0xff; \
+    __asm volatile("nop"); \
-    p[3] = (val >> 24) & 0xff; \
+    __asm volatile("nop"); \
  }
 /**
 * @brief Register access macro
 */
 #define BL_RD_REG16(addr, regname) BL_RD_SHORT(addr + regname##_OFFSET)
 #define BL_WR_REG16(addr, regname, val) \
  BL_WR_SHORT(addr + regname##_OFFSET, val)
 #define BL_RD_REG(addr, regname)      BL_RD_WORD(addr + regname##_OFFSET)
 #define BL_WR_REG(addr, regname, val) BL_WR_WORD(addr + regname##_OFFSET, val)
 #define BL_SET_REG_BIT(val, bitname)  ((val) | (1U << bitname##_POS))
 #define BL_CLR_REG_BIT(val, bitname)  ((val)&bitname##_UMSK)
 #define BL_GET_REG_BITS_VAL(val, bitname) \
  (((val)&bitname##_MSK) >> bitname##_POS)
 #define BL_SET_REG_BITS_VAL(val, bitname, bitval) \
  (((val)&bitname##_UMSK) | ((uint32_t)(bitval) << bitname##_POS))
 #define BL_IS_REG_BIT_SET(val, bitname) \
  (((val) & (1U << (bitname##_POS))) != 0)
 #define __NOP() \
  __asm volatile("nop") /* This implementation generates debug information \
                         */
 #define BL_DRV_DUMMY \
  { \
    __NOP(); \
    __NOP(); \
    __NOP(); \
    __NOP(); \
  }
 #define BL_AHB_SLAVE1_GLB                0x00
 #define BL_AHB_SLAVE1_RF                 0x01
 #define BL_AHB_SLAVE1_GPIP_PHY_AGC       0x02
 #define BL_AHB_SLAVE1_SEC_DBG            0x03
 #define BL_AHB_SLAVE1_SEC                0x04
 #define BL_AHB_SLAVE1_TZ1                0x05
 #define BL_AHB_SLAVE1_TZ2                0x06
 #define BL_AHB_SLAVE1_EFUSE              0x07
 #define BL_AHB_SLAVE1_CCI                0x08
 #define BL_AHB_SLAVE1_L1C                0x09
 #define BL_AHB_SLAVE1_RSVD0A             0x0a
 #define BL_AHB_SLAVE1_SFC                0x0b
 #define BL_AHB_SLAVE1_DMA                0x0c
 #define BL_AHB_SLAVE1_SDU                0x0d
 #define BL_AHB_SLAVE1_PDS_HBN_AON_HBNRAM 0x0e
 #define BL_AHB_SLAVE1_RSVD0F             0x0f
 #define BL_AHB_SLAVE1_UART0              0x10
 #define BL_AHB_SLAVE1_UART1              0x11
 #define BL_AHB_SLAVE1_SPI                0x12
 #define BL_AHB_SLAVE1_I2C                0x13
 #define BL_AHB_SLAVE1_PWM                0x14
 #define BL_AHB_SLAVE1_TMR                0x15
 #define BL_AHB_SLAVE1_IRR                0x16
 #define BL_AHB_SLAVE1_CKS                0x17
 #define BL_AHB_SLAVE1_MAX                0x18
 /* Std driver attribute macro */
 #define ATTR_CLOCK_SECTION       __attribute__((section(".sclock_rlt_code")))
@@ -164,8 +162,6 @@
 #define ATTR_TCM_CONST_SECTION   __attribute__((section(".tcm_const")))
 #define ATTR_DTCM_SECTION        __attribute__((section(".tcm_data")))
 #define ATTR_HSRAM_SECTION       __attribute__((section(".hsram_code")))
 #define SystemCoreClockSet(val)  BL_WR_WORD(0x4000f108, val)
 #define SystemCoreClockGet(val)  BL_RD_WORD(0x4000f108)
 /****************************************************************************
 * Public Types
@@ -173,39 +169,6 @@
 #ifndef __ASSEMBLY__
 enum bl_ahb_slave1_e
 {
  BL_AHB_SLAVE1_GLB                = 0x00,
  BL_AHB_SLAVE1_RF                 = 0x01,
  BL_AHB_SLAVE1_GPIP_PHY_AGC       = 0x02,
  BL_AHB_SLAVE1_SEC_DBG            = 0x03,
  BL_AHB_SLAVE1_SEC                = 0x04,
  BL_AHB_SLAVE1_TZ1                = 0x05,
  BL_AHB_SLAVE1_TZ2                = 0x06,
  BL_AHB_SLAVE1_EFUSE              = 0x07,
  BL_AHB_SLAVE1_CCI                = 0x08,
  BL_AHB_SLAVE1_L1C                = 0x09,
  BL_AHB_SLAVE1_RSVD0A             = 0x0a,
  BL_AHB_SLAVE1_SFC                = 0x0b,
  BL_AHB_SLAVE1_DMA                = 0x0c,
  BL_AHB_SLAVE1_SDU                = 0x0d,
  BL_AHB_SLAVE1_PDS_HBN_AON_HBNRAM = 0x0e,
  BL_AHB_SLAVE1_RSVD0F             = 0x0f,
  BL_AHB_SLAVE1_UART0              = 0x10,
  BL_AHB_SLAVE1_UART1              = 0x11,
  BL_AHB_SLAVE1_SPI                = 0x12,
  BL_AHB_SLAVE1_I2C                = 0x13,
  BL_AHB_SLAVE1_PWM                = 0x14,
  BL_AHB_SLAVE1_TMR                = 0x15,
  BL_AHB_SLAVE1_IRR                = 0x16,
  BL_AHB_SLAVE1_CKS                = 0x17,
  BL_AHB_SLAVE1_MAX                = 0x18,
 };
 /****************************************************************************
 * Public Data
 ****************************************************************************/
 #ifdef __cplusplus
 #define EXTERN extern "C"
 extern "C"
@@ -214,14 +177,6 @@ extern "C"
 #define EXTERN extern
 #endif
 /****************************************************************************
 * Inline Functions
 ****************************************************************************/
 /****************************************************************************
 * Public Function Prototypes
 ****************************************************************************/
 #undef EXTERN
 #ifdef __cplusplus
 }
@@ -1,6 +1,9 @@
 /****************************************************************************
 * arch/risc-v/src/bl602/hardware/bl602_gpio.h
 *
 * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved.
 * Author: Gregory Nutt <gnutt@nuttx.org>
 *
 * Licensed to the Apache Software Foundation (ASF) under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.  The
@@ -33,27 +36,27 @@
 /* Input Floating Mode */
-#define GPIO_MODE_INPUT ((uint32_t)0x00000000U)
+#define GPIO_MODE_INPUT (0x00000000)
 /* Output Push Pull Mode */
-#define GPIO_MODE_OUTPUT ((uint32_t)0x00000001U)
+#define GPIO_MODE_OUTPUT (0x00000001)
 /* Alternate function */
-#define GPIO_MODE_AF ((uint32_t)0x00000002U)
+#define GPIO_MODE_AF (0x00000002)
 /* GPIO pull up */
-#define GPIO_PULL_UP ((uint32_t)0x00000000U)
+#define GPIO_PULL_UP (0x00000000)
 /* GPIO pull down */
-#define GPIO_PULL_DOWN ((uint32_t)0x00000001U)
+#define GPIO_PULL_DOWN (0x00000001)
 /* GPIO no pull up or down */
-#define GPIO_PULL_NONE ((uint32_t)0x00000002U)
+#define GPIO_PULL_NONE (0x00000002)
 /* GPIO0 function definition */
@@ -406,56 +409,50 @@
 #ifndef __ASSEMBLY__
-enum gpio_pins_e
+#define GLB_GPIO_PIN_0  0
-{
+#define GLB_GPIO_PIN_1  1
-  GLB_GPIO_PIN_0 = 0,
+#define GLB_GPIO_PIN_2  2
-  GLB_GPIO_PIN_1,
+#define GLB_GPIO_PIN_3  3
-  GLB_GPIO_PIN_2,
+#define GLB_GPIO_PIN_4  4
-  GLB_GPIO_PIN_3,
+#define GLB_GPIO_PIN_5  5
-  GLB_GPIO_PIN_4,
+#define GLB_GPIO_PIN_6  6
-  GLB_GPIO_PIN_5,
+#define GLB_GPIO_PIN_7  7
-  GLB_GPIO_PIN_6,
+#define GLB_GPIO_PIN_8  8
-  GLB_GPIO_PIN_7,
+#define GLB_GPIO_PIN_9  9
-  GLB_GPIO_PIN_8,
+#define GLB_GPIO_PIN_10 10
-  GLB_GPIO_PIN_9,
+#define GLB_GPIO_PIN_11 11
-  GLB_GPIO_PIN_10,
+#define GLB_GPIO_PIN_12 12
-  GLB_GPIO_PIN_11,
+#define GLB_GPIO_PIN_13 13
-  GLB_GPIO_PIN_12,
+#define GLB_GPIO_PIN_14 14
-  GLB_GPIO_PIN_13,
+#define GLB_GPIO_PIN_15 15
-  GLB_GPIO_PIN_14,
+#define GLB_GPIO_PIN_16 16
-  GLB_GPIO_PIN_15,
+#define GLB_GPIO_PIN_17 17
-  GLB_GPIO_PIN_16,
+#define GLB_GPIO_PIN_18 18
-  GLB_GPIO_PIN_17,
+#define GLB_GPIO_PIN_19 19
-  GLB_GPIO_PIN_18,
+#define GLB_GPIO_PIN_20 20
-  GLB_GPIO_PIN_19,
+#define GLB_GPIO_PIN_21 21
-  GLB_GPIO_PIN_20,
+#define GLB_GPIO_PIN_22 22
-  GLB_GPIO_PIN_21,
+#define GLB_GPIO_PIN_MA 23
  GLB_GPIO_PIN_22,
  GLB_GPIO_PIN_MAX
 };
-enum gpio_fun_e
+#define GPIO_FUN_SDIO   1
-{
+#define GPIO_FUN_FLASH  2
-  GPIO_FUN_SDIO   = 1,
+#define GPIO_FUN_SPI    4
-  GPIO_FUN_FLASH  = 2,
+#define GPIO_FUN_I2C    6
-  GPIO_FUN_SPI    = 4,
+#define GPIO_FUN_UART   7
-  GPIO_FUN_I2C    = 6,
+#define GPIO_FUN_PWM    8
-  GPIO_FUN_UART   = 7,
+#define GPIO_FUN_EXT_PA 8
-  GPIO_FUN_PWM    = 8,
+#define GPIO_FUN_ANALOG 10
-  GPIO_FUN_EXT_PA = 8,
+#define GPIO_FUN_SWGPIO 11
-  GPIO_FUN_ANALOG = 10,
+#define GPIO_FUN_JTAG   14
  GPIO_FUN_SWGPIO = 11,
  GPIO_FUN_JTAG   = 14
 };
 struct gpio_cfg_s
 {
-  enum gpio_pins_e gpio_pin;
+  int gpio_pin;
-  enum gpio_fun_e  gpio_fun;
+  int gpio_fun;
-  int              gpio_mode;
+  int gpio_mode;
-  int              pull_type;
+  int pull_type;
-  int              drive;
+  int drive;
-  int              smt_ctrl;
+  int smt_ctrl;
 };
 /****************************************************************************
@@ -479,7 +476,7 @@ extern "C"
 ****************************************************************************/
 /****************************************************************************
- * Name: gpio_init
+ * Name: bl602_gpio_init
 *
 * Description:
 *   Init a gpio pin.
@@ -496,7 +493,7 @@ extern "C"
 *
 ****************************************************************************/
-EXTERN void gpio_init(struct gpio_cfg_s *cfg);
+EXTERN void bl602_gpio_init(struct gpio_cfg_s *cfg);
 #undef EXTERN
 #ifdef __cplusplus
@@ -1,6 +1,9 @@
 /****************************************************************************
 * arch/risc-v/src/bl602/hardware/bl602_timer.h
 *
 * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved.
 * Author: Gregory Nutt <gnutt@nuttx.org>
 *
 * Licensed to the Apache Software Foundation (ASF) under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.  The
@@ -500,116 +503,85 @@
 #define TIMER_WCDR_MSK    (((1U << TIMER_WCDR_LEN) - 1) << TIMER_WCDR_POS)
 #define TIMER_WCDR_UMSK   (~(((1U << TIMER_WCDR_LEN) - 1) << TIMER_WCDR_POS))
-#define WDT_ENABLE_ACCESS() \
+/* TIMER channel type definition */
-  { \
+
-    BL_WR_REG(TIMER_BASE, \
+#define TIMER_CH0    0 /* TIMER channel 0 port define */
-              TIMER_WFAR, \
+#define TIMER_CH1    1 /* TIMER channel 1 port define */
-              BL_SET_REG_BITS_VAL( \
+#define TIMER_CH_MAX 2
-                BL_RD_REG(TIMER_BASE, TIMER_WFAR), TIMER_WFAR, 0xBABA)); \
+
-    BL_WR_REG(TIMER_BASE, \
+/* TIMER clock source type definition */
-              TIMER_WSAR, \
+
-              BL_SET_REG_BITS_VAL( \
+#define TIMER_CLKSRC_FCLK 0 /* TIMER clock source :System CLK */
-                BL_RD_REG(TIMER_BASE, TIMER_WSAR), TIMER_WSAR, 0xEB10)); \
+#define TIMER_CLKSRC_32K  1 /* TIMER clock source :32K CLK */
-  }
+#define TIMER_CLKSRC_1K   2 /* TIMER clock source :1K CLK,Only for
                             * Timer not for  Watchdog */
 #define TIMER_CLKSRC_XTAL 3  /* TIMER clock source :XTAL CLK */
 /* TIMER match compare ID type definition */
 #define TIMER_COMP_ID_0 0 /* TIMER match compare ID 0 define */
 #define TIMER_COMP_ID_1 1 /* TIMER match compare ID 1 define */
 #define TIMER_COMP_ID_2 2 /* TIMER match compare ID 2 define */
 /* TIMER preload source type definition */
 #define TIMER_PRELOAD_TRIG_NONE 0 /* TIMER no preload source, just free run \
                                   */
 #define TIMER_PRELOAD_TRIG_COMP0 \
  1 /* TIMER count register preload triggered by \
     * comparator 0 */
 #define TIMER_PRELOAD_TRIG_COMP1 \
  2 /* TIMER count register preload triggered by \
     * comparator 1 */
 #define TIMER_PRELOAD_TRIG_COMP2 \
  3 /* TIMER count register preload triggered by \
     * comparator 2 */
 /* TIMER count register run mode type definition */
 #define TIMER_COUNT_PRELOAD \
  0 /* TIMER count register preload from comparator \
     * register */
 #define TIMER_COUNT_FREERUN 1 /* TIMER count register free run */
 /* TIMER interrupt type definition */
 #define TIMER_INT_COMP_0 0 /* Comparator 0 match cause interrupt */
 #define TIMER_INT_COMP_1 1 /* Comparator 1 match cause interrupt */
 #define TIMER_INT_COMP_2 2 /* Comparator 2 match cause interrupt */
 #define TIMER_INT_ALL    3
 /* Watchdog timer interrupt type definition */
 #define WDT_INT     0 /* Comparator 0 match cause interrupt */
 #define WDT_INT_ALL 1
 /****************************************************************************
 * Public Types
 ****************************************************************************/
 #ifndef __ASSEMBLY__
 /* TIMER channel type definition */
 enum timer_chan_e
 {
  TIMER_CH0, /* TIMER channel 0 port define */
  TIMER_CH1, /* TIMER channel 1 port define */
  TIMER_CH_MAX
 };
 typedef enum timer_chan_e timer_chan_t;
 /* TIMER clock source type definition */
 enum timer_clksrc_e
 {
  TIMER_CLKSRC_FCLK, /* TIMER clock source :System CLK */
  TIMER_CLKSRC_32K,  /* TIMER clock source :32K CLK */
  TIMER_CLKSRC_1K,   /* TIMER clock source :1K CLK,Only for Timer not for
                      * Watchdog */
  TIMER_CLKSRC_XTAL  /* TIMER clock source :XTAL CLK */
 };
 typedef enum timer_clksrc_e timer_clksrc_t;
 /* TIMER match compare ID type definition */
 enum timer_comp_id_e
 {
  TIMER_COMP_ID_0, /* TIMER match compare ID 0 define */
  TIMER_COMP_ID_1, /* TIMER match compare ID 1 define */
  TIMER_COMP_ID_2  /* TIMER match compare ID 2 define */
 };
 typedef enum timer_comp_id_e timer_comp_id_t;
 /* TIMER preload source type definition */
 enum timer_preload_trig_e
 {
  TIMER_PRELOAD_TRIG_NONE,  /* TIMER no preload source, just free run */
  TIMER_PRELOAD_TRIG_COMP0, /* TIMER count register preload triggered by
                             * comparator 0 */
  TIMER_PRELOAD_TRIG_COMP1, /* TIMER count register preload triggered by
                             * comparator 1 */
  TIMER_PRELOAD_TRIG_COMP2  /* TIMER count register preload triggered by
                             * comparator 2 */
 };
 typedef enum timer_preload_trig_e timer_preload_trig_t;
 /* TIMER count register run mode type definition */
 enum timer_countmode_e
 {
  TIMER_COUNT_PRELOAD, /* TIMER count register preload from comparator
                        * register */
  TIMER_COUNT_FREERUN  /* TIMER count register free run */
 };
 typedef enum timer_countmode_e timer_countmode_t;
 /* TIMER interrupt type definition */
 enum timer_int_e
 {
  TIMER_INT_COMP_0, /* Comparator 0 match cause interrupt */
  TIMER_INT_COMP_1, /* Comparator 1 match cause interrupt */
  TIMER_INT_COMP_2, /* Comparator 2 match cause interrupt */
  TIMER_INT_ALL
 };
 typedef enum timer_int_e timer_int_t;
 /* Watchdog timer interrupt type definition */
 enum wdt_int_e
 {
  WDT_INT, /* Comparator 0 match cause interrupt */
  WDT_INT_ALL
 };
 typedef enum wdt_int_e wdt_int_t;
 /* TIMER configuration structure type definition */
 struct timer_cfg_s
 {
-  timer_chan_t   timer_ch; /* Timer channel */
+  uint32_t timer_ch; /* Timer channel */
-  timer_clksrc_t clk_src;  /* Timer clock source */
+  uint32_t clk_src;  /* Timer clock source */
  /* Timer count register preload trigger source slelect */
-  timer_preload_trig_t pl_trig_src;
+  uint32_t pl_trig_src;
-  timer_countmode_t count_mode;     /* Timer count mode */
+  uint32_t count_mode;     /* Timer count mode */
-  uint8_t           clock_division; /* Timer clock divison value */
+  uint8_t  clock_division; /* Timer clock divison value */
-  uint32_t          match_val0;     /* Timer match 0 value 0 */
+  uint32_t match_val0;     /* Timer match 0 value 0 */
-  uint32_t          match_val1;     /* Timer match 1 value 0 */
+  uint32_t match_val1;     /* Timer match 1 value 0 */
-  uint32_t          match_val2;     /* Timer match 2 value 0 */
+  uint32_t match_val2;     /* Timer match 2 value 0 */
-  uint32_t          pre_load_val;   /* Timer preload value */
+  uint32_t pre_load_val;   /* Timer preload value */
 };
 typedef struct timer_cfg_s timer_cfg_t;
@@ -626,37 +598,33 @@ extern "C"
 * Public Function Prototypes
 ****************************************************************************/
-EXTERN uint32_t timer_getcompvalue(timer_chan_t    timer_ch,
+EXTERN uint32_t bl602_timer_getcompvalue(uint32_t timer_ch, uint32_t cmp_no);
-                                   timer_comp_id_t cmp_no);
+EXTERN void bl602_timer_setcompvalue(uint32_t timer_ch, uint32_t cmp_no,
-EXTERN void     timer_setcompvalue(timer_chan_t    timer_ch,
+                                     uint32_t val);
-                                   timer_comp_id_t cmp_no,
+EXTERN uint32_t bl602_timer_getcountervalue(uint32_t timer_ch);
-                                   uint32_t        val);
+EXTERN uint32_t bl602_timer_getmatchstatus(uint32_t timer_ch,
-EXTERN uint32_t timer_getcountervalue(timer_chan_t timer_ch);
+                                           uint32_t cmp_no);
-EXTERN uint32_t timer_getmatchstatus(timer_chan_t    timer_ch,
+EXTERN uint32_t bl602_timer_getpreloadvalue(uint32_t timer_ch);
-                                     timer_comp_id_t cmp_no);
+EXTERN void bl602_timer_setpreloadvalue(uint32_t timer_ch, uint32_t val);
-EXTERN uint32_t timer_getpreloadvalue(timer_chan_t timer_ch);
+EXTERN void bl602_timer_setpreloadtrigsrc(uint32_t timer_ch,
-EXTERN void     timer_setpreloadvalue(timer_chan_t timer_ch, uint32_t val);
+                                          uint32_t pl_src);
-EXTERN void     timer_setpreloadtrigsrc(timer_chan_t         timer_ch,
+EXTERN void bl602_timer_setcountmode(uint32_t timer_ch, uint32_t count_mode);
-                                        timer_preload_trig_t pl_src);
+EXTERN void bl602_timer_clearintstatus(uint32_t timer_ch, uint32_t cmp_no);
-EXTERN void     timer_setcountmode(timer_chan_t      timer_ch,
+EXTERN void bl602_timer_init(timer_cfg_t *timer_cfg);
-                                   timer_countmode_t count_mode);
+EXTERN void bl602_timer_enable(uint32_t timer_ch);
-EXTERN void     timer_clearintstatus(timer_chan_t    timer_ch,
+EXTERN void bl602_timer_disable(uint32_t timer_ch);
-                                     timer_comp_id_t cmp_no);
+EXTERN void bl602_timer_intmask(uint32_t timer_ch, uint32_t int_type,
-EXTERN void     timer_init(timer_cfg_t *timer_cfg);
+                                uint32_t int_mask);
-EXTERN void     timer_enable(timer_chan_t timer_ch);
+EXTERN void bl602_wdt_set_clock(uint32_t clk_src, uint8_t div);
-EXTERN void     timer_disable(timer_chan_t timer_ch);
+EXTERN uint32_t bl602_wdt_getmatchvalue(void);
-EXTERN void     timer_intmask(timer_chan_t timer_ch,
+EXTERN void bl602_wdt_setcompvalue(uint16_t val);
-                    timer_int_t int_type, uint32_t int_mask);
+EXTERN uint16_t bl602_wdt_getcountervalue(void);
-EXTERN void     wdt_set_clock(timer_clksrc_t clk_src, uint8_t div);
+EXTERN void bl602_wdt_resetcountervalue(void);
-EXTERN uint32_t wdt_getmatchvalue(void);
+EXTERN uint32_t bl602_wdt_getresetstatus(void);
-EXTERN void     wdt_setcompvalue(uint16_t val);
+EXTERN void bl602_wdt_clearresetstatus(void);
-EXTERN uint16_t wdt_getcountervalue(void);
+EXTERN void bl602_wdt_enable(void);
-EXTERN void     wdt_resetcountervalue(void);
+EXTERN void bl602_wdt_disable(void);
-EXTERN uint32_t wdt_getresetstatus(void);
+EXTERN void bl602_wdt_intmask(uint32_t int_type, uint32_t int_mask);
 EXTERN void     wdt_clearresetstatus(void);
 EXTERN void     wdt_enable(void);
 EXTERN void     wdt_disable(void);
 EXTERN void     wdt_intmask(wdt_int_t int_type, uint32_t int_mask);
 #undef EXTERN
 #if defined(__cplusplus)
@@ -1,6 +1,9 @@
 /****************************************************************************
 * arch/risc-v/src/bl602/hardware/clic.h
 *
 * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved.
 * Author: Gregory Nutt <gnutt@nuttx.org>
 *
 * Licensed to the Apache Software Foundation (ASF) under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.  The
@@ -25,8 +28,8 @@
 * Pre-processor Definitions
 ****************************************************************************/
-#define CLIC_CTRL_ADDR  0x02000000UL
+#define CLIC_CTRL_ADDR  0x02000000
-#define CLIC_HART0_ADDR 0x02800000UL
+#define CLIC_HART0_ADDR 0x02800000
 #define CLIC_MSIP          0x0000
 #define CLIC_MSIP_size     0x4
@@ -61,6 +61,7 @@
 # define putreg16(v,a)        (*(volatile uint16_t *)(a) = (v))
 # define getreg32(a)          (*(volatile uint32_t *)(a))
 # define putreg32(v,a)        (*(volatile uint32_t *)(a) = (v))
 # define getreg64(a)          (*(volatile uint64_t *)(a))
 # define putreg64(v,a)        (*(volatile uint64_t *)(a) = (v))
 /****************************************************************************
@@ -4,7 +4,7 @@
 2. Download Bouffalo lab flash tools
-  $ git clone https://github.com/bouffalo/flash_tools.git
+  $ git clone https://github.com/bouffalolab/flash_tools.git
 3. Configure and build NuttX
@@ -1,6 +1,9 @@
 /****************************************************************************
 * boards/risc-v/bl602/bl602evb/include/board.h
 *
 * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved.
 * Author: Gregory Nutt <gnutt@nuttx.org>
 *
 * Licensed to the Apache Software Foundation (ASF) under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.  The
@@ -37,47 +37,13 @@ SECTIONS
    *(.rodata .rodata.*)
    *(.sdata2.*)
    /* static cli cmds */
    . = ALIGN(4);
    _bl_static_cli_cmds_start = .;
    KEEP(*(.static_cli_cmds))
    *(.static_cli_cmds)
    _bl_static_cli_cmds_end = .;
    /* static fw attribute entry */
    . = ALIGN(4);
    _bl_static_fw_cfg_entry_start = .;
    KEEP(*(.wifi.cfg.entry))
    _bl_static_fw_cfg_entry_end = .;
    /* static blog code1 */
    . = ALIGN(4);
    _bl_static_blogcomponent_code_start = .;
    KEEP(SORT(*)(.static_blogcomponent_code*))
    *(.static_blogcomponent_code*)
    _bl_static_blogcomponent_code_end = .;
    /* static blog code2 */
    . = ALIGN(4);
    _bl_static_blogfile_code_start = .;
    KEEP(SORT(*)(.static_blogfile_code*))
    *(.static_blogfile_code*)
    _bl_static_blogfile_code_end = .;
    /* static blog code3 */
    . = ALIGN(4);
    _bl_static_blogpri_code_start = .;
    KEEP(SORT(*)(.static_blogpri_code*))
    *(.static_blogpri_code*)
    _bl_static_blogpri_code_end = .;
    *(.gnu.linkonce.r.*)
    /*Framework table section, use ALIGN here to avoid fill section*/
    . = ALIGN(4);
    _rom_framework_audio_device_start = .;
    KEEP(*(.framework.audio_device))
    _rom_framework_audio_device_end = .;
  } > flash
  /*put wifibss in the first place*/
@@ -108,8 +74,6 @@ SECTIONS
  .romdata       :
  {
    /*always put freetos under global_pointer with the following order. No change!*/
    PROVIDE( __global_pointer_head$ =  . );
    PROVIDE( __global_pointer$ = . + 0x7F0 );
    . = . + 0x498;
  } > ram_tcm AT > flash
@@ -181,29 +145,17 @@ SECTIONS
  PROVIDE( _heap_start = . );
  PROVIDE( _heap_size = ADDR(.stack) - _heap_start );
  .stack ORIGIN(ram_tcm) + LENGTH(ram_tcm) - __stack_size (NOLOAD) :
  {
    . = . + __stack_size;
    PROVIDE( _sp_main = . );
    __freertos_irq_stack_top = .;
  } >ram_tcm
  /*CFG FW used in code*/
  PROVIDE( _ld_bl_static_cfg_entry_start = _bl_static_fw_cfg_entry_start );
  PROVIDE( _ld_bl_static_cfg_entry_end   = _bl_static_fw_cfg_entry_end );
  PROVIDE( _ld_ram_size0 = LENGTH(flash) );
  PROVIDE( _ld_ram_addr0 = ORIGIN(flash) );
  PROVIDE( _ld_ram_size1 = LENGTH(ram_tcm) );
  PROVIDE( _ld_ram_addr1 = ORIGIN(ram_tcm) );
  PROVIDE( _ld_ram_size2 = LENGTH(ram_wifi) );
  PROVIDE( _ld_ram_addr2 = ORIGIN(ram_wifi) );
  /*BOOT2 sections*/
  PROVIDE ( __boot2_pt_addr_src = BOOT2_PT_ADDR );
  PROVIDE ( __boot2_flash_cfg_src = BOOT2_FLASHCFG_ADDR ); 
  PROVIDE (__LD_CONFIG_EM_SEL = __EM_SIZE);
 }
@@ -1,6 +1,9 @@
 /****************************************************************************
 * boards/risc-v/bl602/evb/src/bl602_appinit.c
 *
 * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved.
 * Author: Gregory Nutt <gnutt@nuttx.org>
 *
 * Licensed to the Apache Software Foundation (ASF) under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.  The
@@ -1,6 +1,9 @@
 /****************************************************************************
 * boards/risc-v/bl602/evb/src/bl602_boot.c
 *
 * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved.
 * Author: Gregory Nutt <gnutt@nuttx.org>
 *
 * Licensed to the Apache Software Foundation (ASF) under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.  The
@@ -1,6 +1,9 @@
 /****************************************************************************
 * boards/risc-v/bl602/evb/src/bl602_bringup.c
 *
 * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved.
 * Author: Gregory Nutt <gnutt@nuttx.org>
 *
 * Licensed to the Apache Software Foundation (ASF) under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.  The
@@ -1,6 +1,9 @@
 /****************************************************************************
 * boards/risc-v/bl602/bl602evb/src/bl602evb.h
 *
 * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved.
 * Author: Gregory Nutt <gnutt@nuttx.org>
 *
 * Licensed to the Apache Software Foundation (ASF) under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.  The