diff --git a/arch/risc-v/include/bl602/chip.h b/arch/risc-v/include/bl602/chip.h index afc95b0b160..a0e7b265829 100644 --- a/arch/risc-v/include/bl602/chip.h +++ b/arch/risc-v/include/bl602/chip.h @@ -1,6 +1,9 @@ /**************************************************************************** * arch/risc-v/include/bl602/chip.h * + * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with * this work for additional information regarding copyright ownership. The diff --git a/arch/risc-v/include/bl602/irq.h b/arch/risc-v/include/bl602/irq.h index aef56640298..dd30c8ff9cc 100644 --- a/arch/risc-v/include/bl602/irq.h +++ b/arch/risc-v/include/bl602/irq.h @@ -1,6 +1,9 @@ /**************************************************************************** * arch/risc-v/include/bl602/irq.h * + * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with * this work for additional information regarding copyright ownership. The diff --git a/arch/risc-v/src/bl602/Make.defs b/arch/risc-v/src/bl602/Make.defs index f172c499af2..1d1b23118cd 100644 --- a/arch/risc-v/src/bl602/Make.defs +++ b/arch/risc-v/src/bl602/Make.defs @@ -1,6 +1,9 @@ ############################################################################ # arch/risc-v/src/bl602/Make.defs # +# Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# # Licensed to the Apache Software Foundation (ASF) under one or more # contributor license agreements. See the NOTICE file distributed with # this work for additional information regarding copyright ownership. The @@ -46,11 +49,14 @@ endif # Specify our C code within this directory to be included CHIP_CSRCS = bl602_allocateheap.c CHIP_CSRCS += bl602_idle.c bl602_irq.c bl602_irq_dispatch.c -CHIP_CSRCS += bl602_serial.c bl602_lowputc.c +CHIP_CSRCS += bl602_serial.c bl602_lowputc.c bl602_tim.c CHIP_CSRCS += bl602_start.c bl602_timerisr.c ifeq ($(CONFIG_TIMER),y) -CHIP_CSRCS += bl602_tim.c bl602_tim_lowerhalf.c bl602_oneshot_lowerhalf.c +CHIP_CSRCS += bl602_tim_lowerhalf.c +endif +ifeq ($(CONFIG_ONESHOT),y) +CHIP_CSRCS += bl602_oneshot_lowerhalf.c endif CHIP_CSRCS += bl602_glb.c bl602_gpio.c bl602_hbn.c diff --git a/arch/risc-v/src/bl602/bl602_allocateheap.c b/arch/risc-v/src/bl602/bl602_allocateheap.c index 065c30cd9c1..be7d2f90b89 100644 --- a/arch/risc-v/src/bl602/bl602_allocateheap.c +++ b/arch/risc-v/src/bl602/bl602_allocateheap.c @@ -1,6 +1,9 @@ /**************************************************************************** * arch/risc-v/src/bl602/bl602_allocateheap.c * + * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with * this work for additional information regarding copyright ownership. The diff --git a/arch/risc-v/src/bl602/bl602_boot2.h b/arch/risc-v/src/bl602/bl602_boot2.h index e4611a70c6c..cab98fc95cf 100644 --- a/arch/risc-v/src/bl602/bl602_boot2.h +++ b/arch/risc-v/src/bl602/bl602_boot2.h @@ -1,6 +1,9 @@ /**************************************************************************** * arch/risc-v/src/bl602/bl602_boot2.h * + * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with * this work for additional information regarding copyright ownership. The @@ -31,45 +34,42 @@ * Pre-processor Definitions ****************************************************************************/ +/* Partition table error type definition */ + +#define PT_ERROR_SUCCESS 0 /* Partition table error type:success */ +#define PT_ERROR_TABLE_NOT_VALID \ + 1 /* Partition table error type:entry not found */ +#define PT_ERROR_ENTRY_NOT_FOUND \ + 2 /* Partition table error type:entry not found */ +#define PT_ERROR_ENTRY_UPDATE_FAIL \ + 3 /* Partition table error type:entry update fail */ +#define PT_ERROR_CRC32 4 /* Partition table error type:crc32 error */ +#define PT_ERROR_PARAMETER \ + 5 /* Partition table error type:input parameter error */ +#define PT_ERROR_FALSH_READ \ + 6 /* Partition table error type:flash read error */ +#define PT_ERROR_FALSH_WRITE \ + 7 /* Partition table error type:flash write error */ +#define PT_ERROR_FALSH_ERASE \ + 8 /* Partition table error type:flash erase error */ + +/* Partition id type definition */ + +#define PT_TABLE_ID_0 0 /* Partition table ID 0 */ +#define PT_TABLE_ID_1 1 /* Partition table ID 1 */ +#define PT_TABLE_ID_INVALID 2 /* Partition table ID invalid */ + +/* Partition id type definition */ + +#define PT_ENTRY_FW_CPU0 0 /* Partition entry type:CPU0 firmware */ +#define PT_ENTRY_FW_CPU1 1 /* Partition entry type:CPU1 firmware */ +#define PT_ENTRY_MAX 16 /* Partition entry type:Max */ + /**************************************************************************** * Public Types ****************************************************************************/ #ifndef __ASSEMBLY__ -/* Partition table error type definition */ - -enum pt_table_error_e -{ - PT_ERROR_SUCCESS, /* Partition table error type:success */ - PT_ERROR_TABLE_NOT_VALID, /* Partition table error type:entry not found */ - PT_ERROR_ENTRY_NOT_FOUND, /* Partition table error type:entry not found */ - PT_ERROR_ENTRY_UPDATE_FAIL, /* Partition table error type:entry update fail - */ - - PT_ERROR_CRC32, /* Partition table error type:crc32 error */ - PT_ERROR_PARAMETER, /* Partition table error type:input parameter error */ - PT_ERROR_FALSH_READ, /* Partition table error type:flash read error */ - PT_ERROR_FALSH_WRITE, /* Partition table error type:flash write error */ - PT_ERROR_FALSH_ERASE /* Partition table error type:flash erase error */ -}; - -/* Partition id type definition */ - -enum pt_table_id_e -{ - PT_TABLE_ID_0, /* Partition table ID 0 */ - PT_TABLE_ID_1, /* Partition table ID 1 */ - PT_TABLE_ID_INVALID, /* Partition table ID invalid */ -}; - -/* Partition id type definition */ - -enum pt_table_entry_type_e -{ - PT_ENTRY_FW_CPU0, /* Partition entry type:CPU0 firmware */ - PT_ENTRY_FW_CPU1, /* Partition entry type:CPU1 firmware */ - PT_ENTRY_MAX = 16, /* Partition entry type:Max */ -}; /* Partition table config definition */ diff --git a/arch/risc-v/src/bl602/bl602_config.h b/arch/risc-v/src/bl602/bl602_config.h index 74c199c3c5c..a5b9a12d327 100644 --- a/arch/risc-v/src/bl602/bl602_config.h +++ b/arch/risc-v/src/bl602/bl602_config.h @@ -1,6 +1,9 @@ /**************************************************************************** * arch/risc-v/src/bl602/bl602_config.h * + * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with * this work for additional information regarding copyright ownership. The diff --git a/arch/risc-v/src/bl602/bl602_entry.S b/arch/risc-v/src/bl602/bl602_entry.S index 6c0a659de88..a7e709f3cda 100644 --- a/arch/risc-v/src/bl602/bl602_entry.S +++ b/arch/risc-v/src/bl602/bl602_entry.S @@ -1,6 +1,9 @@ /**************************************************************************** * arch/risc-v/src/bl602/bl602_entry.S * + * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with * this work for additional information regarding copyright ownership. The @@ -24,121 +27,128 @@ #include - .section .init - .globl bl602_start - .globl __start - .type bl602_start,@function + .section .init + .globl bl602_start + .globl __start + .type bl602_start,@function __start: bl602_start: - .cfi_startproc - .cfi_undefined ra - .option push - .option norelax + .cfi_startproc + .cfi_undefined ra + .option push + .option norelax /*disable IRQ*/ - li t0, MSTATUS_MIE - csrc mstatus, t0 + li t0, MSTATUS_MIE + csrc mstatus, t0 - la gp, __global_pointer$ + la gp, __global_pointer$ .option pop - la sp, _sp_main + la sp, _sp_main #ifndef RUN_IN_RAM - /* Load boot2 partition address */ - la a0, __boot2_pt_addr_src - la a1, __boot2_pt_addr_start - la a2, __boot2_pt_addr_end - bgeu a1, a2, 2f + /* Load boot2 partition address */ -1: - lw t0, (a0) - sw t0, (a1) - addi a0, a0, 4 - addi a1, a1, 4 - bltu a1, a2, 1b + la a0, __boot2_pt_addr_src + la a1, __boot2_pt_addr_start + la a2, __boot2_pt_addr_end + bgeu a1, a2, bl602_entry_load_boot2_partiton_address_end -2: - /* Load boot2 flashCfg address */ +bl602_entry_load_boot2_partiton_address_loop: + lw t0, (a0) + sw t0, (a1) + addi a0, a0, 4 + addi a1, a1, 4 + bltu a1, a2, bl602_entry_load_boot2_partiton_address_loop - jal boot2_get_flash_addr - la a1, __boot2_flash_cfg_start - la a2, __boot2_flash_cfg_end - bgeu a1, a2, 2f +bl602_entry_load_boot2_partiton_address_end: -1: - lw t0, (a0) - sw t0, (a1) - addi a0, a0, 4 - addi a1, a1, 4 - bltu a1, a2, 1b + /* Load boot2 flashCfg address */ -2: + jal boot2_get_flash_addr + la a1, __boot2_flash_cfg_start + la a2, __boot2_flash_cfg_end + bgeu a1, a2, bl602_entry_load_boot2_flashcfg_address_end + +bl602_entry_load_boot2_flashcfg_address_loop: + lw t0, (a0) + sw t0, (a1) + addi a0, a0, 4 + addi a1, a1, 4 + bltu a1, a2, bl602_entry_load_boot2_flashcfg_address_loop + +bl602_entry_load_boot2_flashcfg_address_end: #endif - /* Load data section */ - la a0, _data_load - la a1, _data_run - la a2, _data_run_end - bgeu a1, a2, 2f + /* Load data section */ -1: - lw t0, (a0) - sw t0, (a1) - addi a0, a0, 4 - addi a1, a1, 4 - bltu a1, a2, 1b + la a0, _data_load + la a1, _data_run + la a2, _data_run_end + bgeu a1, a2, bl602_entry_load_data_section_end -2: - /* Clear bss section */ +bl602_entry_load_data_section_loop: + lw t0, (a0) + sw t0, (a1) + addi a0, a0, 4 + addi a1, a1, 4 + bltu a1, a2, bl602_entry_load_data_section_loop - la a0, __bss_start - la a1, __bss_end - bgeu a0, a1, 3f +bl602_entry_load_data_section_end: -1: - sw zero, (a0) - addi a0, a0, 4 - bltu a0, a1, 1b + /* Clear bss section */ - /* Clear bss section */ + la a0, __bss_start + la a1, __bss_end + bgeu a0, a1, bl602_entry_zero_bss_end - la a0, __wifi_bss_start - la a1, __wifi_bss_end - bgeu a0, a1, 3f +bl602_entry_zero_bss_loop: + sw zero, (a0) + addi a0, a0, 4 + bltu a0, a1, bl602_entry_zero_bss_loop +bl602_entry_zero_bss_end: -1: - sw zero, (a0) - addi a0, a0, 4 - bltu a0, a1, 1b + /* Clear bss section */ + + la a0, __wifi_bss_start + la a1, __wifi_bss_end + bgeu a0, a1, bl602_entry_zero_wifi_bss_end + +bl602_entry_zero_wifi_bss_loop: + sw zero, (a0) + addi a0, a0, 4 + bltu a0, a1, bl602_entry_zero_wifi_bss_loop +bl602_entry_zero_wifi_bss_end: -3: #ifndef __riscv_float_abi_soft - /* Enable FPU */ - li t0, MSTATUS_FS - csrs mstatus, t0 - csrr t1, mstatus - and t1, t1, t0 - beqz t1, 1f - fssr x0 -1: + /* Enable FPU */ + + li t0, MSTATUS_FS + csrs mstatus, t0 + csrr t1, mstatus + and t1, t1, t0 + beqz t1, bl602_entry_enable_fpu_end + fssr x0 + +bl602_entry_enable_fpu_end: #endif - auipc ra, 0 - addi sp, sp, -16 - sw ra, 8(sp) + auipc ra, 0 + addi sp, sp, -16 + sw ra, 8(sp) - /* argc = argv = 0 */ + /* argc = argv = 0 */ - li a0, 0 - li a1, 0 - call bfl_main + li a0, 0 + li a1, 0 + call bfl_main -1: - j 1b +bl602_entry_deadloop: + j bl602_entry_deadloop - .cfi_endproc + .cfi_endproc diff --git a/arch/risc-v/src/bl602/bl602_glb.c b/arch/risc-v/src/bl602/bl602_glb.c index c517ba1b0e1..8ed11a3be94 100644 --- a/arch/risc-v/src/bl602/bl602_glb.c +++ b/arch/risc-v/src/bl602/bl602_glb.c @@ -1,6 +1,9 @@ /**************************************************************************** * arch/risc-v/src/bl602/bl602_glb.c * + * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with * this work for additional information regarding copyright ownership. The @@ -23,13 +26,14 @@ ****************************************************************************/ #include "hardware/bl602_glb.h" +#include "riscv_arch.h" /**************************************************************************** * Public Functions ****************************************************************************/ /**************************************************************************** - * Name: glb_uart_fun_sel + * Name: bl602_glb_uart_fun_sel * * Description: * Select UART signal function. @@ -43,12 +47,13 @@ * ****************************************************************************/ -void glb_uart_fun_sel(enum glb_uart_sig_e sig, enum glb_uart_sig_fun_e fun) +void bl602_glb_uart_fun_sel(int sig, int fun) { uint32_t sig_pos = 0; uint32_t tmp_val = 0; - tmp_val = BL_RD_REG(GLB_BASE, GLB_UART_SIG_SEL_0); + tmp_val = getreg32(GLB_BASE + GLB_UART_SIG_SEL_0_OFFSET); + sig_pos = (sig * 4); /* Clear original val */ @@ -58,11 +63,11 @@ void glb_uart_fun_sel(enum glb_uart_sig_e sig, enum glb_uart_sig_fun_e fun) /* Set new value */ tmp_val = tmp_val | (fun << sig_pos); - BL_WR_REG(GLB_BASE, GLB_UART_SIG_SEL_0, tmp_val); + putreg32(tmp_val, GLB_BASE + GLB_UART_SIG_SEL_0_OFFSET); } /**************************************************************************** - * Name: glb_ahb_slave1_reset + * Name: bl602_glb_ahb_slave1_reset * * Description: * Select UART signal function. @@ -76,20 +81,31 @@ void glb_uart_fun_sel(enum glb_uart_sig_e sig, enum glb_uart_sig_fun_e fun) * ****************************************************************************/ -void glb_ahb_slave1_reset(enum bl_ahb_slave1_e slave1) +void bl602_glb_ahb_slave1_reset(uint32_t slave1) { uint32_t tmp_val = 0; - tmp_val = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG1); + tmp_val = getreg32(GLB_BASE + GLB_SWRST_CFG1_OFFSET); tmp_val &= (~(1 << slave1)); - BL_WR_REG(GLB_BASE, GLB_SWRST_CFG1, tmp_val); - BL_DRV_DUMMY; - tmp_val = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG1); - tmp_val |= (1 << slave1); - BL_WR_REG(GLB_BASE, GLB_SWRST_CFG1, tmp_val); - BL_DRV_DUMMY; - tmp_val = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG1); - tmp_val &= (~(1 << slave1)); - BL_WR_REG(GLB_BASE, GLB_SWRST_CFG1, tmp_val); -} + putreg32(tmp_val, GLB_BASE + GLB_SWRST_CFG1_OFFSET); + /* It is to prevent glitch, which cannot be accessed via bus immediately + * after certain register operations, so some nop is added + */ + + BL_DRV_DUMMY(); + + tmp_val = getreg32(GLB_BASE + GLB_SWRST_CFG1_OFFSET); + tmp_val |= (1 << slave1); + putreg32(tmp_val, GLB_BASE + GLB_SWRST_CFG1_OFFSET); + + /* It is to prevent glitch, which cannot be accessed via bus immediately + * after certain register operations, so some nop is added + */ + + BL_DRV_DUMMY(); + + tmp_val = getreg32(GLB_BASE + GLB_SWRST_CFG1_OFFSET); + tmp_val &= (~(1 << slave1)); + putreg32(tmp_val, GLB_BASE + GLB_SWRST_CFG1_OFFSET); +} diff --git a/arch/risc-v/src/bl602/bl602_gpio.c b/arch/risc-v/src/bl602/bl602_gpio.c index 6c2fc29ef41..dd2cc241676 100644 --- a/arch/risc-v/src/bl602/bl602_gpio.c +++ b/arch/risc-v/src/bl602/bl602_gpio.c @@ -1,6 +1,9 @@ /**************************************************************************** * arch/risc-v/src/bl602/bl602_gpio.c * + * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with * this work for additional information regarding copyright ownership. The @@ -25,13 +28,14 @@ #include #include "hardware/bl602_gpio.h" #include "hardware/bl602_glb.h" +#include "riscv_arch.h" /**************************************************************************** * Public Functions ****************************************************************************/ /**************************************************************************** - * Name: gpio_init + * Name: bl602_gpio_init * * Description: * Init a gpio pin. @@ -48,7 +52,7 @@ * ****************************************************************************/ -void gpio_init(struct gpio_cfg_s *cfg) +void bl602_gpio_init(struct gpio_cfg_s *cfg) { uint8_t gpio_pin = cfg->gpio_pin; uint32_t *p_out; @@ -66,7 +70,7 @@ void gpio_init(struct gpio_cfg_s *cfg) tmp_out &= (~(1 << pos)); *p_out = tmp_out; - tmp_val = BL_RD_WORD(GLB_BASE + GLB_GPIO_OFFSET + gpio_pin / 2 * 4); + tmp_val = getreg32(GLB_BASE + GLB_GPIO_OFFSET + gpio_pin / 2 * 4); if (gpio_pin % 2 == 0) { @@ -74,32 +78,33 @@ void gpio_init(struct gpio_cfg_s *cfg) if (cfg->gpio_mode == GPIO_MODE_OUTPUT) { - tmp_val = BL_CLR_REG_BIT(tmp_val, GLB_REG_GPIO_0_IE); + tmp_val = tmp_val & GLB_REG_GPIO_0_IE_UMSK; tmp_out |= (1 << pos); } else { - tmp_val = BL_SET_REG_BIT(tmp_val, GLB_REG_GPIO_0_IE); + tmp_val = tmp_val | (1 << GLB_REG_GPIO_0_IE_POS); } /* Set pull up or down */ - tmp_val = BL_CLR_REG_BIT(tmp_val, GLB_REG_GPIO_0_PU); - tmp_val = BL_CLR_REG_BIT(tmp_val, GLB_REG_GPIO_0_PD); + tmp_val &= GLB_REG_GPIO_0_PU_UMSK; + tmp_val &= GLB_REG_GPIO_0_PD_UMSK; if (cfg->pull_type == GPIO_PULL_UP) { - tmp_val = BL_SET_REG_BIT(tmp_val, GLB_REG_GPIO_0_PU); + tmp_val = tmp_val | (1 << GLB_REG_GPIO_0_PU_POS); } else if (cfg->pull_type == GPIO_PULL_DOWN) { - tmp_val = BL_SET_REG_BIT(tmp_val, GLB_REG_GPIO_0_PD); + tmp_val = tmp_val | (1 << GLB_REG_GPIO_0_PD_POS); } - tmp_val = BL_SET_REG_BITS_VAL(tmp_val, GLB_REG_GPIO_0_DRV, cfg->drive); - tmp_val = - BL_SET_REG_BITS_VAL(tmp_val, GLB_REG_GPIO_0_SMT, cfg->smt_ctrl); - tmp_val = - BL_SET_REG_BITS_VAL(tmp_val, GLB_REG_GPIO_0_FUNC_SEL, cfg->gpio_fun); + tmp_val = (tmp_val & GLB_REG_GPIO_0_DRV_UMSK) | + (cfg->drive << GLB_REG_GPIO_0_DRV_POS); + tmp_val = (tmp_val & GLB_REG_GPIO_0_SMT_UMSK) | + (cfg->smt_ctrl << GLB_REG_GPIO_0_SMT_POS); + tmp_val = (tmp_val & GLB_REG_GPIO_0_FUNC_SEL_UMSK) | + (cfg->gpio_fun << GLB_REG_GPIO_0_FUNC_SEL_POS); } else { @@ -107,36 +112,36 @@ void gpio_init(struct gpio_cfg_s *cfg) if (cfg->gpio_mode == GPIO_MODE_OUTPUT) { - tmp_val = BL_CLR_REG_BIT(tmp_val, GLB_REG_GPIO_1_IE); + tmp_val &= GLB_REG_GPIO_1_IE_UMSK; tmp_out |= (1 << pos); } else { - tmp_val = BL_SET_REG_BIT(tmp_val, GLB_REG_GPIO_1_IE); + tmp_val = tmp_val | (1 << GLB_REG_GPIO_1_IE_POS); } /* Set pull up or down */ - tmp_val = BL_CLR_REG_BIT(tmp_val, GLB_REG_GPIO_1_PU); - tmp_val = BL_CLR_REG_BIT(tmp_val, GLB_REG_GPIO_1_PD); + tmp_val &= GLB_REG_GPIO_1_PU_UMSK; + tmp_val &= GLB_REG_GPIO_1_PD_UMSK; if (cfg->pull_type == GPIO_PULL_UP) { - tmp_val = BL_SET_REG_BIT(tmp_val, GLB_REG_GPIO_1_PU); + tmp_val = tmp_val | (1 << GLB_REG_GPIO_1_PU_POS); } else if (cfg->pull_type == GPIO_PULL_DOWN) { - tmp_val = BL_SET_REG_BIT(tmp_val, GLB_REG_GPIO_1_PD); + tmp_val = tmp_val | (1 << GLB_REG_GPIO_1_PD_POS); } - tmp_val = BL_SET_REG_BITS_VAL(tmp_val, GLB_REG_GPIO_1_DRV, cfg->drive); - tmp_val = - BL_SET_REG_BITS_VAL(tmp_val, GLB_REG_GPIO_1_SMT, cfg->smt_ctrl); - tmp_val = - BL_SET_REG_BITS_VAL(tmp_val, GLB_REG_GPIO_1_FUNC_SEL, cfg->gpio_fun); + tmp_val = (tmp_val & GLB_REG_GPIO_1_DRV_UMSK) | + (cfg->drive << GLB_REG_GPIO_1_DRV_POS); + tmp_val = (tmp_val & GLB_REG_GPIO_1_SMT_UMSK) | + (cfg->smt_ctrl << GLB_REG_GPIO_1_SMT_POS); + tmp_val = (tmp_val & GLB_REG_GPIO_1_FUNC_SEL_UMSK) | + (cfg->gpio_fun << GLB_REG_GPIO_1_FUNC_SEL_POS); } - BL_WR_WORD(GLB_BASE + GLB_GPIO_OFFSET + gpio_pin / 2 * 4, tmp_val); + putreg32(tmp_val, GLB_BASE + GLB_GPIO_OFFSET + gpio_pin / 2 * 4); *p_out = tmp_out; } - diff --git a/arch/risc-v/src/bl602/bl602_hbn.c b/arch/risc-v/src/bl602/bl602_hbn.c index cb58d213d59..884353c9568 100644 --- a/arch/risc-v/src/bl602/bl602_hbn.c +++ b/arch/risc-v/src/bl602/bl602_hbn.c @@ -1,6 +1,8 @@ /**************************************************************************** - * - * + * arch/risc-v/src/bl602/bl602_hbn.c + * + * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -24,13 +26,14 @@ ****************************************************************************/ #include "hardware/bl602_hbn.h" +#include "riscv_arch.h" /**************************************************************************** * Public Functions ****************************************************************************/ /**************************************************************************** - * Name: hbn_set_uart_clk_sel + * Name: bl602_hbn_set_uart_clk_sel * * Description: * Select uart clock source. @@ -47,12 +50,12 @@ * ****************************************************************************/ -void hbn_set_uart_clk_sel(enum hbn_uart_clk_type_e clk_sel) +void bl602_hbn_set_uart_clk_sel(int clk_sel) { uint32_t tmp_val; - tmp_val = BL_RD_REG(HBN_BASE, HBN_GLB); - tmp_val = BL_SET_REG_BITS_VAL(tmp_val, HBN_UART_CLK_SEL, clk_sel); - BL_WR_REG(HBN_BASE, HBN_GLB, tmp_val); + tmp_val = getreg32(HBN_BASE + HBN_GLB_OFFSET); + tmp_val &= ~(1 << 2); + tmp_val |= (clk_sel << 2); + putreg32(tmp_val, HBN_BASE + HBN_GLB_OFFSET); } - diff --git a/arch/risc-v/src/bl602/bl602_head.S b/arch/risc-v/src/bl602/bl602_head.S index 33b17037828..3fc0ea6e2fe 100644 --- a/arch/risc-v/src/bl602/bl602_head.S +++ b/arch/risc-v/src/bl602/bl602_head.S @@ -1,6 +1,9 @@ /**************************************************************************** * arch/risc-v/src/bl602/bl602_head.S * + * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with * this work for additional information regarding copyright ownership. The @@ -34,6 +37,7 @@ /**************************************************************************** * Name: exception_common ****************************************************************************/ + .align 8 exception_common: diff --git a/arch/risc-v/src/bl602/bl602_idle.c b/arch/risc-v/src/bl602/bl602_idle.c index 36f096a96e8..64f4f539de7 100644 --- a/arch/risc-v/src/bl602/bl602_idle.c +++ b/arch/risc-v/src/bl602/bl602_idle.c @@ -1,6 +1,9 @@ /**************************************************************************** * arch/risc-v/src/bl602/bl602_idle.c * + * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with * this work for additional information regarding copyright ownership. The @@ -65,4 +68,3 @@ void up_idle(void) #endif } - diff --git a/arch/risc-v/src/bl602/bl602_irq.c b/arch/risc-v/src/bl602/bl602_irq.c index 9b6d748ba56..60e92916e2c 100644 --- a/arch/risc-v/src/bl602/bl602_irq.c +++ b/arch/risc-v/src/bl602/bl602_irq.c @@ -1,6 +1,9 @@ /**************************************************************************** * arch/risc-v/src/bl602/bl602_irq.c * + * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with * this work for additional information regarding copyright ownership. The @@ -46,22 +49,22 @@ static inline void bl_irq_enable(unsigned int source) { - *(volatile uint8_t *)(CLIC_HART0_ADDR + CLIC_INTIE + source) = 1; + putreg8(1, CLIC_HART0_ADDR + CLIC_INTIE + source); } static inline void bl_irq_disable(unsigned int source) { - *(volatile uint8_t *)(CLIC_HART0_ADDR + CLIC_INTIE + source) = 0; + putreg8(0, CLIC_HART0_ADDR + CLIC_INTIE + source); } static inline void bl_irq_pending_set(unsigned int source) { - *(volatile uint8_t *)(CLIC_HART0_ADDR + CLIC_INTIP + source) = 1; + putreg8(1, CLIC_HART0_ADDR + CLIC_INTIP + source); } static inline void bl_irq_pending_clear(unsigned int source) { - *(volatile uint8_t *)(CLIC_HART0_ADDR + CLIC_INTIP + source) = 0; + putreg8(0, CLIC_HART0_ADDR + CLIC_INTIP + source); } /**************************************************************************** @@ -122,7 +125,7 @@ void up_disable_irq(int irq) } else if (irq == BL602_IRQ_MTIMER) { - *(volatile uint8_t *)CLIC_TIMER_ENABLE_ADDRESS = 0; + putreg8(0, CLIC_TIMER_ENABLE_ADDRESS); /* Read mstatus & clear machine timer interrupt enable in mie */ @@ -155,7 +158,7 @@ void up_enable_irq(int irq) } else if (irq == BL602_IRQ_MTIMER) { - *(volatile uint8_t *)CLIC_TIMER_ENABLE_ADDRESS = 1; + putreg8(1, CLIC_TIMER_ENABLE_ADDRESS); /* Read mstatus & set machine timer interrupt enable in mie */ @@ -255,4 +258,3 @@ irqstate_t up_irq_enable(void) asm volatile("csrrs %0, mstatus, %1" : "=r"(oldstat) : "r"(MSTATUS_MIE)); return oldstat; } - diff --git a/arch/risc-v/src/bl602/bl602_irq_dispatch.c b/arch/risc-v/src/bl602/bl602_irq_dispatch.c index bdc1452fc86..60f71a668fc 100644 --- a/arch/risc-v/src/bl602/bl602_irq_dispatch.c +++ b/arch/risc-v/src/bl602/bl602_irq_dispatch.c @@ -1,6 +1,9 @@ /**************************************************************************** * arch/risc-v/src/bl602/bl602_irq_dispatch.c * + * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with * this work for additional information regarding copyright ownership. The @@ -103,4 +106,3 @@ void *bl602_dispatch_irq(uint32_t vector, uint32_t *regs) return regs; } - diff --git a/arch/risc-v/src/bl602/bl602_lowputc.c b/arch/risc-v/src/bl602/bl602_lowputc.c index 6e66b6b9fc5..66c4810b3ed 100644 --- a/arch/risc-v/src/bl602/bl602_lowputc.c +++ b/arch/risc-v/src/bl602/bl602_lowputc.c @@ -1,6 +1,9 @@ /**************************************************************************** * boards/risc-v/bl602/evb/src/bl602_lowputc.c * + * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with * this work for additional information regarding copyright ownership. The @@ -54,6 +57,7 @@ ****************************************************************************/ /* Select UART parameters for the selected console */ + #ifdef HAVE_SERIAL_CONSOLE #if defined(CONFIG_UART0_SERIAL_CONSOLE) #define BL602_CONSOLE_IDX 0 @@ -144,9 +148,9 @@ static void uart_gpio_init(uint8_t id, uint8_t cts_pin, uint8_t rts_pin) { - struct gpio_cfg_s cfg; - enum glb_uart_sig_fun_e tx_sigfun; - enum glb_uart_sig_fun_e rx_sigfun; + struct gpio_cfg_s cfg; + int tx_sigfun; + int rx_sigfun; cfg.drive = 1; cfg.smt_ctrl = 1; @@ -155,12 +159,12 @@ static void uart_gpio_init(uint8_t id, cfg.gpio_pin = rx_pin; cfg.gpio_mode = GPIO_MODE_AF; cfg.pull_type = GPIO_PULL_UP; - gpio_init(&cfg); + bl602_gpio_init(&cfg); cfg.gpio_pin = tx_pin; cfg.gpio_mode = GPIO_MODE_AF; cfg.pull_type = GPIO_PULL_UP; - gpio_init(&cfg); + bl602_gpio_init(&cfg); /* select uart gpio function */ @@ -175,61 +179,86 @@ static void uart_gpio_init(uint8_t id, rx_sigfun = GLB_UART_SIG_FUN_UART1_RXD; } - glb_uart_fun_sel(tx_pin % 8, tx_sigfun); - glb_uart_fun_sel(rx_pin % 8, rx_sigfun); + bl602_glb_uart_fun_sel(tx_pin % 8, tx_sigfun); + bl602_glb_uart_fun_sel(rx_pin % 8, rx_sigfun); } -static void bl602_enable_uart_clk(uint8_t enable, - enum hbn_uart_clk_type_e clk_sel, - uint8_t div) +static void bl602_enable_uart_clk(uint8_t enable, int clk_sel, uint8_t div) { uint32_t tmp_val; /* disable UART clock first */ - tmp_val = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2); - tmp_val = BL_CLR_REG_BIT(tmp_val, GLB_UART_CLK_EN); - BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmp_val); + bl602_up_serialmodify(GLB_BASE, GLB_CLK_CFG2_OFFSET, (1 << 4), 0); /* Set div */ - tmp_val = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2); - tmp_val = BL_SET_REG_BITS_VAL(tmp_val, GLB_UART_CLK_DIV, div); - BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmp_val); + bl602_up_serialmodify(GLB_BASE, GLB_CLK_CFG2_OFFSET, 0x7, div); /* Select clock source for uart */ - hbn_set_uart_clk_sel(clk_sel); + bl602_hbn_set_uart_clk_sel(clk_sel); /* Set enable or disable */ - tmp_val = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2); + tmp_val = bl602_up_serialin(GLB_BASE, GLB_CLK_CFG2_OFFSET); if (enable) { - tmp_val = BL_SET_REG_BIT(tmp_val, GLB_UART_CLK_EN); + tmp_val |= (1 << 4); } else { - tmp_val = BL_CLR_REG_BIT(tmp_val, GLB_UART_CLK_EN); + tmp_val &= ~(1 << 4); } - BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmp_val); + bl602_up_serialout(GLB_BASE, GLB_CLK_CFG2_OFFSET, tmp_val); } /**************************************************************************** * Public Functions ****************************************************************************/ +uint32_t bl602_up_serialin(uint32_t reg_base, int offset) +{ + return getreg32(reg_base + offset); +} + +void bl602_up_serialout(uint32_t reg_base, int offset, uint32_t value) +{ + putreg32(value, reg_base + offset); +} + +void bl602_up_serialmodify(uint32_t reg_base, + int offset, + uint32_t clearbits, + uint32_t setbits) +{ + modifyreg32(reg_base + offset, clearbits, setbits); +} + +/**************************************************************************** + * Name: bl602_data_setbits + ****************************************************************************/ + +static uint32_t bl602_data_setbits(uint32_t data, + uint32_t start, + uint32_t len, + uint32_t value) +{ + return (((data) & ~((~((~0) << (len))) << (start))) | + (((value) & ((~((~0) << (len))))) << (start))); +} + void bl602_uart_configure(uint32_t uartbase, const struct uart_config_s *config) { - uint32_t tmp_val; - uint32_t div = 0; - uint32_t fraction = 0; - uint32_t tmp_tx_cfg = 0; - uint32_t tmp_rx_cfg = 0; - enum uart_databits_e data_bits; - enum uart_stopbits_e stop_bits; + uint32_t tmp_val; + uint32_t div = 0; + uint32_t fraction = 0; + uint32_t tmp_tx_cfg = 0; + uint32_t tmp_rx_cfg = 0; + int data_bits; + int stop_bits; bl602_enable_uart_clk(1, HBN_UART_CLK_160M, 3); @@ -241,18 +270,12 @@ void bl602_uart_configure(uint32_t uartbase, /* Disable all interrupt */ - tmp_val = BL_RD_REG(uartbase, UART_INT_MASK); - tmp_val |= 0xff; - BL_WR_REG(uartbase, UART_INT_MASK, tmp_val); + bl602_up_serialmodify(uartbase, UART_INT_MASK_OFFSET, 0, 0xff); /* Disable uart before config */ - tmp_val = BL_RD_REG(uartbase, UART_UTX_CONFIG); - BL_WR_REG( - uartbase, UART_UTX_CONFIG, BL_CLR_REG_BIT(tmp_val, UART_CR_UTX_EN)); - tmp_val = BL_RD_REG(uartbase, UART_URX_CONFIG); - BL_WR_REG( - uartbase, UART_URX_CONFIG, BL_CLR_REG_BIT(tmp_val, UART_CR_URX_EN)); + bl602_up_serialmodify(uartbase, UART_UTX_CONFIG_OFFSET, 1, 0); + bl602_up_serialmodify(uartbase, UART_URX_CONFIG_OFFSET, 1, 0); /* cal the baud rate divisor */ @@ -265,31 +288,32 @@ void bl602_uart_configure(uint32_t uartbase, /* set the baud rate register value */ - BL_WR_REG( - uartbase, UART_BIT_PRD, ((div - 1) << 0x10) | ((div - 1) & 0xffff)); + bl602_up_serialout(uartbase, + UART_BIT_PRD_OFFSET, + ((div - 1) << 0x10) | ((div - 1) & 0xffff)); /* configure parity type */ - tmp_tx_cfg = BL_RD_REG(uartbase, UART_UTX_CONFIG); - tmp_rx_cfg = BL_RD_REG(uartbase, UART_URX_CONFIG); + tmp_tx_cfg = bl602_up_serialin(uartbase, UART_UTX_CONFIG_OFFSET); + tmp_rx_cfg = bl602_up_serialin(uartbase, UART_URX_CONFIG_OFFSET); switch (config->parity) { case UART_PARITY_NONE: - tmp_tx_cfg = BL_CLR_REG_BIT(tmp_tx_cfg, UART_CR_UTX_PRT_EN); - tmp_rx_cfg = BL_CLR_REG_BIT(tmp_rx_cfg, UART_CR_URX_PRT_EN); + tmp_tx_cfg &= ~(1 << 4); + tmp_rx_cfg &= ~(1 << 4); break; case UART_PARITY_ODD: - tmp_tx_cfg = BL_SET_REG_BIT(tmp_tx_cfg, UART_CR_UTX_PRT_EN); - tmp_tx_cfg = BL_SET_REG_BIT(tmp_tx_cfg, UART_CR_UTX_PRT_SEL); - tmp_rx_cfg = BL_SET_REG_BIT(tmp_rx_cfg, UART_CR_URX_PRT_EN); - tmp_rx_cfg = BL_SET_REG_BIT(tmp_rx_cfg, UART_CR_URX_PRT_SEL); + tmp_tx_cfg |= 1 << 4; + tmp_tx_cfg |= 1 << 5; + tmp_rx_cfg |= 1 << 4; + tmp_rx_cfg |= 1 << 5; break; case UART_PARITY_EVEN: - tmp_tx_cfg = BL_SET_REG_BIT(tmp_tx_cfg, UART_CR_UTX_PRT_EN); - tmp_tx_cfg = BL_CLR_REG_BIT(tmp_tx_cfg, UART_CR_UTX_PRT_SEL); - tmp_rx_cfg = BL_SET_REG_BIT(tmp_rx_cfg, UART_CR_URX_PRT_EN); - tmp_rx_cfg = BL_CLR_REG_BIT(tmp_rx_cfg, UART_CR_URX_PRT_SEL); + tmp_tx_cfg |= 1 << 4; + tmp_tx_cfg &= ~(1 << 5); + tmp_rx_cfg |= 1 << 4; + tmp_rx_cfg &= ~(1 << 5); break; default: break; @@ -323,78 +347,61 @@ void bl602_uart_configure(uint32_t uartbase, /* Configure data bits */ - tmp_tx_cfg = - BL_SET_REG_BITS_VAL(tmp_tx_cfg, UART_CR_UTX_BIT_CNT_D, (data_bits + 4)); - tmp_rx_cfg = - BL_SET_REG_BITS_VAL(tmp_rx_cfg, UART_CR_URX_BIT_CNT_D, (data_bits + 4)); + tmp_tx_cfg = bl602_data_setbits(tmp_tx_cfg, 8, 3, (data_bits + 4)); + tmp_rx_cfg = bl602_data_setbits(tmp_tx_cfg, 8, 3, (data_bits + 4)); /* Configure tx stop bits */ - tmp_tx_cfg = - BL_SET_REG_BITS_VAL(tmp_tx_cfg, UART_CR_UTX_BIT_CNT_P, (stop_bits + 1)); + tmp_tx_cfg = bl602_data_setbits(tmp_tx_cfg, 12, 2, (stop_bits + 1)); /* Configure tx cts flow control function */ if (config->oflow_ctl) { - tmp_tx_cfg = BL_SET_REG_BIT(tmp_tx_cfg, UART_CR_UTX_CTS_EN); + tmp_tx_cfg |= 1 << 1; } else { - tmp_tx_cfg = BL_CLR_REG_BIT(tmp_tx_cfg, UART_CR_UTX_CTS_EN); + tmp_tx_cfg &= ~(1 << 1); } /* Disable rx input de-glitch function */ - tmp_rx_cfg = BL_CLR_REG_BIT(tmp_rx_cfg, UART_CR_URX_DEG_EN); + tmp_rx_cfg &= ~(1 << 11); if (config->iflow_ctl) { - tmp_tx_cfg = BL_SET_REG_BIT(tmp_tx_cfg, UART_CR_URX_RTS_SW_MODE); + tmp_rx_cfg |= 1 << 1; } else { - tmp_rx_cfg = BL_CLR_REG_BIT(tmp_rx_cfg, UART_CR_URX_RTS_SW_MODE); + tmp_rx_cfg &= ~(1 << 1); } /* Write back */ - BL_WR_REG(uartbase, UART_UTX_CONFIG, tmp_tx_cfg); - BL_WR_REG(uartbase, UART_URX_CONFIG, tmp_rx_cfg); + bl602_up_serialout(uartbase, UART_UTX_CONFIG_OFFSET, tmp_tx_cfg); + bl602_up_serialout(uartbase, UART_URX_CONFIG_OFFSET, tmp_rx_cfg); /* Configure LSB-first */ - tmp_tx_cfg = BL_RD_REG(uartbase, UART_DATA_CONFIG); - tmp_tx_cfg = BL_CLR_REG_BIT(tmp_tx_cfg, UART_CR_UART_BIT_INV); - BL_WR_REG(uartbase, UART_DATA_CONFIG, tmp_tx_cfg); + bl602_up_serialmodify(uartbase, UART_DATA_CONFIG_OFFSET, 1, 0); /* Enable tx free run mode */ - tmp_val = BL_RD_REG(uartbase, UART_UTX_CONFIG); - BL_WR_REG( - uartbase, UART_UTX_CONFIG, BL_SET_REG_BIT(tmp_val, UART_CR_UTX_FRM_EN)); + bl602_up_serialmodify(uartbase, UART_UTX_CONFIG_OFFSET, 0, 1 << 2); /* Deal with uart fifo configure register */ - tmp_val = BL_RD_REG(uartbase, UART_FIFO_CONFIG_1); - - /* Configure dma tx fifo threshold */ - - tmp_val = BL_SET_REG_BITS_VAL(tmp_val, UART_TX_FIFO_TH, 0x10 - 1); - - /* Configure dma rx fifo threshold */ - - tmp_val = BL_SET_REG_BITS_VAL(tmp_val, UART_RX_FIFO_TH, 0x10 - 1); - BL_WR_REG(uartbase, UART_FIFO_CONFIG_1, tmp_val); + tmp_val = bl602_up_serialin(uartbase, UART_FIFO_CONFIG_1_OFFSET); + tmp_val = bl602_data_setbits(tmp_val, UART_TX_FIFO_TH_POS, 5, 0x10 - 1); + tmp_val = bl602_data_setbits(tmp_val, UART_RX_FIFO_TH_POS, 5, 0x10 - 1); + bl602_up_serialout(uartbase, UART_FIFO_CONFIG_1_OFFSET, tmp_val); /* Enable UART tx rx unit */ - tmp_val = BL_RD_REG(uartbase, UART_UTX_CONFIG); - BL_WR_REG( - uartbase, UART_UTX_CONFIG, BL_SET_REG_BIT(tmp_val, UART_CR_UTX_EN)); - tmp_val = BL_RD_REG(uartbase, UART_URX_CONFIG); - BL_WR_REG( - uartbase, UART_URX_CONFIG, BL_SET_REG_BIT(tmp_val, UART_CR_URX_EN)); + bl602_up_serialmodify(uartbase, UART_UTX_CONFIG_OFFSET, 0, 1); + bl602_up_serialmodify(uartbase, UART_URX_CONFIG_OFFSET, 0, 1); } /**************************************************************************** @@ -411,11 +418,12 @@ void up_lowputc(char ch) /* Wait for FIFO */ while ( - BL_GET_REG_BITS_VAL(BL_RD_REG(BL602_CONSOLE_BASE, UART_FIFO_CONFIG_1), - UART_TX_FIFO_CNT) == 0) + ((bl602_up_serialin(BL602_CONSOLE_BASE, UART_FIFO_CONFIG_1_OFFSET)) >> + (UART_TX_FIFO_CNT_POS)) & + (~((~0) << (6)))) ; - BL_WR_BYTE(BL602_CONSOLE_BASE + UART_FIFO_WDATA_OFFSET, ch); + bl602_up_serialout(BL602_CONSOLE_BASE, UART_FIFO_WDATA_OFFSET, ch); #endif /* HAVE_CONSOLE */ } @@ -428,4 +436,3 @@ void bl602_lowsetup(void) #endif /* HAVE_SERIAL_CONSOLE */ } - diff --git a/arch/risc-v/src/bl602/bl602_lowputc.h b/arch/risc-v/src/bl602/bl602_lowputc.h index 07e728bd704..22d19acb7ea 100644 --- a/arch/risc-v/src/bl602/bl602_lowputc.h +++ b/arch/risc-v/src/bl602/bl602_lowputc.h @@ -1,6 +1,9 @@ /** * incubator-nuttx/arch/risc-v/src/bl602/bl602_lowputc.h * + * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at @@ -31,15 +34,6 @@ #ifndef __ASSEMBLY__ -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - struct uart_config_s { uint8_t idx; /* Uart idx */ @@ -55,13 +49,28 @@ struct uart_config_s uint8_t rts_pin; /* RTS pin */ }; -/**************************************************************************** - * Name: bl602_lowsetup - ****************************************************************************/ +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +EXTERN uint32_t bl602_up_serialin(uint32_t reg_base, int offset); + +EXTERN void bl602_up_serialout(uint32_t reg_base, int offset, + uint32_t value); + +EXTERN void bl602_up_serialmodify(uint32_t reg_base, + int offset, + uint32_t clearbits, + uint32_t setbits); EXTERN void bl602_lowsetup(void); -EXTERN void bl602_uart_configure(uint32_t base_addr, +EXTERN void bl602_uart_configure(uint32_t base_addr, const struct uart_config_s *config); #undef EXTERN diff --git a/arch/risc-v/src/bl602/bl602_oneshot_lowerhalf.c b/arch/risc-v/src/bl602/bl602_oneshot_lowerhalf.c index 535f59d8c42..d652a0666cb 100644 --- a/arch/risc-v/src/bl602/bl602_oneshot_lowerhalf.c +++ b/arch/risc-v/src/bl602/bl602_oneshot_lowerhalf.c @@ -1,8 +1,8 @@ /**************************************************************************** - * arch/arm/src/bl602/bl602_oneshot_lowerhalf.c + * arch/arm/src/bl602/bl602_oneshot_lowerhalf.c * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -48,9 +48,17 @@ #include #include +#include "riscv_arch.h" +#include "riscv_internal.h" + #include #include "bl602_oneshot_lowerhalf.h" +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Private definetions */ #define TIMER_MAX_VALUE (0xFFFFFFFF) #define TIMER_CLK_DIV (160) #define TIMER_CLK_FREQ (160000000UL / (TIMER_CLK_DIV)) @@ -142,15 +150,15 @@ static int bl602_oneshot_handler(int irq, FAR void *context, FAR void *arg) uint32_t tmp_val; uint32_t tmp_addr; - int_id = BL_RD_WORD(TIMER_BASE + TIMER_TMSR2_OFFSET + 4 * priv->tim); + int_id = getreg32(TIMER_BASE + TIMER_TMSR2_OFFSET + 4 * priv->tim); tmp_addr = TIMER_BASE + TIMER_TICR2_OFFSET + 4 * priv->tim; - tmp_val = BL_RD_WORD(tmp_addr); + tmp_val = getreg32(tmp_addr); /* Comparator 0 match interrupt */ - if (BL_IS_REG_BIT_SET(int_id, TIMER_TMSR_0)) + if (((int_id) & (1 << (TIMER_TMSR_0_POS))) != 0) { - BL_WR_WORD(tmp_addr, BL_SET_REG_BIT(tmp_val, TIMER_TCLR_0)); + putreg32(tmp_val | (1 << TIMER_TCLR_0_POS), tmp_addr); callback = priv->callback; cbarg = priv->arg; @@ -162,16 +170,16 @@ static int bl602_oneshot_handler(int irq, FAR void *context, FAR void *arg) /* Comparator 1 match interrupt */ - if (BL_IS_REG_BIT_SET(int_id, TIMER_TMSR_1)) + if (((int_id) & (1 << (TIMER_TMSR_1_POS))) != 0) { - BL_WR_WORD(tmp_addr, BL_SET_REG_BIT(tmp_val, TIMER_TCLR_1)); + putreg32(tmp_val | (1 << TIMER_TCLR_1_POS), tmp_addr); } /* Comparator 2 match interrupt */ - if (BL_IS_REG_BIT_SET(int_id, TIMER_TMSR_2)) + if (((int_id) & (1 << (TIMER_TMSR_2_POS))) != 0) { - BL_WR_WORD(tmp_addr, BL_SET_REG_BIT(tmp_val, TIMER_TCLR_2)); + putreg32(tmp_val | (1 << TIMER_TCLR_2_POS), tmp_addr); } return 0; @@ -265,14 +273,14 @@ static int bl602_start(FAR struct oneshot_lowerhalf_s *lower, usec = (uint64_t)ts->tv_sec * USEC_PER_SEC + (uint64_t)(ts->tv_nsec / NSEC_PER_USEC); - timer_setcompvalue( + bl602_timer_setcompvalue( priv->tim, TIMER_COMP_ID_0, usec / (TIMER_CLK_FREQ / priv->freq)); - timer_setpreloadvalue(priv->tim, 0); + bl602_timer_setpreloadvalue(priv->tim, 0); irq_attach(priv->irq, bl602_oneshot_handler, (void *)priv); up_enable_irq(priv->irq); - timer_intmask(priv->tim, TIMER_INT_COMP_0, 0); - timer_enable(priv->tim); + bl602_timer_intmask(priv->tim, TIMER_INT_COMP_0, 0); + bl602_timer_enable(priv->tim); priv->started = true; leave_critical_section(flags); @@ -319,10 +327,10 @@ static int bl602_cancel(FAR struct oneshot_lowerhalf_s *lower, { flags = enter_critical_section(); - timer_disable(priv->tim); + bl602_timer_disable(priv->tim); priv->started = false; up_disable_irq(priv->irq); - timer_intmask(priv->tim, TIMER_INT_COMP_0, 1); + bl602_timer_intmask(priv->tim, TIMER_INT_COMP_0, 1); priv->callback = NULL; priv->arg = NULL; @@ -399,22 +407,21 @@ FAR struct oneshot_lowerhalf_s *oneshot_initialize(int chan, timstr.count_mode = TIMER_COUNT_PRELOAD; /* Timer count mode */ timstr.clock_division = - (TIMER_CLK_DIV * resolution) - 1; /* Timer clock divison value */ + (TIMER_CLK_DIV * resolution) - 1; /* Timer clock divison value */ - timstr.match_val0 = TIMER_MAX_VALUE; /* Timer match 0 value 0 */ - timstr.match_val1 = TIMER_MAX_VALUE; /* Timer match 1 value 0 */ - timstr.match_val2 = TIMER_MAX_VALUE; /* Timer match 2 value 0 */ + timstr.match_val0 = TIMER_MAX_VALUE; /* Timer match 0 value 0 */ + timstr.match_val1 = TIMER_MAX_VALUE; /* Timer match 1 value 0 */ + timstr.match_val2 = TIMER_MAX_VALUE; /* Timer match 2 value 0 */ timstr.pre_load_val = TIMER_MAX_VALUE; /* Timer preload value */ - timer_intmask(chan, TIMER_INT_ALL, 1); + bl602_timer_intmask(chan, TIMER_INT_ALL, 1); /* timer disable */ - timer_disable(chan); + bl602_timer_disable(chan); - timer_init(&timstr); + bl602_timer_init(&timstr); return &priv->lh; } - diff --git a/arch/risc-v/src/bl602/bl602_oneshot_lowerhalf.h b/arch/risc-v/src/bl602/bl602_oneshot_lowerhalf.h index 3388d59bd46..73a6205252f 100644 --- a/arch/risc-v/src/bl602/bl602_oneshot_lowerhalf.h +++ b/arch/risc-v/src/bl602/bl602_oneshot_lowerhalf.h @@ -1,8 +1,8 @@ /**************************************************************************** * arch/risc-v/src/bl602/bl602_oneshot.h * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -71,6 +71,7 @@ * Public Types ****************************************************************************/ +#ifndef __ASSEMBLY__ /* This describes the callback function that will be invoked when the oneshot * timer expires. The oneshot fires, the client will receive: * @@ -208,5 +209,6 @@ int bl602_oneshot_cancel(struct bl602_oneshot_s *oneshot, } #endif +#endif /* __ASSEMBLY__ */ #endif /* CONFIG_BL602_ONESHOT */ #endif /* __ARCH_ARM_SRC_BL602_ONESHOT_H */ diff --git a/arch/risc-v/src/bl602/bl602_serial.c b/arch/risc-v/src/bl602/bl602_serial.c index 2c2e8fdcac7..f5b8e838ef6 100644 --- a/arch/risc-v/src/bl602/bl602_serial.c +++ b/arch/risc-v/src/bl602/bl602_serial.c @@ -1,6 +1,9 @@ /**************************************************************************** * arch/risc-v/src/bl602/bl602_serial.c * + * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with * this work for additional information regarding copyright ownership. The @@ -312,15 +315,15 @@ static int __uart_interrupt(int irq, FAR void *context, FAR void *arg) uint32_t tmp_val = 0; uint32_t mask_val = 0; - tmp_val = BL_RD_REG(uart_priv->uartbase, UART_INT_STS); - mask_val = BL_RD_REG(uart_priv->uartbase, UART_INT_MASK); + tmp_val = bl602_up_serialin(uart_priv->uartbase, UART_INT_STS_OFFSET); + mask_val = bl602_up_serialin(uart_priv->uartbase, UART_INT_MASK_OFFSET); /* Length of uart rx data transfer arrived interrupt */ - if (BL_IS_REG_BIT_SET(tmp_val, UART_URX_END_INT) && - !BL_IS_REG_BIT_SET(mask_val, UART_CR_URX_END_MASK)) + if ((tmp_val & (1 << UART_URX_END_INT_POS)) && + !(mask_val & (1 << UART_CR_URX_END_MASK_POS))) { - BL_WR_REG(uart_priv->uartbase, UART_INT_CLEAR, 0x2); + bl602_up_serialout(uart_priv->uartbase, UART_INT_CLEAR_OFFSET, 0x2); /* Receive Data ready */ @@ -329,8 +332,8 @@ static int __uart_interrupt(int irq, FAR void *context, FAR void *arg) /* Tx fifo ready interrupt,auto-cleared when data is pushed */ - if (BL_IS_REG_BIT_SET(tmp_val, UART_UTX_FIFO_INT) && - !BL_IS_REG_BIT_SET(mask_val, UART_CR_UTX_FIFO_MASK)) + if ((tmp_val & (1 << UART_UTX_FIFO_INT_POS)) && + !(mask_val & (1 << UART_CR_UTX_FIFO_MASK_POS))) { /* Transmit data request interrupt */ @@ -339,8 +342,8 @@ static int __uart_interrupt(int irq, FAR void *context, FAR void *arg) /* Rx fifo ready interrupt,auto-cleared when data is popped */ - if (BL_IS_REG_BIT_SET(tmp_val, UART_URX_FIFO_INT) && - !BL_IS_REG_BIT_SET(mask_val, UART_CR_URX_FIFO_MASK)) + if ((tmp_val & (1 << UART_URX_FIFO_INT_POS)) && + !(mask_val & (1 << UART_CR_URX_FIFO_MASK_POS))) { /* Receive Data ready */ @@ -378,20 +381,12 @@ static int up_setup(struct uart_dev_s *dev) static void up_shutdown(struct uart_dev_s *dev) { - uint32_t tmp_val; struct up_dev_s *uart_priv = (struct up_dev_s *)dev->priv; /* Disable uart before config */ - tmp_val = BL_RD_REG(uart_priv->uartbase, UART_UTX_CONFIG); - BL_WR_REG(uart_priv->uartbase, - UART_UTX_CONFIG, - BL_CLR_REG_BIT(tmp_val, UART_CR_UTX_EN)); - - tmp_val = BL_RD_REG(uart_priv->uartbase, UART_URX_CONFIG); - BL_WR_REG(uart_priv->uartbase, - UART_URX_CONFIG, - BL_CLR_REG_BIT(tmp_val, UART_CR_URX_EN)); + bl602_up_serialmodify(uart_priv->uartbase, UART_UTX_CONFIG_OFFSET, 1, 0); + bl602_up_serialmodify(uart_priv->uartbase, UART_URX_CONFIG_OFFSET, 1, 0); } /**************************************************************************** @@ -446,6 +441,16 @@ static void up_detach(struct uart_dev_s *dev) irq_detach(priv->irq); } +/**************************************************************************** + * Name: bl602_data_getbits + ****************************************************************************/ + +static uint32_t +bl602_data_getbits(uint32_t data, uint32_t start, uint32_t len) +{ + return (((data) >> (start)) & (~((~0) << (len)))); +} + /**************************************************************************** * Name: up_ioctl * @@ -613,9 +618,11 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) * implement TCSADRAIN / TCSAFLUSH */ - tmp_val = BL_RD_REG(priv->uartbase, UART_INT_MASK); + tmp_val = + bl602_up_serialin(priv->uartbase, UART_INT_MASK_OFFSET); bl602_uart_configure(priv->uartbase, &config); - BL_WR_REG(priv->uartbase, UART_INT_MASK, tmp_val); + bl602_up_serialout( + priv->uartbase, UART_INT_MASK_OFFSET, tmp_val); } } while (0); @@ -654,10 +661,12 @@ static int up_receive(struct uart_dev_s *dev, unsigned int *status) /* if uart fifo cnts > 0 */ - if (BL_GET_REG_BITS_VAL(BL_RD_REG(priv->uartbase, UART_FIFO_CONFIG_1), - UART_RX_FIFO_CNT) > 0) + if (bl602_data_getbits( + bl602_up_serialin(priv->uartbase, UART_FIFO_CONFIG_1_OFFSET), + UART_RX_FIFO_CNT_POS, + 6) > 0) { - rxdata = BL_RD_BYTE(priv->uartbase + UART_FIFO_RDATA_OFFSET); + rxdata = bl602_up_serialin(priv->uartbase, UART_FIFO_RDATA_OFFSET); } else { @@ -683,18 +692,18 @@ static void up_rxint(struct uart_dev_s *dev, bool enable) if (enable) { #ifndef CONFIG_SUPPRESS_SERIAL_INTS - tmp_val = BL_RD_REG(priv->uartbase, UART_INT_MASK); + tmp_val = bl602_up_serialin(priv->uartbase, UART_INT_MASK_OFFSET); tmp_val &= ~(1 << UART_INT_RX_FIFO_REQ); tmp_val &= ~(1 << UART_INT_RX_END); - BL_WR_REG(priv->uartbase, UART_INT_MASK, tmp_val); + bl602_up_serialout(priv->uartbase, UART_INT_MASK_OFFSET, tmp_val); #endif } else { - tmp_val = BL_RD_REG(priv->uartbase, UART_INT_MASK); + tmp_val = bl602_up_serialin(priv->uartbase, UART_INT_MASK_OFFSET); tmp_val |= (1 << UART_INT_RX_FIFO_REQ); tmp_val |= (1 << UART_INT_RX_END); - BL_WR_REG(priv->uartbase, UART_INT_MASK, tmp_val); + bl602_up_serialout(priv->uartbase, UART_INT_MASK_OFFSET, tmp_val); } leave_critical_section(flags); @@ -714,8 +723,10 @@ static bool up_rxavailable(struct uart_dev_s *dev) /* Return true is data is available in the receive data buffer */ - uint32_t rxcnt = BL_GET_REG_BITS_VAL( - BL_RD_REG(priv->uartbase, UART_FIFO_CONFIG_1), UART_RX_FIFO_CNT); + uint32_t rxcnt = bl602_data_getbits( + bl602_up_serialin(priv->uartbase, UART_FIFO_CONFIG_1_OFFSET), + UART_RX_FIFO_CNT_POS, + 6); return rxcnt != 0; } @@ -734,11 +745,13 @@ static void up_send(struct uart_dev_s *dev, int ch) /* Wait for FIFO */ - while (BL_GET_REG_BITS_VAL(BL_RD_REG(priv->uartbase, UART_FIFO_CONFIG_1), - UART_TX_FIFO_CNT) == 0) + while (bl602_data_getbits( + bl602_up_serialin(priv->uartbase, UART_FIFO_CONFIG_1_OFFSET), + UART_TX_FIFO_CNT_POS, + 6) == 0) ; - BL_WR_BYTE(priv->uartbase + UART_FIFO_WDATA_OFFSET, ch); + bl602_up_serialout(priv->uartbase, UART_FIFO_WDATA_OFFSET, ch); } /**************************************************************************** @@ -762,9 +775,9 @@ static void up_txint(struct uart_dev_s *dev, bool enable) #ifndef CONFIG_SUPPRESS_SERIAL_INTS /* Enable the TX interrupt */ - tmp_val = BL_RD_REG(priv->uartbase, UART_INT_MASK); + tmp_val = bl602_up_serialin(priv->uartbase, UART_INT_MASK_OFFSET); tmp_val &= ~(1 << UART_INT_TX_FIFO_REQ); - BL_WR_REG(priv->uartbase, UART_INT_MASK, tmp_val); + bl602_up_serialout(priv->uartbase, UART_INT_MASK_OFFSET, tmp_val); /* Fake a TX interrupt here by just calling uart_xmitchars() with * interrupts disabled (note this may recurse). @@ -777,9 +790,9 @@ static void up_txint(struct uart_dev_s *dev, bool enable) { /* Disable the TX interrupt */ - tmp_val = BL_RD_REG(priv->uartbase, UART_INT_MASK); + tmp_val = bl602_up_serialin(priv->uartbase, UART_INT_MASK_OFFSET); tmp_val |= (1 << UART_INT_TX_FIFO_REQ); - BL_WR_REG(priv->uartbase, UART_INT_MASK, tmp_val); + bl602_up_serialout(priv->uartbase, UART_INT_MASK_OFFSET, tmp_val); } leave_critical_section(flags); @@ -799,8 +812,9 @@ static bool up_txready(struct uart_dev_s *dev) /* Return TRUE if the TX FIFO is not full */ - uint32_t txcnt = BL_GET_REG_BITS_VAL( - BL_RD_REG(priv->uartbase, UART_FIFO_CONFIG_1), UART_TX_FIFO_CNT); + uint32_t txcnt = + bl602_up_serialin(priv->uartbase, UART_FIFO_CONFIG_1_OFFSET); + txcnt = (txcnt & UART_TX_FIFO_CNT_MSK) >> UART_TX_FIFO_CNT_POS; return (txcnt != 0); } @@ -819,8 +833,10 @@ static bool up_txempty(struct uart_dev_s *dev) /* Return TRUE if the TX is pending */ - uint32_t txcnt = BL_GET_REG_BITS_VAL( - BL_RD_REG(priv->uartbase, UART_FIFO_CONFIG_1), UART_TX_FIFO_CNT); + uint32_t txcnt = bl602_data_getbits( + bl602_up_serialin(priv->uartbase, UART_FIFO_CONFIG_1_OFFSET), + UART_TX_FIFO_CNT_POS, + 6); return (txcnt == 0); } @@ -983,4 +999,3 @@ int up_putc(int ch) } #endif /* USE_SERIALDRIVER */ - diff --git a/arch/risc-v/src/bl602/bl602_start.c b/arch/risc-v/src/bl602/bl602_start.c index 2aad8989b3c..7698bdea0c5 100644 --- a/arch/risc-v/src/bl602/bl602_start.c +++ b/arch/risc-v/src/bl602/bl602_start.c @@ -1,6 +1,9 @@ /**************************************************************************** * arch/risc-v/src/bl602/bl602_init.c * + * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with * this work for additional information regarding copyright ownership. The @@ -29,6 +32,7 @@ #include +#include "riscv_arch.h" #include "riscv_internal.h" #include "chip.h" @@ -45,18 +49,6 @@ #define showprogress(c) #endif -#define PARTITION_BOOT2_RAM_ADDR_ACTIVE (0x42049C00) -#define PARTITION_HEADER_BOOT2_RAM_ADDR (0x42049C04) -#define PARTITION_BOOT2_FLASH_HEADER (0x42049d14) -#define PARTITION_BOOT2_FLASH_CONFIG (0x42049d18) -#define PARTITION_MAGIC (0x54504642) -#define PARTITION_FW_PART_NAME "FW" -#define PARTITION_FW_PART_HEADER_SIZE (0x1000) - -/* TODO use header file from project */ - -#define FW_XIP_ADDRESS (0x23000000) - #define BL602_IDLESTACK_SIZE (CONFIG_IDLETHREAD_STACKSIZE & ~3) /**************************************************************************** @@ -73,7 +65,7 @@ * address. */ -static uint8_t idle_stack[BL602_IDLESTACK_SIZE]; +static uint8_t g_idle_stack[BL602_IDLESTACK_SIZE]; /* Dont change the name of varaible, since we refer this * boot2_partition_table in linker script @@ -90,7 +82,7 @@ static struct * Public Data ****************************************************************************/ -uint32_t g_idle_topstack = (uintptr_t)idle_stack + BL602_IDLESTACK_SIZE; +uint32_t g_idle_topstack = (uintptr_t)g_idle_stack + BL602_IDLESTACK_SIZE; /**************************************************************************** * Public Functions @@ -131,9 +123,10 @@ void bfl_main(void) /* HBN Config AON pad input and SMT */ - tmp_val = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE); - tmp_val = BL_SET_REG_BITS_VAL(tmp_val, HBN_REG_AON_PAD_IE_SMT, 1); - BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmp_val); + tmp_val = getreg32(HBN_BASE + HBN_IRQ_MODE_OFFSET); + tmp_val = (tmp_val & HBN_REG_AON_PAD_IE_SMT_UMSK) | + (1 << HBN_REG_AON_PAD_IE_SMT_POS); + putreg32(tmp_val, HBN_BASE + HBN_IRQ_MODE_OFFSET); #ifdef USE_EARLYSERIALINIT up_earlyserialinit(); @@ -152,4 +145,3 @@ void bfl_main(void) while (1) ; } - diff --git a/arch/risc-v/src/bl602/bl602_tim.c b/arch/risc-v/src/bl602/bl602_tim.c index 53c4812478e..34ccea40a0a 100644 --- a/arch/risc-v/src/bl602/bl602_tim.c +++ b/arch/risc-v/src/bl602/bl602_tim.c @@ -1,6 +1,9 @@ /**************************************************************************** * boards/risc-v/bl602/evb/src/bl602_tim.c * + * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with * this work for additional information regarding copyright ownership. The @@ -23,6 +26,8 @@ ****************************************************************************/ #include +#include "riscv_arch.h" +#include "riscv_internal.h" /**************************************************************************** * Pre-processor Definitions @@ -30,12 +35,53 @@ #define TIMER_MAX_MATCH 3 +/**************************************************************************** + * Static Functions + ****************************************************************************/ + +static inline uint32_t bl602_up_tim_regin(uint32_t reg_addr) +{ + return getreg32(reg_addr); +} + +static inline void bl602_up_tim_regout(uint32_t reg_addr, uint32_t value) +{ + putreg32(value, reg_addr); +} + +/**************************************************************************** + * Name: bl602_data_setbits + ****************************************************************************/ + +static uint32_t bl602_data_setbits(uint32_t data, + uint32_t start, + uint32_t len, + uint32_t value) +{ + return (((data) & ~((~((~0) << (len))) << (start))) | + (((value) & ((~((~0) << (len))))) << (start))); +} + +static void bl602_wdt_access(void) +{ + uint32_t tmp_val = bl602_up_tim_regin(TIMER_BASE + TIMER_WFAR_OFFSET); + + bl602_up_tim_regout( + TIMER_BASE + TIMER_WFAR_OFFSET, + bl602_data_setbits(tmp_val, TIMER_WFAR_POS, 16, 0xbaba)); + + tmp_val = bl602_up_tim_regin(TIMER_BASE + TIMER_WSAR_OFFSET); + bl602_up_tim_regout( + TIMER_BASE + TIMER_WSAR_OFFSET, + bl602_data_setbits(tmp_val, TIMER_WSAR_POS, 16, 0xeb10)); +} + /**************************************************************************** * Public Functions ****************************************************************************/ /**************************************************************************** - * Name: timer_getcompvalue + * Name: bl602_timer_getcompvalue * * Description: * Get the specified channel and match comparator value. @@ -49,17 +95,17 @@ * ****************************************************************************/ -uint32_t timer_getcompvalue(timer_chan_t timer_ch, timer_comp_id_t cmp_no) +uint32_t bl602_timer_getcompvalue(uint32_t timer_ch, uint32_t cmp_no) { uint32_t tmp_val; - tmp_val = BL_RD_WORD(TIMER_BASE + TIMER_TMR2_0_OFFSET + - 4 * (TIMER_MAX_MATCH * timer_ch + cmp_no)); + tmp_val = bl602_up_tim_regin(TIMER_BASE + TIMER_TMR2_0_OFFSET + + 4 * (TIMER_MAX_MATCH * timer_ch + cmp_no)); return tmp_val; } /**************************************************************************** - * Name: timer_setcompvalue + * Name: bl602_timer_setcompvalue * * Description: * TIMER set specified channel and comparator compare value @@ -74,17 +120,17 @@ uint32_t timer_getcompvalue(timer_chan_t timer_ch, timer_comp_id_t cmp_no) * ****************************************************************************/ -void timer_setcompvalue(timer_chan_t timer_ch, - timer_comp_id_t cmp_no, - uint32_t val) +void bl602_timer_setcompvalue(uint32_t timer_ch, + uint32_t cmp_no, + uint32_t val) { - BL_WR_WORD(TIMER_BASE + TIMER_TMR2_0_OFFSET + - 4 * (TIMER_MAX_MATCH * timer_ch + cmp_no), - val); + bl602_up_tim_regout(TIMER_BASE + TIMER_TMR2_0_OFFSET + + 4 * (TIMER_MAX_MATCH * timer_ch + cmp_no), + val); } /**************************************************************************** - * Name: timer_getcountervalue + * Name: bl602_timer_getcountervalue * * Description: * TIMER get the specified channel count value. @@ -97,7 +143,7 @@ void timer_setcompvalue(timer_chan_t timer_ch, * ****************************************************************************/ -uint32_t timer_getcountervalue(timer_chan_t timer_ch) +uint32_t bl602_timer_getcountervalue(uint32_t timer_ch) { uint32_t tmp_val; uint32_t tmp_addr; @@ -107,19 +153,19 @@ uint32_t timer_getcountervalue(timer_chan_t timer_ch) */ tmp_addr = TIMER_BASE + TIMER_TCVWR2_OFFSET + 4 * timer_ch; - BL_WR_WORD(tmp_addr, 1); + bl602_up_tim_regout(tmp_addr, 1); /* Need wait */ - tmp_val = BL_RD_WORD(tmp_addr); - tmp_val = BL_RD_WORD(tmp_addr); - tmp_val = BL_RD_WORD(tmp_addr); + tmp_val = bl602_up_tim_regin(tmp_addr); + tmp_val = bl602_up_tim_regin(tmp_addr); + tmp_val = bl602_up_tim_regin(tmp_addr); return tmp_val; } /**************************************************************************** - * Name: timer_getmatchstatus + * Name: bl602_timer_getmatchstatus * * Description: * TIMER get specified channel and comparator match status @@ -133,22 +179,23 @@ uint32_t timer_getcountervalue(timer_chan_t timer_ch) * ****************************************************************************/ -uint32_t timer_getmatchstatus(timer_chan_t timer_ch, timer_comp_id_t cmp_no) +uint32_t bl602_timer_getmatchstatus(uint32_t timer_ch, uint32_t cmp_no) { uint32_t tmp_val; uint32_t bit_status = 0; - tmp_val = BL_RD_WORD(TIMER_BASE + TIMER_TMSR2_OFFSET + 4 * timer_ch); + tmp_val = + bl602_up_tim_regin(TIMER_BASE + TIMER_TMSR2_OFFSET + 4 * timer_ch); switch (cmp_no) { case TIMER_COMP_ID_0: - bit_status = BL_IS_REG_BIT_SET(tmp_val, TIMER_TMSR_0) ? 1 : 0; + bit_status = (((tmp_val) & (1 << (TIMER_TMSR_0_POS))) ? 1 : 0); break; case TIMER_COMP_ID_1: - bit_status = BL_IS_REG_BIT_SET(tmp_val, TIMER_TMSR_1) ? 1 : 0; + bit_status = (((tmp_val) & (1 << (TIMER_TMSR_1_POS))) ? 1 : 0); break; case TIMER_COMP_ID_2: - bit_status = BL_IS_REG_BIT_SET(tmp_val, TIMER_TMSR_2) ? 1 : 0; + bit_status = (((tmp_val) & (1 << (TIMER_TMSR_2_POS))) ? 1 : 0); break; default: break; @@ -158,7 +205,7 @@ uint32_t timer_getmatchstatus(timer_chan_t timer_ch, timer_comp_id_t cmp_no) } /**************************************************************************** - * Name: timer_getpreloadvalue + * Name: bl602_timer_getpreloadvalue * * Description: * TIMER get specified channel preload value @@ -171,16 +218,17 @@ uint32_t timer_getmatchstatus(timer_chan_t timer_ch, timer_comp_id_t cmp_no) * ****************************************************************************/ -uint32_t timer_getpreloadvalue(timer_chan_t timer_ch) +uint32_t bl602_timer_getpreloadvalue(uint32_t timer_ch) { uint32_t tmp_val; - tmp_val = BL_RD_WORD(TIMER_BASE + TIMER_TPLVR2_OFFSET + 4 * timer_ch); + tmp_val = + bl602_up_tim_regin(TIMER_BASE + TIMER_TPLVR2_OFFSET + 4 * timer_ch); return tmp_val; } /**************************************************************************** - * Name: timer_setpreloadvalue + * Name: bl602_timer_setpreloadvalue * * Description: * TIMER set preload register low 32bits value @@ -194,13 +242,13 @@ uint32_t timer_getpreloadvalue(timer_chan_t timer_ch) * ****************************************************************************/ -void timer_setpreloadvalue(timer_chan_t timer_ch, uint32_t val) +void bl602_timer_setpreloadvalue(uint32_t timer_ch, uint32_t val) { - BL_WR_WORD(TIMER_BASE + TIMER_TPLVR2_OFFSET + 4 * timer_ch, val); + bl602_up_tim_regout(TIMER_BASE + TIMER_TPLVR2_OFFSET + 4 * timer_ch, val); } /**************************************************************************** - * Name: timer_setpreloadtrigsrc + * Name: bl602_timer_setpreloadtrigsrc * * Description: * TIMER set preload trigger source,COMP0,COMP1,COMP2 or None @@ -214,14 +262,14 @@ void timer_setpreloadvalue(timer_chan_t timer_ch, uint32_t val) * ****************************************************************************/ -void timer_setpreloadtrigsrc(timer_chan_t timer_ch, - timer_preload_trig_t pl_src) +void bl602_timer_setpreloadtrigsrc(uint32_t timer_ch, uint32_t pl_src) { - BL_WR_WORD(TIMER_BASE + TIMER_TPLCR2_OFFSET + 4 * timer_ch, pl_src); + bl602_up_tim_regout(TIMER_BASE + TIMER_TPLCR2_OFFSET + 4 * timer_ch, + pl_src); } /**************************************************************************** - * Name: timer_setcountmode + * Name: bl602_timer_setcountmode * * Description: * TIMER set count mode:preload or free run @@ -236,19 +284,19 @@ void timer_setpreloadtrigsrc(timer_chan_t timer_ch, * ****************************************************************************/ -void timer_setcountmode(timer_chan_t timer_ch, timer_countmode_t count_mode) +void bl602_timer_setcountmode(uint32_t timer_ch, uint32_t count_mode) { uint32_t tmpval; - tmpval = BL_RD_WORD(TIMER_BASE + TIMER_TCMR_OFFSET); + tmpval = bl602_up_tim_regin(TIMER_BASE + TIMER_TCMR_OFFSET); tmpval &= (~(1 << (timer_ch + 1))); tmpval |= (count_mode << (timer_ch + 1)); - BL_WR_WORD(TIMER_BASE + TIMER_TCMR_OFFSET, tmpval); + bl602_up_tim_regout(TIMER_BASE + TIMER_TCMR_OFFSET, tmpval); } /**************************************************************************** - * Name: timer_clearintstatus + * Name: bl602_timer_clearintstatus * * Description: * TIMER clear interrupt status @@ -262,21 +310,21 @@ void timer_setcountmode(timer_chan_t timer_ch, timer_countmode_t count_mode) * ****************************************************************************/ -void timer_clearintstatus(timer_chan_t timer_ch, timer_comp_id_t cmp_no) +void bl602_timer_clearintstatus(uint32_t timer_ch, uint32_t cmp_no) { uint32_t tmp_addr; uint32_t tmp_val; tmp_addr = TIMER_BASE + TIMER_TICR2_OFFSET + 4 * timer_ch; - tmp_val = BL_RD_WORD(tmp_addr); + tmp_val = bl602_up_tim_regin(tmp_addr); tmp_val |= (1 << cmp_no); - BL_WR_WORD(tmp_addr, tmp_val); + bl602_up_tim_regout(tmp_addr, tmp_val); } /**************************************************************************** - * Name: timer_init + * Name: bl602_timer_init * * Description: * TIMER initialization function. @@ -289,65 +337,67 @@ void timer_clearintstatus(timer_chan_t timer_ch, timer_comp_id_t cmp_no) * ****************************************************************************/ -void timer_init(timer_cfg_t *timer_cfg) +void bl602_timer_init(timer_cfg_t *timer_cfg) { - timer_chan_t timer_ch = timer_cfg->timer_ch; - uint32_t tmp_val; + uint32_t timer_ch = timer_cfg->timer_ch; + uint32_t tmp_val; /* Configure timer clock source */ - tmp_val = BL_RD_REG(TIMER_BASE, TIMER_TCCR); + tmp_val = bl602_up_tim_regin(TIMER_BASE + TIMER_TCCR_OFFSET); if (timer_ch == TIMER_CH0) { - tmp_val = BL_SET_REG_BITS_VAL(tmp_val, TIMER_CS_1, timer_cfg->clk_src); + tmp_val = + bl602_data_setbits(tmp_val, TIMER_CS_1_POS, 2, timer_cfg->clk_src); } else { - tmp_val = BL_SET_REG_BITS_VAL(tmp_val, TIMER_CS_2, timer_cfg->clk_src); + tmp_val = + bl602_data_setbits(tmp_val, TIMER_CS_2_POS, 2, timer_cfg->clk_src); } - BL_WR_REG(TIMER_BASE, TIMER_TCCR, tmp_val); + bl602_up_tim_regout(TIMER_BASE + TIMER_TCCR_OFFSET, tmp_val); /* Configure timer clock division */ - tmp_val = BL_RD_REG(TIMER_BASE, TIMER_TCDR); + tmp_val = bl602_up_tim_regin(TIMER_BASE + TIMER_TCDR_OFFSET); if (timer_ch == TIMER_CH0) { - tmp_val = - BL_SET_REG_BITS_VAL(tmp_val, TIMER_TCDR2, timer_cfg->clock_division); + tmp_val = bl602_data_setbits( + tmp_val, TIMER_TCDR2_POS, 8, timer_cfg->clock_division); } else { - tmp_val = - BL_SET_REG_BITS_VAL(tmp_val, TIMER_TCDR3, timer_cfg->clock_division); + tmp_val = bl602_data_setbits( + tmp_val, TIMER_TCDR3_POS, 8, timer_cfg->clock_division); } - BL_WR_REG(TIMER_BASE, TIMER_TCDR, tmp_val); + bl602_up_tim_regout(TIMER_BASE + TIMER_TCDR_OFFSET, tmp_val); /* Configure timer count mode: preload or free run */ - timer_setcountmode(timer_ch, timer_cfg->count_mode); + bl602_timer_setcountmode(timer_ch, timer_cfg->count_mode); /* Configure timer preload trigger src */ - timer_setpreloadtrigsrc(timer_ch, timer_cfg->pl_trig_src); + bl602_timer_setpreloadtrigsrc(timer_ch, timer_cfg->pl_trig_src); if (timer_cfg->count_mode == TIMER_COUNT_PRELOAD) { /* Configure timer preload value */ - timer_setpreloadvalue(timer_ch, timer_cfg->pre_load_val); + bl602_timer_setpreloadvalue(timer_ch, timer_cfg->pre_load_val); } /* Configure match compare values */ - timer_setcompvalue(timer_ch, TIMER_COMP_ID_0, timer_cfg->match_val0); - timer_setcompvalue(timer_ch, TIMER_COMP_ID_1, timer_cfg->match_val1); - timer_setcompvalue(timer_ch, TIMER_COMP_ID_2, timer_cfg->match_val2); + bl602_timer_setcompvalue(timer_ch, TIMER_COMP_ID_0, timer_cfg->match_val0); + bl602_timer_setcompvalue(timer_ch, TIMER_COMP_ID_1, timer_cfg->match_val1); + bl602_timer_setcompvalue(timer_ch, TIMER_COMP_ID_2, timer_cfg->match_val2); } /**************************************************************************** - * Name: timer_enable + * Name: bl602_timer_enable * * Description: * TIMER enable one channel function. @@ -360,18 +410,18 @@ void timer_init(timer_cfg_t *timer_cfg) * ****************************************************************************/ -void timer_enable(timer_chan_t timer_ch) +void bl602_timer_enable(uint32_t timer_ch) { uint32_t tmp_val; - tmp_val = BL_RD_REG(TIMER_BASE, TIMER_TCER); + tmp_val = bl602_up_tim_regin(TIMER_BASE + TIMER_TCER_OFFSET); tmp_val |= (1 << (timer_ch + 1)); - BL_WR_REG(TIMER_BASE, TIMER_TCER, tmp_val); + bl602_up_tim_regout(TIMER_BASE + TIMER_TCER_OFFSET, tmp_val); } /**************************************************************************** - * Name: timer_disable + * Name: bl602_timer_disable * * Description: * TIMER disable one channel function. @@ -384,18 +434,18 @@ void timer_enable(timer_chan_t timer_ch) * ****************************************************************************/ -void timer_disable(timer_chan_t timer_ch) +void bl602_timer_disable(uint32_t timer_ch) { uint32_t tmp_val; - tmp_val = BL_RD_REG(TIMER_BASE, TIMER_TCER); + tmp_val = bl602_up_tim_regin(TIMER_BASE + TIMER_TCER_OFFSET); tmp_val &= (~(1 << (timer_ch + 1))); - BL_WR_REG(TIMER_BASE, TIMER_TCER, tmp_val); + bl602_up_tim_regout(TIMER_BASE + TIMER_TCER_OFFSET, tmp_val); } /**************************************************************************** - * Name: timer_intmask + * Name: bl602_timer_intmask * * Description: * TIMER mask or unmask certain or all interrupt. @@ -411,15 +461,15 @@ void timer_disable(timer_chan_t timer_ch) * ****************************************************************************/ -void timer_intmask(timer_chan_t timer_ch, - timer_int_t int_type, - uint32_t int_mask) +void bl602_timer_intmask(uint32_t timer_ch, + uint32_t int_type, + uint32_t int_mask) { uint32_t tmp_addr; uint32_t tmp_val; tmp_addr = TIMER_BASE + TIMER_TIER2_OFFSET + 4 * timer_ch; - tmp_val = BL_RD_WORD(tmp_addr); + tmp_val = bl602_up_tim_regin(tmp_addr); switch (int_type) { @@ -428,13 +478,13 @@ void timer_intmask(timer_chan_t timer_ch, { /* Enable this interrupt */ - BL_WR_WORD(tmp_addr, BL_SET_REG_BIT(tmp_val, TIMER_TIER_0)); + bl602_up_tim_regout(tmp_addr, tmp_val |= 1 << TIMER_TIER_0_POS); } else { /* Disable this interrupt */ - BL_WR_WORD(tmp_addr, BL_CLR_REG_BIT(tmp_val, TIMER_TIER_0)); + bl602_up_tim_regout(tmp_addr, tmp_val &= ~(1 << TIMER_TIER_0_POS)); } break; @@ -444,13 +494,13 @@ void timer_intmask(timer_chan_t timer_ch, { /* Enable this interrupt */ - BL_WR_WORD(tmp_addr, BL_SET_REG_BIT(tmp_val, TIMER_TIER_1)); + bl602_up_tim_regout(tmp_addr, tmp_val |= 1 << TIMER_TIER_1_POS); } else { /* Disable this interrupt */ - BL_WR_WORD(tmp_addr, BL_CLR_REG_BIT(tmp_val, TIMER_TIER_1)); + bl602_up_tim_regout(tmp_addr, tmp_val &= ~(1 << TIMER_TIER_1_POS)); } break; @@ -460,13 +510,13 @@ void timer_intmask(timer_chan_t timer_ch, { /* Enable this interrupt */ - BL_WR_WORD(tmp_addr, BL_SET_REG_BIT(tmp_val, TIMER_TIER_2)); + bl602_up_tim_regout(tmp_addr, tmp_val |= 1 << TIMER_TIER_2_POS); } else { /* Disable this interrupt */ - BL_WR_WORD(tmp_addr, BL_CLR_REG_BIT(tmp_val, TIMER_TIER_2)); + bl602_up_tim_regout(tmp_addr, tmp_val &= ~(1 << TIMER_TIER_2_POS)); } break; @@ -476,17 +526,17 @@ void timer_intmask(timer_chan_t timer_ch, { /* Enable this interrupt */ - BL_WR_WORD(tmp_addr, BL_SET_REG_BIT(tmp_val, TIMER_TIER_0)); - BL_WR_WORD(tmp_addr, BL_SET_REG_BIT(tmp_val, TIMER_TIER_1)); - BL_WR_WORD(tmp_addr, BL_SET_REG_BIT(tmp_val, TIMER_TIER_2)); + bl602_up_tim_regout(tmp_addr, tmp_val |= 1 << TIMER_TIER_0_POS); + bl602_up_tim_regout(tmp_addr, tmp_val |= 1 << TIMER_TIER_1_POS); + bl602_up_tim_regout(tmp_addr, tmp_val |= 1 << TIMER_TIER_2_POS); } else { /* Disable this interrupt */ - BL_WR_WORD(tmp_addr, BL_CLR_REG_BIT(tmp_val, TIMER_TIER_0)); - BL_WR_WORD(tmp_addr, BL_CLR_REG_BIT(tmp_val, TIMER_TIER_1)); - BL_WR_WORD(tmp_addr, BL_CLR_REG_BIT(tmp_val, TIMER_TIER_2)); + bl602_up_tim_regout(tmp_addr, tmp_val &= ~(1 << TIMER_TIER_0_POS)); + bl602_up_tim_regout(tmp_addr, tmp_val &= ~(1 << TIMER_TIER_1_POS)); + bl602_up_tim_regout(tmp_addr, tmp_val &= ~(1 << TIMER_TIER_2_POS)); } break; @@ -497,7 +547,7 @@ void timer_intmask(timer_chan_t timer_ch, } /**************************************************************************** - * Name: wdt_set_clock + * Name: bl602_wdt_set_clock * * Description: * TIMER set watchdog clock source and clock division. @@ -511,25 +561,25 @@ void timer_intmask(timer_chan_t timer_ch, * ****************************************************************************/ -void wdt_set_clock(timer_clksrc_t clk_src, uint8_t div) +void bl602_wdt_set_clock(uint32_t clk_src, uint8_t div) { uint32_t tmp_val; /* Configure watchdog timer clock source */ - tmp_val = BL_RD_REG(TIMER_BASE, TIMER_TCCR); - tmp_val = BL_SET_REG_BITS_VAL(tmp_val, TIMER_CS_WDT, clk_src); - BL_WR_REG(TIMER_BASE, TIMER_TCCR, tmp_val); + tmp_val = bl602_up_tim_regin(TIMER_BASE + TIMER_TCCR_OFFSET); + tmp_val = bl602_data_setbits(tmp_val, TIMER_CS_WDT_POS, 2, clk_src); + bl602_up_tim_regout(TIMER_BASE + TIMER_TCCR_OFFSET, tmp_val); /* Configure watchdog timer clock divison */ - tmp_val = BL_RD_REG(TIMER_BASE, TIMER_TCDR); - tmp_val = BL_SET_REG_BITS_VAL(tmp_val, TIMER_WCDR, div); - BL_WR_REG(TIMER_BASE, TIMER_TCDR, tmp_val); + tmp_val = bl602_up_tim_regin(TIMER_BASE + TIMER_TCDR_OFFSET); + tmp_val = bl602_data_setbits(tmp_val, TIMER_WCDR_POS, 8, div); + bl602_up_tim_regout(TIMER_BASE + TIMER_TCDR_OFFSET, tmp_val); } /**************************************************************************** - * Name: wdt_getmatchvalue + * Name: bl602_wdt_getmatchvalue * * Description: * TIMER get watchdog match compare value. @@ -542,21 +592,21 @@ void wdt_set_clock(timer_clksrc_t clk_src, uint8_t div) * ****************************************************************************/ -uint32_t wdt_getmatchvalue(void) +uint32_t bl602_wdt_getmatchvalue(void) { uint32_t tmp_val; - WDT_ENABLE_ACCESS(); + bl602_wdt_access(); /* Get watchdog timer match register value */ - tmp_val = BL_RD_REG(TIMER_BASE, TIMER_WMR); + tmp_val = bl602_up_tim_regin(TIMER_BASE + TIMER_WMR_OFFSET); return tmp_val; } /**************************************************************************** - * Name: wdt_setcompvalue + * Name: bl602_wdt_setcompvalue * * Description: * TIMER set watchdog match compare value. @@ -569,17 +619,17 @@ uint32_t wdt_getmatchvalue(void) * ****************************************************************************/ -void wdt_setcompvalue(uint16_t val) +void bl602_wdt_setcompvalue(uint16_t val) { - WDT_ENABLE_ACCESS(); + bl602_wdt_access(); /* Set watchdog timer match register value */ - BL_WR_REG(TIMER_BASE, TIMER_WMR, val); + bl602_up_tim_regout(TIMER_BASE + TIMER_WMR_OFFSET, val); } /**************************************************************************** - * Name: wdt_getcountervalue + * Name: bl602_wdt_getcountervalue * * Description: * TIMER get watchdog count register value. @@ -592,21 +642,21 @@ void wdt_setcompvalue(uint16_t val) * ****************************************************************************/ -uint16_t wdt_getcountervalue(void) +uint16_t bl602_wdt_getcountervalue(void) { uint32_t tmp_val; - WDT_ENABLE_ACCESS(); + bl602_wdt_access(); /* Get watchdog timer count register value */ - tmp_val = BL_RD_REG(TIMER_BASE, TIMER_WVR); + tmp_val = bl602_up_tim_regin(TIMER_BASE + TIMER_WVR_OFFSET); return tmp_val; } /**************************************************************************** - * Name: wdt_resetcountervalue + * Name: bl602_wdt_resetcountervalue * * Description: * TIMER reset watchdog count register value. @@ -619,23 +669,24 @@ uint16_t wdt_getcountervalue(void) * ****************************************************************************/ -void wdt_resetcountervalue(void) +void bl602_wdt_resetcountervalue(void) { uint32_t tmp_val; /* Reset watchdog timer count register value */ - WDT_ENABLE_ACCESS(); + bl602_wdt_access(); - tmp_val = BL_RD_REG(TIMER_BASE, TIMER_WCR); + tmp_val = bl602_up_tim_regin(TIMER_BASE + TIMER_WCR_OFFSET); /* Set watchdog counter reset register bit0 to 1 */ - BL_WR_REG(TIMER_BASE, TIMER_WCR, BL_SET_REG_BIT(tmp_val, TIMER_WCR)); + bl602_up_tim_regout(TIMER_BASE + TIMER_WCR_OFFSET, + tmp_val |= 1 << TIMER_WCR_POS); } /**************************************************************************** - * Name: wdt_getresetstatus + * Name: bl602_wdt_getresetstatus * * Description: * TIMER get watchdog reset status. @@ -648,23 +699,23 @@ void wdt_resetcountervalue(void) * ****************************************************************************/ -uint32_t wdt_getresetstatus(void) +uint32_t bl602_wdt_getresetstatus(void) { uint32_t tmp_val; uint32_t ret; - WDT_ENABLE_ACCESS(); + bl602_wdt_access(); /* Get watchdog status register */ - tmp_val = BL_RD_REG(TIMER_BASE, TIMER_WSR); + tmp_val = bl602_up_tim_regin(TIMER_BASE + TIMER_WSR_OFFSET); - ret = (BL_IS_REG_BIT_SET(tmp_val, TIMER_WTS)) ? 1 : 0; + ret = (((tmp_val) & (1 << (TIMER_WTS_POS))) ? 1 : 0); return ret; } /**************************************************************************** - * Name: wdt_clearresetstatus + * Name: bl602_wdt_clearresetstatus * * Description: * TIMER clear watchdog reset status. @@ -677,21 +728,22 @@ uint32_t wdt_getresetstatus(void) * ****************************************************************************/ -void wdt_clearresetstatus(void) +void bl602_wdt_clearresetstatus(void) { uint32_t tmp_val; - WDT_ENABLE_ACCESS(); + bl602_wdt_access(); - tmp_val = BL_RD_REG(TIMER_BASE, TIMER_WSR); + tmp_val = bl602_up_tim_regin(TIMER_BASE + TIMER_WSR_OFFSET); /* Set watchdog status register */ - BL_WR_REG(TIMER_BASE, TIMER_WSR, BL_CLR_REG_BIT(tmp_val, TIMER_WTS)); + bl602_up_tim_regout(TIMER_BASE + TIMER_WSR_OFFSET, + tmp_val &= ~(1 << TIMER_WTS_POS)); } /**************************************************************************** - * Name: wdt_enable + * Name: bl602_wdt_enable * * Description: * TIMER enable watchdog function. @@ -704,19 +756,20 @@ void wdt_clearresetstatus(void) * ****************************************************************************/ -void wdt_enable(void) +void bl602_wdt_enable(void) { uint32_t tmp_val; - WDT_ENABLE_ACCESS(); + bl602_wdt_access(); - tmp_val = BL_RD_REG(TIMER_BASE, TIMER_WMER); + tmp_val = bl602_up_tim_regin(TIMER_BASE + TIMER_WMER_OFFSET); - BL_WR_REG(TIMER_BASE, TIMER_WMER, BL_SET_REG_BIT(tmp_val, TIMER_WE)); + bl602_up_tim_regout(TIMER_BASE + TIMER_WMER_OFFSET, + tmp_val |= 1 << TIMER_WE_POS); } /**************************************************************************** - * Name: wdt_disable + * Name: bl602_wdt_disable * * Description: * Watchdog timer disable function. @@ -729,19 +782,20 @@ void wdt_enable(void) * ****************************************************************************/ -void wdt_disable(void) +void bl602_wdt_disable(void) { uint32_t tmp_val; - WDT_ENABLE_ACCESS(); + bl602_wdt_access(); - tmp_val = BL_RD_REG(TIMER_BASE, TIMER_WMER); + tmp_val = bl602_up_tim_regin(TIMER_BASE + TIMER_WMER_OFFSET); - BL_WR_REG(TIMER_BASE, TIMER_WMER, BL_CLR_REG_BIT(tmp_val, TIMER_WE)); + bl602_up_tim_regout(TIMER_BASE + TIMER_WMER_OFFSET, + tmp_val &= ~(1 << TIMER_WE_POS)); } /**************************************************************************** - * Name: wdt_intmask + * Name: bl602_wdt_intmask * * Description: * Watchdog timer mask or unmask certain or all interrupt. @@ -756,17 +810,17 @@ void wdt_disable(void) * ****************************************************************************/ -void wdt_intmask(wdt_int_t int_type, uint32_t int_mask) +void bl602_wdt_intmask(uint32_t int_type, uint32_t int_mask) { uint32_t tmp_val; - WDT_ENABLE_ACCESS(); + bl602_wdt_access(); /* Deal with watchdog match/interrupt enable register,WRIE:watchdog * reset/interrupt enable */ - tmp_val = BL_RD_REG(TIMER_BASE, TIMER_WMER); + tmp_val = bl602_up_tim_regin(TIMER_BASE + TIMER_WMER_OFFSET); switch (int_type) { @@ -779,8 +833,8 @@ void wdt_intmask(wdt_int_t int_type, uint32_t int_mask) * not generated */ - BL_WR_REG( - TIMER_BASE, TIMER_WMER, BL_CLR_REG_BIT(tmp_val, TIMER_WRIE)); + bl602_up_tim_regout(TIMER_BASE + TIMER_WMER_OFFSET, + tmp_val &= ~(1 << TIMER_WRIE_POS)); } else { @@ -790,8 +844,8 @@ void wdt_intmask(wdt_int_t int_type, uint32_t int_mask) * not generated */ - BL_WR_REG( - TIMER_BASE, TIMER_WMER, BL_SET_REG_BIT(tmp_val, TIMER_WRIE)); + bl602_up_tim_regout(TIMER_BASE + TIMER_WMER_OFFSET, + tmp_val |= 1 << TIMER_WRIE_POS); } break; @@ -799,4 +853,3 @@ void wdt_intmask(wdt_int_t int_type, uint32_t int_mask) break; } } - diff --git a/arch/risc-v/src/bl602/bl602_tim_lowerhalf.c b/arch/risc-v/src/bl602/bl602_tim_lowerhalf.c index 390c6663f91..ff01555d7d8 100644 --- a/arch/risc-v/src/bl602/bl602_tim_lowerhalf.c +++ b/arch/risc-v/src/bl602/bl602_tim_lowerhalf.c @@ -1,5 +1,8 @@ /**************************************************************************** - * boards/risc-v/bl602/evb/src/bl602_lowerhalf.c + * arch/risc-v/src/bl602/bl602_tim_lowerhalf.c + * + * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -35,6 +38,7 @@ #include #include +#include "riscv_arch.h" #include #include @@ -50,7 +54,7 @@ * Private Types ****************************************************************************/ -struct bl602_lowerhalf_s +struct bl602_tim_lowerhalf_s { FAR const struct timer_ops_s *ops; /* Lower half operations */ @@ -69,15 +73,15 @@ static int bl602_timer_handler(int irq, void *context, void *arg); /* "Lower half" driver methods */ -static int bl602_start(FAR struct timer_lowerhalf_s *lower); -static int bl602_stop(FAR struct timer_lowerhalf_s *lower); -static int bl602_getstatus(FAR struct timer_lowerhalf_s *lower, - FAR struct timer_status_s * status); -static int bl602_settimeout(FAR struct timer_lowerhalf_s *lower, - uint32_t timeout); -static void bl602_setcallback(FAR struct timer_lowerhalf_s *lower, - tccb_t callback, - FAR void * arg); +static int bl602_tim_start(FAR struct timer_lowerhalf_s *lower); +static int bl602_tim_stop(FAR struct timer_lowerhalf_s *lower); +static int bl602_tim_getstatus(FAR struct timer_lowerhalf_s *lower, + FAR struct timer_status_s * status); +static int bl602_tim_settimeout(FAR struct timer_lowerhalf_s *lower, + uint32_t timeout); +static void bl602_tim_setcallback(FAR struct timer_lowerhalf_s *lower, + tccb_t callback, + FAR void * arg); /**************************************************************************** * Private Data @@ -87,16 +91,16 @@ static void bl602_setcallback(FAR struct timer_lowerhalf_s *lower, static const struct timer_ops_s g_timer_ops = { - .start = bl602_start, - .stop = bl602_stop, - .getstatus = bl602_getstatus, - .settimeout = bl602_settimeout, - .setcallback = bl602_setcallback, + .start = bl602_tim_start, + .stop = bl602_tim_stop, + .getstatus = bl602_tim_getstatus, + .settimeout = bl602_tim_settimeout, + .setcallback = bl602_tim_setcallback, .ioctl = NULL, }; #ifdef CONFIG_BL602_TIMER0 -static struct bl602_lowerhalf_s g_tim1_lowerhalf = +static struct bl602_tim_lowerhalf_s g_tim1_lowerhalf = { .ops = &g_timer_ops, .irq = BL602_IRQ_TIMER_CH0, @@ -105,7 +109,7 @@ static struct bl602_lowerhalf_s g_tim1_lowerhalf = #endif #ifdef CONFIG_BL602_TIMER1 -static struct bl602_lowerhalf_s g_tim2_lowerhalf = +static struct bl602_tim_lowerhalf_s g_tim2_lowerhalf = { .ops = &g_timer_ops, .irq = BL602_IRQ_TIMER_CH1, @@ -131,8 +135,9 @@ static struct bl602_lowerhalf_s g_tim2_lowerhalf = static int bl602_timer_handler(int irq, void *context, void *arg) { - FAR struct bl602_lowerhalf_s *priv = (FAR struct bl602_lowerhalf_s *)arg; - uint32_t next_interval_us = 0; + FAR struct bl602_tim_lowerhalf_s *priv = + (FAR struct bl602_tim_lowerhalf_s *)arg; + uint32_t next_interval_us = 0; /* Clear Interrupt Bits */ @@ -140,54 +145,54 @@ static int bl602_timer_handler(int irq, void *context, void *arg) uint32_t tmp_val; uint32_t tmp_addr; - int_id = BL_RD_WORD(TIMER_BASE + TIMER_TMSR2_OFFSET + 4 * priv->tim); + int_id = getreg32(TIMER_BASE + TIMER_TMSR2_OFFSET + 4 * priv->tim); tmp_addr = TIMER_BASE + TIMER_TICR2_OFFSET + 4 * priv->tim; - tmp_val = BL_RD_WORD(tmp_addr); + tmp_val = getreg32(tmp_addr); /* Comparator 0 match interrupt */ - if (BL_IS_REG_BIT_SET(int_id, TIMER_TMSR_0)) + if (((int_id) & (1 << (TIMER_TMSR_0_POS))) != 0) { - BL_WR_WORD(tmp_addr, BL_SET_REG_BIT(tmp_val, TIMER_TCLR_0)); + putreg32(tmp_val | (1 << TIMER_TCLR_0_POS), tmp_addr); if (priv->callback(&next_interval_us, priv->arg)) { if (next_interval_us > 0) { /* Set a value to the alarm */ - timer_disable(priv->tim); - timer_setcompvalue( + bl602_timer_disable(priv->tim); + bl602_timer_setcompvalue( priv->tim, TIMER_COMP_ID_0, next_interval_us); - timer_setpreloadvalue(priv->tim, 0); - timer_enable(priv->tim); + bl602_timer_setpreloadvalue(priv->tim, 0); + bl602_timer_enable(priv->tim); } } else { - timer_disable(priv->tim); - timer_setpreloadvalue(priv->tim, 0); + bl602_timer_disable(priv->tim); + bl602_timer_setpreloadvalue(priv->tim, 0); } } /* Comparator 1 match interrupt */ - if (BL_IS_REG_BIT_SET(int_id, TIMER_TMSR_1)) + if (((int_id) & (1 << (TIMER_TMSR_1_POS))) != 0) { - BL_WR_WORD(tmp_addr, BL_SET_REG_BIT(tmp_val, TIMER_TCLR_1)); + putreg32(tmp_val | (1 << TIMER_TCLR_1_POS), tmp_addr); } /* Comparator 2 match interrupt */ - if (BL_IS_REG_BIT_SET(int_id, TIMER_TMSR_2)) + if (((int_id) & (1 << (TIMER_TMSR_2_POS))) != 0) { - BL_WR_WORD(tmp_addr, BL_SET_REG_BIT(tmp_val, TIMER_TCLR_2)); + putreg32(tmp_val | (1 << TIMER_TCLR_2_POS), tmp_addr); } return OK; } /**************************************************************************** - * Name: bl602_start + * Name: bl602_tim_start * * Description: * Start the timer, resetting the time to the current timeout, @@ -201,9 +206,10 @@ static int bl602_timer_handler(int irq, void *context, void *arg) * ****************************************************************************/ -static int bl602_start(FAR struct timer_lowerhalf_s *lower) +static int bl602_tim_start(FAR struct timer_lowerhalf_s *lower) { - FAR struct bl602_lowerhalf_s *priv = (FAR struct bl602_lowerhalf_s *)lower; + FAR struct bl602_tim_lowerhalf_s *priv = + (FAR struct bl602_tim_lowerhalf_s *)lower; if (!priv->started) { @@ -212,11 +218,11 @@ static int bl602_start(FAR struct timer_lowerhalf_s *lower) return -EPERM; } - timer_setpreloadvalue(priv->tim, 0); + bl602_timer_setpreloadvalue(priv->tim, 0); irq_attach(priv->irq, bl602_timer_handler, (void *)priv); up_enable_irq(priv->irq); - timer_intmask(priv->tim, TIMER_INT_COMP_0, 0); - timer_enable(priv->tim); + bl602_timer_intmask(priv->tim, TIMER_INT_COMP_0, 0); + bl602_timer_enable(priv->tim); priv->started = true; return OK; } @@ -227,7 +233,7 @@ static int bl602_start(FAR struct timer_lowerhalf_s *lower) } /**************************************************************************** - * Name: bl602_stop + * Name: bl602_tim_stop * * Description: * Stop the timer @@ -241,18 +247,19 @@ static int bl602_start(FAR struct timer_lowerhalf_s *lower) * ****************************************************************************/ -static int bl602_stop(FAR struct timer_lowerhalf_s *lower) +static int bl602_tim_stop(FAR struct timer_lowerhalf_s *lower) { - FAR struct bl602_lowerhalf_s *priv = (FAR struct bl602_lowerhalf_s *)lower; + FAR struct bl602_tim_lowerhalf_s *priv = + (FAR struct bl602_tim_lowerhalf_s *)lower; /* timer disable */ if (priv->started) { - timer_disable(priv->tim); + bl602_timer_disable(priv->tim); priv->started = false; up_disable_irq(priv->irq); - timer_intmask(priv->tim, TIMER_INT_COMP_0, 1); + bl602_timer_intmask(priv->tim, TIMER_INT_COMP_0, 1); return OK; } @@ -262,7 +269,7 @@ static int bl602_stop(FAR struct timer_lowerhalf_s *lower) } /**************************************************************************** - * Name: bl602_getstatus + * Name: bl602_tim_getstatus * * Description: * get timer status @@ -277,14 +284,15 @@ static int bl602_stop(FAR struct timer_lowerhalf_s *lower) * ****************************************************************************/ -static int bl602_getstatus(FAR struct timer_lowerhalf_s *lower, - FAR struct timer_status_s * status) +static int bl602_tim_getstatus(FAR struct timer_lowerhalf_s *lower, + FAR struct timer_status_s * status) { - FAR struct bl602_lowerhalf_s *priv = (FAR struct bl602_lowerhalf_s *)lower; - uint32_t current_count; + FAR struct bl602_tim_lowerhalf_s *priv = + (FAR struct bl602_tim_lowerhalf_s *)lower; + uint32_t current_count; status->timeout = timer_getcompvalue(priv->tim, TIMER_COMP_ID_0); - current_count = timer_getcountervalue(priv->tim); + current_count = bl602_timer_getcountervalue(priv->tim); if (current_count < status->timeout) { status->timeleft = status->timeout - current_count; @@ -298,7 +306,7 @@ static int bl602_getstatus(FAR struct timer_lowerhalf_s *lower, } /**************************************************************************** - * Name: bl602_settimeout + * Name: bl602_tim_settimeout * * Description: * Set a new timeout value (and reset the timer) @@ -313,18 +321,19 @@ static int bl602_getstatus(FAR struct timer_lowerhalf_s *lower, * ****************************************************************************/ -static int bl602_settimeout(FAR struct timer_lowerhalf_s *lower, - uint32_t timeout) +static int bl602_tim_settimeout(FAR struct timer_lowerhalf_s *lower, + uint32_t timeout) { - FAR struct bl602_lowerhalf_s *priv = (FAR struct bl602_lowerhalf_s *)lower; + FAR struct bl602_tim_lowerhalf_s *priv = + (FAR struct bl602_tim_lowerhalf_s *)lower; - timer_setcompvalue(priv->tim, TIMER_COMP_ID_0, timeout); + bl602_timer_setcompvalue(priv->tim, TIMER_COMP_ID_0, timeout); return OK; } /**************************************************************************** - * Name: bl602_setcallback + * Name: bl602_tim_setcallback * * Description: * Call this user provided timeout handler. @@ -342,12 +351,13 @@ static int bl602_settimeout(FAR struct timer_lowerhalf_s *lower, * ****************************************************************************/ -static void bl602_setcallback(FAR struct timer_lowerhalf_s *lower, - tccb_t callback, - FAR void * arg) +static void bl602_tim_setcallback(FAR struct timer_lowerhalf_s *lower, + tccb_t callback, + FAR void * arg) { - struct bl602_lowerhalf_s *priv = (FAR struct bl602_lowerhalf_s *)lower; - irqstate_t flags = enter_critical_section(); + struct bl602_tim_lowerhalf_s *priv = + (FAR struct bl602_tim_lowerhalf_s *)lower; + irqstate_t flags = enter_critical_section(); /* Save the new callback */ @@ -381,8 +391,8 @@ static void bl602_setcallback(FAR struct timer_lowerhalf_s *lower, int bl602_timer_initialize(FAR const char *devpath, int timer) { - FAR struct bl602_lowerhalf_s *lower; - timer_cfg_t timstr; + FAR struct bl602_tim_lowerhalf_s *lower; + timer_cfg_t timstr; switch (timer) { @@ -413,15 +423,15 @@ int bl602_timer_initialize(FAR const char *devpath, int timer) timstr.match_val2 = TIMER_MAX_VALUE; /* Timer match 2 value 0 */ timstr.pre_load_val = TIMER_MAX_VALUE; /* Timer preload value */ - glb_ahb_slave1_reset(BL_AHB_SLAVE1_TMR); + bl602_glb_ahb_slave1_reset(BL_AHB_SLAVE1_TMR); - timer_intmask(lower->tim, TIMER_INT_ALL, 1); + bl602_timer_intmask(lower->tim, TIMER_INT_ALL, 1); /* timer disable */ - timer_disable(lower->tim); + bl602_timer_disable(lower->tim); - timer_init(&timstr); + bl602_timer_init(&timstr); /* Initialize the elements of lower half state structure */ @@ -448,4 +458,3 @@ int bl602_timer_initialize(FAR const char *devpath, int timer) return OK; } - diff --git a/arch/risc-v/src/bl602/bl602_tim_lowerhalf.h b/arch/risc-v/src/bl602/bl602_tim_lowerhalf.h index 9b9eaea55da..f330453350c 100644 --- a/arch/risc-v/src/bl602/bl602_tim_lowerhalf.h +++ b/arch/risc-v/src/bl602/bl602_tim_lowerhalf.h @@ -1,6 +1,9 @@ /** * incubator-nuttx/arch/risc-v/src/bl602/bl602_lowerhalf.h * + * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at diff --git a/arch/risc-v/src/bl602/bl602_timerisr.c b/arch/risc-v/src/bl602/bl602_timerisr.c index b5e9e5d90b6..c015b3dfabf 100644 --- a/arch/risc-v/src/bl602/bl602_timerisr.c +++ b/arch/risc-v/src/bl602/bl602_timerisr.c @@ -1,6 +1,9 @@ /**************************************************************************** * arch/risc-v/src/bl602/bl602_timerisr.c * + * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with * this work for additional information regarding copyright ownership. The @@ -31,7 +34,7 @@ #include #include #include - +#include "hardware/bl602_clint.h" #include "riscv_arch.h" #include "chip.h" @@ -40,21 +43,14 @@ * Pre-processor Definitions ****************************************************************************/ -#define TICK_COUNT (10 * 1000 * 1000 / TICK_PER_SEC) -#define CLINT_BASE_ADDRESS 0x02000000 - -#define getreg64(a) (*(volatile uint64_t *)(a)) -#define putreg64(v, a) (*(volatile uint64_t *)(a) = (v)) +/* Private definetions: mtimer frequency */ +#define TICK_COUNT (10 * 1000 * 1000 / TICK_PER_SEC) /**************************************************************************** * Private Data ****************************************************************************/ -static bool _b_tick_started = false; - -#define MTIMER_HIGH (CLINT_BASE_ADDRESS + 0xBFFC) -#define MTIMER_LOW (CLINT_BASE_ADDRESS + 0xBFF8) -#define MTIMER_CMP (CLINT_BASE_ADDRESS + 0x4000) +static bool g_b_tick_started = false; /**************************************************************************** * Private Functions @@ -68,21 +64,21 @@ static bool _b_tick_started = false; static inline uint64_t bl602_clint_time_read(void) { - uint64_t r = getreg32(MTIMER_HIGH); + uint64_t r = getreg32(BL602_MTIMER_HIGH); r <<= 32; - r |= getreg32(MTIMER_LOW); + r |= getreg32(BL602_MTIMER_LOW); return r; } static inline uint64_t bl602_clint_time_cmp_read(void) { - return getreg64(MTIMER_CMP); + return getreg64(BL602_MTIMER_CMP); } static inline void bl602_clint_time_cmp_write(uint64_t v) { - putreg64(v, MTIMER_CMP); + putreg64(v, BL602_MTIMER_CMP); } /**************************************************************************** @@ -96,10 +92,10 @@ static void bl602_reload_mtimecmp(void) uint64_t current; uint64_t next; - if (!_b_tick_started) + if (!g_b_tick_started) { - _b_tick_started = true; - current = bl602_clint_time_read(); + g_b_tick_started = true; + current = bl602_clint_time_read(); } else { @@ -154,4 +150,3 @@ void up_timer_initialize(void) up_enable_irq(BL602_IRQ_MTIMER); } - diff --git a/arch/risc-v/src/bl602/bl602_vectors.S b/arch/risc-v/src/bl602/bl602_vectors.S index 2c090685330..523a69803dc 100644 --- a/arch/risc-v/src/bl602/bl602_vectors.S +++ b/arch/risc-v/src/bl602/bl602_vectors.S @@ -1,6 +1,9 @@ /**************************************************************************** * arch/risc-v/src/bl602/bl602_vectors.S * + * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with * this work for additional information regarding copyright ownership. The diff --git a/arch/risc-v/src/bl602/chip.h b/arch/risc-v/src/bl602/chip.h index afc95b0b160..a0e7b265829 100644 --- a/arch/risc-v/src/bl602/chip.h +++ b/arch/risc-v/src/bl602/chip.h @@ -1,6 +1,9 @@ /**************************************************************************** * arch/risc-v/include/bl602/chip.h * + * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with * this work for additional information regarding copyright ownership. The diff --git a/arch/risc-v/src/bl602/hardware/bl602_clint.h b/arch/risc-v/src/bl602/hardware/bl602_clint.h new file mode 100644 index 00000000000..c1b4e458c9e --- /dev/null +++ b/arch/risc-v/src/bl602/hardware/bl602_clint.h @@ -0,0 +1,43 @@ +/**************************************************************************** + * arch/risc-v/src/bl602/hardware/bl602_clint.h + * + * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_CLINT_H +#define __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_CLINT_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define BL602_CLINT_BASE (0x02000000) + +#define BL602_MTIMER_HIGH ((uint32_t *)(BL602_CLINT_BASE + 0xBFFC)) +#define BL602_MTIMER_LOW ((uint32_t *)(BL602_CLINT_BASE + 0xBFF8)) +#define BL602_MTIMER_CMP ((uint64_t *)(BL602_CLINT_BASE + 0x4000)) + +#endif /* __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_CLINT_H */ diff --git a/arch/risc-v/src/bl602/hardware/bl602_common.h b/arch/risc-v/src/bl602/hardware/bl602_common.h index 7b41b64718c..6b48db092c8 100644 --- a/arch/risc-v/src/bl602/hardware/bl602_common.h +++ b/arch/risc-v/src/bl602/hardware/bl602_common.h @@ -1,6 +1,9 @@ /**************************************************************************** * arch/risc-v/src/bl602/hardware/bl602_common.h * + * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with * this work for additional information regarding copyright ownership. The @@ -31,131 +34,126 @@ * Pre-processor Definitions ****************************************************************************/ -#define BL602_FLASH_XIP_BASE 0x23000000 +#define BL602_FLASH_XIP_BASE (0x23000000) #define BL602_FLASH_XIP_END (0x23000000 + 16 * 1024 * 1024) -#define BL602_FLASH_XIP_REMAP0_BASE 0x33000000 +#define BL602_FLASH_XIP_REMAP0_BASE (0x33000000) #define BL602_FLASH_XIP_REMAP0_END (0x33000000 + 16 * 1024 * 1024) -#define BL602_FLASH_XIP_REMAP1_BASE 0x43000000 +#define BL602_FLASH_XIP_REMAP1_BASE (0x43000000) #define BL602_FLASH_XIP_REMAP1_END (0x43000000 + 16 * 1024 * 1024) -#define BL602_FLASH_XIP_REMAP2_BASE 0x53000000 +#define BL602_FLASH_XIP_REMAP2_BASE (0x53000000) #define BL602_FLASH_XIP_REMAP2_END (0x53000000 + 16 * 1024 * 1024) -#define BL602_WRAM_BASE 0x42020000 +#define BL602_WRAM_BASE (0x42020000) #define BL602_WRAM_END (0x42020000 + 176 * 1024) -#define BL602_WRAM_REMAP0_BASE 0x22020000 +#define BL602_WRAM_REMAP0_BASE (0x22020000) #define BL602_WRAM_REMAP0_END (0x22020000 + 176 * 1024) -#define BL602_WRAM_REMAP1_BASE 0x32020000 +#define BL602_WRAM_REMAP1_BASE (0x32020000) + #define BL602_WRAM_REMAP1_END (0x32020000 + 176 * 1024) -#define BL602_WRAM_REMAP2_BASE 0x52020000 +#define BL602_WRAM_REMAP2_BASE (0x52020000) #define BL602_WRAM_REMAP2_END (0x52020000 + 176 * 1024) -#define BL602_TCM_BASE 0x22008000 +#define BL602_TCM_BASE (0x22008000) #define BL602_TCM_END (0x22008000 + (96 + 176) * 1024) -#define BL602_TCM_REMAP0_BASE 0x32008000 +#define BL602_TCM_REMAP0_BASE (0x32008000) #define BL602_TCM_REMAP0_END (0x32008000 + (96 + 176) * 1024) -#define BL602_TCM_REMAP1_BASE 0x42008000 +#define BL602_TCM_REMAP1_BASE (0x42008000) #define BL602_TCM_REMAP1_END (0x42008000 + (96 + 176) * 1024) -#define BL602_TCM_REMAP2_BASE 0x52008000 +#define BL602_TCM_REMAP2_BASE (0x52008000) #define BL602_TCM_REMAP2_END (0x52008000 + (96 + 176) * 1024) /* BL602 peripherals base address */ -#define GLB_BASE ((uint32_t)0x40000000) -#define RF_BASE ((uint32_t)0x40001000) +#define GLB_BASE (0x40000000) +#define RF_BASE (0x40001000) /* AUX module base address */ -#define GPIP_BASE ((uint32_t)0x40002000) +#define GPIP_BASE (0x40002000) /* Security Debug module base address */ -#define SEC_DBG_BASE ((uint32_t)0x40003000) +#define SEC_DBG_BASE (0x40003000) /* Security Engine module base address */ -#define SEC_ENG_BASE ((uint32_t)0x40004000) +#define SEC_ENG_BASE (0x40004000) /* Trustzone control security base address */ -#define TZC_SEC_BASE ((uint32_t)0x40005000) +#define TZC_SEC_BASE (0x40005000) /* Trustzone control none-security base address */ -#define TZC_NSEC_BASE ((uint32_t)0x40006000) -#define EF_DATA_BASE ((uint32_t)0x40007000) -#define EF_CTRL_BASE ((uint32_t)0x40007000) -#define CCI_BASE ((uint32_t)0x40008000) +#define TZC_NSEC_BASE (0x40006000) +#define EF_DATA_BASE (0x40007000) +#define EF_CTRL_BASE (0x40007000) +#define CCI_BASE (0x40008000) /* L1 cache config base address */ -#define L1C_BASE ((uint32_t)0x40009000) -#define UART0_BASE ((uint32_t)0x4000A000) -#define UART1_BASE ((uint32_t)0x4000A100) -#define SPI_BASE ((uint32_t)0x4000A200) -#define I2C_BASE ((uint32_t)0x4000A300) -#define PWM_BASE ((uint32_t)0x4000A400) -#define TIMER_BASE ((uint32_t)0x4000A500) -#define IR_BASE ((uint32_t)0x4000A600) -#define SF_CTRL_BASE ((uint32_t)0x4000B000) -#define SF_CTRL_BUF_BASE ((uint32_t)0x4000B700) -#define DMA_BASE ((uint32_t)0x4000C000) -#define SDU_BASE ((uint32_t)0x4000D000) +#define L1C_BASE (0x40009000) +#define UART0_BASE (0x4000A000) +#define UART1_BASE (0x4000A100) +#define SPI_BASE (0x4000A200) +#define I2C_BASE (0x4000A300) +#define PWM_BASE (0x4000A400) +#define TIMER_BASE (0x4000A500) +#define IR_BASE (0x4000A600) +#define SF_CTRL_BASE (0x4000B000) +#define SF_CTRL_BUF_BASE (0x4000B700) +#define DMA_BASE (0x4000C000) +#define SDU_BASE (0x4000D000) /* Power down sleep module base address */ -#define PDS_BASE ((uint32_t)0x4000E000) +#define PDS_BASE (0x4000E000) /* Hibernate module base address */ -#define HBN_BASE ((uint32_t)0x4000F000) +#define HBN_BASE (0x4000F000) /* Always on module base address */ -#define AON_BASE ((uint32_t)0x4000F000) -#define HBN_RAM_BASE ((uint32_t)0x40010000) +#define AON_BASE (0x4000F000) +#define HBN_RAM_BASE (0x40010000) -#define BL_RD_WORD(addr) (*((volatile uint32_t *)(addr))) -#define BL_WR_WORD(addr, val) ((*(volatile uint32_t *)(addr)) = (val)) -#define BL_RD_SHORT(addr) (*((volatile uint16_t *)(addr))) -#define BL_WR_SHORT(addr, val) ((*(volatile uint16_t *)(addr)) = (val)) -#define BL_RD_BYTE(addr) (*((volatile uint8_t *)(addr))) -#define BL_WR_BYTE(addr, val) ((*(volatile uint8_t *)(addr)) = (val)) -#define BL_RDWD_FRM_BYTEP(p) \ - ((p[3] << 24) | (p[2] << 16) | (p[1] << 8) | (p[0])) -#define BL_WRWD_TO_BYTEP(p, val) \ +/* Delay for a while */ + +#define BL_DRV_DUMMY() \ { \ - p[0] = val & 0xff; \ - p[1] = (val >> 8) & 0xff; \ - p[2] = (val >> 16) & 0xff; \ - p[3] = (val >> 24) & 0xff; \ - } -/** - * @brief Register access macro - */ -#define BL_RD_REG16(addr, regname) BL_RD_SHORT(addr + regname##_OFFSET) -#define BL_WR_REG16(addr, regname, val) \ - BL_WR_SHORT(addr + regname##_OFFSET, val) -#define BL_RD_REG(addr, regname) BL_RD_WORD(addr + regname##_OFFSET) -#define BL_WR_REG(addr, regname, val) BL_WR_WORD(addr + regname##_OFFSET, val) -#define BL_SET_REG_BIT(val, bitname) ((val) | (1U << bitname##_POS)) -#define BL_CLR_REG_BIT(val, bitname) ((val)&bitname##_UMSK) -#define BL_GET_REG_BITS_VAL(val, bitname) \ - (((val)&bitname##_MSK) >> bitname##_POS) -#define BL_SET_REG_BITS_VAL(val, bitname, bitval) \ - (((val)&bitname##_UMSK) | ((uint32_t)(bitval) << bitname##_POS)) -#define BL_IS_REG_BIT_SET(val, bitname) \ - (((val) & (1U << (bitname##_POS))) != 0) -#define __NOP() \ - __asm volatile("nop") /* This implementation generates debug information \ - */ -#define BL_DRV_DUMMY \ - { \ - __NOP(); \ - __NOP(); \ - __NOP(); \ - __NOP(); \ + __asm volatile("nop"); \ + __asm volatile("nop"); \ + __asm volatile("nop"); \ + __asm volatile("nop"); \ } +#define BL_AHB_SLAVE1_GLB 0x00 +#define BL_AHB_SLAVE1_RF 0x01 +#define BL_AHB_SLAVE1_GPIP_PHY_AGC 0x02 +#define BL_AHB_SLAVE1_SEC_DBG 0x03 +#define BL_AHB_SLAVE1_SEC 0x04 +#define BL_AHB_SLAVE1_TZ1 0x05 +#define BL_AHB_SLAVE1_TZ2 0x06 +#define BL_AHB_SLAVE1_EFUSE 0x07 +#define BL_AHB_SLAVE1_CCI 0x08 +#define BL_AHB_SLAVE1_L1C 0x09 +#define BL_AHB_SLAVE1_RSVD0A 0x0a +#define BL_AHB_SLAVE1_SFC 0x0b +#define BL_AHB_SLAVE1_DMA 0x0c +#define BL_AHB_SLAVE1_SDU 0x0d +#define BL_AHB_SLAVE1_PDS_HBN_AON_HBNRAM 0x0e +#define BL_AHB_SLAVE1_RSVD0F 0x0f +#define BL_AHB_SLAVE1_UART0 0x10 +#define BL_AHB_SLAVE1_UART1 0x11 +#define BL_AHB_SLAVE1_SPI 0x12 +#define BL_AHB_SLAVE1_I2C 0x13 +#define BL_AHB_SLAVE1_PWM 0x14 +#define BL_AHB_SLAVE1_TMR 0x15 +#define BL_AHB_SLAVE1_IRR 0x16 +#define BL_AHB_SLAVE1_CKS 0x17 +#define BL_AHB_SLAVE1_MAX 0x18 + /* Std driver attribute macro */ #define ATTR_CLOCK_SECTION __attribute__((section(".sclock_rlt_code"))) @@ -164,8 +162,6 @@ #define ATTR_TCM_CONST_SECTION __attribute__((section(".tcm_const"))) #define ATTR_DTCM_SECTION __attribute__((section(".tcm_data"))) #define ATTR_HSRAM_SECTION __attribute__((section(".hsram_code"))) -#define SystemCoreClockSet(val) BL_WR_WORD(0x4000f108, val) -#define SystemCoreClockGet(val) BL_RD_WORD(0x4000f108) /**************************************************************************** * Public Types @@ -173,39 +169,6 @@ #ifndef __ASSEMBLY__ -enum bl_ahb_slave1_e -{ - BL_AHB_SLAVE1_GLB = 0x00, - BL_AHB_SLAVE1_RF = 0x01, - BL_AHB_SLAVE1_GPIP_PHY_AGC = 0x02, - BL_AHB_SLAVE1_SEC_DBG = 0x03, - BL_AHB_SLAVE1_SEC = 0x04, - BL_AHB_SLAVE1_TZ1 = 0x05, - BL_AHB_SLAVE1_TZ2 = 0x06, - BL_AHB_SLAVE1_EFUSE = 0x07, - BL_AHB_SLAVE1_CCI = 0x08, - BL_AHB_SLAVE1_L1C = 0x09, - BL_AHB_SLAVE1_RSVD0A = 0x0a, - BL_AHB_SLAVE1_SFC = 0x0b, - BL_AHB_SLAVE1_DMA = 0x0c, - BL_AHB_SLAVE1_SDU = 0x0d, - BL_AHB_SLAVE1_PDS_HBN_AON_HBNRAM = 0x0e, - BL_AHB_SLAVE1_RSVD0F = 0x0f, - BL_AHB_SLAVE1_UART0 = 0x10, - BL_AHB_SLAVE1_UART1 = 0x11, - BL_AHB_SLAVE1_SPI = 0x12, - BL_AHB_SLAVE1_I2C = 0x13, - BL_AHB_SLAVE1_PWM = 0x14, - BL_AHB_SLAVE1_TMR = 0x15, - BL_AHB_SLAVE1_IRR = 0x16, - BL_AHB_SLAVE1_CKS = 0x17, - BL_AHB_SLAVE1_MAX = 0x18, -}; - -/**************************************************************************** - * Public Data - ****************************************************************************/ - #ifdef __cplusplus #define EXTERN extern "C" extern "C" @@ -214,14 +177,6 @@ extern "C" #define EXTERN extern #endif -/**************************************************************************** - * Inline Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - #undef EXTERN #ifdef __cplusplus } diff --git a/arch/risc-v/src/bl602/hardware/bl602_glb.h b/arch/risc-v/src/bl602/hardware/bl602_glb.h index d99514e59de..b689001cece 100644 --- a/arch/risc-v/src/bl602/hardware/bl602_glb.h +++ b/arch/risc-v/src/bl602/hardware/bl602_glb.h @@ -1,6 +1,9 @@ /**************************************************************************** * arch/risc-v/src/bl602/hardware/bl602_glb.h * + * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with * this work for additional information regarding copyright ownership. The @@ -35,459 +38,459 @@ #define GLB_CLK_CFG0_OFFSET (0x0) #define GLB_REG_PLL_EN GLB_REG_PLL_EN -#define GLB_REG_PLL_EN_POS (0U) -#define GLB_REG_PLL_EN_LEN (1U) +#define GLB_REG_PLL_EN_POS (0) +#define GLB_REG_PLL_EN_LEN (1) #define GLB_REG_PLL_EN_MSK \ - (((1U << GLB_REG_PLL_EN_LEN) - 1) << GLB_REG_PLL_EN_POS) + (((1 << GLB_REG_PLL_EN_LEN) - 1) << GLB_REG_PLL_EN_POS) #define GLB_REG_PLL_EN_UMSK \ - (~(((1U << GLB_REG_PLL_EN_LEN) - 1) << GLB_REG_PLL_EN_POS)) + (~(((1 << GLB_REG_PLL_EN_LEN) - 1) << GLB_REG_PLL_EN_POS)) #define GLB_REG_FCLK_EN GLB_REG_FCLK_EN -#define GLB_REG_FCLK_EN_POS (1U) -#define GLB_REG_FCLK_EN_LEN (1U) +#define GLB_REG_FCLK_EN_POS (1) +#define GLB_REG_FCLK_EN_LEN (1) #define GLB_REG_FCLK_EN_MSK \ - (((1U << GLB_REG_FCLK_EN_LEN) - 1) << GLB_REG_FCLK_EN_POS) + (((1 << GLB_REG_FCLK_EN_LEN) - 1) << GLB_REG_FCLK_EN_POS) #define GLB_REG_FCLK_EN_UMSK \ - (~(((1U << GLB_REG_FCLK_EN_LEN) - 1) << GLB_REG_FCLK_EN_POS)) + (~(((1 << GLB_REG_FCLK_EN_LEN) - 1) << GLB_REG_FCLK_EN_POS)) #define GLB_REG_HCLK_EN GLB_REG_HCLK_EN -#define GLB_REG_HCLK_EN_POS (2U) -#define GLB_REG_HCLK_EN_LEN (1U) +#define GLB_REG_HCLK_EN_POS (2) +#define GLB_REG_HCLK_EN_LEN (1) #define GLB_REG_HCLK_EN_MSK \ - (((1U << GLB_REG_HCLK_EN_LEN) - 1) << GLB_REG_HCLK_EN_POS) + (((1 << GLB_REG_HCLK_EN_LEN) - 1) << GLB_REG_HCLK_EN_POS) #define GLB_REG_HCLK_EN_UMSK \ - (~(((1U << GLB_REG_HCLK_EN_LEN) - 1) << GLB_REG_HCLK_EN_POS)) + (~(((1 << GLB_REG_HCLK_EN_LEN) - 1) << GLB_REG_HCLK_EN_POS)) #define GLB_REG_BCLK_EN GLB_REG_BCLK_EN -#define GLB_REG_BCLK_EN_POS (3U) -#define GLB_REG_BCLK_EN_LEN (1U) +#define GLB_REG_BCLK_EN_POS (3) +#define GLB_REG_BCLK_EN_LEN (1) #define GLB_REG_BCLK_EN_MSK \ - (((1U << GLB_REG_BCLK_EN_LEN) - 1) << GLB_REG_BCLK_EN_POS) + (((1 << GLB_REG_BCLK_EN_LEN) - 1) << GLB_REG_BCLK_EN_POS) #define GLB_REG_BCLK_EN_UMSK \ - (~(((1U << GLB_REG_BCLK_EN_LEN) - 1) << GLB_REG_BCLK_EN_POS)) + (~(((1 << GLB_REG_BCLK_EN_LEN) - 1) << GLB_REG_BCLK_EN_POS)) #define GLB_REG_PLL_SEL GLB_REG_PLL_SEL -#define GLB_REG_PLL_SEL_POS (4U) -#define GLB_REG_PLL_SEL_LEN (2U) +#define GLB_REG_PLL_SEL_POS (4) +#define GLB_REG_PLL_SEL_LEN (2) #define GLB_REG_PLL_SEL_MSK \ - (((1U << GLB_REG_PLL_SEL_LEN) - 1) << GLB_REG_PLL_SEL_POS) + (((1 << GLB_REG_PLL_SEL_LEN) - 1) << GLB_REG_PLL_SEL_POS) #define GLB_REG_PLL_SEL_UMSK \ - (~(((1U << GLB_REG_PLL_SEL_LEN) - 1) << GLB_REG_PLL_SEL_POS)) + (~(((1 << GLB_REG_PLL_SEL_LEN) - 1) << GLB_REG_PLL_SEL_POS)) #define GLB_HBN_ROOT_CLK_SEL GLB_HBN_ROOT_CLK_SEL -#define GLB_HBN_ROOT_CLK_SEL_POS (6U) -#define GLB_HBN_ROOT_CLK_SEL_LEN (2U) +#define GLB_HBN_ROOT_CLK_SEL_POS (6) +#define GLB_HBN_ROOT_CLK_SEL_LEN (2) #define GLB_HBN_ROOT_CLK_SEL_MSK \ - (((1U << GLB_HBN_ROOT_CLK_SEL_LEN) - 1) << GLB_HBN_ROOT_CLK_SEL_POS) + (((1 << GLB_HBN_ROOT_CLK_SEL_LEN) - 1) << GLB_HBN_ROOT_CLK_SEL_POS) #define GLB_HBN_ROOT_CLK_SEL_UMSK \ - (~(((1U << GLB_HBN_ROOT_CLK_SEL_LEN) - 1) << GLB_HBN_ROOT_CLK_SEL_POS)) + (~(((1 << GLB_HBN_ROOT_CLK_SEL_LEN) - 1) << GLB_HBN_ROOT_CLK_SEL_POS)) #define GLB_REG_HCLK_DIV GLB_REG_HCLK_DIV -#define GLB_REG_HCLK_DIV_POS (8U) -#define GLB_REG_HCLK_DIV_LEN (8U) +#define GLB_REG_HCLK_DIV_POS (8) +#define GLB_REG_HCLK_DIV_LEN (8) #define GLB_REG_HCLK_DIV_MSK \ - (((1U << GLB_REG_HCLK_DIV_LEN) - 1) << GLB_REG_HCLK_DIV_POS) + (((1 << GLB_REG_HCLK_DIV_LEN) - 1) << GLB_REG_HCLK_DIV_POS) #define GLB_REG_HCLK_DIV_UMSK \ - (~(((1U << GLB_REG_HCLK_DIV_LEN) - 1) << GLB_REG_HCLK_DIV_POS)) + (~(((1 << GLB_REG_HCLK_DIV_LEN) - 1) << GLB_REG_HCLK_DIV_POS)) #define GLB_REG_BCLK_DIV GLB_REG_BCLK_DIV -#define GLB_REG_BCLK_DIV_POS (16U) -#define GLB_REG_BCLK_DIV_LEN (8U) +#define GLB_REG_BCLK_DIV_POS (16) +#define GLB_REG_BCLK_DIV_LEN (8) #define GLB_REG_BCLK_DIV_MSK \ - (((1U << GLB_REG_BCLK_DIV_LEN) - 1) << GLB_REG_BCLK_DIV_POS) + (((1 << GLB_REG_BCLK_DIV_LEN) - 1) << GLB_REG_BCLK_DIV_POS) #define GLB_REG_BCLK_DIV_UMSK \ - (~(((1U << GLB_REG_BCLK_DIV_LEN) - 1) << GLB_REG_BCLK_DIV_POS)) + (~(((1 << GLB_REG_BCLK_DIV_LEN) - 1) << GLB_REG_BCLK_DIV_POS)) #define GLB_FCLK_SW_STATE GLB_FCLK_SW_STATE -#define GLB_FCLK_SW_STATE_POS (24U) -#define GLB_FCLK_SW_STATE_LEN (3U) +#define GLB_FCLK_SW_STATE_POS (24) +#define GLB_FCLK_SW_STATE_LEN (3) #define GLB_FCLK_SW_STATE_MSK \ - (((1U << GLB_FCLK_SW_STATE_LEN) - 1) << GLB_FCLK_SW_STATE_POS) + (((1 << GLB_FCLK_SW_STATE_LEN) - 1) << GLB_FCLK_SW_STATE_POS) #define GLB_FCLK_SW_STATE_UMSK \ - (~(((1U << GLB_FCLK_SW_STATE_LEN) - 1) << GLB_FCLK_SW_STATE_POS)) + (~(((1 << GLB_FCLK_SW_STATE_LEN) - 1) << GLB_FCLK_SW_STATE_POS)) #define GLB_CHIP_RDY GLB_CHIP_RDY -#define GLB_CHIP_RDY_POS (27U) -#define GLB_CHIP_RDY_LEN (1U) -#define GLB_CHIP_RDY_MSK (((1U << GLB_CHIP_RDY_LEN) - 1) << GLB_CHIP_RDY_POS) +#define GLB_CHIP_RDY_POS (27) +#define GLB_CHIP_RDY_LEN (1) +#define GLB_CHIP_RDY_MSK (((1 << GLB_CHIP_RDY_LEN) - 1) << GLB_CHIP_RDY_POS) #define GLB_CHIP_RDY_UMSK \ - (~(((1U << GLB_CHIP_RDY_LEN) - 1) << GLB_CHIP_RDY_POS)) + (~(((1 << GLB_CHIP_RDY_LEN) - 1) << GLB_CHIP_RDY_POS)) #define GLB_ID GLB_ID -#define GLB_ID_POS (28U) -#define GLB_ID_LEN (4U) -#define GLB_ID_MSK (((1U << GLB_ID_LEN) - 1) << GLB_ID_POS) -#define GLB_ID_UMSK (~(((1U << GLB_ID_LEN) - 1) << GLB_ID_POS)) +#define GLB_ID_POS (28) +#define GLB_ID_LEN (4) +#define GLB_ID_MSK (((1 << GLB_ID_LEN) - 1) << GLB_ID_POS) +#define GLB_ID_UMSK (~(((1 << GLB_ID_LEN) - 1) << GLB_ID_POS)) /* 0x4 : clk_cfg1 */ #define GLB_CLK_CFG1_OFFSET (0x4) #define GLB_WIFI_MAC_CORE_DIV GLB_WIFI_MAC_CORE_DIV -#define GLB_WIFI_MAC_CORE_DIV_POS (0U) -#define GLB_WIFI_MAC_CORE_DIV_LEN (4U) +#define GLB_WIFI_MAC_CORE_DIV_POS (0) +#define GLB_WIFI_MAC_CORE_DIV_LEN (4) #define GLB_WIFI_MAC_CORE_DIV_MSK \ - (((1U << GLB_WIFI_MAC_CORE_DIV_LEN) - 1) << GLB_WIFI_MAC_CORE_DIV_POS) + (((1 << GLB_WIFI_MAC_CORE_DIV_LEN) - 1) << GLB_WIFI_MAC_CORE_DIV_POS) #define GLB_WIFI_MAC_CORE_DIV_UMSK \ - (~(((1U << GLB_WIFI_MAC_CORE_DIV_LEN) - 1) << GLB_WIFI_MAC_CORE_DIV_POS)) + (~(((1 << GLB_WIFI_MAC_CORE_DIV_LEN) - 1) << GLB_WIFI_MAC_CORE_DIV_POS)) #define GLB_WIFI_MAC_WT_DIV GLB_WIFI_MAC_WT_DIV -#define GLB_WIFI_MAC_WT_DIV_POS (4U) -#define GLB_WIFI_MAC_WT_DIV_LEN (4U) +#define GLB_WIFI_MAC_WT_DIV_POS (4) +#define GLB_WIFI_MAC_WT_DIV_LEN (4) #define GLB_WIFI_MAC_WT_DIV_MSK \ - (((1U << GLB_WIFI_MAC_WT_DIV_LEN) - 1) << GLB_WIFI_MAC_WT_DIV_POS) + (((1 << GLB_WIFI_MAC_WT_DIV_LEN) - 1) << GLB_WIFI_MAC_WT_DIV_POS) #define GLB_WIFI_MAC_WT_DIV_UMSK \ - (~(((1U << GLB_WIFI_MAC_WT_DIV_LEN) - 1) << GLB_WIFI_MAC_WT_DIV_POS)) + (~(((1 << GLB_WIFI_MAC_WT_DIV_LEN) - 1) << GLB_WIFI_MAC_WT_DIV_POS)) #define GLB_BLE_CLK_SEL GLB_BLE_CLK_SEL -#define GLB_BLE_CLK_SEL_POS (16U) -#define GLB_BLE_CLK_SEL_LEN (6U) +#define GLB_BLE_CLK_SEL_POS (16) +#define GLB_BLE_CLK_SEL_LEN (6) #define GLB_BLE_CLK_SEL_MSK \ - (((1U << GLB_BLE_CLK_SEL_LEN) - 1) << GLB_BLE_CLK_SEL_POS) + (((1 << GLB_BLE_CLK_SEL_LEN) - 1) << GLB_BLE_CLK_SEL_POS) #define GLB_BLE_CLK_SEL_UMSK \ - (~(((1U << GLB_BLE_CLK_SEL_LEN) - 1) << GLB_BLE_CLK_SEL_POS)) + (~(((1 << GLB_BLE_CLK_SEL_LEN) - 1) << GLB_BLE_CLK_SEL_POS)) #define GLB_BLE_EN GLB_BLE_EN -#define GLB_BLE_EN_POS (24U) -#define GLB_BLE_EN_LEN (1U) -#define GLB_BLE_EN_MSK (((1U << GLB_BLE_EN_LEN) - 1) << GLB_BLE_EN_POS) -#define GLB_BLE_EN_UMSK (~(((1U << GLB_BLE_EN_LEN) - 1) << GLB_BLE_EN_POS)) +#define GLB_BLE_EN_POS (24) +#define GLB_BLE_EN_LEN (1) +#define GLB_BLE_EN_MSK (((1 << GLB_BLE_EN_LEN) - 1) << GLB_BLE_EN_POS) +#define GLB_BLE_EN_UMSK (~(((1 << GLB_BLE_EN_LEN) - 1) << GLB_BLE_EN_POS)) /* 0x8 : clk_cfg2 */ #define GLB_CLK_CFG2_OFFSET (0x8) #define GLB_UART_CLK_DIV GLB_UART_CLK_DIV -#define GLB_UART_CLK_DIV_POS (0U) -#define GLB_UART_CLK_DIV_LEN (3U) +#define GLB_UART_CLK_DIV_POS (0) +#define GLB_UART_CLK_DIV_LEN (3) #define GLB_UART_CLK_DIV_MSK \ - (((1U << GLB_UART_CLK_DIV_LEN) - 1) << GLB_UART_CLK_DIV_POS) + (((1 << GLB_UART_CLK_DIV_LEN) - 1) << GLB_UART_CLK_DIV_POS) #define GLB_UART_CLK_DIV_UMSK \ - (~(((1U << GLB_UART_CLK_DIV_LEN) - 1) << GLB_UART_CLK_DIV_POS)) + (~(((1 << GLB_UART_CLK_DIV_LEN) - 1) << GLB_UART_CLK_DIV_POS)) #define GLB_UART_CLK_EN GLB_UART_CLK_EN -#define GLB_UART_CLK_EN_POS (4U) -#define GLB_UART_CLK_EN_LEN (1U) +#define GLB_UART_CLK_EN_POS (4) +#define GLB_UART_CLK_EN_LEN (1) #define GLB_UART_CLK_EN_MSK \ - (((1U << GLB_UART_CLK_EN_LEN) - 1) << GLB_UART_CLK_EN_POS) + (((1 << GLB_UART_CLK_EN_LEN) - 1) << GLB_UART_CLK_EN_POS) #define GLB_UART_CLK_EN_UMSK \ - (~(((1U << GLB_UART_CLK_EN_LEN) - 1) << GLB_UART_CLK_EN_POS)) + (~(((1 << GLB_UART_CLK_EN_LEN) - 1) << GLB_UART_CLK_EN_POS)) #define GLB_HBN_UART_CLK_SEL GLB_HBN_UART_CLK_SEL -#define GLB_HBN_UART_CLK_SEL_POS (7U) -#define GLB_HBN_UART_CLK_SEL_LEN (1U) +#define GLB_HBN_UART_CLK_SEL_POS (7) +#define GLB_HBN_UART_CLK_SEL_LEN (1) #define GLB_HBN_UART_CLK_SEL_MSK \ - (((1U << GLB_HBN_UART_CLK_SEL_LEN) - 1) << GLB_HBN_UART_CLK_SEL_POS) + (((1 << GLB_HBN_UART_CLK_SEL_LEN) - 1) << GLB_HBN_UART_CLK_SEL_POS) #define GLB_HBN_UART_CLK_SEL_UMSK \ - (~(((1U << GLB_HBN_UART_CLK_SEL_LEN) - 1) << GLB_HBN_UART_CLK_SEL_POS)) + (~(((1 << GLB_HBN_UART_CLK_SEL_LEN) - 1) << GLB_HBN_UART_CLK_SEL_POS)) #define GLB_SF_CLK_DIV GLB_SF_CLK_DIV -#define GLB_SF_CLK_DIV_POS (8U) -#define GLB_SF_CLK_DIV_LEN (3U) +#define GLB_SF_CLK_DIV_POS (8) +#define GLB_SF_CLK_DIV_LEN (3) #define GLB_SF_CLK_DIV_MSK \ - (((1U << GLB_SF_CLK_DIV_LEN) - 1) << GLB_SF_CLK_DIV_POS) + (((1 << GLB_SF_CLK_DIV_LEN) - 1) << GLB_SF_CLK_DIV_POS) #define GLB_SF_CLK_DIV_UMSK \ - (~(((1U << GLB_SF_CLK_DIV_LEN) - 1) << GLB_SF_CLK_DIV_POS)) + (~(((1 << GLB_SF_CLK_DIV_LEN) - 1) << GLB_SF_CLK_DIV_POS)) #define GLB_SF_CLK_EN GLB_SF_CLK_EN -#define GLB_SF_CLK_EN_POS (11U) -#define GLB_SF_CLK_EN_LEN (1U) +#define GLB_SF_CLK_EN_POS (11) +#define GLB_SF_CLK_EN_LEN (1) #define GLB_SF_CLK_EN_MSK \ - (((1U << GLB_SF_CLK_EN_LEN) - 1) << GLB_SF_CLK_EN_POS) + (((1 << GLB_SF_CLK_EN_LEN) - 1) << GLB_SF_CLK_EN_POS) #define GLB_SF_CLK_EN_UMSK \ - (~(((1U << GLB_SF_CLK_EN_LEN) - 1) << GLB_SF_CLK_EN_POS)) + (~(((1 << GLB_SF_CLK_EN_LEN) - 1) << GLB_SF_CLK_EN_POS)) #define GLB_SF_CLK_SEL GLB_SF_CLK_SEL -#define GLB_SF_CLK_SEL_POS (12U) -#define GLB_SF_CLK_SEL_LEN (2U) +#define GLB_SF_CLK_SEL_POS (12) +#define GLB_SF_CLK_SEL_LEN (2) #define GLB_SF_CLK_SEL_MSK \ - (((1U << GLB_SF_CLK_SEL_LEN) - 1) << GLB_SF_CLK_SEL_POS) + (((1 << GLB_SF_CLK_SEL_LEN) - 1) << GLB_SF_CLK_SEL_POS) #define GLB_SF_CLK_SEL_UMSK \ - (~(((1U << GLB_SF_CLK_SEL_LEN) - 1) << GLB_SF_CLK_SEL_POS)) + (~(((1 << GLB_SF_CLK_SEL_LEN) - 1) << GLB_SF_CLK_SEL_POS)) #define GLB_SF_CLK_SEL2 GLB_SF_CLK_SEL2 -#define GLB_SF_CLK_SEL2_POS (14U) -#define GLB_SF_CLK_SEL2_LEN (2U) +#define GLB_SF_CLK_SEL2_POS (14) +#define GLB_SF_CLK_SEL2_LEN (2) #define GLB_SF_CLK_SEL2_MSK \ - (((1U << GLB_SF_CLK_SEL2_LEN) - 1) << GLB_SF_CLK_SEL2_POS) + (((1 << GLB_SF_CLK_SEL2_LEN) - 1) << GLB_SF_CLK_SEL2_POS) #define GLB_SF_CLK_SEL2_UMSK \ - (~(((1U << GLB_SF_CLK_SEL2_LEN) - 1) << GLB_SF_CLK_SEL2_POS)) + (~(((1 << GLB_SF_CLK_SEL2_LEN) - 1) << GLB_SF_CLK_SEL2_POS)) #define GLB_IR_CLK_DIV GLB_IR_CLK_DIV -#define GLB_IR_CLK_DIV_POS (16U) -#define GLB_IR_CLK_DIV_LEN (6U) +#define GLB_IR_CLK_DIV_POS (16) +#define GLB_IR_CLK_DIV_LEN (6) #define GLB_IR_CLK_DIV_MSK \ - (((1U << GLB_IR_CLK_DIV_LEN) - 1) << GLB_IR_CLK_DIV_POS) + (((1 << GLB_IR_CLK_DIV_LEN) - 1) << GLB_IR_CLK_DIV_POS) #define GLB_IR_CLK_DIV_UMSK \ - (~(((1U << GLB_IR_CLK_DIV_LEN) - 1) << GLB_IR_CLK_DIV_POS)) + (~(((1 << GLB_IR_CLK_DIV_LEN) - 1) << GLB_IR_CLK_DIV_POS)) #define GLB_IR_CLK_EN GLB_IR_CLK_EN -#define GLB_IR_CLK_EN_POS (23U) -#define GLB_IR_CLK_EN_LEN (1U) +#define GLB_IR_CLK_EN_POS (23) +#define GLB_IR_CLK_EN_LEN (1) #define GLB_IR_CLK_EN_MSK \ - (((1U << GLB_IR_CLK_EN_LEN) - 1) << GLB_IR_CLK_EN_POS) + (((1 << GLB_IR_CLK_EN_LEN) - 1) << GLB_IR_CLK_EN_POS) #define GLB_IR_CLK_EN_UMSK \ - (~(((1U << GLB_IR_CLK_EN_LEN) - 1) << GLB_IR_CLK_EN_POS)) + (~(((1 << GLB_IR_CLK_EN_LEN) - 1) << GLB_IR_CLK_EN_POS)) #define GLB_DMA_CLK_EN GLB_DMA_CLK_EN -#define GLB_DMA_CLK_EN_POS (24U) -#define GLB_DMA_CLK_EN_LEN (8U) +#define GLB_DMA_CLK_EN_POS (24) +#define GLB_DMA_CLK_EN_LEN (8) #define GLB_DMA_CLK_EN_MSK \ - (((1U << GLB_DMA_CLK_EN_LEN) - 1) << GLB_DMA_CLK_EN_POS) + (((1 << GLB_DMA_CLK_EN_LEN) - 1) << GLB_DMA_CLK_EN_POS) #define GLB_DMA_CLK_EN_UMSK \ - (~(((1U << GLB_DMA_CLK_EN_LEN) - 1) << GLB_DMA_CLK_EN_POS)) + (~(((1 << GLB_DMA_CLK_EN_LEN) - 1) << GLB_DMA_CLK_EN_POS)) /* 0xC : clk_cfg3 */ #define GLB_CLK_CFG3_OFFSET (0xC) #define GLB_SPI_CLK_DIV GLB_SPI_CLK_DIV -#define GLB_SPI_CLK_DIV_POS (0U) -#define GLB_SPI_CLK_DIV_LEN (5U) +#define GLB_SPI_CLK_DIV_POS (0) +#define GLB_SPI_CLK_DIV_LEN (5) #define GLB_SPI_CLK_DIV_MSK \ - (((1U << GLB_SPI_CLK_DIV_LEN) - 1) << GLB_SPI_CLK_DIV_POS) + (((1 << GLB_SPI_CLK_DIV_LEN) - 1) << GLB_SPI_CLK_DIV_POS) #define GLB_SPI_CLK_DIV_UMSK \ - (~(((1U << GLB_SPI_CLK_DIV_LEN) - 1) << GLB_SPI_CLK_DIV_POS)) + (~(((1 << GLB_SPI_CLK_DIV_LEN) - 1) << GLB_SPI_CLK_DIV_POS)) #define GLB_SPI_CLK_EN GLB_SPI_CLK_EN -#define GLB_SPI_CLK_EN_POS (8U) -#define GLB_SPI_CLK_EN_LEN (1U) +#define GLB_SPI_CLK_EN_POS (8) +#define GLB_SPI_CLK_EN_LEN (1) #define GLB_SPI_CLK_EN_MSK \ - (((1U << GLB_SPI_CLK_EN_LEN) - 1) << GLB_SPI_CLK_EN_POS) + (((1 << GLB_SPI_CLK_EN_LEN) - 1) << GLB_SPI_CLK_EN_POS) #define GLB_SPI_CLK_EN_UMSK \ - (~(((1U << GLB_SPI_CLK_EN_LEN) - 1) << GLB_SPI_CLK_EN_POS)) + (~(((1 << GLB_SPI_CLK_EN_LEN) - 1) << GLB_SPI_CLK_EN_POS)) #define GLB_I2C_CLK_DIV GLB_I2C_CLK_DIV -#define GLB_I2C_CLK_DIV_POS (16U) -#define GLB_I2C_CLK_DIV_LEN (8U) +#define GLB_I2C_CLK_DIV_POS (16) +#define GLB_I2C_CLK_DIV_LEN (8) #define GLB_I2C_CLK_DIV_MSK \ - (((1U << GLB_I2C_CLK_DIV_LEN) - 1) << GLB_I2C_CLK_DIV_POS) + (((1 << GLB_I2C_CLK_DIV_LEN) - 1) << GLB_I2C_CLK_DIV_POS) #define GLB_I2C_CLK_DIV_UMSK \ - (~(((1U << GLB_I2C_CLK_DIV_LEN) - 1) << GLB_I2C_CLK_DIV_POS)) + (~(((1 << GLB_I2C_CLK_DIV_LEN) - 1) << GLB_I2C_CLK_DIV_POS)) #define GLB_I2C_CLK_EN GLB_I2C_CLK_EN -#define GLB_I2C_CLK_EN_POS (24U) -#define GLB_I2C_CLK_EN_LEN (1U) +#define GLB_I2C_CLK_EN_POS (24) +#define GLB_I2C_CLK_EN_LEN (1) #define GLB_I2C_CLK_EN_MSK \ - (((1U << GLB_I2C_CLK_EN_LEN) - 1) << GLB_I2C_CLK_EN_POS) + (((1 << GLB_I2C_CLK_EN_LEN) - 1) << GLB_I2C_CLK_EN_POS) #define GLB_I2C_CLK_EN_UMSK \ - (~(((1U << GLB_I2C_CLK_EN_LEN) - 1) << GLB_I2C_CLK_EN_POS)) + (~(((1 << GLB_I2C_CLK_EN_LEN) - 1) << GLB_I2C_CLK_EN_POS)) /* 0x10 : swrst_cfg0 */ #define GLB_SWRST_CFG0_OFFSET (0x10) #define GLB_SWRST_S00 GLB_SWRST_S00 -#define GLB_SWRST_S00_POS (0U) -#define GLB_SWRST_S00_LEN (1U) +#define GLB_SWRST_S00_POS (0) +#define GLB_SWRST_S00_LEN (1) #define GLB_SWRST_S00_MSK \ - (((1U << GLB_SWRST_S00_LEN) - 1) << GLB_SWRST_S00_POS) + (((1 << GLB_SWRST_S00_LEN) - 1) << GLB_SWRST_S00_POS) #define GLB_SWRST_S00_UMSK \ - (~(((1U << GLB_SWRST_S00_LEN) - 1) << GLB_SWRST_S00_POS)) + (~(((1 << GLB_SWRST_S00_LEN) - 1) << GLB_SWRST_S00_POS)) #define GLB_SWRST_S01 GLB_SWRST_S01 -#define GLB_SWRST_S01_POS (1U) -#define GLB_SWRST_S01_LEN (1U) +#define GLB_SWRST_S01_POS (1) +#define GLB_SWRST_S01_LEN (1) #define GLB_SWRST_S01_MSK \ - (((1U << GLB_SWRST_S01_LEN) - 1) << GLB_SWRST_S01_POS) + (((1 << GLB_SWRST_S01_LEN) - 1) << GLB_SWRST_S01_POS) #define GLB_SWRST_S01_UMSK \ - (~(((1U << GLB_SWRST_S01_LEN) - 1) << GLB_SWRST_S01_POS)) + (~(((1 << GLB_SWRST_S01_LEN) - 1) << GLB_SWRST_S01_POS)) #define GLB_SWRST_S20 GLB_SWRST_S20 -#define GLB_SWRST_S20_POS (4U) -#define GLB_SWRST_S20_LEN (1U) +#define GLB_SWRST_S20_POS (4) +#define GLB_SWRST_S20_LEN (1) #define GLB_SWRST_S20_MSK \ - (((1U << GLB_SWRST_S20_LEN) - 1) << GLB_SWRST_S20_POS) + (((1 << GLB_SWRST_S20_LEN) - 1) << GLB_SWRST_S20_POS) #define GLB_SWRST_S20_UMSK \ - (~(((1U << GLB_SWRST_S20_LEN) - 1) << GLB_SWRST_S20_POS)) + (~(((1 << GLB_SWRST_S20_LEN) - 1) << GLB_SWRST_S20_POS)) #define GLB_SWRST_S30 GLB_SWRST_S30 -#define GLB_SWRST_S30_POS (8U) -#define GLB_SWRST_S30_LEN (1U) +#define GLB_SWRST_S30_POS (8) +#define GLB_SWRST_S30_LEN (1) #define GLB_SWRST_S30_MSK \ - (((1U << GLB_SWRST_S30_LEN) - 1) << GLB_SWRST_S30_POS) + (((1 << GLB_SWRST_S30_LEN) - 1) << GLB_SWRST_S30_POS) #define GLB_SWRST_S30_UMSK \ - (~(((1U << GLB_SWRST_S30_LEN) - 1) << GLB_SWRST_S30_POS)) + (~(((1 << GLB_SWRST_S30_LEN) - 1) << GLB_SWRST_S30_POS)) /* 0x14 : swrst_cfg1 */ #define GLB_SWRST_CFG1_OFFSET (0x14) #define GLB_SWRST_S10 GLB_SWRST_S10 -#define GLB_SWRST_S10_POS (0U) -#define GLB_SWRST_S10_LEN (1U) +#define GLB_SWRST_S10_POS (0) +#define GLB_SWRST_S10_LEN (1) #define GLB_SWRST_S10_MSK \ - (((1U << GLB_SWRST_S10_LEN) - 1) << GLB_SWRST_S10_POS) + (((1 << GLB_SWRST_S10_LEN) - 1) << GLB_SWRST_S10_POS) #define GLB_SWRST_S10_UMSK \ - (~(((1U << GLB_SWRST_S10_LEN) - 1) << GLB_SWRST_S10_POS)) + (~(((1 << GLB_SWRST_S10_LEN) - 1) << GLB_SWRST_S10_POS)) #define GLB_SWRST_S11 GLB_SWRST_S11 -#define GLB_SWRST_S11_POS (1U) -#define GLB_SWRST_S11_LEN (1U) +#define GLB_SWRST_S11_POS (1) +#define GLB_SWRST_S11_LEN (1) #define GLB_SWRST_S11_MSK \ - (((1U << GLB_SWRST_S11_LEN) - 1) << GLB_SWRST_S11_POS) + (((1 << GLB_SWRST_S11_LEN) - 1) << GLB_SWRST_S11_POS) #define GLB_SWRST_S11_UMSK \ - (~(((1U << GLB_SWRST_S11_LEN) - 1) << GLB_SWRST_S11_POS)) + (~(((1 << GLB_SWRST_S11_LEN) - 1) << GLB_SWRST_S11_POS)) #define GLB_SWRST_S12 GLB_SWRST_S12 -#define GLB_SWRST_S12_POS (2U) -#define GLB_SWRST_S12_LEN (1U) +#define GLB_SWRST_S12_POS (2) +#define GLB_SWRST_S12_LEN (1) #define GLB_SWRST_S12_MSK \ - (((1U << GLB_SWRST_S12_LEN) - 1) << GLB_SWRST_S12_POS) + (((1 << GLB_SWRST_S12_LEN) - 1) << GLB_SWRST_S12_POS) #define GLB_SWRST_S12_UMSK \ - (~(((1U << GLB_SWRST_S12_LEN) - 1) << GLB_SWRST_S12_POS)) + (~(((1 << GLB_SWRST_S12_LEN) - 1) << GLB_SWRST_S12_POS)) #define GLB_SWRST_S13 GLB_SWRST_S13 -#define GLB_SWRST_S13_POS (3U) -#define GLB_SWRST_S13_LEN (1U) +#define GLB_SWRST_S13_POS (3) +#define GLB_SWRST_S13_LEN (1) #define GLB_SWRST_S13_MSK \ - (((1U << GLB_SWRST_S13_LEN) - 1) << GLB_SWRST_S13_POS) + (((1 << GLB_SWRST_S13_LEN) - 1) << GLB_SWRST_S13_POS) #define GLB_SWRST_S13_UMSK \ - (~(((1U << GLB_SWRST_S13_LEN) - 1) << GLB_SWRST_S13_POS)) + (~(((1 << GLB_SWRST_S13_LEN) - 1) << GLB_SWRST_S13_POS)) #define GLB_SWRST_S14 GLB_SWRST_S14 -#define GLB_SWRST_S14_POS (4U) -#define GLB_SWRST_S14_LEN (1U) +#define GLB_SWRST_S14_POS (4) +#define GLB_SWRST_S14_LEN (1) #define GLB_SWRST_S14_MSK \ - (((1U << GLB_SWRST_S14_LEN) - 1) << GLB_SWRST_S14_POS) + (((1 << GLB_SWRST_S14_LEN) - 1) << GLB_SWRST_S14_POS) #define GLB_SWRST_S14_UMSK \ - (~(((1U << GLB_SWRST_S14_LEN) - 1) << GLB_SWRST_S14_POS)) + (~(((1 << GLB_SWRST_S14_LEN) - 1) << GLB_SWRST_S14_POS)) #define GLB_SWRST_S15 GLB_SWRST_S15 -#define GLB_SWRST_S15_POS (5U) -#define GLB_SWRST_S15_LEN (1U) +#define GLB_SWRST_S15_POS (5) +#define GLB_SWRST_S15_LEN (1) #define GLB_SWRST_S15_MSK \ - (((1U << GLB_SWRST_S15_LEN) - 1) << GLB_SWRST_S15_POS) + (((1 << GLB_SWRST_S15_LEN) - 1) << GLB_SWRST_S15_POS) #define GLB_SWRST_S15_UMSK \ - (~(((1U << GLB_SWRST_S15_LEN) - 1) << GLB_SWRST_S15_POS)) + (~(((1 << GLB_SWRST_S15_LEN) - 1) << GLB_SWRST_S15_POS)) #define GLB_SWRST_S16 GLB_SWRST_S16 -#define GLB_SWRST_S16_POS (6U) -#define GLB_SWRST_S16_LEN (1U) +#define GLB_SWRST_S16_POS (6) +#define GLB_SWRST_S16_LEN (1) #define GLB_SWRST_S16_MSK \ - (((1U << GLB_SWRST_S16_LEN) - 1) << GLB_SWRST_S16_POS) + (((1 << GLB_SWRST_S16_LEN) - 1) << GLB_SWRST_S16_POS) #define GLB_SWRST_S16_UMSK \ - (~(((1U << GLB_SWRST_S16_LEN) - 1) << GLB_SWRST_S16_POS)) + (~(((1 << GLB_SWRST_S16_LEN) - 1) << GLB_SWRST_S16_POS)) #define GLB_SWRST_S17 GLB_SWRST_S17 -#define GLB_SWRST_S17_POS (7U) -#define GLB_SWRST_S17_LEN (1U) +#define GLB_SWRST_S17_POS (7) +#define GLB_SWRST_S17_LEN (1) #define GLB_SWRST_S17_MSK \ - (((1U << GLB_SWRST_S17_LEN) - 1) << GLB_SWRST_S17_POS) + (((1 << GLB_SWRST_S17_LEN) - 1) << GLB_SWRST_S17_POS) #define GLB_SWRST_S17_UMSK \ - (~(((1U << GLB_SWRST_S17_LEN) - 1) << GLB_SWRST_S17_POS)) + (~(((1 << GLB_SWRST_S17_LEN) - 1) << GLB_SWRST_S17_POS)) #define GLB_SWRST_S18 GLB_SWRST_S18 -#define GLB_SWRST_S18_POS (8U) -#define GLB_SWRST_S18_LEN (1U) +#define GLB_SWRST_S18_POS (8) +#define GLB_SWRST_S18_LEN (1) #define GLB_SWRST_S18_MSK \ - (((1U << GLB_SWRST_S18_LEN) - 1) << GLB_SWRST_S18_POS) + (((1 << GLB_SWRST_S18_LEN) - 1) << GLB_SWRST_S18_POS) #define GLB_SWRST_S18_UMSK \ - (~(((1U << GLB_SWRST_S18_LEN) - 1) << GLB_SWRST_S18_POS)) + (~(((1 << GLB_SWRST_S18_LEN) - 1) << GLB_SWRST_S18_POS)) #define GLB_SWRST_S19 GLB_SWRST_S19 -#define GLB_SWRST_S19_POS (9U) -#define GLB_SWRST_S19_LEN (1U) +#define GLB_SWRST_S19_POS (9) +#define GLB_SWRST_S19_LEN (1) #define GLB_SWRST_S19_MSK \ - (((1U << GLB_SWRST_S19_LEN) - 1) << GLB_SWRST_S19_POS) + (((1 << GLB_SWRST_S19_LEN) - 1) << GLB_SWRST_S19_POS) #define GLB_SWRST_S19_UMSK \ - (~(((1U << GLB_SWRST_S19_LEN) - 1) << GLB_SWRST_S19_POS)) + (~(((1 << GLB_SWRST_S19_LEN) - 1) << GLB_SWRST_S19_POS)) #define GLB_SWRST_S1A GLB_SWRST_S1A -#define GLB_SWRST_S1A_POS (10U) -#define GLB_SWRST_S1A_LEN (1U) +#define GLB_SWRST_S1A_POS (10) +#define GLB_SWRST_S1A_LEN (1) #define GLB_SWRST_S1A_MSK \ - (((1U << GLB_SWRST_S1A_LEN) - 1) << GLB_SWRST_S1A_POS) + (((1 << GLB_SWRST_S1A_LEN) - 1) << GLB_SWRST_S1A_POS) #define GLB_SWRST_S1A_UMSK \ - (~(((1U << GLB_SWRST_S1A_LEN) - 1) << GLB_SWRST_S1A_POS)) + (~(((1 << GLB_SWRST_S1A_LEN) - 1) << GLB_SWRST_S1A_POS)) #define GLB_SWRST_S1B GLB_SWRST_S1B -#define GLB_SWRST_S1B_POS (11U) -#define GLB_SWRST_S1B_LEN (1U) +#define GLB_SWRST_S1B_POS (11) +#define GLB_SWRST_S1B_LEN (1) #define GLB_SWRST_S1B_MSK \ - (((1U << GLB_SWRST_S1B_LEN) - 1) << GLB_SWRST_S1B_POS) + (((1 << GLB_SWRST_S1B_LEN) - 1) << GLB_SWRST_S1B_POS) #define GLB_SWRST_S1B_UMSK \ - (~(((1U << GLB_SWRST_S1B_LEN) - 1) << GLB_SWRST_S1B_POS)) + (~(((1 << GLB_SWRST_S1B_LEN) - 1) << GLB_SWRST_S1B_POS)) #define GLB_SWRST_S1C GLB_SWRST_S1C -#define GLB_SWRST_S1C_POS (12U) -#define GLB_SWRST_S1C_LEN (1U) +#define GLB_SWRST_S1C_POS (12) +#define GLB_SWRST_S1C_LEN (1) #define GLB_SWRST_S1C_MSK \ - (((1U << GLB_SWRST_S1C_LEN) - 1) << GLB_SWRST_S1C_POS) + (((1 << GLB_SWRST_S1C_LEN) - 1) << GLB_SWRST_S1C_POS) #define GLB_SWRST_S1C_UMSK \ - (~(((1U << GLB_SWRST_S1C_LEN) - 1) << GLB_SWRST_S1C_POS)) + (~(((1 << GLB_SWRST_S1C_LEN) - 1) << GLB_SWRST_S1C_POS)) #define GLB_SWRST_S1D GLB_SWRST_S1D -#define GLB_SWRST_S1D_POS (13U) -#define GLB_SWRST_S1D_LEN (1U) +#define GLB_SWRST_S1D_POS (13) +#define GLB_SWRST_S1D_LEN (1) #define GLB_SWRST_S1D_MSK \ - (((1U << GLB_SWRST_S1D_LEN) - 1) << GLB_SWRST_S1D_POS) + (((1 << GLB_SWRST_S1D_LEN) - 1) << GLB_SWRST_S1D_POS) #define GLB_SWRST_S1D_UMSK \ - (~(((1U << GLB_SWRST_S1D_LEN) - 1) << GLB_SWRST_S1D_POS)) + (~(((1 << GLB_SWRST_S1D_LEN) - 1) << GLB_SWRST_S1D_POS)) #define GLB_SWRST_S1E GLB_SWRST_S1E -#define GLB_SWRST_S1E_POS (14U) -#define GLB_SWRST_S1E_LEN (1U) +#define GLB_SWRST_S1E_POS (14) +#define GLB_SWRST_S1E_LEN (1) #define GLB_SWRST_S1E_MSK \ - (((1U << GLB_SWRST_S1E_LEN) - 1) << GLB_SWRST_S1E_POS) + (((1 << GLB_SWRST_S1E_LEN) - 1) << GLB_SWRST_S1E_POS) #define GLB_SWRST_S1E_UMSK \ - (~(((1U << GLB_SWRST_S1E_LEN) - 1) << GLB_SWRST_S1E_POS)) + (~(((1 << GLB_SWRST_S1E_LEN) - 1) << GLB_SWRST_S1E_POS)) #define GLB_SWRST_S1F GLB_SWRST_S1F -#define GLB_SWRST_S1F_POS (15U) -#define GLB_SWRST_S1F_LEN (1U) +#define GLB_SWRST_S1F_POS (15) +#define GLB_SWRST_S1F_LEN (1) #define GLB_SWRST_S1F_MSK \ - (((1U << GLB_SWRST_S1F_LEN) - 1) << GLB_SWRST_S1F_POS) + (((1 << GLB_SWRST_S1F_LEN) - 1) << GLB_SWRST_S1F_POS) #define GLB_SWRST_S1F_UMSK \ - (~(((1U << GLB_SWRST_S1F_LEN) - 1) << GLB_SWRST_S1F_POS)) + (~(((1 << GLB_SWRST_S1F_LEN) - 1) << GLB_SWRST_S1F_POS)) #define GLB_SWRST_S1A0 GLB_SWRST_S1A0 -#define GLB_SWRST_S1A0_POS (16U) -#define GLB_SWRST_S1A0_LEN (1U) +#define GLB_SWRST_S1A0_POS (16) +#define GLB_SWRST_S1A0_LEN (1) #define GLB_SWRST_S1A0_MSK \ - (((1U << GLB_SWRST_S1A0_LEN) - 1) << GLB_SWRST_S1A0_POS) + (((1 << GLB_SWRST_S1A0_LEN) - 1) << GLB_SWRST_S1A0_POS) #define GLB_SWRST_S1A0_UMSK \ - (~(((1U << GLB_SWRST_S1A0_LEN) - 1) << GLB_SWRST_S1A0_POS)) + (~(((1 << GLB_SWRST_S1A0_LEN) - 1) << GLB_SWRST_S1A0_POS)) #define GLB_SWRST_S1A1 GLB_SWRST_S1A1 -#define GLB_SWRST_S1A1_POS (17U) -#define GLB_SWRST_S1A1_LEN (1U) +#define GLB_SWRST_S1A1_POS (17) +#define GLB_SWRST_S1A1_LEN (1) #define GLB_SWRST_S1A1_MSK \ - (((1U << GLB_SWRST_S1A1_LEN) - 1) << GLB_SWRST_S1A1_POS) + (((1 << GLB_SWRST_S1A1_LEN) - 1) << GLB_SWRST_S1A1_POS) #define GLB_SWRST_S1A1_UMSK \ - (~(((1U << GLB_SWRST_S1A1_LEN) - 1) << GLB_SWRST_S1A1_POS)) + (~(((1 << GLB_SWRST_S1A1_LEN) - 1) << GLB_SWRST_S1A1_POS)) #define GLB_SWRST_S1A2 GLB_SWRST_S1A2 -#define GLB_SWRST_S1A2_POS (18U) -#define GLB_SWRST_S1A2_LEN (1U) +#define GLB_SWRST_S1A2_POS (18) +#define GLB_SWRST_S1A2_LEN (1) #define GLB_SWRST_S1A2_MSK \ - (((1U << GLB_SWRST_S1A2_LEN) - 1) << GLB_SWRST_S1A2_POS) + (((1 << GLB_SWRST_S1A2_LEN) - 1) << GLB_SWRST_S1A2_POS) #define GLB_SWRST_S1A2_UMSK \ - (~(((1U << GLB_SWRST_S1A2_LEN) - 1) << GLB_SWRST_S1A2_POS)) + (~(((1 << GLB_SWRST_S1A2_LEN) - 1) << GLB_SWRST_S1A2_POS)) #define GLB_SWRST_S1A3 GLB_SWRST_S1A3 -#define GLB_SWRST_S1A3_POS (19U) -#define GLB_SWRST_S1A3_LEN (1U) +#define GLB_SWRST_S1A3_POS (19) +#define GLB_SWRST_S1A3_LEN (1) #define GLB_SWRST_S1A3_MSK \ - (((1U << GLB_SWRST_S1A3_LEN) - 1) << GLB_SWRST_S1A3_POS) + (((1 << GLB_SWRST_S1A3_LEN) - 1) << GLB_SWRST_S1A3_POS) #define GLB_SWRST_S1A3_UMSK \ - (~(((1U << GLB_SWRST_S1A3_LEN) - 1) << GLB_SWRST_S1A3_POS)) + (~(((1 << GLB_SWRST_S1A3_LEN) - 1) << GLB_SWRST_S1A3_POS)) #define GLB_SWRST_S1A4 GLB_SWRST_S1A4 -#define GLB_SWRST_S1A4_POS (20U) -#define GLB_SWRST_S1A4_LEN (1U) +#define GLB_SWRST_S1A4_POS (20) +#define GLB_SWRST_S1A4_LEN (1) #define GLB_SWRST_S1A4_MSK \ - (((1U << GLB_SWRST_S1A4_LEN) - 1) << GLB_SWRST_S1A4_POS) + (((1 << GLB_SWRST_S1A4_LEN) - 1) << GLB_SWRST_S1A4_POS) #define GLB_SWRST_S1A4_UMSK \ - (~(((1U << GLB_SWRST_S1A4_LEN) - 1) << GLB_SWRST_S1A4_POS)) + (~(((1 << GLB_SWRST_S1A4_LEN) - 1) << GLB_SWRST_S1A4_POS)) #define GLB_SWRST_S1A5 GLB_SWRST_S1A5 -#define GLB_SWRST_S1A5_POS (21U) -#define GLB_SWRST_S1A5_LEN (1U) +#define GLB_SWRST_S1A5_POS (21) +#define GLB_SWRST_S1A5_LEN (1) #define GLB_SWRST_S1A5_MSK \ - (((1U << GLB_SWRST_S1A5_LEN) - 1) << GLB_SWRST_S1A5_POS) + (((1 << GLB_SWRST_S1A5_LEN) - 1) << GLB_SWRST_S1A5_POS) #define GLB_SWRST_S1A5_UMSK \ - (~(((1U << GLB_SWRST_S1A5_LEN) - 1) << GLB_SWRST_S1A5_POS)) + (~(((1 << GLB_SWRST_S1A5_LEN) - 1) << GLB_SWRST_S1A5_POS)) #define GLB_SWRST_S1A6 GLB_SWRST_S1A6 -#define GLB_SWRST_S1A6_POS (22U) -#define GLB_SWRST_S1A6_LEN (1U) +#define GLB_SWRST_S1A6_POS (22) +#define GLB_SWRST_S1A6_LEN (1) #define GLB_SWRST_S1A6_MSK \ - (((1U << GLB_SWRST_S1A6_LEN) - 1) << GLB_SWRST_S1A6_POS) + (((1 << GLB_SWRST_S1A6_LEN) - 1) << GLB_SWRST_S1A6_POS) #define GLB_SWRST_S1A6_UMSK \ - (~(((1U << GLB_SWRST_S1A6_LEN) - 1) << GLB_SWRST_S1A6_POS)) + (~(((1 << GLB_SWRST_S1A6_LEN) - 1) << GLB_SWRST_S1A6_POS)) #define GLB_SWRST_S1A7 GLB_SWRST_S1A7 -#define GLB_SWRST_S1A7_POS (23U) -#define GLB_SWRST_S1A7_LEN (1U) +#define GLB_SWRST_S1A7_POS (23) +#define GLB_SWRST_S1A7_LEN (1) #define GLB_SWRST_S1A7_MSK \ - (((1U << GLB_SWRST_S1A7_LEN) - 1) << GLB_SWRST_S1A7_POS) + (((1 << GLB_SWRST_S1A7_LEN) - 1) << GLB_SWRST_S1A7_POS) #define GLB_SWRST_S1A7_UMSK \ - (~(((1U << GLB_SWRST_S1A7_LEN) - 1) << GLB_SWRST_S1A7_POS)) + (~(((1 << GLB_SWRST_S1A7_LEN) - 1) << GLB_SWRST_S1A7_POS)) /* 0x18 : swrst_cfg2 */ #define GLB_SWRST_CFG2_OFFSET (0x18) #define GLB_REG_CTRL_PWRON_RST GLB_REG_CTRL_PWRON_RST -#define GLB_REG_CTRL_PWRON_RST_POS (0U) -#define GLB_REG_CTRL_PWRON_RST_LEN (1U) +#define GLB_REG_CTRL_PWRON_RST_POS (0) +#define GLB_REG_CTRL_PWRON_RST_LEN (1) #define GLB_REG_CTRL_PWRON_RST_MSK \ - (((1U << GLB_REG_CTRL_PWRON_RST_LEN) - 1) << GLB_REG_CTRL_PWRON_RST_POS) + (((1 << GLB_REG_CTRL_PWRON_RST_LEN) - 1) << GLB_REG_CTRL_PWRON_RST_POS) #define GLB_REG_CTRL_PWRON_RST_UMSK \ - (~(((1U << GLB_REG_CTRL_PWRON_RST_LEN) - 1) << GLB_REG_CTRL_PWRON_RST_POS)) + (~(((1 << GLB_REG_CTRL_PWRON_RST_LEN) - 1) << GLB_REG_CTRL_PWRON_RST_POS)) #define GLB_REG_CTRL_CPU_RESET GLB_REG_CTRL_CPU_RESET -#define GLB_REG_CTRL_CPU_RESET_POS (1U) -#define GLB_REG_CTRL_CPU_RESET_LEN (1U) +#define GLB_REG_CTRL_CPU_RESET_POS (1) +#define GLB_REG_CTRL_CPU_RESET_LEN (1) #define GLB_REG_CTRL_CPU_RESET_MSK \ - (((1U << GLB_REG_CTRL_CPU_RESET_LEN) - 1) << GLB_REG_CTRL_CPU_RESET_POS) + (((1 << GLB_REG_CTRL_CPU_RESET_LEN) - 1) << GLB_REG_CTRL_CPU_RESET_POS) #define GLB_REG_CTRL_CPU_RESET_UMSK \ - (~(((1U << GLB_REG_CTRL_CPU_RESET_LEN) - 1) << GLB_REG_CTRL_CPU_RESET_POS)) + (~(((1 << GLB_REG_CTRL_CPU_RESET_LEN) - 1) << GLB_REG_CTRL_CPU_RESET_POS)) #define GLB_REG_CTRL_SYS_RESET GLB_REG_CTRL_SYS_RESET -#define GLB_REG_CTRL_SYS_RESET_POS (2U) -#define GLB_REG_CTRL_SYS_RESET_LEN (1U) +#define GLB_REG_CTRL_SYS_RESET_POS (2) +#define GLB_REG_CTRL_SYS_RESET_LEN (1) #define GLB_REG_CTRL_SYS_RESET_MSK \ - (((1U << GLB_REG_CTRL_SYS_RESET_LEN) - 1) << GLB_REG_CTRL_SYS_RESET_POS) + (((1 << GLB_REG_CTRL_SYS_RESET_LEN) - 1) << GLB_REG_CTRL_SYS_RESET_POS) #define GLB_REG_CTRL_SYS_RESET_UMSK \ - (~(((1U << GLB_REG_CTRL_SYS_RESET_LEN) - 1) << GLB_REG_CTRL_SYS_RESET_POS)) + (~(((1 << GLB_REG_CTRL_SYS_RESET_LEN) - 1) << GLB_REG_CTRL_SYS_RESET_POS)) #define GLB_REG_CTRL_RESET_DUMMY GLB_REG_CTRL_RESET_DUMMY -#define GLB_REG_CTRL_RESET_DUMMY_POS (4U) -#define GLB_REG_CTRL_RESET_DUMMY_LEN (4U) +#define GLB_REG_CTRL_RESET_DUMMY_POS (4) +#define GLB_REG_CTRL_RESET_DUMMY_LEN (4) #define GLB_REG_CTRL_RESET_DUMMY_MSK \ - (((1U << GLB_REG_CTRL_RESET_DUMMY_LEN) - 1) << GLB_REG_CTRL_RESET_DUMMY_POS) + (((1 << GLB_REG_CTRL_RESET_DUMMY_LEN) - 1) << GLB_REG_CTRL_RESET_DUMMY_POS) #define GLB_REG_CTRL_RESET_DUMMY_UMSK \ - (~(((1U << GLB_REG_CTRL_RESET_DUMMY_LEN) - 1) \ + (~(((1 << GLB_REG_CTRL_RESET_DUMMY_LEN) - 1) \ << GLB_REG_CTRL_RESET_DUMMY_POS)) #define GLB_PKA_CLK_SEL GLB_PKA_CLK_SEL -#define GLB_PKA_CLK_SEL_POS (24U) -#define GLB_PKA_CLK_SEL_LEN (1U) +#define GLB_PKA_CLK_SEL_POS (24) +#define GLB_PKA_CLK_SEL_LEN (1) #define GLB_PKA_CLK_SEL_MSK \ - (((1U << GLB_PKA_CLK_SEL_LEN) - 1) << GLB_PKA_CLK_SEL_POS) + (((1 << GLB_PKA_CLK_SEL_LEN) - 1) << GLB_PKA_CLK_SEL_POS) #define GLB_PKA_CLK_SEL_UMSK \ - (~(((1U << GLB_PKA_CLK_SEL_LEN) - 1) << GLB_PKA_CLK_SEL_POS)) + (~(((1 << GLB_PKA_CLK_SEL_LEN) - 1) << GLB_PKA_CLK_SEL_POS)) /* 0x1C : swrst_cfg3 */ @@ -497,39 +500,39 @@ #define GLB_CGEN_CFG0_OFFSET (0x20) #define GLB_CGEN_M GLB_CGEN_M -#define GLB_CGEN_M_POS (0U) -#define GLB_CGEN_M_LEN (8U) -#define GLB_CGEN_M_MSK (((1U << GLB_CGEN_M_LEN) - 1) << GLB_CGEN_M_POS) -#define GLB_CGEN_M_UMSK (~(((1U << GLB_CGEN_M_LEN) - 1) << GLB_CGEN_M_POS)) +#define GLB_CGEN_M_POS (0) +#define GLB_CGEN_M_LEN (8) +#define GLB_CGEN_M_MSK (((1 << GLB_CGEN_M_LEN) - 1) << GLB_CGEN_M_POS) +#define GLB_CGEN_M_UMSK (~(((1 << GLB_CGEN_M_LEN) - 1) << GLB_CGEN_M_POS)) /* 0x24 : cgen_cfg1 */ #define GLB_CGEN_CFG1_OFFSET (0x24) #define GLB_CGEN_S1 GLB_CGEN_S1 -#define GLB_CGEN_S1_POS (0U) -#define GLB_CGEN_S1_LEN (16U) -#define GLB_CGEN_S1_MSK (((1U << GLB_CGEN_S1_LEN) - 1) << GLB_CGEN_S1_POS) -#define GLB_CGEN_S1_UMSK (~(((1U << GLB_CGEN_S1_LEN) - 1) << GLB_CGEN_S1_POS)) +#define GLB_CGEN_S1_POS (0) +#define GLB_CGEN_S1_LEN (16) +#define GLB_CGEN_S1_MSK (((1 << GLB_CGEN_S1_LEN) - 1) << GLB_CGEN_S1_POS) +#define GLB_CGEN_S1_UMSK (~(((1 << GLB_CGEN_S1_LEN) - 1) << GLB_CGEN_S1_POS)) #define GLB_CGEN_S1A GLB_CGEN_S1A -#define GLB_CGEN_S1A_POS (16U) -#define GLB_CGEN_S1A_LEN (8U) -#define GLB_CGEN_S1A_MSK (((1U << GLB_CGEN_S1A_LEN) - 1) << GLB_CGEN_S1A_POS) +#define GLB_CGEN_S1A_POS (16) +#define GLB_CGEN_S1A_LEN (8) +#define GLB_CGEN_S1A_MSK (((1 << GLB_CGEN_S1A_LEN) - 1) << GLB_CGEN_S1A_POS) #define GLB_CGEN_S1A_UMSK \ - (~(((1U << GLB_CGEN_S1A_LEN) - 1) << GLB_CGEN_S1A_POS)) + (~(((1 << GLB_CGEN_S1A_LEN) - 1) << GLB_CGEN_S1A_POS)) /* 0x28 : cgen_cfg2 */ #define GLB_CGEN_CFG2_OFFSET (0x28) #define GLB_CGEN_S2 GLB_CGEN_S2 -#define GLB_CGEN_S2_POS (0U) -#define GLB_CGEN_S2_LEN (1U) -#define GLB_CGEN_S2_MSK (((1U << GLB_CGEN_S2_LEN) - 1) << GLB_CGEN_S2_POS) -#define GLB_CGEN_S2_UMSK (~(((1U << GLB_CGEN_S2_LEN) - 1) << GLB_CGEN_S2_POS)) +#define GLB_CGEN_S2_POS (0) +#define GLB_CGEN_S2_LEN (1) +#define GLB_CGEN_S2_MSK (((1 << GLB_CGEN_S2_LEN) - 1) << GLB_CGEN_S2_POS) +#define GLB_CGEN_S2_UMSK (~(((1 << GLB_CGEN_S2_LEN) - 1) << GLB_CGEN_S2_POS)) #define GLB_CGEN_S3 GLB_CGEN_S3 -#define GLB_CGEN_S3_POS (4U) -#define GLB_CGEN_S3_LEN (1U) -#define GLB_CGEN_S3_MSK (((1U << GLB_CGEN_S3_LEN) - 1) << GLB_CGEN_S3_POS) -#define GLB_CGEN_S3_UMSK (~(((1U << GLB_CGEN_S3_LEN) - 1) << GLB_CGEN_S3_POS)) +#define GLB_CGEN_S3_POS (4) +#define GLB_CGEN_S3_LEN (1) +#define GLB_CGEN_S3_MSK (((1 << GLB_CGEN_S3_LEN) - 1) << GLB_CGEN_S3_POS) +#define GLB_CGEN_S3_UMSK (~(((1 << GLB_CGEN_S3_LEN) - 1) << GLB_CGEN_S3_POS)) /* 0x2C : cgen_cfg3 */ @@ -539,236 +542,235 @@ #define GLB_MBIST_CTL_OFFSET (0x30) #define GLB_IROM_MBIST_MODE GLB_IROM_MBIST_MODE -#define GLB_IROM_MBIST_MODE_POS (0U) -#define GLB_IROM_MBIST_MODE_LEN (1U) +#define GLB_IROM_MBIST_MODE_POS (0) +#define GLB_IROM_MBIST_MODE_LEN (1) #define GLB_IROM_MBIST_MODE_MSK \ - (((1U << GLB_IROM_MBIST_MODE_LEN) - 1) << GLB_IROM_MBIST_MODE_POS) + (((1 << GLB_IROM_MBIST_MODE_LEN) - 1) << GLB_IROM_MBIST_MODE_POS) #define GLB_IROM_MBIST_MODE_UMSK \ - (~(((1U << GLB_IROM_MBIST_MODE_LEN) - 1) << GLB_IROM_MBIST_MODE_POS)) + (~(((1 << GLB_IROM_MBIST_MODE_LEN) - 1) << GLB_IROM_MBIST_MODE_POS)) #define GLB_HSRAM_MBIST_MODE GLB_HSRAM_MBIST_MODE -#define GLB_HSRAM_MBIST_MODE_POS (1U) -#define GLB_HSRAM_MBIST_MODE_LEN (1U) +#define GLB_HSRAM_MBIST_MODE_POS (1) +#define GLB_HSRAM_MBIST_MODE_LEN (1) #define GLB_HSRAM_MBIST_MODE_MSK \ - (((1U << GLB_HSRAM_MBIST_MODE_LEN) - 1) << GLB_HSRAM_MBIST_MODE_POS) + (((1 << GLB_HSRAM_MBIST_MODE_LEN) - 1) << GLB_HSRAM_MBIST_MODE_POS) #define GLB_HSRAM_MBIST_MODE_UMSK \ - (~(((1U << GLB_HSRAM_MBIST_MODE_LEN) - 1) << GLB_HSRAM_MBIST_MODE_POS)) + (~(((1 << GLB_HSRAM_MBIST_MODE_LEN) - 1) << GLB_HSRAM_MBIST_MODE_POS)) #define GLB_TAG_MBIST_MODE GLB_TAG_MBIST_MODE -#define GLB_TAG_MBIST_MODE_POS (2U) -#define GLB_TAG_MBIST_MODE_LEN (1U) +#define GLB_TAG_MBIST_MODE_POS (2) +#define GLB_TAG_MBIST_MODE_LEN (1) #define GLB_TAG_MBIST_MODE_MSK \ - (((1U << GLB_TAG_MBIST_MODE_LEN) - 1) << GLB_TAG_MBIST_MODE_POS) + (((1 << GLB_TAG_MBIST_MODE_LEN) - 1) << GLB_TAG_MBIST_MODE_POS) #define GLB_TAG_MBIST_MODE_UMSK \ - (~(((1U << GLB_TAG_MBIST_MODE_LEN) - 1) << GLB_TAG_MBIST_MODE_POS)) + (~(((1 << GLB_TAG_MBIST_MODE_LEN) - 1) << GLB_TAG_MBIST_MODE_POS)) #define GLB_OCRAM_MBIST_MODE GLB_OCRAM_MBIST_MODE -#define GLB_OCRAM_MBIST_MODE_POS (3U) -#define GLB_OCRAM_MBIST_MODE_LEN (1U) +#define GLB_OCRAM_MBIST_MODE_POS (3) +#define GLB_OCRAM_MBIST_MODE_LEN (1) #define GLB_OCRAM_MBIST_MODE_MSK \ - (((1U << GLB_OCRAM_MBIST_MODE_LEN) - 1) << GLB_OCRAM_MBIST_MODE_POS) + (((1 << GLB_OCRAM_MBIST_MODE_LEN) - 1) << GLB_OCRAM_MBIST_MODE_POS) #define GLB_OCRAM_MBIST_MODE_UMSK \ - (~(((1U << GLB_OCRAM_MBIST_MODE_LEN) - 1) << GLB_OCRAM_MBIST_MODE_POS)) + (~(((1 << GLB_OCRAM_MBIST_MODE_LEN) - 1) << GLB_OCRAM_MBIST_MODE_POS)) #define GLB_WIFI_MBIST_MODE GLB_WIFI_MBIST_MODE -#define GLB_WIFI_MBIST_MODE_POS (4U) -#define GLB_WIFI_MBIST_MODE_LEN (1U) +#define GLB_WIFI_MBIST_MODE_POS (4) +#define GLB_WIFI_MBIST_MODE_LEN (1) #define GLB_WIFI_MBIST_MODE_MSK \ - (((1U << GLB_WIFI_MBIST_MODE_LEN) - 1) << GLB_WIFI_MBIST_MODE_POS) + (((1 << GLB_WIFI_MBIST_MODE_LEN) - 1) << GLB_WIFI_MBIST_MODE_POS) #define GLB_WIFI_MBIST_MODE_UMSK \ - (~(((1U << GLB_WIFI_MBIST_MODE_LEN) - 1) << GLB_WIFI_MBIST_MODE_POS)) + (~(((1 << GLB_WIFI_MBIST_MODE_LEN) - 1) << GLB_WIFI_MBIST_MODE_POS)) #define GLB_REG_MBIST_RST_N GLB_REG_MBIST_RST_N -#define GLB_REG_MBIST_RST_N_POS (31U) -#define GLB_REG_MBIST_RST_N_LEN (1U) +#define GLB_REG_MBIST_RST_N_POS (31) +#define GLB_REG_MBIST_RST_N_LEN (1) #define GLB_REG_MBIST_RST_N_MSK \ - (((1U << GLB_REG_MBIST_RST_N_LEN) - 1) << GLB_REG_MBIST_RST_N_POS) + (((1 << GLB_REG_MBIST_RST_N_LEN) - 1) << GLB_REG_MBIST_RST_N_POS) #define GLB_REG_MBIST_RST_N_UMSK \ - (~(((1U << GLB_REG_MBIST_RST_N_LEN) - 1) << GLB_REG_MBIST_RST_N_POS)) + (~(((1 << GLB_REG_MBIST_RST_N_LEN) - 1) << GLB_REG_MBIST_RST_N_POS)) /* 0x34 : MBIST_STAT */ #define GLB_MBIST_STAT_OFFSET (0x34) #define GLB_IROM_MBIST_DONE GLB_IROM_MBIST_DONE -#define GLB_IROM_MBIST_DONE_POS (0U) -#define GLB_IROM_MBIST_DONE_LEN (1U) +#define GLB_IROM_MBIST_DONE_POS (0) +#define GLB_IROM_MBIST_DONE_LEN (1) #define GLB_IROM_MBIST_DONE_MSK \ - (((1U << GLB_IROM_MBIST_DONE_LEN) - 1) << GLB_IROM_MBIST_DONE_POS) + (((1 << GLB_IROM_MBIST_DONE_LEN) - 1) << GLB_IROM_MBIST_DONE_POS) #define GLB_IROM_MBIST_DONE_UMSK \ - (~(((1U << GLB_IROM_MBIST_DONE_LEN) - 1) << GLB_IROM_MBIST_DONE_POS)) + (~(((1 << GLB_IROM_MBIST_DONE_LEN) - 1) << GLB_IROM_MBIST_DONE_POS)) #define GLB_HSRAM_MBIST_DONE GLB_HSRAM_MBIST_DONE -#define GLB_HSRAM_MBIST_DONE_POS (1U) -#define GLB_HSRAM_MBIST_DONE_LEN (1U) +#define GLB_HSRAM_MBIST_DONE_POS (1) +#define GLB_HSRAM_MBIST_DONE_LEN (1) #define GLB_HSRAM_MBIST_DONE_MSK \ - (((1U << GLB_HSRAM_MBIST_DONE_LEN) - 1) << GLB_HSRAM_MBIST_DONE_POS) + (((1 << GLB_HSRAM_MBIST_DONE_LEN) - 1) << GLB_HSRAM_MBIST_DONE_POS) #define GLB_HSRAM_MBIST_DONE_UMSK \ - (~(((1U << GLB_HSRAM_MBIST_DONE_LEN) - 1) << GLB_HSRAM_MBIST_DONE_POS)) + (~(((1 << GLB_HSRAM_MBIST_DONE_LEN) - 1) << GLB_HSRAM_MBIST_DONE_POS)) #define GLB_TAG_MBIST_DONE GLB_TAG_MBIST_DONE -#define GLB_TAG_MBIST_DONE_POS (2U) -#define GLB_TAG_MBIST_DONE_LEN (1U) +#define GLB_TAG_MBIST_DONE_POS (2) +#define GLB_TAG_MBIST_DONE_LEN (1) #define GLB_TAG_MBIST_DONE_MSK \ - (((1U << GLB_TAG_MBIST_DONE_LEN) - 1) << GLB_TAG_MBIST_DONE_POS) + (((1 << GLB_TAG_MBIST_DONE_LEN) - 1) << GLB_TAG_MBIST_DONE_POS) #define GLB_TAG_MBIST_DONE_UMSK \ - (~(((1U << GLB_TAG_MBIST_DONE_LEN) - 1) << GLB_TAG_MBIST_DONE_POS)) + (~(((1 << GLB_TAG_MBIST_DONE_LEN) - 1) << GLB_TAG_MBIST_DONE_POS)) #define GLB_OCRAM_MBIST_DONE GLB_OCRAM_MBIST_DONE -#define GLB_OCRAM_MBIST_DONE_POS (3U) -#define GLB_OCRAM_MBIST_DONE_LEN (1U) +#define GLB_OCRAM_MBIST_DONE_POS (3) +#define GLB_OCRAM_MBIST_DONE_LEN (1) #define GLB_OCRAM_MBIST_DONE_MSK \ - (((1U << GLB_OCRAM_MBIST_DONE_LEN) - 1) << GLB_OCRAM_MBIST_DONE_POS) + (((1 << GLB_OCRAM_MBIST_DONE_LEN) - 1) << GLB_OCRAM_MBIST_DONE_POS) #define GLB_OCRAM_MBIST_DONE_UMSK \ - (~(((1U << GLB_OCRAM_MBIST_DONE_LEN) - 1) << GLB_OCRAM_MBIST_DONE_POS)) + (~(((1 << GLB_OCRAM_MBIST_DONE_LEN) - 1) << GLB_OCRAM_MBIST_DONE_POS)) #define GLB_WIFI_MBIST_DONE GLB_WIFI_MBIST_DONE -#define GLB_WIFI_MBIST_DONE_POS (4U) -#define GLB_WIFI_MBIST_DONE_LEN (1U) +#define GLB_WIFI_MBIST_DONE_POS (4) +#define GLB_WIFI_MBIST_DONE_LEN (1) #define GLB_WIFI_MBIST_DONE_MSK \ - (((1U << GLB_WIFI_MBIST_DONE_LEN) - 1) << GLB_WIFI_MBIST_DONE_POS) + (((1 << GLB_WIFI_MBIST_DONE_LEN) - 1) << GLB_WIFI_MBIST_DONE_POS) #define GLB_WIFI_MBIST_DONE_UMSK \ - (~(((1U << GLB_WIFI_MBIST_DONE_LEN) - 1) << GLB_WIFI_MBIST_DONE_POS)) + (~(((1 << GLB_WIFI_MBIST_DONE_LEN) - 1) << GLB_WIFI_MBIST_DONE_POS)) #define GLB_IROM_MBIST_FAIL GLB_IROM_MBIST_FAIL -#define GLB_IROM_MBIST_FAIL_POS (16U) -#define GLB_IROM_MBIST_FAIL_LEN (1U) +#define GLB_IROM_MBIST_FAIL_POS (16) +#define GLB_IROM_MBIST_FAIL_LEN (1) #define GLB_IROM_MBIST_FAIL_MSK \ - (((1U << GLB_IROM_MBIST_FAIL_LEN) - 1) << GLB_IROM_MBIST_FAIL_POS) + (((1 << GLB_IROM_MBIST_FAIL_LEN) - 1) << GLB_IROM_MBIST_FAIL_POS) #define GLB_IROM_MBIST_FAIL_UMSK \ - (~(((1U << GLB_IROM_MBIST_FAIL_LEN) - 1) << GLB_IROM_MBIST_FAIL_POS)) + (~(((1 << GLB_IROM_MBIST_FAIL_LEN) - 1) << GLB_IROM_MBIST_FAIL_POS)) #define GLB_HSRAM_MBIST_FAIL GLB_HSRAM_MBIST_FAIL -#define GLB_HSRAM_MBIST_FAIL_POS (17U) -#define GLB_HSRAM_MBIST_FAIL_LEN (1U) +#define GLB_HSRAM_MBIST_FAIL_POS (17) +#define GLB_HSRAM_MBIST_FAIL_LEN (1) #define GLB_HSRAM_MBIST_FAIL_MSK \ - (((1U << GLB_HSRAM_MBIST_FAIL_LEN) - 1) << GLB_HSRAM_MBIST_FAIL_POS) + (((1 << GLB_HSRAM_MBIST_FAIL_LEN) - 1) << GLB_HSRAM_MBIST_FAIL_POS) #define GLB_HSRAM_MBIST_FAIL_UMSK \ - (~(((1U << GLB_HSRAM_MBIST_FAIL_LEN) - 1) << GLB_HSRAM_MBIST_FAIL_POS)) + (~(((1 << GLB_HSRAM_MBIST_FAIL_LEN) - 1) << GLB_HSRAM_MBIST_FAIL_POS)) #define GLB_TAG_MBIST_FAIL GLB_TAG_MBIST_FAIL -#define GLB_TAG_MBIST_FAIL_POS (18U) -#define GLB_TAG_MBIST_FAIL_LEN (1U) +#define GLB_TAG_MBIST_FAIL_POS (18) +#define GLB_TAG_MBIST_FAIL_LEN (1) #define GLB_TAG_MBIST_FAIL_MSK \ - (((1U << GLB_TAG_MBIST_FAIL_LEN) - 1) << GLB_TAG_MBIST_FAIL_POS) + (((1 << GLB_TAG_MBIST_FAIL_LEN) - 1) << GLB_TAG_MBIST_FAIL_POS) #define GLB_TAG_MBIST_FAIL_UMSK \ - (~(((1U << GLB_TAG_MBIST_FAIL_LEN) - 1) << GLB_TAG_MBIST_FAIL_POS)) + (~(((1 << GLB_TAG_MBIST_FAIL_LEN) - 1) << GLB_TAG_MBIST_FAIL_POS)) #define GLB_OCRAM_MBIST_FAIL GLB_OCRAM_MBIST_FAIL -#define GLB_OCRAM_MBIST_FAIL_POS (19U) -#define GLB_OCRAM_MBIST_FAIL_LEN (1U) +#define GLB_OCRAM_MBIST_FAIL_POS (19) +#define GLB_OCRAM_MBIST_FAIL_LEN (1) #define GLB_OCRAM_MBIST_FAIL_MSK \ - (((1U << GLB_OCRAM_MBIST_FAIL_LEN) - 1) << GLB_OCRAM_MBIST_FAIL_POS) + (((1 << GLB_OCRAM_MBIST_FAIL_LEN) - 1) << GLB_OCRAM_MBIST_FAIL_POS) #define GLB_OCRAM_MBIST_FAIL_UMSK \ - (~(((1U << GLB_OCRAM_MBIST_FAIL_LEN) - 1) << GLB_OCRAM_MBIST_FAIL_POS)) + (~(((1 << GLB_OCRAM_MBIST_FAIL_LEN) - 1) << GLB_OCRAM_MBIST_FAIL_POS)) #define GLB_WIFI_MBIST_FAIL GLB_WIFI_MBIST_FAIL -#define GLB_WIFI_MBIST_FAIL_POS (20U) -#define GLB_WIFI_MBIST_FAIL_LEN (1U) +#define GLB_WIFI_MBIST_FAIL_POS (20) +#define GLB_WIFI_MBIST_FAIL_LEN (1) #define GLB_WIFI_MBIST_FAIL_MSK \ - (((1U << GLB_WIFI_MBIST_FAIL_LEN) - 1) << GLB_WIFI_MBIST_FAIL_POS) + (((1 << GLB_WIFI_MBIST_FAIL_LEN) - 1) << GLB_WIFI_MBIST_FAIL_POS) #define GLB_WIFI_MBIST_FAIL_UMSK \ - (~(((1U << GLB_WIFI_MBIST_FAIL_LEN) - 1) << GLB_WIFI_MBIST_FAIL_POS)) + (~(((1 << GLB_WIFI_MBIST_FAIL_LEN) - 1) << GLB_WIFI_MBIST_FAIL_POS)) /* 0x50 : bmx_cfg1 */ #define GLB_BMX_CFG1_OFFSET (0x50) #define GLB_BMX_TIMEOUT_EN GLB_BMX_TIMEOUT_EN -#define GLB_BMX_TIMEOUT_EN_POS (0U) -#define GLB_BMX_TIMEOUT_EN_LEN (4U) +#define GLB_BMX_TIMEOUT_EN_POS (0) +#define GLB_BMX_TIMEOUT_EN_LEN (4) #define GLB_BMX_TIMEOUT_EN_MSK \ - (((1U << GLB_BMX_TIMEOUT_EN_LEN) - 1) << GLB_BMX_TIMEOUT_EN_POS) + (((1 << GLB_BMX_TIMEOUT_EN_LEN) - 1) << GLB_BMX_TIMEOUT_EN_POS) #define GLB_BMX_TIMEOUT_EN_UMSK \ - (~(((1U << GLB_BMX_TIMEOUT_EN_LEN) - 1) << GLB_BMX_TIMEOUT_EN_POS)) + (~(((1 << GLB_BMX_TIMEOUT_EN_LEN) - 1) << GLB_BMX_TIMEOUT_EN_POS)) #define GLB_BMX_ARB_MODE GLB_BMX_ARB_MODE -#define GLB_BMX_ARB_MODE_POS (4U) -#define GLB_BMX_ARB_MODE_LEN (2U) +#define GLB_BMX_ARB_MODE_POS (4) +#define GLB_BMX_ARB_MODE_LEN (2) #define GLB_BMX_ARB_MODE_MSK \ - (((1U << GLB_BMX_ARB_MODE_LEN) - 1) << GLB_BMX_ARB_MODE_POS) + (((1 << GLB_BMX_ARB_MODE_LEN) - 1) << GLB_BMX_ARB_MODE_POS) #define GLB_BMX_ARB_MODE_UMSK \ - (~(((1U << GLB_BMX_ARB_MODE_LEN) - 1) << GLB_BMX_ARB_MODE_POS)) + (~(((1 << GLB_BMX_ARB_MODE_LEN) - 1) << GLB_BMX_ARB_MODE_POS)) #define GLB_BMX_ERR_EN GLB_BMX_ERR_EN -#define GLB_BMX_ERR_EN_POS (8U) -#define GLB_BMX_ERR_EN_LEN (1U) +#define GLB_BMX_ERR_EN_POS (8) +#define GLB_BMX_ERR_EN_LEN (1) #define GLB_BMX_ERR_EN_MSK \ - (((1U << GLB_BMX_ERR_EN_LEN) - 1) << GLB_BMX_ERR_EN_POS) + (((1 << GLB_BMX_ERR_EN_LEN) - 1) << GLB_BMX_ERR_EN_POS) #define GLB_BMX_ERR_EN_UMSK \ - (~(((1U << GLB_BMX_ERR_EN_LEN) - 1) << GLB_BMX_ERR_EN_POS)) + (~(((1 << GLB_BMX_ERR_EN_LEN) - 1) << GLB_BMX_ERR_EN_POS)) #define GLB_BMX_BUSY_OPTION_DIS GLB_BMX_BUSY_OPTION_DIS -#define GLB_BMX_BUSY_OPTION_DIS_POS (9U) -#define GLB_BMX_BUSY_OPTION_DIS_LEN (1U) +#define GLB_BMX_BUSY_OPTION_DIS_POS (9) +#define GLB_BMX_BUSY_OPTION_DIS_LEN (1) #define GLB_BMX_BUSY_OPTION_DIS_MSK \ - (((1U << GLB_BMX_BUSY_OPTION_DIS_LEN) - 1) << GLB_BMX_BUSY_OPTION_DIS_POS) + (((1 << GLB_BMX_BUSY_OPTION_DIS_LEN) - 1) << GLB_BMX_BUSY_OPTION_DIS_POS) #define GLB_BMX_BUSY_OPTION_DIS_UMSK \ - (~(((1U << GLB_BMX_BUSY_OPTION_DIS_LEN) - 1) \ - << GLB_BMX_BUSY_OPTION_DIS_POS)) + (~(((1 << GLB_BMX_BUSY_OPTION_DIS_LEN) - 1) << GLB_BMX_BUSY_OPTION_DIS_POS)) #define GLB_BMX_GATING_DIS GLB_BMX_GATING_DIS -#define GLB_BMX_GATING_DIS_POS (10U) -#define GLB_BMX_GATING_DIS_LEN (1U) +#define GLB_BMX_GATING_DIS_POS (10) +#define GLB_BMX_GATING_DIS_LEN (1) #define GLB_BMX_GATING_DIS_MSK \ - (((1U << GLB_BMX_GATING_DIS_LEN) - 1) << GLB_BMX_GATING_DIS_POS) + (((1 << GLB_BMX_GATING_DIS_LEN) - 1) << GLB_BMX_GATING_DIS_POS) #define GLB_BMX_GATING_DIS_UMSK \ - (~(((1U << GLB_BMX_GATING_DIS_LEN) - 1) << GLB_BMX_GATING_DIS_POS)) + (~(((1 << GLB_BMX_GATING_DIS_LEN) - 1) << GLB_BMX_GATING_DIS_POS)) #define GLB_HSEL_OPTION GLB_HSEL_OPTION -#define GLB_HSEL_OPTION_POS (12U) -#define GLB_HSEL_OPTION_LEN (4U) +#define GLB_HSEL_OPTION_POS (12) +#define GLB_HSEL_OPTION_LEN (4) #define GLB_HSEL_OPTION_MSK \ - (((1U << GLB_HSEL_OPTION_LEN) - 1) << GLB_HSEL_OPTION_POS) + (((1 << GLB_HSEL_OPTION_LEN) - 1) << GLB_HSEL_OPTION_POS) #define GLB_HSEL_OPTION_UMSK \ - (~(((1U << GLB_HSEL_OPTION_LEN) - 1) << GLB_HSEL_OPTION_POS)) + (~(((1 << GLB_HSEL_OPTION_LEN) - 1) << GLB_HSEL_OPTION_POS)) #define GLB_PDS_APB_CFG GLB_PDS_APB_CFG -#define GLB_PDS_APB_CFG_POS (16U) -#define GLB_PDS_APB_CFG_LEN (8U) +#define GLB_PDS_APB_CFG_POS (16) +#define GLB_PDS_APB_CFG_LEN (8) #define GLB_PDS_APB_CFG_MSK \ - (((1U << GLB_PDS_APB_CFG_LEN) - 1) << GLB_PDS_APB_CFG_POS) + (((1 << GLB_PDS_APB_CFG_LEN) - 1) << GLB_PDS_APB_CFG_POS) #define GLB_PDS_APB_CFG_UMSK \ - (~(((1U << GLB_PDS_APB_CFG_LEN) - 1) << GLB_PDS_APB_CFG_POS)) + (~(((1 << GLB_PDS_APB_CFG_LEN) - 1) << GLB_PDS_APB_CFG_POS)) #define GLB_HBN_APB_CFG GLB_HBN_APB_CFG -#define GLB_HBN_APB_CFG_POS (24U) -#define GLB_HBN_APB_CFG_LEN (8U) +#define GLB_HBN_APB_CFG_POS (24) +#define GLB_HBN_APB_CFG_LEN (8) #define GLB_HBN_APB_CFG_MSK \ - (((1U << GLB_HBN_APB_CFG_LEN) - 1) << GLB_HBN_APB_CFG_POS) + (((1 << GLB_HBN_APB_CFG_LEN) - 1) << GLB_HBN_APB_CFG_POS) #define GLB_HBN_APB_CFG_UMSK \ - (~(((1U << GLB_HBN_APB_CFG_LEN) - 1) << GLB_HBN_APB_CFG_POS)) + (~(((1 << GLB_HBN_APB_CFG_LEN) - 1) << GLB_HBN_APB_CFG_POS)) /* 0x54 : bmx_cfg2 */ #define GLB_BMX_CFG2_OFFSET (0x54) #define GLB_BMX_ERR_ADDR_DIS GLB_BMX_ERR_ADDR_DIS -#define GLB_BMX_ERR_ADDR_DIS_POS (0U) -#define GLB_BMX_ERR_ADDR_DIS_LEN (1U) +#define GLB_BMX_ERR_ADDR_DIS_POS (0) +#define GLB_BMX_ERR_ADDR_DIS_LEN (1) #define GLB_BMX_ERR_ADDR_DIS_MSK \ - (((1U << GLB_BMX_ERR_ADDR_DIS_LEN) - 1) << GLB_BMX_ERR_ADDR_DIS_POS) + (((1 << GLB_BMX_ERR_ADDR_DIS_LEN) - 1) << GLB_BMX_ERR_ADDR_DIS_POS) #define GLB_BMX_ERR_ADDR_DIS_UMSK \ - (~(((1U << GLB_BMX_ERR_ADDR_DIS_LEN) - 1) << GLB_BMX_ERR_ADDR_DIS_POS)) + (~(((1 << GLB_BMX_ERR_ADDR_DIS_LEN) - 1) << GLB_BMX_ERR_ADDR_DIS_POS)) #define GLB_BMX_ERR_DEC GLB_BMX_ERR_DEC -#define GLB_BMX_ERR_DEC_POS (4U) -#define GLB_BMX_ERR_DEC_LEN (1U) +#define GLB_BMX_ERR_DEC_POS (4) +#define GLB_BMX_ERR_DEC_LEN (1) #define GLB_BMX_ERR_DEC_MSK \ - (((1U << GLB_BMX_ERR_DEC_LEN) - 1) << GLB_BMX_ERR_DEC_POS) + (((1 << GLB_BMX_ERR_DEC_LEN) - 1) << GLB_BMX_ERR_DEC_POS) #define GLB_BMX_ERR_DEC_UMSK \ - (~(((1U << GLB_BMX_ERR_DEC_LEN) - 1) << GLB_BMX_ERR_DEC_POS)) + (~(((1 << GLB_BMX_ERR_DEC_LEN) - 1) << GLB_BMX_ERR_DEC_POS)) #define GLB_BMX_ERR_TZ GLB_BMX_ERR_TZ -#define GLB_BMX_ERR_TZ_POS (5U) -#define GLB_BMX_ERR_TZ_LEN (1U) +#define GLB_BMX_ERR_TZ_POS (5) +#define GLB_BMX_ERR_TZ_LEN (1) #define GLB_BMX_ERR_TZ_MSK \ - (((1U << GLB_BMX_ERR_TZ_LEN) - 1) << GLB_BMX_ERR_TZ_POS) + (((1 << GLB_BMX_ERR_TZ_LEN) - 1) << GLB_BMX_ERR_TZ_POS) #define GLB_BMX_ERR_TZ_UMSK \ - (~(((1U << GLB_BMX_ERR_TZ_LEN) - 1) << GLB_BMX_ERR_TZ_POS)) + (~(((1 << GLB_BMX_ERR_TZ_LEN) - 1) << GLB_BMX_ERR_TZ_POS)) #define GLB_BMX_DBG_SEL GLB_BMX_DBG_SEL -#define GLB_BMX_DBG_SEL_POS (28U) -#define GLB_BMX_DBG_SEL_LEN (4U) +#define GLB_BMX_DBG_SEL_POS (28) +#define GLB_BMX_DBG_SEL_LEN (4) #define GLB_BMX_DBG_SEL_MSK \ - (((1U << GLB_BMX_DBG_SEL_LEN) - 1) << GLB_BMX_DBG_SEL_POS) + (((1 << GLB_BMX_DBG_SEL_LEN) - 1) << GLB_BMX_DBG_SEL_POS) #define GLB_BMX_DBG_SEL_UMSK \ - (~(((1U << GLB_BMX_DBG_SEL_LEN) - 1) << GLB_BMX_DBG_SEL_POS)) + (~(((1 << GLB_BMX_DBG_SEL_LEN) - 1) << GLB_BMX_DBG_SEL_POS)) /* 0x58 : bmx_err_addr */ #define GLB_BMX_ERR_ADDR_OFFSET (0x58) #define GLB_BMX_ERR_ADDR GLB_BMX_ERR_ADDR -#define GLB_BMX_ERR_ADDR_POS (0U) -#define GLB_BMX_ERR_ADDR_LEN (32U) +#define GLB_BMX_ERR_ADDR_POS (0) +#define GLB_BMX_ERR_ADDR_LEN (32) #define GLB_BMX_ERR_ADDR_MSK \ - (((1U << GLB_BMX_ERR_ADDR_LEN) - 1) << GLB_BMX_ERR_ADDR_POS) + (((1 << GLB_BMX_ERR_ADDR_LEN) - 1) << GLB_BMX_ERR_ADDR_POS) #define GLB_BMX_ERR_ADDR_UMSK \ - (~(((1U << GLB_BMX_ERR_ADDR_LEN) - 1) << GLB_BMX_ERR_ADDR_POS)) + (~(((1 << GLB_BMX_ERR_ADDR_LEN) - 1) << GLB_BMX_ERR_ADDR_POS)) /* 0x5C : bmx_dbg_out */ #define GLB_BMX_DBG_OUT_OFFSET (0x5C) #define GLB_BMX_DBG_OUT GLB_BMX_DBG_OUT -#define GLB_BMX_DBG_OUT_POS (0U) -#define GLB_BMX_DBG_OUT_LEN (32U) +#define GLB_BMX_DBG_OUT_POS (0) +#define GLB_BMX_DBG_OUT_LEN (32) #define GLB_BMX_DBG_OUT_MSK \ - (((1U << GLB_BMX_DBG_OUT_LEN) - 1) << GLB_BMX_DBG_OUT_POS) + (((1 << GLB_BMX_DBG_OUT_LEN) - 1) << GLB_BMX_DBG_OUT_POS) #define GLB_BMX_DBG_OUT_UMSK \ - (~(((1U << GLB_BMX_DBG_OUT_LEN) - 1) << GLB_BMX_DBG_OUT_POS)) + (~(((1 << GLB_BMX_DBG_OUT_LEN) - 1) << GLB_BMX_DBG_OUT_POS)) /* 0x60 : rsv0 */ @@ -790,1921 +792,1910 @@ #define GLB_SRAM_RET_OFFSET (0x70) #define GLB_REG_SRAM_RET GLB_REG_SRAM_RET -#define GLB_REG_SRAM_RET_POS (0U) -#define GLB_REG_SRAM_RET_LEN (32U) +#define GLB_REG_SRAM_RET_POS (0) +#define GLB_REG_SRAM_RET_LEN (32) #define GLB_REG_SRAM_RET_MSK \ - (((1U << GLB_REG_SRAM_RET_LEN) - 1) << GLB_REG_SRAM_RET_POS) + (((1 << GLB_REG_SRAM_RET_LEN) - 1) << GLB_REG_SRAM_RET_POS) #define GLB_REG_SRAM_RET_UMSK \ - (~(((1U << GLB_REG_SRAM_RET_LEN) - 1) << GLB_REG_SRAM_RET_POS)) + (~(((1 << GLB_REG_SRAM_RET_LEN) - 1) << GLB_REG_SRAM_RET_POS)) /* 0x74 : sram_slp */ #define GLB_SRAM_SLP_OFFSET (0x74) #define GLB_REG_SRAM_SLP GLB_REG_SRAM_SLP -#define GLB_REG_SRAM_SLP_POS (0U) -#define GLB_REG_SRAM_SLP_LEN (32U) +#define GLB_REG_SRAM_SLP_POS (0) +#define GLB_REG_SRAM_SLP_LEN (32) #define GLB_REG_SRAM_SLP_MSK \ - (((1U << GLB_REG_SRAM_SLP_LEN) - 1) << GLB_REG_SRAM_SLP_POS) + (((1 << GLB_REG_SRAM_SLP_LEN) - 1) << GLB_REG_SRAM_SLP_POS) #define GLB_REG_SRAM_SLP_UMSK \ - (~(((1U << GLB_REG_SRAM_SLP_LEN) - 1) << GLB_REG_SRAM_SLP_POS)) + (~(((1 << GLB_REG_SRAM_SLP_LEN) - 1) << GLB_REG_SRAM_SLP_POS)) /* 0x78 : sram_parm */ #define GLB_SRAM_PARM_OFFSET (0x78) #define GLB_REG_SRAM_PARM GLB_REG_SRAM_PARM -#define GLB_REG_SRAM_PARM_POS (0U) -#define GLB_REG_SRAM_PARM_LEN (32U) +#define GLB_REG_SRAM_PARM_POS (0) +#define GLB_REG_SRAM_PARM_LEN (32) #define GLB_REG_SRAM_PARM_MSK \ - (((1U << GLB_REG_SRAM_PARM_LEN) - 1) << GLB_REG_SRAM_PARM_POS) + (((1 << GLB_REG_SRAM_PARM_LEN) - 1) << GLB_REG_SRAM_PARM_POS) #define GLB_REG_SRAM_PARM_UMSK \ - (~(((1U << GLB_REG_SRAM_PARM_LEN) - 1) << GLB_REG_SRAM_PARM_POS)) + (~(((1 << GLB_REG_SRAM_PARM_LEN) - 1) << GLB_REG_SRAM_PARM_POS)) /* 0x7C : seam_misc */ #define GLB_SEAM_MISC_OFFSET (0x7C) #define GLB_EM_SEL GLB_EM_SEL -#define GLB_EM_SEL_POS (0U) -#define GLB_EM_SEL_LEN (4U) -#define GLB_EM_SEL_MSK (((1U << GLB_EM_SEL_LEN) - 1) << GLB_EM_SEL_POS) -#define GLB_EM_SEL_UMSK (~(((1U << GLB_EM_SEL_LEN) - 1) << GLB_EM_SEL_POS)) +#define GLB_EM_SEL_POS (0) +#define GLB_EM_SEL_LEN (4) +#define GLB_EM_SEL_MSK (((1 << GLB_EM_SEL_LEN) - 1) << GLB_EM_SEL_POS) +#define GLB_EM_SEL_UMSK (~(((1 << GLB_EM_SEL_LEN) - 1) << GLB_EM_SEL_POS)) /* 0x80 : glb_parm */ #define GLB_PARM_OFFSET (0x80) #define GLB_REG_BD_EN GLB_REG_BD_EN -#define GLB_REG_BD_EN_POS (0U) -#define GLB_REG_BD_EN_LEN (1U) +#define GLB_REG_BD_EN_POS (0) +#define GLB_REG_BD_EN_LEN (1) #define GLB_REG_BD_EN_MSK \ - (((1U << GLB_REG_BD_EN_LEN) - 1) << GLB_REG_BD_EN_POS) + (((1 << GLB_REG_BD_EN_LEN) - 1) << GLB_REG_BD_EN_POS) #define GLB_REG_BD_EN_UMSK \ - (~(((1U << GLB_REG_BD_EN_LEN) - 1) << GLB_REG_BD_EN_POS)) + (~(((1 << GLB_REG_BD_EN_LEN) - 1) << GLB_REG_BD_EN_POS)) #define GLB_REG_EXT_RST_SMT GLB_REG_EXT_RST_SMT -#define GLB_REG_EXT_RST_SMT_POS (1U) -#define GLB_REG_EXT_RST_SMT_LEN (1U) +#define GLB_REG_EXT_RST_SMT_POS (1) +#define GLB_REG_EXT_RST_SMT_LEN (1) #define GLB_REG_EXT_RST_SMT_MSK \ - (((1U << GLB_REG_EXT_RST_SMT_LEN) - 1) << GLB_REG_EXT_RST_SMT_POS) + (((1 << GLB_REG_EXT_RST_SMT_LEN) - 1) << GLB_REG_EXT_RST_SMT_POS) #define GLB_REG_EXT_RST_SMT_UMSK \ - (~(((1U << GLB_REG_EXT_RST_SMT_LEN) - 1) << GLB_REG_EXT_RST_SMT_POS)) + (~(((1 << GLB_REG_EXT_RST_SMT_LEN) - 1) << GLB_REG_EXT_RST_SMT_POS)) #define GLB_JTAG_SWAP_SET GLB_JTAG_SWAP_SET -#define GLB_JTAG_SWAP_SET_POS (2U) -#define GLB_JTAG_SWAP_SET_LEN (6U) +#define GLB_JTAG_SWAP_SET_POS (2) +#define GLB_JTAG_SWAP_SET_LEN (6) #define GLB_JTAG_SWAP_SET_MSK \ - (((1U << GLB_JTAG_SWAP_SET_LEN) - 1) << GLB_JTAG_SWAP_SET_POS) + (((1 << GLB_JTAG_SWAP_SET_LEN) - 1) << GLB_JTAG_SWAP_SET_POS) #define GLB_JTAG_SWAP_SET_UMSK \ - (~(((1U << GLB_JTAG_SWAP_SET_LEN) - 1) << GLB_JTAG_SWAP_SET_POS)) + (~(((1 << GLB_JTAG_SWAP_SET_LEN) - 1) << GLB_JTAG_SWAP_SET_POS)) #define GLB_SWAP_SFLASH_IO_3_IO_0 GLB_SWAP_SFLASH_IO_3_IO_0 -#define GLB_SWAP_SFLASH_IO_3_IO_0_POS (8U) -#define GLB_SWAP_SFLASH_IO_3_IO_0_LEN (1U) +#define GLB_SWAP_SFLASH_IO_3_IO_0_POS (8) +#define GLB_SWAP_SFLASH_IO_3_IO_0_LEN (1) #define GLB_SWAP_SFLASH_IO_3_IO_0_MSK \ - (((1U << GLB_SWAP_SFLASH_IO_3_IO_0_LEN) - 1) \ + (((1 << GLB_SWAP_SFLASH_IO_3_IO_0_LEN) - 1) \ << GLB_SWAP_SFLASH_IO_3_IO_0_POS) #define GLB_SWAP_SFLASH_IO_3_IO_0_UMSK \ - (~(((1U << GLB_SWAP_SFLASH_IO_3_IO_0_LEN) - 1) \ + (~(((1 << GLB_SWAP_SFLASH_IO_3_IO_0_LEN) - 1) \ << GLB_SWAP_SFLASH_IO_3_IO_0_POS)) #define GLB_SEL_EMBEDDED_SFLASH GLB_SEL_EMBEDDED_SFLASH -#define GLB_SEL_EMBEDDED_SFLASH_POS (9U) -#define GLB_SEL_EMBEDDED_SFLASH_LEN (1U) +#define GLB_SEL_EMBEDDED_SFLASH_POS (9) +#define GLB_SEL_EMBEDDED_SFLASH_LEN (1) #define GLB_SEL_EMBEDDED_SFLASH_MSK \ - (((1U << GLB_SEL_EMBEDDED_SFLASH_LEN) - 1) << GLB_SEL_EMBEDDED_SFLASH_POS) + (((1 << GLB_SEL_EMBEDDED_SFLASH_LEN) - 1) << GLB_SEL_EMBEDDED_SFLASH_POS) #define GLB_SEL_EMBEDDED_SFLASH_UMSK \ - (~(((1U << GLB_SEL_EMBEDDED_SFLASH_LEN) - 1) \ - << GLB_SEL_EMBEDDED_SFLASH_POS)) + (~(((1 << GLB_SEL_EMBEDDED_SFLASH_LEN) - 1) << GLB_SEL_EMBEDDED_SFLASH_POS)) #define GLB_REG_SPI_0_MASTER_MODE GLB_REG_SPI_0_MASTER_MODE -#define GLB_REG_SPI_0_MASTER_MODE_POS (12U) -#define GLB_REG_SPI_0_MASTER_MODE_LEN (1U) +#define GLB_REG_SPI_0_MASTER_MODE_POS (12) +#define GLB_REG_SPI_0_MASTER_MODE_LEN (1) #define GLB_REG_SPI_0_MASTER_MODE_MSK \ - (((1U << GLB_REG_SPI_0_MASTER_MODE_LEN) - 1) \ + (((1 << GLB_REG_SPI_0_MASTER_MODE_LEN) - 1) \ << GLB_REG_SPI_0_MASTER_MODE_POS) #define GLB_REG_SPI_0_MASTER_MODE_UMSK \ - (~(((1U << GLB_REG_SPI_0_MASTER_MODE_LEN) - 1) \ + (~(((1 << GLB_REG_SPI_0_MASTER_MODE_LEN) - 1) \ << GLB_REG_SPI_0_MASTER_MODE_POS)) #define GLB_REG_SPI_0_SWAP GLB_REG_SPI_0_SWAP -#define GLB_REG_SPI_0_SWAP_POS (13U) -#define GLB_REG_SPI_0_SWAP_LEN (1U) +#define GLB_REG_SPI_0_SWAP_POS (13) +#define GLB_REG_SPI_0_SWAP_LEN (1) #define GLB_REG_SPI_0_SWAP_MSK \ - (((1U << GLB_REG_SPI_0_SWAP_LEN) - 1) << GLB_REG_SPI_0_SWAP_POS) + (((1 << GLB_REG_SPI_0_SWAP_LEN) - 1) << GLB_REG_SPI_0_SWAP_POS) #define GLB_REG_SPI_0_SWAP_UMSK \ - (~(((1U << GLB_REG_SPI_0_SWAP_LEN) - 1) << GLB_REG_SPI_0_SWAP_POS)) + (~(((1 << GLB_REG_SPI_0_SWAP_LEN) - 1) << GLB_REG_SPI_0_SWAP_POS)) #define GLB_REG_CCI_USE_JTAG_PIN GLB_REG_CCI_USE_JTAG_PIN -#define GLB_REG_CCI_USE_JTAG_PIN_POS (15U) -#define GLB_REG_CCI_USE_JTAG_PIN_LEN (1U) +#define GLB_REG_CCI_USE_JTAG_PIN_POS (15) +#define GLB_REG_CCI_USE_JTAG_PIN_LEN (1) #define GLB_REG_CCI_USE_JTAG_PIN_MSK \ - (((1U << GLB_REG_CCI_USE_JTAG_PIN_LEN) - 1) << GLB_REG_CCI_USE_JTAG_PIN_POS) + (((1 << GLB_REG_CCI_USE_JTAG_PIN_LEN) - 1) << GLB_REG_CCI_USE_JTAG_PIN_POS) #define GLB_REG_CCI_USE_JTAG_PIN_UMSK \ - (~(((1U << GLB_REG_CCI_USE_JTAG_PIN_LEN) - 1) \ + (~(((1 << GLB_REG_CCI_USE_JTAG_PIN_LEN) - 1) \ << GLB_REG_CCI_USE_JTAG_PIN_POS)) #define GLB_REG_CCI_USE_SDIO_PIN GLB_REG_CCI_USE_SDIO_PIN -#define GLB_REG_CCI_USE_SDIO_PIN_POS (16U) -#define GLB_REG_CCI_USE_SDIO_PIN_LEN (1U) +#define GLB_REG_CCI_USE_SDIO_PIN_POS (16) +#define GLB_REG_CCI_USE_SDIO_PIN_LEN (1) #define GLB_REG_CCI_USE_SDIO_PIN_MSK \ - (((1U << GLB_REG_CCI_USE_SDIO_PIN_LEN) - 1) << GLB_REG_CCI_USE_SDIO_PIN_POS) + (((1 << GLB_REG_CCI_USE_SDIO_PIN_LEN) - 1) << GLB_REG_CCI_USE_SDIO_PIN_POS) #define GLB_REG_CCI_USE_SDIO_PIN_UMSK \ - (~(((1U << GLB_REG_CCI_USE_SDIO_PIN_LEN) - 1) \ + (~(((1 << GLB_REG_CCI_USE_SDIO_PIN_LEN) - 1) \ << GLB_REG_CCI_USE_SDIO_PIN_POS)) #define GLB_P1_ADC_TEST_WITH_CCI GLB_P1_ADC_TEST_WITH_CCI -#define GLB_P1_ADC_TEST_WITH_CCI_POS (17U) -#define GLB_P1_ADC_TEST_WITH_CCI_LEN (1U) +#define GLB_P1_ADC_TEST_WITH_CCI_POS (17) +#define GLB_P1_ADC_TEST_WITH_CCI_LEN (1) #define GLB_P1_ADC_TEST_WITH_CCI_MSK \ - (((1U << GLB_P1_ADC_TEST_WITH_CCI_LEN) - 1) << GLB_P1_ADC_TEST_WITH_CCI_POS) + (((1 << GLB_P1_ADC_TEST_WITH_CCI_LEN) - 1) << GLB_P1_ADC_TEST_WITH_CCI_POS) #define GLB_P1_ADC_TEST_WITH_CCI_UMSK \ - (~(((1U << GLB_P1_ADC_TEST_WITH_CCI_LEN) - 1) \ + (~(((1 << GLB_P1_ADC_TEST_WITH_CCI_LEN) - 1) \ << GLB_P1_ADC_TEST_WITH_CCI_POS)) #define GLB_P2_DAC_TEST_WITH_CCI GLB_P2_DAC_TEST_WITH_CCI -#define GLB_P2_DAC_TEST_WITH_CCI_POS (18U) -#define GLB_P2_DAC_TEST_WITH_CCI_LEN (1U) +#define GLB_P2_DAC_TEST_WITH_CCI_POS (18) +#define GLB_P2_DAC_TEST_WITH_CCI_LEN (1) #define GLB_P2_DAC_TEST_WITH_CCI_MSK \ - (((1U << GLB_P2_DAC_TEST_WITH_CCI_LEN) - 1) << GLB_P2_DAC_TEST_WITH_CCI_POS) + (((1 << GLB_P2_DAC_TEST_WITH_CCI_LEN) - 1) << GLB_P2_DAC_TEST_WITH_CCI_POS) #define GLB_P2_DAC_TEST_WITH_CCI_UMSK \ - (~(((1U << GLB_P2_DAC_TEST_WITH_CCI_LEN) - 1) \ + (~(((1 << GLB_P2_DAC_TEST_WITH_CCI_LEN) - 1) \ << GLB_P2_DAC_TEST_WITH_CCI_POS)) #define GLB_P3_CCI_USE_IO_2_5 GLB_P3_CCI_USE_IO_2_5 -#define GLB_P3_CCI_USE_IO_2_5_POS (19U) -#define GLB_P3_CCI_USE_IO_2_5_LEN (1U) +#define GLB_P3_CCI_USE_IO_2_5_POS (19) +#define GLB_P3_CCI_USE_IO_2_5_LEN (1) #define GLB_P3_CCI_USE_IO_2_5_MSK \ - (((1U << GLB_P3_CCI_USE_IO_2_5_LEN) - 1) << GLB_P3_CCI_USE_IO_2_5_POS) + (((1 << GLB_P3_CCI_USE_IO_2_5_LEN) - 1) << GLB_P3_CCI_USE_IO_2_5_POS) #define GLB_P3_CCI_USE_IO_2_5_UMSK \ - (~(((1U << GLB_P3_CCI_USE_IO_2_5_LEN) - 1) << GLB_P3_CCI_USE_IO_2_5_POS)) + (~(((1 << GLB_P3_CCI_USE_IO_2_5_LEN) - 1) << GLB_P3_CCI_USE_IO_2_5_POS)) #define GLB_P4_ADC_TEST_WITH_JTAG GLB_P4_ADC_TEST_WITH_JTAG -#define GLB_P4_ADC_TEST_WITH_JTAG_POS (20U) -#define GLB_P4_ADC_TEST_WITH_JTAG_LEN (1U) +#define GLB_P4_ADC_TEST_WITH_JTAG_POS (20) +#define GLB_P4_ADC_TEST_WITH_JTAG_LEN (1) #define GLB_P4_ADC_TEST_WITH_JTAG_MSK \ - (((1U << GLB_P4_ADC_TEST_WITH_JTAG_LEN) - 1) \ + (((1 << GLB_P4_ADC_TEST_WITH_JTAG_LEN) - 1) \ << GLB_P4_ADC_TEST_WITH_JTAG_POS) #define GLB_P4_ADC_TEST_WITH_JTAG_UMSK \ - (~(((1U << GLB_P4_ADC_TEST_WITH_JTAG_LEN) - 1) \ + (~(((1 << GLB_P4_ADC_TEST_WITH_JTAG_LEN) - 1) \ << GLB_P4_ADC_TEST_WITH_JTAG_POS)) #define GLB_P5_DAC_TEST_WITH_JTAG GLB_P5_DAC_TEST_WITH_JTAG -#define GLB_P5_DAC_TEST_WITH_JTAG_POS (21U) -#define GLB_P5_DAC_TEST_WITH_JTAG_LEN (1U) +#define GLB_P5_DAC_TEST_WITH_JTAG_POS (21) +#define GLB_P5_DAC_TEST_WITH_JTAG_LEN (1) #define GLB_P5_DAC_TEST_WITH_JTAG_MSK \ - (((1U << GLB_P5_DAC_TEST_WITH_JTAG_LEN) - 1) \ + (((1 << GLB_P5_DAC_TEST_WITH_JTAG_LEN) - 1) \ << GLB_P5_DAC_TEST_WITH_JTAG_POS) #define GLB_P5_DAC_TEST_WITH_JTAG_UMSK \ - (~(((1U << GLB_P5_DAC_TEST_WITH_JTAG_LEN) - 1) \ + (~(((1 << GLB_P5_DAC_TEST_WITH_JTAG_LEN) - 1) \ << GLB_P5_DAC_TEST_WITH_JTAG_POS)) #define GLB_P6_SDIO_USE_IO_0_5 GLB_P6_SDIO_USE_IO_0_5 -#define GLB_P6_SDIO_USE_IO_0_5_POS (22U) -#define GLB_P6_SDIO_USE_IO_0_5_LEN (1U) +#define GLB_P6_SDIO_USE_IO_0_5_POS (22) +#define GLB_P6_SDIO_USE_IO_0_5_LEN (1) #define GLB_P6_SDIO_USE_IO_0_5_MSK \ - (((1U << GLB_P6_SDIO_USE_IO_0_5_LEN) - 1) << GLB_P6_SDIO_USE_IO_0_5_POS) + (((1 << GLB_P6_SDIO_USE_IO_0_5_LEN) - 1) << GLB_P6_SDIO_USE_IO_0_5_POS) #define GLB_P6_SDIO_USE_IO_0_5_UMSK \ - (~(((1U << GLB_P6_SDIO_USE_IO_0_5_LEN) - 1) << GLB_P6_SDIO_USE_IO_0_5_POS)) + (~(((1 << GLB_P6_SDIO_USE_IO_0_5_LEN) - 1) << GLB_P6_SDIO_USE_IO_0_5_POS)) #define GLB_P7_JTAG_USE_IO_2_5 GLB_P7_JTAG_USE_IO_2_5 -#define GLB_P7_JTAG_USE_IO_2_5_POS (23U) -#define GLB_P7_JTAG_USE_IO_2_5_LEN (1U) +#define GLB_P7_JTAG_USE_IO_2_5_POS (23) +#define GLB_P7_JTAG_USE_IO_2_5_LEN (1) #define GLB_P7_JTAG_USE_IO_2_5_MSK \ - (((1U << GLB_P7_JTAG_USE_IO_2_5_LEN) - 1) << GLB_P7_JTAG_USE_IO_2_5_POS) + (((1 << GLB_P7_JTAG_USE_IO_2_5_LEN) - 1) << GLB_P7_JTAG_USE_IO_2_5_POS) #define GLB_P7_JTAG_USE_IO_2_5_UMSK \ - (~(((1U << GLB_P7_JTAG_USE_IO_2_5_LEN) - 1) << GLB_P7_JTAG_USE_IO_2_5_POS)) + (~(((1 << GLB_P7_JTAG_USE_IO_2_5_LEN) - 1) << GLB_P7_JTAG_USE_IO_2_5_POS)) #define GLB_UART_SWAP_SET GLB_UART_SWAP_SET -#define GLB_UART_SWAP_SET_POS (24U) -#define GLB_UART_SWAP_SET_LEN (3U) +#define GLB_UART_SWAP_SET_POS (24) +#define GLB_UART_SWAP_SET_LEN (3) #define GLB_UART_SWAP_SET_MSK \ - (((1U << GLB_UART_SWAP_SET_LEN) - 1) << GLB_UART_SWAP_SET_POS) + (((1 << GLB_UART_SWAP_SET_LEN) - 1) << GLB_UART_SWAP_SET_POS) #define GLB_UART_SWAP_SET_UMSK \ - (~(((1U << GLB_UART_SWAP_SET_LEN) - 1) << GLB_UART_SWAP_SET_POS)) + (~(((1 << GLB_UART_SWAP_SET_LEN) - 1) << GLB_UART_SWAP_SET_POS)) /* 0x90 : CPU_CLK_CFG */ #define GLB_CPU_CLK_CFG_OFFSET (0x90) #define GLB_CPU_RTC_DIV GLB_CPU_RTC_DIV -#define GLB_CPU_RTC_DIV_POS (0U) -#define GLB_CPU_RTC_DIV_LEN (17U) +#define GLB_CPU_RTC_DIV_POS (0) +#define GLB_CPU_RTC_DIV_LEN (17) #define GLB_CPU_RTC_DIV_MSK \ - (((1U << GLB_CPU_RTC_DIV_LEN) - 1) << GLB_CPU_RTC_DIV_POS) + (((1 << GLB_CPU_RTC_DIV_LEN) - 1) << GLB_CPU_RTC_DIV_POS) #define GLB_CPU_RTC_DIV_UMSK \ - (~(((1U << GLB_CPU_RTC_DIV_LEN) - 1) << GLB_CPU_RTC_DIV_POS)) + (~(((1 << GLB_CPU_RTC_DIV_LEN) - 1) << GLB_CPU_RTC_DIV_POS)) #define GLB_CPU_RTC_EN GLB_CPU_RTC_EN -#define GLB_CPU_RTC_EN_POS (18U) -#define GLB_CPU_RTC_EN_LEN (1U) +#define GLB_CPU_RTC_EN_POS (18) +#define GLB_CPU_RTC_EN_LEN (1) #define GLB_CPU_RTC_EN_MSK \ - (((1U << GLB_CPU_RTC_EN_LEN) - 1) << GLB_CPU_RTC_EN_POS) + (((1 << GLB_CPU_RTC_EN_LEN) - 1) << GLB_CPU_RTC_EN_POS) #define GLB_CPU_RTC_EN_UMSK \ - (~(((1U << GLB_CPU_RTC_EN_LEN) - 1) << GLB_CPU_RTC_EN_POS)) + (~(((1 << GLB_CPU_RTC_EN_LEN) - 1) << GLB_CPU_RTC_EN_POS)) #define GLB_CPU_RTC_SEL GLB_CPU_RTC_SEL -#define GLB_CPU_RTC_SEL_POS (19U) -#define GLB_CPU_RTC_SEL_LEN (1U) +#define GLB_CPU_RTC_SEL_POS (19) +#define GLB_CPU_RTC_SEL_LEN (1) #define GLB_CPU_RTC_SEL_MSK \ - (((1U << GLB_CPU_RTC_SEL_LEN) - 1) << GLB_CPU_RTC_SEL_POS) + (((1 << GLB_CPU_RTC_SEL_LEN) - 1) << GLB_CPU_RTC_SEL_POS) #define GLB_CPU_RTC_SEL_UMSK \ - (~(((1U << GLB_CPU_RTC_SEL_LEN) - 1) << GLB_CPU_RTC_SEL_POS)) + (~(((1 << GLB_CPU_RTC_SEL_LEN) - 1) << GLB_CPU_RTC_SEL_POS)) #define GLB_DEBUG_NDRESET_GATE GLB_DEBUG_NDRESET_GATE -#define GLB_DEBUG_NDRESET_GATE_POS (20U) -#define GLB_DEBUG_NDRESET_GATE_LEN (1U) +#define GLB_DEBUG_NDRESET_GATE_POS (20) +#define GLB_DEBUG_NDRESET_GATE_LEN (1) #define GLB_DEBUG_NDRESET_GATE_MSK \ - (((1U << GLB_DEBUG_NDRESET_GATE_LEN) - 1) << GLB_DEBUG_NDRESET_GATE_POS) + (((1 << GLB_DEBUG_NDRESET_GATE_LEN) - 1) << GLB_DEBUG_NDRESET_GATE_POS) #define GLB_DEBUG_NDRESET_GATE_UMSK \ - (~(((1U << GLB_DEBUG_NDRESET_GATE_LEN) - 1) << GLB_DEBUG_NDRESET_GATE_POS)) + (~(((1 << GLB_DEBUG_NDRESET_GATE_LEN) - 1) << GLB_DEBUG_NDRESET_GATE_POS)) /* 0xA4 : GPADC_32M_SRC_CTRL */ #define GLB_GPADC_32M_SRC_CTRL_OFFSET (0xA4) #define GLB_GPADC_32M_CLK_DIV GLB_GPADC_32M_CLK_DIV -#define GLB_GPADC_32M_CLK_DIV_POS (0U) -#define GLB_GPADC_32M_CLK_DIV_LEN (6U) +#define GLB_GPADC_32M_CLK_DIV_POS (0) +#define GLB_GPADC_32M_CLK_DIV_LEN (6) #define GLB_GPADC_32M_CLK_DIV_MSK \ - (((1U << GLB_GPADC_32M_CLK_DIV_LEN) - 1) << GLB_GPADC_32M_CLK_DIV_POS) + (((1 << GLB_GPADC_32M_CLK_DIV_LEN) - 1) << GLB_GPADC_32M_CLK_DIV_POS) #define GLB_GPADC_32M_CLK_DIV_UMSK \ - (~(((1U << GLB_GPADC_32M_CLK_DIV_LEN) - 1) << GLB_GPADC_32M_CLK_DIV_POS)) + (~(((1 << GLB_GPADC_32M_CLK_DIV_LEN) - 1) << GLB_GPADC_32M_CLK_DIV_POS)) #define GLB_GPADC_32M_CLK_SEL GLB_GPADC_32M_CLK_SEL -#define GLB_GPADC_32M_CLK_SEL_POS (7U) -#define GLB_GPADC_32M_CLK_SEL_LEN (1U) +#define GLB_GPADC_32M_CLK_SEL_POS (7) +#define GLB_GPADC_32M_CLK_SEL_LEN (1) #define GLB_GPADC_32M_CLK_SEL_MSK \ - (((1U << GLB_GPADC_32M_CLK_SEL_LEN) - 1) << GLB_GPADC_32M_CLK_SEL_POS) + (((1 << GLB_GPADC_32M_CLK_SEL_LEN) - 1) << GLB_GPADC_32M_CLK_SEL_POS) #define GLB_GPADC_32M_CLK_SEL_UMSK \ - (~(((1U << GLB_GPADC_32M_CLK_SEL_LEN) - 1) << GLB_GPADC_32M_CLK_SEL_POS)) + (~(((1 << GLB_GPADC_32M_CLK_SEL_LEN) - 1) << GLB_GPADC_32M_CLK_SEL_POS)) #define GLB_GPADC_32M_DIV_EN GLB_GPADC_32M_DIV_EN -#define GLB_GPADC_32M_DIV_EN_POS (8U) -#define GLB_GPADC_32M_DIV_EN_LEN (1U) +#define GLB_GPADC_32M_DIV_EN_POS (8) +#define GLB_GPADC_32M_DIV_EN_LEN (1) #define GLB_GPADC_32M_DIV_EN_MSK \ - (((1U << GLB_GPADC_32M_DIV_EN_LEN) - 1) << GLB_GPADC_32M_DIV_EN_POS) + (((1 << GLB_GPADC_32M_DIV_EN_LEN) - 1) << GLB_GPADC_32M_DIV_EN_POS) #define GLB_GPADC_32M_DIV_EN_UMSK \ - (~(((1U << GLB_GPADC_32M_DIV_EN_LEN) - 1) << GLB_GPADC_32M_DIV_EN_POS)) + (~(((1 << GLB_GPADC_32M_DIV_EN_LEN) - 1) << GLB_GPADC_32M_DIV_EN_POS)) /* 0xA8 : DIG32K_WAKEUP_CTRL */ #define GLB_DIG32K_WAKEUP_CTRL_OFFSET (0xA8) #define GLB_DIG_32K_DIV GLB_DIG_32K_DIV -#define GLB_DIG_32K_DIV_POS (0U) -#define GLB_DIG_32K_DIV_LEN (11U) +#define GLB_DIG_32K_DIV_POS (0) +#define GLB_DIG_32K_DIV_LEN (11) #define GLB_DIG_32K_DIV_MSK \ - (((1U << GLB_DIG_32K_DIV_LEN) - 1) << GLB_DIG_32K_DIV_POS) + (((1 << GLB_DIG_32K_DIV_LEN) - 1) << GLB_DIG_32K_DIV_POS) #define GLB_DIG_32K_DIV_UMSK \ - (~(((1U << GLB_DIG_32K_DIV_LEN) - 1) << GLB_DIG_32K_DIV_POS)) + (~(((1 << GLB_DIG_32K_DIV_LEN) - 1) << GLB_DIG_32K_DIV_POS)) #define GLB_DIG_32K_EN GLB_DIG_32K_EN -#define GLB_DIG_32K_EN_POS (12U) -#define GLB_DIG_32K_EN_LEN (1U) +#define GLB_DIG_32K_EN_POS (12) +#define GLB_DIG_32K_EN_LEN (1) #define GLB_DIG_32K_EN_MSK \ - (((1U << GLB_DIG_32K_EN_LEN) - 1) << GLB_DIG_32K_EN_POS) + (((1 << GLB_DIG_32K_EN_LEN) - 1) << GLB_DIG_32K_EN_POS) #define GLB_DIG_32K_EN_UMSK \ - (~(((1U << GLB_DIG_32K_EN_LEN) - 1) << GLB_DIG_32K_EN_POS)) + (~(((1 << GLB_DIG_32K_EN_LEN) - 1) << GLB_DIG_32K_EN_POS)) #define GLB_DIG_32K_COMP GLB_DIG_32K_COMP -#define GLB_DIG_32K_COMP_POS (13U) -#define GLB_DIG_32K_COMP_LEN (1U) +#define GLB_DIG_32K_COMP_POS (13) +#define GLB_DIG_32K_COMP_LEN (1) #define GLB_DIG_32K_COMP_MSK \ - (((1U << GLB_DIG_32K_COMP_LEN) - 1) << GLB_DIG_32K_COMP_POS) + (((1 << GLB_DIG_32K_COMP_LEN) - 1) << GLB_DIG_32K_COMP_POS) #define GLB_DIG_32K_COMP_UMSK \ - (~(((1U << GLB_DIG_32K_COMP_LEN) - 1) << GLB_DIG_32K_COMP_POS)) + (~(((1 << GLB_DIG_32K_COMP_LEN) - 1) << GLB_DIG_32K_COMP_POS)) #define GLB_DIG_512K_DIV GLB_DIG_512K_DIV -#define GLB_DIG_512K_DIV_POS (16U) -#define GLB_DIG_512K_DIV_LEN (7U) +#define GLB_DIG_512K_DIV_POS (16) +#define GLB_DIG_512K_DIV_LEN (7) #define GLB_DIG_512K_DIV_MSK \ - (((1U << GLB_DIG_512K_DIV_LEN) - 1) << GLB_DIG_512K_DIV_POS) + (((1 << GLB_DIG_512K_DIV_LEN) - 1) << GLB_DIG_512K_DIV_POS) #define GLB_DIG_512K_DIV_UMSK \ - (~(((1U << GLB_DIG_512K_DIV_LEN) - 1) << GLB_DIG_512K_DIV_POS)) + (~(((1 << GLB_DIG_512K_DIV_LEN) - 1) << GLB_DIG_512K_DIV_POS)) #define GLB_DIG_512K_EN GLB_DIG_512K_EN -#define GLB_DIG_512K_EN_POS (24U) -#define GLB_DIG_512K_EN_LEN (1U) +#define GLB_DIG_512K_EN_POS (24) +#define GLB_DIG_512K_EN_LEN (1) #define GLB_DIG_512K_EN_MSK \ - (((1U << GLB_DIG_512K_EN_LEN) - 1) << GLB_DIG_512K_EN_POS) + (((1 << GLB_DIG_512K_EN_LEN) - 1) << GLB_DIG_512K_EN_POS) #define GLB_DIG_512K_EN_UMSK \ - (~(((1U << GLB_DIG_512K_EN_LEN) - 1) << GLB_DIG_512K_EN_POS)) + (~(((1 << GLB_DIG_512K_EN_LEN) - 1) << GLB_DIG_512K_EN_POS)) #define GLB_DIG_512K_COMP GLB_DIG_512K_COMP -#define GLB_DIG_512K_COMP_POS (25U) -#define GLB_DIG_512K_COMP_LEN (1U) +#define GLB_DIG_512K_COMP_POS (25) +#define GLB_DIG_512K_COMP_LEN (1) #define GLB_DIG_512K_COMP_MSK \ - (((1U << GLB_DIG_512K_COMP_LEN) - 1) << GLB_DIG_512K_COMP_POS) + (((1 << GLB_DIG_512K_COMP_LEN) - 1) << GLB_DIG_512K_COMP_POS) #define GLB_DIG_512K_COMP_UMSK \ - (~(((1U << GLB_DIG_512K_COMP_LEN) - 1) << GLB_DIG_512K_COMP_POS)) + (~(((1 << GLB_DIG_512K_COMP_LEN) - 1) << GLB_DIG_512K_COMP_POS)) #define GLB_DIG_CLK_SRC_SEL GLB_DIG_CLK_SRC_SEL -#define GLB_DIG_CLK_SRC_SEL_POS (28U) -#define GLB_DIG_CLK_SRC_SEL_LEN (1U) +#define GLB_DIG_CLK_SRC_SEL_POS (28) +#define GLB_DIG_CLK_SRC_SEL_LEN (1) #define GLB_DIG_CLK_SRC_SEL_MSK \ - (((1U << GLB_DIG_CLK_SRC_SEL_LEN) - 1) << GLB_DIG_CLK_SRC_SEL_POS) + (((1 << GLB_DIG_CLK_SRC_SEL_LEN) - 1) << GLB_DIG_CLK_SRC_SEL_POS) #define GLB_DIG_CLK_SRC_SEL_UMSK \ - (~(((1U << GLB_DIG_CLK_SRC_SEL_LEN) - 1) << GLB_DIG_CLK_SRC_SEL_POS)) + (~(((1 << GLB_DIG_CLK_SRC_SEL_LEN) - 1) << GLB_DIG_CLK_SRC_SEL_POS)) #define GLB_REG_EN_PLATFORM_WAKEUP GLB_REG_EN_PLATFORM_WAKEUP -#define GLB_REG_EN_PLATFORM_WAKEUP_POS (31U) -#define GLB_REG_EN_PLATFORM_WAKEUP_LEN (1U) +#define GLB_REG_EN_PLATFORM_WAKEUP_POS (31) +#define GLB_REG_EN_PLATFORM_WAKEUP_LEN (1) #define GLB_REG_EN_PLATFORM_WAKEUP_MSK \ - (((1U << GLB_REG_EN_PLATFORM_WAKEUP_LEN) - 1) \ + (((1 << GLB_REG_EN_PLATFORM_WAKEUP_LEN) - 1) \ << GLB_REG_EN_PLATFORM_WAKEUP_POS) #define GLB_REG_EN_PLATFORM_WAKEUP_UMSK \ - (~(((1U << GLB_REG_EN_PLATFORM_WAKEUP_LEN) - 1) \ + (~(((1 << GLB_REG_EN_PLATFORM_WAKEUP_LEN) - 1) \ << GLB_REG_EN_PLATFORM_WAKEUP_POS)) /* 0xAC : WIFI_BT_COEX_CTRL */ #define GLB_WIFI_BT_COEX_CTRL_OFFSET (0xAC) #define GLB_COEX_BT_CHANNEL GLB_COEX_BT_CHANNEL -#define GLB_COEX_BT_CHANNEL_POS (0U) -#define GLB_COEX_BT_CHANNEL_LEN (7U) +#define GLB_COEX_BT_CHANNEL_POS (0) +#define GLB_COEX_BT_CHANNEL_LEN (7) #define GLB_COEX_BT_CHANNEL_MSK \ - (((1U << GLB_COEX_BT_CHANNEL_LEN) - 1) << GLB_COEX_BT_CHANNEL_POS) + (((1 << GLB_COEX_BT_CHANNEL_LEN) - 1) << GLB_COEX_BT_CHANNEL_POS) #define GLB_COEX_BT_CHANNEL_UMSK \ - (~(((1U << GLB_COEX_BT_CHANNEL_LEN) - 1) << GLB_COEX_BT_CHANNEL_POS)) + (~(((1 << GLB_COEX_BT_CHANNEL_LEN) - 1) << GLB_COEX_BT_CHANNEL_POS)) #define GLB_COEX_BT_PTI GLB_COEX_BT_PTI -#define GLB_COEX_BT_PTI_POS (7U) -#define GLB_COEX_BT_PTI_LEN (4U) +#define GLB_COEX_BT_PTI_POS (7) +#define GLB_COEX_BT_PTI_LEN (4) #define GLB_COEX_BT_PTI_MSK \ - (((1U << GLB_COEX_BT_PTI_LEN) - 1) << GLB_COEX_BT_PTI_POS) + (((1 << GLB_COEX_BT_PTI_LEN) - 1) << GLB_COEX_BT_PTI_POS) #define GLB_COEX_BT_PTI_UMSK \ - (~(((1U << GLB_COEX_BT_PTI_LEN) - 1) << GLB_COEX_BT_PTI_POS)) + (~(((1 << GLB_COEX_BT_PTI_LEN) - 1) << GLB_COEX_BT_PTI_POS)) #define GLB_COEX_BT_BW GLB_COEX_BT_BW -#define GLB_COEX_BT_BW_POS (11U) -#define GLB_COEX_BT_BW_LEN (1U) +#define GLB_COEX_BT_BW_POS (11) +#define GLB_COEX_BT_BW_LEN (1) #define GLB_COEX_BT_BW_MSK \ - (((1U << GLB_COEX_BT_BW_LEN) - 1) << GLB_COEX_BT_BW_POS) + (((1 << GLB_COEX_BT_BW_LEN) - 1) << GLB_COEX_BT_BW_POS) #define GLB_COEX_BT_BW_UMSK \ - (~(((1U << GLB_COEX_BT_BW_LEN) - 1) << GLB_COEX_BT_BW_POS)) + (~(((1 << GLB_COEX_BT_BW_LEN) - 1) << GLB_COEX_BT_BW_POS)) #define GLB_EN_GPIO_BT_COEX GLB_EN_GPIO_BT_COEX -#define GLB_EN_GPIO_BT_COEX_POS (12U) -#define GLB_EN_GPIO_BT_COEX_LEN (1U) +#define GLB_EN_GPIO_BT_COEX_POS (12) +#define GLB_EN_GPIO_BT_COEX_LEN (1) #define GLB_EN_GPIO_BT_COEX_MSK \ - (((1U << GLB_EN_GPIO_BT_COEX_LEN) - 1) << GLB_EN_GPIO_BT_COEX_POS) + (((1 << GLB_EN_GPIO_BT_COEX_LEN) - 1) << GLB_EN_GPIO_BT_COEX_POS) #define GLB_EN_GPIO_BT_COEX_UMSK \ - (~(((1U << GLB_EN_GPIO_BT_COEX_LEN) - 1) << GLB_EN_GPIO_BT_COEX_POS)) + (~(((1 << GLB_EN_GPIO_BT_COEX_LEN) - 1) << GLB_EN_GPIO_BT_COEX_POS)) /* 0xC0 : UART_SIG_SEL_0 */ #define GLB_UART_SIG_SEL_0_OFFSET (0xC0) #define GLB_UART_SIG_0_SEL GLB_UART_SIG_0_SEL -#define GLB_UART_SIG_0_SEL_POS (0U) -#define GLB_UART_SIG_0_SEL_LEN (4U) +#define GLB_UART_SIG_0_SEL_POS (0) +#define GLB_UART_SIG_0_SEL_LEN (4) #define GLB_UART_SIG_0_SEL_MSK \ - (((1U << GLB_UART_SIG_0_SEL_LEN) - 1) << GLB_UART_SIG_0_SEL_POS) + (((1 << GLB_UART_SIG_0_SEL_LEN) - 1) << GLB_UART_SIG_0_SEL_POS) #define GLB_UART_SIG_0_SEL_UMSK \ - (~(((1U << GLB_UART_SIG_0_SEL_LEN) - 1) << GLB_UART_SIG_0_SEL_POS)) + (~(((1 << GLB_UART_SIG_0_SEL_LEN) - 1) << GLB_UART_SIG_0_SEL_POS)) #define GLB_UART_SIG_1_SEL GLB_UART_SIG_1_SEL -#define GLB_UART_SIG_1_SEL_POS (4U) -#define GLB_UART_SIG_1_SEL_LEN (4U) +#define GLB_UART_SIG_1_SEL_POS (4) +#define GLB_UART_SIG_1_SEL_LEN (4) #define GLB_UART_SIG_1_SEL_MSK \ - (((1U << GLB_UART_SIG_1_SEL_LEN) - 1) << GLB_UART_SIG_1_SEL_POS) + (((1 << GLB_UART_SIG_1_SEL_LEN) - 1) << GLB_UART_SIG_1_SEL_POS) #define GLB_UART_SIG_1_SEL_UMSK \ - (~(((1U << GLB_UART_SIG_1_SEL_LEN) - 1) << GLB_UART_SIG_1_SEL_POS)) + (~(((1 << GLB_UART_SIG_1_SEL_LEN) - 1) << GLB_UART_SIG_1_SEL_POS)) #define GLB_UART_SIG_2_SEL GLB_UART_SIG_2_SEL -#define GLB_UART_SIG_2_SEL_POS (8U) -#define GLB_UART_SIG_2_SEL_LEN (4U) +#define GLB_UART_SIG_2_SEL_POS (8) +#define GLB_UART_SIG_2_SEL_LEN (4) #define GLB_UART_SIG_2_SEL_MSK \ - (((1U << GLB_UART_SIG_2_SEL_LEN) - 1) << GLB_UART_SIG_2_SEL_POS) + (((1 << GLB_UART_SIG_2_SEL_LEN) - 1) << GLB_UART_SIG_2_SEL_POS) #define GLB_UART_SIG_2_SEL_UMSK \ - (~(((1U << GLB_UART_SIG_2_SEL_LEN) - 1) << GLB_UART_SIG_2_SEL_POS)) + (~(((1 << GLB_UART_SIG_2_SEL_LEN) - 1) << GLB_UART_SIG_2_SEL_POS)) #define GLB_UART_SIG_3_SEL GLB_UART_SIG_3_SEL -#define GLB_UART_SIG_3_SEL_POS (12U) -#define GLB_UART_SIG_3_SEL_LEN (4U) +#define GLB_UART_SIG_3_SEL_POS (12) +#define GLB_UART_SIG_3_SEL_LEN (4) #define GLB_UART_SIG_3_SEL_MSK \ - (((1U << GLB_UART_SIG_3_SEL_LEN) - 1) << GLB_UART_SIG_3_SEL_POS) + (((1 << GLB_UART_SIG_3_SEL_LEN) - 1) << GLB_UART_SIG_3_SEL_POS) #define GLB_UART_SIG_3_SEL_UMSK \ - (~(((1U << GLB_UART_SIG_3_SEL_LEN) - 1) << GLB_UART_SIG_3_SEL_POS)) + (~(((1 << GLB_UART_SIG_3_SEL_LEN) - 1) << GLB_UART_SIG_3_SEL_POS)) #define GLB_UART_SIG_4_SEL GLB_UART_SIG_4_SEL -#define GLB_UART_SIG_4_SEL_POS (16U) -#define GLB_UART_SIG_4_SEL_LEN (4U) +#define GLB_UART_SIG_4_SEL_POS (16) +#define GLB_UART_SIG_4_SEL_LEN (4) #define GLB_UART_SIG_4_SEL_MSK \ - (((1U << GLB_UART_SIG_4_SEL_LEN) - 1) << GLB_UART_SIG_4_SEL_POS) + (((1 << GLB_UART_SIG_4_SEL_LEN) - 1) << GLB_UART_SIG_4_SEL_POS) #define GLB_UART_SIG_4_SEL_UMSK \ - (~(((1U << GLB_UART_SIG_4_SEL_LEN) - 1) << GLB_UART_SIG_4_SEL_POS)) + (~(((1 << GLB_UART_SIG_4_SEL_LEN) - 1) << GLB_UART_SIG_4_SEL_POS)) #define GLB_UART_SIG_5_SEL GLB_UART_SIG_5_SEL -#define GLB_UART_SIG_5_SEL_POS (20U) -#define GLB_UART_SIG_5_SEL_LEN (4U) +#define GLB_UART_SIG_5_SEL_POS (20) +#define GLB_UART_SIG_5_SEL_LEN (4) #define GLB_UART_SIG_5_SEL_MSK \ - (((1U << GLB_UART_SIG_5_SEL_LEN) - 1) << GLB_UART_SIG_5_SEL_POS) + (((1 << GLB_UART_SIG_5_SEL_LEN) - 1) << GLB_UART_SIG_5_SEL_POS) #define GLB_UART_SIG_5_SEL_UMSK \ - (~(((1U << GLB_UART_SIG_5_SEL_LEN) - 1) << GLB_UART_SIG_5_SEL_POS)) + (~(((1 << GLB_UART_SIG_5_SEL_LEN) - 1) << GLB_UART_SIG_5_SEL_POS)) #define GLB_UART_SIG_6_SEL GLB_UART_SIG_6_SEL -#define GLB_UART_SIG_6_SEL_POS (24U) -#define GLB_UART_SIG_6_SEL_LEN (4U) +#define GLB_UART_SIG_6_SEL_POS (24) +#define GLB_UART_SIG_6_SEL_LEN (4) #define GLB_UART_SIG_6_SEL_MSK \ - (((1U << GLB_UART_SIG_6_SEL_LEN) - 1) << GLB_UART_SIG_6_SEL_POS) + (((1 << GLB_UART_SIG_6_SEL_LEN) - 1) << GLB_UART_SIG_6_SEL_POS) #define GLB_UART_SIG_6_SEL_UMSK \ - (~(((1U << GLB_UART_SIG_6_SEL_LEN) - 1) << GLB_UART_SIG_6_SEL_POS)) + (~(((1 << GLB_UART_SIG_6_SEL_LEN) - 1) << GLB_UART_SIG_6_SEL_POS)) #define GLB_UART_SIG_7_SEL GLB_UART_SIG_7_SEL -#define GLB_UART_SIG_7_SEL_POS (28U) -#define GLB_UART_SIG_7_SEL_LEN (4U) +#define GLB_UART_SIG_7_SEL_POS (28) +#define GLB_UART_SIG_7_SEL_LEN (4) #define GLB_UART_SIG_7_SEL_MSK \ - (((1U << GLB_UART_SIG_7_SEL_LEN) - 1) << GLB_UART_SIG_7_SEL_POS) + (((1 << GLB_UART_SIG_7_SEL_LEN) - 1) << GLB_UART_SIG_7_SEL_POS) #define GLB_UART_SIG_7_SEL_UMSK \ - (~(((1U << GLB_UART_SIG_7_SEL_LEN) - 1) << GLB_UART_SIG_7_SEL_POS)) + (~(((1 << GLB_UART_SIG_7_SEL_LEN) - 1) << GLB_UART_SIG_7_SEL_POS)) /* 0xD0 : DBG_SEL_LL */ #define GLB_DBG_SEL_LL_OFFSET (0xD0) #define GLB_REG_DBG_LL_CTRL GLB_REG_DBG_LL_CTRL -#define GLB_REG_DBG_LL_CTRL_POS (0U) -#define GLB_REG_DBG_LL_CTRL_LEN (32U) +#define GLB_REG_DBG_LL_CTRL_POS (0) +#define GLB_REG_DBG_LL_CTRL_LEN (32) #define GLB_REG_DBG_LL_CTRL_MSK \ - (((1U << GLB_REG_DBG_LL_CTRL_LEN) - 1) << GLB_REG_DBG_LL_CTRL_POS) + (((1 << GLB_REG_DBG_LL_CTRL_LEN) - 1) << GLB_REG_DBG_LL_CTRL_POS) #define GLB_REG_DBG_LL_CTRL_UMSK \ - (~(((1U << GLB_REG_DBG_LL_CTRL_LEN) - 1) << GLB_REG_DBG_LL_CTRL_POS)) + (~(((1 << GLB_REG_DBG_LL_CTRL_LEN) - 1) << GLB_REG_DBG_LL_CTRL_POS)) /* 0xD4 : DBG_SEL_LH */ #define GLB_DBG_SEL_LH_OFFSET (0xD4) #define GLB_REG_DBG_LH_CTRL GLB_REG_DBG_LH_CTRL -#define GLB_REG_DBG_LH_CTRL_POS (0U) -#define GLB_REG_DBG_LH_CTRL_LEN (32U) +#define GLB_REG_DBG_LH_CTRL_POS (0) +#define GLB_REG_DBG_LH_CTRL_LEN (32) #define GLB_REG_DBG_LH_CTRL_MSK \ - (((1U << GLB_REG_DBG_LH_CTRL_LEN) - 1) << GLB_REG_DBG_LH_CTRL_POS) + (((1 << GLB_REG_DBG_LH_CTRL_LEN) - 1) << GLB_REG_DBG_LH_CTRL_POS) #define GLB_REG_DBG_LH_CTRL_UMSK \ - (~(((1U << GLB_REG_DBG_LH_CTRL_LEN) - 1) << GLB_REG_DBG_LH_CTRL_POS)) + (~(((1 << GLB_REG_DBG_LH_CTRL_LEN) - 1) << GLB_REG_DBG_LH_CTRL_POS)) /* 0xD8 : DBG_SEL_HL */ #define GLB_DBG_SEL_HL_OFFSET (0xD8) #define GLB_REG_DBG_HL_CTRL GLB_REG_DBG_HL_CTRL -#define GLB_REG_DBG_HL_CTRL_POS (0U) -#define GLB_REG_DBG_HL_CTRL_LEN (32U) +#define GLB_REG_DBG_HL_CTRL_POS (0) +#define GLB_REG_DBG_HL_CTRL_LEN (32) #define GLB_REG_DBG_HL_CTRL_MSK \ - (((1U << GLB_REG_DBG_HL_CTRL_LEN) - 1) << GLB_REG_DBG_HL_CTRL_POS) + (((1 << GLB_REG_DBG_HL_CTRL_LEN) - 1) << GLB_REG_DBG_HL_CTRL_POS) #define GLB_REG_DBG_HL_CTRL_UMSK \ - (~(((1U << GLB_REG_DBG_HL_CTRL_LEN) - 1) << GLB_REG_DBG_HL_CTRL_POS)) + (~(((1 << GLB_REG_DBG_HL_CTRL_LEN) - 1) << GLB_REG_DBG_HL_CTRL_POS)) /* 0xDC : DBG_SEL_HH */ #define GLB_DBG_SEL_HH_OFFSET (0xDC) #define GLB_REG_DBG_HH_CTRL GLB_REG_DBG_HH_CTRL -#define GLB_REG_DBG_HH_CTRL_POS (0U) -#define GLB_REG_DBG_HH_CTRL_LEN (32U) +#define GLB_REG_DBG_HH_CTRL_POS (0) +#define GLB_REG_DBG_HH_CTRL_LEN (32) #define GLB_REG_DBG_HH_CTRL_MSK \ - (((1U << GLB_REG_DBG_HH_CTRL_LEN) - 1) << GLB_REG_DBG_HH_CTRL_POS) + (((1 << GLB_REG_DBG_HH_CTRL_LEN) - 1) << GLB_REG_DBG_HH_CTRL_POS) #define GLB_REG_DBG_HH_CTRL_UMSK \ - (~(((1U << GLB_REG_DBG_HH_CTRL_LEN) - 1) << GLB_REG_DBG_HH_CTRL_POS)) + (~(((1 << GLB_REG_DBG_HH_CTRL_LEN) - 1) << GLB_REG_DBG_HH_CTRL_POS)) /* 0xE0 : debug */ #define GLB_DEBUG_OFFSET (0xE0) #define GLB_DEBUG_OE GLB_DEBUG_OE -#define GLB_DEBUG_OE_POS (0U) -#define GLB_DEBUG_OE_LEN (1U) -#define GLB_DEBUG_OE_MSK (((1U << GLB_DEBUG_OE_LEN) - 1) << GLB_DEBUG_OE_POS) +#define GLB_DEBUG_OE_POS (0) +#define GLB_DEBUG_OE_LEN (1) +#define GLB_DEBUG_OE_MSK (((1 << GLB_DEBUG_OE_LEN) - 1) << GLB_DEBUG_OE_POS) #define GLB_DEBUG_OE_UMSK \ - (~(((1U << GLB_DEBUG_OE_LEN) - 1) << GLB_DEBUG_OE_POS)) + (~(((1 << GLB_DEBUG_OE_LEN) - 1) << GLB_DEBUG_OE_POS)) #define GLB_DEBUG_I GLB_DEBUG_I -#define GLB_DEBUG_I_POS (1U) -#define GLB_DEBUG_I_LEN (31U) -#define GLB_DEBUG_I_MSK (((1U << GLB_DEBUG_I_LEN) - 1) << GLB_DEBUG_I_POS) -#define GLB_DEBUG_I_UMSK (~(((1U << GLB_DEBUG_I_LEN) - 1) << GLB_DEBUG_I_POS)) +#define GLB_DEBUG_I_POS (1) +#define GLB_DEBUG_I_LEN (31) +#define GLB_DEBUG_I_MSK (((1 << GLB_DEBUG_I_LEN) - 1) << GLB_DEBUG_I_POS) +#define GLB_DEBUG_I_UMSK (~(((1 << GLB_DEBUG_I_LEN) - 1) << GLB_DEBUG_I_POS)) /* 0x100 : GPIO_CFGCTL0 */ #define GLB_GPIO_CFGCTL0_OFFSET (0x100) #define GLB_REG_GPIO_0_IE GLB_REG_GPIO_0_IE -#define GLB_REG_GPIO_0_IE_POS (0U) -#define GLB_REG_GPIO_0_IE_LEN (1U) +#define GLB_REG_GPIO_0_IE_POS (0) +#define GLB_REG_GPIO_0_IE_LEN (1) #define GLB_REG_GPIO_0_IE_MSK \ - (((1U << GLB_REG_GPIO_0_IE_LEN) - 1) << GLB_REG_GPIO_0_IE_POS) + (((1 << GLB_REG_GPIO_0_IE_LEN) - 1) << GLB_REG_GPIO_0_IE_POS) #define GLB_REG_GPIO_0_IE_UMSK \ - (~(((1U << GLB_REG_GPIO_0_IE_LEN) - 1) << GLB_REG_GPIO_0_IE_POS)) + (~(((1 << GLB_REG_GPIO_0_IE_LEN) - 1) << GLB_REG_GPIO_0_IE_POS)) #define GLB_REG_GPIO_0_SMT GLB_REG_GPIO_0_SMT -#define GLB_REG_GPIO_0_SMT_POS (1U) -#define GLB_REG_GPIO_0_SMT_LEN (1U) +#define GLB_REG_GPIO_0_SMT_POS (1) +#define GLB_REG_GPIO_0_SMT_LEN (1) #define GLB_REG_GPIO_0_SMT_MSK \ - (((1U << GLB_REG_GPIO_0_SMT_LEN) - 1) << GLB_REG_GPIO_0_SMT_POS) + (((1 << GLB_REG_GPIO_0_SMT_LEN) - 1) << GLB_REG_GPIO_0_SMT_POS) #define GLB_REG_GPIO_0_SMT_UMSK \ - (~(((1U << GLB_REG_GPIO_0_SMT_LEN) - 1) << GLB_REG_GPIO_0_SMT_POS)) + (~(((1 << GLB_REG_GPIO_0_SMT_LEN) - 1) << GLB_REG_GPIO_0_SMT_POS)) #define GLB_REG_GPIO_0_DRV GLB_REG_GPIO_0_DRV -#define GLB_REG_GPIO_0_DRV_POS (2U) -#define GLB_REG_GPIO_0_DRV_LEN (2U) +#define GLB_REG_GPIO_0_DRV_POS (2) +#define GLB_REG_GPIO_0_DRV_LEN (2) #define GLB_REG_GPIO_0_DRV_MSK \ - (((1U << GLB_REG_GPIO_0_DRV_LEN) - 1) << GLB_REG_GPIO_0_DRV_POS) + (((1 << GLB_REG_GPIO_0_DRV_LEN) - 1) << GLB_REG_GPIO_0_DRV_POS) #define GLB_REG_GPIO_0_DRV_UMSK \ - (~(((1U << GLB_REG_GPIO_0_DRV_LEN) - 1) << GLB_REG_GPIO_0_DRV_POS)) + (~(((1 << GLB_REG_GPIO_0_DRV_LEN) - 1) << GLB_REG_GPIO_0_DRV_POS)) #define GLB_REG_GPIO_0_PU GLB_REG_GPIO_0_PU -#define GLB_REG_GPIO_0_PU_POS (4U) -#define GLB_REG_GPIO_0_PU_LEN (1U) +#define GLB_REG_GPIO_0_PU_POS (4) +#define GLB_REG_GPIO_0_PU_LEN (1) #define GLB_REG_GPIO_0_PU_MSK \ - (((1U << GLB_REG_GPIO_0_PU_LEN) - 1) << GLB_REG_GPIO_0_PU_POS) + (((1 << GLB_REG_GPIO_0_PU_LEN) - 1) << GLB_REG_GPIO_0_PU_POS) #define GLB_REG_GPIO_0_PU_UMSK \ - (~(((1U << GLB_REG_GPIO_0_PU_LEN) - 1) << GLB_REG_GPIO_0_PU_POS)) + (~(((1 << GLB_REG_GPIO_0_PU_LEN) - 1) << GLB_REG_GPIO_0_PU_POS)) #define GLB_REG_GPIO_0_PD GLB_REG_GPIO_0_PD -#define GLB_REG_GPIO_0_PD_POS (5U) -#define GLB_REG_GPIO_0_PD_LEN (1U) +#define GLB_REG_GPIO_0_PD_POS (5) +#define GLB_REG_GPIO_0_PD_LEN (1) #define GLB_REG_GPIO_0_PD_MSK \ - (((1U << GLB_REG_GPIO_0_PD_LEN) - 1) << GLB_REG_GPIO_0_PD_POS) + (((1 << GLB_REG_GPIO_0_PD_LEN) - 1) << GLB_REG_GPIO_0_PD_POS) #define GLB_REG_GPIO_0_PD_UMSK \ - (~(((1U << GLB_REG_GPIO_0_PD_LEN) - 1) << GLB_REG_GPIO_0_PD_POS)) + (~(((1 << GLB_REG_GPIO_0_PD_LEN) - 1) << GLB_REG_GPIO_0_PD_POS)) #define GLB_REG_GPIO_0_FUNC_SEL GLB_REG_GPIO_0_FUNC_SEL -#define GLB_REG_GPIO_0_FUNC_SEL_POS (8U) -#define GLB_REG_GPIO_0_FUNC_SEL_LEN (4U) +#define GLB_REG_GPIO_0_FUNC_SEL_POS (8) +#define GLB_REG_GPIO_0_FUNC_SEL_LEN (4) #define GLB_REG_GPIO_0_FUNC_SEL_MSK \ - (((1U << GLB_REG_GPIO_0_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_0_FUNC_SEL_POS) + (((1 << GLB_REG_GPIO_0_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_0_FUNC_SEL_POS) #define GLB_REG_GPIO_0_FUNC_SEL_UMSK \ - (~(((1U << GLB_REG_GPIO_0_FUNC_SEL_LEN) - 1) \ - << GLB_REG_GPIO_0_FUNC_SEL_POS)) + (~(((1 << GLB_REG_GPIO_0_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_0_FUNC_SEL_POS)) #define GLB_REAL_GPIO_0_FUNC_SEL GLB_REAL_GPIO_0_FUNC_SEL -#define GLB_REAL_GPIO_0_FUNC_SEL_POS (12U) -#define GLB_REAL_GPIO_0_FUNC_SEL_LEN (4U) +#define GLB_REAL_GPIO_0_FUNC_SEL_POS (12) +#define GLB_REAL_GPIO_0_FUNC_SEL_LEN (4) #define GLB_REAL_GPIO_0_FUNC_SEL_MSK \ - (((1U << GLB_REAL_GPIO_0_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_0_FUNC_SEL_POS) + (((1 << GLB_REAL_GPIO_0_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_0_FUNC_SEL_POS) #define GLB_REAL_GPIO_0_FUNC_SEL_UMSK \ - (~(((1U << GLB_REAL_GPIO_0_FUNC_SEL_LEN) - 1) \ + (~(((1 << GLB_REAL_GPIO_0_FUNC_SEL_LEN) - 1) \ << GLB_REAL_GPIO_0_FUNC_SEL_POS)) #define GLB_REG_GPIO_1_IE GLB_REG_GPIO_1_IE -#define GLB_REG_GPIO_1_IE_POS (16U) -#define GLB_REG_GPIO_1_IE_LEN (1U) +#define GLB_REG_GPIO_1_IE_POS (16) +#define GLB_REG_GPIO_1_IE_LEN (1) #define GLB_REG_GPIO_1_IE_MSK \ - (((1U << GLB_REG_GPIO_1_IE_LEN) - 1) << GLB_REG_GPIO_1_IE_POS) + (((1 << GLB_REG_GPIO_1_IE_LEN) - 1) << GLB_REG_GPIO_1_IE_POS) #define GLB_REG_GPIO_1_IE_UMSK \ - (~(((1U << GLB_REG_GPIO_1_IE_LEN) - 1) << GLB_REG_GPIO_1_IE_POS)) + (~(((1 << GLB_REG_GPIO_1_IE_LEN) - 1) << GLB_REG_GPIO_1_IE_POS)) #define GLB_REG_GPIO_1_SMT GLB_REG_GPIO_1_SMT -#define GLB_REG_GPIO_1_SMT_POS (17U) -#define GLB_REG_GPIO_1_SMT_LEN (1U) +#define GLB_REG_GPIO_1_SMT_POS (17) +#define GLB_REG_GPIO_1_SMT_LEN (1) #define GLB_REG_GPIO_1_SMT_MSK \ - (((1U << GLB_REG_GPIO_1_SMT_LEN) - 1) << GLB_REG_GPIO_1_SMT_POS) + (((1 << GLB_REG_GPIO_1_SMT_LEN) - 1) << GLB_REG_GPIO_1_SMT_POS) #define GLB_REG_GPIO_1_SMT_UMSK \ - (~(((1U << GLB_REG_GPIO_1_SMT_LEN) - 1) << GLB_REG_GPIO_1_SMT_POS)) + (~(((1 << GLB_REG_GPIO_1_SMT_LEN) - 1) << GLB_REG_GPIO_1_SMT_POS)) #define GLB_REG_GPIO_1_DRV GLB_REG_GPIO_1_DRV -#define GLB_REG_GPIO_1_DRV_POS (18U) -#define GLB_REG_GPIO_1_DRV_LEN (2U) +#define GLB_REG_GPIO_1_DRV_POS (18) +#define GLB_REG_GPIO_1_DRV_LEN (2) #define GLB_REG_GPIO_1_DRV_MSK \ - (((1U << GLB_REG_GPIO_1_DRV_LEN) - 1) << GLB_REG_GPIO_1_DRV_POS) + (((1 << GLB_REG_GPIO_1_DRV_LEN) - 1) << GLB_REG_GPIO_1_DRV_POS) #define GLB_REG_GPIO_1_DRV_UMSK \ - (~(((1U << GLB_REG_GPIO_1_DRV_LEN) - 1) << GLB_REG_GPIO_1_DRV_POS)) + (~(((1 << GLB_REG_GPIO_1_DRV_LEN) - 1) << GLB_REG_GPIO_1_DRV_POS)) #define GLB_REG_GPIO_1_PU GLB_REG_GPIO_1_PU -#define GLB_REG_GPIO_1_PU_POS (20U) -#define GLB_REG_GPIO_1_PU_LEN (1U) +#define GLB_REG_GPIO_1_PU_POS (20) +#define GLB_REG_GPIO_1_PU_LEN (1) #define GLB_REG_GPIO_1_PU_MSK \ - (((1U << GLB_REG_GPIO_1_PU_LEN) - 1) << GLB_REG_GPIO_1_PU_POS) + (((1 << GLB_REG_GPIO_1_PU_LEN) - 1) << GLB_REG_GPIO_1_PU_POS) #define GLB_REG_GPIO_1_PU_UMSK \ - (~(((1U << GLB_REG_GPIO_1_PU_LEN) - 1) << GLB_REG_GPIO_1_PU_POS)) + (~(((1 << GLB_REG_GPIO_1_PU_LEN) - 1) << GLB_REG_GPIO_1_PU_POS)) #define GLB_REG_GPIO_1_PD GLB_REG_GPIO_1_PD -#define GLB_REG_GPIO_1_PD_POS (21U) -#define GLB_REG_GPIO_1_PD_LEN (1U) +#define GLB_REG_GPIO_1_PD_POS (21) +#define GLB_REG_GPIO_1_PD_LEN (1) #define GLB_REG_GPIO_1_PD_MSK \ - (((1U << GLB_REG_GPIO_1_PD_LEN) - 1) << GLB_REG_GPIO_1_PD_POS) + (((1 << GLB_REG_GPIO_1_PD_LEN) - 1) << GLB_REG_GPIO_1_PD_POS) #define GLB_REG_GPIO_1_PD_UMSK \ - (~(((1U << GLB_REG_GPIO_1_PD_LEN) - 1) << GLB_REG_GPIO_1_PD_POS)) + (~(((1 << GLB_REG_GPIO_1_PD_LEN) - 1) << GLB_REG_GPIO_1_PD_POS)) #define GLB_REG_GPIO_1_FUNC_SEL GLB_REG_GPIO_1_FUNC_SEL -#define GLB_REG_GPIO_1_FUNC_SEL_POS (24U) -#define GLB_REG_GPIO_1_FUNC_SEL_LEN (4U) +#define GLB_REG_GPIO_1_FUNC_SEL_POS (24) +#define GLB_REG_GPIO_1_FUNC_SEL_LEN (4) #define GLB_REG_GPIO_1_FUNC_SEL_MSK \ - (((1U << GLB_REG_GPIO_1_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_1_FUNC_SEL_POS) + (((1 << GLB_REG_GPIO_1_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_1_FUNC_SEL_POS) #define GLB_REG_GPIO_1_FUNC_SEL_UMSK \ - (~(((1U << GLB_REG_GPIO_1_FUNC_SEL_LEN) - 1) \ - << GLB_REG_GPIO_1_FUNC_SEL_POS)) + (~(((1 << GLB_REG_GPIO_1_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_1_FUNC_SEL_POS)) #define GLB_REAL_GPIO_1_FUNC_SEL GLB_REAL_GPIO_1_FUNC_SEL -#define GLB_REAL_GPIO_1_FUNC_SEL_POS (28U) -#define GLB_REAL_GPIO_1_FUNC_SEL_LEN (4U) +#define GLB_REAL_GPIO_1_FUNC_SEL_POS (28) +#define GLB_REAL_GPIO_1_FUNC_SEL_LEN (4) #define GLB_REAL_GPIO_1_FUNC_SEL_MSK \ - (((1U << GLB_REAL_GPIO_1_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_1_FUNC_SEL_POS) + (((1 << GLB_REAL_GPIO_1_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_1_FUNC_SEL_POS) #define GLB_REAL_GPIO_1_FUNC_SEL_UMSK \ - (~(((1U << GLB_REAL_GPIO_1_FUNC_SEL_LEN) - 1) \ + (~(((1 << GLB_REAL_GPIO_1_FUNC_SEL_LEN) - 1) \ << GLB_REAL_GPIO_1_FUNC_SEL_POS)) /* 0x104 : GPIO_CFGCTL1 */ #define GLB_GPIO_CFGCTL1_OFFSET (0x104) #define GLB_REG_GPIO_2_IE GLB_REG_GPIO_2_IE -#define GLB_REG_GPIO_2_IE_POS (0U) -#define GLB_REG_GPIO_2_IE_LEN (1U) +#define GLB_REG_GPIO_2_IE_POS (0) +#define GLB_REG_GPIO_2_IE_LEN (1) #define GLB_REG_GPIO_2_IE_MSK \ - (((1U << GLB_REG_GPIO_2_IE_LEN) - 1) << GLB_REG_GPIO_2_IE_POS) + (((1 << GLB_REG_GPIO_2_IE_LEN) - 1) << GLB_REG_GPIO_2_IE_POS) #define GLB_REG_GPIO_2_IE_UMSK \ - (~(((1U << GLB_REG_GPIO_2_IE_LEN) - 1) << GLB_REG_GPIO_2_IE_POS)) + (~(((1 << GLB_REG_GPIO_2_IE_LEN) - 1) << GLB_REG_GPIO_2_IE_POS)) #define GLB_REG_GPIO_2_SMT GLB_REG_GPIO_2_SMT -#define GLB_REG_GPIO_2_SMT_POS (1U) -#define GLB_REG_GPIO_2_SMT_LEN (1U) +#define GLB_REG_GPIO_2_SMT_POS (1) +#define GLB_REG_GPIO_2_SMT_LEN (1) #define GLB_REG_GPIO_2_SMT_MSK \ - (((1U << GLB_REG_GPIO_2_SMT_LEN) - 1) << GLB_REG_GPIO_2_SMT_POS) + (((1 << GLB_REG_GPIO_2_SMT_LEN) - 1) << GLB_REG_GPIO_2_SMT_POS) #define GLB_REG_GPIO_2_SMT_UMSK \ - (~(((1U << GLB_REG_GPIO_2_SMT_LEN) - 1) << GLB_REG_GPIO_2_SMT_POS)) + (~(((1 << GLB_REG_GPIO_2_SMT_LEN) - 1) << GLB_REG_GPIO_2_SMT_POS)) #define GLB_REG_GPIO_2_DRV GLB_REG_GPIO_2_DRV -#define GLB_REG_GPIO_2_DRV_POS (2U) -#define GLB_REG_GPIO_2_DRV_LEN (2U) +#define GLB_REG_GPIO_2_DRV_POS (2) +#define GLB_REG_GPIO_2_DRV_LEN (2) #define GLB_REG_GPIO_2_DRV_MSK \ - (((1U << GLB_REG_GPIO_2_DRV_LEN) - 1) << GLB_REG_GPIO_2_DRV_POS) + (((1 << GLB_REG_GPIO_2_DRV_LEN) - 1) << GLB_REG_GPIO_2_DRV_POS) #define GLB_REG_GPIO_2_DRV_UMSK \ - (~(((1U << GLB_REG_GPIO_2_DRV_LEN) - 1) << GLB_REG_GPIO_2_DRV_POS)) + (~(((1 << GLB_REG_GPIO_2_DRV_LEN) - 1) << GLB_REG_GPIO_2_DRV_POS)) #define GLB_REG_GPIO_2_PU GLB_REG_GPIO_2_PU -#define GLB_REG_GPIO_2_PU_POS (4U) -#define GLB_REG_GPIO_2_PU_LEN (1U) +#define GLB_REG_GPIO_2_PU_POS (4) +#define GLB_REG_GPIO_2_PU_LEN (1) #define GLB_REG_GPIO_2_PU_MSK \ - (((1U << GLB_REG_GPIO_2_PU_LEN) - 1) << GLB_REG_GPIO_2_PU_POS) + (((1 << GLB_REG_GPIO_2_PU_LEN) - 1) << GLB_REG_GPIO_2_PU_POS) #define GLB_REG_GPIO_2_PU_UMSK \ - (~(((1U << GLB_REG_GPIO_2_PU_LEN) - 1) << GLB_REG_GPIO_2_PU_POS)) + (~(((1 << GLB_REG_GPIO_2_PU_LEN) - 1) << GLB_REG_GPIO_2_PU_POS)) #define GLB_REG_GPIO_2_PD GLB_REG_GPIO_2_PD -#define GLB_REG_GPIO_2_PD_POS (5U) -#define GLB_REG_GPIO_2_PD_LEN (1U) +#define GLB_REG_GPIO_2_PD_POS (5) +#define GLB_REG_GPIO_2_PD_LEN (1) #define GLB_REG_GPIO_2_PD_MSK \ - (((1U << GLB_REG_GPIO_2_PD_LEN) - 1) << GLB_REG_GPIO_2_PD_POS) + (((1 << GLB_REG_GPIO_2_PD_LEN) - 1) << GLB_REG_GPIO_2_PD_POS) #define GLB_REG_GPIO_2_PD_UMSK \ - (~(((1U << GLB_REG_GPIO_2_PD_LEN) - 1) << GLB_REG_GPIO_2_PD_POS)) + (~(((1 << GLB_REG_GPIO_2_PD_LEN) - 1) << GLB_REG_GPIO_2_PD_POS)) #define GLB_REG_GPIO_2_FUNC_SEL GLB_REG_GPIO_2_FUNC_SEL -#define GLB_REG_GPIO_2_FUNC_SEL_POS (8U) -#define GLB_REG_GPIO_2_FUNC_SEL_LEN (4U) +#define GLB_REG_GPIO_2_FUNC_SEL_POS (8) +#define GLB_REG_GPIO_2_FUNC_SEL_LEN (4) #define GLB_REG_GPIO_2_FUNC_SEL_MSK \ - (((1U << GLB_REG_GPIO_2_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_2_FUNC_SEL_POS) + (((1 << GLB_REG_GPIO_2_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_2_FUNC_SEL_POS) #define GLB_REG_GPIO_2_FUNC_SEL_UMSK \ - (~(((1U << GLB_REG_GPIO_2_FUNC_SEL_LEN) - 1) \ - << GLB_REG_GPIO_2_FUNC_SEL_POS)) + (~(((1 << GLB_REG_GPIO_2_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_2_FUNC_SEL_POS)) #define GLB_REAL_GPIO_2_FUNC_SEL GLB_REAL_GPIO_2_FUNC_SEL -#define GLB_REAL_GPIO_2_FUNC_SEL_POS (12U) -#define GLB_REAL_GPIO_2_FUNC_SEL_LEN (4U) +#define GLB_REAL_GPIO_2_FUNC_SEL_POS (12) +#define GLB_REAL_GPIO_2_FUNC_SEL_LEN (4) #define GLB_REAL_GPIO_2_FUNC_SEL_MSK \ - (((1U << GLB_REAL_GPIO_2_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_2_FUNC_SEL_POS) + (((1 << GLB_REAL_GPIO_2_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_2_FUNC_SEL_POS) #define GLB_REAL_GPIO_2_FUNC_SEL_UMSK \ - (~(((1U << GLB_REAL_GPIO_2_FUNC_SEL_LEN) - 1) \ + (~(((1 << GLB_REAL_GPIO_2_FUNC_SEL_LEN) - 1) \ << GLB_REAL_GPIO_2_FUNC_SEL_POS)) #define GLB_REG_GPIO_3_IE GLB_REG_GPIO_3_IE -#define GLB_REG_GPIO_3_IE_POS (16U) -#define GLB_REG_GPIO_3_IE_LEN (1U) +#define GLB_REG_GPIO_3_IE_POS (16) +#define GLB_REG_GPIO_3_IE_LEN (1) #define GLB_REG_GPIO_3_IE_MSK \ - (((1U << GLB_REG_GPIO_3_IE_LEN) - 1) << GLB_REG_GPIO_3_IE_POS) + (((1 << GLB_REG_GPIO_3_IE_LEN) - 1) << GLB_REG_GPIO_3_IE_POS) #define GLB_REG_GPIO_3_IE_UMSK \ - (~(((1U << GLB_REG_GPIO_3_IE_LEN) - 1) << GLB_REG_GPIO_3_IE_POS)) + (~(((1 << GLB_REG_GPIO_3_IE_LEN) - 1) << GLB_REG_GPIO_3_IE_POS)) #define GLB_REG_GPIO_3_SMT GLB_REG_GPIO_3_SMT -#define GLB_REG_GPIO_3_SMT_POS (17U) -#define GLB_REG_GPIO_3_SMT_LEN (1U) +#define GLB_REG_GPIO_3_SMT_POS (17) +#define GLB_REG_GPIO_3_SMT_LEN (1) #define GLB_REG_GPIO_3_SMT_MSK \ - (((1U << GLB_REG_GPIO_3_SMT_LEN) - 1) << GLB_REG_GPIO_3_SMT_POS) + (((1 << GLB_REG_GPIO_3_SMT_LEN) - 1) << GLB_REG_GPIO_3_SMT_POS) #define GLB_REG_GPIO_3_SMT_UMSK \ - (~(((1U << GLB_REG_GPIO_3_SMT_LEN) - 1) << GLB_REG_GPIO_3_SMT_POS)) + (~(((1 << GLB_REG_GPIO_3_SMT_LEN) - 1) << GLB_REG_GPIO_3_SMT_POS)) #define GLB_REG_GPIO_3_DRV GLB_REG_GPIO_3_DRV -#define GLB_REG_GPIO_3_DRV_POS (18U) -#define GLB_REG_GPIO_3_DRV_LEN (2U) +#define GLB_REG_GPIO_3_DRV_POS (18) +#define GLB_REG_GPIO_3_DRV_LEN (2) #define GLB_REG_GPIO_3_DRV_MSK \ - (((1U << GLB_REG_GPIO_3_DRV_LEN) - 1) << GLB_REG_GPIO_3_DRV_POS) + (((1 << GLB_REG_GPIO_3_DRV_LEN) - 1) << GLB_REG_GPIO_3_DRV_POS) #define GLB_REG_GPIO_3_DRV_UMSK \ - (~(((1U << GLB_REG_GPIO_3_DRV_LEN) - 1) << GLB_REG_GPIO_3_DRV_POS)) + (~(((1 << GLB_REG_GPIO_3_DRV_LEN) - 1) << GLB_REG_GPIO_3_DRV_POS)) #define GLB_REG_GPIO_3_PU GLB_REG_GPIO_3_PU -#define GLB_REG_GPIO_3_PU_POS (20U) -#define GLB_REG_GPIO_3_PU_LEN (1U) +#define GLB_REG_GPIO_3_PU_POS (20) +#define GLB_REG_GPIO_3_PU_LEN (1) #define GLB_REG_GPIO_3_PU_MSK \ - (((1U << GLB_REG_GPIO_3_PU_LEN) - 1) << GLB_REG_GPIO_3_PU_POS) + (((1 << GLB_REG_GPIO_3_PU_LEN) - 1) << GLB_REG_GPIO_3_PU_POS) #define GLB_REG_GPIO_3_PU_UMSK \ - (~(((1U << GLB_REG_GPIO_3_PU_LEN) - 1) << GLB_REG_GPIO_3_PU_POS)) + (~(((1 << GLB_REG_GPIO_3_PU_LEN) - 1) << GLB_REG_GPIO_3_PU_POS)) #define GLB_REG_GPIO_3_PD GLB_REG_GPIO_3_PD -#define GLB_REG_GPIO_3_PD_POS (21U) -#define GLB_REG_GPIO_3_PD_LEN (1U) +#define GLB_REG_GPIO_3_PD_POS (21) +#define GLB_REG_GPIO_3_PD_LEN (1) #define GLB_REG_GPIO_3_PD_MSK \ - (((1U << GLB_REG_GPIO_3_PD_LEN) - 1) << GLB_REG_GPIO_3_PD_POS) + (((1 << GLB_REG_GPIO_3_PD_LEN) - 1) << GLB_REG_GPIO_3_PD_POS) #define GLB_REG_GPIO_3_PD_UMSK \ - (~(((1U << GLB_REG_GPIO_3_PD_LEN) - 1) << GLB_REG_GPIO_3_PD_POS)) + (~(((1 << GLB_REG_GPIO_3_PD_LEN) - 1) << GLB_REG_GPIO_3_PD_POS)) #define GLB_REG_GPIO_3_FUNC_SEL GLB_REG_GPIO_3_FUNC_SEL -#define GLB_REG_GPIO_3_FUNC_SEL_POS (24U) -#define GLB_REG_GPIO_3_FUNC_SEL_LEN (4U) +#define GLB_REG_GPIO_3_FUNC_SEL_POS (24) +#define GLB_REG_GPIO_3_FUNC_SEL_LEN (4) #define GLB_REG_GPIO_3_FUNC_SEL_MSK \ - (((1U << GLB_REG_GPIO_3_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_3_FUNC_SEL_POS) + (((1 << GLB_REG_GPIO_3_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_3_FUNC_SEL_POS) #define GLB_REG_GPIO_3_FUNC_SEL_UMSK \ - (~(((1U << GLB_REG_GPIO_3_FUNC_SEL_LEN) - 1) \ - << GLB_REG_GPIO_3_FUNC_SEL_POS)) + (~(((1 << GLB_REG_GPIO_3_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_3_FUNC_SEL_POS)) #define GLB_REAL_GPIO_3_FUNC_SEL GLB_REAL_GPIO_3_FUNC_SEL -#define GLB_REAL_GPIO_3_FUNC_SEL_POS (28U) -#define GLB_REAL_GPIO_3_FUNC_SEL_LEN (4U) +#define GLB_REAL_GPIO_3_FUNC_SEL_POS (28) +#define GLB_REAL_GPIO_3_FUNC_SEL_LEN (4) #define GLB_REAL_GPIO_3_FUNC_SEL_MSK \ - (((1U << GLB_REAL_GPIO_3_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_3_FUNC_SEL_POS) + (((1 << GLB_REAL_GPIO_3_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_3_FUNC_SEL_POS) #define GLB_REAL_GPIO_3_FUNC_SEL_UMSK \ - (~(((1U << GLB_REAL_GPIO_3_FUNC_SEL_LEN) - 1) \ + (~(((1 << GLB_REAL_GPIO_3_FUNC_SEL_LEN) - 1) \ << GLB_REAL_GPIO_3_FUNC_SEL_POS)) /* 0x108 : GPIO_CFGCTL2 */ #define GLB_GPIO_CFGCTL2_OFFSET (0x108) #define GLB_REG_GPIO_4_IE GLB_REG_GPIO_4_IE -#define GLB_REG_GPIO_4_IE_POS (0U) -#define GLB_REG_GPIO_4_IE_LEN (1U) +#define GLB_REG_GPIO_4_IE_POS (0) +#define GLB_REG_GPIO_4_IE_LEN (1) #define GLB_REG_GPIO_4_IE_MSK \ - (((1U << GLB_REG_GPIO_4_IE_LEN) - 1) << GLB_REG_GPIO_4_IE_POS) + (((1 << GLB_REG_GPIO_4_IE_LEN) - 1) << GLB_REG_GPIO_4_IE_POS) #define GLB_REG_GPIO_4_IE_UMSK \ - (~(((1U << GLB_REG_GPIO_4_IE_LEN) - 1) << GLB_REG_GPIO_4_IE_POS)) + (~(((1 << GLB_REG_GPIO_4_IE_LEN) - 1) << GLB_REG_GPIO_4_IE_POS)) #define GLB_REG_GPIO_4_SMT GLB_REG_GPIO_4_SMT -#define GLB_REG_GPIO_4_SMT_POS (1U) -#define GLB_REG_GPIO_4_SMT_LEN (1U) +#define GLB_REG_GPIO_4_SMT_POS (1) +#define GLB_REG_GPIO_4_SMT_LEN (1) #define GLB_REG_GPIO_4_SMT_MSK \ - (((1U << GLB_REG_GPIO_4_SMT_LEN) - 1) << GLB_REG_GPIO_4_SMT_POS) + (((1 << GLB_REG_GPIO_4_SMT_LEN) - 1) << GLB_REG_GPIO_4_SMT_POS) #define GLB_REG_GPIO_4_SMT_UMSK \ - (~(((1U << GLB_REG_GPIO_4_SMT_LEN) - 1) << GLB_REG_GPIO_4_SMT_POS)) + (~(((1 << GLB_REG_GPIO_4_SMT_LEN) - 1) << GLB_REG_GPIO_4_SMT_POS)) #define GLB_REG_GPIO_4_DRV GLB_REG_GPIO_4_DRV -#define GLB_REG_GPIO_4_DRV_POS (2U) -#define GLB_REG_GPIO_4_DRV_LEN (2U) +#define GLB_REG_GPIO_4_DRV_POS (2) +#define GLB_REG_GPIO_4_DRV_LEN (2) #define GLB_REG_GPIO_4_DRV_MSK \ - (((1U << GLB_REG_GPIO_4_DRV_LEN) - 1) << GLB_REG_GPIO_4_DRV_POS) + (((1 << GLB_REG_GPIO_4_DRV_LEN) - 1) << GLB_REG_GPIO_4_DRV_POS) #define GLB_REG_GPIO_4_DRV_UMSK \ - (~(((1U << GLB_REG_GPIO_4_DRV_LEN) - 1) << GLB_REG_GPIO_4_DRV_POS)) + (~(((1 << GLB_REG_GPIO_4_DRV_LEN) - 1) << GLB_REG_GPIO_4_DRV_POS)) #define GLB_REG_GPIO_4_PU GLB_REG_GPIO_4_PU -#define GLB_REG_GPIO_4_PU_POS (4U) -#define GLB_REG_GPIO_4_PU_LEN (1U) +#define GLB_REG_GPIO_4_PU_POS (4) +#define GLB_REG_GPIO_4_PU_LEN (1) #define GLB_REG_GPIO_4_PU_MSK \ - (((1U << GLB_REG_GPIO_4_PU_LEN) - 1) << GLB_REG_GPIO_4_PU_POS) + (((1 << GLB_REG_GPIO_4_PU_LEN) - 1) << GLB_REG_GPIO_4_PU_POS) #define GLB_REG_GPIO_4_PU_UMSK \ - (~(((1U << GLB_REG_GPIO_4_PU_LEN) - 1) << GLB_REG_GPIO_4_PU_POS)) + (~(((1 << GLB_REG_GPIO_4_PU_LEN) - 1) << GLB_REG_GPIO_4_PU_POS)) #define GLB_REG_GPIO_4_PD GLB_REG_GPIO_4_PD -#define GLB_REG_GPIO_4_PD_POS (5U) -#define GLB_REG_GPIO_4_PD_LEN (1U) +#define GLB_REG_GPIO_4_PD_POS (5) +#define GLB_REG_GPIO_4_PD_LEN (1) #define GLB_REG_GPIO_4_PD_MSK \ - (((1U << GLB_REG_GPIO_4_PD_LEN) - 1) << GLB_REG_GPIO_4_PD_POS) + (((1 << GLB_REG_GPIO_4_PD_LEN) - 1) << GLB_REG_GPIO_4_PD_POS) #define GLB_REG_GPIO_4_PD_UMSK \ - (~(((1U << GLB_REG_GPIO_4_PD_LEN) - 1) << GLB_REG_GPIO_4_PD_POS)) + (~(((1 << GLB_REG_GPIO_4_PD_LEN) - 1) << GLB_REG_GPIO_4_PD_POS)) #define GLB_REG_GPIO_4_FUNC_SEL GLB_REG_GPIO_4_FUNC_SEL -#define GLB_REG_GPIO_4_FUNC_SEL_POS (8U) -#define GLB_REG_GPIO_4_FUNC_SEL_LEN (4U) +#define GLB_REG_GPIO_4_FUNC_SEL_POS (8) +#define GLB_REG_GPIO_4_FUNC_SEL_LEN (4) #define GLB_REG_GPIO_4_FUNC_SEL_MSK \ - (((1U << GLB_REG_GPIO_4_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_4_FUNC_SEL_POS) + (((1 << GLB_REG_GPIO_4_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_4_FUNC_SEL_POS) #define GLB_REG_GPIO_4_FUNC_SEL_UMSK \ - (~(((1U << GLB_REG_GPIO_4_FUNC_SEL_LEN) - 1) \ - << GLB_REG_GPIO_4_FUNC_SEL_POS)) + (~(((1 << GLB_REG_GPIO_4_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_4_FUNC_SEL_POS)) #define GLB_REAL_GPIO_4_FUNC_SEL GLB_REAL_GPIO_4_FUNC_SEL -#define GLB_REAL_GPIO_4_FUNC_SEL_POS (12U) -#define GLB_REAL_GPIO_4_FUNC_SEL_LEN (4U) +#define GLB_REAL_GPIO_4_FUNC_SEL_POS (12) +#define GLB_REAL_GPIO_4_FUNC_SEL_LEN (4) #define GLB_REAL_GPIO_4_FUNC_SEL_MSK \ - (((1U << GLB_REAL_GPIO_4_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_4_FUNC_SEL_POS) + (((1 << GLB_REAL_GPIO_4_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_4_FUNC_SEL_POS) #define GLB_REAL_GPIO_4_FUNC_SEL_UMSK \ - (~(((1U << GLB_REAL_GPIO_4_FUNC_SEL_LEN) - 1) \ + (~(((1 << GLB_REAL_GPIO_4_FUNC_SEL_LEN) - 1) \ << GLB_REAL_GPIO_4_FUNC_SEL_POS)) #define GLB_REG_GPIO_5_IE GLB_REG_GPIO_5_IE -#define GLB_REG_GPIO_5_IE_POS (16U) -#define GLB_REG_GPIO_5_IE_LEN (1U) +#define GLB_REG_GPIO_5_IE_POS (16) +#define GLB_REG_GPIO_5_IE_LEN (1) #define GLB_REG_GPIO_5_IE_MSK \ - (((1U << GLB_REG_GPIO_5_IE_LEN) - 1) << GLB_REG_GPIO_5_IE_POS) + (((1 << GLB_REG_GPIO_5_IE_LEN) - 1) << GLB_REG_GPIO_5_IE_POS) #define GLB_REG_GPIO_5_IE_UMSK \ - (~(((1U << GLB_REG_GPIO_5_IE_LEN) - 1) << GLB_REG_GPIO_5_IE_POS)) + (~(((1 << GLB_REG_GPIO_5_IE_LEN) - 1) << GLB_REG_GPIO_5_IE_POS)) #define GLB_REG_GPIO_5_SMT GLB_REG_GPIO_5_SMT -#define GLB_REG_GPIO_5_SMT_POS (17U) -#define GLB_REG_GPIO_5_SMT_LEN (1U) +#define GLB_REG_GPIO_5_SMT_POS (17) +#define GLB_REG_GPIO_5_SMT_LEN (1) #define GLB_REG_GPIO_5_SMT_MSK \ - (((1U << GLB_REG_GPIO_5_SMT_LEN) - 1) << GLB_REG_GPIO_5_SMT_POS) + (((1 << GLB_REG_GPIO_5_SMT_LEN) - 1) << GLB_REG_GPIO_5_SMT_POS) #define GLB_REG_GPIO_5_SMT_UMSK \ - (~(((1U << GLB_REG_GPIO_5_SMT_LEN) - 1) << GLB_REG_GPIO_5_SMT_POS)) + (~(((1 << GLB_REG_GPIO_5_SMT_LEN) - 1) << GLB_REG_GPIO_5_SMT_POS)) #define GLB_REG_GPIO_5_DRV GLB_REG_GPIO_5_DRV -#define GLB_REG_GPIO_5_DRV_POS (18U) -#define GLB_REG_GPIO_5_DRV_LEN (2U) +#define GLB_REG_GPIO_5_DRV_POS (18) +#define GLB_REG_GPIO_5_DRV_LEN (2) #define GLB_REG_GPIO_5_DRV_MSK \ - (((1U << GLB_REG_GPIO_5_DRV_LEN) - 1) << GLB_REG_GPIO_5_DRV_POS) + (((1 << GLB_REG_GPIO_5_DRV_LEN) - 1) << GLB_REG_GPIO_5_DRV_POS) #define GLB_REG_GPIO_5_DRV_UMSK \ - (~(((1U << GLB_REG_GPIO_5_DRV_LEN) - 1) << GLB_REG_GPIO_5_DRV_POS)) + (~(((1 << GLB_REG_GPIO_5_DRV_LEN) - 1) << GLB_REG_GPIO_5_DRV_POS)) #define GLB_REG_GPIO_5_PU GLB_REG_GPIO_5_PU -#define GLB_REG_GPIO_5_PU_POS (20U) -#define GLB_REG_GPIO_5_PU_LEN (1U) +#define GLB_REG_GPIO_5_PU_POS (20) +#define GLB_REG_GPIO_5_PU_LEN (1) #define GLB_REG_GPIO_5_PU_MSK \ - (((1U << GLB_REG_GPIO_5_PU_LEN) - 1) << GLB_REG_GPIO_5_PU_POS) + (((1 << GLB_REG_GPIO_5_PU_LEN) - 1) << GLB_REG_GPIO_5_PU_POS) #define GLB_REG_GPIO_5_PU_UMSK \ - (~(((1U << GLB_REG_GPIO_5_PU_LEN) - 1) << GLB_REG_GPIO_5_PU_POS)) + (~(((1 << GLB_REG_GPIO_5_PU_LEN) - 1) << GLB_REG_GPIO_5_PU_POS)) #define GLB_REG_GPIO_5_PD GLB_REG_GPIO_5_PD -#define GLB_REG_GPIO_5_PD_POS (21U) -#define GLB_REG_GPIO_5_PD_LEN (1U) +#define GLB_REG_GPIO_5_PD_POS (21) +#define GLB_REG_GPIO_5_PD_LEN (1) #define GLB_REG_GPIO_5_PD_MSK \ - (((1U << GLB_REG_GPIO_5_PD_LEN) - 1) << GLB_REG_GPIO_5_PD_POS) + (((1 << GLB_REG_GPIO_5_PD_LEN) - 1) << GLB_REG_GPIO_5_PD_POS) #define GLB_REG_GPIO_5_PD_UMSK \ - (~(((1U << GLB_REG_GPIO_5_PD_LEN) - 1) << GLB_REG_GPIO_5_PD_POS)) + (~(((1 << GLB_REG_GPIO_5_PD_LEN) - 1) << GLB_REG_GPIO_5_PD_POS)) #define GLB_REG_GPIO_5_FUNC_SEL GLB_REG_GPIO_5_FUNC_SEL -#define GLB_REG_GPIO_5_FUNC_SEL_POS (24U) -#define GLB_REG_GPIO_5_FUNC_SEL_LEN (4U) +#define GLB_REG_GPIO_5_FUNC_SEL_POS (24) +#define GLB_REG_GPIO_5_FUNC_SEL_LEN (4) #define GLB_REG_GPIO_5_FUNC_SEL_MSK \ - (((1U << GLB_REG_GPIO_5_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_5_FUNC_SEL_POS) + (((1 << GLB_REG_GPIO_5_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_5_FUNC_SEL_POS) #define GLB_REG_GPIO_5_FUNC_SEL_UMSK \ - (~(((1U << GLB_REG_GPIO_5_FUNC_SEL_LEN) - 1) \ - << GLB_REG_GPIO_5_FUNC_SEL_POS)) + (~(((1 << GLB_REG_GPIO_5_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_5_FUNC_SEL_POS)) #define GLB_REAL_GPIO_5_FUNC_SEL GLB_REAL_GPIO_5_FUNC_SEL -#define GLB_REAL_GPIO_5_FUNC_SEL_POS (28U) -#define GLB_REAL_GPIO_5_FUNC_SEL_LEN (4U) +#define GLB_REAL_GPIO_5_FUNC_SEL_POS (28) +#define GLB_REAL_GPIO_5_FUNC_SEL_LEN (4) #define GLB_REAL_GPIO_5_FUNC_SEL_MSK \ - (((1U << GLB_REAL_GPIO_5_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_5_FUNC_SEL_POS) + (((1 << GLB_REAL_GPIO_5_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_5_FUNC_SEL_POS) #define GLB_REAL_GPIO_5_FUNC_SEL_UMSK \ - (~(((1U << GLB_REAL_GPIO_5_FUNC_SEL_LEN) - 1) \ + (~(((1 << GLB_REAL_GPIO_5_FUNC_SEL_LEN) - 1) \ << GLB_REAL_GPIO_5_FUNC_SEL_POS)) /* 0x10C : GPIO_CFGCTL3 */ #define GLB_GPIO_CFGCTL3_OFFSET (0x10C) #define GLB_REG_GPIO_6_IE GLB_REG_GPIO_6_IE -#define GLB_REG_GPIO_6_IE_POS (0U) -#define GLB_REG_GPIO_6_IE_LEN (1U) +#define GLB_REG_GPIO_6_IE_POS (0) +#define GLB_REG_GPIO_6_IE_LEN (1) #define GLB_REG_GPIO_6_IE_MSK \ - (((1U << GLB_REG_GPIO_6_IE_LEN) - 1) << GLB_REG_GPIO_6_IE_POS) + (((1 << GLB_REG_GPIO_6_IE_LEN) - 1) << GLB_REG_GPIO_6_IE_POS) #define GLB_REG_GPIO_6_IE_UMSK \ - (~(((1U << GLB_REG_GPIO_6_IE_LEN) - 1) << GLB_REG_GPIO_6_IE_POS)) + (~(((1 << GLB_REG_GPIO_6_IE_LEN) - 1) << GLB_REG_GPIO_6_IE_POS)) #define GLB_REG_GPIO_6_SMT GLB_REG_GPIO_6_SMT -#define GLB_REG_GPIO_6_SMT_POS (1U) -#define GLB_REG_GPIO_6_SMT_LEN (1U) +#define GLB_REG_GPIO_6_SMT_POS (1) +#define GLB_REG_GPIO_6_SMT_LEN (1) #define GLB_REG_GPIO_6_SMT_MSK \ - (((1U << GLB_REG_GPIO_6_SMT_LEN) - 1) << GLB_REG_GPIO_6_SMT_POS) + (((1 << GLB_REG_GPIO_6_SMT_LEN) - 1) << GLB_REG_GPIO_6_SMT_POS) #define GLB_REG_GPIO_6_SMT_UMSK \ - (~(((1U << GLB_REG_GPIO_6_SMT_LEN) - 1) << GLB_REG_GPIO_6_SMT_POS)) + (~(((1 << GLB_REG_GPIO_6_SMT_LEN) - 1) << GLB_REG_GPIO_6_SMT_POS)) #define GLB_REG_GPIO_6_DRV GLB_REG_GPIO_6_DRV -#define GLB_REG_GPIO_6_DRV_POS (2U) -#define GLB_REG_GPIO_6_DRV_LEN (2U) +#define GLB_REG_GPIO_6_DRV_POS (2) +#define GLB_REG_GPIO_6_DRV_LEN (2) #define GLB_REG_GPIO_6_DRV_MSK \ - (((1U << GLB_REG_GPIO_6_DRV_LEN) - 1) << GLB_REG_GPIO_6_DRV_POS) + (((1 << GLB_REG_GPIO_6_DRV_LEN) - 1) << GLB_REG_GPIO_6_DRV_POS) #define GLB_REG_GPIO_6_DRV_UMSK \ - (~(((1U << GLB_REG_GPIO_6_DRV_LEN) - 1) << GLB_REG_GPIO_6_DRV_POS)) + (~(((1 << GLB_REG_GPIO_6_DRV_LEN) - 1) << GLB_REG_GPIO_6_DRV_POS)) #define GLB_REG_GPIO_6_PU GLB_REG_GPIO_6_PU -#define GLB_REG_GPIO_6_PU_POS (4U) -#define GLB_REG_GPIO_6_PU_LEN (1U) +#define GLB_REG_GPIO_6_PU_POS (4) +#define GLB_REG_GPIO_6_PU_LEN (1) #define GLB_REG_GPIO_6_PU_MSK \ - (((1U << GLB_REG_GPIO_6_PU_LEN) - 1) << GLB_REG_GPIO_6_PU_POS) + (((1 << GLB_REG_GPIO_6_PU_LEN) - 1) << GLB_REG_GPIO_6_PU_POS) #define GLB_REG_GPIO_6_PU_UMSK \ - (~(((1U << GLB_REG_GPIO_6_PU_LEN) - 1) << GLB_REG_GPIO_6_PU_POS)) + (~(((1 << GLB_REG_GPIO_6_PU_LEN) - 1) << GLB_REG_GPIO_6_PU_POS)) #define GLB_REG_GPIO_6_PD GLB_REG_GPIO_6_PD -#define GLB_REG_GPIO_6_PD_POS (5U) -#define GLB_REG_GPIO_6_PD_LEN (1U) +#define GLB_REG_GPIO_6_PD_POS (5) +#define GLB_REG_GPIO_6_PD_LEN (1) #define GLB_REG_GPIO_6_PD_MSK \ - (((1U << GLB_REG_GPIO_6_PD_LEN) - 1) << GLB_REG_GPIO_6_PD_POS) + (((1 << GLB_REG_GPIO_6_PD_LEN) - 1) << GLB_REG_GPIO_6_PD_POS) #define GLB_REG_GPIO_6_PD_UMSK \ - (~(((1U << GLB_REG_GPIO_6_PD_LEN) - 1) << GLB_REG_GPIO_6_PD_POS)) + (~(((1 << GLB_REG_GPIO_6_PD_LEN) - 1) << GLB_REG_GPIO_6_PD_POS)) #define GLB_REG_GPIO_6_FUNC_SEL GLB_REG_GPIO_6_FUNC_SEL -#define GLB_REG_GPIO_6_FUNC_SEL_POS (8U) -#define GLB_REG_GPIO_6_FUNC_SEL_LEN (4U) +#define GLB_REG_GPIO_6_FUNC_SEL_POS (8) +#define GLB_REG_GPIO_6_FUNC_SEL_LEN (4) #define GLB_REG_GPIO_6_FUNC_SEL_MSK \ - (((1U << GLB_REG_GPIO_6_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_6_FUNC_SEL_POS) + (((1 << GLB_REG_GPIO_6_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_6_FUNC_SEL_POS) #define GLB_REG_GPIO_6_FUNC_SEL_UMSK \ - (~(((1U << GLB_REG_GPIO_6_FUNC_SEL_LEN) - 1) \ - << GLB_REG_GPIO_6_FUNC_SEL_POS)) + (~(((1 << GLB_REG_GPIO_6_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_6_FUNC_SEL_POS)) #define GLB_REG_GPIO_7_IE GLB_REG_GPIO_7_IE -#define GLB_REG_GPIO_7_IE_POS (16U) -#define GLB_REG_GPIO_7_IE_LEN (1U) +#define GLB_REG_GPIO_7_IE_POS (16) +#define GLB_REG_GPIO_7_IE_LEN (1) #define GLB_REG_GPIO_7_IE_MSK \ - (((1U << GLB_REG_GPIO_7_IE_LEN) - 1) << GLB_REG_GPIO_7_IE_POS) + (((1 << GLB_REG_GPIO_7_IE_LEN) - 1) << GLB_REG_GPIO_7_IE_POS) #define GLB_REG_GPIO_7_IE_UMSK \ - (~(((1U << GLB_REG_GPIO_7_IE_LEN) - 1) << GLB_REG_GPIO_7_IE_POS)) + (~(((1 << GLB_REG_GPIO_7_IE_LEN) - 1) << GLB_REG_GPIO_7_IE_POS)) #define GLB_REG_GPIO_7_SMT GLB_REG_GPIO_7_SMT -#define GLB_REG_GPIO_7_SMT_POS (17U) -#define GLB_REG_GPIO_7_SMT_LEN (1U) +#define GLB_REG_GPIO_7_SMT_POS (17) +#define GLB_REG_GPIO_7_SMT_LEN (1) #define GLB_REG_GPIO_7_SMT_MSK \ - (((1U << GLB_REG_GPIO_7_SMT_LEN) - 1) << GLB_REG_GPIO_7_SMT_POS) + (((1 << GLB_REG_GPIO_7_SMT_LEN) - 1) << GLB_REG_GPIO_7_SMT_POS) #define GLB_REG_GPIO_7_SMT_UMSK \ - (~(((1U << GLB_REG_GPIO_7_SMT_LEN) - 1) << GLB_REG_GPIO_7_SMT_POS)) + (~(((1 << GLB_REG_GPIO_7_SMT_LEN) - 1) << GLB_REG_GPIO_7_SMT_POS)) #define GLB_REG_GPIO_7_DRV GLB_REG_GPIO_7_DRV -#define GLB_REG_GPIO_7_DRV_POS (18U) -#define GLB_REG_GPIO_7_DRV_LEN (2U) +#define GLB_REG_GPIO_7_DRV_POS (18) +#define GLB_REG_GPIO_7_DRV_LEN (2) #define GLB_REG_GPIO_7_DRV_MSK \ - (((1U << GLB_REG_GPIO_7_DRV_LEN) - 1) << GLB_REG_GPIO_7_DRV_POS) + (((1 << GLB_REG_GPIO_7_DRV_LEN) - 1) << GLB_REG_GPIO_7_DRV_POS) #define GLB_REG_GPIO_7_DRV_UMSK \ - (~(((1U << GLB_REG_GPIO_7_DRV_LEN) - 1) << GLB_REG_GPIO_7_DRV_POS)) + (~(((1 << GLB_REG_GPIO_7_DRV_LEN) - 1) << GLB_REG_GPIO_7_DRV_POS)) #define GLB_REG_GPIO_7_PU GLB_REG_GPIO_7_PU -#define GLB_REG_GPIO_7_PU_POS (20U) -#define GLB_REG_GPIO_7_PU_LEN (1U) +#define GLB_REG_GPIO_7_PU_POS (20) +#define GLB_REG_GPIO_7_PU_LEN (1) #define GLB_REG_GPIO_7_PU_MSK \ - (((1U << GLB_REG_GPIO_7_PU_LEN) - 1) << GLB_REG_GPIO_7_PU_POS) + (((1 << GLB_REG_GPIO_7_PU_LEN) - 1) << GLB_REG_GPIO_7_PU_POS) #define GLB_REG_GPIO_7_PU_UMSK \ - (~(((1U << GLB_REG_GPIO_7_PU_LEN) - 1) << GLB_REG_GPIO_7_PU_POS)) + (~(((1 << GLB_REG_GPIO_7_PU_LEN) - 1) << GLB_REG_GPIO_7_PU_POS)) #define GLB_REG_GPIO_7_PD GLB_REG_GPIO_7_PD -#define GLB_REG_GPIO_7_PD_POS (21U) -#define GLB_REG_GPIO_7_PD_LEN (1U) +#define GLB_REG_GPIO_7_PD_POS (21) +#define GLB_REG_GPIO_7_PD_LEN (1) #define GLB_REG_GPIO_7_PD_MSK \ - (((1U << GLB_REG_GPIO_7_PD_LEN) - 1) << GLB_REG_GPIO_7_PD_POS) + (((1 << GLB_REG_GPIO_7_PD_LEN) - 1) << GLB_REG_GPIO_7_PD_POS) #define GLB_REG_GPIO_7_PD_UMSK \ - (~(((1U << GLB_REG_GPIO_7_PD_LEN) - 1) << GLB_REG_GPIO_7_PD_POS)) + (~(((1 << GLB_REG_GPIO_7_PD_LEN) - 1) << GLB_REG_GPIO_7_PD_POS)) #define GLB_REG_GPIO_7_FUNC_SEL GLB_REG_GPIO_7_FUNC_SEL -#define GLB_REG_GPIO_7_FUNC_SEL_POS (24U) -#define GLB_REG_GPIO_7_FUNC_SEL_LEN (4U) +#define GLB_REG_GPIO_7_FUNC_SEL_POS (24) +#define GLB_REG_GPIO_7_FUNC_SEL_LEN (4) #define GLB_REG_GPIO_7_FUNC_SEL_MSK \ - (((1U << GLB_REG_GPIO_7_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_7_FUNC_SEL_POS) + (((1 << GLB_REG_GPIO_7_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_7_FUNC_SEL_POS) #define GLB_REG_GPIO_7_FUNC_SEL_UMSK \ - (~(((1U << GLB_REG_GPIO_7_FUNC_SEL_LEN) - 1) \ - << GLB_REG_GPIO_7_FUNC_SEL_POS)) + (~(((1 << GLB_REG_GPIO_7_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_7_FUNC_SEL_POS)) /* 0x110 : GPIO_CFGCTL4 */ #define GLB_GPIO_CFGCTL4_OFFSET (0x110) #define GLB_REG_GPIO_8_IE GLB_REG_GPIO_8_IE -#define GLB_REG_GPIO_8_IE_POS (0U) -#define GLB_REG_GPIO_8_IE_LEN (1U) +#define GLB_REG_GPIO_8_IE_POS (0) +#define GLB_REG_GPIO_8_IE_LEN (1) #define GLB_REG_GPIO_8_IE_MSK \ - (((1U << GLB_REG_GPIO_8_IE_LEN) - 1) << GLB_REG_GPIO_8_IE_POS) + (((1 << GLB_REG_GPIO_8_IE_LEN) - 1) << GLB_REG_GPIO_8_IE_POS) #define GLB_REG_GPIO_8_IE_UMSK \ - (~(((1U << GLB_REG_GPIO_8_IE_LEN) - 1) << GLB_REG_GPIO_8_IE_POS)) + (~(((1 << GLB_REG_GPIO_8_IE_LEN) - 1) << GLB_REG_GPIO_8_IE_POS)) #define GLB_REG_GPIO_8_SMT GLB_REG_GPIO_8_SMT -#define GLB_REG_GPIO_8_SMT_POS (1U) -#define GLB_REG_GPIO_8_SMT_LEN (1U) +#define GLB_REG_GPIO_8_SMT_POS (1) +#define GLB_REG_GPIO_8_SMT_LEN (1) #define GLB_REG_GPIO_8_SMT_MSK \ - (((1U << GLB_REG_GPIO_8_SMT_LEN) - 1) << GLB_REG_GPIO_8_SMT_POS) + (((1 << GLB_REG_GPIO_8_SMT_LEN) - 1) << GLB_REG_GPIO_8_SMT_POS) #define GLB_REG_GPIO_8_SMT_UMSK \ - (~(((1U << GLB_REG_GPIO_8_SMT_LEN) - 1) << GLB_REG_GPIO_8_SMT_POS)) + (~(((1 << GLB_REG_GPIO_8_SMT_LEN) - 1) << GLB_REG_GPIO_8_SMT_POS)) #define GLB_REG_GPIO_8_DRV GLB_REG_GPIO_8_DRV -#define GLB_REG_GPIO_8_DRV_POS (2U) -#define GLB_REG_GPIO_8_DRV_LEN (2U) +#define GLB_REG_GPIO_8_DRV_POS (2) +#define GLB_REG_GPIO_8_DRV_LEN (2) #define GLB_REG_GPIO_8_DRV_MSK \ - (((1U << GLB_REG_GPIO_8_DRV_LEN) - 1) << GLB_REG_GPIO_8_DRV_POS) + (((1 << GLB_REG_GPIO_8_DRV_LEN) - 1) << GLB_REG_GPIO_8_DRV_POS) #define GLB_REG_GPIO_8_DRV_UMSK \ - (~(((1U << GLB_REG_GPIO_8_DRV_LEN) - 1) << GLB_REG_GPIO_8_DRV_POS)) + (~(((1 << GLB_REG_GPIO_8_DRV_LEN) - 1) << GLB_REG_GPIO_8_DRV_POS)) #define GLB_REG_GPIO_8_PU GLB_REG_GPIO_8_PU -#define GLB_REG_GPIO_8_PU_POS (4U) -#define GLB_REG_GPIO_8_PU_LEN (1U) +#define GLB_REG_GPIO_8_PU_POS (4) +#define GLB_REG_GPIO_8_PU_LEN (1) #define GLB_REG_GPIO_8_PU_MSK \ - (((1U << GLB_REG_GPIO_8_PU_LEN) - 1) << GLB_REG_GPIO_8_PU_POS) + (((1 << GLB_REG_GPIO_8_PU_LEN) - 1) << GLB_REG_GPIO_8_PU_POS) #define GLB_REG_GPIO_8_PU_UMSK \ - (~(((1U << GLB_REG_GPIO_8_PU_LEN) - 1) << GLB_REG_GPIO_8_PU_POS)) + (~(((1 << GLB_REG_GPIO_8_PU_LEN) - 1) << GLB_REG_GPIO_8_PU_POS)) #define GLB_REG_GPIO_8_PD GLB_REG_GPIO_8_PD -#define GLB_REG_GPIO_8_PD_POS (5U) -#define GLB_REG_GPIO_8_PD_LEN (1U) +#define GLB_REG_GPIO_8_PD_POS (5) +#define GLB_REG_GPIO_8_PD_LEN (1) #define GLB_REG_GPIO_8_PD_MSK \ - (((1U << GLB_REG_GPIO_8_PD_LEN) - 1) << GLB_REG_GPIO_8_PD_POS) + (((1 << GLB_REG_GPIO_8_PD_LEN) - 1) << GLB_REG_GPIO_8_PD_POS) #define GLB_REG_GPIO_8_PD_UMSK \ - (~(((1U << GLB_REG_GPIO_8_PD_LEN) - 1) << GLB_REG_GPIO_8_PD_POS)) + (~(((1 << GLB_REG_GPIO_8_PD_LEN) - 1) << GLB_REG_GPIO_8_PD_POS)) #define GLB_REG_GPIO_8_FUNC_SEL GLB_REG_GPIO_8_FUNC_SEL -#define GLB_REG_GPIO_8_FUNC_SEL_POS (8U) -#define GLB_REG_GPIO_8_FUNC_SEL_LEN (4U) +#define GLB_REG_GPIO_8_FUNC_SEL_POS (8) +#define GLB_REG_GPIO_8_FUNC_SEL_LEN (4) #define GLB_REG_GPIO_8_FUNC_SEL_MSK \ - (((1U << GLB_REG_GPIO_8_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_8_FUNC_SEL_POS) + (((1 << GLB_REG_GPIO_8_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_8_FUNC_SEL_POS) #define GLB_REG_GPIO_8_FUNC_SEL_UMSK \ - (~(((1U << GLB_REG_GPIO_8_FUNC_SEL_LEN) - 1) \ - << GLB_REG_GPIO_8_FUNC_SEL_POS)) + (~(((1 << GLB_REG_GPIO_8_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_8_FUNC_SEL_POS)) #define GLB_REG_GPIO_9_IE GLB_REG_GPIO_9_IE -#define GLB_REG_GPIO_9_IE_POS (16U) -#define GLB_REG_GPIO_9_IE_LEN (1U) +#define GLB_REG_GPIO_9_IE_POS (16) +#define GLB_REG_GPIO_9_IE_LEN (1) #define GLB_REG_GPIO_9_IE_MSK \ - (((1U << GLB_REG_GPIO_9_IE_LEN) - 1) << GLB_REG_GPIO_9_IE_POS) + (((1 << GLB_REG_GPIO_9_IE_LEN) - 1) << GLB_REG_GPIO_9_IE_POS) #define GLB_REG_GPIO_9_IE_UMSK \ - (~(((1U << GLB_REG_GPIO_9_IE_LEN) - 1) << GLB_REG_GPIO_9_IE_POS)) + (~(((1 << GLB_REG_GPIO_9_IE_LEN) - 1) << GLB_REG_GPIO_9_IE_POS)) #define GLB_REG_GPIO_9_SMT GLB_REG_GPIO_9_SMT -#define GLB_REG_GPIO_9_SMT_POS (17U) -#define GLB_REG_GPIO_9_SMT_LEN (1U) +#define GLB_REG_GPIO_9_SMT_POS (17) +#define GLB_REG_GPIO_9_SMT_LEN (1) #define GLB_REG_GPIO_9_SMT_MSK \ - (((1U << GLB_REG_GPIO_9_SMT_LEN) - 1) << GLB_REG_GPIO_9_SMT_POS) + (((1 << GLB_REG_GPIO_9_SMT_LEN) - 1) << GLB_REG_GPIO_9_SMT_POS) #define GLB_REG_GPIO_9_SMT_UMSK \ - (~(((1U << GLB_REG_GPIO_9_SMT_LEN) - 1) << GLB_REG_GPIO_9_SMT_POS)) + (~(((1 << GLB_REG_GPIO_9_SMT_LEN) - 1) << GLB_REG_GPIO_9_SMT_POS)) #define GLB_REG_GPIO_9_DRV GLB_REG_GPIO_9_DRV -#define GLB_REG_GPIO_9_DRV_POS (18U) -#define GLB_REG_GPIO_9_DRV_LEN (2U) +#define GLB_REG_GPIO_9_DRV_POS (18) +#define GLB_REG_GPIO_9_DRV_LEN (2) #define GLB_REG_GPIO_9_DRV_MSK \ - (((1U << GLB_REG_GPIO_9_DRV_LEN) - 1) << GLB_REG_GPIO_9_DRV_POS) + (((1 << GLB_REG_GPIO_9_DRV_LEN) - 1) << GLB_REG_GPIO_9_DRV_POS) #define GLB_REG_GPIO_9_DRV_UMSK \ - (~(((1U << GLB_REG_GPIO_9_DRV_LEN) - 1) << GLB_REG_GPIO_9_DRV_POS)) + (~(((1 << GLB_REG_GPIO_9_DRV_LEN) - 1) << GLB_REG_GPIO_9_DRV_POS)) #define GLB_REG_GPIO_9_PU GLB_REG_GPIO_9_PU -#define GLB_REG_GPIO_9_PU_POS (20U) -#define GLB_REG_GPIO_9_PU_LEN (1U) +#define GLB_REG_GPIO_9_PU_POS (20) +#define GLB_REG_GPIO_9_PU_LEN (1) #define GLB_REG_GPIO_9_PU_MSK \ - (((1U << GLB_REG_GPIO_9_PU_LEN) - 1) << GLB_REG_GPIO_9_PU_POS) + (((1 << GLB_REG_GPIO_9_PU_LEN) - 1) << GLB_REG_GPIO_9_PU_POS) #define GLB_REG_GPIO_9_PU_UMSK \ - (~(((1U << GLB_REG_GPIO_9_PU_LEN) - 1) << GLB_REG_GPIO_9_PU_POS)) + (~(((1 << GLB_REG_GPIO_9_PU_LEN) - 1) << GLB_REG_GPIO_9_PU_POS)) #define GLB_REG_GPIO_9_PD GLB_REG_GPIO_9_PD -#define GLB_REG_GPIO_9_PD_POS (21U) -#define GLB_REG_GPIO_9_PD_LEN (1U) +#define GLB_REG_GPIO_9_PD_POS (21) +#define GLB_REG_GPIO_9_PD_LEN (1) #define GLB_REG_GPIO_9_PD_MSK \ - (((1U << GLB_REG_GPIO_9_PD_LEN) - 1) << GLB_REG_GPIO_9_PD_POS) + (((1 << GLB_REG_GPIO_9_PD_LEN) - 1) << GLB_REG_GPIO_9_PD_POS) #define GLB_REG_GPIO_9_PD_UMSK \ - (~(((1U << GLB_REG_GPIO_9_PD_LEN) - 1) << GLB_REG_GPIO_9_PD_POS)) + (~(((1 << GLB_REG_GPIO_9_PD_LEN) - 1) << GLB_REG_GPIO_9_PD_POS)) #define GLB_REG_GPIO_9_FUNC_SEL GLB_REG_GPIO_9_FUNC_SEL -#define GLB_REG_GPIO_9_FUNC_SEL_POS (24U) -#define GLB_REG_GPIO_9_FUNC_SEL_LEN (4U) +#define GLB_REG_GPIO_9_FUNC_SEL_POS (24) +#define GLB_REG_GPIO_9_FUNC_SEL_LEN (4) #define GLB_REG_GPIO_9_FUNC_SEL_MSK \ - (((1U << GLB_REG_GPIO_9_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_9_FUNC_SEL_POS) + (((1 << GLB_REG_GPIO_9_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_9_FUNC_SEL_POS) #define GLB_REG_GPIO_9_FUNC_SEL_UMSK \ - (~(((1U << GLB_REG_GPIO_9_FUNC_SEL_LEN) - 1) \ - << GLB_REG_GPIO_9_FUNC_SEL_POS)) + (~(((1 << GLB_REG_GPIO_9_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_9_FUNC_SEL_POS)) /* 0x114 : GPIO_CFGCTL5 */ #define GLB_GPIO_CFGCTL5_OFFSET (0x114) #define GLB_REG_GPIO_10_IE GLB_REG_GPIO_10_IE -#define GLB_REG_GPIO_10_IE_POS (0U) -#define GLB_REG_GPIO_10_IE_LEN (1U) +#define GLB_REG_GPIO_10_IE_POS (0) +#define GLB_REG_GPIO_10_IE_LEN (1) #define GLB_REG_GPIO_10_IE_MSK \ - (((1U << GLB_REG_GPIO_10_IE_LEN) - 1) << GLB_REG_GPIO_10_IE_POS) + (((1 << GLB_REG_GPIO_10_IE_LEN) - 1) << GLB_REG_GPIO_10_IE_POS) #define GLB_REG_GPIO_10_IE_UMSK \ - (~(((1U << GLB_REG_GPIO_10_IE_LEN) - 1) << GLB_REG_GPIO_10_IE_POS)) + (~(((1 << GLB_REG_GPIO_10_IE_LEN) - 1) << GLB_REG_GPIO_10_IE_POS)) #define GLB_REG_GPIO_10_SMT GLB_REG_GPIO_10_SMT -#define GLB_REG_GPIO_10_SMT_POS (1U) -#define GLB_REG_GPIO_10_SMT_LEN (1U) +#define GLB_REG_GPIO_10_SMT_POS (1) +#define GLB_REG_GPIO_10_SMT_LEN (1) #define GLB_REG_GPIO_10_SMT_MSK \ - (((1U << GLB_REG_GPIO_10_SMT_LEN) - 1) << GLB_REG_GPIO_10_SMT_POS) + (((1 << GLB_REG_GPIO_10_SMT_LEN) - 1) << GLB_REG_GPIO_10_SMT_POS) #define GLB_REG_GPIO_10_SMT_UMSK \ - (~(((1U << GLB_REG_GPIO_10_SMT_LEN) - 1) << GLB_REG_GPIO_10_SMT_POS)) + (~(((1 << GLB_REG_GPIO_10_SMT_LEN) - 1) << GLB_REG_GPIO_10_SMT_POS)) #define GLB_REG_GPIO_10_DRV GLB_REG_GPIO_10_DRV -#define GLB_REG_GPIO_10_DRV_POS (2U) -#define GLB_REG_GPIO_10_DRV_LEN (2U) +#define GLB_REG_GPIO_10_DRV_POS (2) +#define GLB_REG_GPIO_10_DRV_LEN (2) #define GLB_REG_GPIO_10_DRV_MSK \ - (((1U << GLB_REG_GPIO_10_DRV_LEN) - 1) << GLB_REG_GPIO_10_DRV_POS) + (((1 << GLB_REG_GPIO_10_DRV_LEN) - 1) << GLB_REG_GPIO_10_DRV_POS) #define GLB_REG_GPIO_10_DRV_UMSK \ - (~(((1U << GLB_REG_GPIO_10_DRV_LEN) - 1) << GLB_REG_GPIO_10_DRV_POS)) + (~(((1 << GLB_REG_GPIO_10_DRV_LEN) - 1) << GLB_REG_GPIO_10_DRV_POS)) #define GLB_REG_GPIO_10_PU GLB_REG_GPIO_10_PU -#define GLB_REG_GPIO_10_PU_POS (4U) -#define GLB_REG_GPIO_10_PU_LEN (1U) +#define GLB_REG_GPIO_10_PU_POS (4) +#define GLB_REG_GPIO_10_PU_LEN (1) #define GLB_REG_GPIO_10_PU_MSK \ - (((1U << GLB_REG_GPIO_10_PU_LEN) - 1) << GLB_REG_GPIO_10_PU_POS) + (((1 << GLB_REG_GPIO_10_PU_LEN) - 1) << GLB_REG_GPIO_10_PU_POS) #define GLB_REG_GPIO_10_PU_UMSK \ - (~(((1U << GLB_REG_GPIO_10_PU_LEN) - 1) << GLB_REG_GPIO_10_PU_POS)) + (~(((1 << GLB_REG_GPIO_10_PU_LEN) - 1) << GLB_REG_GPIO_10_PU_POS)) #define GLB_REG_GPIO_10_PD GLB_REG_GPIO_10_PD -#define GLB_REG_GPIO_10_PD_POS (5U) -#define GLB_REG_GPIO_10_PD_LEN (1U) +#define GLB_REG_GPIO_10_PD_POS (5) +#define GLB_REG_GPIO_10_PD_LEN (1) #define GLB_REG_GPIO_10_PD_MSK \ - (((1U << GLB_REG_GPIO_10_PD_LEN) - 1) << GLB_REG_GPIO_10_PD_POS) + (((1 << GLB_REG_GPIO_10_PD_LEN) - 1) << GLB_REG_GPIO_10_PD_POS) #define GLB_REG_GPIO_10_PD_UMSK \ - (~(((1U << GLB_REG_GPIO_10_PD_LEN) - 1) << GLB_REG_GPIO_10_PD_POS)) + (~(((1 << GLB_REG_GPIO_10_PD_LEN) - 1) << GLB_REG_GPIO_10_PD_POS)) #define GLB_REG_GPIO_10_FUNC_SEL GLB_REG_GPIO_10_FUNC_SEL -#define GLB_REG_GPIO_10_FUNC_SEL_POS (8U) -#define GLB_REG_GPIO_10_FUNC_SEL_LEN (4U) +#define GLB_REG_GPIO_10_FUNC_SEL_POS (8) +#define GLB_REG_GPIO_10_FUNC_SEL_LEN (4) #define GLB_REG_GPIO_10_FUNC_SEL_MSK \ - (((1U << GLB_REG_GPIO_10_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_10_FUNC_SEL_POS) + (((1 << GLB_REG_GPIO_10_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_10_FUNC_SEL_POS) #define GLB_REG_GPIO_10_FUNC_SEL_UMSK \ - (~(((1U << GLB_REG_GPIO_10_FUNC_SEL_LEN) - 1) \ + (~(((1 << GLB_REG_GPIO_10_FUNC_SEL_LEN) - 1) \ << GLB_REG_GPIO_10_FUNC_SEL_POS)) #define GLB_REG_GPIO_11_IE GLB_REG_GPIO_11_IE -#define GLB_REG_GPIO_11_IE_POS (16U) -#define GLB_REG_GPIO_11_IE_LEN (1U) +#define GLB_REG_GPIO_11_IE_POS (16) +#define GLB_REG_GPIO_11_IE_LEN (1) #define GLB_REG_GPIO_11_IE_MSK \ - (((1U << GLB_REG_GPIO_11_IE_LEN) - 1) << GLB_REG_GPIO_11_IE_POS) + (((1 << GLB_REG_GPIO_11_IE_LEN) - 1) << GLB_REG_GPIO_11_IE_POS) #define GLB_REG_GPIO_11_IE_UMSK \ - (~(((1U << GLB_REG_GPIO_11_IE_LEN) - 1) << GLB_REG_GPIO_11_IE_POS)) + (~(((1 << GLB_REG_GPIO_11_IE_LEN) - 1) << GLB_REG_GPIO_11_IE_POS)) #define GLB_REG_GPIO_11_SMT GLB_REG_GPIO_11_SMT -#define GLB_REG_GPIO_11_SMT_POS (17U) -#define GLB_REG_GPIO_11_SMT_LEN (1U) +#define GLB_REG_GPIO_11_SMT_POS (17) +#define GLB_REG_GPIO_11_SMT_LEN (1) #define GLB_REG_GPIO_11_SMT_MSK \ - (((1U << GLB_REG_GPIO_11_SMT_LEN) - 1) << GLB_REG_GPIO_11_SMT_POS) + (((1 << GLB_REG_GPIO_11_SMT_LEN) - 1) << GLB_REG_GPIO_11_SMT_POS) #define GLB_REG_GPIO_11_SMT_UMSK \ - (~(((1U << GLB_REG_GPIO_11_SMT_LEN) - 1) << GLB_REG_GPIO_11_SMT_POS)) + (~(((1 << GLB_REG_GPIO_11_SMT_LEN) - 1) << GLB_REG_GPIO_11_SMT_POS)) #define GLB_REG_GPIO_11_DRV GLB_REG_GPIO_11_DRV -#define GLB_REG_GPIO_11_DRV_POS (18U) -#define GLB_REG_GPIO_11_DRV_LEN (2U) +#define GLB_REG_GPIO_11_DRV_POS (18) +#define GLB_REG_GPIO_11_DRV_LEN (2) #define GLB_REG_GPIO_11_DRV_MSK \ - (((1U << GLB_REG_GPIO_11_DRV_LEN) - 1) << GLB_REG_GPIO_11_DRV_POS) + (((1 << GLB_REG_GPIO_11_DRV_LEN) - 1) << GLB_REG_GPIO_11_DRV_POS) #define GLB_REG_GPIO_11_DRV_UMSK \ - (~(((1U << GLB_REG_GPIO_11_DRV_LEN) - 1) << GLB_REG_GPIO_11_DRV_POS)) + (~(((1 << GLB_REG_GPIO_11_DRV_LEN) - 1) << GLB_REG_GPIO_11_DRV_POS)) #define GLB_REG_GPIO_11_PU GLB_REG_GPIO_11_PU -#define GLB_REG_GPIO_11_PU_POS (20U) -#define GLB_REG_GPIO_11_PU_LEN (1U) +#define GLB_REG_GPIO_11_PU_POS (20) +#define GLB_REG_GPIO_11_PU_LEN (1) #define GLB_REG_GPIO_11_PU_MSK \ - (((1U << GLB_REG_GPIO_11_PU_LEN) - 1) << GLB_REG_GPIO_11_PU_POS) + (((1 << GLB_REG_GPIO_11_PU_LEN) - 1) << GLB_REG_GPIO_11_PU_POS) #define GLB_REG_GPIO_11_PU_UMSK \ - (~(((1U << GLB_REG_GPIO_11_PU_LEN) - 1) << GLB_REG_GPIO_11_PU_POS)) + (~(((1 << GLB_REG_GPIO_11_PU_LEN) - 1) << GLB_REG_GPIO_11_PU_POS)) #define GLB_REG_GPIO_11_PD GLB_REG_GPIO_11_PD -#define GLB_REG_GPIO_11_PD_POS (21U) -#define GLB_REG_GPIO_11_PD_LEN (1U) +#define GLB_REG_GPIO_11_PD_POS (21) +#define GLB_REG_GPIO_11_PD_LEN (1) #define GLB_REG_GPIO_11_PD_MSK \ - (((1U << GLB_REG_GPIO_11_PD_LEN) - 1) << GLB_REG_GPIO_11_PD_POS) + (((1 << GLB_REG_GPIO_11_PD_LEN) - 1) << GLB_REG_GPIO_11_PD_POS) #define GLB_REG_GPIO_11_PD_UMSK \ - (~(((1U << GLB_REG_GPIO_11_PD_LEN) - 1) << GLB_REG_GPIO_11_PD_POS)) + (~(((1 << GLB_REG_GPIO_11_PD_LEN) - 1) << GLB_REG_GPIO_11_PD_POS)) #define GLB_REG_GPIO_11_FUNC_SEL GLB_REG_GPIO_11_FUNC_SEL -#define GLB_REG_GPIO_11_FUNC_SEL_POS (24U) -#define GLB_REG_GPIO_11_FUNC_SEL_LEN (4U) +#define GLB_REG_GPIO_11_FUNC_SEL_POS (24) +#define GLB_REG_GPIO_11_FUNC_SEL_LEN (4) #define GLB_REG_GPIO_11_FUNC_SEL_MSK \ - (((1U << GLB_REG_GPIO_11_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_11_FUNC_SEL_POS) + (((1 << GLB_REG_GPIO_11_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_11_FUNC_SEL_POS) #define GLB_REG_GPIO_11_FUNC_SEL_UMSK \ - (~(((1U << GLB_REG_GPIO_11_FUNC_SEL_LEN) - 1) \ + (~(((1 << GLB_REG_GPIO_11_FUNC_SEL_LEN) - 1) \ << GLB_REG_GPIO_11_FUNC_SEL_POS)) /* 0x118 : GPIO_CFGCTL6 */ #define GLB_GPIO_CFGCTL6_OFFSET (0x118) #define GLB_REG_GPIO_12_IE GLB_REG_GPIO_12_IE -#define GLB_REG_GPIO_12_IE_POS (0U) -#define GLB_REG_GPIO_12_IE_LEN (1U) +#define GLB_REG_GPIO_12_IE_POS (0) +#define GLB_REG_GPIO_12_IE_LEN (1) #define GLB_REG_GPIO_12_IE_MSK \ - (((1U << GLB_REG_GPIO_12_IE_LEN) - 1) << GLB_REG_GPIO_12_IE_POS) + (((1 << GLB_REG_GPIO_12_IE_LEN) - 1) << GLB_REG_GPIO_12_IE_POS) #define GLB_REG_GPIO_12_IE_UMSK \ - (~(((1U << GLB_REG_GPIO_12_IE_LEN) - 1) << GLB_REG_GPIO_12_IE_POS)) + (~(((1 << GLB_REG_GPIO_12_IE_LEN) - 1) << GLB_REG_GPIO_12_IE_POS)) #define GLB_REG_GPIO_12_SMT GLB_REG_GPIO_12_SMT -#define GLB_REG_GPIO_12_SMT_POS (1U) -#define GLB_REG_GPIO_12_SMT_LEN (1U) +#define GLB_REG_GPIO_12_SMT_POS (1) +#define GLB_REG_GPIO_12_SMT_LEN (1) #define GLB_REG_GPIO_12_SMT_MSK \ - (((1U << GLB_REG_GPIO_12_SMT_LEN) - 1) << GLB_REG_GPIO_12_SMT_POS) + (((1 << GLB_REG_GPIO_12_SMT_LEN) - 1) << GLB_REG_GPIO_12_SMT_POS) #define GLB_REG_GPIO_12_SMT_UMSK \ - (~(((1U << GLB_REG_GPIO_12_SMT_LEN) - 1) << GLB_REG_GPIO_12_SMT_POS)) + (~(((1 << GLB_REG_GPIO_12_SMT_LEN) - 1) << GLB_REG_GPIO_12_SMT_POS)) #define GLB_REG_GPIO_12_DRV GLB_REG_GPIO_12_DRV -#define GLB_REG_GPIO_12_DRV_POS (2U) -#define GLB_REG_GPIO_12_DRV_LEN (2U) +#define GLB_REG_GPIO_12_DRV_POS (2) +#define GLB_REG_GPIO_12_DRV_LEN (2) #define GLB_REG_GPIO_12_DRV_MSK \ - (((1U << GLB_REG_GPIO_12_DRV_LEN) - 1) << GLB_REG_GPIO_12_DRV_POS) + (((1 << GLB_REG_GPIO_12_DRV_LEN) - 1) << GLB_REG_GPIO_12_DRV_POS) #define GLB_REG_GPIO_12_DRV_UMSK \ - (~(((1U << GLB_REG_GPIO_12_DRV_LEN) - 1) << GLB_REG_GPIO_12_DRV_POS)) + (~(((1 << GLB_REG_GPIO_12_DRV_LEN) - 1) << GLB_REG_GPIO_12_DRV_POS)) #define GLB_REG_GPIO_12_PU GLB_REG_GPIO_12_PU -#define GLB_REG_GPIO_12_PU_POS (4U) -#define GLB_REG_GPIO_12_PU_LEN (1U) +#define GLB_REG_GPIO_12_PU_POS (4) +#define GLB_REG_GPIO_12_PU_LEN (1) #define GLB_REG_GPIO_12_PU_MSK \ - (((1U << GLB_REG_GPIO_12_PU_LEN) - 1) << GLB_REG_GPIO_12_PU_POS) + (((1 << GLB_REG_GPIO_12_PU_LEN) - 1) << GLB_REG_GPIO_12_PU_POS) #define GLB_REG_GPIO_12_PU_UMSK \ - (~(((1U << GLB_REG_GPIO_12_PU_LEN) - 1) << GLB_REG_GPIO_12_PU_POS)) + (~(((1 << GLB_REG_GPIO_12_PU_LEN) - 1) << GLB_REG_GPIO_12_PU_POS)) #define GLB_REG_GPIO_12_PD GLB_REG_GPIO_12_PD -#define GLB_REG_GPIO_12_PD_POS (5U) -#define GLB_REG_GPIO_12_PD_LEN (1U) +#define GLB_REG_GPIO_12_PD_POS (5) +#define GLB_REG_GPIO_12_PD_LEN (1) #define GLB_REG_GPIO_12_PD_MSK \ - (((1U << GLB_REG_GPIO_12_PD_LEN) - 1) << GLB_REG_GPIO_12_PD_POS) + (((1 << GLB_REG_GPIO_12_PD_LEN) - 1) << GLB_REG_GPIO_12_PD_POS) #define GLB_REG_GPIO_12_PD_UMSK \ - (~(((1U << GLB_REG_GPIO_12_PD_LEN) - 1) << GLB_REG_GPIO_12_PD_POS)) + (~(((1 << GLB_REG_GPIO_12_PD_LEN) - 1) << GLB_REG_GPIO_12_PD_POS)) #define GLB_REG_GPIO_12_FUNC_SEL GLB_REG_GPIO_12_FUNC_SEL -#define GLB_REG_GPIO_12_FUNC_SEL_POS (8U) -#define GLB_REG_GPIO_12_FUNC_SEL_LEN (4U) +#define GLB_REG_GPIO_12_FUNC_SEL_POS (8) +#define GLB_REG_GPIO_12_FUNC_SEL_LEN (4) #define GLB_REG_GPIO_12_FUNC_SEL_MSK \ - (((1U << GLB_REG_GPIO_12_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_12_FUNC_SEL_POS) + (((1 << GLB_REG_GPIO_12_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_12_FUNC_SEL_POS) #define GLB_REG_GPIO_12_FUNC_SEL_UMSK \ - (~(((1U << GLB_REG_GPIO_12_FUNC_SEL_LEN) - 1) \ + (~(((1 << GLB_REG_GPIO_12_FUNC_SEL_LEN) - 1) \ << GLB_REG_GPIO_12_FUNC_SEL_POS)) #define GLB_REG_GPIO_13_IE GLB_REG_GPIO_13_IE -#define GLB_REG_GPIO_13_IE_POS (16U) -#define GLB_REG_GPIO_13_IE_LEN (1U) +#define GLB_REG_GPIO_13_IE_POS (16) +#define GLB_REG_GPIO_13_IE_LEN (1) #define GLB_REG_GPIO_13_IE_MSK \ - (((1U << GLB_REG_GPIO_13_IE_LEN) - 1) << GLB_REG_GPIO_13_IE_POS) + (((1 << GLB_REG_GPIO_13_IE_LEN) - 1) << GLB_REG_GPIO_13_IE_POS) #define GLB_REG_GPIO_13_IE_UMSK \ - (~(((1U << GLB_REG_GPIO_13_IE_LEN) - 1) << GLB_REG_GPIO_13_IE_POS)) + (~(((1 << GLB_REG_GPIO_13_IE_LEN) - 1) << GLB_REG_GPIO_13_IE_POS)) #define GLB_REG_GPIO_13_SMT GLB_REG_GPIO_13_SMT -#define GLB_REG_GPIO_13_SMT_POS (17U) -#define GLB_REG_GPIO_13_SMT_LEN (1U) +#define GLB_REG_GPIO_13_SMT_POS (17) +#define GLB_REG_GPIO_13_SMT_LEN (1) #define GLB_REG_GPIO_13_SMT_MSK \ - (((1U << GLB_REG_GPIO_13_SMT_LEN) - 1) << GLB_REG_GPIO_13_SMT_POS) + (((1 << GLB_REG_GPIO_13_SMT_LEN) - 1) << GLB_REG_GPIO_13_SMT_POS) #define GLB_REG_GPIO_13_SMT_UMSK \ - (~(((1U << GLB_REG_GPIO_13_SMT_LEN) - 1) << GLB_REG_GPIO_13_SMT_POS)) + (~(((1 << GLB_REG_GPIO_13_SMT_LEN) - 1) << GLB_REG_GPIO_13_SMT_POS)) #define GLB_REG_GPIO_13_DRV GLB_REG_GPIO_13_DRV -#define GLB_REG_GPIO_13_DRV_POS (18U) -#define GLB_REG_GPIO_13_DRV_LEN (2U) +#define GLB_REG_GPIO_13_DRV_POS (18) +#define GLB_REG_GPIO_13_DRV_LEN (2) #define GLB_REG_GPIO_13_DRV_MSK \ - (((1U << GLB_REG_GPIO_13_DRV_LEN) - 1) << GLB_REG_GPIO_13_DRV_POS) + (((1 << GLB_REG_GPIO_13_DRV_LEN) - 1) << GLB_REG_GPIO_13_DRV_POS) #define GLB_REG_GPIO_13_DRV_UMSK \ - (~(((1U << GLB_REG_GPIO_13_DRV_LEN) - 1) << GLB_REG_GPIO_13_DRV_POS)) + (~(((1 << GLB_REG_GPIO_13_DRV_LEN) - 1) << GLB_REG_GPIO_13_DRV_POS)) #define GLB_REG_GPIO_13_PU GLB_REG_GPIO_13_PU -#define GLB_REG_GPIO_13_PU_POS (20U) -#define GLB_REG_GPIO_13_PU_LEN (1U) +#define GLB_REG_GPIO_13_PU_POS (20) +#define GLB_REG_GPIO_13_PU_LEN (1) #define GLB_REG_GPIO_13_PU_MSK \ - (((1U << GLB_REG_GPIO_13_PU_LEN) - 1) << GLB_REG_GPIO_13_PU_POS) + (((1 << GLB_REG_GPIO_13_PU_LEN) - 1) << GLB_REG_GPIO_13_PU_POS) #define GLB_REG_GPIO_13_PU_UMSK \ - (~(((1U << GLB_REG_GPIO_13_PU_LEN) - 1) << GLB_REG_GPIO_13_PU_POS)) + (~(((1 << GLB_REG_GPIO_13_PU_LEN) - 1) << GLB_REG_GPIO_13_PU_POS)) #define GLB_REG_GPIO_13_PD GLB_REG_GPIO_13_PD -#define GLB_REG_GPIO_13_PD_POS (21U) -#define GLB_REG_GPIO_13_PD_LEN (1U) +#define GLB_REG_GPIO_13_PD_POS (21) +#define GLB_REG_GPIO_13_PD_LEN (1) #define GLB_REG_GPIO_13_PD_MSK \ - (((1U << GLB_REG_GPIO_13_PD_LEN) - 1) << GLB_REG_GPIO_13_PD_POS) + (((1 << GLB_REG_GPIO_13_PD_LEN) - 1) << GLB_REG_GPIO_13_PD_POS) #define GLB_REG_GPIO_13_PD_UMSK \ - (~(((1U << GLB_REG_GPIO_13_PD_LEN) - 1) << GLB_REG_GPIO_13_PD_POS)) + (~(((1 << GLB_REG_GPIO_13_PD_LEN) - 1) << GLB_REG_GPIO_13_PD_POS)) #define GLB_REG_GPIO_13_FUNC_SEL GLB_REG_GPIO_13_FUNC_SEL -#define GLB_REG_GPIO_13_FUNC_SEL_POS (24U) -#define GLB_REG_GPIO_13_FUNC_SEL_LEN (4U) +#define GLB_REG_GPIO_13_FUNC_SEL_POS (24) +#define GLB_REG_GPIO_13_FUNC_SEL_LEN (4) #define GLB_REG_GPIO_13_FUNC_SEL_MSK \ - (((1U << GLB_REG_GPIO_13_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_13_FUNC_SEL_POS) + (((1 << GLB_REG_GPIO_13_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_13_FUNC_SEL_POS) #define GLB_REG_GPIO_13_FUNC_SEL_UMSK \ - (~(((1U << GLB_REG_GPIO_13_FUNC_SEL_LEN) - 1) \ + (~(((1 << GLB_REG_GPIO_13_FUNC_SEL_LEN) - 1) \ << GLB_REG_GPIO_13_FUNC_SEL_POS)) /* 0x11C : GPIO_CFGCTL7 */ #define GLB_GPIO_CFGCTL7_OFFSET (0x11C) #define GLB_REG_GPIO_14_IE GLB_REG_GPIO_14_IE -#define GLB_REG_GPIO_14_IE_POS (0U) -#define GLB_REG_GPIO_14_IE_LEN (1U) +#define GLB_REG_GPIO_14_IE_POS (0) +#define GLB_REG_GPIO_14_IE_LEN (1) #define GLB_REG_GPIO_14_IE_MSK \ - (((1U << GLB_REG_GPIO_14_IE_LEN) - 1) << GLB_REG_GPIO_14_IE_POS) + (((1 << GLB_REG_GPIO_14_IE_LEN) - 1) << GLB_REG_GPIO_14_IE_POS) #define GLB_REG_GPIO_14_IE_UMSK \ - (~(((1U << GLB_REG_GPIO_14_IE_LEN) - 1) << GLB_REG_GPIO_14_IE_POS)) + (~(((1 << GLB_REG_GPIO_14_IE_LEN) - 1) << GLB_REG_GPIO_14_IE_POS)) #define GLB_REG_GPIO_14_SMT GLB_REG_GPIO_14_SMT -#define GLB_REG_GPIO_14_SMT_POS (1U) -#define GLB_REG_GPIO_14_SMT_LEN (1U) +#define GLB_REG_GPIO_14_SMT_POS (1) +#define GLB_REG_GPIO_14_SMT_LEN (1) #define GLB_REG_GPIO_14_SMT_MSK \ - (((1U << GLB_REG_GPIO_14_SMT_LEN) - 1) << GLB_REG_GPIO_14_SMT_POS) + (((1 << GLB_REG_GPIO_14_SMT_LEN) - 1) << GLB_REG_GPIO_14_SMT_POS) #define GLB_REG_GPIO_14_SMT_UMSK \ - (~(((1U << GLB_REG_GPIO_14_SMT_LEN) - 1) << GLB_REG_GPIO_14_SMT_POS)) + (~(((1 << GLB_REG_GPIO_14_SMT_LEN) - 1) << GLB_REG_GPIO_14_SMT_POS)) #define GLB_REG_GPIO_14_DRV GLB_REG_GPIO_14_DRV -#define GLB_REG_GPIO_14_DRV_POS (2U) -#define GLB_REG_GPIO_14_DRV_LEN (2U) +#define GLB_REG_GPIO_14_DRV_POS (2) +#define GLB_REG_GPIO_14_DRV_LEN (2) #define GLB_REG_GPIO_14_DRV_MSK \ - (((1U << GLB_REG_GPIO_14_DRV_LEN) - 1) << GLB_REG_GPIO_14_DRV_POS) + (((1 << GLB_REG_GPIO_14_DRV_LEN) - 1) << GLB_REG_GPIO_14_DRV_POS) #define GLB_REG_GPIO_14_DRV_UMSK \ - (~(((1U << GLB_REG_GPIO_14_DRV_LEN) - 1) << GLB_REG_GPIO_14_DRV_POS)) + (~(((1 << GLB_REG_GPIO_14_DRV_LEN) - 1) << GLB_REG_GPIO_14_DRV_POS)) #define GLB_REG_GPIO_14_PU GLB_REG_GPIO_14_PU -#define GLB_REG_GPIO_14_PU_POS (4U) -#define GLB_REG_GPIO_14_PU_LEN (1U) +#define GLB_REG_GPIO_14_PU_POS (4) +#define GLB_REG_GPIO_14_PU_LEN (1) #define GLB_REG_GPIO_14_PU_MSK \ - (((1U << GLB_REG_GPIO_14_PU_LEN) - 1) << GLB_REG_GPIO_14_PU_POS) + (((1 << GLB_REG_GPIO_14_PU_LEN) - 1) << GLB_REG_GPIO_14_PU_POS) #define GLB_REG_GPIO_14_PU_UMSK \ - (~(((1U << GLB_REG_GPIO_14_PU_LEN) - 1) << GLB_REG_GPIO_14_PU_POS)) + (~(((1 << GLB_REG_GPIO_14_PU_LEN) - 1) << GLB_REG_GPIO_14_PU_POS)) #define GLB_REG_GPIO_14_PD GLB_REG_GPIO_14_PD -#define GLB_REG_GPIO_14_PD_POS (5U) -#define GLB_REG_GPIO_14_PD_LEN (1U) +#define GLB_REG_GPIO_14_PD_POS (5) +#define GLB_REG_GPIO_14_PD_LEN (1) #define GLB_REG_GPIO_14_PD_MSK \ - (((1U << GLB_REG_GPIO_14_PD_LEN) - 1) << GLB_REG_GPIO_14_PD_POS) + (((1 << GLB_REG_GPIO_14_PD_LEN) - 1) << GLB_REG_GPIO_14_PD_POS) #define GLB_REG_GPIO_14_PD_UMSK \ - (~(((1U << GLB_REG_GPIO_14_PD_LEN) - 1) << GLB_REG_GPIO_14_PD_POS)) + (~(((1 << GLB_REG_GPIO_14_PD_LEN) - 1) << GLB_REG_GPIO_14_PD_POS)) #define GLB_REG_GPIO_14_FUNC_SEL GLB_REG_GPIO_14_FUNC_SEL -#define GLB_REG_GPIO_14_FUNC_SEL_POS (8U) -#define GLB_REG_GPIO_14_FUNC_SEL_LEN (4U) +#define GLB_REG_GPIO_14_FUNC_SEL_POS (8) +#define GLB_REG_GPIO_14_FUNC_SEL_LEN (4) #define GLB_REG_GPIO_14_FUNC_SEL_MSK \ - (((1U << GLB_REG_GPIO_14_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_14_FUNC_SEL_POS) + (((1 << GLB_REG_GPIO_14_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_14_FUNC_SEL_POS) #define GLB_REG_GPIO_14_FUNC_SEL_UMSK \ - (~(((1U << GLB_REG_GPIO_14_FUNC_SEL_LEN) - 1) \ + (~(((1 << GLB_REG_GPIO_14_FUNC_SEL_LEN) - 1) \ << GLB_REG_GPIO_14_FUNC_SEL_POS)) #define GLB_REG_GPIO_15_IE GLB_REG_GPIO_15_IE -#define GLB_REG_GPIO_15_IE_POS (16U) -#define GLB_REG_GPIO_15_IE_LEN (1U) +#define GLB_REG_GPIO_15_IE_POS (16) +#define GLB_REG_GPIO_15_IE_LEN (1) #define GLB_REG_GPIO_15_IE_MSK \ - (((1U << GLB_REG_GPIO_15_IE_LEN) - 1) << GLB_REG_GPIO_15_IE_POS) + (((1 << GLB_REG_GPIO_15_IE_LEN) - 1) << GLB_REG_GPIO_15_IE_POS) #define GLB_REG_GPIO_15_IE_UMSK \ - (~(((1U << GLB_REG_GPIO_15_IE_LEN) - 1) << GLB_REG_GPIO_15_IE_POS)) + (~(((1 << GLB_REG_GPIO_15_IE_LEN) - 1) << GLB_REG_GPIO_15_IE_POS)) #define GLB_REG_GPIO_15_SMT GLB_REG_GPIO_15_SMT -#define GLB_REG_GPIO_15_SMT_POS (17U) -#define GLB_REG_GPIO_15_SMT_LEN (1U) +#define GLB_REG_GPIO_15_SMT_POS (17) +#define GLB_REG_GPIO_15_SMT_LEN (1) #define GLB_REG_GPIO_15_SMT_MSK \ - (((1U << GLB_REG_GPIO_15_SMT_LEN) - 1) << GLB_REG_GPIO_15_SMT_POS) + (((1 << GLB_REG_GPIO_15_SMT_LEN) - 1) << GLB_REG_GPIO_15_SMT_POS) #define GLB_REG_GPIO_15_SMT_UMSK \ - (~(((1U << GLB_REG_GPIO_15_SMT_LEN) - 1) << GLB_REG_GPIO_15_SMT_POS)) + (~(((1 << GLB_REG_GPIO_15_SMT_LEN) - 1) << GLB_REG_GPIO_15_SMT_POS)) #define GLB_REG_GPIO_15_DRV GLB_REG_GPIO_15_DRV -#define GLB_REG_GPIO_15_DRV_POS (18U) -#define GLB_REG_GPIO_15_DRV_LEN (2U) +#define GLB_REG_GPIO_15_DRV_POS (18) +#define GLB_REG_GPIO_15_DRV_LEN (2) #define GLB_REG_GPIO_15_DRV_MSK \ - (((1U << GLB_REG_GPIO_15_DRV_LEN) - 1) << GLB_REG_GPIO_15_DRV_POS) + (((1 << GLB_REG_GPIO_15_DRV_LEN) - 1) << GLB_REG_GPIO_15_DRV_POS) #define GLB_REG_GPIO_15_DRV_UMSK \ - (~(((1U << GLB_REG_GPIO_15_DRV_LEN) - 1) << GLB_REG_GPIO_15_DRV_POS)) + (~(((1 << GLB_REG_GPIO_15_DRV_LEN) - 1) << GLB_REG_GPIO_15_DRV_POS)) #define GLB_REG_GPIO_15_PU GLB_REG_GPIO_15_PU -#define GLB_REG_GPIO_15_PU_POS (20U) -#define GLB_REG_GPIO_15_PU_LEN (1U) +#define GLB_REG_GPIO_15_PU_POS (20) +#define GLB_REG_GPIO_15_PU_LEN (1) #define GLB_REG_GPIO_15_PU_MSK \ - (((1U << GLB_REG_GPIO_15_PU_LEN) - 1) << GLB_REG_GPIO_15_PU_POS) + (((1 << GLB_REG_GPIO_15_PU_LEN) - 1) << GLB_REG_GPIO_15_PU_POS) #define GLB_REG_GPIO_15_PU_UMSK \ - (~(((1U << GLB_REG_GPIO_15_PU_LEN) - 1) << GLB_REG_GPIO_15_PU_POS)) + (~(((1 << GLB_REG_GPIO_15_PU_LEN) - 1) << GLB_REG_GPIO_15_PU_POS)) #define GLB_REG_GPIO_15_PD GLB_REG_GPIO_15_PD -#define GLB_REG_GPIO_15_PD_POS (21U) -#define GLB_REG_GPIO_15_PD_LEN (1U) +#define GLB_REG_GPIO_15_PD_POS (21) +#define GLB_REG_GPIO_15_PD_LEN (1) #define GLB_REG_GPIO_15_PD_MSK \ - (((1U << GLB_REG_GPIO_15_PD_LEN) - 1) << GLB_REG_GPIO_15_PD_POS) + (((1 << GLB_REG_GPIO_15_PD_LEN) - 1) << GLB_REG_GPIO_15_PD_POS) #define GLB_REG_GPIO_15_PD_UMSK \ - (~(((1U << GLB_REG_GPIO_15_PD_LEN) - 1) << GLB_REG_GPIO_15_PD_POS)) + (~(((1 << GLB_REG_GPIO_15_PD_LEN) - 1) << GLB_REG_GPIO_15_PD_POS)) #define GLB_REG_GPIO_15_FUNC_SEL GLB_REG_GPIO_15_FUNC_SEL -#define GLB_REG_GPIO_15_FUNC_SEL_POS (24U) -#define GLB_REG_GPIO_15_FUNC_SEL_LEN (4U) +#define GLB_REG_GPIO_15_FUNC_SEL_POS (24) +#define GLB_REG_GPIO_15_FUNC_SEL_LEN (4) #define GLB_REG_GPIO_15_FUNC_SEL_MSK \ - (((1U << GLB_REG_GPIO_15_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_15_FUNC_SEL_POS) + (((1 << GLB_REG_GPIO_15_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_15_FUNC_SEL_POS) #define GLB_REG_GPIO_15_FUNC_SEL_UMSK \ - (~(((1U << GLB_REG_GPIO_15_FUNC_SEL_LEN) - 1) \ + (~(((1 << GLB_REG_GPIO_15_FUNC_SEL_LEN) - 1) \ << GLB_REG_GPIO_15_FUNC_SEL_POS)) /* 0x120 : GPIO_CFGCTL8 */ #define GLB_GPIO_CFGCTL8_OFFSET (0x120) #define GLB_REG_GPIO_16_IE GLB_REG_GPIO_16_IE -#define GLB_REG_GPIO_16_IE_POS (0U) -#define GLB_REG_GPIO_16_IE_LEN (1U) +#define GLB_REG_GPIO_16_IE_POS (0) +#define GLB_REG_GPIO_16_IE_LEN (1) #define GLB_REG_GPIO_16_IE_MSK \ - (((1U << GLB_REG_GPIO_16_IE_LEN) - 1) << GLB_REG_GPIO_16_IE_POS) + (((1 << GLB_REG_GPIO_16_IE_LEN) - 1) << GLB_REG_GPIO_16_IE_POS) #define GLB_REG_GPIO_16_IE_UMSK \ - (~(((1U << GLB_REG_GPIO_16_IE_LEN) - 1) << GLB_REG_GPIO_16_IE_POS)) + (~(((1 << GLB_REG_GPIO_16_IE_LEN) - 1) << GLB_REG_GPIO_16_IE_POS)) #define GLB_REG_GPIO_16_SMT GLB_REG_GPIO_16_SMT -#define GLB_REG_GPIO_16_SMT_POS (1U) -#define GLB_REG_GPIO_16_SMT_LEN (1U) +#define GLB_REG_GPIO_16_SMT_POS (1) +#define GLB_REG_GPIO_16_SMT_LEN (1) #define GLB_REG_GPIO_16_SMT_MSK \ - (((1U << GLB_REG_GPIO_16_SMT_LEN) - 1) << GLB_REG_GPIO_16_SMT_POS) + (((1 << GLB_REG_GPIO_16_SMT_LEN) - 1) << GLB_REG_GPIO_16_SMT_POS) #define GLB_REG_GPIO_16_SMT_UMSK \ - (~(((1U << GLB_REG_GPIO_16_SMT_LEN) - 1) << GLB_REG_GPIO_16_SMT_POS)) + (~(((1 << GLB_REG_GPIO_16_SMT_LEN) - 1) << GLB_REG_GPIO_16_SMT_POS)) #define GLB_REG_GPIO_16_DRV GLB_REG_GPIO_16_DRV -#define GLB_REG_GPIO_16_DRV_POS (2U) -#define GLB_REG_GPIO_16_DRV_LEN (2U) +#define GLB_REG_GPIO_16_DRV_POS (2) +#define GLB_REG_GPIO_16_DRV_LEN (2) #define GLB_REG_GPIO_16_DRV_MSK \ - (((1U << GLB_REG_GPIO_16_DRV_LEN) - 1) << GLB_REG_GPIO_16_DRV_POS) + (((1 << GLB_REG_GPIO_16_DRV_LEN) - 1) << GLB_REG_GPIO_16_DRV_POS) #define GLB_REG_GPIO_16_DRV_UMSK \ - (~(((1U << GLB_REG_GPIO_16_DRV_LEN) - 1) << GLB_REG_GPIO_16_DRV_POS)) + (~(((1 << GLB_REG_GPIO_16_DRV_LEN) - 1) << GLB_REG_GPIO_16_DRV_POS)) #define GLB_REG_GPIO_16_PU GLB_REG_GPIO_16_PU -#define GLB_REG_GPIO_16_PU_POS (4U) -#define GLB_REG_GPIO_16_PU_LEN (1U) +#define GLB_REG_GPIO_16_PU_POS (4) +#define GLB_REG_GPIO_16_PU_LEN (1) #define GLB_REG_GPIO_16_PU_MSK \ - (((1U << GLB_REG_GPIO_16_PU_LEN) - 1) << GLB_REG_GPIO_16_PU_POS) + (((1 << GLB_REG_GPIO_16_PU_LEN) - 1) << GLB_REG_GPIO_16_PU_POS) #define GLB_REG_GPIO_16_PU_UMSK \ - (~(((1U << GLB_REG_GPIO_16_PU_LEN) - 1) << GLB_REG_GPIO_16_PU_POS)) + (~(((1 << GLB_REG_GPIO_16_PU_LEN) - 1) << GLB_REG_GPIO_16_PU_POS)) #define GLB_REG_GPIO_16_PD GLB_REG_GPIO_16_PD -#define GLB_REG_GPIO_16_PD_POS (5U) -#define GLB_REG_GPIO_16_PD_LEN (1U) +#define GLB_REG_GPIO_16_PD_POS (5) +#define GLB_REG_GPIO_16_PD_LEN (1) #define GLB_REG_GPIO_16_PD_MSK \ - (((1U << GLB_REG_GPIO_16_PD_LEN) - 1) << GLB_REG_GPIO_16_PD_POS) + (((1 << GLB_REG_GPIO_16_PD_LEN) - 1) << GLB_REG_GPIO_16_PD_POS) #define GLB_REG_GPIO_16_PD_UMSK \ - (~(((1U << GLB_REG_GPIO_16_PD_LEN) - 1) << GLB_REG_GPIO_16_PD_POS)) + (~(((1 << GLB_REG_GPIO_16_PD_LEN) - 1) << GLB_REG_GPIO_16_PD_POS)) #define GLB_REG_GPIO_16_FUNC_SEL GLB_REG_GPIO_16_FUNC_SEL -#define GLB_REG_GPIO_16_FUNC_SEL_POS (8U) -#define GLB_REG_GPIO_16_FUNC_SEL_LEN (4U) +#define GLB_REG_GPIO_16_FUNC_SEL_POS (8) +#define GLB_REG_GPIO_16_FUNC_SEL_LEN (4) #define GLB_REG_GPIO_16_FUNC_SEL_MSK \ - (((1U << GLB_REG_GPIO_16_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_16_FUNC_SEL_POS) + (((1 << GLB_REG_GPIO_16_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_16_FUNC_SEL_POS) #define GLB_REG_GPIO_16_FUNC_SEL_UMSK \ - (~(((1U << GLB_REG_GPIO_16_FUNC_SEL_LEN) - 1) \ + (~(((1 << GLB_REG_GPIO_16_FUNC_SEL_LEN) - 1) \ << GLB_REG_GPIO_16_FUNC_SEL_POS)) #define GLB_REG_GPIO_17_IE GLB_REG_GPIO_17_IE -#define GLB_REG_GPIO_17_IE_POS (16U) -#define GLB_REG_GPIO_17_IE_LEN (1U) +#define GLB_REG_GPIO_17_IE_POS (16) +#define GLB_REG_GPIO_17_IE_LEN (1) #define GLB_REG_GPIO_17_IE_MSK \ - (((1U << GLB_REG_GPIO_17_IE_LEN) - 1) << GLB_REG_GPIO_17_IE_POS) + (((1 << GLB_REG_GPIO_17_IE_LEN) - 1) << GLB_REG_GPIO_17_IE_POS) #define GLB_REG_GPIO_17_IE_UMSK \ - (~(((1U << GLB_REG_GPIO_17_IE_LEN) - 1) << GLB_REG_GPIO_17_IE_POS)) + (~(((1 << GLB_REG_GPIO_17_IE_LEN) - 1) << GLB_REG_GPIO_17_IE_POS)) #define GLB_REG_GPIO_17_SMT GLB_REG_GPIO_17_SMT -#define GLB_REG_GPIO_17_SMT_POS (17U) -#define GLB_REG_GPIO_17_SMT_LEN (1U) +#define GLB_REG_GPIO_17_SMT_POS (17) +#define GLB_REG_GPIO_17_SMT_LEN (1) #define GLB_REG_GPIO_17_SMT_MSK \ - (((1U << GLB_REG_GPIO_17_SMT_LEN) - 1) << GLB_REG_GPIO_17_SMT_POS) + (((1 << GLB_REG_GPIO_17_SMT_LEN) - 1) << GLB_REG_GPIO_17_SMT_POS) #define GLB_REG_GPIO_17_SMT_UMSK \ - (~(((1U << GLB_REG_GPIO_17_SMT_LEN) - 1) << GLB_REG_GPIO_17_SMT_POS)) + (~(((1 << GLB_REG_GPIO_17_SMT_LEN) - 1) << GLB_REG_GPIO_17_SMT_POS)) #define GLB_REG_GPIO_17_DRV GLB_REG_GPIO_17_DRV -#define GLB_REG_GPIO_17_DRV_POS (18U) -#define GLB_REG_GPIO_17_DRV_LEN (2U) +#define GLB_REG_GPIO_17_DRV_POS (18) +#define GLB_REG_GPIO_17_DRV_LEN (2) #define GLB_REG_GPIO_17_DRV_MSK \ - (((1U << GLB_REG_GPIO_17_DRV_LEN) - 1) << GLB_REG_GPIO_17_DRV_POS) + (((1 << GLB_REG_GPIO_17_DRV_LEN) - 1) << GLB_REG_GPIO_17_DRV_POS) #define GLB_REG_GPIO_17_DRV_UMSK \ - (~(((1U << GLB_REG_GPIO_17_DRV_LEN) - 1) << GLB_REG_GPIO_17_DRV_POS)) + (~(((1 << GLB_REG_GPIO_17_DRV_LEN) - 1) << GLB_REG_GPIO_17_DRV_POS)) #define GLB_REG_GPIO_17_PU GLB_REG_GPIO_17_PU -#define GLB_REG_GPIO_17_PU_POS (20U) -#define GLB_REG_GPIO_17_PU_LEN (1U) +#define GLB_REG_GPIO_17_PU_POS (20) +#define GLB_REG_GPIO_17_PU_LEN (1) #define GLB_REG_GPIO_17_PU_MSK \ - (((1U << GLB_REG_GPIO_17_PU_LEN) - 1) << GLB_REG_GPIO_17_PU_POS) + (((1 << GLB_REG_GPIO_17_PU_LEN) - 1) << GLB_REG_GPIO_17_PU_POS) #define GLB_REG_GPIO_17_PU_UMSK \ - (~(((1U << GLB_REG_GPIO_17_PU_LEN) - 1) << GLB_REG_GPIO_17_PU_POS)) + (~(((1 << GLB_REG_GPIO_17_PU_LEN) - 1) << GLB_REG_GPIO_17_PU_POS)) #define GLB_REG_GPIO_17_PD GLB_REG_GPIO_17_PD -#define GLB_REG_GPIO_17_PD_POS (21U) -#define GLB_REG_GPIO_17_PD_LEN (1U) +#define GLB_REG_GPIO_17_PD_POS (21) +#define GLB_REG_GPIO_17_PD_LEN (1) #define GLB_REG_GPIO_17_PD_MSK \ - (((1U << GLB_REG_GPIO_17_PD_LEN) - 1) << GLB_REG_GPIO_17_PD_POS) + (((1 << GLB_REG_GPIO_17_PD_LEN) - 1) << GLB_REG_GPIO_17_PD_POS) #define GLB_REG_GPIO_17_PD_UMSK \ - (~(((1U << GLB_REG_GPIO_17_PD_LEN) - 1) << GLB_REG_GPIO_17_PD_POS)) + (~(((1 << GLB_REG_GPIO_17_PD_LEN) - 1) << GLB_REG_GPIO_17_PD_POS)) #define GLB_REG_GPIO_17_FUNC_SEL GLB_REG_GPIO_17_FUNC_SEL -#define GLB_REG_GPIO_17_FUNC_SEL_POS (24U) -#define GLB_REG_GPIO_17_FUNC_SEL_LEN (4U) +#define GLB_REG_GPIO_17_FUNC_SEL_POS (24) +#define GLB_REG_GPIO_17_FUNC_SEL_LEN (4) #define GLB_REG_GPIO_17_FUNC_SEL_MSK \ - (((1U << GLB_REG_GPIO_17_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_17_FUNC_SEL_POS) + (((1 << GLB_REG_GPIO_17_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_17_FUNC_SEL_POS) #define GLB_REG_GPIO_17_FUNC_SEL_UMSK \ - (~(((1U << GLB_REG_GPIO_17_FUNC_SEL_LEN) - 1) \ + (~(((1 << GLB_REG_GPIO_17_FUNC_SEL_LEN) - 1) \ << GLB_REG_GPIO_17_FUNC_SEL_POS)) /* 0x124 : GPIO_CFGCTL9 */ #define GLB_GPIO_CFGCTL9_OFFSET (0x124) #define GLB_REG_GPIO_18_IE GLB_REG_GPIO_18_IE -#define GLB_REG_GPIO_18_IE_POS (0U) -#define GLB_REG_GPIO_18_IE_LEN (1U) +#define GLB_REG_GPIO_18_IE_POS (0) +#define GLB_REG_GPIO_18_IE_LEN (1) #define GLB_REG_GPIO_18_IE_MSK \ - (((1U << GLB_REG_GPIO_18_IE_LEN) - 1) << GLB_REG_GPIO_18_IE_POS) + (((1 << GLB_REG_GPIO_18_IE_LEN) - 1) << GLB_REG_GPIO_18_IE_POS) #define GLB_REG_GPIO_18_IE_UMSK \ - (~(((1U << GLB_REG_GPIO_18_IE_LEN) - 1) << GLB_REG_GPIO_18_IE_POS)) + (~(((1 << GLB_REG_GPIO_18_IE_LEN) - 1) << GLB_REG_GPIO_18_IE_POS)) #define GLB_REG_GPIO_18_SMT GLB_REG_GPIO_18_SMT -#define GLB_REG_GPIO_18_SMT_POS (1U) -#define GLB_REG_GPIO_18_SMT_LEN (1U) +#define GLB_REG_GPIO_18_SMT_POS (1) +#define GLB_REG_GPIO_18_SMT_LEN (1) #define GLB_REG_GPIO_18_SMT_MSK \ - (((1U << GLB_REG_GPIO_18_SMT_LEN) - 1) << GLB_REG_GPIO_18_SMT_POS) + (((1 << GLB_REG_GPIO_18_SMT_LEN) - 1) << GLB_REG_GPIO_18_SMT_POS) #define GLB_REG_GPIO_18_SMT_UMSK \ - (~(((1U << GLB_REG_GPIO_18_SMT_LEN) - 1) << GLB_REG_GPIO_18_SMT_POS)) + (~(((1 << GLB_REG_GPIO_18_SMT_LEN) - 1) << GLB_REG_GPIO_18_SMT_POS)) #define GLB_REG_GPIO_18_DRV GLB_REG_GPIO_18_DRV -#define GLB_REG_GPIO_18_DRV_POS (2U) -#define GLB_REG_GPIO_18_DRV_LEN (2U) +#define GLB_REG_GPIO_18_DRV_POS (2) +#define GLB_REG_GPIO_18_DRV_LEN (2) #define GLB_REG_GPIO_18_DRV_MSK \ - (((1U << GLB_REG_GPIO_18_DRV_LEN) - 1) << GLB_REG_GPIO_18_DRV_POS) + (((1 << GLB_REG_GPIO_18_DRV_LEN) - 1) << GLB_REG_GPIO_18_DRV_POS) #define GLB_REG_GPIO_18_DRV_UMSK \ - (~(((1U << GLB_REG_GPIO_18_DRV_LEN) - 1) << GLB_REG_GPIO_18_DRV_POS)) + (~(((1 << GLB_REG_GPIO_18_DRV_LEN) - 1) << GLB_REG_GPIO_18_DRV_POS)) #define GLB_REG_GPIO_18_PU GLB_REG_GPIO_18_PU -#define GLB_REG_GPIO_18_PU_POS (4U) -#define GLB_REG_GPIO_18_PU_LEN (1U) +#define GLB_REG_GPIO_18_PU_POS (4) +#define GLB_REG_GPIO_18_PU_LEN (1) #define GLB_REG_GPIO_18_PU_MSK \ - (((1U << GLB_REG_GPIO_18_PU_LEN) - 1) << GLB_REG_GPIO_18_PU_POS) + (((1 << GLB_REG_GPIO_18_PU_LEN) - 1) << GLB_REG_GPIO_18_PU_POS) #define GLB_REG_GPIO_18_PU_UMSK \ - (~(((1U << GLB_REG_GPIO_18_PU_LEN) - 1) << GLB_REG_GPIO_18_PU_POS)) + (~(((1 << GLB_REG_GPIO_18_PU_LEN) - 1) << GLB_REG_GPIO_18_PU_POS)) #define GLB_REG_GPIO_18_PD GLB_REG_GPIO_18_PD -#define GLB_REG_GPIO_18_PD_POS (5U) -#define GLB_REG_GPIO_18_PD_LEN (1U) +#define GLB_REG_GPIO_18_PD_POS (5) +#define GLB_REG_GPIO_18_PD_LEN (1) #define GLB_REG_GPIO_18_PD_MSK \ - (((1U << GLB_REG_GPIO_18_PD_LEN) - 1) << GLB_REG_GPIO_18_PD_POS) + (((1 << GLB_REG_GPIO_18_PD_LEN) - 1) << GLB_REG_GPIO_18_PD_POS) #define GLB_REG_GPIO_18_PD_UMSK \ - (~(((1U << GLB_REG_GPIO_18_PD_LEN) - 1) << GLB_REG_GPIO_18_PD_POS)) + (~(((1 << GLB_REG_GPIO_18_PD_LEN) - 1) << GLB_REG_GPIO_18_PD_POS)) #define GLB_REG_GPIO_18_FUNC_SEL GLB_REG_GPIO_18_FUNC_SEL -#define GLB_REG_GPIO_18_FUNC_SEL_POS (8U) -#define GLB_REG_GPIO_18_FUNC_SEL_LEN (4U) +#define GLB_REG_GPIO_18_FUNC_SEL_POS (8) +#define GLB_REG_GPIO_18_FUNC_SEL_LEN (4) #define GLB_REG_GPIO_18_FUNC_SEL_MSK \ - (((1U << GLB_REG_GPIO_18_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_18_FUNC_SEL_POS) + (((1 << GLB_REG_GPIO_18_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_18_FUNC_SEL_POS) #define GLB_REG_GPIO_18_FUNC_SEL_UMSK \ - (~(((1U << GLB_REG_GPIO_18_FUNC_SEL_LEN) - 1) \ + (~(((1 << GLB_REG_GPIO_18_FUNC_SEL_LEN) - 1) \ << GLB_REG_GPIO_18_FUNC_SEL_POS)) #define GLB_REG_GPIO_19_IE GLB_REG_GPIO_19_IE -#define GLB_REG_GPIO_19_IE_POS (16U) -#define GLB_REG_GPIO_19_IE_LEN (1U) +#define GLB_REG_GPIO_19_IE_POS (16) +#define GLB_REG_GPIO_19_IE_LEN (1) #define GLB_REG_GPIO_19_IE_MSK \ - (((1U << GLB_REG_GPIO_19_IE_LEN) - 1) << GLB_REG_GPIO_19_IE_POS) + (((1 << GLB_REG_GPIO_19_IE_LEN) - 1) << GLB_REG_GPIO_19_IE_POS) #define GLB_REG_GPIO_19_IE_UMSK \ - (~(((1U << GLB_REG_GPIO_19_IE_LEN) - 1) << GLB_REG_GPIO_19_IE_POS)) + (~(((1 << GLB_REG_GPIO_19_IE_LEN) - 1) << GLB_REG_GPIO_19_IE_POS)) #define GLB_REG_GPIO_19_SMT GLB_REG_GPIO_19_SMT -#define GLB_REG_GPIO_19_SMT_POS (17U) -#define GLB_REG_GPIO_19_SMT_LEN (1U) +#define GLB_REG_GPIO_19_SMT_POS (17) +#define GLB_REG_GPIO_19_SMT_LEN (1) #define GLB_REG_GPIO_19_SMT_MSK \ - (((1U << GLB_REG_GPIO_19_SMT_LEN) - 1) << GLB_REG_GPIO_19_SMT_POS) + (((1 << GLB_REG_GPIO_19_SMT_LEN) - 1) << GLB_REG_GPIO_19_SMT_POS) #define GLB_REG_GPIO_19_SMT_UMSK \ - (~(((1U << GLB_REG_GPIO_19_SMT_LEN) - 1) << GLB_REG_GPIO_19_SMT_POS)) + (~(((1 << GLB_REG_GPIO_19_SMT_LEN) - 1) << GLB_REG_GPIO_19_SMT_POS)) #define GLB_REG_GPIO_19_DRV GLB_REG_GPIO_19_DRV -#define GLB_REG_GPIO_19_DRV_POS (18U) -#define GLB_REG_GPIO_19_DRV_LEN (2U) +#define GLB_REG_GPIO_19_DRV_POS (18) +#define GLB_REG_GPIO_19_DRV_LEN (2) #define GLB_REG_GPIO_19_DRV_MSK \ - (((1U << GLB_REG_GPIO_19_DRV_LEN) - 1) << GLB_REG_GPIO_19_DRV_POS) + (((1 << GLB_REG_GPIO_19_DRV_LEN) - 1) << GLB_REG_GPIO_19_DRV_POS) #define GLB_REG_GPIO_19_DRV_UMSK \ - (~(((1U << GLB_REG_GPIO_19_DRV_LEN) - 1) << GLB_REG_GPIO_19_DRV_POS)) + (~(((1 << GLB_REG_GPIO_19_DRV_LEN) - 1) << GLB_REG_GPIO_19_DRV_POS)) #define GLB_REG_GPIO_19_PU GLB_REG_GPIO_19_PU -#define GLB_REG_GPIO_19_PU_POS (20U) -#define GLB_REG_GPIO_19_PU_LEN (1U) +#define GLB_REG_GPIO_19_PU_POS (20) +#define GLB_REG_GPIO_19_PU_LEN (1) #define GLB_REG_GPIO_19_PU_MSK \ - (((1U << GLB_REG_GPIO_19_PU_LEN) - 1) << GLB_REG_GPIO_19_PU_POS) + (((1 << GLB_REG_GPIO_19_PU_LEN) - 1) << GLB_REG_GPIO_19_PU_POS) #define GLB_REG_GPIO_19_PU_UMSK \ - (~(((1U << GLB_REG_GPIO_19_PU_LEN) - 1) << GLB_REG_GPIO_19_PU_POS)) + (~(((1 << GLB_REG_GPIO_19_PU_LEN) - 1) << GLB_REG_GPIO_19_PU_POS)) #define GLB_REG_GPIO_19_PD GLB_REG_GPIO_19_PD -#define GLB_REG_GPIO_19_PD_POS (21U) -#define GLB_REG_GPIO_19_PD_LEN (1U) +#define GLB_REG_GPIO_19_PD_POS (21) +#define GLB_REG_GPIO_19_PD_LEN (1) #define GLB_REG_GPIO_19_PD_MSK \ - (((1U << GLB_REG_GPIO_19_PD_LEN) - 1) << GLB_REG_GPIO_19_PD_POS) + (((1 << GLB_REG_GPIO_19_PD_LEN) - 1) << GLB_REG_GPIO_19_PD_POS) #define GLB_REG_GPIO_19_PD_UMSK \ - (~(((1U << GLB_REG_GPIO_19_PD_LEN) - 1) << GLB_REG_GPIO_19_PD_POS)) + (~(((1 << GLB_REG_GPIO_19_PD_LEN) - 1) << GLB_REG_GPIO_19_PD_POS)) #define GLB_REG_GPIO_19_FUNC_SEL GLB_REG_GPIO_19_FUNC_SEL -#define GLB_REG_GPIO_19_FUNC_SEL_POS (24U) -#define GLB_REG_GPIO_19_FUNC_SEL_LEN (4U) +#define GLB_REG_GPIO_19_FUNC_SEL_POS (24) +#define GLB_REG_GPIO_19_FUNC_SEL_LEN (4) #define GLB_REG_GPIO_19_FUNC_SEL_MSK \ - (((1U << GLB_REG_GPIO_19_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_19_FUNC_SEL_POS) + (((1 << GLB_REG_GPIO_19_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_19_FUNC_SEL_POS) #define GLB_REG_GPIO_19_FUNC_SEL_UMSK \ - (~(((1U << GLB_REG_GPIO_19_FUNC_SEL_LEN) - 1) \ + (~(((1 << GLB_REG_GPIO_19_FUNC_SEL_LEN) - 1) \ << GLB_REG_GPIO_19_FUNC_SEL_POS)) /* 0x128 : GPIO_CFGCTL10 */ #define GLB_GPIO_CFGCTL10_OFFSET (0x128) #define GLB_REG_GPIO_20_IE GLB_REG_GPIO_20_IE -#define GLB_REG_GPIO_20_IE_POS (0U) -#define GLB_REG_GPIO_20_IE_LEN (1U) +#define GLB_REG_GPIO_20_IE_POS (0) +#define GLB_REG_GPIO_20_IE_LEN (1) #define GLB_REG_GPIO_20_IE_MSK \ - (((1U << GLB_REG_GPIO_20_IE_LEN) - 1) << GLB_REG_GPIO_20_IE_POS) + (((1 << GLB_REG_GPIO_20_IE_LEN) - 1) << GLB_REG_GPIO_20_IE_POS) #define GLB_REG_GPIO_20_IE_UMSK \ - (~(((1U << GLB_REG_GPIO_20_IE_LEN) - 1) << GLB_REG_GPIO_20_IE_POS)) + (~(((1 << GLB_REG_GPIO_20_IE_LEN) - 1) << GLB_REG_GPIO_20_IE_POS)) #define GLB_REG_GPIO_20_SMT GLB_REG_GPIO_20_SMT -#define GLB_REG_GPIO_20_SMT_POS (1U) -#define GLB_REG_GPIO_20_SMT_LEN (1U) +#define GLB_REG_GPIO_20_SMT_POS (1) +#define GLB_REG_GPIO_20_SMT_LEN (1) #define GLB_REG_GPIO_20_SMT_MSK \ - (((1U << GLB_REG_GPIO_20_SMT_LEN) - 1) << GLB_REG_GPIO_20_SMT_POS) + (((1 << GLB_REG_GPIO_20_SMT_LEN) - 1) << GLB_REG_GPIO_20_SMT_POS) #define GLB_REG_GPIO_20_SMT_UMSK \ - (~(((1U << GLB_REG_GPIO_20_SMT_LEN) - 1) << GLB_REG_GPIO_20_SMT_POS)) + (~(((1 << GLB_REG_GPIO_20_SMT_LEN) - 1) << GLB_REG_GPIO_20_SMT_POS)) #define GLB_REG_GPIO_20_DRV GLB_REG_GPIO_20_DRV -#define GLB_REG_GPIO_20_DRV_POS (2U) -#define GLB_REG_GPIO_20_DRV_LEN (2U) +#define GLB_REG_GPIO_20_DRV_POS (2) +#define GLB_REG_GPIO_20_DRV_LEN (2) #define GLB_REG_GPIO_20_DRV_MSK \ - (((1U << GLB_REG_GPIO_20_DRV_LEN) - 1) << GLB_REG_GPIO_20_DRV_POS) + (((1 << GLB_REG_GPIO_20_DRV_LEN) - 1) << GLB_REG_GPIO_20_DRV_POS) #define GLB_REG_GPIO_20_DRV_UMSK \ - (~(((1U << GLB_REG_GPIO_20_DRV_LEN) - 1) << GLB_REG_GPIO_20_DRV_POS)) + (~(((1 << GLB_REG_GPIO_20_DRV_LEN) - 1) << GLB_REG_GPIO_20_DRV_POS)) #define GLB_REG_GPIO_20_PU GLB_REG_GPIO_20_PU -#define GLB_REG_GPIO_20_PU_POS (4U) -#define GLB_REG_GPIO_20_PU_LEN (1U) +#define GLB_REG_GPIO_20_PU_POS (4) +#define GLB_REG_GPIO_20_PU_LEN (1) #define GLB_REG_GPIO_20_PU_MSK \ - (((1U << GLB_REG_GPIO_20_PU_LEN) - 1) << GLB_REG_GPIO_20_PU_POS) + (((1 << GLB_REG_GPIO_20_PU_LEN) - 1) << GLB_REG_GPIO_20_PU_POS) #define GLB_REG_GPIO_20_PU_UMSK \ - (~(((1U << GLB_REG_GPIO_20_PU_LEN) - 1) << GLB_REG_GPIO_20_PU_POS)) + (~(((1 << GLB_REG_GPIO_20_PU_LEN) - 1) << GLB_REG_GPIO_20_PU_POS)) #define GLB_REG_GPIO_20_PD GLB_REG_GPIO_20_PD -#define GLB_REG_GPIO_20_PD_POS (5U) -#define GLB_REG_GPIO_20_PD_LEN (1U) +#define GLB_REG_GPIO_20_PD_POS (5) +#define GLB_REG_GPIO_20_PD_LEN (1) #define GLB_REG_GPIO_20_PD_MSK \ - (((1U << GLB_REG_GPIO_20_PD_LEN) - 1) << GLB_REG_GPIO_20_PD_POS) + (((1 << GLB_REG_GPIO_20_PD_LEN) - 1) << GLB_REG_GPIO_20_PD_POS) #define GLB_REG_GPIO_20_PD_UMSK \ - (~(((1U << GLB_REG_GPIO_20_PD_LEN) - 1) << GLB_REG_GPIO_20_PD_POS)) + (~(((1 << GLB_REG_GPIO_20_PD_LEN) - 1) << GLB_REG_GPIO_20_PD_POS)) #define GLB_REG_GPIO_20_FUNC_SEL GLB_REG_GPIO_20_FUNC_SEL -#define GLB_REG_GPIO_20_FUNC_SEL_POS (8U) -#define GLB_REG_GPIO_20_FUNC_SEL_LEN (4U) +#define GLB_REG_GPIO_20_FUNC_SEL_POS (8) +#define GLB_REG_GPIO_20_FUNC_SEL_LEN (4) #define GLB_REG_GPIO_20_FUNC_SEL_MSK \ - (((1U << GLB_REG_GPIO_20_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_20_FUNC_SEL_POS) + (((1 << GLB_REG_GPIO_20_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_20_FUNC_SEL_POS) #define GLB_REG_GPIO_20_FUNC_SEL_UMSK \ - (~(((1U << GLB_REG_GPIO_20_FUNC_SEL_LEN) - 1) \ + (~(((1 << GLB_REG_GPIO_20_FUNC_SEL_LEN) - 1) \ << GLB_REG_GPIO_20_FUNC_SEL_POS)) #define GLB_REG_GPIO_21_IE GLB_REG_GPIO_21_IE -#define GLB_REG_GPIO_21_IE_POS (16U) -#define GLB_REG_GPIO_21_IE_LEN (1U) +#define GLB_REG_GPIO_21_IE_POS (16) +#define GLB_REG_GPIO_21_IE_LEN (1) #define GLB_REG_GPIO_21_IE_MSK \ - (((1U << GLB_REG_GPIO_21_IE_LEN) - 1) << GLB_REG_GPIO_21_IE_POS) + (((1 << GLB_REG_GPIO_21_IE_LEN) - 1) << GLB_REG_GPIO_21_IE_POS) #define GLB_REG_GPIO_21_IE_UMSK \ - (~(((1U << GLB_REG_GPIO_21_IE_LEN) - 1) << GLB_REG_GPIO_21_IE_POS)) + (~(((1 << GLB_REG_GPIO_21_IE_LEN) - 1) << GLB_REG_GPIO_21_IE_POS)) #define GLB_REG_GPIO_21_SMT GLB_REG_GPIO_21_SMT -#define GLB_REG_GPIO_21_SMT_POS (17U) -#define GLB_REG_GPIO_21_SMT_LEN (1U) +#define GLB_REG_GPIO_21_SMT_POS (17) +#define GLB_REG_GPIO_21_SMT_LEN (1) #define GLB_REG_GPIO_21_SMT_MSK \ - (((1U << GLB_REG_GPIO_21_SMT_LEN) - 1) << GLB_REG_GPIO_21_SMT_POS) + (((1 << GLB_REG_GPIO_21_SMT_LEN) - 1) << GLB_REG_GPIO_21_SMT_POS) #define GLB_REG_GPIO_21_SMT_UMSK \ - (~(((1U << GLB_REG_GPIO_21_SMT_LEN) - 1) << GLB_REG_GPIO_21_SMT_POS)) + (~(((1 << GLB_REG_GPIO_21_SMT_LEN) - 1) << GLB_REG_GPIO_21_SMT_POS)) #define GLB_REG_GPIO_21_DRV GLB_REG_GPIO_21_DRV -#define GLB_REG_GPIO_21_DRV_POS (18U) -#define GLB_REG_GPIO_21_DRV_LEN (2U) +#define GLB_REG_GPIO_21_DRV_POS (18) +#define GLB_REG_GPIO_21_DRV_LEN (2) #define GLB_REG_GPIO_21_DRV_MSK \ - (((1U << GLB_REG_GPIO_21_DRV_LEN) - 1) << GLB_REG_GPIO_21_DRV_POS) + (((1 << GLB_REG_GPIO_21_DRV_LEN) - 1) << GLB_REG_GPIO_21_DRV_POS) #define GLB_REG_GPIO_21_DRV_UMSK \ - (~(((1U << GLB_REG_GPIO_21_DRV_LEN) - 1) << GLB_REG_GPIO_21_DRV_POS)) + (~(((1 << GLB_REG_GPIO_21_DRV_LEN) - 1) << GLB_REG_GPIO_21_DRV_POS)) #define GLB_REG_GPIO_21_PU GLB_REG_GPIO_21_PU -#define GLB_REG_GPIO_21_PU_POS (20U) -#define GLB_REG_GPIO_21_PU_LEN (1U) +#define GLB_REG_GPIO_21_PU_POS (20) +#define GLB_REG_GPIO_21_PU_LEN (1) #define GLB_REG_GPIO_21_PU_MSK \ - (((1U << GLB_REG_GPIO_21_PU_LEN) - 1) << GLB_REG_GPIO_21_PU_POS) + (((1 << GLB_REG_GPIO_21_PU_LEN) - 1) << GLB_REG_GPIO_21_PU_POS) #define GLB_REG_GPIO_21_PU_UMSK \ - (~(((1U << GLB_REG_GPIO_21_PU_LEN) - 1) << GLB_REG_GPIO_21_PU_POS)) + (~(((1 << GLB_REG_GPIO_21_PU_LEN) - 1) << GLB_REG_GPIO_21_PU_POS)) #define GLB_REG_GPIO_21_PD GLB_REG_GPIO_21_PD -#define GLB_REG_GPIO_21_PD_POS (21U) -#define GLB_REG_GPIO_21_PD_LEN (1U) +#define GLB_REG_GPIO_21_PD_POS (21) +#define GLB_REG_GPIO_21_PD_LEN (1) #define GLB_REG_GPIO_21_PD_MSK \ - (((1U << GLB_REG_GPIO_21_PD_LEN) - 1) << GLB_REG_GPIO_21_PD_POS) + (((1 << GLB_REG_GPIO_21_PD_LEN) - 1) << GLB_REG_GPIO_21_PD_POS) #define GLB_REG_GPIO_21_PD_UMSK \ - (~(((1U << GLB_REG_GPIO_21_PD_LEN) - 1) << GLB_REG_GPIO_21_PD_POS)) + (~(((1 << GLB_REG_GPIO_21_PD_LEN) - 1) << GLB_REG_GPIO_21_PD_POS)) #define GLB_REG_GPIO_21_FUNC_SEL GLB_REG_GPIO_21_FUNC_SEL -#define GLB_REG_GPIO_21_FUNC_SEL_POS (24U) -#define GLB_REG_GPIO_21_FUNC_SEL_LEN (4U) +#define GLB_REG_GPIO_21_FUNC_SEL_POS (24) +#define GLB_REG_GPIO_21_FUNC_SEL_LEN (4) #define GLB_REG_GPIO_21_FUNC_SEL_MSK \ - (((1U << GLB_REG_GPIO_21_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_21_FUNC_SEL_POS) + (((1 << GLB_REG_GPIO_21_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_21_FUNC_SEL_POS) #define GLB_REG_GPIO_21_FUNC_SEL_UMSK \ - (~(((1U << GLB_REG_GPIO_21_FUNC_SEL_LEN) - 1) \ + (~(((1 << GLB_REG_GPIO_21_FUNC_SEL_LEN) - 1) \ << GLB_REG_GPIO_21_FUNC_SEL_POS)) /* 0x12C : GPIO_CFGCTL11 */ #define GLB_GPIO_CFGCTL11_OFFSET (0x12C) #define GLB_REG_GPIO_22_IE GLB_REG_GPIO_22_IE -#define GLB_REG_GPIO_22_IE_POS (0U) -#define GLB_REG_GPIO_22_IE_LEN (1U) +#define GLB_REG_GPIO_22_IE_POS (0) +#define GLB_REG_GPIO_22_IE_LEN (1) #define GLB_REG_GPIO_22_IE_MSK \ - (((1U << GLB_REG_GPIO_22_IE_LEN) - 1) << GLB_REG_GPIO_22_IE_POS) + (((1 << GLB_REG_GPIO_22_IE_LEN) - 1) << GLB_REG_GPIO_22_IE_POS) #define GLB_REG_GPIO_22_IE_UMSK \ - (~(((1U << GLB_REG_GPIO_22_IE_LEN) - 1) << GLB_REG_GPIO_22_IE_POS)) + (~(((1 << GLB_REG_GPIO_22_IE_LEN) - 1) << GLB_REG_GPIO_22_IE_POS)) #define GLB_REG_GPIO_22_SMT GLB_REG_GPIO_22_SMT -#define GLB_REG_GPIO_22_SMT_POS (1U) -#define GLB_REG_GPIO_22_SMT_LEN (1U) +#define GLB_REG_GPIO_22_SMT_POS (1) +#define GLB_REG_GPIO_22_SMT_LEN (1) #define GLB_REG_GPIO_22_SMT_MSK \ - (((1U << GLB_REG_GPIO_22_SMT_LEN) - 1) << GLB_REG_GPIO_22_SMT_POS) + (((1 << GLB_REG_GPIO_22_SMT_LEN) - 1) << GLB_REG_GPIO_22_SMT_POS) #define GLB_REG_GPIO_22_SMT_UMSK \ - (~(((1U << GLB_REG_GPIO_22_SMT_LEN) - 1) << GLB_REG_GPIO_22_SMT_POS)) + (~(((1 << GLB_REG_GPIO_22_SMT_LEN) - 1) << GLB_REG_GPIO_22_SMT_POS)) #define GLB_REG_GPIO_22_DRV GLB_REG_GPIO_22_DRV -#define GLB_REG_GPIO_22_DRV_POS (2U) -#define GLB_REG_GPIO_22_DRV_LEN (2U) +#define GLB_REG_GPIO_22_DRV_POS (2) +#define GLB_REG_GPIO_22_DRV_LEN (2) #define GLB_REG_GPIO_22_DRV_MSK \ - (((1U << GLB_REG_GPIO_22_DRV_LEN) - 1) << GLB_REG_GPIO_22_DRV_POS) + (((1 << GLB_REG_GPIO_22_DRV_LEN) - 1) << GLB_REG_GPIO_22_DRV_POS) #define GLB_REG_GPIO_22_DRV_UMSK \ - (~(((1U << GLB_REG_GPIO_22_DRV_LEN) - 1) << GLB_REG_GPIO_22_DRV_POS)) + (~(((1 << GLB_REG_GPIO_22_DRV_LEN) - 1) << GLB_REG_GPIO_22_DRV_POS)) #define GLB_REG_GPIO_22_PU GLB_REG_GPIO_22_PU -#define GLB_REG_GPIO_22_PU_POS (4U) -#define GLB_REG_GPIO_22_PU_LEN (1U) +#define GLB_REG_GPIO_22_PU_POS (4) +#define GLB_REG_GPIO_22_PU_LEN (1) #define GLB_REG_GPIO_22_PU_MSK \ - (((1U << GLB_REG_GPIO_22_PU_LEN) - 1) << GLB_REG_GPIO_22_PU_POS) + (((1 << GLB_REG_GPIO_22_PU_LEN) - 1) << GLB_REG_GPIO_22_PU_POS) #define GLB_REG_GPIO_22_PU_UMSK \ - (~(((1U << GLB_REG_GPIO_22_PU_LEN) - 1) << GLB_REG_GPIO_22_PU_POS)) + (~(((1 << GLB_REG_GPIO_22_PU_LEN) - 1) << GLB_REG_GPIO_22_PU_POS)) #define GLB_REG_GPIO_22_PD GLB_REG_GPIO_22_PD -#define GLB_REG_GPIO_22_PD_POS (5U) -#define GLB_REG_GPIO_22_PD_LEN (1U) +#define GLB_REG_GPIO_22_PD_POS (5) +#define GLB_REG_GPIO_22_PD_LEN (1) #define GLB_REG_GPIO_22_PD_MSK \ - (((1U << GLB_REG_GPIO_22_PD_LEN) - 1) << GLB_REG_GPIO_22_PD_POS) + (((1 << GLB_REG_GPIO_22_PD_LEN) - 1) << GLB_REG_GPIO_22_PD_POS) #define GLB_REG_GPIO_22_PD_UMSK \ - (~(((1U << GLB_REG_GPIO_22_PD_LEN) - 1) << GLB_REG_GPIO_22_PD_POS)) + (~(((1 << GLB_REG_GPIO_22_PD_LEN) - 1) << GLB_REG_GPIO_22_PD_POS)) #define GLB_REG_GPIO_22_FUNC_SEL GLB_REG_GPIO_22_FUNC_SEL -#define GLB_REG_GPIO_22_FUNC_SEL_POS (8U) -#define GLB_REG_GPIO_22_FUNC_SEL_LEN (4U) +#define GLB_REG_GPIO_22_FUNC_SEL_POS (8) +#define GLB_REG_GPIO_22_FUNC_SEL_LEN (4) #define GLB_REG_GPIO_22_FUNC_SEL_MSK \ - (((1U << GLB_REG_GPIO_22_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_22_FUNC_SEL_POS) + (((1 << GLB_REG_GPIO_22_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_22_FUNC_SEL_POS) #define GLB_REG_GPIO_22_FUNC_SEL_UMSK \ - (~(((1U << GLB_REG_GPIO_22_FUNC_SEL_LEN) - 1) \ + (~(((1 << GLB_REG_GPIO_22_FUNC_SEL_LEN) - 1) \ << GLB_REG_GPIO_22_FUNC_SEL_POS)) #define GLB_REG_GPIO_23_IE GLB_REG_GPIO_23_IE -#define GLB_REG_GPIO_23_IE_POS (16U) -#define GLB_REG_GPIO_23_IE_LEN (1U) +#define GLB_REG_GPIO_23_IE_POS (16) +#define GLB_REG_GPIO_23_IE_LEN (1) #define GLB_REG_GPIO_23_IE_MSK \ - (((1U << GLB_REG_GPIO_23_IE_LEN) - 1) << GLB_REG_GPIO_23_IE_POS) + (((1 << GLB_REG_GPIO_23_IE_LEN) - 1) << GLB_REG_GPIO_23_IE_POS) #define GLB_REG_GPIO_23_IE_UMSK \ - (~(((1U << GLB_REG_GPIO_23_IE_LEN) - 1) << GLB_REG_GPIO_23_IE_POS)) + (~(((1 << GLB_REG_GPIO_23_IE_LEN) - 1) << GLB_REG_GPIO_23_IE_POS)) #define GLB_REG_GPIO_23_SMT GLB_REG_GPIO_23_SMT -#define GLB_REG_GPIO_23_SMT_POS (17U) -#define GLB_REG_GPIO_23_SMT_LEN (1U) +#define GLB_REG_GPIO_23_SMT_POS (17) +#define GLB_REG_GPIO_23_SMT_LEN (1) #define GLB_REG_GPIO_23_SMT_MSK \ - (((1U << GLB_REG_GPIO_23_SMT_LEN) - 1) << GLB_REG_GPIO_23_SMT_POS) + (((1 << GLB_REG_GPIO_23_SMT_LEN) - 1) << GLB_REG_GPIO_23_SMT_POS) #define GLB_REG_GPIO_23_SMT_UMSK \ - (~(((1U << GLB_REG_GPIO_23_SMT_LEN) - 1) << GLB_REG_GPIO_23_SMT_POS)) + (~(((1 << GLB_REG_GPIO_23_SMT_LEN) - 1) << GLB_REG_GPIO_23_SMT_POS)) #define GLB_REG_GPIO_23_DRV GLB_REG_GPIO_23_DRV -#define GLB_REG_GPIO_23_DRV_POS (18U) -#define GLB_REG_GPIO_23_DRV_LEN (2U) +#define GLB_REG_GPIO_23_DRV_POS (18) +#define GLB_REG_GPIO_23_DRV_LEN (2) #define GLB_REG_GPIO_23_DRV_MSK \ - (((1U << GLB_REG_GPIO_23_DRV_LEN) - 1) << GLB_REG_GPIO_23_DRV_POS) + (((1 << GLB_REG_GPIO_23_DRV_LEN) - 1) << GLB_REG_GPIO_23_DRV_POS) #define GLB_REG_GPIO_23_DRV_UMSK \ - (~(((1U << GLB_REG_GPIO_23_DRV_LEN) - 1) << GLB_REG_GPIO_23_DRV_POS)) + (~(((1 << GLB_REG_GPIO_23_DRV_LEN) - 1) << GLB_REG_GPIO_23_DRV_POS)) #define GLB_REG_GPIO_23_PU GLB_REG_GPIO_23_PU -#define GLB_REG_GPIO_23_PU_POS (20U) -#define GLB_REG_GPIO_23_PU_LEN (1U) +#define GLB_REG_GPIO_23_PU_POS (20) +#define GLB_REG_GPIO_23_PU_LEN (1) #define GLB_REG_GPIO_23_PU_MSK \ - (((1U << GLB_REG_GPIO_23_PU_LEN) - 1) << GLB_REG_GPIO_23_PU_POS) + (((1 << GLB_REG_GPIO_23_PU_LEN) - 1) << GLB_REG_GPIO_23_PU_POS) #define GLB_REG_GPIO_23_PU_UMSK \ - (~(((1U << GLB_REG_GPIO_23_PU_LEN) - 1) << GLB_REG_GPIO_23_PU_POS)) + (~(((1 << GLB_REG_GPIO_23_PU_LEN) - 1) << GLB_REG_GPIO_23_PU_POS)) #define GLB_REG_GPIO_23_PD GLB_REG_GPIO_23_PD -#define GLB_REG_GPIO_23_PD_POS (21U) -#define GLB_REG_GPIO_23_PD_LEN (1U) +#define GLB_REG_GPIO_23_PD_POS (21) +#define GLB_REG_GPIO_23_PD_LEN (1) #define GLB_REG_GPIO_23_PD_MSK \ - (((1U << GLB_REG_GPIO_23_PD_LEN) - 1) << GLB_REG_GPIO_23_PD_POS) + (((1 << GLB_REG_GPIO_23_PD_LEN) - 1) << GLB_REG_GPIO_23_PD_POS) #define GLB_REG_GPIO_23_PD_UMSK \ - (~(((1U << GLB_REG_GPIO_23_PD_LEN) - 1) << GLB_REG_GPIO_23_PD_POS)) + (~(((1 << GLB_REG_GPIO_23_PD_LEN) - 1) << GLB_REG_GPIO_23_PD_POS)) /* 0x130 : GPIO_CFGCTL12 */ #define GLB_GPIO_CFGCTL12_OFFSET (0x130) #define GLB_REG_GPIO_24_IE GLB_REG_GPIO_24_IE -#define GLB_REG_GPIO_24_IE_POS (0U) -#define GLB_REG_GPIO_24_IE_LEN (1U) +#define GLB_REG_GPIO_24_IE_POS (0) +#define GLB_REG_GPIO_24_IE_LEN (1) #define GLB_REG_GPIO_24_IE_MSK \ - (((1U << GLB_REG_GPIO_24_IE_LEN) - 1) << GLB_REG_GPIO_24_IE_POS) + (((1 << GLB_REG_GPIO_24_IE_LEN) - 1) << GLB_REG_GPIO_24_IE_POS) #define GLB_REG_GPIO_24_IE_UMSK \ - (~(((1U << GLB_REG_GPIO_24_IE_LEN) - 1) << GLB_REG_GPIO_24_IE_POS)) + (~(((1 << GLB_REG_GPIO_24_IE_LEN) - 1) << GLB_REG_GPIO_24_IE_POS)) #define GLB_REG_GPIO_24_SMT GLB_REG_GPIO_24_SMT -#define GLB_REG_GPIO_24_SMT_POS (1U) -#define GLB_REG_GPIO_24_SMT_LEN (1U) +#define GLB_REG_GPIO_24_SMT_POS (1) +#define GLB_REG_GPIO_24_SMT_LEN (1) #define GLB_REG_GPIO_24_SMT_MSK \ - (((1U << GLB_REG_GPIO_24_SMT_LEN) - 1) << GLB_REG_GPIO_24_SMT_POS) + (((1 << GLB_REG_GPIO_24_SMT_LEN) - 1) << GLB_REG_GPIO_24_SMT_POS) #define GLB_REG_GPIO_24_SMT_UMSK \ - (~(((1U << GLB_REG_GPIO_24_SMT_LEN) - 1) << GLB_REG_GPIO_24_SMT_POS)) + (~(((1 << GLB_REG_GPIO_24_SMT_LEN) - 1) << GLB_REG_GPIO_24_SMT_POS)) #define GLB_REG_GPIO_24_DRV GLB_REG_GPIO_24_DRV -#define GLB_REG_GPIO_24_DRV_POS (2U) -#define GLB_REG_GPIO_24_DRV_LEN (2U) +#define GLB_REG_GPIO_24_DRV_POS (2) +#define GLB_REG_GPIO_24_DRV_LEN (2) #define GLB_REG_GPIO_24_DRV_MSK \ - (((1U << GLB_REG_GPIO_24_DRV_LEN) - 1) << GLB_REG_GPIO_24_DRV_POS) + (((1 << GLB_REG_GPIO_24_DRV_LEN) - 1) << GLB_REG_GPIO_24_DRV_POS) #define GLB_REG_GPIO_24_DRV_UMSK \ - (~(((1U << GLB_REG_GPIO_24_DRV_LEN) - 1) << GLB_REG_GPIO_24_DRV_POS)) + (~(((1 << GLB_REG_GPIO_24_DRV_LEN) - 1) << GLB_REG_GPIO_24_DRV_POS)) #define GLB_REG_GPIO_24_PU GLB_REG_GPIO_24_PU -#define GLB_REG_GPIO_24_PU_POS (4U) -#define GLB_REG_GPIO_24_PU_LEN (1U) +#define GLB_REG_GPIO_24_PU_POS (4) +#define GLB_REG_GPIO_24_PU_LEN (1) #define GLB_REG_GPIO_24_PU_MSK \ - (((1U << GLB_REG_GPIO_24_PU_LEN) - 1) << GLB_REG_GPIO_24_PU_POS) + (((1 << GLB_REG_GPIO_24_PU_LEN) - 1) << GLB_REG_GPIO_24_PU_POS) #define GLB_REG_GPIO_24_PU_UMSK \ - (~(((1U << GLB_REG_GPIO_24_PU_LEN) - 1) << GLB_REG_GPIO_24_PU_POS)) + (~(((1 << GLB_REG_GPIO_24_PU_LEN) - 1) << GLB_REG_GPIO_24_PU_POS)) #define GLB_REG_GPIO_24_PD GLB_REG_GPIO_24_PD -#define GLB_REG_GPIO_24_PD_POS (5U) -#define GLB_REG_GPIO_24_PD_LEN (1U) +#define GLB_REG_GPIO_24_PD_POS (5) +#define GLB_REG_GPIO_24_PD_LEN (1) #define GLB_REG_GPIO_24_PD_MSK \ - (((1U << GLB_REG_GPIO_24_PD_LEN) - 1) << GLB_REG_GPIO_24_PD_POS) + (((1 << GLB_REG_GPIO_24_PD_LEN) - 1) << GLB_REG_GPIO_24_PD_POS) #define GLB_REG_GPIO_24_PD_UMSK \ - (~(((1U << GLB_REG_GPIO_24_PD_LEN) - 1) << GLB_REG_GPIO_24_PD_POS)) + (~(((1 << GLB_REG_GPIO_24_PD_LEN) - 1) << GLB_REG_GPIO_24_PD_POS)) #define GLB_REG_GPIO_25_IE GLB_REG_GPIO_25_IE -#define GLB_REG_GPIO_25_IE_POS (16U) -#define GLB_REG_GPIO_25_IE_LEN (1U) +#define GLB_REG_GPIO_25_IE_POS (16) +#define GLB_REG_GPIO_25_IE_LEN (1) #define GLB_REG_GPIO_25_IE_MSK \ - (((1U << GLB_REG_GPIO_25_IE_LEN) - 1) << GLB_REG_GPIO_25_IE_POS) + (((1 << GLB_REG_GPIO_25_IE_LEN) - 1) << GLB_REG_GPIO_25_IE_POS) #define GLB_REG_GPIO_25_IE_UMSK \ - (~(((1U << GLB_REG_GPIO_25_IE_LEN) - 1) << GLB_REG_GPIO_25_IE_POS)) + (~(((1 << GLB_REG_GPIO_25_IE_LEN) - 1) << GLB_REG_GPIO_25_IE_POS)) #define GLB_REG_GPIO_25_SMT GLB_REG_GPIO_25_SMT -#define GLB_REG_GPIO_25_SMT_POS (17U) -#define GLB_REG_GPIO_25_SMT_LEN (1U) +#define GLB_REG_GPIO_25_SMT_POS (17) +#define GLB_REG_GPIO_25_SMT_LEN (1) #define GLB_REG_GPIO_25_SMT_MSK \ - (((1U << GLB_REG_GPIO_25_SMT_LEN) - 1) << GLB_REG_GPIO_25_SMT_POS) + (((1 << GLB_REG_GPIO_25_SMT_LEN) - 1) << GLB_REG_GPIO_25_SMT_POS) #define GLB_REG_GPIO_25_SMT_UMSK \ - (~(((1U << GLB_REG_GPIO_25_SMT_LEN) - 1) << GLB_REG_GPIO_25_SMT_POS)) + (~(((1 << GLB_REG_GPIO_25_SMT_LEN) - 1) << GLB_REG_GPIO_25_SMT_POS)) #define GLB_REG_GPIO_25_DRV GLB_REG_GPIO_25_DRV -#define GLB_REG_GPIO_25_DRV_POS (18U) -#define GLB_REG_GPIO_25_DRV_LEN (2U) +#define GLB_REG_GPIO_25_DRV_POS (18) +#define GLB_REG_GPIO_25_DRV_LEN (2) #define GLB_REG_GPIO_25_DRV_MSK \ - (((1U << GLB_REG_GPIO_25_DRV_LEN) - 1) << GLB_REG_GPIO_25_DRV_POS) + (((1 << GLB_REG_GPIO_25_DRV_LEN) - 1) << GLB_REG_GPIO_25_DRV_POS) #define GLB_REG_GPIO_25_DRV_UMSK \ - (~(((1U << GLB_REG_GPIO_25_DRV_LEN) - 1) << GLB_REG_GPIO_25_DRV_POS)) + (~(((1 << GLB_REG_GPIO_25_DRV_LEN) - 1) << GLB_REG_GPIO_25_DRV_POS)) #define GLB_REG_GPIO_25_PU GLB_REG_GPIO_25_PU -#define GLB_REG_GPIO_25_PU_POS (20U) -#define GLB_REG_GPIO_25_PU_LEN (1U) +#define GLB_REG_GPIO_25_PU_POS (20) +#define GLB_REG_GPIO_25_PU_LEN (1) #define GLB_REG_GPIO_25_PU_MSK \ - (((1U << GLB_REG_GPIO_25_PU_LEN) - 1) << GLB_REG_GPIO_25_PU_POS) + (((1 << GLB_REG_GPIO_25_PU_LEN) - 1) << GLB_REG_GPIO_25_PU_POS) #define GLB_REG_GPIO_25_PU_UMSK \ - (~(((1U << GLB_REG_GPIO_25_PU_LEN) - 1) << GLB_REG_GPIO_25_PU_POS)) + (~(((1 << GLB_REG_GPIO_25_PU_LEN) - 1) << GLB_REG_GPIO_25_PU_POS)) #define GLB_REG_GPIO_25_PD GLB_REG_GPIO_25_PD -#define GLB_REG_GPIO_25_PD_POS (21U) -#define GLB_REG_GPIO_25_PD_LEN (1U) +#define GLB_REG_GPIO_25_PD_POS (21) +#define GLB_REG_GPIO_25_PD_LEN (1) #define GLB_REG_GPIO_25_PD_MSK \ - (((1U << GLB_REG_GPIO_25_PD_LEN) - 1) << GLB_REG_GPIO_25_PD_POS) + (((1 << GLB_REG_GPIO_25_PD_LEN) - 1) << GLB_REG_GPIO_25_PD_POS) #define GLB_REG_GPIO_25_PD_UMSK \ - (~(((1U << GLB_REG_GPIO_25_PD_LEN) - 1) << GLB_REG_GPIO_25_PD_POS)) + (~(((1 << GLB_REG_GPIO_25_PD_LEN) - 1) << GLB_REG_GPIO_25_PD_POS)) /* 0x134 : GPIO_CFGCTL13 */ #define GLB_GPIO_CFGCTL13_OFFSET (0x134) #define GLB_REG_GPIO_26_IE GLB_REG_GPIO_26_IE -#define GLB_REG_GPIO_26_IE_POS (0U) -#define GLB_REG_GPIO_26_IE_LEN (1U) +#define GLB_REG_GPIO_26_IE_POS (0) +#define GLB_REG_GPIO_26_IE_LEN (1) #define GLB_REG_GPIO_26_IE_MSK \ - (((1U << GLB_REG_GPIO_26_IE_LEN) - 1) << GLB_REG_GPIO_26_IE_POS) + (((1 << GLB_REG_GPIO_26_IE_LEN) - 1) << GLB_REG_GPIO_26_IE_POS) #define GLB_REG_GPIO_26_IE_UMSK \ - (~(((1U << GLB_REG_GPIO_26_IE_LEN) - 1) << GLB_REG_GPIO_26_IE_POS)) + (~(((1 << GLB_REG_GPIO_26_IE_LEN) - 1) << GLB_REG_GPIO_26_IE_POS)) #define GLB_REG_GPIO_26_SMT GLB_REG_GPIO_26_SMT -#define GLB_REG_GPIO_26_SMT_POS (1U) -#define GLB_REG_GPIO_26_SMT_LEN (1U) +#define GLB_REG_GPIO_26_SMT_POS (1) +#define GLB_REG_GPIO_26_SMT_LEN (1) #define GLB_REG_GPIO_26_SMT_MSK \ - (((1U << GLB_REG_GPIO_26_SMT_LEN) - 1) << GLB_REG_GPIO_26_SMT_POS) + (((1 << GLB_REG_GPIO_26_SMT_LEN) - 1) << GLB_REG_GPIO_26_SMT_POS) #define GLB_REG_GPIO_26_SMT_UMSK \ - (~(((1U << GLB_REG_GPIO_26_SMT_LEN) - 1) << GLB_REG_GPIO_26_SMT_POS)) + (~(((1 << GLB_REG_GPIO_26_SMT_LEN) - 1) << GLB_REG_GPIO_26_SMT_POS)) #define GLB_REG_GPIO_26_DRV GLB_REG_GPIO_26_DRV -#define GLB_REG_GPIO_26_DRV_POS (2U) -#define GLB_REG_GPIO_26_DRV_LEN (2U) +#define GLB_REG_GPIO_26_DRV_POS (2) +#define GLB_REG_GPIO_26_DRV_LEN (2) #define GLB_REG_GPIO_26_DRV_MSK \ - (((1U << GLB_REG_GPIO_26_DRV_LEN) - 1) << GLB_REG_GPIO_26_DRV_POS) + (((1 << GLB_REG_GPIO_26_DRV_LEN) - 1) << GLB_REG_GPIO_26_DRV_POS) #define GLB_REG_GPIO_26_DRV_UMSK \ - (~(((1U << GLB_REG_GPIO_26_DRV_LEN) - 1) << GLB_REG_GPIO_26_DRV_POS)) + (~(((1 << GLB_REG_GPIO_26_DRV_LEN) - 1) << GLB_REG_GPIO_26_DRV_POS)) #define GLB_REG_GPIO_26_PU GLB_REG_GPIO_26_PU -#define GLB_REG_GPIO_26_PU_POS (4U) -#define GLB_REG_GPIO_26_PU_LEN (1U) +#define GLB_REG_GPIO_26_PU_POS (4) +#define GLB_REG_GPIO_26_PU_LEN (1) #define GLB_REG_GPIO_26_PU_MSK \ - (((1U << GLB_REG_GPIO_26_PU_LEN) - 1) << GLB_REG_GPIO_26_PU_POS) + (((1 << GLB_REG_GPIO_26_PU_LEN) - 1) << GLB_REG_GPIO_26_PU_POS) #define GLB_REG_GPIO_26_PU_UMSK \ - (~(((1U << GLB_REG_GPIO_26_PU_LEN) - 1) << GLB_REG_GPIO_26_PU_POS)) + (~(((1 << GLB_REG_GPIO_26_PU_LEN) - 1) << GLB_REG_GPIO_26_PU_POS)) #define GLB_REG_GPIO_26_PD GLB_REG_GPIO_26_PD -#define GLB_REG_GPIO_26_PD_POS (5U) -#define GLB_REG_GPIO_26_PD_LEN (1U) +#define GLB_REG_GPIO_26_PD_POS (5) +#define GLB_REG_GPIO_26_PD_LEN (1) #define GLB_REG_GPIO_26_PD_MSK \ - (((1U << GLB_REG_GPIO_26_PD_LEN) - 1) << GLB_REG_GPIO_26_PD_POS) + (((1 << GLB_REG_GPIO_26_PD_LEN) - 1) << GLB_REG_GPIO_26_PD_POS) #define GLB_REG_GPIO_26_PD_UMSK \ - (~(((1U << GLB_REG_GPIO_26_PD_LEN) - 1) << GLB_REG_GPIO_26_PD_POS)) + (~(((1 << GLB_REG_GPIO_26_PD_LEN) - 1) << GLB_REG_GPIO_26_PD_POS)) #define GLB_REG_GPIO_27_IE GLB_REG_GPIO_27_IE -#define GLB_REG_GPIO_27_IE_POS (16U) -#define GLB_REG_GPIO_27_IE_LEN (1U) +#define GLB_REG_GPIO_27_IE_POS (16) +#define GLB_REG_GPIO_27_IE_LEN (1) #define GLB_REG_GPIO_27_IE_MSK \ - (((1U << GLB_REG_GPIO_27_IE_LEN) - 1) << GLB_REG_GPIO_27_IE_POS) + (((1 << GLB_REG_GPIO_27_IE_LEN) - 1) << GLB_REG_GPIO_27_IE_POS) #define GLB_REG_GPIO_27_IE_UMSK \ - (~(((1U << GLB_REG_GPIO_27_IE_LEN) - 1) << GLB_REG_GPIO_27_IE_POS)) + (~(((1 << GLB_REG_GPIO_27_IE_LEN) - 1) << GLB_REG_GPIO_27_IE_POS)) #define GLB_REG_GPIO_27_SMT GLB_REG_GPIO_27_SMT -#define GLB_REG_GPIO_27_SMT_POS (17U) -#define GLB_REG_GPIO_27_SMT_LEN (1U) +#define GLB_REG_GPIO_27_SMT_POS (17) +#define GLB_REG_GPIO_27_SMT_LEN (1) #define GLB_REG_GPIO_27_SMT_MSK \ - (((1U << GLB_REG_GPIO_27_SMT_LEN) - 1) << GLB_REG_GPIO_27_SMT_POS) + (((1 << GLB_REG_GPIO_27_SMT_LEN) - 1) << GLB_REG_GPIO_27_SMT_POS) #define GLB_REG_GPIO_27_SMT_UMSK \ - (~(((1U << GLB_REG_GPIO_27_SMT_LEN) - 1) << GLB_REG_GPIO_27_SMT_POS)) + (~(((1 << GLB_REG_GPIO_27_SMT_LEN) - 1) << GLB_REG_GPIO_27_SMT_POS)) #define GLB_REG_GPIO_27_DRV GLB_REG_GPIO_27_DRV -#define GLB_REG_GPIO_27_DRV_POS (18U) -#define GLB_REG_GPIO_27_DRV_LEN (2U) +#define GLB_REG_GPIO_27_DRV_POS (18) +#define GLB_REG_GPIO_27_DRV_LEN (2) #define GLB_REG_GPIO_27_DRV_MSK \ - (((1U << GLB_REG_GPIO_27_DRV_LEN) - 1) << GLB_REG_GPIO_27_DRV_POS) + (((1 << GLB_REG_GPIO_27_DRV_LEN) - 1) << GLB_REG_GPIO_27_DRV_POS) #define GLB_REG_GPIO_27_DRV_UMSK \ - (~(((1U << GLB_REG_GPIO_27_DRV_LEN) - 1) << GLB_REG_GPIO_27_DRV_POS)) + (~(((1 << GLB_REG_GPIO_27_DRV_LEN) - 1) << GLB_REG_GPIO_27_DRV_POS)) #define GLB_REG_GPIO_27_PU GLB_REG_GPIO_27_PU -#define GLB_REG_GPIO_27_PU_POS (20U) -#define GLB_REG_GPIO_27_PU_LEN (1U) +#define GLB_REG_GPIO_27_PU_POS (20) +#define GLB_REG_GPIO_27_PU_LEN (1) #define GLB_REG_GPIO_27_PU_MSK \ - (((1U << GLB_REG_GPIO_27_PU_LEN) - 1) << GLB_REG_GPIO_27_PU_POS) + (((1 << GLB_REG_GPIO_27_PU_LEN) - 1) << GLB_REG_GPIO_27_PU_POS) #define GLB_REG_GPIO_27_PU_UMSK \ - (~(((1U << GLB_REG_GPIO_27_PU_LEN) - 1) << GLB_REG_GPIO_27_PU_POS)) + (~(((1 << GLB_REG_GPIO_27_PU_LEN) - 1) << GLB_REG_GPIO_27_PU_POS)) #define GLB_REG_GPIO_27_PD GLB_REG_GPIO_27_PD -#define GLB_REG_GPIO_27_PD_POS (21U) -#define GLB_REG_GPIO_27_PD_LEN (1U) +#define GLB_REG_GPIO_27_PD_POS (21) +#define GLB_REG_GPIO_27_PD_LEN (1) #define GLB_REG_GPIO_27_PD_MSK \ - (((1U << GLB_REG_GPIO_27_PD_LEN) - 1) << GLB_REG_GPIO_27_PD_POS) + (((1 << GLB_REG_GPIO_27_PD_LEN) - 1) << GLB_REG_GPIO_27_PD_POS) #define GLB_REG_GPIO_27_PD_UMSK \ - (~(((1U << GLB_REG_GPIO_27_PD_LEN) - 1) << GLB_REG_GPIO_27_PD_POS)) + (~(((1 << GLB_REG_GPIO_27_PD_LEN) - 1) << GLB_REG_GPIO_27_PD_POS)) /* 0x138 : GPIO_CFGCTL14 */ #define GLB_GPIO_CFGCTL14_OFFSET (0x138) #define GLB_REG_GPIO_28_IE GLB_REG_GPIO_28_IE -#define GLB_REG_GPIO_28_IE_POS (0U) -#define GLB_REG_GPIO_28_IE_LEN (1U) +#define GLB_REG_GPIO_28_IE_POS (0) +#define GLB_REG_GPIO_28_IE_LEN (1) #define GLB_REG_GPIO_28_IE_MSK \ - (((1U << GLB_REG_GPIO_28_IE_LEN) - 1) << GLB_REG_GPIO_28_IE_POS) + (((1 << GLB_REG_GPIO_28_IE_LEN) - 1) << GLB_REG_GPIO_28_IE_POS) #define GLB_REG_GPIO_28_IE_UMSK \ - (~(((1U << GLB_REG_GPIO_28_IE_LEN) - 1) << GLB_REG_GPIO_28_IE_POS)) + (~(((1 << GLB_REG_GPIO_28_IE_LEN) - 1) << GLB_REG_GPIO_28_IE_POS)) #define GLB_REG_GPIO_28_SMT GLB_REG_GPIO_28_SMT -#define GLB_REG_GPIO_28_SMT_POS (1U) -#define GLB_REG_GPIO_28_SMT_LEN (1U) +#define GLB_REG_GPIO_28_SMT_POS (1) +#define GLB_REG_GPIO_28_SMT_LEN (1) #define GLB_REG_GPIO_28_SMT_MSK \ - (((1U << GLB_REG_GPIO_28_SMT_LEN) - 1) << GLB_REG_GPIO_28_SMT_POS) + (((1 << GLB_REG_GPIO_28_SMT_LEN) - 1) << GLB_REG_GPIO_28_SMT_POS) #define GLB_REG_GPIO_28_SMT_UMSK \ - (~(((1U << GLB_REG_GPIO_28_SMT_LEN) - 1) << GLB_REG_GPIO_28_SMT_POS)) + (~(((1 << GLB_REG_GPIO_28_SMT_LEN) - 1) << GLB_REG_GPIO_28_SMT_POS)) #define GLB_REG_GPIO_28_DRV GLB_REG_GPIO_28_DRV -#define GLB_REG_GPIO_28_DRV_POS (2U) -#define GLB_REG_GPIO_28_DRV_LEN (2U) +#define GLB_REG_GPIO_28_DRV_POS (2) +#define GLB_REG_GPIO_28_DRV_LEN (2) #define GLB_REG_GPIO_28_DRV_MSK \ - (((1U << GLB_REG_GPIO_28_DRV_LEN) - 1) << GLB_REG_GPIO_28_DRV_POS) + (((1 << GLB_REG_GPIO_28_DRV_LEN) - 1) << GLB_REG_GPIO_28_DRV_POS) #define GLB_REG_GPIO_28_DRV_UMSK \ - (~(((1U << GLB_REG_GPIO_28_DRV_LEN) - 1) << GLB_REG_GPIO_28_DRV_POS)) + (~(((1 << GLB_REG_GPIO_28_DRV_LEN) - 1) << GLB_REG_GPIO_28_DRV_POS)) #define GLB_REG_GPIO_28_PU GLB_REG_GPIO_28_PU -#define GLB_REG_GPIO_28_PU_POS (4U) -#define GLB_REG_GPIO_28_PU_LEN (1U) +#define GLB_REG_GPIO_28_PU_POS (4) +#define GLB_REG_GPIO_28_PU_LEN (1) #define GLB_REG_GPIO_28_PU_MSK \ - (((1U << GLB_REG_GPIO_28_PU_LEN) - 1) << GLB_REG_GPIO_28_PU_POS) + (((1 << GLB_REG_GPIO_28_PU_LEN) - 1) << GLB_REG_GPIO_28_PU_POS) #define GLB_REG_GPIO_28_PU_UMSK \ - (~(((1U << GLB_REG_GPIO_28_PU_LEN) - 1) << GLB_REG_GPIO_28_PU_POS)) + (~(((1 << GLB_REG_GPIO_28_PU_LEN) - 1) << GLB_REG_GPIO_28_PU_POS)) #define GLB_REG_GPIO_28_PD GLB_REG_GPIO_28_PD -#define GLB_REG_GPIO_28_PD_POS (5U) -#define GLB_REG_GPIO_28_PD_LEN (1U) +#define GLB_REG_GPIO_28_PD_POS (5) +#define GLB_REG_GPIO_28_PD_LEN (1) #define GLB_REG_GPIO_28_PD_MSK \ - (((1U << GLB_REG_GPIO_28_PD_LEN) - 1) << GLB_REG_GPIO_28_PD_POS) + (((1 << GLB_REG_GPIO_28_PD_LEN) - 1) << GLB_REG_GPIO_28_PD_POS) #define GLB_REG_GPIO_28_PD_UMSK \ - (~(((1U << GLB_REG_GPIO_28_PD_LEN) - 1) << GLB_REG_GPIO_28_PD_POS)) + (~(((1 << GLB_REG_GPIO_28_PD_LEN) - 1) << GLB_REG_GPIO_28_PD_POS)) /* 0x180 : GPIO_CFGCTL30 */ #define GLB_GPIO_CFGCTL30_OFFSET (0x180) #define GLB_REG_GPIO_0_I GLB_REG_GPIO_0_I -#define GLB_REG_GPIO_0_I_POS (0U) -#define GLB_REG_GPIO_0_I_LEN (1U) +#define GLB_REG_GPIO_0_I_POS (0) +#define GLB_REG_GPIO_0_I_LEN (1) #define GLB_REG_GPIO_0_I_MSK \ - (((1U << GLB_REG_GPIO_0_I_LEN) - 1) << GLB_REG_GPIO_0_I_POS) + (((1 << GLB_REG_GPIO_0_I_LEN) - 1) << GLB_REG_GPIO_0_I_POS) #define GLB_REG_GPIO_0_I_UMSK \ - (~(((1U << GLB_REG_GPIO_0_I_LEN) - 1) << GLB_REG_GPIO_0_I_POS)) + (~(((1 << GLB_REG_GPIO_0_I_LEN) - 1) << GLB_REG_GPIO_0_I_POS)) #define GLB_REG_GPIO_1_I GLB_REG_GPIO_1_I -#define GLB_REG_GPIO_1_I_POS (1U) -#define GLB_REG_GPIO_1_I_LEN (1U) +#define GLB_REG_GPIO_1_I_POS (1) +#define GLB_REG_GPIO_1_I_LEN (1) #define GLB_REG_GPIO_1_I_MSK \ - (((1U << GLB_REG_GPIO_1_I_LEN) - 1) << GLB_REG_GPIO_1_I_POS) + (((1 << GLB_REG_GPIO_1_I_LEN) - 1) << GLB_REG_GPIO_1_I_POS) #define GLB_REG_GPIO_1_I_UMSK \ - (~(((1U << GLB_REG_GPIO_1_I_LEN) - 1) << GLB_REG_GPIO_1_I_POS)) + (~(((1 << GLB_REG_GPIO_1_I_LEN) - 1) << GLB_REG_GPIO_1_I_POS)) #define GLB_REG_GPIO_2_I GLB_REG_GPIO_2_I -#define GLB_REG_GPIO_2_I_POS (2U) -#define GLB_REG_GPIO_2_I_LEN (1U) +#define GLB_REG_GPIO_2_I_POS (2) +#define GLB_REG_GPIO_2_I_LEN (1) #define GLB_REG_GPIO_2_I_MSK \ - (((1U << GLB_REG_GPIO_2_I_LEN) - 1) << GLB_REG_GPIO_2_I_POS) + (((1 << GLB_REG_GPIO_2_I_LEN) - 1) << GLB_REG_GPIO_2_I_POS) #define GLB_REG_GPIO_2_I_UMSK \ - (~(((1U << GLB_REG_GPIO_2_I_LEN) - 1) << GLB_REG_GPIO_2_I_POS)) + (~(((1 << GLB_REG_GPIO_2_I_LEN) - 1) << GLB_REG_GPIO_2_I_POS)) #define GLB_REG_GPIO_3_I GLB_REG_GPIO_3_I -#define GLB_REG_GPIO_3_I_POS (3U) -#define GLB_REG_GPIO_3_I_LEN (1U) +#define GLB_REG_GPIO_3_I_POS (3) +#define GLB_REG_GPIO_3_I_LEN (1) #define GLB_REG_GPIO_3_I_MSK \ - (((1U << GLB_REG_GPIO_3_I_LEN) - 1) << GLB_REG_GPIO_3_I_POS) + (((1 << GLB_REG_GPIO_3_I_LEN) - 1) << GLB_REG_GPIO_3_I_POS) #define GLB_REG_GPIO_3_I_UMSK \ - (~(((1U << GLB_REG_GPIO_3_I_LEN) - 1) << GLB_REG_GPIO_3_I_POS)) + (~(((1 << GLB_REG_GPIO_3_I_LEN) - 1) << GLB_REG_GPIO_3_I_POS)) #define GLB_REG_GPIO_4_I GLB_REG_GPIO_4_I -#define GLB_REG_GPIO_4_I_POS (4U) -#define GLB_REG_GPIO_4_I_LEN (1U) +#define GLB_REG_GPIO_4_I_POS (4) +#define GLB_REG_GPIO_4_I_LEN (1) #define GLB_REG_GPIO_4_I_MSK \ - (((1U << GLB_REG_GPIO_4_I_LEN) - 1) << GLB_REG_GPIO_4_I_POS) + (((1 << GLB_REG_GPIO_4_I_LEN) - 1) << GLB_REG_GPIO_4_I_POS) #define GLB_REG_GPIO_4_I_UMSK \ - (~(((1U << GLB_REG_GPIO_4_I_LEN) - 1) << GLB_REG_GPIO_4_I_POS)) + (~(((1 << GLB_REG_GPIO_4_I_LEN) - 1) << GLB_REG_GPIO_4_I_POS)) #define GLB_REG_GPIO_5_I GLB_REG_GPIO_5_I -#define GLB_REG_GPIO_5_I_POS (5U) -#define GLB_REG_GPIO_5_I_LEN (1U) +#define GLB_REG_GPIO_5_I_POS (5) +#define GLB_REG_GPIO_5_I_LEN (1) #define GLB_REG_GPIO_5_I_MSK \ - (((1U << GLB_REG_GPIO_5_I_LEN) - 1) << GLB_REG_GPIO_5_I_POS) + (((1 << GLB_REG_GPIO_5_I_LEN) - 1) << GLB_REG_GPIO_5_I_POS) #define GLB_REG_GPIO_5_I_UMSK \ - (~(((1U << GLB_REG_GPIO_5_I_LEN) - 1) << GLB_REG_GPIO_5_I_POS)) + (~(((1 << GLB_REG_GPIO_5_I_LEN) - 1) << GLB_REG_GPIO_5_I_POS)) #define GLB_REG_GPIO_6_I GLB_REG_GPIO_6_I -#define GLB_REG_GPIO_6_I_POS (6U) -#define GLB_REG_GPIO_6_I_LEN (1U) +#define GLB_REG_GPIO_6_I_POS (6) +#define GLB_REG_GPIO_6_I_LEN (1) #define GLB_REG_GPIO_6_I_MSK \ - (((1U << GLB_REG_GPIO_6_I_LEN) - 1) << GLB_REG_GPIO_6_I_POS) + (((1 << GLB_REG_GPIO_6_I_LEN) - 1) << GLB_REG_GPIO_6_I_POS) #define GLB_REG_GPIO_6_I_UMSK \ - (~(((1U << GLB_REG_GPIO_6_I_LEN) - 1) << GLB_REG_GPIO_6_I_POS)) + (~(((1 << GLB_REG_GPIO_6_I_LEN) - 1) << GLB_REG_GPIO_6_I_POS)) #define GLB_REG_GPIO_7_I GLB_REG_GPIO_7_I -#define GLB_REG_GPIO_7_I_POS (7U) -#define GLB_REG_GPIO_7_I_LEN (1U) +#define GLB_REG_GPIO_7_I_POS (7) +#define GLB_REG_GPIO_7_I_LEN (1) #define GLB_REG_GPIO_7_I_MSK \ - (((1U << GLB_REG_GPIO_7_I_LEN) - 1) << GLB_REG_GPIO_7_I_POS) + (((1 << GLB_REG_GPIO_7_I_LEN) - 1) << GLB_REG_GPIO_7_I_POS) #define GLB_REG_GPIO_7_I_UMSK \ - (~(((1U << GLB_REG_GPIO_7_I_LEN) - 1) << GLB_REG_GPIO_7_I_POS)) + (~(((1 << GLB_REG_GPIO_7_I_LEN) - 1) << GLB_REG_GPIO_7_I_POS)) #define GLB_REG_GPIO_8_I GLB_REG_GPIO_8_I -#define GLB_REG_GPIO_8_I_POS (8U) -#define GLB_REG_GPIO_8_I_LEN (1U) +#define GLB_REG_GPIO_8_I_POS (8) +#define GLB_REG_GPIO_8_I_LEN (1) #define GLB_REG_GPIO_8_I_MSK \ - (((1U << GLB_REG_GPIO_8_I_LEN) - 1) << GLB_REG_GPIO_8_I_POS) + (((1 << GLB_REG_GPIO_8_I_LEN) - 1) << GLB_REG_GPIO_8_I_POS) #define GLB_REG_GPIO_8_I_UMSK \ - (~(((1U << GLB_REG_GPIO_8_I_LEN) - 1) << GLB_REG_GPIO_8_I_POS)) + (~(((1 << GLB_REG_GPIO_8_I_LEN) - 1) << GLB_REG_GPIO_8_I_POS)) #define GLB_REG_GPIO_9_I GLB_REG_GPIO_9_I -#define GLB_REG_GPIO_9_I_POS (9U) -#define GLB_REG_GPIO_9_I_LEN (1U) +#define GLB_REG_GPIO_9_I_POS (9) +#define GLB_REG_GPIO_9_I_LEN (1) #define GLB_REG_GPIO_9_I_MSK \ - (((1U << GLB_REG_GPIO_9_I_LEN) - 1) << GLB_REG_GPIO_9_I_POS) + (((1 << GLB_REG_GPIO_9_I_LEN) - 1) << GLB_REG_GPIO_9_I_POS) #define GLB_REG_GPIO_9_I_UMSK \ - (~(((1U << GLB_REG_GPIO_9_I_LEN) - 1) << GLB_REG_GPIO_9_I_POS)) + (~(((1 << GLB_REG_GPIO_9_I_LEN) - 1) << GLB_REG_GPIO_9_I_POS)) #define GLB_REG_GPIO_10_I GLB_REG_GPIO_10_I -#define GLB_REG_GPIO_10_I_POS (10U) -#define GLB_REG_GPIO_10_I_LEN (1U) +#define GLB_REG_GPIO_10_I_POS (10) +#define GLB_REG_GPIO_10_I_LEN (1) #define GLB_REG_GPIO_10_I_MSK \ - (((1U << GLB_REG_GPIO_10_I_LEN) - 1) << GLB_REG_GPIO_10_I_POS) + (((1 << GLB_REG_GPIO_10_I_LEN) - 1) << GLB_REG_GPIO_10_I_POS) #define GLB_REG_GPIO_10_I_UMSK \ - (~(((1U << GLB_REG_GPIO_10_I_LEN) - 1) << GLB_REG_GPIO_10_I_POS)) + (~(((1 << GLB_REG_GPIO_10_I_LEN) - 1) << GLB_REG_GPIO_10_I_POS)) #define GLB_REG_GPIO_11_I GLB_REG_GPIO_11_I -#define GLB_REG_GPIO_11_I_POS (11U) -#define GLB_REG_GPIO_11_I_LEN (1U) +#define GLB_REG_GPIO_11_I_POS (11) +#define GLB_REG_GPIO_11_I_LEN (1) #define GLB_REG_GPIO_11_I_MSK \ - (((1U << GLB_REG_GPIO_11_I_LEN) - 1) << GLB_REG_GPIO_11_I_POS) + (((1 << GLB_REG_GPIO_11_I_LEN) - 1) << GLB_REG_GPIO_11_I_POS) #define GLB_REG_GPIO_11_I_UMSK \ - (~(((1U << GLB_REG_GPIO_11_I_LEN) - 1) << GLB_REG_GPIO_11_I_POS)) + (~(((1 << GLB_REG_GPIO_11_I_LEN) - 1) << GLB_REG_GPIO_11_I_POS)) #define GLB_REG_GPIO_12_I GLB_REG_GPIO_12_I -#define GLB_REG_GPIO_12_I_POS (12U) -#define GLB_REG_GPIO_12_I_LEN (1U) +#define GLB_REG_GPIO_12_I_POS (12) +#define GLB_REG_GPIO_12_I_LEN (1) #define GLB_REG_GPIO_12_I_MSK \ - (((1U << GLB_REG_GPIO_12_I_LEN) - 1) << GLB_REG_GPIO_12_I_POS) + (((1 << GLB_REG_GPIO_12_I_LEN) - 1) << GLB_REG_GPIO_12_I_POS) #define GLB_REG_GPIO_12_I_UMSK \ - (~(((1U << GLB_REG_GPIO_12_I_LEN) - 1) << GLB_REG_GPIO_12_I_POS)) + (~(((1 << GLB_REG_GPIO_12_I_LEN) - 1) << GLB_REG_GPIO_12_I_POS)) #define GLB_REG_GPIO_13_I GLB_REG_GPIO_13_I -#define GLB_REG_GPIO_13_I_POS (13U) -#define GLB_REG_GPIO_13_I_LEN (1U) +#define GLB_REG_GPIO_13_I_POS (13) +#define GLB_REG_GPIO_13_I_LEN (1) #define GLB_REG_GPIO_13_I_MSK \ - (((1U << GLB_REG_GPIO_13_I_LEN) - 1) << GLB_REG_GPIO_13_I_POS) + (((1 << GLB_REG_GPIO_13_I_LEN) - 1) << GLB_REG_GPIO_13_I_POS) #define GLB_REG_GPIO_13_I_UMSK \ - (~(((1U << GLB_REG_GPIO_13_I_LEN) - 1) << GLB_REG_GPIO_13_I_POS)) + (~(((1 << GLB_REG_GPIO_13_I_LEN) - 1) << GLB_REG_GPIO_13_I_POS)) #define GLB_REG_GPIO_14_I GLB_REG_GPIO_14_I -#define GLB_REG_GPIO_14_I_POS (14U) -#define GLB_REG_GPIO_14_I_LEN (1U) +#define GLB_REG_GPIO_14_I_POS (14) +#define GLB_REG_GPIO_14_I_LEN (1) #define GLB_REG_GPIO_14_I_MSK \ - (((1U << GLB_REG_GPIO_14_I_LEN) - 1) << GLB_REG_GPIO_14_I_POS) + (((1 << GLB_REG_GPIO_14_I_LEN) - 1) << GLB_REG_GPIO_14_I_POS) #define GLB_REG_GPIO_14_I_UMSK \ - (~(((1U << GLB_REG_GPIO_14_I_LEN) - 1) << GLB_REG_GPIO_14_I_POS)) + (~(((1 << GLB_REG_GPIO_14_I_LEN) - 1) << GLB_REG_GPIO_14_I_POS)) #define GLB_REG_GPIO_15_I GLB_REG_GPIO_15_I -#define GLB_REG_GPIO_15_I_POS (15U) -#define GLB_REG_GPIO_15_I_LEN (1U) +#define GLB_REG_GPIO_15_I_POS (15) +#define GLB_REG_GPIO_15_I_LEN (1) #define GLB_REG_GPIO_15_I_MSK \ - (((1U << GLB_REG_GPIO_15_I_LEN) - 1) << GLB_REG_GPIO_15_I_POS) + (((1 << GLB_REG_GPIO_15_I_LEN) - 1) << GLB_REG_GPIO_15_I_POS) #define GLB_REG_GPIO_15_I_UMSK \ - (~(((1U << GLB_REG_GPIO_15_I_LEN) - 1) << GLB_REG_GPIO_15_I_POS)) + (~(((1 << GLB_REG_GPIO_15_I_LEN) - 1) << GLB_REG_GPIO_15_I_POS)) #define GLB_REG_GPIO_16_I GLB_REG_GPIO_16_I -#define GLB_REG_GPIO_16_I_POS (16U) -#define GLB_REG_GPIO_16_I_LEN (1U) +#define GLB_REG_GPIO_16_I_POS (16) +#define GLB_REG_GPIO_16_I_LEN (1) #define GLB_REG_GPIO_16_I_MSK \ - (((1U << GLB_REG_GPIO_16_I_LEN) - 1) << GLB_REG_GPIO_16_I_POS) + (((1 << GLB_REG_GPIO_16_I_LEN) - 1) << GLB_REG_GPIO_16_I_POS) #define GLB_REG_GPIO_16_I_UMSK \ - (~(((1U << GLB_REG_GPIO_16_I_LEN) - 1) << GLB_REG_GPIO_16_I_POS)) + (~(((1 << GLB_REG_GPIO_16_I_LEN) - 1) << GLB_REG_GPIO_16_I_POS)) #define GLB_REG_GPIO_17_I GLB_REG_GPIO_17_I -#define GLB_REG_GPIO_17_I_POS (17U) -#define GLB_REG_GPIO_17_I_LEN (1U) +#define GLB_REG_GPIO_17_I_POS (17) +#define GLB_REG_GPIO_17_I_LEN (1) #define GLB_REG_GPIO_17_I_MSK \ - (((1U << GLB_REG_GPIO_17_I_LEN) - 1) << GLB_REG_GPIO_17_I_POS) + (((1 << GLB_REG_GPIO_17_I_LEN) - 1) << GLB_REG_GPIO_17_I_POS) #define GLB_REG_GPIO_17_I_UMSK \ - (~(((1U << GLB_REG_GPIO_17_I_LEN) - 1) << GLB_REG_GPIO_17_I_POS)) + (~(((1 << GLB_REG_GPIO_17_I_LEN) - 1) << GLB_REG_GPIO_17_I_POS)) #define GLB_REG_GPIO_18_I GLB_REG_GPIO_18_I -#define GLB_REG_GPIO_18_I_POS (18U) -#define GLB_REG_GPIO_18_I_LEN (1U) +#define GLB_REG_GPIO_18_I_POS (18) +#define GLB_REG_GPIO_18_I_LEN (1) #define GLB_REG_GPIO_18_I_MSK \ - (((1U << GLB_REG_GPIO_18_I_LEN) - 1) << GLB_REG_GPIO_18_I_POS) + (((1 << GLB_REG_GPIO_18_I_LEN) - 1) << GLB_REG_GPIO_18_I_POS) #define GLB_REG_GPIO_18_I_UMSK \ - (~(((1U << GLB_REG_GPIO_18_I_LEN) - 1) << GLB_REG_GPIO_18_I_POS)) + (~(((1 << GLB_REG_GPIO_18_I_LEN) - 1) << GLB_REG_GPIO_18_I_POS)) #define GLB_REG_GPIO_19_I GLB_REG_GPIO_19_I -#define GLB_REG_GPIO_19_I_POS (19U) -#define GLB_REG_GPIO_19_I_LEN (1U) +#define GLB_REG_GPIO_19_I_POS (19) +#define GLB_REG_GPIO_19_I_LEN (1) #define GLB_REG_GPIO_19_I_MSK \ - (((1U << GLB_REG_GPIO_19_I_LEN) - 1) << GLB_REG_GPIO_19_I_POS) + (((1 << GLB_REG_GPIO_19_I_LEN) - 1) << GLB_REG_GPIO_19_I_POS) #define GLB_REG_GPIO_19_I_UMSK \ - (~(((1U << GLB_REG_GPIO_19_I_LEN) - 1) << GLB_REG_GPIO_19_I_POS)) + (~(((1 << GLB_REG_GPIO_19_I_LEN) - 1) << GLB_REG_GPIO_19_I_POS)) #define GLB_REG_GPIO_20_I GLB_REG_GPIO_20_I -#define GLB_REG_GPIO_20_I_POS (20U) -#define GLB_REG_GPIO_20_I_LEN (1U) +#define GLB_REG_GPIO_20_I_POS (20) +#define GLB_REG_GPIO_20_I_LEN (1) #define GLB_REG_GPIO_20_I_MSK \ - (((1U << GLB_REG_GPIO_20_I_LEN) - 1) << GLB_REG_GPIO_20_I_POS) + (((1 << GLB_REG_GPIO_20_I_LEN) - 1) << GLB_REG_GPIO_20_I_POS) #define GLB_REG_GPIO_20_I_UMSK \ - (~(((1U << GLB_REG_GPIO_20_I_LEN) - 1) << GLB_REG_GPIO_20_I_POS)) + (~(((1 << GLB_REG_GPIO_20_I_LEN) - 1) << GLB_REG_GPIO_20_I_POS)) #define GLB_REG_GPIO_21_I GLB_REG_GPIO_21_I -#define GLB_REG_GPIO_21_I_POS (21U) -#define GLB_REG_GPIO_21_I_LEN (1U) +#define GLB_REG_GPIO_21_I_POS (21) +#define GLB_REG_GPIO_21_I_LEN (1) #define GLB_REG_GPIO_21_I_MSK \ - (((1U << GLB_REG_GPIO_21_I_LEN) - 1) << GLB_REG_GPIO_21_I_POS) + (((1 << GLB_REG_GPIO_21_I_LEN) - 1) << GLB_REG_GPIO_21_I_POS) #define GLB_REG_GPIO_21_I_UMSK \ - (~(((1U << GLB_REG_GPIO_21_I_LEN) - 1) << GLB_REG_GPIO_21_I_POS)) + (~(((1 << GLB_REG_GPIO_21_I_LEN) - 1) << GLB_REG_GPIO_21_I_POS)) #define GLB_REG_GPIO_22_I GLB_REG_GPIO_22_I -#define GLB_REG_GPIO_22_I_POS (22U) -#define GLB_REG_GPIO_22_I_LEN (1U) +#define GLB_REG_GPIO_22_I_POS (22) +#define GLB_REG_GPIO_22_I_LEN (1) #define GLB_REG_GPIO_22_I_MSK \ - (((1U << GLB_REG_GPIO_22_I_LEN) - 1) << GLB_REG_GPIO_22_I_POS) + (((1 << GLB_REG_GPIO_22_I_LEN) - 1) << GLB_REG_GPIO_22_I_POS) #define GLB_REG_GPIO_22_I_UMSK \ - (~(((1U << GLB_REG_GPIO_22_I_LEN) - 1) << GLB_REG_GPIO_22_I_POS)) + (~(((1 << GLB_REG_GPIO_22_I_LEN) - 1) << GLB_REG_GPIO_22_I_POS)) /* 0x184 : GPIO_CFGCTL31 */ @@ -2714,166 +2705,166 @@ #define GLB_GPIO_CFGCTL32_OFFSET (0x188) #define GLB_REG_GPIO_0_O GLB_REG_GPIO_0_O -#define GLB_REG_GPIO_0_O_POS (0U) -#define GLB_REG_GPIO_0_O_LEN (1U) +#define GLB_REG_GPIO_0_O_POS (0) +#define GLB_REG_GPIO_0_O_LEN (1) #define GLB_REG_GPIO_0_O_MSK \ - (((1U << GLB_REG_GPIO_0_O_LEN) - 1) << GLB_REG_GPIO_0_O_POS) + (((1 << GLB_REG_GPIO_0_O_LEN) - 1) << GLB_REG_GPIO_0_O_POS) #define GLB_REG_GPIO_0_O_UMSK \ - (~(((1U << GLB_REG_GPIO_0_O_LEN) - 1) << GLB_REG_GPIO_0_O_POS)) + (~(((1 << GLB_REG_GPIO_0_O_LEN) - 1) << GLB_REG_GPIO_0_O_POS)) #define GLB_REG_GPIO_1_O GLB_REG_GPIO_1_O -#define GLB_REG_GPIO_1_O_POS (1U) -#define GLB_REG_GPIO_1_O_LEN (1U) +#define GLB_REG_GPIO_1_O_POS (1) +#define GLB_REG_GPIO_1_O_LEN (1) #define GLB_REG_GPIO_1_O_MSK \ - (((1U << GLB_REG_GPIO_1_O_LEN) - 1) << GLB_REG_GPIO_1_O_POS) + (((1 << GLB_REG_GPIO_1_O_LEN) - 1) << GLB_REG_GPIO_1_O_POS) #define GLB_REG_GPIO_1_O_UMSK \ - (~(((1U << GLB_REG_GPIO_1_O_LEN) - 1) << GLB_REG_GPIO_1_O_POS)) + (~(((1 << GLB_REG_GPIO_1_O_LEN) - 1) << GLB_REG_GPIO_1_O_POS)) #define GLB_REG_GPIO_2_O GLB_REG_GPIO_2_O -#define GLB_REG_GPIO_2_O_POS (2U) -#define GLB_REG_GPIO_2_O_LEN (1U) +#define GLB_REG_GPIO_2_O_POS (2) +#define GLB_REG_GPIO_2_O_LEN (1) #define GLB_REG_GPIO_2_O_MSK \ - (((1U << GLB_REG_GPIO_2_O_LEN) - 1) << GLB_REG_GPIO_2_O_POS) + (((1 << GLB_REG_GPIO_2_O_LEN) - 1) << GLB_REG_GPIO_2_O_POS) #define GLB_REG_GPIO_2_O_UMSK \ - (~(((1U << GLB_REG_GPIO_2_O_LEN) - 1) << GLB_REG_GPIO_2_O_POS)) + (~(((1 << GLB_REG_GPIO_2_O_LEN) - 1) << GLB_REG_GPIO_2_O_POS)) #define GLB_REG_GPIO_3_O GLB_REG_GPIO_3_O -#define GLB_REG_GPIO_3_O_POS (3U) -#define GLB_REG_GPIO_3_O_LEN (1U) +#define GLB_REG_GPIO_3_O_POS (3) +#define GLB_REG_GPIO_3_O_LEN (1) #define GLB_REG_GPIO_3_O_MSK \ - (((1U << GLB_REG_GPIO_3_O_LEN) - 1) << GLB_REG_GPIO_3_O_POS) + (((1 << GLB_REG_GPIO_3_O_LEN) - 1) << GLB_REG_GPIO_3_O_POS) #define GLB_REG_GPIO_3_O_UMSK \ - (~(((1U << GLB_REG_GPIO_3_O_LEN) - 1) << GLB_REG_GPIO_3_O_POS)) + (~(((1 << GLB_REG_GPIO_3_O_LEN) - 1) << GLB_REG_GPIO_3_O_POS)) #define GLB_REG_GPIO_4_O GLB_REG_GPIO_4_O -#define GLB_REG_GPIO_4_O_POS (4U) -#define GLB_REG_GPIO_4_O_LEN (1U) +#define GLB_REG_GPIO_4_O_POS (4) +#define GLB_REG_GPIO_4_O_LEN (1) #define GLB_REG_GPIO_4_O_MSK \ - (((1U << GLB_REG_GPIO_4_O_LEN) - 1) << GLB_REG_GPIO_4_O_POS) + (((1 << GLB_REG_GPIO_4_O_LEN) - 1) << GLB_REG_GPIO_4_O_POS) #define GLB_REG_GPIO_4_O_UMSK \ - (~(((1U << GLB_REG_GPIO_4_O_LEN) - 1) << GLB_REG_GPIO_4_O_POS)) + (~(((1 << GLB_REG_GPIO_4_O_LEN) - 1) << GLB_REG_GPIO_4_O_POS)) #define GLB_REG_GPIO_5_O GLB_REG_GPIO_5_O -#define GLB_REG_GPIO_5_O_POS (5U) -#define GLB_REG_GPIO_5_O_LEN (1U) +#define GLB_REG_GPIO_5_O_POS (5) +#define GLB_REG_GPIO_5_O_LEN (1) #define GLB_REG_GPIO_5_O_MSK \ - (((1U << GLB_REG_GPIO_5_O_LEN) - 1) << GLB_REG_GPIO_5_O_POS) + (((1 << GLB_REG_GPIO_5_O_LEN) - 1) << GLB_REG_GPIO_5_O_POS) #define GLB_REG_GPIO_5_O_UMSK \ - (~(((1U << GLB_REG_GPIO_5_O_LEN) - 1) << GLB_REG_GPIO_5_O_POS)) + (~(((1 << GLB_REG_GPIO_5_O_LEN) - 1) << GLB_REG_GPIO_5_O_POS)) #define GLB_REG_GPIO_6_O GLB_REG_GPIO_6_O -#define GLB_REG_GPIO_6_O_POS (6U) -#define GLB_REG_GPIO_6_O_LEN (1U) +#define GLB_REG_GPIO_6_O_POS (6) +#define GLB_REG_GPIO_6_O_LEN (1) #define GLB_REG_GPIO_6_O_MSK \ - (((1U << GLB_REG_GPIO_6_O_LEN) - 1) << GLB_REG_GPIO_6_O_POS) + (((1 << GLB_REG_GPIO_6_O_LEN) - 1) << GLB_REG_GPIO_6_O_POS) #define GLB_REG_GPIO_6_O_UMSK \ - (~(((1U << GLB_REG_GPIO_6_O_LEN) - 1) << GLB_REG_GPIO_6_O_POS)) + (~(((1 << GLB_REG_GPIO_6_O_LEN) - 1) << GLB_REG_GPIO_6_O_POS)) #define GLB_REG_GPIO_7_O GLB_REG_GPIO_7_O -#define GLB_REG_GPIO_7_O_POS (7U) -#define GLB_REG_GPIO_7_O_LEN (1U) +#define GLB_REG_GPIO_7_O_POS (7) +#define GLB_REG_GPIO_7_O_LEN (1) #define GLB_REG_GPIO_7_O_MSK \ - (((1U << GLB_REG_GPIO_7_O_LEN) - 1) << GLB_REG_GPIO_7_O_POS) + (((1 << GLB_REG_GPIO_7_O_LEN) - 1) << GLB_REG_GPIO_7_O_POS) #define GLB_REG_GPIO_7_O_UMSK \ - (~(((1U << GLB_REG_GPIO_7_O_LEN) - 1) << GLB_REG_GPIO_7_O_POS)) + (~(((1 << GLB_REG_GPIO_7_O_LEN) - 1) << GLB_REG_GPIO_7_O_POS)) #define GLB_REG_GPIO_8_O GLB_REG_GPIO_8_O -#define GLB_REG_GPIO_8_O_POS (8U) -#define GLB_REG_GPIO_8_O_LEN (1U) +#define GLB_REG_GPIO_8_O_POS (8) +#define GLB_REG_GPIO_8_O_LEN (1) #define GLB_REG_GPIO_8_O_MSK \ - (((1U << GLB_REG_GPIO_8_O_LEN) - 1) << GLB_REG_GPIO_8_O_POS) + (((1 << GLB_REG_GPIO_8_O_LEN) - 1) << GLB_REG_GPIO_8_O_POS) #define GLB_REG_GPIO_8_O_UMSK \ - (~(((1U << GLB_REG_GPIO_8_O_LEN) - 1) << GLB_REG_GPIO_8_O_POS)) + (~(((1 << GLB_REG_GPIO_8_O_LEN) - 1) << GLB_REG_GPIO_8_O_POS)) #define GLB_REG_GPIO_9_O GLB_REG_GPIO_9_O -#define GLB_REG_GPIO_9_O_POS (9U) -#define GLB_REG_GPIO_9_O_LEN (1U) +#define GLB_REG_GPIO_9_O_POS (9) +#define GLB_REG_GPIO_9_O_LEN (1) #define GLB_REG_GPIO_9_O_MSK \ - (((1U << GLB_REG_GPIO_9_O_LEN) - 1) << GLB_REG_GPIO_9_O_POS) + (((1 << GLB_REG_GPIO_9_O_LEN) - 1) << GLB_REG_GPIO_9_O_POS) #define GLB_REG_GPIO_9_O_UMSK \ - (~(((1U << GLB_REG_GPIO_9_O_LEN) - 1) << GLB_REG_GPIO_9_O_POS)) + (~(((1 << GLB_REG_GPIO_9_O_LEN) - 1) << GLB_REG_GPIO_9_O_POS)) #define GLB_REG_GPIO_10_O GLB_REG_GPIO_10_O -#define GLB_REG_GPIO_10_O_POS (10U) -#define GLB_REG_GPIO_10_O_LEN (1U) +#define GLB_REG_GPIO_10_O_POS (10) +#define GLB_REG_GPIO_10_O_LEN (1) #define GLB_REG_GPIO_10_O_MSK \ - (((1U << GLB_REG_GPIO_10_O_LEN) - 1) << GLB_REG_GPIO_10_O_POS) + (((1 << GLB_REG_GPIO_10_O_LEN) - 1) << GLB_REG_GPIO_10_O_POS) #define GLB_REG_GPIO_10_O_UMSK \ - (~(((1U << GLB_REG_GPIO_10_O_LEN) - 1) << GLB_REG_GPIO_10_O_POS)) + (~(((1 << GLB_REG_GPIO_10_O_LEN) - 1) << GLB_REG_GPIO_10_O_POS)) #define GLB_REG_GPIO_11_O GLB_REG_GPIO_11_O -#define GLB_REG_GPIO_11_O_POS (11U) -#define GLB_REG_GPIO_11_O_LEN (1U) +#define GLB_REG_GPIO_11_O_POS (11) +#define GLB_REG_GPIO_11_O_LEN (1) #define GLB_REG_GPIO_11_O_MSK \ - (((1U << GLB_REG_GPIO_11_O_LEN) - 1) << GLB_REG_GPIO_11_O_POS) + (((1 << GLB_REG_GPIO_11_O_LEN) - 1) << GLB_REG_GPIO_11_O_POS) #define GLB_REG_GPIO_11_O_UMSK \ - (~(((1U << GLB_REG_GPIO_11_O_LEN) - 1) << GLB_REG_GPIO_11_O_POS)) + (~(((1 << GLB_REG_GPIO_11_O_LEN) - 1) << GLB_REG_GPIO_11_O_POS)) #define GLB_REG_GPIO_12_O GLB_REG_GPIO_12_O -#define GLB_REG_GPIO_12_O_POS (12U) -#define GLB_REG_GPIO_12_O_LEN (1U) +#define GLB_REG_GPIO_12_O_POS (12) +#define GLB_REG_GPIO_12_O_LEN (1) #define GLB_REG_GPIO_12_O_MSK \ - (((1U << GLB_REG_GPIO_12_O_LEN) - 1) << GLB_REG_GPIO_12_O_POS) + (((1 << GLB_REG_GPIO_12_O_LEN) - 1) << GLB_REG_GPIO_12_O_POS) #define GLB_REG_GPIO_12_O_UMSK \ - (~(((1U << GLB_REG_GPIO_12_O_LEN) - 1) << GLB_REG_GPIO_12_O_POS)) + (~(((1 << GLB_REG_GPIO_12_O_LEN) - 1) << GLB_REG_GPIO_12_O_POS)) #define GLB_REG_GPIO_13_O GLB_REG_GPIO_13_O -#define GLB_REG_GPIO_13_O_POS (13U) -#define GLB_REG_GPIO_13_O_LEN (1U) +#define GLB_REG_GPIO_13_O_POS (13) +#define GLB_REG_GPIO_13_O_LEN (1) #define GLB_REG_GPIO_13_O_MSK \ - (((1U << GLB_REG_GPIO_13_O_LEN) - 1) << GLB_REG_GPIO_13_O_POS) + (((1 << GLB_REG_GPIO_13_O_LEN) - 1) << GLB_REG_GPIO_13_O_POS) #define GLB_REG_GPIO_13_O_UMSK \ - (~(((1U << GLB_REG_GPIO_13_O_LEN) - 1) << GLB_REG_GPIO_13_O_POS)) + (~(((1 << GLB_REG_GPIO_13_O_LEN) - 1) << GLB_REG_GPIO_13_O_POS)) #define GLB_REG_GPIO_14_O GLB_REG_GPIO_14_O -#define GLB_REG_GPIO_14_O_POS (14U) -#define GLB_REG_GPIO_14_O_LEN (1U) +#define GLB_REG_GPIO_14_O_POS (14) +#define GLB_REG_GPIO_14_O_LEN (1) #define GLB_REG_GPIO_14_O_MSK \ - (((1U << GLB_REG_GPIO_14_O_LEN) - 1) << GLB_REG_GPIO_14_O_POS) + (((1 << GLB_REG_GPIO_14_O_LEN) - 1) << GLB_REG_GPIO_14_O_POS) #define GLB_REG_GPIO_14_O_UMSK \ - (~(((1U << GLB_REG_GPIO_14_O_LEN) - 1) << GLB_REG_GPIO_14_O_POS)) + (~(((1 << GLB_REG_GPIO_14_O_LEN) - 1) << GLB_REG_GPIO_14_O_POS)) #define GLB_REG_GPIO_15_O GLB_REG_GPIO_15_O -#define GLB_REG_GPIO_15_O_POS (15U) -#define GLB_REG_GPIO_15_O_LEN (1U) +#define GLB_REG_GPIO_15_O_POS (15) +#define GLB_REG_GPIO_15_O_LEN (1) #define GLB_REG_GPIO_15_O_MSK \ - (((1U << GLB_REG_GPIO_15_O_LEN) - 1) << GLB_REG_GPIO_15_O_POS) + (((1 << GLB_REG_GPIO_15_O_LEN) - 1) << GLB_REG_GPIO_15_O_POS) #define GLB_REG_GPIO_15_O_UMSK \ - (~(((1U << GLB_REG_GPIO_15_O_LEN) - 1) << GLB_REG_GPIO_15_O_POS)) + (~(((1 << GLB_REG_GPIO_15_O_LEN) - 1) << GLB_REG_GPIO_15_O_POS)) #define GLB_REG_GPIO_16_O GLB_REG_GPIO_16_O -#define GLB_REG_GPIO_16_O_POS (16U) -#define GLB_REG_GPIO_16_O_LEN (1U) +#define GLB_REG_GPIO_16_O_POS (16) +#define GLB_REG_GPIO_16_O_LEN (1) #define GLB_REG_GPIO_16_O_MSK \ - (((1U << GLB_REG_GPIO_16_O_LEN) - 1) << GLB_REG_GPIO_16_O_POS) + (((1 << GLB_REG_GPIO_16_O_LEN) - 1) << GLB_REG_GPIO_16_O_POS) #define GLB_REG_GPIO_16_O_UMSK \ - (~(((1U << GLB_REG_GPIO_16_O_LEN) - 1) << GLB_REG_GPIO_16_O_POS)) + (~(((1 << GLB_REG_GPIO_16_O_LEN) - 1) << GLB_REG_GPIO_16_O_POS)) #define GLB_REG_GPIO_17_O GLB_REG_GPIO_17_O -#define GLB_REG_GPIO_17_O_POS (17U) -#define GLB_REG_GPIO_17_O_LEN (1U) +#define GLB_REG_GPIO_17_O_POS (17) +#define GLB_REG_GPIO_17_O_LEN (1) #define GLB_REG_GPIO_17_O_MSK \ - (((1U << GLB_REG_GPIO_17_O_LEN) - 1) << GLB_REG_GPIO_17_O_POS) + (((1 << GLB_REG_GPIO_17_O_LEN) - 1) << GLB_REG_GPIO_17_O_POS) #define GLB_REG_GPIO_17_O_UMSK \ - (~(((1U << GLB_REG_GPIO_17_O_LEN) - 1) << GLB_REG_GPIO_17_O_POS)) + (~(((1 << GLB_REG_GPIO_17_O_LEN) - 1) << GLB_REG_GPIO_17_O_POS)) #define GLB_REG_GPIO_18_O GLB_REG_GPIO_18_O -#define GLB_REG_GPIO_18_O_POS (18U) -#define GLB_REG_GPIO_18_O_LEN (1U) +#define GLB_REG_GPIO_18_O_POS (18) +#define GLB_REG_GPIO_18_O_LEN (1) #define GLB_REG_GPIO_18_O_MSK \ - (((1U << GLB_REG_GPIO_18_O_LEN) - 1) << GLB_REG_GPIO_18_O_POS) + (((1 << GLB_REG_GPIO_18_O_LEN) - 1) << GLB_REG_GPIO_18_O_POS) #define GLB_REG_GPIO_18_O_UMSK \ - (~(((1U << GLB_REG_GPIO_18_O_LEN) - 1) << GLB_REG_GPIO_18_O_POS)) + (~(((1 << GLB_REG_GPIO_18_O_LEN) - 1) << GLB_REG_GPIO_18_O_POS)) #define GLB_REG_GPIO_19_O GLB_REG_GPIO_19_O -#define GLB_REG_GPIO_19_O_POS (19U) -#define GLB_REG_GPIO_19_O_LEN (1U) +#define GLB_REG_GPIO_19_O_POS (19) +#define GLB_REG_GPIO_19_O_LEN (1) #define GLB_REG_GPIO_19_O_MSK \ - (((1U << GLB_REG_GPIO_19_O_LEN) - 1) << GLB_REG_GPIO_19_O_POS) + (((1 << GLB_REG_GPIO_19_O_LEN) - 1) << GLB_REG_GPIO_19_O_POS) #define GLB_REG_GPIO_19_O_UMSK \ - (~(((1U << GLB_REG_GPIO_19_O_LEN) - 1) << GLB_REG_GPIO_19_O_POS)) + (~(((1 << GLB_REG_GPIO_19_O_LEN) - 1) << GLB_REG_GPIO_19_O_POS)) #define GLB_REG_GPIO_20_O GLB_REG_GPIO_20_O -#define GLB_REG_GPIO_20_O_POS (20U) -#define GLB_REG_GPIO_20_O_LEN (1U) +#define GLB_REG_GPIO_20_O_POS (20) +#define GLB_REG_GPIO_20_O_LEN (1) #define GLB_REG_GPIO_20_O_MSK \ - (((1U << GLB_REG_GPIO_20_O_LEN) - 1) << GLB_REG_GPIO_20_O_POS) + (((1 << GLB_REG_GPIO_20_O_LEN) - 1) << GLB_REG_GPIO_20_O_POS) #define GLB_REG_GPIO_20_O_UMSK \ - (~(((1U << GLB_REG_GPIO_20_O_LEN) - 1) << GLB_REG_GPIO_20_O_POS)) + (~(((1 << GLB_REG_GPIO_20_O_LEN) - 1) << GLB_REG_GPIO_20_O_POS)) #define GLB_REG_GPIO_21_O GLB_REG_GPIO_21_O -#define GLB_REG_GPIO_21_O_POS (21U) -#define GLB_REG_GPIO_21_O_LEN (1U) +#define GLB_REG_GPIO_21_O_POS (21) +#define GLB_REG_GPIO_21_O_LEN (1) #define GLB_REG_GPIO_21_O_MSK \ - (((1U << GLB_REG_GPIO_21_O_LEN) - 1) << GLB_REG_GPIO_21_O_POS) + (((1 << GLB_REG_GPIO_21_O_LEN) - 1) << GLB_REG_GPIO_21_O_POS) #define GLB_REG_GPIO_21_O_UMSK \ - (~(((1U << GLB_REG_GPIO_21_O_LEN) - 1) << GLB_REG_GPIO_21_O_POS)) + (~(((1 << GLB_REG_GPIO_21_O_LEN) - 1) << GLB_REG_GPIO_21_O_POS)) #define GLB_REG_GPIO_22_O GLB_REG_GPIO_22_O -#define GLB_REG_GPIO_22_O_POS (22U) -#define GLB_REG_GPIO_22_O_LEN (1U) +#define GLB_REG_GPIO_22_O_POS (22) +#define GLB_REG_GPIO_22_O_LEN (1) #define GLB_REG_GPIO_22_O_MSK \ - (((1U << GLB_REG_GPIO_22_O_LEN) - 1) << GLB_REG_GPIO_22_O_POS) + (((1 << GLB_REG_GPIO_22_O_LEN) - 1) << GLB_REG_GPIO_22_O_POS) #define GLB_REG_GPIO_22_O_UMSK \ - (~(((1U << GLB_REG_GPIO_22_O_LEN) - 1) << GLB_REG_GPIO_22_O_POS)) + (~(((1 << GLB_REG_GPIO_22_O_LEN) - 1) << GLB_REG_GPIO_22_O_POS)) /* 0x18C : GPIO_CFGCTL33 */ @@ -2883,166 +2874,166 @@ #define GLB_GPIO_CFGCTL34_OFFSET (0x190) #define GLB_REG_GPIO_0_OE GLB_REG_GPIO_0_OE -#define GLB_REG_GPIO_0_OE_POS (0U) -#define GLB_REG_GPIO_0_OE_LEN (1U) +#define GLB_REG_GPIO_0_OE_POS (0) +#define GLB_REG_GPIO_0_OE_LEN (1) #define GLB_REG_GPIO_0_OE_MSK \ - (((1U << GLB_REG_GPIO_0_OE_LEN) - 1) << GLB_REG_GPIO_0_OE_POS) + (((1 << GLB_REG_GPIO_0_OE_LEN) - 1) << GLB_REG_GPIO_0_OE_POS) #define GLB_REG_GPIO_0_OE_UMSK \ - (~(((1U << GLB_REG_GPIO_0_OE_LEN) - 1) << GLB_REG_GPIO_0_OE_POS)) + (~(((1 << GLB_REG_GPIO_0_OE_LEN) - 1) << GLB_REG_GPIO_0_OE_POS)) #define GLB_REG_GPIO_1_OE GLB_REG_GPIO_1_OE -#define GLB_REG_GPIO_1_OE_POS (1U) -#define GLB_REG_GPIO_1_OE_LEN (1U) +#define GLB_REG_GPIO_1_OE_POS (1) +#define GLB_REG_GPIO_1_OE_LEN (1) #define GLB_REG_GPIO_1_OE_MSK \ - (((1U << GLB_REG_GPIO_1_OE_LEN) - 1) << GLB_REG_GPIO_1_OE_POS) + (((1 << GLB_REG_GPIO_1_OE_LEN) - 1) << GLB_REG_GPIO_1_OE_POS) #define GLB_REG_GPIO_1_OE_UMSK \ - (~(((1U << GLB_REG_GPIO_1_OE_LEN) - 1) << GLB_REG_GPIO_1_OE_POS)) + (~(((1 << GLB_REG_GPIO_1_OE_LEN) - 1) << GLB_REG_GPIO_1_OE_POS)) #define GLB_REG_GPIO_2_OE GLB_REG_GPIO_2_OE -#define GLB_REG_GPIO_2_OE_POS (2U) -#define GLB_REG_GPIO_2_OE_LEN (1U) +#define GLB_REG_GPIO_2_OE_POS (2) +#define GLB_REG_GPIO_2_OE_LEN (1) #define GLB_REG_GPIO_2_OE_MSK \ - (((1U << GLB_REG_GPIO_2_OE_LEN) - 1) << GLB_REG_GPIO_2_OE_POS) + (((1 << GLB_REG_GPIO_2_OE_LEN) - 1) << GLB_REG_GPIO_2_OE_POS) #define GLB_REG_GPIO_2_OE_UMSK \ - (~(((1U << GLB_REG_GPIO_2_OE_LEN) - 1) << GLB_REG_GPIO_2_OE_POS)) + (~(((1 << GLB_REG_GPIO_2_OE_LEN) - 1) << GLB_REG_GPIO_2_OE_POS)) #define GLB_REG_GPIO_3_OE GLB_REG_GPIO_3_OE -#define GLB_REG_GPIO_3_OE_POS (3U) -#define GLB_REG_GPIO_3_OE_LEN (1U) +#define GLB_REG_GPIO_3_OE_POS (3) +#define GLB_REG_GPIO_3_OE_LEN (1) #define GLB_REG_GPIO_3_OE_MSK \ - (((1U << GLB_REG_GPIO_3_OE_LEN) - 1) << GLB_REG_GPIO_3_OE_POS) + (((1 << GLB_REG_GPIO_3_OE_LEN) - 1) << GLB_REG_GPIO_3_OE_POS) #define GLB_REG_GPIO_3_OE_UMSK \ - (~(((1U << GLB_REG_GPIO_3_OE_LEN) - 1) << GLB_REG_GPIO_3_OE_POS)) + (~(((1 << GLB_REG_GPIO_3_OE_LEN) - 1) << GLB_REG_GPIO_3_OE_POS)) #define GLB_REG_GPIO_4_OE GLB_REG_GPIO_4_OE -#define GLB_REG_GPIO_4_OE_POS (4U) -#define GLB_REG_GPIO_4_OE_LEN (1U) +#define GLB_REG_GPIO_4_OE_POS (4) +#define GLB_REG_GPIO_4_OE_LEN (1) #define GLB_REG_GPIO_4_OE_MSK \ - (((1U << GLB_REG_GPIO_4_OE_LEN) - 1) << GLB_REG_GPIO_4_OE_POS) + (((1 << GLB_REG_GPIO_4_OE_LEN) - 1) << GLB_REG_GPIO_4_OE_POS) #define GLB_REG_GPIO_4_OE_UMSK \ - (~(((1U << GLB_REG_GPIO_4_OE_LEN) - 1) << GLB_REG_GPIO_4_OE_POS)) + (~(((1 << GLB_REG_GPIO_4_OE_LEN) - 1) << GLB_REG_GPIO_4_OE_POS)) #define GLB_REG_GPIO_5_OE GLB_REG_GPIO_5_OE -#define GLB_REG_GPIO_5_OE_POS (5U) -#define GLB_REG_GPIO_5_OE_LEN (1U) +#define GLB_REG_GPIO_5_OE_POS (5) +#define GLB_REG_GPIO_5_OE_LEN (1) #define GLB_REG_GPIO_5_OE_MSK \ - (((1U << GLB_REG_GPIO_5_OE_LEN) - 1) << GLB_REG_GPIO_5_OE_POS) + (((1 << GLB_REG_GPIO_5_OE_LEN) - 1) << GLB_REG_GPIO_5_OE_POS) #define GLB_REG_GPIO_5_OE_UMSK \ - (~(((1U << GLB_REG_GPIO_5_OE_LEN) - 1) << GLB_REG_GPIO_5_OE_POS)) + (~(((1 << GLB_REG_GPIO_5_OE_LEN) - 1) << GLB_REG_GPIO_5_OE_POS)) #define GLB_REG_GPIO_6_OE GLB_REG_GPIO_6_OE -#define GLB_REG_GPIO_6_OE_POS (6U) -#define GLB_REG_GPIO_6_OE_LEN (1U) +#define GLB_REG_GPIO_6_OE_POS (6) +#define GLB_REG_GPIO_6_OE_LEN (1) #define GLB_REG_GPIO_6_OE_MSK \ - (((1U << GLB_REG_GPIO_6_OE_LEN) - 1) << GLB_REG_GPIO_6_OE_POS) + (((1 << GLB_REG_GPIO_6_OE_LEN) - 1) << GLB_REG_GPIO_6_OE_POS) #define GLB_REG_GPIO_6_OE_UMSK \ - (~(((1U << GLB_REG_GPIO_6_OE_LEN) - 1) << GLB_REG_GPIO_6_OE_POS)) + (~(((1 << GLB_REG_GPIO_6_OE_LEN) - 1) << GLB_REG_GPIO_6_OE_POS)) #define GLB_REG_GPIO_7_OE GLB_REG_GPIO_7_OE -#define GLB_REG_GPIO_7_OE_POS (7U) -#define GLB_REG_GPIO_7_OE_LEN (1U) +#define GLB_REG_GPIO_7_OE_POS (7) +#define GLB_REG_GPIO_7_OE_LEN (1) #define GLB_REG_GPIO_7_OE_MSK \ - (((1U << GLB_REG_GPIO_7_OE_LEN) - 1) << GLB_REG_GPIO_7_OE_POS) + (((1 << GLB_REG_GPIO_7_OE_LEN) - 1) << GLB_REG_GPIO_7_OE_POS) #define GLB_REG_GPIO_7_OE_UMSK \ - (~(((1U << GLB_REG_GPIO_7_OE_LEN) - 1) << GLB_REG_GPIO_7_OE_POS)) + (~(((1 << GLB_REG_GPIO_7_OE_LEN) - 1) << GLB_REG_GPIO_7_OE_POS)) #define GLB_REG_GPIO_8_OE GLB_REG_GPIO_8_OE -#define GLB_REG_GPIO_8_OE_POS (8U) -#define GLB_REG_GPIO_8_OE_LEN (1U) +#define GLB_REG_GPIO_8_OE_POS (8) +#define GLB_REG_GPIO_8_OE_LEN (1) #define GLB_REG_GPIO_8_OE_MSK \ - (((1U << GLB_REG_GPIO_8_OE_LEN) - 1) << GLB_REG_GPIO_8_OE_POS) + (((1 << GLB_REG_GPIO_8_OE_LEN) - 1) << GLB_REG_GPIO_8_OE_POS) #define GLB_REG_GPIO_8_OE_UMSK \ - (~(((1U << GLB_REG_GPIO_8_OE_LEN) - 1) << GLB_REG_GPIO_8_OE_POS)) + (~(((1 << GLB_REG_GPIO_8_OE_LEN) - 1) << GLB_REG_GPIO_8_OE_POS)) #define GLB_REG_GPIO_9_OE GLB_REG_GPIO_9_OE -#define GLB_REG_GPIO_9_OE_POS (9U) -#define GLB_REG_GPIO_9_OE_LEN (1U) +#define GLB_REG_GPIO_9_OE_POS (9) +#define GLB_REG_GPIO_9_OE_LEN (1) #define GLB_REG_GPIO_9_OE_MSK \ - (((1U << GLB_REG_GPIO_9_OE_LEN) - 1) << GLB_REG_GPIO_9_OE_POS) + (((1 << GLB_REG_GPIO_9_OE_LEN) - 1) << GLB_REG_GPIO_9_OE_POS) #define GLB_REG_GPIO_9_OE_UMSK \ - (~(((1U << GLB_REG_GPIO_9_OE_LEN) - 1) << GLB_REG_GPIO_9_OE_POS)) + (~(((1 << GLB_REG_GPIO_9_OE_LEN) - 1) << GLB_REG_GPIO_9_OE_POS)) #define GLB_REG_GPIO_10_OE GLB_REG_GPIO_10_OE -#define GLB_REG_GPIO_10_OE_POS (10U) -#define GLB_REG_GPIO_10_OE_LEN (1U) +#define GLB_REG_GPIO_10_OE_POS (10) +#define GLB_REG_GPIO_10_OE_LEN (1) #define GLB_REG_GPIO_10_OE_MSK \ - (((1U << GLB_REG_GPIO_10_OE_LEN) - 1) << GLB_REG_GPIO_10_OE_POS) + (((1 << GLB_REG_GPIO_10_OE_LEN) - 1) << GLB_REG_GPIO_10_OE_POS) #define GLB_REG_GPIO_10_OE_UMSK \ - (~(((1U << GLB_REG_GPIO_10_OE_LEN) - 1) << GLB_REG_GPIO_10_OE_POS)) + (~(((1 << GLB_REG_GPIO_10_OE_LEN) - 1) << GLB_REG_GPIO_10_OE_POS)) #define GLB_REG_GPIO_11_OE GLB_REG_GPIO_11_OE -#define GLB_REG_GPIO_11_OE_POS (11U) -#define GLB_REG_GPIO_11_OE_LEN (1U) +#define GLB_REG_GPIO_11_OE_POS (11) +#define GLB_REG_GPIO_11_OE_LEN (1) #define GLB_REG_GPIO_11_OE_MSK \ - (((1U << GLB_REG_GPIO_11_OE_LEN) - 1) << GLB_REG_GPIO_11_OE_POS) + (((1 << GLB_REG_GPIO_11_OE_LEN) - 1) << GLB_REG_GPIO_11_OE_POS) #define GLB_REG_GPIO_11_OE_UMSK \ - (~(((1U << GLB_REG_GPIO_11_OE_LEN) - 1) << GLB_REG_GPIO_11_OE_POS)) + (~(((1 << GLB_REG_GPIO_11_OE_LEN) - 1) << GLB_REG_GPIO_11_OE_POS)) #define GLB_REG_GPIO_12_OE GLB_REG_GPIO_12_OE -#define GLB_REG_GPIO_12_OE_POS (12U) -#define GLB_REG_GPIO_12_OE_LEN (1U) +#define GLB_REG_GPIO_12_OE_POS (12) +#define GLB_REG_GPIO_12_OE_LEN (1) #define GLB_REG_GPIO_12_OE_MSK \ - (((1U << GLB_REG_GPIO_12_OE_LEN) - 1) << GLB_REG_GPIO_12_OE_POS) + (((1 << GLB_REG_GPIO_12_OE_LEN) - 1) << GLB_REG_GPIO_12_OE_POS) #define GLB_REG_GPIO_12_OE_UMSK \ - (~(((1U << GLB_REG_GPIO_12_OE_LEN) - 1) << GLB_REG_GPIO_12_OE_POS)) + (~(((1 << GLB_REG_GPIO_12_OE_LEN) - 1) << GLB_REG_GPIO_12_OE_POS)) #define GLB_REG_GPIO_13_OE GLB_REG_GPIO_13_OE -#define GLB_REG_GPIO_13_OE_POS (13U) -#define GLB_REG_GPIO_13_OE_LEN (1U) +#define GLB_REG_GPIO_13_OE_POS (13) +#define GLB_REG_GPIO_13_OE_LEN (1) #define GLB_REG_GPIO_13_OE_MSK \ - (((1U << GLB_REG_GPIO_13_OE_LEN) - 1) << GLB_REG_GPIO_13_OE_POS) + (((1 << GLB_REG_GPIO_13_OE_LEN) - 1) << GLB_REG_GPIO_13_OE_POS) #define GLB_REG_GPIO_13_OE_UMSK \ - (~(((1U << GLB_REG_GPIO_13_OE_LEN) - 1) << GLB_REG_GPIO_13_OE_POS)) + (~(((1 << GLB_REG_GPIO_13_OE_LEN) - 1) << GLB_REG_GPIO_13_OE_POS)) #define GLB_REG_GPIO_14_OE GLB_REG_GPIO_14_OE -#define GLB_REG_GPIO_14_OE_POS (14U) -#define GLB_REG_GPIO_14_OE_LEN (1U) +#define GLB_REG_GPIO_14_OE_POS (14) +#define GLB_REG_GPIO_14_OE_LEN (1) #define GLB_REG_GPIO_14_OE_MSK \ - (((1U << GLB_REG_GPIO_14_OE_LEN) - 1) << GLB_REG_GPIO_14_OE_POS) + (((1 << GLB_REG_GPIO_14_OE_LEN) - 1) << GLB_REG_GPIO_14_OE_POS) #define GLB_REG_GPIO_14_OE_UMSK \ - (~(((1U << GLB_REG_GPIO_14_OE_LEN) - 1) << GLB_REG_GPIO_14_OE_POS)) + (~(((1 << GLB_REG_GPIO_14_OE_LEN) - 1) << GLB_REG_GPIO_14_OE_POS)) #define GLB_REG_GPIO_15_OE GLB_REG_GPIO_15_OE -#define GLB_REG_GPIO_15_OE_POS (15U) -#define GLB_REG_GPIO_15_OE_LEN (1U) +#define GLB_REG_GPIO_15_OE_POS (15) +#define GLB_REG_GPIO_15_OE_LEN (1) #define GLB_REG_GPIO_15_OE_MSK \ - (((1U << GLB_REG_GPIO_15_OE_LEN) - 1) << GLB_REG_GPIO_15_OE_POS) + (((1 << GLB_REG_GPIO_15_OE_LEN) - 1) << GLB_REG_GPIO_15_OE_POS) #define GLB_REG_GPIO_15_OE_UMSK \ - (~(((1U << GLB_REG_GPIO_15_OE_LEN) - 1) << GLB_REG_GPIO_15_OE_POS)) + (~(((1 << GLB_REG_GPIO_15_OE_LEN) - 1) << GLB_REG_GPIO_15_OE_POS)) #define GLB_REG_GPIO_16_OE GLB_REG_GPIO_16_OE -#define GLB_REG_GPIO_16_OE_POS (16U) -#define GLB_REG_GPIO_16_OE_LEN (1U) +#define GLB_REG_GPIO_16_OE_POS (16) +#define GLB_REG_GPIO_16_OE_LEN (1) #define GLB_REG_GPIO_16_OE_MSK \ - (((1U << GLB_REG_GPIO_16_OE_LEN) - 1) << GLB_REG_GPIO_16_OE_POS) + (((1 << GLB_REG_GPIO_16_OE_LEN) - 1) << GLB_REG_GPIO_16_OE_POS) #define GLB_REG_GPIO_16_OE_UMSK \ - (~(((1U << GLB_REG_GPIO_16_OE_LEN) - 1) << GLB_REG_GPIO_16_OE_POS)) + (~(((1 << GLB_REG_GPIO_16_OE_LEN) - 1) << GLB_REG_GPIO_16_OE_POS)) #define GLB_REG_GPIO_17_OE GLB_REG_GPIO_17_OE -#define GLB_REG_GPIO_17_OE_POS (17U) -#define GLB_REG_GPIO_17_OE_LEN (1U) +#define GLB_REG_GPIO_17_OE_POS (17) +#define GLB_REG_GPIO_17_OE_LEN (1) #define GLB_REG_GPIO_17_OE_MSK \ - (((1U << GLB_REG_GPIO_17_OE_LEN) - 1) << GLB_REG_GPIO_17_OE_POS) + (((1 << GLB_REG_GPIO_17_OE_LEN) - 1) << GLB_REG_GPIO_17_OE_POS) #define GLB_REG_GPIO_17_OE_UMSK \ - (~(((1U << GLB_REG_GPIO_17_OE_LEN) - 1) << GLB_REG_GPIO_17_OE_POS)) + (~(((1 << GLB_REG_GPIO_17_OE_LEN) - 1) << GLB_REG_GPIO_17_OE_POS)) #define GLB_REG_GPIO_18_OE GLB_REG_GPIO_18_OE -#define GLB_REG_GPIO_18_OE_POS (18U) -#define GLB_REG_GPIO_18_OE_LEN (1U) +#define GLB_REG_GPIO_18_OE_POS (18) +#define GLB_REG_GPIO_18_OE_LEN (1) #define GLB_REG_GPIO_18_OE_MSK \ - (((1U << GLB_REG_GPIO_18_OE_LEN) - 1) << GLB_REG_GPIO_18_OE_POS) + (((1 << GLB_REG_GPIO_18_OE_LEN) - 1) << GLB_REG_GPIO_18_OE_POS) #define GLB_REG_GPIO_18_OE_UMSK \ - (~(((1U << GLB_REG_GPIO_18_OE_LEN) - 1) << GLB_REG_GPIO_18_OE_POS)) + (~(((1 << GLB_REG_GPIO_18_OE_LEN) - 1) << GLB_REG_GPIO_18_OE_POS)) #define GLB_REG_GPIO_19_OE GLB_REG_GPIO_19_OE -#define GLB_REG_GPIO_19_OE_POS (19U) -#define GLB_REG_GPIO_19_OE_LEN (1U) +#define GLB_REG_GPIO_19_OE_POS (19) +#define GLB_REG_GPIO_19_OE_LEN (1) #define GLB_REG_GPIO_19_OE_MSK \ - (((1U << GLB_REG_GPIO_19_OE_LEN) - 1) << GLB_REG_GPIO_19_OE_POS) + (((1 << GLB_REG_GPIO_19_OE_LEN) - 1) << GLB_REG_GPIO_19_OE_POS) #define GLB_REG_GPIO_19_OE_UMSK \ - (~(((1U << GLB_REG_GPIO_19_OE_LEN) - 1) << GLB_REG_GPIO_19_OE_POS)) + (~(((1 << GLB_REG_GPIO_19_OE_LEN) - 1) << GLB_REG_GPIO_19_OE_POS)) #define GLB_REG_GPIO_20_OE GLB_REG_GPIO_20_OE -#define GLB_REG_GPIO_20_OE_POS (20U) -#define GLB_REG_GPIO_20_OE_LEN (1U) +#define GLB_REG_GPIO_20_OE_POS (20) +#define GLB_REG_GPIO_20_OE_LEN (1) #define GLB_REG_GPIO_20_OE_MSK \ - (((1U << GLB_REG_GPIO_20_OE_LEN) - 1) << GLB_REG_GPIO_20_OE_POS) + (((1 << GLB_REG_GPIO_20_OE_LEN) - 1) << GLB_REG_GPIO_20_OE_POS) #define GLB_REG_GPIO_20_OE_UMSK \ - (~(((1U << GLB_REG_GPIO_20_OE_LEN) - 1) << GLB_REG_GPIO_20_OE_POS)) + (~(((1 << GLB_REG_GPIO_20_OE_LEN) - 1) << GLB_REG_GPIO_20_OE_POS)) #define GLB_REG_GPIO_21_OE GLB_REG_GPIO_21_OE -#define GLB_REG_GPIO_21_OE_POS (21U) -#define GLB_REG_GPIO_21_OE_LEN (1U) +#define GLB_REG_GPIO_21_OE_POS (21) +#define GLB_REG_GPIO_21_OE_LEN (1) #define GLB_REG_GPIO_21_OE_MSK \ - (((1U << GLB_REG_GPIO_21_OE_LEN) - 1) << GLB_REG_GPIO_21_OE_POS) + (((1 << GLB_REG_GPIO_21_OE_LEN) - 1) << GLB_REG_GPIO_21_OE_POS) #define GLB_REG_GPIO_21_OE_UMSK \ - (~(((1U << GLB_REG_GPIO_21_OE_LEN) - 1) << GLB_REG_GPIO_21_OE_POS)) + (~(((1 << GLB_REG_GPIO_21_OE_LEN) - 1) << GLB_REG_GPIO_21_OE_POS)) #define GLB_REG_GPIO_22_OE GLB_REG_GPIO_22_OE -#define GLB_REG_GPIO_22_OE_POS (22U) -#define GLB_REG_GPIO_22_OE_LEN (1U) +#define GLB_REG_GPIO_22_OE_POS (22) +#define GLB_REG_GPIO_22_OE_LEN (1) #define GLB_REG_GPIO_22_OE_MSK \ - (((1U << GLB_REG_GPIO_22_OE_LEN) - 1) << GLB_REG_GPIO_22_OE_POS) + (((1 << GLB_REG_GPIO_22_OE_LEN) - 1) << GLB_REG_GPIO_22_OE_POS) #define GLB_REG_GPIO_22_OE_UMSK \ - (~(((1U << GLB_REG_GPIO_22_OE_LEN) - 1) << GLB_REG_GPIO_22_OE_POS)) + (~(((1 << GLB_REG_GPIO_22_OE_LEN) - 1) << GLB_REG_GPIO_22_OE_POS)) /* 0x194 : GPIO_CFGCTL35 */ @@ -3052,891 +3043,881 @@ #define GLB_GPIO_INT_MASK1_OFFSET (0x1A0) #define GLB_REG_GPIO_INT_MASK1 GLB_REG_GPIO_INT_MASK1 -#define GLB_REG_GPIO_INT_MASK1_POS (0U) -#define GLB_REG_GPIO_INT_MASK1_LEN (32U) +#define GLB_REG_GPIO_INT_MASK1_POS (0) +#define GLB_REG_GPIO_INT_MASK1_LEN (32) #define GLB_REG_GPIO_INT_MASK1_MSK \ - (((1U << GLB_REG_GPIO_INT_MASK1_LEN) - 1) << GLB_REG_GPIO_INT_MASK1_POS) + (((1 << GLB_REG_GPIO_INT_MASK1_LEN) - 1) << GLB_REG_GPIO_INT_MASK1_POS) #define GLB_REG_GPIO_INT_MASK1_UMSK \ - (~(((1U << GLB_REG_GPIO_INT_MASK1_LEN) - 1) << GLB_REG_GPIO_INT_MASK1_POS)) + (~(((1 << GLB_REG_GPIO_INT_MASK1_LEN) - 1) << GLB_REG_GPIO_INT_MASK1_POS)) /* 0x1A8 : GPIO_INT_STAT1 */ #define GLB_GPIO_INT_STAT1_OFFSET (0x1A8) #define GLB_GPIO_INT_STAT1 GLB_GPIO_INT_STAT1 -#define GLB_GPIO_INT_STAT1_POS (0U) -#define GLB_GPIO_INT_STAT1_LEN (32U) +#define GLB_GPIO_INT_STAT1_POS (0) +#define GLB_GPIO_INT_STAT1_LEN (32) #define GLB_GPIO_INT_STAT1_MSK \ - (((1U << GLB_GPIO_INT_STAT1_LEN) - 1) << GLB_GPIO_INT_STAT1_POS) + (((1 << GLB_GPIO_INT_STAT1_LEN) - 1) << GLB_GPIO_INT_STAT1_POS) #define GLB_GPIO_INT_STAT1_UMSK \ - (~(((1U << GLB_GPIO_INT_STAT1_LEN) - 1) << GLB_GPIO_INT_STAT1_POS)) + (~(((1 << GLB_GPIO_INT_STAT1_LEN) - 1) << GLB_GPIO_INT_STAT1_POS)) /* 0x1B0 : GPIO_INT_CLR1 */ #define GLB_GPIO_INT_CLR1_OFFSET (0x1B0) #define GLB_REG_GPIO_INT_CLR1 GLB_REG_GPIO_INT_CLR1 -#define GLB_REG_GPIO_INT_CLR1_POS (0U) -#define GLB_REG_GPIO_INT_CLR1_LEN (32U) +#define GLB_REG_GPIO_INT_CLR1_POS (0) +#define GLB_REG_GPIO_INT_CLR1_LEN (32) #define GLB_REG_GPIO_INT_CLR1_MSK \ - (((1U << GLB_REG_GPIO_INT_CLR1_LEN) - 1) << GLB_REG_GPIO_INT_CLR1_POS) + (((1 << GLB_REG_GPIO_INT_CLR1_LEN) - 1) << GLB_REG_GPIO_INT_CLR1_POS) #define GLB_REG_GPIO_INT_CLR1_UMSK \ - (~(((1U << GLB_REG_GPIO_INT_CLR1_LEN) - 1) << GLB_REG_GPIO_INT_CLR1_POS)) + (~(((1 << GLB_REG_GPIO_INT_CLR1_LEN) - 1) << GLB_REG_GPIO_INT_CLR1_POS)) /* 0x1C0 : GPIO_INT_MODE_SET1 */ #define GLB_GPIO_INT_MODE_SET1_OFFSET (0x1C0) #define GLB_REG_GPIO_INT_MODE_SET1 GLB_REG_GPIO_INT_MODE_SET1 -#define GLB_REG_GPIO_INT_MODE_SET1_POS (0U) -#define GLB_REG_GPIO_INT_MODE_SET1_LEN (32U) +#define GLB_REG_GPIO_INT_MODE_SET1_POS (0) +#define GLB_REG_GPIO_INT_MODE_SET1_LEN (32) #define GLB_REG_GPIO_INT_MODE_SET1_MSK \ - (((1U << GLB_REG_GPIO_INT_MODE_SET1_LEN) - 1) \ + (((1 << GLB_REG_GPIO_INT_MODE_SET1_LEN) - 1) \ << GLB_REG_GPIO_INT_MODE_SET1_POS) #define GLB_REG_GPIO_INT_MODE_SET1_UMSK \ - (~(((1U << GLB_REG_GPIO_INT_MODE_SET1_LEN) - 1) \ + (~(((1 << GLB_REG_GPIO_INT_MODE_SET1_LEN) - 1) \ << GLB_REG_GPIO_INT_MODE_SET1_POS)) /* 0x1C4 : GPIO_INT_MODE_SET2 */ #define GLB_GPIO_INT_MODE_SET2_OFFSET (0x1C4) #define GLB_REG_GPIO_INT_MODE_SET2 GLB_REG_GPIO_INT_MODE_SET2 -#define GLB_REG_GPIO_INT_MODE_SET2_POS (0U) -#define GLB_REG_GPIO_INT_MODE_SET2_LEN (32U) +#define GLB_REG_GPIO_INT_MODE_SET2_POS (0) +#define GLB_REG_GPIO_INT_MODE_SET2_LEN (32) #define GLB_REG_GPIO_INT_MODE_SET2_MSK \ - (((1U << GLB_REG_GPIO_INT_MODE_SET2_LEN) - 1) \ + (((1 << GLB_REG_GPIO_INT_MODE_SET2_LEN) - 1) \ << GLB_REG_GPIO_INT_MODE_SET2_POS) #define GLB_REG_GPIO_INT_MODE_SET2_UMSK \ - (~(((1U << GLB_REG_GPIO_INT_MODE_SET2_LEN) - 1) \ + (~(((1 << GLB_REG_GPIO_INT_MODE_SET2_LEN) - 1) \ << GLB_REG_GPIO_INT_MODE_SET2_POS)) /* 0x1C8 : GPIO_INT_MODE_SET3 */ #define GLB_GPIO_INT_MODE_SET3_OFFSET (0x1C8) #define GLB_REG_GPIO_INT_MODE_SET3 GLB_REG_GPIO_INT_MODE_SET3 -#define GLB_REG_GPIO_INT_MODE_SET3_POS (0U) -#define GLB_REG_GPIO_INT_MODE_SET3_LEN (32U) +#define GLB_REG_GPIO_INT_MODE_SET3_POS (0) +#define GLB_REG_GPIO_INT_MODE_SET3_LEN (32) #define GLB_REG_GPIO_INT_MODE_SET3_MSK \ - (((1U << GLB_REG_GPIO_INT_MODE_SET3_LEN) - 1) \ + (((1 << GLB_REG_GPIO_INT_MODE_SET3_LEN) - 1) \ << GLB_REG_GPIO_INT_MODE_SET3_POS) #define GLB_REG_GPIO_INT_MODE_SET3_UMSK \ - (~(((1U << GLB_REG_GPIO_INT_MODE_SET3_LEN) - 1) \ + (~(((1 << GLB_REG_GPIO_INT_MODE_SET3_LEN) - 1) \ << GLB_REG_GPIO_INT_MODE_SET3_POS)) /* 0x224 : led_driver */ #define GLB_LED_DRIVER_OFFSET (0x224) #define GLB_LED_DIN_REG GLB_LED_DIN_REG -#define GLB_LED_DIN_REG_POS (0U) -#define GLB_LED_DIN_REG_LEN (1U) +#define GLB_LED_DIN_REG_POS (0) +#define GLB_LED_DIN_REG_LEN (1) #define GLB_LED_DIN_REG_MSK \ - (((1U << GLB_LED_DIN_REG_LEN) - 1) << GLB_LED_DIN_REG_POS) + (((1 << GLB_LED_DIN_REG_LEN) - 1) << GLB_LED_DIN_REG_POS) #define GLB_LED_DIN_REG_UMSK \ - (~(((1U << GLB_LED_DIN_REG_LEN) - 1) << GLB_LED_DIN_REG_POS)) + (~(((1 << GLB_LED_DIN_REG_LEN) - 1) << GLB_LED_DIN_REG_POS)) #define GLB_LED_DIN_SEL GLB_LED_DIN_SEL -#define GLB_LED_DIN_SEL_POS (1U) -#define GLB_LED_DIN_SEL_LEN (1U) +#define GLB_LED_DIN_SEL_POS (1) +#define GLB_LED_DIN_SEL_LEN (1) #define GLB_LED_DIN_SEL_MSK \ - (((1U << GLB_LED_DIN_SEL_LEN) - 1) << GLB_LED_DIN_SEL_POS) + (((1 << GLB_LED_DIN_SEL_LEN) - 1) << GLB_LED_DIN_SEL_POS) #define GLB_LED_DIN_SEL_UMSK \ - (~(((1U << GLB_LED_DIN_SEL_LEN) - 1) << GLB_LED_DIN_SEL_POS)) + (~(((1 << GLB_LED_DIN_SEL_LEN) - 1) << GLB_LED_DIN_SEL_POS)) #define GLB_LED_DIN_POLARITY_SEL GLB_LED_DIN_POLARITY_SEL -#define GLB_LED_DIN_POLARITY_SEL_POS (2U) -#define GLB_LED_DIN_POLARITY_SEL_LEN (1U) +#define GLB_LED_DIN_POLARITY_SEL_POS (2) +#define GLB_LED_DIN_POLARITY_SEL_LEN (1) #define GLB_LED_DIN_POLARITY_SEL_MSK \ - (((1U << GLB_LED_DIN_POLARITY_SEL_LEN) - 1) << GLB_LED_DIN_POLARITY_SEL_POS) + (((1 << GLB_LED_DIN_POLARITY_SEL_LEN) - 1) << GLB_LED_DIN_POLARITY_SEL_POS) #define GLB_LED_DIN_POLARITY_SEL_UMSK \ - (~(((1U << GLB_LED_DIN_POLARITY_SEL_LEN) - 1) \ + (~(((1 << GLB_LED_DIN_POLARITY_SEL_LEN) - 1) \ << GLB_LED_DIN_POLARITY_SEL_POS)) #define GLB_LEDDRV_IBIAS GLB_LEDDRV_IBIAS -#define GLB_LEDDRV_IBIAS_POS (4U) -#define GLB_LEDDRV_IBIAS_LEN (4U) +#define GLB_LEDDRV_IBIAS_POS (4) +#define GLB_LEDDRV_IBIAS_LEN (4) #define GLB_LEDDRV_IBIAS_MSK \ - (((1U << GLB_LEDDRV_IBIAS_LEN) - 1) << GLB_LEDDRV_IBIAS_POS) + (((1 << GLB_LEDDRV_IBIAS_LEN) - 1) << GLB_LEDDRV_IBIAS_POS) #define GLB_LEDDRV_IBIAS_UMSK \ - (~(((1U << GLB_LEDDRV_IBIAS_LEN) - 1) << GLB_LEDDRV_IBIAS_POS)) + (~(((1 << GLB_LEDDRV_IBIAS_LEN) - 1) << GLB_LEDDRV_IBIAS_POS)) #define GLB_IR_RX_GPIO_SEL GLB_IR_RX_GPIO_SEL -#define GLB_IR_RX_GPIO_SEL_POS (8U) -#define GLB_IR_RX_GPIO_SEL_LEN (2U) +#define GLB_IR_RX_GPIO_SEL_POS (8) +#define GLB_IR_RX_GPIO_SEL_LEN (2) #define GLB_IR_RX_GPIO_SEL_MSK \ - (((1U << GLB_IR_RX_GPIO_SEL_LEN) - 1) << GLB_IR_RX_GPIO_SEL_POS) + (((1 << GLB_IR_RX_GPIO_SEL_LEN) - 1) << GLB_IR_RX_GPIO_SEL_POS) #define GLB_IR_RX_GPIO_SEL_UMSK \ - (~(((1U << GLB_IR_RX_GPIO_SEL_LEN) - 1) << GLB_IR_RX_GPIO_SEL_POS)) + (~(((1 << GLB_IR_RX_GPIO_SEL_LEN) - 1) << GLB_IR_RX_GPIO_SEL_POS)) #define GLB_PU_LEDDRV GLB_PU_LEDDRV -#define GLB_PU_LEDDRV_POS (31U) -#define GLB_PU_LEDDRV_LEN (1U) +#define GLB_PU_LEDDRV_POS (31) +#define GLB_PU_LEDDRV_LEN (1) #define GLB_PU_LEDDRV_MSK \ - (((1U << GLB_PU_LEDDRV_LEN) - 1) << GLB_PU_LEDDRV_POS) + (((1 << GLB_PU_LEDDRV_LEN) - 1) << GLB_PU_LEDDRV_POS) #define GLB_PU_LEDDRV_UMSK \ - (~(((1U << GLB_PU_LEDDRV_LEN) - 1) << GLB_PU_LEDDRV_POS)) + (~(((1 << GLB_PU_LEDDRV_LEN) - 1) << GLB_PU_LEDDRV_POS)) /* 0x308 : gpdac_ctrl */ #define GLB_GPDAC_CTRL_OFFSET (0x308) #define GLB_GPDACA_RSTN_ANA GLB_GPDACA_RSTN_ANA -#define GLB_GPDACA_RSTN_ANA_POS (0U) -#define GLB_GPDACA_RSTN_ANA_LEN (1U) +#define GLB_GPDACA_RSTN_ANA_POS (0) +#define GLB_GPDACA_RSTN_ANA_LEN (1) #define GLB_GPDACA_RSTN_ANA_MSK \ - (((1U << GLB_GPDACA_RSTN_ANA_LEN) - 1) << GLB_GPDACA_RSTN_ANA_POS) + (((1 << GLB_GPDACA_RSTN_ANA_LEN) - 1) << GLB_GPDACA_RSTN_ANA_POS) #define GLB_GPDACA_RSTN_ANA_UMSK \ - (~(((1U << GLB_GPDACA_RSTN_ANA_LEN) - 1) << GLB_GPDACA_RSTN_ANA_POS)) + (~(((1 << GLB_GPDACA_RSTN_ANA_LEN) - 1) << GLB_GPDACA_RSTN_ANA_POS)) #define GLB_GPDACB_RSTN_ANA GLB_GPDACB_RSTN_ANA -#define GLB_GPDACB_RSTN_ANA_POS (1U) -#define GLB_GPDACB_RSTN_ANA_LEN (1U) +#define GLB_GPDACB_RSTN_ANA_POS (1) +#define GLB_GPDACB_RSTN_ANA_LEN (1) #define GLB_GPDACB_RSTN_ANA_MSK \ - (((1U << GLB_GPDACB_RSTN_ANA_LEN) - 1) << GLB_GPDACB_RSTN_ANA_POS) + (((1 << GLB_GPDACB_RSTN_ANA_LEN) - 1) << GLB_GPDACB_RSTN_ANA_POS) #define GLB_GPDACB_RSTN_ANA_UMSK \ - (~(((1U << GLB_GPDACB_RSTN_ANA_LEN) - 1) << GLB_GPDACB_RSTN_ANA_POS)) + (~(((1 << GLB_GPDACB_RSTN_ANA_LEN) - 1) << GLB_GPDACB_RSTN_ANA_POS)) #define GLB_GPDAC_TEST_EN GLB_GPDAC_TEST_EN -#define GLB_GPDAC_TEST_EN_POS (7U) -#define GLB_GPDAC_TEST_EN_LEN (1U) +#define GLB_GPDAC_TEST_EN_POS (7) +#define GLB_GPDAC_TEST_EN_LEN (1) #define GLB_GPDAC_TEST_EN_MSK \ - (((1U << GLB_GPDAC_TEST_EN_LEN) - 1) << GLB_GPDAC_TEST_EN_POS) + (((1 << GLB_GPDAC_TEST_EN_LEN) - 1) << GLB_GPDAC_TEST_EN_POS) #define GLB_GPDAC_TEST_EN_UMSK \ - (~(((1U << GLB_GPDAC_TEST_EN_LEN) - 1) << GLB_GPDAC_TEST_EN_POS)) + (~(((1 << GLB_GPDAC_TEST_EN_LEN) - 1) << GLB_GPDAC_TEST_EN_POS)) #define GLB_GPDAC_REF_SEL GLB_GPDAC_REF_SEL -#define GLB_GPDAC_REF_SEL_POS (8U) -#define GLB_GPDAC_REF_SEL_LEN (1U) +#define GLB_GPDAC_REF_SEL_POS (8) +#define GLB_GPDAC_REF_SEL_LEN (1) #define GLB_GPDAC_REF_SEL_MSK \ - (((1U << GLB_GPDAC_REF_SEL_LEN) - 1) << GLB_GPDAC_REF_SEL_POS) + (((1 << GLB_GPDAC_REF_SEL_LEN) - 1) << GLB_GPDAC_REF_SEL_POS) #define GLB_GPDAC_REF_SEL_UMSK \ - (~(((1U << GLB_GPDAC_REF_SEL_LEN) - 1) << GLB_GPDAC_REF_SEL_POS)) + (~(((1 << GLB_GPDAC_REF_SEL_LEN) - 1) << GLB_GPDAC_REF_SEL_POS)) #define GLB_GPDAC_TEST_SEL GLB_GPDAC_TEST_SEL -#define GLB_GPDAC_TEST_SEL_POS (9U) -#define GLB_GPDAC_TEST_SEL_LEN (3U) +#define GLB_GPDAC_TEST_SEL_POS (9) +#define GLB_GPDAC_TEST_SEL_LEN (3) #define GLB_GPDAC_TEST_SEL_MSK \ - (((1U << GLB_GPDAC_TEST_SEL_LEN) - 1) << GLB_GPDAC_TEST_SEL_POS) + (((1 << GLB_GPDAC_TEST_SEL_LEN) - 1) << GLB_GPDAC_TEST_SEL_POS) #define GLB_GPDAC_TEST_SEL_UMSK \ - (~(((1U << GLB_GPDAC_TEST_SEL_LEN) - 1) << GLB_GPDAC_TEST_SEL_POS)) + (~(((1 << GLB_GPDAC_TEST_SEL_LEN) - 1) << GLB_GPDAC_TEST_SEL_POS)) #define GLB_GPDAC_RESERVED GLB_GPDAC_RESERVED -#define GLB_GPDAC_RESERVED_POS (24U) -#define GLB_GPDAC_RESERVED_LEN (8U) +#define GLB_GPDAC_RESERVED_POS (24) +#define GLB_GPDAC_RESERVED_LEN (8) #define GLB_GPDAC_RESERVED_MSK \ - (((1U << GLB_GPDAC_RESERVED_LEN) - 1) << GLB_GPDAC_RESERVED_POS) + (((1 << GLB_GPDAC_RESERVED_LEN) - 1) << GLB_GPDAC_RESERVED_POS) #define GLB_GPDAC_RESERVED_UMSK \ - (~(((1U << GLB_GPDAC_RESERVED_LEN) - 1) << GLB_GPDAC_RESERVED_POS)) + (~(((1 << GLB_GPDAC_RESERVED_LEN) - 1) << GLB_GPDAC_RESERVED_POS)) /* 0x30C : gpdac_actrl */ #define GLB_GPDAC_ACTRL_OFFSET (0x30C) #define GLB_GPDAC_A_EN GLB_GPDAC_A_EN -#define GLB_GPDAC_A_EN_POS (0U) -#define GLB_GPDAC_A_EN_LEN (1U) +#define GLB_GPDAC_A_EN_POS (0) +#define GLB_GPDAC_A_EN_LEN (1) #define GLB_GPDAC_A_EN_MSK \ - (((1U << GLB_GPDAC_A_EN_LEN) - 1) << GLB_GPDAC_A_EN_POS) + (((1 << GLB_GPDAC_A_EN_LEN) - 1) << GLB_GPDAC_A_EN_POS) #define GLB_GPDAC_A_EN_UMSK \ - (~(((1U << GLB_GPDAC_A_EN_LEN) - 1) << GLB_GPDAC_A_EN_POS)) + (~(((1 << GLB_GPDAC_A_EN_LEN) - 1) << GLB_GPDAC_A_EN_POS)) #define GLB_GPDAC_IOA_EN GLB_GPDAC_IOA_EN -#define GLB_GPDAC_IOA_EN_POS (1U) -#define GLB_GPDAC_IOA_EN_LEN (1U) +#define GLB_GPDAC_IOA_EN_POS (1) +#define GLB_GPDAC_IOA_EN_LEN (1) #define GLB_GPDAC_IOA_EN_MSK \ - (((1U << GLB_GPDAC_IOA_EN_LEN) - 1) << GLB_GPDAC_IOA_EN_POS) + (((1 << GLB_GPDAC_IOA_EN_LEN) - 1) << GLB_GPDAC_IOA_EN_POS) #define GLB_GPDAC_IOA_EN_UMSK \ - (~(((1U << GLB_GPDAC_IOA_EN_LEN) - 1) << GLB_GPDAC_IOA_EN_POS)) + (~(((1 << GLB_GPDAC_IOA_EN_LEN) - 1) << GLB_GPDAC_IOA_EN_POS)) #define GLB_GPDAC_A_RNG GLB_GPDAC_A_RNG -#define GLB_GPDAC_A_RNG_POS (18U) -#define GLB_GPDAC_A_RNG_LEN (2U) +#define GLB_GPDAC_A_RNG_POS (18) +#define GLB_GPDAC_A_RNG_LEN (2) #define GLB_GPDAC_A_RNG_MSK \ - (((1U << GLB_GPDAC_A_RNG_LEN) - 1) << GLB_GPDAC_A_RNG_POS) + (((1 << GLB_GPDAC_A_RNG_LEN) - 1) << GLB_GPDAC_A_RNG_POS) #define GLB_GPDAC_A_RNG_UMSK \ - (~(((1U << GLB_GPDAC_A_RNG_LEN) - 1) << GLB_GPDAC_A_RNG_POS)) + (~(((1 << GLB_GPDAC_A_RNG_LEN) - 1) << GLB_GPDAC_A_RNG_POS)) #define GLB_GPDAC_A_OUTMUX GLB_GPDAC_A_OUTMUX -#define GLB_GPDAC_A_OUTMUX_POS (20U) -#define GLB_GPDAC_A_OUTMUX_LEN (3U) +#define GLB_GPDAC_A_OUTMUX_POS (20) +#define GLB_GPDAC_A_OUTMUX_LEN (3) #define GLB_GPDAC_A_OUTMUX_MSK \ - (((1U << GLB_GPDAC_A_OUTMUX_LEN) - 1) << GLB_GPDAC_A_OUTMUX_POS) + (((1 << GLB_GPDAC_A_OUTMUX_LEN) - 1) << GLB_GPDAC_A_OUTMUX_POS) #define GLB_GPDAC_A_OUTMUX_UMSK \ - (~(((1U << GLB_GPDAC_A_OUTMUX_LEN) - 1) << GLB_GPDAC_A_OUTMUX_POS)) + (~(((1 << GLB_GPDAC_A_OUTMUX_LEN) - 1) << GLB_GPDAC_A_OUTMUX_POS)) /* 0x310 : gpdac_bctrl */ #define GLB_GPDAC_BCTRL_OFFSET (0x310) #define GLB_GPDAC_B_EN GLB_GPDAC_B_EN -#define GLB_GPDAC_B_EN_POS (0U) -#define GLB_GPDAC_B_EN_LEN (1U) +#define GLB_GPDAC_B_EN_POS (0) +#define GLB_GPDAC_B_EN_LEN (1) #define GLB_GPDAC_B_EN_MSK \ - (((1U << GLB_GPDAC_B_EN_LEN) - 1) << GLB_GPDAC_B_EN_POS) + (((1 << GLB_GPDAC_B_EN_LEN) - 1) << GLB_GPDAC_B_EN_POS) #define GLB_GPDAC_B_EN_UMSK \ - (~(((1U << GLB_GPDAC_B_EN_LEN) - 1) << GLB_GPDAC_B_EN_POS)) + (~(((1 << GLB_GPDAC_B_EN_LEN) - 1) << GLB_GPDAC_B_EN_POS)) #define GLB_GPDAC_IOB_EN GLB_GPDAC_IOB_EN -#define GLB_GPDAC_IOB_EN_POS (1U) -#define GLB_GPDAC_IOB_EN_LEN (1U) +#define GLB_GPDAC_IOB_EN_POS (1) +#define GLB_GPDAC_IOB_EN_LEN (1) #define GLB_GPDAC_IOB_EN_MSK \ - (((1U << GLB_GPDAC_IOB_EN_LEN) - 1) << GLB_GPDAC_IOB_EN_POS) + (((1 << GLB_GPDAC_IOB_EN_LEN) - 1) << GLB_GPDAC_IOB_EN_POS) #define GLB_GPDAC_IOB_EN_UMSK \ - (~(((1U << GLB_GPDAC_IOB_EN_LEN) - 1) << GLB_GPDAC_IOB_EN_POS)) + (~(((1 << GLB_GPDAC_IOB_EN_LEN) - 1) << GLB_GPDAC_IOB_EN_POS)) #define GLB_GPDAC_B_RNG GLB_GPDAC_B_RNG -#define GLB_GPDAC_B_RNG_POS (18U) -#define GLB_GPDAC_B_RNG_LEN (2U) +#define GLB_GPDAC_B_RNG_POS (18) +#define GLB_GPDAC_B_RNG_LEN (2) #define GLB_GPDAC_B_RNG_MSK \ - (((1U << GLB_GPDAC_B_RNG_LEN) - 1) << GLB_GPDAC_B_RNG_POS) + (((1 << GLB_GPDAC_B_RNG_LEN) - 1) << GLB_GPDAC_B_RNG_POS) #define GLB_GPDAC_B_RNG_UMSK \ - (~(((1U << GLB_GPDAC_B_RNG_LEN) - 1) << GLB_GPDAC_B_RNG_POS)) + (~(((1 << GLB_GPDAC_B_RNG_LEN) - 1) << GLB_GPDAC_B_RNG_POS)) #define GLB_GPDAC_B_OUTMUX GLB_GPDAC_B_OUTMUX -#define GLB_GPDAC_B_OUTMUX_POS (20U) -#define GLB_GPDAC_B_OUTMUX_LEN (3U) +#define GLB_GPDAC_B_OUTMUX_POS (20) +#define GLB_GPDAC_B_OUTMUX_LEN (3) #define GLB_GPDAC_B_OUTMUX_MSK \ - (((1U << GLB_GPDAC_B_OUTMUX_LEN) - 1) << GLB_GPDAC_B_OUTMUX_POS) + (((1 << GLB_GPDAC_B_OUTMUX_LEN) - 1) << GLB_GPDAC_B_OUTMUX_POS) #define GLB_GPDAC_B_OUTMUX_UMSK \ - (~(((1U << GLB_GPDAC_B_OUTMUX_LEN) - 1) << GLB_GPDAC_B_OUTMUX_POS)) + (~(((1 << GLB_GPDAC_B_OUTMUX_LEN) - 1) << GLB_GPDAC_B_OUTMUX_POS)) /* 0x314 : gpdac_data */ #define GLB_GPDAC_DATA_OFFSET (0x314) #define GLB_GPDAC_B_DATA GLB_GPDAC_B_DATA -#define GLB_GPDAC_B_DATA_POS (0U) -#define GLB_GPDAC_B_DATA_LEN (10U) +#define GLB_GPDAC_B_DATA_POS (0) +#define GLB_GPDAC_B_DATA_LEN (10) #define GLB_GPDAC_B_DATA_MSK \ - (((1U << GLB_GPDAC_B_DATA_LEN) - 1) << GLB_GPDAC_B_DATA_POS) + (((1 << GLB_GPDAC_B_DATA_LEN) - 1) << GLB_GPDAC_B_DATA_POS) #define GLB_GPDAC_B_DATA_UMSK \ - (~(((1U << GLB_GPDAC_B_DATA_LEN) - 1) << GLB_GPDAC_B_DATA_POS)) + (~(((1 << GLB_GPDAC_B_DATA_LEN) - 1) << GLB_GPDAC_B_DATA_POS)) #define GLB_GPDAC_A_DATA GLB_GPDAC_A_DATA -#define GLB_GPDAC_A_DATA_POS (16U) -#define GLB_GPDAC_A_DATA_LEN (10U) +#define GLB_GPDAC_A_DATA_POS (16) +#define GLB_GPDAC_A_DATA_LEN (10) #define GLB_GPDAC_A_DATA_MSK \ - (((1U << GLB_GPDAC_A_DATA_LEN) - 1) << GLB_GPDAC_A_DATA_POS) + (((1 << GLB_GPDAC_A_DATA_LEN) - 1) << GLB_GPDAC_A_DATA_POS) #define GLB_GPDAC_A_DATA_UMSK \ - (~(((1U << GLB_GPDAC_A_DATA_LEN) - 1) << GLB_GPDAC_A_DATA_POS)) + (~(((1 << GLB_GPDAC_A_DATA_LEN) - 1) << GLB_GPDAC_A_DATA_POS)) /* 0xF00 : tzc_glb_ctrl_0 */ #define GLB_TZC_GLB_CTRL_0_OFFSET (0xF00) #define GLB_TZC_GLB_SWRST_S00_LOCK GLB_TZC_GLB_SWRST_S00_LOCK -#define GLB_TZC_GLB_SWRST_S00_LOCK_POS (0U) -#define GLB_TZC_GLB_SWRST_S00_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S00_LOCK_POS (0) +#define GLB_TZC_GLB_SWRST_S00_LOCK_LEN (1) #define GLB_TZC_GLB_SWRST_S00_LOCK_MSK \ - (((1U << GLB_TZC_GLB_SWRST_S00_LOCK_LEN) - 1) \ + (((1 << GLB_TZC_GLB_SWRST_S00_LOCK_LEN) - 1) \ << GLB_TZC_GLB_SWRST_S00_LOCK_POS) #define GLB_TZC_GLB_SWRST_S00_LOCK_UMSK \ - (~(((1U << GLB_TZC_GLB_SWRST_S00_LOCK_LEN) - 1) \ + (~(((1 << GLB_TZC_GLB_SWRST_S00_LOCK_LEN) - 1) \ << GLB_TZC_GLB_SWRST_S00_LOCK_POS)) #define GLB_TZC_GLB_SWRST_S01_LOCK GLB_TZC_GLB_SWRST_S01_LOCK -#define GLB_TZC_GLB_SWRST_S01_LOCK_POS (1U) -#define GLB_TZC_GLB_SWRST_S01_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S01_LOCK_POS (1) +#define GLB_TZC_GLB_SWRST_S01_LOCK_LEN (1) #define GLB_TZC_GLB_SWRST_S01_LOCK_MSK \ - (((1U << GLB_TZC_GLB_SWRST_S01_LOCK_LEN) - 1) \ + (((1 << GLB_TZC_GLB_SWRST_S01_LOCK_LEN) - 1) \ << GLB_TZC_GLB_SWRST_S01_LOCK_POS) #define GLB_TZC_GLB_SWRST_S01_LOCK_UMSK \ - (~(((1U << GLB_TZC_GLB_SWRST_S01_LOCK_LEN) - 1) \ + (~(((1 << GLB_TZC_GLB_SWRST_S01_LOCK_LEN) - 1) \ << GLB_TZC_GLB_SWRST_S01_LOCK_POS)) #define GLB_TZC_GLB_SWRST_S30_LOCK GLB_TZC_GLB_SWRST_S30_LOCK -#define GLB_TZC_GLB_SWRST_S30_LOCK_POS (8U) -#define GLB_TZC_GLB_SWRST_S30_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S30_LOCK_POS (8) +#define GLB_TZC_GLB_SWRST_S30_LOCK_LEN (1) #define GLB_TZC_GLB_SWRST_S30_LOCK_MSK \ - (((1U << GLB_TZC_GLB_SWRST_S30_LOCK_LEN) - 1) \ + (((1 << GLB_TZC_GLB_SWRST_S30_LOCK_LEN) - 1) \ << GLB_TZC_GLB_SWRST_S30_LOCK_POS) #define GLB_TZC_GLB_SWRST_S30_LOCK_UMSK \ - (~(((1U << GLB_TZC_GLB_SWRST_S30_LOCK_LEN) - 1) \ + (~(((1 << GLB_TZC_GLB_SWRST_S30_LOCK_LEN) - 1) \ << GLB_TZC_GLB_SWRST_S30_LOCK_POS)) #define GLB_TZC_GLB_CTRL_PWRON_RST_LOCK GLB_TZC_GLB_CTRL_PWRON_RST_LOCK -#define GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_POS (12U) -#define GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_LEN (1U) +#define GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_POS (12) +#define GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_LEN (1) #define GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_MSK \ - (((1U << GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_LEN) - 1) \ + (((1 << GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_LEN) - 1) \ << GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_POS) #define GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_UMSK \ - (~(((1U << GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_LEN) - 1) \ + (~(((1 << GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_LEN) - 1) \ << GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_POS)) #define GLB_TZC_GLB_CTRL_CPU_RESET_LOCK GLB_TZC_GLB_CTRL_CPU_RESET_LOCK -#define GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_POS (13U) -#define GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_LEN (1U) +#define GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_POS (13) +#define GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_LEN (1) #define GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_MSK \ - (((1U << GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_LEN) - 1) \ + (((1 << GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_LEN) - 1) \ << GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_POS) #define GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_UMSK \ - (~(((1U << GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_LEN) - 1) \ + (~(((1 << GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_LEN) - 1) \ << GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_POS)) #define GLB_TZC_GLB_CTRL_SYS_RESET_LOCK GLB_TZC_GLB_CTRL_SYS_RESET_LOCK -#define GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_POS (14U) -#define GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_LEN (1U) +#define GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_POS (14) +#define GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_LEN (1) #define GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_MSK \ - (((1U << GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_LEN) - 1) \ + (((1 << GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_LEN) - 1) \ << GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_POS) #define GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_UMSK \ - (~(((1U << GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_LEN) - 1) \ + (~(((1 << GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_LEN) - 1) \ << GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_POS)) #define GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK -#define GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_POS (15U) -#define GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_LEN (1U) +#define GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_POS (15) +#define GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_LEN (1) #define GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_MSK \ - (((1U << GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_LEN) - 1) \ + (((1 << GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_LEN) - 1) \ << GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_POS) #define GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_UMSK \ - (~(((1U << GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_LEN) - 1) \ + (~(((1 << GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_LEN) - 1) \ << GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_POS)) #define GLB_TZC_GLB_MISC_LOCK GLB_TZC_GLB_MISC_LOCK -#define GLB_TZC_GLB_MISC_LOCK_POS (25U) -#define GLB_TZC_GLB_MISC_LOCK_LEN (1U) +#define GLB_TZC_GLB_MISC_LOCK_POS (25) +#define GLB_TZC_GLB_MISC_LOCK_LEN (1) #define GLB_TZC_GLB_MISC_LOCK_MSK \ - (((1U << GLB_TZC_GLB_MISC_LOCK_LEN) - 1) << GLB_TZC_GLB_MISC_LOCK_POS) + (((1 << GLB_TZC_GLB_MISC_LOCK_LEN) - 1) << GLB_TZC_GLB_MISC_LOCK_POS) #define GLB_TZC_GLB_MISC_LOCK_UMSK \ - (~(((1U << GLB_TZC_GLB_MISC_LOCK_LEN) - 1) << GLB_TZC_GLB_MISC_LOCK_POS)) + (~(((1 << GLB_TZC_GLB_MISC_LOCK_LEN) - 1) << GLB_TZC_GLB_MISC_LOCK_POS)) #define GLB_TZC_GLB_SRAM_LOCK GLB_TZC_GLB_SRAM_LOCK -#define GLB_TZC_GLB_SRAM_LOCK_POS (26U) -#define GLB_TZC_GLB_SRAM_LOCK_LEN (1U) +#define GLB_TZC_GLB_SRAM_LOCK_POS (26) +#define GLB_TZC_GLB_SRAM_LOCK_LEN (1) #define GLB_TZC_GLB_SRAM_LOCK_MSK \ - (((1U << GLB_TZC_GLB_SRAM_LOCK_LEN) - 1) << GLB_TZC_GLB_SRAM_LOCK_POS) + (((1 << GLB_TZC_GLB_SRAM_LOCK_LEN) - 1) << GLB_TZC_GLB_SRAM_LOCK_POS) #define GLB_TZC_GLB_SRAM_LOCK_UMSK \ - (~(((1U << GLB_TZC_GLB_SRAM_LOCK_LEN) - 1) << GLB_TZC_GLB_SRAM_LOCK_POS)) + (~(((1 << GLB_TZC_GLB_SRAM_LOCK_LEN) - 1) << GLB_TZC_GLB_SRAM_LOCK_POS)) #define GLB_TZC_GLB_L2C_LOCK GLB_TZC_GLB_L2C_LOCK -#define GLB_TZC_GLB_L2C_LOCK_POS (27U) -#define GLB_TZC_GLB_L2C_LOCK_LEN (1U) +#define GLB_TZC_GLB_L2C_LOCK_POS (27) +#define GLB_TZC_GLB_L2C_LOCK_LEN (1) #define GLB_TZC_GLB_L2C_LOCK_MSK \ - (((1U << GLB_TZC_GLB_L2C_LOCK_LEN) - 1) << GLB_TZC_GLB_L2C_LOCK_POS) + (((1 << GLB_TZC_GLB_L2C_LOCK_LEN) - 1) << GLB_TZC_GLB_L2C_LOCK_POS) #define GLB_TZC_GLB_L2C_LOCK_UMSK \ - (~(((1U << GLB_TZC_GLB_L2C_LOCK_LEN) - 1) << GLB_TZC_GLB_L2C_LOCK_POS)) + (~(((1 << GLB_TZC_GLB_L2C_LOCK_LEN) - 1) << GLB_TZC_GLB_L2C_LOCK_POS)) #define GLB_TZC_GLB_BMX_LOCK GLB_TZC_GLB_BMX_LOCK -#define GLB_TZC_GLB_BMX_LOCK_POS (28U) -#define GLB_TZC_GLB_BMX_LOCK_LEN (1U) +#define GLB_TZC_GLB_BMX_LOCK_POS (28) +#define GLB_TZC_GLB_BMX_LOCK_LEN (1) #define GLB_TZC_GLB_BMX_LOCK_MSK \ - (((1U << GLB_TZC_GLB_BMX_LOCK_LEN) - 1) << GLB_TZC_GLB_BMX_LOCK_POS) + (((1 << GLB_TZC_GLB_BMX_LOCK_LEN) - 1) << GLB_TZC_GLB_BMX_LOCK_POS) #define GLB_TZC_GLB_BMX_LOCK_UMSK \ - (~(((1U << GLB_TZC_GLB_BMX_LOCK_LEN) - 1) << GLB_TZC_GLB_BMX_LOCK_POS)) + (~(((1 << GLB_TZC_GLB_BMX_LOCK_LEN) - 1) << GLB_TZC_GLB_BMX_LOCK_POS)) #define GLB_TZC_GLB_DBG_LOCK GLB_TZC_GLB_DBG_LOCK -#define GLB_TZC_GLB_DBG_LOCK_POS (29U) -#define GLB_TZC_GLB_DBG_LOCK_LEN (1U) +#define GLB_TZC_GLB_DBG_LOCK_POS (29) +#define GLB_TZC_GLB_DBG_LOCK_LEN (1) #define GLB_TZC_GLB_DBG_LOCK_MSK \ - (((1U << GLB_TZC_GLB_DBG_LOCK_LEN) - 1) << GLB_TZC_GLB_DBG_LOCK_POS) + (((1 << GLB_TZC_GLB_DBG_LOCK_LEN) - 1) << GLB_TZC_GLB_DBG_LOCK_POS) #define GLB_TZC_GLB_DBG_LOCK_UMSK \ - (~(((1U << GLB_TZC_GLB_DBG_LOCK_LEN) - 1) << GLB_TZC_GLB_DBG_LOCK_POS)) + (~(((1 << GLB_TZC_GLB_DBG_LOCK_LEN) - 1) << GLB_TZC_GLB_DBG_LOCK_POS)) #define GLB_TZC_GLB_MBIST_LOCK GLB_TZC_GLB_MBIST_LOCK -#define GLB_TZC_GLB_MBIST_LOCK_POS (30U) -#define GLB_TZC_GLB_MBIST_LOCK_LEN (1U) +#define GLB_TZC_GLB_MBIST_LOCK_POS (30) +#define GLB_TZC_GLB_MBIST_LOCK_LEN (1) #define GLB_TZC_GLB_MBIST_LOCK_MSK \ - (((1U << GLB_TZC_GLB_MBIST_LOCK_LEN) - 1) << GLB_TZC_GLB_MBIST_LOCK_POS) + (((1 << GLB_TZC_GLB_MBIST_LOCK_LEN) - 1) << GLB_TZC_GLB_MBIST_LOCK_POS) #define GLB_TZC_GLB_MBIST_LOCK_UMSK \ - (~(((1U << GLB_TZC_GLB_MBIST_LOCK_LEN) - 1) << GLB_TZC_GLB_MBIST_LOCK_POS)) + (~(((1 << GLB_TZC_GLB_MBIST_LOCK_LEN) - 1) << GLB_TZC_GLB_MBIST_LOCK_POS)) #define GLB_TZC_GLB_CLK_LOCK GLB_TZC_GLB_CLK_LOCK -#define GLB_TZC_GLB_CLK_LOCK_POS (31U) -#define GLB_TZC_GLB_CLK_LOCK_LEN (1U) +#define GLB_TZC_GLB_CLK_LOCK_POS (31) +#define GLB_TZC_GLB_CLK_LOCK_LEN (1) #define GLB_TZC_GLB_CLK_LOCK_MSK \ - (((1U << GLB_TZC_GLB_CLK_LOCK_LEN) - 1) << GLB_TZC_GLB_CLK_LOCK_POS) + (((1 << GLB_TZC_GLB_CLK_LOCK_LEN) - 1) << GLB_TZC_GLB_CLK_LOCK_POS) #define GLB_TZC_GLB_CLK_LOCK_UMSK \ - (~(((1U << GLB_TZC_GLB_CLK_LOCK_LEN) - 1) << GLB_TZC_GLB_CLK_LOCK_POS)) + (~(((1 << GLB_TZC_GLB_CLK_LOCK_LEN) - 1) << GLB_TZC_GLB_CLK_LOCK_POS)) /* 0xF04 : tzc_glb_ctrl_1 */ #define GLB_TZC_GLB_CTRL_1_OFFSET (0xF04) #define GLB_TZC_GLB_SWRST_S20_LOCK GLB_TZC_GLB_SWRST_S20_LOCK -#define GLB_TZC_GLB_SWRST_S20_LOCK_POS (0U) -#define GLB_TZC_GLB_SWRST_S20_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S20_LOCK_POS (0) +#define GLB_TZC_GLB_SWRST_S20_LOCK_LEN (1) #define GLB_TZC_GLB_SWRST_S20_LOCK_MSK \ - (((1U << GLB_TZC_GLB_SWRST_S20_LOCK_LEN) - 1) \ + (((1 << GLB_TZC_GLB_SWRST_S20_LOCK_LEN) - 1) \ << GLB_TZC_GLB_SWRST_S20_LOCK_POS) #define GLB_TZC_GLB_SWRST_S20_LOCK_UMSK \ - (~(((1U << GLB_TZC_GLB_SWRST_S20_LOCK_LEN) - 1) \ + (~(((1 << GLB_TZC_GLB_SWRST_S20_LOCK_LEN) - 1) \ << GLB_TZC_GLB_SWRST_S20_LOCK_POS)) #define GLB_TZC_GLB_SWRST_S21_LOCK GLB_TZC_GLB_SWRST_S21_LOCK -#define GLB_TZC_GLB_SWRST_S21_LOCK_POS (1U) -#define GLB_TZC_GLB_SWRST_S21_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S21_LOCK_POS (1) +#define GLB_TZC_GLB_SWRST_S21_LOCK_LEN (1) #define GLB_TZC_GLB_SWRST_S21_LOCK_MSK \ - (((1U << GLB_TZC_GLB_SWRST_S21_LOCK_LEN) - 1) \ + (((1 << GLB_TZC_GLB_SWRST_S21_LOCK_LEN) - 1) \ << GLB_TZC_GLB_SWRST_S21_LOCK_POS) #define GLB_TZC_GLB_SWRST_S21_LOCK_UMSK \ - (~(((1U << GLB_TZC_GLB_SWRST_S21_LOCK_LEN) - 1) \ + (~(((1 << GLB_TZC_GLB_SWRST_S21_LOCK_LEN) - 1) \ << GLB_TZC_GLB_SWRST_S21_LOCK_POS)) #define GLB_TZC_GLB_SWRST_S22_LOCK GLB_TZC_GLB_SWRST_S22_LOCK -#define GLB_TZC_GLB_SWRST_S22_LOCK_POS (2U) -#define GLB_TZC_GLB_SWRST_S22_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S22_LOCK_POS (2) +#define GLB_TZC_GLB_SWRST_S22_LOCK_LEN (1) #define GLB_TZC_GLB_SWRST_S22_LOCK_MSK \ - (((1U << GLB_TZC_GLB_SWRST_S22_LOCK_LEN) - 1) \ + (((1 << GLB_TZC_GLB_SWRST_S22_LOCK_LEN) - 1) \ << GLB_TZC_GLB_SWRST_S22_LOCK_POS) #define GLB_TZC_GLB_SWRST_S22_LOCK_UMSK \ - (~(((1U << GLB_TZC_GLB_SWRST_S22_LOCK_LEN) - 1) \ + (~(((1 << GLB_TZC_GLB_SWRST_S22_LOCK_LEN) - 1) \ << GLB_TZC_GLB_SWRST_S22_LOCK_POS)) #define GLB_TZC_GLB_SWRST_S23_LOCK GLB_TZC_GLB_SWRST_S23_LOCK -#define GLB_TZC_GLB_SWRST_S23_LOCK_POS (3U) -#define GLB_TZC_GLB_SWRST_S23_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S23_LOCK_POS (3) +#define GLB_TZC_GLB_SWRST_S23_LOCK_LEN (1) #define GLB_TZC_GLB_SWRST_S23_LOCK_MSK \ - (((1U << GLB_TZC_GLB_SWRST_S23_LOCK_LEN) - 1) \ + (((1 << GLB_TZC_GLB_SWRST_S23_LOCK_LEN) - 1) \ << GLB_TZC_GLB_SWRST_S23_LOCK_POS) #define GLB_TZC_GLB_SWRST_S23_LOCK_UMSK \ - (~(((1U << GLB_TZC_GLB_SWRST_S23_LOCK_LEN) - 1) \ + (~(((1 << GLB_TZC_GLB_SWRST_S23_LOCK_LEN) - 1) \ << GLB_TZC_GLB_SWRST_S23_LOCK_POS)) #define GLB_TZC_GLB_SWRST_S24_LOCK GLB_TZC_GLB_SWRST_S24_LOCK -#define GLB_TZC_GLB_SWRST_S24_LOCK_POS (4U) -#define GLB_TZC_GLB_SWRST_S24_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S24_LOCK_POS (4) +#define GLB_TZC_GLB_SWRST_S24_LOCK_LEN (1) #define GLB_TZC_GLB_SWRST_S24_LOCK_MSK \ - (((1U << GLB_TZC_GLB_SWRST_S24_LOCK_LEN) - 1) \ + (((1 << GLB_TZC_GLB_SWRST_S24_LOCK_LEN) - 1) \ << GLB_TZC_GLB_SWRST_S24_LOCK_POS) #define GLB_TZC_GLB_SWRST_S24_LOCK_UMSK \ - (~(((1U << GLB_TZC_GLB_SWRST_S24_LOCK_LEN) - 1) \ + (~(((1 << GLB_TZC_GLB_SWRST_S24_LOCK_LEN) - 1) \ << GLB_TZC_GLB_SWRST_S24_LOCK_POS)) #define GLB_TZC_GLB_SWRST_S25_LOCK GLB_TZC_GLB_SWRST_S25_LOCK -#define GLB_TZC_GLB_SWRST_S25_LOCK_POS (5U) -#define GLB_TZC_GLB_SWRST_S25_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S25_LOCK_POS (5) +#define GLB_TZC_GLB_SWRST_S25_LOCK_LEN (1) #define GLB_TZC_GLB_SWRST_S25_LOCK_MSK \ - (((1U << GLB_TZC_GLB_SWRST_S25_LOCK_LEN) - 1) \ + (((1 << GLB_TZC_GLB_SWRST_S25_LOCK_LEN) - 1) \ << GLB_TZC_GLB_SWRST_S25_LOCK_POS) #define GLB_TZC_GLB_SWRST_S25_LOCK_UMSK \ - (~(((1U << GLB_TZC_GLB_SWRST_S25_LOCK_LEN) - 1) \ + (~(((1 << GLB_TZC_GLB_SWRST_S25_LOCK_LEN) - 1) \ << GLB_TZC_GLB_SWRST_S25_LOCK_POS)) #define GLB_TZC_GLB_SWRST_S26_LOCK GLB_TZC_GLB_SWRST_S26_LOCK -#define GLB_TZC_GLB_SWRST_S26_LOCK_POS (6U) -#define GLB_TZC_GLB_SWRST_S26_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S26_LOCK_POS (6) +#define GLB_TZC_GLB_SWRST_S26_LOCK_LEN (1) #define GLB_TZC_GLB_SWRST_S26_LOCK_MSK \ - (((1U << GLB_TZC_GLB_SWRST_S26_LOCK_LEN) - 1) \ + (((1 << GLB_TZC_GLB_SWRST_S26_LOCK_LEN) - 1) \ << GLB_TZC_GLB_SWRST_S26_LOCK_POS) #define GLB_TZC_GLB_SWRST_S26_LOCK_UMSK \ - (~(((1U << GLB_TZC_GLB_SWRST_S26_LOCK_LEN) - 1) \ + (~(((1 << GLB_TZC_GLB_SWRST_S26_LOCK_LEN) - 1) \ << GLB_TZC_GLB_SWRST_S26_LOCK_POS)) #define GLB_TZC_GLB_SWRST_S27_LOCK GLB_TZC_GLB_SWRST_S27_LOCK -#define GLB_TZC_GLB_SWRST_S27_LOCK_POS (7U) -#define GLB_TZC_GLB_SWRST_S27_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S27_LOCK_POS (7) +#define GLB_TZC_GLB_SWRST_S27_LOCK_LEN (1) #define GLB_TZC_GLB_SWRST_S27_LOCK_MSK \ - (((1U << GLB_TZC_GLB_SWRST_S27_LOCK_LEN) - 1) \ + (((1 << GLB_TZC_GLB_SWRST_S27_LOCK_LEN) - 1) \ << GLB_TZC_GLB_SWRST_S27_LOCK_POS) #define GLB_TZC_GLB_SWRST_S27_LOCK_UMSK \ - (~(((1U << GLB_TZC_GLB_SWRST_S27_LOCK_LEN) - 1) \ + (~(((1 << GLB_TZC_GLB_SWRST_S27_LOCK_LEN) - 1) \ << GLB_TZC_GLB_SWRST_S27_LOCK_POS)) #define GLB_TZC_GLB_SWRST_S28_LOCK GLB_TZC_GLB_SWRST_S28_LOCK -#define GLB_TZC_GLB_SWRST_S28_LOCK_POS (8U) -#define GLB_TZC_GLB_SWRST_S28_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S28_LOCK_POS (8) +#define GLB_TZC_GLB_SWRST_S28_LOCK_LEN (1) #define GLB_TZC_GLB_SWRST_S28_LOCK_MSK \ - (((1U << GLB_TZC_GLB_SWRST_S28_LOCK_LEN) - 1) \ + (((1 << GLB_TZC_GLB_SWRST_S28_LOCK_LEN) - 1) \ << GLB_TZC_GLB_SWRST_S28_LOCK_POS) #define GLB_TZC_GLB_SWRST_S28_LOCK_UMSK \ - (~(((1U << GLB_TZC_GLB_SWRST_S28_LOCK_LEN) - 1) \ + (~(((1 << GLB_TZC_GLB_SWRST_S28_LOCK_LEN) - 1) \ << GLB_TZC_GLB_SWRST_S28_LOCK_POS)) #define GLB_TZC_GLB_SWRST_S29_LOCK GLB_TZC_GLB_SWRST_S29_LOCK -#define GLB_TZC_GLB_SWRST_S29_LOCK_POS (9U) -#define GLB_TZC_GLB_SWRST_S29_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S29_LOCK_POS (9) +#define GLB_TZC_GLB_SWRST_S29_LOCK_LEN (1) #define GLB_TZC_GLB_SWRST_S29_LOCK_MSK \ - (((1U << GLB_TZC_GLB_SWRST_S29_LOCK_LEN) - 1) \ + (((1 << GLB_TZC_GLB_SWRST_S29_LOCK_LEN) - 1) \ << GLB_TZC_GLB_SWRST_S29_LOCK_POS) #define GLB_TZC_GLB_SWRST_S29_LOCK_UMSK \ - (~(((1U << GLB_TZC_GLB_SWRST_S29_LOCK_LEN) - 1) \ + (~(((1 << GLB_TZC_GLB_SWRST_S29_LOCK_LEN) - 1) \ << GLB_TZC_GLB_SWRST_S29_LOCK_POS)) #define GLB_TZC_GLB_SWRST_S2A_LOCK GLB_TZC_GLB_SWRST_S2A_LOCK -#define GLB_TZC_GLB_SWRST_S2A_LOCK_POS (10U) -#define GLB_TZC_GLB_SWRST_S2A_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S2A_LOCK_POS (10) +#define GLB_TZC_GLB_SWRST_S2A_LOCK_LEN (1) #define GLB_TZC_GLB_SWRST_S2A_LOCK_MSK \ - (((1U << GLB_TZC_GLB_SWRST_S2A_LOCK_LEN) - 1) \ + (((1 << GLB_TZC_GLB_SWRST_S2A_LOCK_LEN) - 1) \ << GLB_TZC_GLB_SWRST_S2A_LOCK_POS) #define GLB_TZC_GLB_SWRST_S2A_LOCK_UMSK \ - (~(((1U << GLB_TZC_GLB_SWRST_S2A_LOCK_LEN) - 1) \ + (~(((1 << GLB_TZC_GLB_SWRST_S2A_LOCK_LEN) - 1) \ << GLB_TZC_GLB_SWRST_S2A_LOCK_POS)) #define GLB_TZC_GLB_SWRST_S2B_LOCK GLB_TZC_GLB_SWRST_S2B_LOCK -#define GLB_TZC_GLB_SWRST_S2B_LOCK_POS (11U) -#define GLB_TZC_GLB_SWRST_S2B_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S2B_LOCK_POS (11) +#define GLB_TZC_GLB_SWRST_S2B_LOCK_LEN (1) #define GLB_TZC_GLB_SWRST_S2B_LOCK_MSK \ - (((1U << GLB_TZC_GLB_SWRST_S2B_LOCK_LEN) - 1) \ + (((1 << GLB_TZC_GLB_SWRST_S2B_LOCK_LEN) - 1) \ << GLB_TZC_GLB_SWRST_S2B_LOCK_POS) #define GLB_TZC_GLB_SWRST_S2B_LOCK_UMSK \ - (~(((1U << GLB_TZC_GLB_SWRST_S2B_LOCK_LEN) - 1) \ + (~(((1 << GLB_TZC_GLB_SWRST_S2B_LOCK_LEN) - 1) \ << GLB_TZC_GLB_SWRST_S2B_LOCK_POS)) #define GLB_TZC_GLB_SWRST_S2C_LOCK GLB_TZC_GLB_SWRST_S2C_LOCK -#define GLB_TZC_GLB_SWRST_S2C_LOCK_POS (12U) -#define GLB_TZC_GLB_SWRST_S2C_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S2C_LOCK_POS (12) +#define GLB_TZC_GLB_SWRST_S2C_LOCK_LEN (1) #define GLB_TZC_GLB_SWRST_S2C_LOCK_MSK \ - (((1U << GLB_TZC_GLB_SWRST_S2C_LOCK_LEN) - 1) \ + (((1 << GLB_TZC_GLB_SWRST_S2C_LOCK_LEN) - 1) \ << GLB_TZC_GLB_SWRST_S2C_LOCK_POS) #define GLB_TZC_GLB_SWRST_S2C_LOCK_UMSK \ - (~(((1U << GLB_TZC_GLB_SWRST_S2C_LOCK_LEN) - 1) \ + (~(((1 << GLB_TZC_GLB_SWRST_S2C_LOCK_LEN) - 1) \ << GLB_TZC_GLB_SWRST_S2C_LOCK_POS)) #define GLB_TZC_GLB_SWRST_S2D_LOCK GLB_TZC_GLB_SWRST_S2D_LOCK -#define GLB_TZC_GLB_SWRST_S2D_LOCK_POS (13U) -#define GLB_TZC_GLB_SWRST_S2D_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S2D_LOCK_POS (13) +#define GLB_TZC_GLB_SWRST_S2D_LOCK_LEN (1) #define GLB_TZC_GLB_SWRST_S2D_LOCK_MSK \ - (((1U << GLB_TZC_GLB_SWRST_S2D_LOCK_LEN) - 1) \ + (((1 << GLB_TZC_GLB_SWRST_S2D_LOCK_LEN) - 1) \ << GLB_TZC_GLB_SWRST_S2D_LOCK_POS) #define GLB_TZC_GLB_SWRST_S2D_LOCK_UMSK \ - (~(((1U << GLB_TZC_GLB_SWRST_S2D_LOCK_LEN) - 1) \ + (~(((1 << GLB_TZC_GLB_SWRST_S2D_LOCK_LEN) - 1) \ << GLB_TZC_GLB_SWRST_S2D_LOCK_POS)) #define GLB_TZC_GLB_SWRST_S2E_LOCK GLB_TZC_GLB_SWRST_S2E_LOCK -#define GLB_TZC_GLB_SWRST_S2E_LOCK_POS (14U) -#define GLB_TZC_GLB_SWRST_S2E_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S2E_LOCK_POS (14) +#define GLB_TZC_GLB_SWRST_S2E_LOCK_LEN (1) #define GLB_TZC_GLB_SWRST_S2E_LOCK_MSK \ - (((1U << GLB_TZC_GLB_SWRST_S2E_LOCK_LEN) - 1) \ + (((1 << GLB_TZC_GLB_SWRST_S2E_LOCK_LEN) - 1) \ << GLB_TZC_GLB_SWRST_S2E_LOCK_POS) #define GLB_TZC_GLB_SWRST_S2E_LOCK_UMSK \ - (~(((1U << GLB_TZC_GLB_SWRST_S2E_LOCK_LEN) - 1) \ + (~(((1 << GLB_TZC_GLB_SWRST_S2E_LOCK_LEN) - 1) \ << GLB_TZC_GLB_SWRST_S2E_LOCK_POS)) #define GLB_TZC_GLB_SWRST_S2F_LOCK GLB_TZC_GLB_SWRST_S2F_LOCK -#define GLB_TZC_GLB_SWRST_S2F_LOCK_POS (15U) -#define GLB_TZC_GLB_SWRST_S2F_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S2F_LOCK_POS (15) +#define GLB_TZC_GLB_SWRST_S2F_LOCK_LEN (1) #define GLB_TZC_GLB_SWRST_S2F_LOCK_MSK \ - (((1U << GLB_TZC_GLB_SWRST_S2F_LOCK_LEN) - 1) \ + (((1 << GLB_TZC_GLB_SWRST_S2F_LOCK_LEN) - 1) \ << GLB_TZC_GLB_SWRST_S2F_LOCK_POS) #define GLB_TZC_GLB_SWRST_S2F_LOCK_UMSK \ - (~(((1U << GLB_TZC_GLB_SWRST_S2F_LOCK_LEN) - 1) \ + (~(((1 << GLB_TZC_GLB_SWRST_S2F_LOCK_LEN) - 1) \ << GLB_TZC_GLB_SWRST_S2F_LOCK_POS)) #define GLB_TZC_GLB_SWRST_S10_LOCK GLB_TZC_GLB_SWRST_S10_LOCK -#define GLB_TZC_GLB_SWRST_S10_LOCK_POS (16U) -#define GLB_TZC_GLB_SWRST_S10_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S10_LOCK_POS (16) +#define GLB_TZC_GLB_SWRST_S10_LOCK_LEN (1) #define GLB_TZC_GLB_SWRST_S10_LOCK_MSK \ - (((1U << GLB_TZC_GLB_SWRST_S10_LOCK_LEN) - 1) \ + (((1 << GLB_TZC_GLB_SWRST_S10_LOCK_LEN) - 1) \ << GLB_TZC_GLB_SWRST_S10_LOCK_POS) #define GLB_TZC_GLB_SWRST_S10_LOCK_UMSK \ - (~(((1U << GLB_TZC_GLB_SWRST_S10_LOCK_LEN) - 1) \ + (~(((1 << GLB_TZC_GLB_SWRST_S10_LOCK_LEN) - 1) \ << GLB_TZC_GLB_SWRST_S10_LOCK_POS)) #define GLB_TZC_GLB_SWRST_S11_LOCK GLB_TZC_GLB_SWRST_S11_LOCK -#define GLB_TZC_GLB_SWRST_S11_LOCK_POS (17U) -#define GLB_TZC_GLB_SWRST_S11_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S11_LOCK_POS (17) +#define GLB_TZC_GLB_SWRST_S11_LOCK_LEN (1) #define GLB_TZC_GLB_SWRST_S11_LOCK_MSK \ - (((1U << GLB_TZC_GLB_SWRST_S11_LOCK_LEN) - 1) \ + (((1 << GLB_TZC_GLB_SWRST_S11_LOCK_LEN) - 1) \ << GLB_TZC_GLB_SWRST_S11_LOCK_POS) #define GLB_TZC_GLB_SWRST_S11_LOCK_UMSK \ - (~(((1U << GLB_TZC_GLB_SWRST_S11_LOCK_LEN) - 1) \ + (~(((1 << GLB_TZC_GLB_SWRST_S11_LOCK_LEN) - 1) \ << GLB_TZC_GLB_SWRST_S11_LOCK_POS)) #define GLB_TZC_GLB_SWRST_S12_LOCK GLB_TZC_GLB_SWRST_S12_LOCK -#define GLB_TZC_GLB_SWRST_S12_LOCK_POS (18U) -#define GLB_TZC_GLB_SWRST_S12_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S12_LOCK_POS (18) +#define GLB_TZC_GLB_SWRST_S12_LOCK_LEN (1) #define GLB_TZC_GLB_SWRST_S12_LOCK_MSK \ - (((1U << GLB_TZC_GLB_SWRST_S12_LOCK_LEN) - 1) \ + (((1 << GLB_TZC_GLB_SWRST_S12_LOCK_LEN) - 1) \ << GLB_TZC_GLB_SWRST_S12_LOCK_POS) #define GLB_TZC_GLB_SWRST_S12_LOCK_UMSK \ - (~(((1U << GLB_TZC_GLB_SWRST_S12_LOCK_LEN) - 1) \ + (~(((1 << GLB_TZC_GLB_SWRST_S12_LOCK_LEN) - 1) \ << GLB_TZC_GLB_SWRST_S12_LOCK_POS)) #define GLB_TZC_GLB_SWRST_S13_LOCK GLB_TZC_GLB_SWRST_S13_LOCK -#define GLB_TZC_GLB_SWRST_S13_LOCK_POS (19U) -#define GLB_TZC_GLB_SWRST_S13_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S13_LOCK_POS (19) +#define GLB_TZC_GLB_SWRST_S13_LOCK_LEN (1) #define GLB_TZC_GLB_SWRST_S13_LOCK_MSK \ - (((1U << GLB_TZC_GLB_SWRST_S13_LOCK_LEN) - 1) \ + (((1 << GLB_TZC_GLB_SWRST_S13_LOCK_LEN) - 1) \ << GLB_TZC_GLB_SWRST_S13_LOCK_POS) #define GLB_TZC_GLB_SWRST_S13_LOCK_UMSK \ - (~(((1U << GLB_TZC_GLB_SWRST_S13_LOCK_LEN) - 1) \ + (~(((1 << GLB_TZC_GLB_SWRST_S13_LOCK_LEN) - 1) \ << GLB_TZC_GLB_SWRST_S13_LOCK_POS)) #define GLB_TZC_GLB_SWRST_S14_LOCK GLB_TZC_GLB_SWRST_S14_LOCK -#define GLB_TZC_GLB_SWRST_S14_LOCK_POS (20U) -#define GLB_TZC_GLB_SWRST_S14_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S14_LOCK_POS (20) +#define GLB_TZC_GLB_SWRST_S14_LOCK_LEN (1) #define GLB_TZC_GLB_SWRST_S14_LOCK_MSK \ - (((1U << GLB_TZC_GLB_SWRST_S14_LOCK_LEN) - 1) \ + (((1 << GLB_TZC_GLB_SWRST_S14_LOCK_LEN) - 1) \ << GLB_TZC_GLB_SWRST_S14_LOCK_POS) #define GLB_TZC_GLB_SWRST_S14_LOCK_UMSK \ - (~(((1U << GLB_TZC_GLB_SWRST_S14_LOCK_LEN) - 1) \ + (~(((1 << GLB_TZC_GLB_SWRST_S14_LOCK_LEN) - 1) \ << GLB_TZC_GLB_SWRST_S14_LOCK_POS)) #define GLB_TZC_GLB_SWRST_S15_LOCK GLB_TZC_GLB_SWRST_S15_LOCK -#define GLB_TZC_GLB_SWRST_S15_LOCK_POS (21U) -#define GLB_TZC_GLB_SWRST_S15_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S15_LOCK_POS (21) +#define GLB_TZC_GLB_SWRST_S15_LOCK_LEN (1) #define GLB_TZC_GLB_SWRST_S15_LOCK_MSK \ - (((1U << GLB_TZC_GLB_SWRST_S15_LOCK_LEN) - 1) \ + (((1 << GLB_TZC_GLB_SWRST_S15_LOCK_LEN) - 1) \ << GLB_TZC_GLB_SWRST_S15_LOCK_POS) #define GLB_TZC_GLB_SWRST_S15_LOCK_UMSK \ - (~(((1U << GLB_TZC_GLB_SWRST_S15_LOCK_LEN) - 1) \ + (~(((1 << GLB_TZC_GLB_SWRST_S15_LOCK_LEN) - 1) \ << GLB_TZC_GLB_SWRST_S15_LOCK_POS)) #define GLB_TZC_GLB_SWRST_S16_LOCK GLB_TZC_GLB_SWRST_S16_LOCK -#define GLB_TZC_GLB_SWRST_S16_LOCK_POS (22U) -#define GLB_TZC_GLB_SWRST_S16_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S16_LOCK_POS (22) +#define GLB_TZC_GLB_SWRST_S16_LOCK_LEN (1) #define GLB_TZC_GLB_SWRST_S16_LOCK_MSK \ - (((1U << GLB_TZC_GLB_SWRST_S16_LOCK_LEN) - 1) \ + (((1 << GLB_TZC_GLB_SWRST_S16_LOCK_LEN) - 1) \ << GLB_TZC_GLB_SWRST_S16_LOCK_POS) #define GLB_TZC_GLB_SWRST_S16_LOCK_UMSK \ - (~(((1U << GLB_TZC_GLB_SWRST_S16_LOCK_LEN) - 1) \ + (~(((1 << GLB_TZC_GLB_SWRST_S16_LOCK_LEN) - 1) \ << GLB_TZC_GLB_SWRST_S16_LOCK_POS)) #define GLB_TZC_GLB_SWRST_S17_LOCK GLB_TZC_GLB_SWRST_S17_LOCK -#define GLB_TZC_GLB_SWRST_S17_LOCK_POS (23U) -#define GLB_TZC_GLB_SWRST_S17_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S17_LOCK_POS (23) +#define GLB_TZC_GLB_SWRST_S17_LOCK_LEN (1) #define GLB_TZC_GLB_SWRST_S17_LOCK_MSK \ - (((1U << GLB_TZC_GLB_SWRST_S17_LOCK_LEN) - 1) \ + (((1 << GLB_TZC_GLB_SWRST_S17_LOCK_LEN) - 1) \ << GLB_TZC_GLB_SWRST_S17_LOCK_POS) #define GLB_TZC_GLB_SWRST_S17_LOCK_UMSK \ - (~(((1U << GLB_TZC_GLB_SWRST_S17_LOCK_LEN) - 1) \ + (~(((1 << GLB_TZC_GLB_SWRST_S17_LOCK_LEN) - 1) \ << GLB_TZC_GLB_SWRST_S17_LOCK_POS)) #define GLB_TZC_GLB_SWRST_S18_LOCK GLB_TZC_GLB_SWRST_S18_LOCK -#define GLB_TZC_GLB_SWRST_S18_LOCK_POS (24U) -#define GLB_TZC_GLB_SWRST_S18_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S18_LOCK_POS (24) +#define GLB_TZC_GLB_SWRST_S18_LOCK_LEN (1) #define GLB_TZC_GLB_SWRST_S18_LOCK_MSK \ - (((1U << GLB_TZC_GLB_SWRST_S18_LOCK_LEN) - 1) \ + (((1 << GLB_TZC_GLB_SWRST_S18_LOCK_LEN) - 1) \ << GLB_TZC_GLB_SWRST_S18_LOCK_POS) #define GLB_TZC_GLB_SWRST_S18_LOCK_UMSK \ - (~(((1U << GLB_TZC_GLB_SWRST_S18_LOCK_LEN) - 1) \ + (~(((1 << GLB_TZC_GLB_SWRST_S18_LOCK_LEN) - 1) \ << GLB_TZC_GLB_SWRST_S18_LOCK_POS)) #define GLB_TZC_GLB_SWRST_S19_LOCK GLB_TZC_GLB_SWRST_S19_LOCK -#define GLB_TZC_GLB_SWRST_S19_LOCK_POS (25U) -#define GLB_TZC_GLB_SWRST_S19_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S19_LOCK_POS (25) +#define GLB_TZC_GLB_SWRST_S19_LOCK_LEN (1) #define GLB_TZC_GLB_SWRST_S19_LOCK_MSK \ - (((1U << GLB_TZC_GLB_SWRST_S19_LOCK_LEN) - 1) \ + (((1 << GLB_TZC_GLB_SWRST_S19_LOCK_LEN) - 1) \ << GLB_TZC_GLB_SWRST_S19_LOCK_POS) #define GLB_TZC_GLB_SWRST_S19_LOCK_UMSK \ - (~(((1U << GLB_TZC_GLB_SWRST_S19_LOCK_LEN) - 1) \ + (~(((1 << GLB_TZC_GLB_SWRST_S19_LOCK_LEN) - 1) \ << GLB_TZC_GLB_SWRST_S19_LOCK_POS)) #define GLB_TZC_GLB_SWRST_S1A_LOCK GLB_TZC_GLB_SWRST_S1A_LOCK -#define GLB_TZC_GLB_SWRST_S1A_LOCK_POS (26U) -#define GLB_TZC_GLB_SWRST_S1A_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S1A_LOCK_POS (26) +#define GLB_TZC_GLB_SWRST_S1A_LOCK_LEN (1) #define GLB_TZC_GLB_SWRST_S1A_LOCK_MSK \ - (((1U << GLB_TZC_GLB_SWRST_S1A_LOCK_LEN) - 1) \ + (((1 << GLB_TZC_GLB_SWRST_S1A_LOCK_LEN) - 1) \ << GLB_TZC_GLB_SWRST_S1A_LOCK_POS) #define GLB_TZC_GLB_SWRST_S1A_LOCK_UMSK \ - (~(((1U << GLB_TZC_GLB_SWRST_S1A_LOCK_LEN) - 1) \ + (~(((1 << GLB_TZC_GLB_SWRST_S1A_LOCK_LEN) - 1) \ << GLB_TZC_GLB_SWRST_S1A_LOCK_POS)) #define GLB_TZC_GLB_SWRST_S1B_LOCK GLB_TZC_GLB_SWRST_S1B_LOCK -#define GLB_TZC_GLB_SWRST_S1B_LOCK_POS (27U) -#define GLB_TZC_GLB_SWRST_S1B_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S1B_LOCK_POS (27) +#define GLB_TZC_GLB_SWRST_S1B_LOCK_LEN (1) #define GLB_TZC_GLB_SWRST_S1B_LOCK_MSK \ - (((1U << GLB_TZC_GLB_SWRST_S1B_LOCK_LEN) - 1) \ + (((1 << GLB_TZC_GLB_SWRST_S1B_LOCK_LEN) - 1) \ << GLB_TZC_GLB_SWRST_S1B_LOCK_POS) #define GLB_TZC_GLB_SWRST_S1B_LOCK_UMSK \ - (~(((1U << GLB_TZC_GLB_SWRST_S1B_LOCK_LEN) - 1) \ + (~(((1 << GLB_TZC_GLB_SWRST_S1B_LOCK_LEN) - 1) \ << GLB_TZC_GLB_SWRST_S1B_LOCK_POS)) #define GLB_TZC_GLB_SWRST_S1C_LOCK GLB_TZC_GLB_SWRST_S1C_LOCK -#define GLB_TZC_GLB_SWRST_S1C_LOCK_POS (28U) -#define GLB_TZC_GLB_SWRST_S1C_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S1C_LOCK_POS (28) +#define GLB_TZC_GLB_SWRST_S1C_LOCK_LEN (1) #define GLB_TZC_GLB_SWRST_S1C_LOCK_MSK \ - (((1U << GLB_TZC_GLB_SWRST_S1C_LOCK_LEN) - 1) \ + (((1 << GLB_TZC_GLB_SWRST_S1C_LOCK_LEN) - 1) \ << GLB_TZC_GLB_SWRST_S1C_LOCK_POS) #define GLB_TZC_GLB_SWRST_S1C_LOCK_UMSK \ - (~(((1U << GLB_TZC_GLB_SWRST_S1C_LOCK_LEN) - 1) \ + (~(((1 << GLB_TZC_GLB_SWRST_S1C_LOCK_LEN) - 1) \ << GLB_TZC_GLB_SWRST_S1C_LOCK_POS)) #define GLB_TZC_GLB_SWRST_S1D_LOCK GLB_TZC_GLB_SWRST_S1D_LOCK -#define GLB_TZC_GLB_SWRST_S1D_LOCK_POS (29U) -#define GLB_TZC_GLB_SWRST_S1D_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S1D_LOCK_POS (29) +#define GLB_TZC_GLB_SWRST_S1D_LOCK_LEN (1) #define GLB_TZC_GLB_SWRST_S1D_LOCK_MSK \ - (((1U << GLB_TZC_GLB_SWRST_S1D_LOCK_LEN) - 1) \ + (((1 << GLB_TZC_GLB_SWRST_S1D_LOCK_LEN) - 1) \ << GLB_TZC_GLB_SWRST_S1D_LOCK_POS) #define GLB_TZC_GLB_SWRST_S1D_LOCK_UMSK \ - (~(((1U << GLB_TZC_GLB_SWRST_S1D_LOCK_LEN) - 1) \ + (~(((1 << GLB_TZC_GLB_SWRST_S1D_LOCK_LEN) - 1) \ << GLB_TZC_GLB_SWRST_S1D_LOCK_POS)) #define GLB_TZC_GLB_SWRST_S1E_LOCK GLB_TZC_GLB_SWRST_S1E_LOCK -#define GLB_TZC_GLB_SWRST_S1E_LOCK_POS (30U) -#define GLB_TZC_GLB_SWRST_S1E_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S1E_LOCK_POS (30) +#define GLB_TZC_GLB_SWRST_S1E_LOCK_LEN (1) #define GLB_TZC_GLB_SWRST_S1E_LOCK_MSK \ - (((1U << GLB_TZC_GLB_SWRST_S1E_LOCK_LEN) - 1) \ + (((1 << GLB_TZC_GLB_SWRST_S1E_LOCK_LEN) - 1) \ << GLB_TZC_GLB_SWRST_S1E_LOCK_POS) #define GLB_TZC_GLB_SWRST_S1E_LOCK_UMSK \ - (~(((1U << GLB_TZC_GLB_SWRST_S1E_LOCK_LEN) - 1) \ + (~(((1 << GLB_TZC_GLB_SWRST_S1E_LOCK_LEN) - 1) \ << GLB_TZC_GLB_SWRST_S1E_LOCK_POS)) #define GLB_TZC_GLB_SWRST_S1F_LOCK GLB_TZC_GLB_SWRST_S1F_LOCK -#define GLB_TZC_GLB_SWRST_S1F_LOCK_POS (31U) -#define GLB_TZC_GLB_SWRST_S1F_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S1F_LOCK_POS (31) +#define GLB_TZC_GLB_SWRST_S1F_LOCK_LEN (1) #define GLB_TZC_GLB_SWRST_S1F_LOCK_MSK \ - (((1U << GLB_TZC_GLB_SWRST_S1F_LOCK_LEN) - 1) \ + (((1 << GLB_TZC_GLB_SWRST_S1F_LOCK_LEN) - 1) \ << GLB_TZC_GLB_SWRST_S1F_LOCK_POS) #define GLB_TZC_GLB_SWRST_S1F_LOCK_UMSK \ - (~(((1U << GLB_TZC_GLB_SWRST_S1F_LOCK_LEN) - 1) \ + (~(((1 << GLB_TZC_GLB_SWRST_S1F_LOCK_LEN) - 1) \ << GLB_TZC_GLB_SWRST_S1F_LOCK_POS)) /* 0xF08 : tzc_glb_ctrl_2 */ #define GLB_TZC_GLB_CTRL_2_OFFSET (0xF08) #define GLB_TZC_GLB_GPIO_0_LOCK GLB_TZC_GLB_GPIO_0_LOCK -#define GLB_TZC_GLB_GPIO_0_LOCK_POS (0U) -#define GLB_TZC_GLB_GPIO_0_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_0_LOCK_POS (0) +#define GLB_TZC_GLB_GPIO_0_LOCK_LEN (1) #define GLB_TZC_GLB_GPIO_0_LOCK_MSK \ - (((1U << GLB_TZC_GLB_GPIO_0_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_0_LOCK_POS) + (((1 << GLB_TZC_GLB_GPIO_0_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_0_LOCK_POS) #define GLB_TZC_GLB_GPIO_0_LOCK_UMSK \ - (~(((1U << GLB_TZC_GLB_GPIO_0_LOCK_LEN) - 1) \ - << GLB_TZC_GLB_GPIO_0_LOCK_POS)) + (~(((1 << GLB_TZC_GLB_GPIO_0_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_0_LOCK_POS)) #define GLB_TZC_GLB_GPIO_1_LOCK GLB_TZC_GLB_GPIO_1_LOCK -#define GLB_TZC_GLB_GPIO_1_LOCK_POS (1U) -#define GLB_TZC_GLB_GPIO_1_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_1_LOCK_POS (1) +#define GLB_TZC_GLB_GPIO_1_LOCK_LEN (1) #define GLB_TZC_GLB_GPIO_1_LOCK_MSK \ - (((1U << GLB_TZC_GLB_GPIO_1_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_1_LOCK_POS) + (((1 << GLB_TZC_GLB_GPIO_1_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_1_LOCK_POS) #define GLB_TZC_GLB_GPIO_1_LOCK_UMSK \ - (~(((1U << GLB_TZC_GLB_GPIO_1_LOCK_LEN) - 1) \ - << GLB_TZC_GLB_GPIO_1_LOCK_POS)) + (~(((1 << GLB_TZC_GLB_GPIO_1_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_1_LOCK_POS)) #define GLB_TZC_GLB_GPIO_2_LOCK GLB_TZC_GLB_GPIO_2_LOCK -#define GLB_TZC_GLB_GPIO_2_LOCK_POS (2U) -#define GLB_TZC_GLB_GPIO_2_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_2_LOCK_POS (2) +#define GLB_TZC_GLB_GPIO_2_LOCK_LEN (1) #define GLB_TZC_GLB_GPIO_2_LOCK_MSK \ - (((1U << GLB_TZC_GLB_GPIO_2_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_2_LOCK_POS) + (((1 << GLB_TZC_GLB_GPIO_2_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_2_LOCK_POS) #define GLB_TZC_GLB_GPIO_2_LOCK_UMSK \ - (~(((1U << GLB_TZC_GLB_GPIO_2_LOCK_LEN) - 1) \ - << GLB_TZC_GLB_GPIO_2_LOCK_POS)) + (~(((1 << GLB_TZC_GLB_GPIO_2_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_2_LOCK_POS)) #define GLB_TZC_GLB_GPIO_3_LOCK GLB_TZC_GLB_GPIO_3_LOCK -#define GLB_TZC_GLB_GPIO_3_LOCK_POS (3U) -#define GLB_TZC_GLB_GPIO_3_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_3_LOCK_POS (3) +#define GLB_TZC_GLB_GPIO_3_LOCK_LEN (1) #define GLB_TZC_GLB_GPIO_3_LOCK_MSK \ - (((1U << GLB_TZC_GLB_GPIO_3_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_3_LOCK_POS) + (((1 << GLB_TZC_GLB_GPIO_3_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_3_LOCK_POS) #define GLB_TZC_GLB_GPIO_3_LOCK_UMSK \ - (~(((1U << GLB_TZC_GLB_GPIO_3_LOCK_LEN) - 1) \ - << GLB_TZC_GLB_GPIO_3_LOCK_POS)) + (~(((1 << GLB_TZC_GLB_GPIO_3_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_3_LOCK_POS)) #define GLB_TZC_GLB_GPIO_4_LOCK GLB_TZC_GLB_GPIO_4_LOCK -#define GLB_TZC_GLB_GPIO_4_LOCK_POS (4U) -#define GLB_TZC_GLB_GPIO_4_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_4_LOCK_POS (4) +#define GLB_TZC_GLB_GPIO_4_LOCK_LEN (1) #define GLB_TZC_GLB_GPIO_4_LOCK_MSK \ - (((1U << GLB_TZC_GLB_GPIO_4_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_4_LOCK_POS) + (((1 << GLB_TZC_GLB_GPIO_4_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_4_LOCK_POS) #define GLB_TZC_GLB_GPIO_4_LOCK_UMSK \ - (~(((1U << GLB_TZC_GLB_GPIO_4_LOCK_LEN) - 1) \ - << GLB_TZC_GLB_GPIO_4_LOCK_POS)) + (~(((1 << GLB_TZC_GLB_GPIO_4_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_4_LOCK_POS)) #define GLB_TZC_GLB_GPIO_5_LOCK GLB_TZC_GLB_GPIO_5_LOCK -#define GLB_TZC_GLB_GPIO_5_LOCK_POS (5U) -#define GLB_TZC_GLB_GPIO_5_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_5_LOCK_POS (5) +#define GLB_TZC_GLB_GPIO_5_LOCK_LEN (1) #define GLB_TZC_GLB_GPIO_5_LOCK_MSK \ - (((1U << GLB_TZC_GLB_GPIO_5_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_5_LOCK_POS) + (((1 << GLB_TZC_GLB_GPIO_5_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_5_LOCK_POS) #define GLB_TZC_GLB_GPIO_5_LOCK_UMSK \ - (~(((1U << GLB_TZC_GLB_GPIO_5_LOCK_LEN) - 1) \ - << GLB_TZC_GLB_GPIO_5_LOCK_POS)) + (~(((1 << GLB_TZC_GLB_GPIO_5_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_5_LOCK_POS)) #define GLB_TZC_GLB_GPIO_6_LOCK GLB_TZC_GLB_GPIO_6_LOCK -#define GLB_TZC_GLB_GPIO_6_LOCK_POS (6U) -#define GLB_TZC_GLB_GPIO_6_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_6_LOCK_POS (6) +#define GLB_TZC_GLB_GPIO_6_LOCK_LEN (1) #define GLB_TZC_GLB_GPIO_6_LOCK_MSK \ - (((1U << GLB_TZC_GLB_GPIO_6_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_6_LOCK_POS) + (((1 << GLB_TZC_GLB_GPIO_6_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_6_LOCK_POS) #define GLB_TZC_GLB_GPIO_6_LOCK_UMSK \ - (~(((1U << GLB_TZC_GLB_GPIO_6_LOCK_LEN) - 1) \ - << GLB_TZC_GLB_GPIO_6_LOCK_POS)) + (~(((1 << GLB_TZC_GLB_GPIO_6_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_6_LOCK_POS)) #define GLB_TZC_GLB_GPIO_7_LOCK GLB_TZC_GLB_GPIO_7_LOCK -#define GLB_TZC_GLB_GPIO_7_LOCK_POS (7U) -#define GLB_TZC_GLB_GPIO_7_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_7_LOCK_POS (7) +#define GLB_TZC_GLB_GPIO_7_LOCK_LEN (1) #define GLB_TZC_GLB_GPIO_7_LOCK_MSK \ - (((1U << GLB_TZC_GLB_GPIO_7_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_7_LOCK_POS) + (((1 << GLB_TZC_GLB_GPIO_7_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_7_LOCK_POS) #define GLB_TZC_GLB_GPIO_7_LOCK_UMSK \ - (~(((1U << GLB_TZC_GLB_GPIO_7_LOCK_LEN) - 1) \ - << GLB_TZC_GLB_GPIO_7_LOCK_POS)) + (~(((1 << GLB_TZC_GLB_GPIO_7_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_7_LOCK_POS)) #define GLB_TZC_GLB_GPIO_8_LOCK GLB_TZC_GLB_GPIO_8_LOCK -#define GLB_TZC_GLB_GPIO_8_LOCK_POS (8U) -#define GLB_TZC_GLB_GPIO_8_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_8_LOCK_POS (8) +#define GLB_TZC_GLB_GPIO_8_LOCK_LEN (1) #define GLB_TZC_GLB_GPIO_8_LOCK_MSK \ - (((1U << GLB_TZC_GLB_GPIO_8_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_8_LOCK_POS) + (((1 << GLB_TZC_GLB_GPIO_8_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_8_LOCK_POS) #define GLB_TZC_GLB_GPIO_8_LOCK_UMSK \ - (~(((1U << GLB_TZC_GLB_GPIO_8_LOCK_LEN) - 1) \ - << GLB_TZC_GLB_GPIO_8_LOCK_POS)) + (~(((1 << GLB_TZC_GLB_GPIO_8_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_8_LOCK_POS)) #define GLB_TZC_GLB_GPIO_9_LOCK GLB_TZC_GLB_GPIO_9_LOCK -#define GLB_TZC_GLB_GPIO_9_LOCK_POS (9U) -#define GLB_TZC_GLB_GPIO_9_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_9_LOCK_POS (9) +#define GLB_TZC_GLB_GPIO_9_LOCK_LEN (1) #define GLB_TZC_GLB_GPIO_9_LOCK_MSK \ - (((1U << GLB_TZC_GLB_GPIO_9_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_9_LOCK_POS) + (((1 << GLB_TZC_GLB_GPIO_9_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_9_LOCK_POS) #define GLB_TZC_GLB_GPIO_9_LOCK_UMSK \ - (~(((1U << GLB_TZC_GLB_GPIO_9_LOCK_LEN) - 1) \ - << GLB_TZC_GLB_GPIO_9_LOCK_POS)) + (~(((1 << GLB_TZC_GLB_GPIO_9_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_9_LOCK_POS)) #define GLB_TZC_GLB_GPIO_10_LOCK GLB_TZC_GLB_GPIO_10_LOCK -#define GLB_TZC_GLB_GPIO_10_LOCK_POS (10U) -#define GLB_TZC_GLB_GPIO_10_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_10_LOCK_POS (10) +#define GLB_TZC_GLB_GPIO_10_LOCK_LEN (1) #define GLB_TZC_GLB_GPIO_10_LOCK_MSK \ - (((1U << GLB_TZC_GLB_GPIO_10_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_10_LOCK_POS) + (((1 << GLB_TZC_GLB_GPIO_10_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_10_LOCK_POS) #define GLB_TZC_GLB_GPIO_10_LOCK_UMSK \ - (~(((1U << GLB_TZC_GLB_GPIO_10_LOCK_LEN) - 1) \ + (~(((1 << GLB_TZC_GLB_GPIO_10_LOCK_LEN) - 1) \ << GLB_TZC_GLB_GPIO_10_LOCK_POS)) #define GLB_TZC_GLB_GPIO_11_LOCK GLB_TZC_GLB_GPIO_11_LOCK -#define GLB_TZC_GLB_GPIO_11_LOCK_POS (11U) -#define GLB_TZC_GLB_GPIO_11_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_11_LOCK_POS (11) +#define GLB_TZC_GLB_GPIO_11_LOCK_LEN (1) #define GLB_TZC_GLB_GPIO_11_LOCK_MSK \ - (((1U << GLB_TZC_GLB_GPIO_11_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_11_LOCK_POS) + (((1 << GLB_TZC_GLB_GPIO_11_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_11_LOCK_POS) #define GLB_TZC_GLB_GPIO_11_LOCK_UMSK \ - (~(((1U << GLB_TZC_GLB_GPIO_11_LOCK_LEN) - 1) \ + (~(((1 << GLB_TZC_GLB_GPIO_11_LOCK_LEN) - 1) \ << GLB_TZC_GLB_GPIO_11_LOCK_POS)) #define GLB_TZC_GLB_GPIO_12_LOCK GLB_TZC_GLB_GPIO_12_LOCK -#define GLB_TZC_GLB_GPIO_12_LOCK_POS (12U) -#define GLB_TZC_GLB_GPIO_12_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_12_LOCK_POS (12) +#define GLB_TZC_GLB_GPIO_12_LOCK_LEN (1) #define GLB_TZC_GLB_GPIO_12_LOCK_MSK \ - (((1U << GLB_TZC_GLB_GPIO_12_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_12_LOCK_POS) + (((1 << GLB_TZC_GLB_GPIO_12_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_12_LOCK_POS) #define GLB_TZC_GLB_GPIO_12_LOCK_UMSK \ - (~(((1U << GLB_TZC_GLB_GPIO_12_LOCK_LEN) - 1) \ + (~(((1 << GLB_TZC_GLB_GPIO_12_LOCK_LEN) - 1) \ << GLB_TZC_GLB_GPIO_12_LOCK_POS)) #define GLB_TZC_GLB_GPIO_13_LOCK GLB_TZC_GLB_GPIO_13_LOCK -#define GLB_TZC_GLB_GPIO_13_LOCK_POS (13U) -#define GLB_TZC_GLB_GPIO_13_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_13_LOCK_POS (13) +#define GLB_TZC_GLB_GPIO_13_LOCK_LEN (1) #define GLB_TZC_GLB_GPIO_13_LOCK_MSK \ - (((1U << GLB_TZC_GLB_GPIO_13_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_13_LOCK_POS) + (((1 << GLB_TZC_GLB_GPIO_13_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_13_LOCK_POS) #define GLB_TZC_GLB_GPIO_13_LOCK_UMSK \ - (~(((1U << GLB_TZC_GLB_GPIO_13_LOCK_LEN) - 1) \ + (~(((1 << GLB_TZC_GLB_GPIO_13_LOCK_LEN) - 1) \ << GLB_TZC_GLB_GPIO_13_LOCK_POS)) #define GLB_TZC_GLB_GPIO_14_LOCK GLB_TZC_GLB_GPIO_14_LOCK -#define GLB_TZC_GLB_GPIO_14_LOCK_POS (14U) -#define GLB_TZC_GLB_GPIO_14_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_14_LOCK_POS (14) +#define GLB_TZC_GLB_GPIO_14_LOCK_LEN (1) #define GLB_TZC_GLB_GPIO_14_LOCK_MSK \ - (((1U << GLB_TZC_GLB_GPIO_14_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_14_LOCK_POS) + (((1 << GLB_TZC_GLB_GPIO_14_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_14_LOCK_POS) #define GLB_TZC_GLB_GPIO_14_LOCK_UMSK \ - (~(((1U << GLB_TZC_GLB_GPIO_14_LOCK_LEN) - 1) \ + (~(((1 << GLB_TZC_GLB_GPIO_14_LOCK_LEN) - 1) \ << GLB_TZC_GLB_GPIO_14_LOCK_POS)) #define GLB_TZC_GLB_GPIO_15_LOCK GLB_TZC_GLB_GPIO_15_LOCK -#define GLB_TZC_GLB_GPIO_15_LOCK_POS (15U) -#define GLB_TZC_GLB_GPIO_15_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_15_LOCK_POS (15) +#define GLB_TZC_GLB_GPIO_15_LOCK_LEN (1) #define GLB_TZC_GLB_GPIO_15_LOCK_MSK \ - (((1U << GLB_TZC_GLB_GPIO_15_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_15_LOCK_POS) + (((1 << GLB_TZC_GLB_GPIO_15_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_15_LOCK_POS) #define GLB_TZC_GLB_GPIO_15_LOCK_UMSK \ - (~(((1U << GLB_TZC_GLB_GPIO_15_LOCK_LEN) - 1) \ + (~(((1 << GLB_TZC_GLB_GPIO_15_LOCK_LEN) - 1) \ << GLB_TZC_GLB_GPIO_15_LOCK_POS)) #define GLB_TZC_GLB_GPIO_16_LOCK GLB_TZC_GLB_GPIO_16_LOCK -#define GLB_TZC_GLB_GPIO_16_LOCK_POS (16U) -#define GLB_TZC_GLB_GPIO_16_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_16_LOCK_POS (16) +#define GLB_TZC_GLB_GPIO_16_LOCK_LEN (1) #define GLB_TZC_GLB_GPIO_16_LOCK_MSK \ - (((1U << GLB_TZC_GLB_GPIO_16_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_16_LOCK_POS) + (((1 << GLB_TZC_GLB_GPIO_16_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_16_LOCK_POS) #define GLB_TZC_GLB_GPIO_16_LOCK_UMSK \ - (~(((1U << GLB_TZC_GLB_GPIO_16_LOCK_LEN) - 1) \ + (~(((1 << GLB_TZC_GLB_GPIO_16_LOCK_LEN) - 1) \ << GLB_TZC_GLB_GPIO_16_LOCK_POS)) #define GLB_TZC_GLB_GPIO_17_LOCK GLB_TZC_GLB_GPIO_17_LOCK -#define GLB_TZC_GLB_GPIO_17_LOCK_POS (17U) -#define GLB_TZC_GLB_GPIO_17_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_17_LOCK_POS (17) +#define GLB_TZC_GLB_GPIO_17_LOCK_LEN (1) #define GLB_TZC_GLB_GPIO_17_LOCK_MSK \ - (((1U << GLB_TZC_GLB_GPIO_17_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_17_LOCK_POS) + (((1 << GLB_TZC_GLB_GPIO_17_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_17_LOCK_POS) #define GLB_TZC_GLB_GPIO_17_LOCK_UMSK \ - (~(((1U << GLB_TZC_GLB_GPIO_17_LOCK_LEN) - 1) \ + (~(((1 << GLB_TZC_GLB_GPIO_17_LOCK_LEN) - 1) \ << GLB_TZC_GLB_GPIO_17_LOCK_POS)) #define GLB_TZC_GLB_GPIO_18_LOCK GLB_TZC_GLB_GPIO_18_LOCK -#define GLB_TZC_GLB_GPIO_18_LOCK_POS (18U) -#define GLB_TZC_GLB_GPIO_18_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_18_LOCK_POS (18) +#define GLB_TZC_GLB_GPIO_18_LOCK_LEN (1) #define GLB_TZC_GLB_GPIO_18_LOCK_MSK \ - (((1U << GLB_TZC_GLB_GPIO_18_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_18_LOCK_POS) + (((1 << GLB_TZC_GLB_GPIO_18_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_18_LOCK_POS) #define GLB_TZC_GLB_GPIO_18_LOCK_UMSK \ - (~(((1U << GLB_TZC_GLB_GPIO_18_LOCK_LEN) - 1) \ + (~(((1 << GLB_TZC_GLB_GPIO_18_LOCK_LEN) - 1) \ << GLB_TZC_GLB_GPIO_18_LOCK_POS)) #define GLB_TZC_GLB_GPIO_19_LOCK GLB_TZC_GLB_GPIO_19_LOCK -#define GLB_TZC_GLB_GPIO_19_LOCK_POS (19U) -#define GLB_TZC_GLB_GPIO_19_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_19_LOCK_POS (19) +#define GLB_TZC_GLB_GPIO_19_LOCK_LEN (1) #define GLB_TZC_GLB_GPIO_19_LOCK_MSK \ - (((1U << GLB_TZC_GLB_GPIO_19_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_19_LOCK_POS) + (((1 << GLB_TZC_GLB_GPIO_19_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_19_LOCK_POS) #define GLB_TZC_GLB_GPIO_19_LOCK_UMSK \ - (~(((1U << GLB_TZC_GLB_GPIO_19_LOCK_LEN) - 1) \ + (~(((1 << GLB_TZC_GLB_GPIO_19_LOCK_LEN) - 1) \ << GLB_TZC_GLB_GPIO_19_LOCK_POS)) #define GLB_TZC_GLB_GPIO_20_LOCK GLB_TZC_GLB_GPIO_20_LOCK -#define GLB_TZC_GLB_GPIO_20_LOCK_POS (20U) -#define GLB_TZC_GLB_GPIO_20_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_20_LOCK_POS (20) +#define GLB_TZC_GLB_GPIO_20_LOCK_LEN (1) #define GLB_TZC_GLB_GPIO_20_LOCK_MSK \ - (((1U << GLB_TZC_GLB_GPIO_20_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_20_LOCK_POS) + (((1 << GLB_TZC_GLB_GPIO_20_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_20_LOCK_POS) #define GLB_TZC_GLB_GPIO_20_LOCK_UMSK \ - (~(((1U << GLB_TZC_GLB_GPIO_20_LOCK_LEN) - 1) \ + (~(((1 << GLB_TZC_GLB_GPIO_20_LOCK_LEN) - 1) \ << GLB_TZC_GLB_GPIO_20_LOCK_POS)) #define GLB_TZC_GLB_GPIO_21_LOCK GLB_TZC_GLB_GPIO_21_LOCK -#define GLB_TZC_GLB_GPIO_21_LOCK_POS (21U) -#define GLB_TZC_GLB_GPIO_21_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_21_LOCK_POS (21) +#define GLB_TZC_GLB_GPIO_21_LOCK_LEN (1) #define GLB_TZC_GLB_GPIO_21_LOCK_MSK \ - (((1U << GLB_TZC_GLB_GPIO_21_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_21_LOCK_POS) + (((1 << GLB_TZC_GLB_GPIO_21_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_21_LOCK_POS) #define GLB_TZC_GLB_GPIO_21_LOCK_UMSK \ - (~(((1U << GLB_TZC_GLB_GPIO_21_LOCK_LEN) - 1) \ + (~(((1 << GLB_TZC_GLB_GPIO_21_LOCK_LEN) - 1) \ << GLB_TZC_GLB_GPIO_21_LOCK_POS)) #define GLB_TZC_GLB_GPIO_22_LOCK GLB_TZC_GLB_GPIO_22_LOCK -#define GLB_TZC_GLB_GPIO_22_LOCK_POS (22U) -#define GLB_TZC_GLB_GPIO_22_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_22_LOCK_POS (22) +#define GLB_TZC_GLB_GPIO_22_LOCK_LEN (1) #define GLB_TZC_GLB_GPIO_22_LOCK_MSK \ - (((1U << GLB_TZC_GLB_GPIO_22_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_22_LOCK_POS) + (((1 << GLB_TZC_GLB_GPIO_22_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_22_LOCK_POS) #define GLB_TZC_GLB_GPIO_22_LOCK_UMSK \ - (~(((1U << GLB_TZC_GLB_GPIO_22_LOCK_LEN) - 1) \ + (~(((1 << GLB_TZC_GLB_GPIO_22_LOCK_LEN) - 1) \ << GLB_TZC_GLB_GPIO_22_LOCK_POS)) #define GLB_TZC_GLB_GPIO_23_LOCK GLB_TZC_GLB_GPIO_23_LOCK -#define GLB_TZC_GLB_GPIO_23_LOCK_POS (23U) -#define GLB_TZC_GLB_GPIO_23_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_23_LOCK_POS (23) +#define GLB_TZC_GLB_GPIO_23_LOCK_LEN (1) #define GLB_TZC_GLB_GPIO_23_LOCK_MSK \ - (((1U << GLB_TZC_GLB_GPIO_23_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_23_LOCK_POS) + (((1 << GLB_TZC_GLB_GPIO_23_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_23_LOCK_POS) #define GLB_TZC_GLB_GPIO_23_LOCK_UMSK \ - (~(((1U << GLB_TZC_GLB_GPIO_23_LOCK_LEN) - 1) \ + (~(((1 << GLB_TZC_GLB_GPIO_23_LOCK_LEN) - 1) \ << GLB_TZC_GLB_GPIO_23_LOCK_POS)) #define GLB_TZC_GLB_GPIO_24_LOCK GLB_TZC_GLB_GPIO_24_LOCK -#define GLB_TZC_GLB_GPIO_24_LOCK_POS (24U) -#define GLB_TZC_GLB_GPIO_24_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_24_LOCK_POS (24) +#define GLB_TZC_GLB_GPIO_24_LOCK_LEN (1) #define GLB_TZC_GLB_GPIO_24_LOCK_MSK \ - (((1U << GLB_TZC_GLB_GPIO_24_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_24_LOCK_POS) + (((1 << GLB_TZC_GLB_GPIO_24_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_24_LOCK_POS) #define GLB_TZC_GLB_GPIO_24_LOCK_UMSK \ - (~(((1U << GLB_TZC_GLB_GPIO_24_LOCK_LEN) - 1) \ + (~(((1 << GLB_TZC_GLB_GPIO_24_LOCK_LEN) - 1) \ << GLB_TZC_GLB_GPIO_24_LOCK_POS)) #define GLB_TZC_GLB_GPIO_25_LOCK GLB_TZC_GLB_GPIO_25_LOCK -#define GLB_TZC_GLB_GPIO_25_LOCK_POS (25U) -#define GLB_TZC_GLB_GPIO_25_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_25_LOCK_POS (25) +#define GLB_TZC_GLB_GPIO_25_LOCK_LEN (1) #define GLB_TZC_GLB_GPIO_25_LOCK_MSK \ - (((1U << GLB_TZC_GLB_GPIO_25_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_25_LOCK_POS) + (((1 << GLB_TZC_GLB_GPIO_25_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_25_LOCK_POS) #define GLB_TZC_GLB_GPIO_25_LOCK_UMSK \ - (~(((1U << GLB_TZC_GLB_GPIO_25_LOCK_LEN) - 1) \ + (~(((1 << GLB_TZC_GLB_GPIO_25_LOCK_LEN) - 1) \ << GLB_TZC_GLB_GPIO_25_LOCK_POS)) #define GLB_TZC_GLB_GPIO_26_LOCK GLB_TZC_GLB_GPIO_26_LOCK -#define GLB_TZC_GLB_GPIO_26_LOCK_POS (26U) -#define GLB_TZC_GLB_GPIO_26_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_26_LOCK_POS (26) +#define GLB_TZC_GLB_GPIO_26_LOCK_LEN (1) #define GLB_TZC_GLB_GPIO_26_LOCK_MSK \ - (((1U << GLB_TZC_GLB_GPIO_26_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_26_LOCK_POS) + (((1 << GLB_TZC_GLB_GPIO_26_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_26_LOCK_POS) #define GLB_TZC_GLB_GPIO_26_LOCK_UMSK \ - (~(((1U << GLB_TZC_GLB_GPIO_26_LOCK_LEN) - 1) \ + (~(((1 << GLB_TZC_GLB_GPIO_26_LOCK_LEN) - 1) \ << GLB_TZC_GLB_GPIO_26_LOCK_POS)) #define GLB_TZC_GLB_GPIO_27_LOCK GLB_TZC_GLB_GPIO_27_LOCK -#define GLB_TZC_GLB_GPIO_27_LOCK_POS (27U) -#define GLB_TZC_GLB_GPIO_27_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_27_LOCK_POS (27) +#define GLB_TZC_GLB_GPIO_27_LOCK_LEN (1) #define GLB_TZC_GLB_GPIO_27_LOCK_MSK \ - (((1U << GLB_TZC_GLB_GPIO_27_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_27_LOCK_POS) + (((1 << GLB_TZC_GLB_GPIO_27_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_27_LOCK_POS) #define GLB_TZC_GLB_GPIO_27_LOCK_UMSK \ - (~(((1U << GLB_TZC_GLB_GPIO_27_LOCK_LEN) - 1) \ + (~(((1 << GLB_TZC_GLB_GPIO_27_LOCK_LEN) - 1) \ << GLB_TZC_GLB_GPIO_27_LOCK_POS)) #define GLB_TZC_GLB_GPIO_28_LOCK GLB_TZC_GLB_GPIO_28_LOCK -#define GLB_TZC_GLB_GPIO_28_LOCK_POS (28U) -#define GLB_TZC_GLB_GPIO_28_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_28_LOCK_POS (28) +#define GLB_TZC_GLB_GPIO_28_LOCK_LEN (1) #define GLB_TZC_GLB_GPIO_28_LOCK_MSK \ - (((1U << GLB_TZC_GLB_GPIO_28_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_28_LOCK_POS) + (((1 << GLB_TZC_GLB_GPIO_28_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_28_LOCK_POS) #define GLB_TZC_GLB_GPIO_28_LOCK_UMSK \ - (~(((1U << GLB_TZC_GLB_GPIO_28_LOCK_LEN) - 1) \ + (~(((1 << GLB_TZC_GLB_GPIO_28_LOCK_LEN) - 1) \ << GLB_TZC_GLB_GPIO_28_LOCK_POS)) /* 0xF0C : tzc_glb_ctrl_3 */ @@ -3947,106 +3928,104 @@ #define GLB_GPIO_CFGCTL_OFFSET (0x0) #define GLB_REG_GPIO_0_IE GLB_REG_GPIO_0_IE -#define GLB_REG_GPIO_0_IE_POS (0U) -#define GLB_REG_GPIO_0_IE_LEN (1U) +#define GLB_REG_GPIO_0_IE_POS (0) +#define GLB_REG_GPIO_0_IE_LEN (1) #define GLB_REG_GPIO_0_IE_MSK \ - (((1U << GLB_REG_GPIO_0_IE_LEN) - 1) << GLB_REG_GPIO_0_IE_POS) + (((1 << GLB_REG_GPIO_0_IE_LEN) - 1) << GLB_REG_GPIO_0_IE_POS) #define GLB_REG_GPIO_0_IE_UMSK \ - (~(((1U << GLB_REG_GPIO_0_IE_LEN) - 1) << GLB_REG_GPIO_0_IE_POS)) + (~(((1 << GLB_REG_GPIO_0_IE_LEN) - 1) << GLB_REG_GPIO_0_IE_POS)) #define GLB_REG_GPIO_0_SMT GLB_REG_GPIO_0_SMT -#define GLB_REG_GPIO_0_SMT_POS (1U) -#define GLB_REG_GPIO_0_SMT_LEN (1U) +#define GLB_REG_GPIO_0_SMT_POS (1) +#define GLB_REG_GPIO_0_SMT_LEN (1) #define GLB_REG_GPIO_0_SMT_MSK \ - (((1U << GLB_REG_GPIO_0_SMT_LEN) - 1) << GLB_REG_GPIO_0_SMT_POS) + (((1 << GLB_REG_GPIO_0_SMT_LEN) - 1) << GLB_REG_GPIO_0_SMT_POS) #define GLB_REG_GPIO_0_SMT_UMSK \ - (~(((1U << GLB_REG_GPIO_0_SMT_LEN) - 1) << GLB_REG_GPIO_0_SMT_POS)) + (~(((1 << GLB_REG_GPIO_0_SMT_LEN) - 1) << GLB_REG_GPIO_0_SMT_POS)) #define GLB_REG_GPIO_0_DRV GLB_REG_GPIO_0_DRV -#define GLB_REG_GPIO_0_DRV_POS (2U) -#define GLB_REG_GPIO_0_DRV_LEN (2U) +#define GLB_REG_GPIO_0_DRV_POS (2) +#define GLB_REG_GPIO_0_DRV_LEN (2) #define GLB_REG_GPIO_0_DRV_MSK \ - (((1U << GLB_REG_GPIO_0_DRV_LEN) - 1) << GLB_REG_GPIO_0_DRV_POS) + (((1 << GLB_REG_GPIO_0_DRV_LEN) - 1) << GLB_REG_GPIO_0_DRV_POS) #define GLB_REG_GPIO_0_DRV_UMSK \ - (~(((1U << GLB_REG_GPIO_0_DRV_LEN) - 1) << GLB_REG_GPIO_0_DRV_POS)) + (~(((1 << GLB_REG_GPIO_0_DRV_LEN) - 1) << GLB_REG_GPIO_0_DRV_POS)) #define GLB_REG_GPIO_0_PU GLB_REG_GPIO_0_PU -#define GLB_REG_GPIO_0_PU_POS (4U) -#define GLB_REG_GPIO_0_PU_LEN (1U) +#define GLB_REG_GPIO_0_PU_POS (4) +#define GLB_REG_GPIO_0_PU_LEN (1) #define GLB_REG_GPIO_0_PU_MSK \ - (((1U << GLB_REG_GPIO_0_PU_LEN) - 1) << GLB_REG_GPIO_0_PU_POS) + (((1 << GLB_REG_GPIO_0_PU_LEN) - 1) << GLB_REG_GPIO_0_PU_POS) #define GLB_REG_GPIO_0_PU_UMSK \ - (~(((1U << GLB_REG_GPIO_0_PU_LEN) - 1) << GLB_REG_GPIO_0_PU_POS)) + (~(((1 << GLB_REG_GPIO_0_PU_LEN) - 1) << GLB_REG_GPIO_0_PU_POS)) #define GLB_REG_GPIO_0_PD GLB_REG_GPIO_0_PD -#define GLB_REG_GPIO_0_PD_POS (5U) -#define GLB_REG_GPIO_0_PD_LEN (1U) +#define GLB_REG_GPIO_0_PD_POS (5) +#define GLB_REG_GPIO_0_PD_LEN (1) #define GLB_REG_GPIO_0_PD_MSK \ - (((1U << GLB_REG_GPIO_0_PD_LEN) - 1) << GLB_REG_GPIO_0_PD_POS) + (((1 << GLB_REG_GPIO_0_PD_LEN) - 1) << GLB_REG_GPIO_0_PD_POS) #define GLB_REG_GPIO_0_PD_UMSK \ - (~(((1U << GLB_REG_GPIO_0_PD_LEN) - 1) << GLB_REG_GPIO_0_PD_POS)) + (~(((1 << GLB_REG_GPIO_0_PD_LEN) - 1) << GLB_REG_GPIO_0_PD_POS)) #define GLB_REG_GPIO_0_FUNC_SEL GLB_REG_GPIO_0_FUNC_SEL -#define GLB_REG_GPIO_0_FUNC_SEL_POS (8U) -#define GLB_REG_GPIO_0_FUNC_SEL_LEN (4U) +#define GLB_REG_GPIO_0_FUNC_SEL_POS (8) +#define GLB_REG_GPIO_0_FUNC_SEL_LEN (4) #define GLB_REG_GPIO_0_FUNC_SEL_MSK \ - (((1U << GLB_REG_GPIO_0_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_0_FUNC_SEL_POS) + (((1 << GLB_REG_GPIO_0_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_0_FUNC_SEL_POS) #define GLB_REG_GPIO_0_FUNC_SEL_UMSK \ - (~(((1U << GLB_REG_GPIO_0_FUNC_SEL_LEN) - 1) \ - << GLB_REG_GPIO_0_FUNC_SEL_POS)) + (~(((1 << GLB_REG_GPIO_0_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_0_FUNC_SEL_POS)) #define GLB_REAL_GPIO_0_FUNC_SEL GLB_REAL_GPIO_0_FUNC_SEL -#define GLB_REAL_GPIO_0_FUNC_SEL_POS (12U) -#define GLB_REAL_GPIO_0_FUNC_SEL_LEN (4U) +#define GLB_REAL_GPIO_0_FUNC_SEL_POS (12) +#define GLB_REAL_GPIO_0_FUNC_SEL_LEN (4) #define GLB_REAL_GPIO_0_FUNC_SEL_MSK \ - (((1U << GLB_REAL_GPIO_0_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_0_FUNC_SEL_POS) + (((1 << GLB_REAL_GPIO_0_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_0_FUNC_SEL_POS) #define GLB_REAL_GPIO_0_FUNC_SEL_UMSK \ - (~(((1U << GLB_REAL_GPIO_0_FUNC_SEL_LEN) - 1) \ + (~(((1 << GLB_REAL_GPIO_0_FUNC_SEL_LEN) - 1) \ << GLB_REAL_GPIO_0_FUNC_SEL_POS)) #define GLB_REG_GPIO_1_IE GLB_REG_GPIO_1_IE -#define GLB_REG_GPIO_1_IE_POS (16U) -#define GLB_REG_GPIO_1_IE_LEN (1U) +#define GLB_REG_GPIO_1_IE_POS (16) +#define GLB_REG_GPIO_1_IE_LEN (1) #define GLB_REG_GPIO_1_IE_MSK \ - (((1U << GLB_REG_GPIO_1_IE_LEN) - 1) << GLB_REG_GPIO_1_IE_POS) + (((1 << GLB_REG_GPIO_1_IE_LEN) - 1) << GLB_REG_GPIO_1_IE_POS) #define GLB_REG_GPIO_1_IE_UMSK \ - (~(((1U << GLB_REG_GPIO_1_IE_LEN) - 1) << GLB_REG_GPIO_1_IE_POS)) + (~(((1 << GLB_REG_GPIO_1_IE_LEN) - 1) << GLB_REG_GPIO_1_IE_POS)) #define GLB_REG_GPIO_1_SMT GLB_REG_GPIO_1_SMT -#define GLB_REG_GPIO_1_SMT_POS (17U) -#define GLB_REG_GPIO_1_SMT_LEN (1U) +#define GLB_REG_GPIO_1_SMT_POS (17) +#define GLB_REG_GPIO_1_SMT_LEN (1) #define GLB_REG_GPIO_1_SMT_MSK \ - (((1U << GLB_REG_GPIO_1_SMT_LEN) - 1) << GLB_REG_GPIO_1_SMT_POS) + (((1 << GLB_REG_GPIO_1_SMT_LEN) - 1) << GLB_REG_GPIO_1_SMT_POS) #define GLB_REG_GPIO_1_SMT_UMSK \ - (~(((1U << GLB_REG_GPIO_1_SMT_LEN) - 1) << GLB_REG_GPIO_1_SMT_POS)) + (~(((1 << GLB_REG_GPIO_1_SMT_LEN) - 1) << GLB_REG_GPIO_1_SMT_POS)) #define GLB_REG_GPIO_1_DRV GLB_REG_GPIO_1_DRV -#define GLB_REG_GPIO_1_DRV_POS (18U) -#define GLB_REG_GPIO_1_DRV_LEN (2U) +#define GLB_REG_GPIO_1_DRV_POS (18) +#define GLB_REG_GPIO_1_DRV_LEN (2) #define GLB_REG_GPIO_1_DRV_MSK \ - (((1U << GLB_REG_GPIO_1_DRV_LEN) - 1) << GLB_REG_GPIO_1_DRV_POS) + (((1 << GLB_REG_GPIO_1_DRV_LEN) - 1) << GLB_REG_GPIO_1_DRV_POS) #define GLB_REG_GPIO_1_DRV_UMSK \ - (~(((1U << GLB_REG_GPIO_1_DRV_LEN) - 1) << GLB_REG_GPIO_1_DRV_POS)) + (~(((1 << GLB_REG_GPIO_1_DRV_LEN) - 1) << GLB_REG_GPIO_1_DRV_POS)) #define GLB_REG_GPIO_1_PU GLB_REG_GPIO_1_PU -#define GLB_REG_GPIO_1_PU_POS (20U) -#define GLB_REG_GPIO_1_PU_LEN (1U) +#define GLB_REG_GPIO_1_PU_POS (20) +#define GLB_REG_GPIO_1_PU_LEN (1) #define GLB_REG_GPIO_1_PU_MSK \ - (((1U << GLB_REG_GPIO_1_PU_LEN) - 1) << GLB_REG_GPIO_1_PU_POS) + (((1 << GLB_REG_GPIO_1_PU_LEN) - 1) << GLB_REG_GPIO_1_PU_POS) #define GLB_REG_GPIO_1_PU_UMSK \ - (~(((1U << GLB_REG_GPIO_1_PU_LEN) - 1) << GLB_REG_GPIO_1_PU_POS)) + (~(((1 << GLB_REG_GPIO_1_PU_LEN) - 1) << GLB_REG_GPIO_1_PU_POS)) #define GLB_REG_GPIO_1_PD GLB_REG_GPIO_1_PD -#define GLB_REG_GPIO_1_PD_POS (21U) -#define GLB_REG_GPIO_1_PD_LEN (1U) +#define GLB_REG_GPIO_1_PD_POS (21) +#define GLB_REG_GPIO_1_PD_LEN (1) #define GLB_REG_GPIO_1_PD_MSK \ - (((1U << GLB_REG_GPIO_1_PD_LEN) - 1) << GLB_REG_GPIO_1_PD_POS) + (((1 << GLB_REG_GPIO_1_PD_LEN) - 1) << GLB_REG_GPIO_1_PD_POS) #define GLB_REG_GPIO_1_PD_UMSK \ - (~(((1U << GLB_REG_GPIO_1_PD_LEN) - 1) << GLB_REG_GPIO_1_PD_POS)) + (~(((1 << GLB_REG_GPIO_1_PD_LEN) - 1) << GLB_REG_GPIO_1_PD_POS)) #define GLB_REG_GPIO_1_FUNC_SEL GLB_REG_GPIO_1_FUNC_SEL -#define GLB_REG_GPIO_1_FUNC_SEL_POS (24U) -#define GLB_REG_GPIO_1_FUNC_SEL_LEN (4U) +#define GLB_REG_GPIO_1_FUNC_SEL_POS (24) +#define GLB_REG_GPIO_1_FUNC_SEL_LEN (4) #define GLB_REG_GPIO_1_FUNC_SEL_MSK \ - (((1U << GLB_REG_GPIO_1_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_1_FUNC_SEL_POS) + (((1 << GLB_REG_GPIO_1_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_1_FUNC_SEL_POS) #define GLB_REG_GPIO_1_FUNC_SEL_UMSK \ - (~(((1U << GLB_REG_GPIO_1_FUNC_SEL_LEN) - 1) \ - << GLB_REG_GPIO_1_FUNC_SEL_POS)) + (~(((1 << GLB_REG_GPIO_1_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_1_FUNC_SEL_POS)) #define GLB_REAL_GPIO_1_FUNC_SEL GLB_REAL_GPIO_1_FUNC_SEL -#define GLB_REAL_GPIO_1_FUNC_SEL_POS (28U) -#define GLB_REAL_GPIO_1_FUNC_SEL_LEN (4U) +#define GLB_REAL_GPIO_1_FUNC_SEL_POS (28) +#define GLB_REAL_GPIO_1_FUNC_SEL_LEN (4) #define GLB_REAL_GPIO_1_FUNC_SEL_MSK \ - (((1U << GLB_REAL_GPIO_1_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_1_FUNC_SEL_POS) + (((1 << GLB_REAL_GPIO_1_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_1_FUNC_SEL_POS) #define GLB_REAL_GPIO_1_FUNC_SEL_UMSK \ - (~(((1U << GLB_REAL_GPIO_1_FUNC_SEL_LEN) - 1) \ + (~(((1 << GLB_REAL_GPIO_1_FUNC_SEL_LEN) - 1) \ << GLB_REAL_GPIO_1_FUNC_SEL_POS)) #define GLB_GPIO_OFFSET 0x100 @@ -4054,1706 +4033,188 @@ #define GLB_GPIO_OUTPUT_OFFSET 0x188 #define GLB_GPIO_OUTPUT_EN_OFFSET 0x190 +/* GLB root clock type definition */ + +#define GLB_ROOT_CLK_RC32M 0 /* root clock select RC32M */ +#define GLB_ROOT_CLK_XTAL 1 /* root clock select XTAL */ +#define GLB_ROOT_CLK_PLL 2 /* root clock select PLL others */ + +/* GLB system clock type definition */ + +#define GLB_SYS_CLK_RC32M 0 /* use RC32M as system clock frequency */ +#define GLB_SYS_CLK_XTAL 1 /* use XTAL as system clock */ +#define GLB_SYS_CLK_PLL48M 2 /* use PLL output 48M as system clock */ +#define GLB_SYS_CLK_PLL120M 3 /* use PLL output 120M as system clock */ +#define GLB_SYS_CLK_PLL160M 4 /* use PLL output 160M as system clock */ +#define GLB_SYS_CLK_PLL192M 5 /* use PLL output 192M as system clock */ + +/* GLB DMA clock ID type definition */ + +#define GLB_DMA_CLK_DMA0_CH0 0 /* DMA clock ID:channel 0 */ +#define GLB_DMA_CLK_DMA0_CH1 1 /* DMA clock ID:channel 1 */ +#define GLB_DMA_CLK_DMA0_CH2 2 /* DMA clock ID:channel 2 */ +#define GLB_DMA_CLK_DMA0_CH3 3 /* DMA clock ID:channel 3 */ + +/* GLB clock source type definition */ + +#define GLB_IR_CLK_SRC_XCLK 0 /* IR clock source select XCLK */ + +/* GLB flash clock type definition */ + +#define GLB_SFLASH_CLK_120M 0 /* Select 120M as flash clock */ +#define GLB_SFLASH_CLK_XTAL 1 /* Select XTAL as flash clock */ +#define GLB_SFLASH_CLK_48M 2 /* Select 48M as flash clock */ +#define GLB_SFLASH_CLK_80M 3 /* Select 80M as flash clock */ +#define GLB_SFLASH_CLK_BCLK 4 /* Select BCLK as flash clock */ +#define GLB_SFLASH_CLK_96M 5 /* Select 96M as flash clock */ + +/* GLB SPI pad action type definition */ + +#define GLB_SPI_PAD_ACT_AS_SLAVE 0 /* SPI pad act as slave */ +#define GLB_SPI_PAD_ACT_AS_MASTER 1 /* SPI pad act as master */ + +/* GLB PKA clock type definition */ + +#define GLB_PKA_CLK_HCLK 0 /* Select HCLK as PKA clock */ +#define GLB_PKA_CLK_PLL120M 1 /* Select PLL 120M as PKA clock */ + +/* BMX arb mode type definition */ + +#define BMX_ARB_FIX 0 /* 0->fix */ +#define BMX_ARB_ROUND_ROBIN 1 /* 2->round-robin */ +#define BMX_ARB_RANDOM 2 /* 3->random */ + +/* BMX bus err type definition */ + +#define BMX_BUS_ERR_TRUSTZONE_DECODE 0 /* Bus trustzone decode error */ +#define BMX_BUS_ERR_ADDR_DECODE 1 /* Bus addr decode error */ + +/* BMX bus err interrupt type definition */ + +#define BMX_ERR_INT_ERR 0 /* BMX bus err interrupt */ +#define BMX_ERR_INT_ALL 1 /* BMX bus err interrupt max num */ + +/* BMX time out interrupt type definition */ + +#define BMX_TO_INT_TIMEOUT 0 /* BMX timeout interrupt */ +#define BMX_TO_INT_ALL 1 /* BMX timeout interrupt max num */ + +/* GLB EM type definition */ + +#define GLB_EM_0KB 0x0 /* 0x0 --> 0KB */ +#define GLB_EM_8KB 0x3 /* 0x3 --> 8KB */ +#define GLB_EM_16KB 0xF /* 0xF --> 16KB */ + +/* GLB RTC clock type definition */ + +#define GLB_MTIMER_CLK_BCLK 0 /* BUS clock */ +#define GLB_MTIMER_CLK_32K 1 /* 32KHz */ + +/* GLB ADC clock type definition */ + +#define GLB_ADC_CLK_96M 0 /* use 96M as ADC clock */ +#define GLB_ADC_CLK_XCLK 1 /* use XCLK as ADC clock */ + +/* GLB DAC clock type definition */ + +#define GLB_DAC_CLK_32M 0 /* use 32M as DAC clock */ +#define GLB_DAC_CLK_XCLK 1 /* use XCLK as DAC clock */ + +/* GLB DIG clock source select type definition */ + +#define GLB_DIG_CLK_PLL_32M 0 /* select PLL 32M as DIG clock source */ +#define GLB_DIG_CLK_XCLK 1 /* select XCLK as DIG clock source */ + +/* GLB 512K clock out select type definition */ + +#define GLB_512K_CLK_OUT_512K 0 /* select 512K clock out */ +#define GLB_512K_CLK_OUT_256K 1 /* select 256K clock out */ +#define GLB_512K_CLK_OUT_128K 2 /* select 128K clock out */ + +/* GLB BT bandwidth type definition */ + +#define GLB_BT_BANDWIDTH_1M 0 /* BT bandwidth 1MHz */ +#define GLB_BT_BANDWIDTH_2M 1 /* BT bandwidth 2MHz */ + +/* GLB UART signal type definition */ + +#define GLB_UART_SIG_0 0 /* UART signal 0 */ +#define GLB_UART_SIG_1 1 /* UART signal 1 */ +#define GLB_UART_SIG_2 2 /* UART signal 2 */ +#define GLB_UART_SIG_3 3 /* UART signal 3 */ +#define GLB_UART_SIG_4 4 /* UART signal 4 */ +#define GLB_UART_SIG_5 5 /* UART signal 5 */ +#define GLB_UART_SIG_6 6 /* UART signal 6 */ +#define GLB_UART_SIG_7 7 /* UART signal 7 */ + +/* GLB UART signal function type definition */ + +#define GLB_UART_SIG_FUN_UART0_RTS 0 /* UART funtion: UART 0 RTS */ +#define GLB_UART_SIG_FUN_UART0_CTS 1 /* UART funtion: UART 0 CTS */ +#define GLB_UART_SIG_FUN_UART0_TXD 2 /* UART funtion: UART 0 TXD */ +#define GLB_UART_SIG_FUN_UART0_RXD 3 /* UART funtion: UART 0 RXD */ +#define GLB_UART_SIG_FUN_UART1_RTS 4 /* UART funtion: UART 1 RTS */ +#define GLB_UART_SIG_FUN_UART1_CTS 5 /* UART funtion: UART 1 CTS */ +#define GLB_UART_SIG_FUN_UART1_TXD 6 /* UART funtion: UART 1 TXD */ +#define GLB_UART_SIG_FUN_UART1_RXD 7 /* UART funtion: UART 1 RXD */ + +/* GLB GPIO real mode type definition */ + +#define GLB_GPIO_REAL_MODE_REG \ + 0 /* GPIO real function is reg_gpio_x_func_sel */ + +#define GLB_GPIO_REAL_MODE_SDIO 1 /* GPIO real function is SDIO */ +#define GLB_GPIO_REAL_MODE_RF 2 /* GPIO real function is RF */ +#define GLB_GPIO_REAL_MODE_JTAG 3 /* GPIO real function is JTAG */ +#define GLB_GPIO_REAL_MODE_CCI 4 /* GPIO real function is CCI */ + +/* GLB GPIO interrupt trigger mode type definition */ + +#define GLB_GPIO_INT_TRIG_NEG_PULSE \ + 0 /* GPIO negedge pulse trigger interrupt */ + +#define GLB_GPIO_INT_TRIG_POS_PULSE \ + 1 /* GPIO posedge pulse trigger interrupt */ + +#define GLB_GPIO_INT_TRIG_NEG_LEVEL \ + 2 /* GPIO negedge level trigger interrupt (32k 3T) */ + +#define GLB_GPIO_INT_TRIG_POS_LEVEL \ + 3 /* GPIO posedge level trigger interrupt (32k 3T) */ + +/* GLB GPIO interrupt control mode type definition */ + +#define GLB_GPIO_INT_CONTROL_SYNC 0 /* GPIO interrupt sync mode */ +#define GLB_GPIO_INT_CONTROL_ASYNC 1 /* GPIO interrupt async mode */ + +/* PLL XTAL type definition */ + +#define GLB_PLL_XTAL_NONE 0 /* XTAL is none */ +#define GLB_PLL_XTAL_24M 1 /* XTAL is 24M */ +#define GLB_PLL_XTAL_32M 2 /* XTAL is 32M */ +#define GLB_PLL_XTAL_38P4M 3 /* XTAL is 38.4M */ +#define GLB_PLL_XTAL_40M 4 /* XTAL is 40M */ +#define GLB_PLL_XTAL_26M 5 /* XTAL is 26M */ +#define GLB_PLL_XTAL_RC32M 6 /* XTAL is RC32M */ + +/* PLL output clock type definition */ + +#define GLB_PLL_CLK_480M 0 /* PLL output clock:480M */ +#define GLB_PLL_CLK_240M 1 /* PLL output clock:240M */ +#define GLB_PLL_CLK_192M 2 /* PLL output clock:192M */ +#define GLB_PLL_CLK_160M 3 /* PLL output clock:160M */ +#define GLB_PLL_CLK_120M 4 /* PLL output clock:120M */ +#define GLB_PLL_CLK_96M 5 /* PLL output clock:96M */ +#define GLB_PLL_CLK_80M 6 /* PLL output clock:80M */ +#define GLB_PLL_CLK_48M 7 /* PLL output clock:48M */ +#define GLB_PLL_CLK_32M 8 /* PLL output clock:32M */ + /**************************************************************************** * Public Types ****************************************************************************/ #ifndef __ASSEMBLY__ -/* GLB root clock type definition */ - -enum glb_root_clk_e -{ - GLB_ROOT_CLK_RC32M, /* root clock select RC32M */ - GLB_ROOT_CLK_XTAL, /* root clock select XTAL */ - GLB_ROOT_CLK_PLL /* root clock select PLL others */ -}; - -/* GLB system clock type definition */ - -enum glb_sys_clk_e -{ - GLB_SYS_CLK_RC32M, /* use RC32M as system clock frequency */ - GLB_SYS_CLK_XTAL, /* use XTAL as system clock */ - GLB_SYS_CLK_PLL48M, /* use PLL output 48M as system clock */ - GLB_SYS_CLK_PLL120M, /* use PLL output 120M as system clock */ - GLB_SYS_CLK_PLL160M, /* use PLL output 160M as system clock */ - GLB_SYS_CLK_PLL192M /* use PLL output 192M as system clock */ -}; - -/* GLB DMA clock ID type definition */ - -enum glb_dma_clk_id_e -{ - GLB_DMA_CLK_DMA0_CH0, /* DMA clock ID:channel 0 */ - GLB_DMA_CLK_DMA0_CH1, /* DMA clock ID:channel 1 */ - GLB_DMA_CLK_DMA0_CH2, /* DMA clock ID:channel 2 */ - GLB_DMA_CLK_DMA0_CH3 /* DMA clock ID:channel 3 */ -}; - -/* GLB clock source type definition */ - -enum glb_ir_clk_src_e -{ - GLB_IR_CLK_SRC_XCLK /* IR clock source select XCLK */ -}; - -/* GLB flash clock type definition */ - -enum glb_sflash_clk_e -{ - GLB_SFLASH_CLK_120M, /* Select 120M as flash clock */ - GLB_SFLASH_CLK_XTAL, /* Select XTAL as flash clock */ - GLB_SFLASH_CLK_48M, /* Select 48M as flash clock */ - GLB_SFLASH_CLK_80M, /* Select 80M as flash clock */ - GLB_SFLASH_CLK_BCLK, /* Select BCLK as flash clock */ - GLB_SFLASH_CLK_96M /* Select 96M as flash clock */ -}; - -/* GLB SPI pad action type definition */ - -enum glb_spi_pad_act_as_e -{ - GLB_SPI_PAD_ACT_AS_SLAVE, /* SPI pad act as slave */ - GLB_SPI_PAD_ACT_AS_MASTER /* SPI pad act as master */ -}; - -/* GLB PKA clock type definition */ - -enum glb_pka_clk_type_e -{ - GLB_PKA_CLK_HCLK, /* Select HCLK as PKA clock */ - GLB_PKA_CLK_PLL120M /* Select PLL 120M as PKA clock */ -}; - -/* BMX arb mode type definition */ - -enum bmx_arb_type_e -{ - BMX_ARB_FIX, /* 0->fix */ - BMX_ARB_ROUND_ROBIN, /* 2->round-robin */ - BMX_ARB_RANDOM /* 3->random */ -}; - -/* BMX configuration structure type definition */ - -struct bmx_cfg_type_s -{ - /* Bus timeout enable: detect slave no reaponse in 1024 cycles */ - - uint8_t timeout_en; - void * err_en; /* Bus error response enable */ - enum bmx_arb_type_e arb_mod; /* 0->fix, 2->round-robin, 3->random */ -}; - -/* BMX bus err type definition */ - -enum bmx_bus_err_type_e -{ - BMX_BUS_ERR_TRUSTZONE_DECODE, /* Bus trustzone decode error */ - BMX_BUS_ERR_ADDR_DECODE /* Bus addr decode error */ -}; - -/* BMX bus err interrupt type definition */ - -enum bmx_err_int_type_e -{ - BMX_ERR_INT_ERR, /* BMX bus err interrupt */ - BMX_ERR_INT_ALL /* BMX bus err interrupt max num */ -}; - -/* BMX time out interrupt type definition */ - -enum bmx_to_int_type_e -{ - BMX_TO_INT_TIMEOUT, /* BMX timeout interrupt */ - BMX_TO_INT_ALL /* BMX timeout interrupt max num */ -}; - -/* GLB EM type definition */ - -enum glb_em_type_e -{ - GLB_EM_0KB = 0x0, /* 0x0 --> 0KB */ - GLB_EM_8KB = 0x3, /* 0x3 --> 8KB */ - GLB_EM_16KB = 0xf /* 0xF --> 16KB */ -}; - -/* GLB RTC clock type definition */ - -enum glb_mtimer_clk_e -{ - GLB_MTIMER_CLK_BCLK, /* BUS clock */ - GLB_MTIMER_CLK_32K /* 32KHz */ -}; - -/* GLB ADC clock type definition */ - -enum glb_adc_clk_e -{ - GLB_ADC_CLK_96M, /* use 96M as ADC clock */ - GLB_ADC_CLK_XCLK /* use XCLK as ADC clock */ -}; - -/* GLB DAC clock type definition */ - -enum glb_dac_clk_e -{ - GLB_DAC_CLK_32M, /* use 32M as DAC clock */ - GLB_DAC_CLK_XCLK /* use XCLK as DAC clock */ -}; - -/* GLB DIG clock source select type definition */ - -enum glb_dig_clk_e -{ - GLB_DIG_CLK_PLL_32M, /* select PLL 32M as DIG clock source */ - GLB_DIG_CLK_XCLK /* select XCLK as DIG clock source */ -}; - -/* GLB 512K clock out select type definition */ - -enum glb_512k_clk_out_e -{ - GLB_512K_CLK_OUT_512K, /* select 512K clock out */ - GLB_512K_CLK_OUT_256K, /* select 256K clock out */ - GLB_512K_CLK_OUT_128K /* select 128K clock out */ -}; - -/* GLB BT bandwidth type definition */ - -enum glb_bt_bandwidth_e -{ - GLB_BT_BANDWIDTH_1M, /* BT bandwidth 1MHz */ - GLB_BT_BANDWIDTH_2M /* BT bandwidth 2MHz */ -}; - -/* GLB UART signal type definition */ - -enum glb_uart_sig_e -{ - GLB_UART_SIG_0, /* UART signal 0 */ - GLB_UART_SIG_1, /* UART signal 1 */ - GLB_UART_SIG_2, /* UART signal 2 */ - GLB_UART_SIG_3, /* UART signal 3 */ - GLB_UART_SIG_4, /* UART signal 4 */ - GLB_UART_SIG_5, /* UART signal 5 */ - GLB_UART_SIG_6, /* UART signal 6 */ - GLB_UART_SIG_7 /* UART signal 7 */ -}; - -/* GLB UART signal function type definition */ - -enum glb_uart_sig_fun_e -{ - GLB_UART_SIG_FUN_UART0_RTS, /* UART funtion: UART 0 RTS */ - GLB_UART_SIG_FUN_UART0_CTS, /* UART funtion: UART 0 CTS */ - GLB_UART_SIG_FUN_UART0_TXD, /* UART funtion: UART 0 TXD */ - GLB_UART_SIG_FUN_UART0_RXD, /* UART funtion: UART 0 RXD */ - GLB_UART_SIG_FUN_UART1_RTS, /* UART funtion: UART 1 RTS */ - GLB_UART_SIG_FUN_UART1_CTS, /* UART funtion: UART 1 CTS */ - GLB_UART_SIG_FUN_UART1_TXD, /* UART funtion: UART 1 TXD */ - GLB_UART_SIG_FUN_UART1_RXD /* UART funtion: UART 1 RXD */ -}; - -/* GLB GPIO real mode type definition */ - -enum glb_gpio_real_mode_e -{ - /* GPIO real function is reg_gpio_x_func_sel */ - - GLB_GPIO_REAL_MODE_REG = 0x0, - GLB_GPIO_REAL_MODE_SDIO = 0x1, /* GPIO real function is SDIO */ - GLB_GPIO_REAL_MODE_RF = 0xc, /* GPIO real function is RF */ - GLB_GPIO_REAL_MODE_JTAG = 0xe, /* GPIO real function is JTAG */ - GLB_GPIO_REAL_MODE_CCI = 0xf /* GPIO real function is CCI */ -}; - -/* GLB GPIO interrupt trigger mode type definition */ - -enum glb_gpio_int_trig_e -{ - GLB_GPIO_INT_TRIG_NEG_PULSE, /* GPIO negedge pulse trigger interrupt */ - GLB_GPIO_INT_TRIG_POS_PULSE, /* GPIO posedge pulse trigger interrupt */ - - /* GPIO negedge level trigger interrupt (32k 3T) */ - - GLB_GPIO_INT_TRIG_NEG_LEVEL, - - /* GPIO posedge level trigger interrupt (32k 3T) */ - - GLB_GPIO_INT_TRIG_POS_LEVEL -}; - -/* GLB GPIO interrupt control mode type definition */ - -enum glb_gpio_int_control_e -{ - GLB_GPIO_INT_CONTROL_SYNC, /* GPIO interrupt sync mode */ - GLB_GPIO_INT_CONTROL_ASYNC /* GPIO interrupt async mode */ -}; - -/* PLL XTAL type definition */ - -enum glb_pll_xtal_e -{ - GLB_PLL_XTAL_NONE, /* XTAL is none */ - GLB_PLL_XTAL_24M, /* XTAL is 24M */ - GLB_PLL_XTAL_32M, /* XTAL is 32M */ - GLB_PLL_XTAL_38P4M, /* XTAL is 38.4M */ - GLB_PLL_XTAL_40M, /* XTAL is 40M */ - GLB_PLL_XTAL_26M, /* XTAL is 26M */ - GLB_PLL_XTAL_RC32M /* XTAL is RC32M */ -}; - -/* PLL output clock type definition */ - -enum glb_pll_clk_e -{ - GLB_PLL_CLK_480M, /* PLL output clock:480M */ - GLB_PLL_CLK_240M, /* PLL output clock:240M */ - GLB_PLL_CLK_192M, /* PLL output clock:192M */ - GLB_PLL_CLK_160M, /* PLL output clock:160M */ - GLB_PLL_CLK_120M, /* PLL output clock:120M */ - GLB_PLL_CLK_96M, /* PLL output clock:96M */ - GLB_PLL_CLK_80M, /* PLL output clock:80M */ - GLB_PLL_CLK_48M, /* PLL output clock:48M */ - GLB_PLL_CLK_32M /* PLL output clock:32M */ -}; - -struct glb_reg_s -{ - /* 0x0 : clk_cfg0 */ - - union - { - struct - { - uint32_t reg_pll_en : 1; /* [ 0], r/w, 0x1 */ - uint32_t reg_fclk_en : 1; /* [ 1], r/w, 0x1 */ - uint32_t reg_hclk_en : 1; /* [ 2], r/w, 0x1 */ - uint32_t reg_bclk_en : 1; /* [ 3], r/w, 0x1 */ - uint32_t reg_pll_sel : 2; /* [ 5: 4], r/w, 0x0 */ - uint32_t hbn_root_clk_sel : 2; /* [ 7: 6], r, 0x0 */ - uint32_t reg_hclk_div : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_bclk_div : 8; /* [23:16], r/w, 0x0 */ - uint32_t fclk_sw_state : 3; /* [26:24], r, 0x0 */ - uint32_t chip_rdy : 1; /* [ 27], r, 0x0 */ - uint32_t glb_id : 4; /* [31:28], r, 0x6 */ - } bf; - uint32_t word; - } clk_cfg0; - - /* 0x4 : clk_cfg1 */ - - union - { - struct - { - uint32_t wifi_mac_core_div : 4; /* [ 3: 0], r/w, 0x1 */ - uint32_t wifi_mac_wt_div : 4; /* [ 7: 4], r/w, 0x0 */ - uint32_t reserved_8_15 : 8; /* [15: 8], rsvd, 0x0 */ - uint32_t ble_clk_sel : 6; /* [21:16], r/w, 0x10 */ - uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ - uint32_t ble_en : 1; /* [ 24], r/w, 0x1 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } bf; - uint32_t word; - } clk_cfg1; - - /* 0x8 : clk_cfg2 */ - - union - { - struct - { - uint32_t uart_clk_div : 3; /* [ 2: 0], r/w, 0x7 */ - uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */ - uint32_t uart_clk_en : 1; /* [ 4], r/w, 0x1 */ - uint32_t reserved_5_6 : 2; /* [ 6: 5], rsvd, 0x0 */ - uint32_t hbn_uart_clk_sel : 1; /* [ 7], r, 0x0 */ - uint32_t sf_clk_div : 3; /* [10: 8], r/w, 0x3 */ - uint32_t sf_clk_en : 1; /* [ 11], r/w, 0x1 */ - uint32_t sf_clk_sel : 2; /* [13:12], r/w, 0x2 */ - uint32_t sf_clk_sel2 : 2; /* [15:14], r/w, 0x0 */ - uint32_t ir_clk_div : 6; /* [21:16], r/w, 0xf */ - uint32_t reserved_22 : 1; /* [ 22], rsvd, 0x0 */ - uint32_t ir_clk_en : 1; /* [ 23], r/w, 0x1 */ - uint32_t dma_clk_en : 8; /* [31:24], r/w, 0xff */ - } bf; - uint32_t word; - } clk_cfg2; - - /* 0xC : clk_cfg3 */ - - union - { - struct - { - uint32_t spi_clk_div : 5; /* [ 4: 0], r/w, 0x3 */ - uint32_t reserved_5_7 : 3; /* [ 7: 5], rsvd, 0x0 */ - uint32_t spi_clk_en : 1; /* [ 8], r/w, 0x1 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t i2c_clk_div : 8; /* [23:16], r/w, 0xff */ - uint32_t i2c_clk_en : 1; /* [ 24], r/w, 0x1 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } bf; - uint32_t word; - } clk_cfg3; - - /* 0x10 : swrst_cfg0 */ - - union - { - struct - { - uint32_t swrst_s00 : 1; /* [ 0], r/w, 0x0 */ - uint32_t swrst_s01 : 1; /* [ 1], r/w, 0x0 */ - uint32_t reserved_2_3 : 2; /* [ 3: 2], rsvd, 0x0 */ - uint32_t swrst_s20 : 1; /* [ 4], r/w, 0x0 */ - uint32_t reserved_5_7 : 3; /* [ 7: 5], rsvd, 0x0 */ - uint32_t swrst_s30 : 1; /* [ 8], r/w, 0x0 */ - uint32_t reserved_9_31 : 23; /* [31: 9], rsvd, 0x0 */ - } bf; - uint32_t word; - } swrst_cfg0; - - /* 0x14 : swrst_cfg1 */ - - union - { - struct - { - uint32_t swrst_s10 : 1; /* [ 0], r/w, 0x0 */ - uint32_t swrst_s11 : 1; /* [ 1], r/w, 0x0 */ - uint32_t swrst_s12 : 1; /* [ 2], r/w, 0x0 */ - uint32_t swrst_s13 : 1; /* [ 3], r/w, 0x0 */ - uint32_t swrst_s14 : 1; /* [ 4], r/w, 0x0 */ - uint32_t swrst_s15 : 1; /* [ 5], r/w, 0x0 */ - uint32_t swrst_s16 : 1; /* [ 6], r/w, 0x0 */ - uint32_t swrst_s17 : 1; /* [ 7], r/w, 0x0 */ - uint32_t swrst_s18 : 1; /* [ 8], r/w, 0x0 */ - uint32_t swrst_s19 : 1; /* [ 9], r/w, 0x0 */ - uint32_t swrst_s1a : 1; /* [ 10], r/w, 0x0 */ - uint32_t swrst_s1b : 1; /* [ 11], r/w, 0x0 */ - uint32_t swrst_s1c : 1; /* [ 12], r/w, 0x0 */ - uint32_t swrst_s1d : 1; /* [ 13], r/w, 0x0 */ - uint32_t swrst_s1e : 1; /* [ 14], r/w, 0x0 */ - uint32_t swrst_s1f : 1; /* [ 15], r/w, 0x0 */ - uint32_t swrst_s1a0 : 1; /* [ 16], r/w, 0x0 */ - uint32_t swrst_s1a1 : 1; /* [ 17], r/w, 0x0 */ - uint32_t swrst_s1a2 : 1; /* [ 18], r/w, 0x0 */ - uint32_t swrst_s1a3 : 1; /* [ 19], r/w, 0x0 */ - uint32_t swrst_s1a4 : 1; /* [ 20], r/w, 0x0 */ - uint32_t swrst_s1a5 : 1; /* [ 21], r/w, 0x0 */ - uint32_t swrst_s1a6 : 1; /* [ 22], r/w, 0x0 */ - uint32_t swrst_s1a7 : 1; /* [ 23], r/w, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } bf; - uint32_t word; - } swrst_cfg1; - - /* 0x18 : swrst_cfg2 */ - - union - { - struct - { - uint32_t reg_ctrl_pwron_rst : 1; /* [ 0], r/w, 0x0 */ - uint32_t reg_ctrl_cpu_reset : 1; /* [ 1], r/w, 0x0 */ - uint32_t reg_ctrl_sys_reset : 1; /* [ 2], r/w, 0x0 */ - uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */ - uint32_t reg_ctrl_reset_dummy : 4; /* [ 7: 4], r/w, 0x0 */ - uint32_t reserved_8_23 : 16; /* [23: 8], rsvd, 0x0 */ - uint32_t pka_clk_sel : 1; /* [ 24], r/w, 0x0 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } bf; - uint32_t word; - } swrst_cfg2; - - /* 0x1C : swrst_cfg3 */ - - union - { - struct - { - uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */ - } bf; - uint32_t word; - } swrst_cfg3; - - /* 0x20 : cgen_cfg0 */ - - union - { - struct - { - uint32_t cgen_m : 8; /* [ 7: 0], r/w, 0xff */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } bf; - uint32_t word; - } cgen_cfg0; - - /* 0x24 : cgen_cfg1 */ - - union - { - struct - { - uint32_t cgen_s1 : 16; /* [15: 0], r/w, 0xffff */ - uint32_t cgen_s1a : 8; /* [23:16], r/w, 0xff */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } bf; - uint32_t word; - } cgen_cfg1; - - /* 0x28 : cgen_cfg2 */ - - union - { - struct - { - uint32_t cgen_s2 : 1; /* [ 0], r/w, 0x1 */ - uint32_t reserved_1_3 : 3; /* [ 3: 1], rsvd, 0x0 */ - uint32_t cgen_s3 : 1; /* [ 4], r/w, 0x1 */ - uint32_t reserved_5_31 : 27; /* [31: 5], rsvd, 0x0 */ - } bf; - uint32_t word; - } cgen_cfg2; - - /* 0x2C : cgen_cfg3 */ - - union - { - struct - { - uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */ - } bf; - uint32_t word; - } cgen_cfg3; - - /* 0x30 : MBIST_CTL */ - - union - { - struct - { - uint32_t irom_mbist_mode : 1; /* [ 0], r/w, 0x0 */ - uint32_t hsram_mbist_mode : 1; /* [ 1], r/w, 0x0 */ - uint32_t tag_mbist_mode : 1; /* [ 2], r/w, 0x0 */ - uint32_t ocram_mbist_mode : 1; /* [ 3], r/w, 0x0 */ - uint32_t wifi_mbist_mode : 1; /* [ 4], r/w, 0x0 */ - uint32_t reserved_5_30 : 26; /* [30: 5], rsvd, 0x0 */ - uint32_t reg_mbist_rst_n : 1; /* [ 31], r/w, 0x0 */ - } bf; - uint32_t word; - } MBIST_CTL; - - /* 0x34 : MBIST_STAT */ - - union - { - struct - { - uint32_t irom_mbist_done : 1; /* [ 0], r, 0x0 */ - uint32_t hsram_mbist_done : 1; /* [ 1], r, 0x0 */ - uint32_t tag_mbist_done : 1; /* [ 2], r, 0x0 */ - uint32_t ocram_mbist_done : 1; /* [ 3], r, 0x0 */ - uint32_t wifi_mbist_done : 1; /* [ 4], r, 0x0 */ - uint32_t reserved_5_15 : 11; /* [15: 5], rsvd, 0x0 */ - uint32_t irom_mbist_fail : 1; /* [ 16], r, 0x0 */ - uint32_t hsram_mbist_fail : 1; /* [ 17], r, 0x0 */ - uint32_t tag_mbist_fail : 1; /* [ 18], r, 0x0 */ - uint32_t ocram_mbist_fail : 1; /* [ 19], r, 0x0 */ - uint32_t wifi_mbist_fail : 1; /* [ 20], r, 0x0 */ - uint32_t reserved_21_31 : 11; /* [31:21], rsvd, 0x0 */ - } bf; - uint32_t word; - } MBIST_STAT; - - /* 0x38 reserved */ - - uint8_t reserved_0x38[24]; - - /* 0x50 : bmx_cfg1 */ - - union - { - struct - { - uint32_t bmx_timeout_en : 4; /* [ 3: 0], r/w, 0x0 */ - uint32_t bmx_arb_mode : 2; /* [ 5: 4], r/w, 0x0 */ - uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ - uint32_t bmx_err_en : 1; /* [ 8], r/w, 0x0 */ - uint32_t bmx_busy_option_dis : 1; /* [ 9], r/w, 0x0 */ - uint32_t bmx_gating_dis : 1; /* [ 10], r/w, 0x0 */ - uint32_t reserved_11 : 1; /* [ 11], rsvd, 0x0 */ - uint32_t hsel_option : 4; /* [15:12], r/w, 0x0 */ - uint32_t pds_apb_cfg : 8; /* [23:16], r/w, 0x0 */ - uint32_t hbn_apb_cfg : 8; /* [31:24], r/w, 0x0 */ - } bf; - uint32_t word; - } bmx_cfg1; - - /* 0x54 : bmx_cfg2 */ - - union - { - struct - { - uint32_t bmx_err_addr_dis : 1; /* [ 0], r/w, 0x0 */ - uint32_t reserved_1_3 : 3; /* [ 3: 1], rsvd, 0x0 */ - uint32_t bmx_err_dec : 1; /* [ 4], r, 0x0 */ - uint32_t bmx_err_tz : 1; /* [ 5], r, 0x0 */ - uint32_t reserved_6_27 : 22; /* [27: 6], rsvd, 0x0 */ - uint32_t bmx_dbg_sel : 4; /* [31:28], r/w, 0x0 */ - } bf; - uint32_t word; - } bmx_cfg2; - - /* 0x58 : bmx_err_addr */ - - union - { - struct - { - uint32_t bmx_err_addr : 32; /* [31: 0], r, 0x0 */ - } bf; - uint32_t word; - } bmx_err_addr; - - /* 0x5C : bmx_dbg_out */ - - union - { - struct - { - uint32_t bmx_dbg_out : 32; /* [31: 0], r, 0x0 */ - } bf; - uint32_t word; - } bmx_dbg_out; - - /* 0x60 : rsv0 */ - - union - { - struct - { - uint32_t rsvd_31_0 : 32; /* [31: 0], rsvd, 0x0 */ - } bf; - uint32_t word; - } rsv0; - - /* 0x64 : rsv1 */ - - union - { - struct - { - uint32_t rsvd_31_0 : 32; /* [31: 0], rsvd, 0x0 */ - } bf; - uint32_t word; - } rsv1; - - /* 0x68 : rsv2 */ - - union - { - struct - { - uint32_t rsvd_31_0 : 32; /* [31: 0], rsvd, 0x0 */ - } bf; - uint32_t word; - } rsv2; - - /* 0x6C : rsv3 */ - - union - { - struct - { - uint32_t rsvd_31_0 : 32; /* [31: 0], rsvd, 0xffffffffL */ - } bf; - uint32_t word; - } rsv3; - - /* 0x70 : sram_ret */ - - union - { - struct - { - uint32_t reg_sram_ret : 32; /* [31: 0], r/w, 0x0 */ - } bf; - uint32_t word; - } sram_ret; - - /* 0x74 : sram_slp */ - - union - { - struct - { - uint32_t reg_sram_slp : 32; /* [31: 0], r/w, 0x0 */ - } bf; - uint32_t word; - } sram_slp; - - /* 0x78 : sram_parm */ - - union - { - struct - { - uint32_t reg_sram_parm : 32; /* [31: 0], r/w, 0xc0c0c0c */ - } bf; - uint32_t word; - } sram_parm; - - /* 0x7C : seam_misc */ - - union - { - struct - { - uint32_t em_sel : 4; /* [ 3: 0], r/w, 0x3 */ - uint32_t reserved_4_31 : 28; /* [31: 4], rsvd, 0x0 */ - } bf; - uint32_t word; - } seam_misc; - - /* 0x80 : glb_parm */ - - union - { - struct - { - uint32_t reg_bd_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t reg_ext_rst_smt : 1; /* [ 1], r/w, 0x0 */ - uint32_t jtag_swap_set : 6; /* [ 7: 2], r/w, 0x0 */ - uint32_t swap_sflash_io_3_io_0 : 1; /* [ 8], r/w, 0x1 */ - uint32_t sel_embedded_sflash : 1; /* [ 9], r/w, 0x1 */ - uint32_t reserved_10_11 : 2; /* [11:10], rsvd, 0x0 */ - uint32_t reg_spi_0_master_mode : 1; /* [ 12], r/w, 0x0 */ - uint32_t reg_spi_0_swap : 1; /* [ 13], r/w, 0x0 */ - uint32_t reserved_14 : 1; /* [ 14], rsvd, 0x0 */ - uint32_t reg_cci_use_jtag_pin : 1; /* [ 15], r/w, 0x1 */ - uint32_t reg_cci_use_sdio_pin : 1; /* [ 16], r/w, 0x1 */ - uint32_t p1_adc_test_with_cci : 1; /* [ 17], r/w, 0x0 */ - uint32_t p2_dac_test_with_cci : 1; /* [ 18], r/w, 0x0 */ - uint32_t p3_cci_use_io_2_5 : 1; /* [ 19], r/w, 0x0 */ - uint32_t p4_adc_test_with_jtag : 1; /* [ 20], r/w, 0x0 */ - uint32_t p5_dac_test_with_jtag : 1; /* [ 21], r/w, 0x0 */ - uint32_t p6_sdio_use_io_0_5 : 1; /* [ 22], r/w, 0x0 */ - uint32_t p7_jtag_use_io_2_5 : 1; /* [ 23], r/w, 0x0 */ - uint32_t uart_swap_set : 3; /* [26:24], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } bf; - uint32_t word; - } glb_parm; - - /* 0x84 reserved */ - - uint8_t reserved_0x84[12]; - - /* 0x90 : CPU_CLK_CFG */ - - union - { - struct - { - uint32_t cpu_rtc_div : 17; /* [16: 0], r/w, 0x10 */ - uint32_t reserved_17 : 1; /* [ 17], rsvd, 0x0 */ - uint32_t cpu_rtc_en : 1; /* [ 18], r/w, 0x0 */ - uint32_t cpu_rtc_sel : 1; /* [ 19], r/w, 0x1 */ - uint32_t debug_ndreset_gate : 1; /* [ 20], r/w, 0x0 */ - uint32_t reserved_21_31 : 11; /* [31:21], rsvd, 0x0 */ - } bf; - uint32_t word; - } CPU_CLK_CFG; - - /* 0x94 reserved */ - - uint8_t reserved_0x94[16]; - - /* 0xA4 : GPADC_32M_SRC_CTRL */ - - union - { - struct - { - uint32_t gpadc_32m_clk_div : 6; /* [ 5: 0], r/w, 0x2 */ - uint32_t reserved_6 : 1; /* [ 6], rsvd, 0x0 */ - uint32_t gpadc_32m_clk_sel : 1; /* [ 7], r/w, 0x0 */ - uint32_t gpadc_32m_div_en : 1; /* [ 8], r/w, 0x1 */ - uint32_t reserved_9_31 : 23; /* [31: 9], rsvd, 0x0 */ - } bf; - uint32_t word; - } GPADC_32M_SRC_CTRL; - - /* 0xA8 : DIG32K_WAKEUP_CTRL */ - - union - { - struct - { - uint32_t dig_32k_div : 11; /* [10: 0], r/w, 0x3e8 */ - uint32_t reserved_11 : 1; /* [ 11], rsvd, 0x0 */ - uint32_t dig_32k_en : 1; /* [ 12], r/w, 0x1 */ - uint32_t dig_32k_comp : 1; /* [ 13], r/w, 0x0 */ - uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */ - uint32_t dig_512k_div : 7; /* [22:16], r/w, 0x3e */ - uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */ - uint32_t dig_512k_en : 1; /* [ 24], r/w, 0x1 */ - uint32_t dig_512k_comp : 1; /* [ 25], r/w, 0x1 */ - uint32_t reserved_26_27 : 2; /* [27:26], rsvd, 0x0 */ - uint32_t dig_clk_src_sel : 1; /* [ 28], r/w, 0x0 */ - uint32_t reserved_29_30 : 2; /* [30:29], rsvd, 0x0 */ - uint32_t reg_en_platform_wakeup : 1; /* [ 31], r/w, 0x0 */ - } bf; - uint32_t word; - } DIG32K_WAKEUP_CTRL; - - /* 0xAC : WIFI_BT_COEX_CTRL */ - - union - { - struct - { - uint32_t coex_bt_channel : 7; /* [ 6: 0], r/w, 0x0 */ - uint32_t coex_bt_pti : 4; /* [10: 7], r/w, 0x0 */ - uint32_t coex_bt_bw : 1; /* [ 11], r/w, 0x0 */ - uint32_t en_gpio_bt_coex : 1; /* [ 12], r/w, 0x0 */ - uint32_t reserved_13_31 : 19; /* [31:13], rsvd, 0x0 */ - } bf; - uint32_t word; - } WIFI_BT_COEX_CTRL; - - /* 0xb0 reserved */ - - uint8_t reserved_0xb0[16]; - - /* 0xC0 : UART_SIG_SEL_0 */ - - union - { - struct - { - uint32_t uart_sig_0_sel : 4; /* [ 3: 0], r/w, 0x0 */ - uint32_t uart_sig_1_sel : 4; /* [ 7: 4], r/w, 0x1 */ - uint32_t uart_sig_2_sel : 4; /* [11: 8], r/w, 0x2 */ - uint32_t uart_sig_3_sel : 4; /* [15:12], r/w, 0x3 */ - uint32_t uart_sig_4_sel : 4; /* [19:16], r/w, 0x4 */ - uint32_t uart_sig_5_sel : 4; /* [23:20], r/w, 0x5 */ - uint32_t uart_sig_6_sel : 4; /* [27:24], r/w, 0x6 */ - uint32_t uart_sig_7_sel : 4; /* [31:28], r/w, 0x7 */ - } bf; - uint32_t word; - } UART_SIG_SEL_0; - - /* 0xc4 reserved */ - - uint8_t reserved_0xc4[12]; - - /* 0xD0 : DBG_SEL_LL */ - - union - { - struct - { - uint32_t reg_dbg_ll_ctrl : 32; /* [31: 0], r/w, 0x0 */ - } bf; - uint32_t word; - } DBG_SEL_LL; - - /* 0xD4 : DBG_SEL_LH */ - - union - { - struct - { - uint32_t reg_dbg_lh_ctrl : 32; /* [31: 0], r/w, 0x0 */ - } bf; - uint32_t word; - } DBG_SEL_LH; - - /* 0xD8 : DBG_SEL_HL */ - - union - { - struct - { - uint32_t reg_dbg_hl_ctrl : 32; /* [31: 0], r/w, 0x0 */ - } bf; - uint32_t word; - } DBG_SEL_HL; - - /* 0xDC : DBG_SEL_HH */ - - union - { - struct - { - uint32_t reg_dbg_hh_ctrl : 32; /* [31: 0], r/w, 0x0 */ - } bf; - uint32_t word; - } DBG_SEL_HH; - - /* 0xE0 : debug */ - - union - { - struct - { - uint32_t debug_oe : 1; /* [ 0], r/w, 0x0 */ - uint32_t debug_i : 31; /* [31: 1], r, 0x0 */ - } bf; - uint32_t word; - } debug; - - /* 0xe4 reserved */ - - uint8_t reserved_0xe4[28]; - - /* 0x100 : GPIO_CFGCTL0 */ - - union - { - struct - { - uint32_t reg_gpio_0_ie : 1; /* [ 0], r/w, 0x1 */ - uint32_t reg_gpio_0_smt : 1; /* [ 1], r/w, 0x1 */ - uint32_t reg_gpio_0_drv : 2; /* [ 3: 2], r/w, 0x0 */ - uint32_t reg_gpio_0_pu : 1; /* [ 4], r/w, 0x0 */ - uint32_t reg_gpio_0_pd : 1; /* [ 5], r/w, 0x0 */ - uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ - uint32_t reg_gpio_0_func_sel : 4; /* [11: 8], r/w, 0x1 */ - uint32_t real_gpio_0_func_sel : 4; /* [15:12], r, 0x1 */ - uint32_t reg_gpio_1_ie : 1; /* [ 16], r/w, 0x1 */ - uint32_t reg_gpio_1_smt : 1; /* [ 17], r/w, 0x1 */ - uint32_t reg_gpio_1_drv : 2; /* [19:18], r/w, 0x0 */ - uint32_t reg_gpio_1_pu : 1; /* [ 20], r/w, 0x0 */ - uint32_t reg_gpio_1_pd : 1; /* [ 21], r/w, 0x0 */ - uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ - uint32_t reg_gpio_1_func_sel : 4; /* [27:24], r/w, 0x1 */ - uint32_t real_gpio_1_func_sel : 4; /* [31:28], r, 0x1 */ - } bf; - uint32_t word; - } GPIO_CFGCTL0; - - /* 0x104 : GPIO_CFGCTL1 */ - - union - { - struct - { - uint32_t reg_gpio_2_ie : 1; /* [ 0], r/w, 0x1 */ - uint32_t reg_gpio_2_smt : 1; /* [ 1], r/w, 0x1 */ - uint32_t reg_gpio_2_drv : 2; /* [ 3: 2], r/w, 0x0 */ - uint32_t reg_gpio_2_pu : 1; /* [ 4], r/w, 0x0 */ - uint32_t reg_gpio_2_pd : 1; /* [ 5], r/w, 0x0 */ - uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ - uint32_t reg_gpio_2_func_sel : 4; /* [11: 8], r/w, 0x1 */ - uint32_t real_gpio_2_func_sel : 4; /* [15:12], r, 0x1 */ - uint32_t reg_gpio_3_ie : 1; /* [ 16], r/w, 0x1 */ - uint32_t reg_gpio_3_smt : 1; /* [ 17], r/w, 0x1 */ - uint32_t reg_gpio_3_drv : 2; /* [19:18], r/w, 0x0 */ - uint32_t reg_gpio_3_pu : 1; /* [ 20], r/w, 0x0 */ - uint32_t reg_gpio_3_pd : 1; /* [ 21], r/w, 0x0 */ - uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ - uint32_t reg_gpio_3_func_sel : 4; /* [27:24], r/w, 0x1 */ - uint32_t real_gpio_3_func_sel : 4; /* [31:28], r, 0x1 */ - } bf; - uint32_t word; - } GPIO_CFGCTL1; - - /* 0x108 : GPIO_CFGCTL2 */ - - union - { - struct - { - uint32_t reg_gpio_4_ie : 1; /* [ 0], r/w, 0x1 */ - uint32_t reg_gpio_4_smt : 1; /* [ 1], r/w, 0x1 */ - uint32_t reg_gpio_4_drv : 2; /* [ 3: 2], r/w, 0x0 */ - uint32_t reg_gpio_4_pu : 1; /* [ 4], r/w, 0x0 */ - uint32_t reg_gpio_4_pd : 1; /* [ 5], r/w, 0x0 */ - uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ - uint32_t reg_gpio_4_func_sel : 4; /* [11: 8], r/w, 0x1 */ - uint32_t real_gpio_4_func_sel : 4; /* [15:12], r, 0x1 */ - uint32_t reg_gpio_5_ie : 1; /* [ 16], r/w, 0x1 */ - uint32_t reg_gpio_5_smt : 1; /* [ 17], r/w, 0x1 */ - uint32_t reg_gpio_5_drv : 2; /* [19:18], r/w, 0x0 */ - uint32_t reg_gpio_5_pu : 1; /* [ 20], r/w, 0x0 */ - uint32_t reg_gpio_5_pd : 1; /* [ 21], r/w, 0x0 */ - uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ - uint32_t reg_gpio_5_func_sel : 4; /* [27:24], r/w, 0x1 */ - uint32_t real_gpio_5_func_sel : 4; /* [31:28], r, 0x1 */ - } bf; - uint32_t word; - } GPIO_CFGCTL2; - - /* 0x10C : GPIO_CFGCTL3 */ - - union - { - struct - { - uint32_t reg_gpio_6_ie : 1; /* [ 0], r/w, 0x1 */ - uint32_t reg_gpio_6_smt : 1; /* [ 1], r/w, 0x1 */ - uint32_t reg_gpio_6_drv : 2; /* [ 3: 2], r/w, 0x0 */ - uint32_t reg_gpio_6_pu : 1; /* [ 4], r/w, 0x0 */ - uint32_t reg_gpio_6_pd : 1; /* [ 5], r/w, 0x0 */ - uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ - uint32_t reg_gpio_6_func_sel : 4; /* [11: 8], r/w, 0xb */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_gpio_7_ie : 1; /* [ 16], r/w, 0x1 */ - uint32_t reg_gpio_7_smt : 1; /* [ 17], r/w, 0x1 */ - uint32_t reg_gpio_7_drv : 2; /* [19:18], r/w, 0x0 */ - uint32_t reg_gpio_7_pu : 1; /* [ 20], r/w, 0x0 */ - uint32_t reg_gpio_7_pd : 1; /* [ 21], r/w, 0x0 */ - uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ - uint32_t reg_gpio_7_func_sel : 4; /* [27:24], r/w, 0xb */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } bf; - uint32_t word; - } GPIO_CFGCTL3; - - /* 0x110 : GPIO_CFGCTL4 */ - - union - { - struct - { - uint32_t reg_gpio_8_ie : 1; /* [ 0], r/w, 0x1 */ - uint32_t reg_gpio_8_smt : 1; /* [ 1], r/w, 0x1 */ - uint32_t reg_gpio_8_drv : 2; /* [ 3: 2], r/w, 0x0 */ - uint32_t reg_gpio_8_pu : 1; /* [ 4], r/w, 0x0 */ - uint32_t reg_gpio_8_pd : 1; /* [ 5], r/w, 0x0 */ - uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ - uint32_t reg_gpio_8_func_sel : 4; /* [11: 8], r/w, 0xb */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_gpio_9_ie : 1; /* [ 16], r/w, 0x1 */ - uint32_t reg_gpio_9_smt : 1; /* [ 17], r/w, 0x1 */ - uint32_t reg_gpio_9_drv : 2; /* [19:18], r/w, 0x0 */ - uint32_t reg_gpio_9_pu : 1; /* [ 20], r/w, 0x0 */ - uint32_t reg_gpio_9_pd : 1; /* [ 21], r/w, 0x0 */ - uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ - uint32_t reg_gpio_9_func_sel : 4; /* [27:24], r/w, 0xb */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } bf; - uint32_t word; - } GPIO_CFGCTL4; - - /* 0x114 : GPIO_CFGCTL5 */ - - union - { - struct - { - uint32_t reg_gpio_10_ie : 1; /* [ 0], r/w, 0x1 */ - uint32_t reg_gpio_10_smt : 1; /* [ 1], r/w, 0x1 */ - uint32_t reg_gpio_10_drv : 2; /* [ 3: 2], r/w, 0x0 */ - uint32_t reg_gpio_10_pu : 1; /* [ 4], r/w, 0x0 */ - uint32_t reg_gpio_10_pd : 1; /* [ 5], r/w, 0x0 */ - uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ - uint32_t reg_gpio_10_func_sel : 4; /* [11: 8], r/w, 0xb */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_gpio_11_ie : 1; /* [ 16], r/w, 0x1 */ - uint32_t reg_gpio_11_smt : 1; /* [ 17], r/w, 0x1 */ - uint32_t reg_gpio_11_drv : 2; /* [19:18], r/w, 0x0 */ - uint32_t reg_gpio_11_pu : 1; /* [ 20], r/w, 0x0 */ - uint32_t reg_gpio_11_pd : 1; /* [ 21], r/w, 0x0 */ - uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ - uint32_t reg_gpio_11_func_sel : 4; /* [27:24], r/w, 0xe */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } bf; - uint32_t word; - } GPIO_CFGCTL5; - - /* 0x118 : GPIO_CFGCTL6 */ - - union - { - struct - { - uint32_t reg_gpio_12_ie : 1; /* [ 0], r/w, 0x1 */ - uint32_t reg_gpio_12_smt : 1; /* [ 1], r/w, 0x1 */ - uint32_t reg_gpio_12_drv : 2; /* [ 3: 2], r/w, 0x0 */ - uint32_t reg_gpio_12_pu : 1; /* [ 4], r/w, 0x0 */ - uint32_t reg_gpio_12_pd : 1; /* [ 5], r/w, 0x0 */ - uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ - uint32_t reg_gpio_12_func_sel : 4; /* [11: 8], r/w, 0xe */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_gpio_13_ie : 1; /* [ 16], r/w, 0x1 */ - uint32_t reg_gpio_13_smt : 1; /* [ 17], r/w, 0x1 */ - uint32_t reg_gpio_13_drv : 2; /* [19:18], r/w, 0x0 */ - uint32_t reg_gpio_13_pu : 1; /* [ 20], r/w, 0x0 */ - uint32_t reg_gpio_13_pd : 1; /* [ 21], r/w, 0x0 */ - uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ - uint32_t reg_gpio_13_func_sel : 4; /* [27:24], r/w, 0xb */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } bf; - uint32_t word; - } GPIO_CFGCTL6; - - /* 0x11C : GPIO_CFGCTL7 */ - - union - { - struct - { - uint32_t reg_gpio_14_ie : 1; /* [ 0], r/w, 0x1 */ - uint32_t reg_gpio_14_smt : 1; /* [ 1], r/w, 0x1 */ - uint32_t reg_gpio_14_drv : 2; /* [ 3: 2], r/w, 0x0 */ - uint32_t reg_gpio_14_pu : 1; /* [ 4], r/w, 0x0 */ - uint32_t reg_gpio_14_pd : 1; /* [ 5], r/w, 0x0 */ - uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ - uint32_t reg_gpio_14_func_sel : 4; /* [11: 8], r/w, 0xe */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_gpio_15_ie : 1; /* [ 16], r/w, 0x1 */ - uint32_t reg_gpio_15_smt : 1; /* [ 17], r/w, 0x1 */ - uint32_t reg_gpio_15_drv : 2; /* [19:18], r/w, 0x0 */ - uint32_t reg_gpio_15_pu : 1; /* [ 20], r/w, 0x0 */ - uint32_t reg_gpio_15_pd : 1; /* [ 21], r/w, 0x0 */ - uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ - uint32_t reg_gpio_15_func_sel : 4; /* [27:24], r/w, 0xb */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } bf; - uint32_t word; - } GPIO_CFGCTL7; - - /* 0x120 : GPIO_CFGCTL8 */ - - union - { - struct - { - uint32_t reg_gpio_16_ie : 1; /* [ 0], r/w, 0x1 */ - uint32_t reg_gpio_16_smt : 1; /* [ 1], r/w, 0x1 */ - uint32_t reg_gpio_16_drv : 2; /* [ 3: 2], r/w, 0x0 */ - uint32_t reg_gpio_16_pu : 1; /* [ 4], r/w, 0x0 */ - uint32_t reg_gpio_16_pd : 1; /* [ 5], r/w, 0x0 */ - uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ - uint32_t reg_gpio_16_func_sel : 4; /* [11: 8], r/w, 0xb */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_gpio_17_ie : 1; /* [ 16], r/w, 0x1 */ - uint32_t reg_gpio_17_smt : 1; /* [ 17], r/w, 0x1 */ - uint32_t reg_gpio_17_drv : 2; /* [19:18], r/w, 0x0 */ - uint32_t reg_gpio_17_pu : 1; /* [ 20], r/w, 0x0 */ - uint32_t reg_gpio_17_pd : 1; /* [ 21], r/w, 0x0 */ - uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ - uint32_t reg_gpio_17_func_sel : 4; /* [27:24], r/w, 0xe */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } bf; - uint32_t word; - } GPIO_CFGCTL8; - - /* 0x124 : GPIO_CFGCTL9 */ - - union - { - struct - { - uint32_t reg_gpio_18_ie : 1; /* [ 0], r/w, 0x1 */ - uint32_t reg_gpio_18_smt : 1; /* [ 1], r/w, 0x1 */ - uint32_t reg_gpio_18_drv : 2; /* [ 3: 2], r/w, 0x0 */ - uint32_t reg_gpio_18_pu : 1; /* [ 4], r/w, 0x0 */ - uint32_t reg_gpio_18_pd : 1; /* [ 5], r/w, 0x0 */ - uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ - uint32_t reg_gpio_18_func_sel : 4; /* [11: 8], r/w, 0xb */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_gpio_19_ie : 1; /* [ 16], r/w, 0x1 */ - uint32_t reg_gpio_19_smt : 1; /* [ 17], r/w, 0x1 */ - uint32_t reg_gpio_19_drv : 2; /* [19:18], r/w, 0x0 */ - uint32_t reg_gpio_19_pu : 1; /* [ 20], r/w, 0x0 */ - uint32_t reg_gpio_19_pd : 1; /* [ 21], r/w, 0x0 */ - uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ - uint32_t reg_gpio_19_func_sel : 4; /* [27:24], r/w, 0xb */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } bf; - uint32_t word; - } GPIO_CFGCTL9; - - /* 0x128 : GPIO_CFGCTL10 */ - - union - { - struct - { - uint32_t reg_gpio_20_ie : 1; /* [ 0], r/w, 0x1 */ - uint32_t reg_gpio_20_smt : 1; /* [ 1], r/w, 0x1 */ - uint32_t reg_gpio_20_drv : 2; /* [ 3: 2], r/w, 0x0 */ - uint32_t reg_gpio_20_pu : 1; /* [ 4], r/w, 0x0 */ - uint32_t reg_gpio_20_pd : 1; /* [ 5], r/w, 0x0 */ - uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ - uint32_t reg_gpio_20_func_sel : 4; /* [11: 8], r/w, 0xb */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_gpio_21_ie : 1; /* [ 16], r/w, 0x1 */ - uint32_t reg_gpio_21_smt : 1; /* [ 17], r/w, 0x1 */ - uint32_t reg_gpio_21_drv : 2; /* [19:18], r/w, 0x0 */ - uint32_t reg_gpio_21_pu : 1; /* [ 20], r/w, 0x0 */ - uint32_t reg_gpio_21_pd : 1; /* [ 21], r/w, 0x0 */ - uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ - uint32_t reg_gpio_21_func_sel : 4; /* [27:24], r/w, 0xb */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } bf; - uint32_t word; - } GPIO_CFGCTL10; - - /* 0x12C : GPIO_CFGCTL11 */ - - union - { - struct - { - uint32_t reg_gpio_22_ie : 1; /* [ 0], r/w, 0x1 */ - uint32_t reg_gpio_22_smt : 1; /* [ 1], r/w, 0x1 */ - uint32_t reg_gpio_22_drv : 2; /* [ 3: 2], r/w, 0x0 */ - uint32_t reg_gpio_22_pu : 1; /* [ 4], r/w, 0x0 */ - uint32_t reg_gpio_22_pd : 1; /* [ 5], r/w, 0x0 */ - uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ - uint32_t reg_gpio_22_func_sel : 4; /* [11: 8], r/w, 0xb */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_gpio_23_ie : 1; /* [ 16], r/w, 0x1 */ - uint32_t reg_gpio_23_smt : 1; /* [ 17], r/w, 0x1 */ - uint32_t reg_gpio_23_drv : 2; /* [19:18], r/w, 0x0 */ - uint32_t reg_gpio_23_pu : 1; /* [ 20], r/w, 0x0 */ - uint32_t reg_gpio_23_pd : 1; /* [ 21], r/w, 0x0 */ - uint32_t reserved_22_31 : 10; /* [31:22], rsvd, 0x0 */ - } bf; - uint32_t word; - } GPIO_CFGCTL11; - - /* 0x130 : GPIO_CFGCTL12 */ - - union - { - struct - { - uint32_t reg_gpio_24_ie : 1; /* [ 0], r/w, 0x1 */ - uint32_t reg_gpio_24_smt : 1; /* [ 1], r/w, 0x1 */ - uint32_t reg_gpio_24_drv : 2; /* [ 3: 2], r/w, 0x0 */ - uint32_t reg_gpio_24_pu : 1; /* [ 4], r/w, 0x0 */ - uint32_t reg_gpio_24_pd : 1; /* [ 5], r/w, 0x1 */ - uint32_t reserved_6_15 : 10; /* [15: 6], rsvd, 0x0 */ - uint32_t reg_gpio_25_ie : 1; /* [ 16], r/w, 0x1 */ - uint32_t reg_gpio_25_smt : 1; /* [ 17], r/w, 0x1 */ - uint32_t reg_gpio_25_drv : 2; /* [19:18], r/w, 0x0 */ - uint32_t reg_gpio_25_pu : 1; /* [ 20], r/w, 0x0 */ - uint32_t reg_gpio_25_pd : 1; /* [ 21], r/w, 0x0 */ - uint32_t reserved_22_31 : 10; /* [31:22], rsvd, 0x0 */ - } bf; - uint32_t word; - } GPIO_CFGCTL12; - - /* 0x134 : GPIO_CFGCTL13 */ - - union - { - struct - { - uint32_t reg_gpio_26_ie : 1; /* [ 0], r/w, 0x1 */ - uint32_t reg_gpio_26_smt : 1; /* [ 1], r/w, 0x1 */ - uint32_t reg_gpio_26_drv : 2; /* [ 3: 2], r/w, 0x0 */ - uint32_t reg_gpio_26_pu : 1; /* [ 4], r/w, 0x0 */ - uint32_t reg_gpio_26_pd : 1; /* [ 5], r/w, 0x0 */ - uint32_t reserved_6_15 : 10; /* [15: 6], rsvd, 0x0 */ - uint32_t reg_gpio_27_ie : 1; /* [ 16], r/w, 0x1 */ - uint32_t reg_gpio_27_smt : 1; /* [ 17], r/w, 0x1 */ - uint32_t reg_gpio_27_drv : 2; /* [19:18], r/w, 0x0 */ - uint32_t reg_gpio_27_pu : 1; /* [ 20], r/w, 0x0 */ - uint32_t reg_gpio_27_pd : 1; /* [ 21], r/w, 0x0 */ - uint32_t reserved_22_31 : 10; /* [31:22], rsvd, 0x0 */ - } bf; - uint32_t word; - } GPIO_CFGCTL13; - - /* 0x138 : GPIO_CFGCTL14 */ - - union - { - struct - { - uint32_t reg_gpio_28_ie : 1; /* [ 0], r/w, 0x1 */ - uint32_t reg_gpio_28_smt : 1; /* [ 1], r/w, 0x1 */ - uint32_t reg_gpio_28_drv : 2; /* [ 3: 2], r/w, 0x0 */ - uint32_t reg_gpio_28_pu : 1; /* [ 4], r/w, 0x0 */ - uint32_t reg_gpio_28_pd : 1; /* [ 5], r/w, 0x0 */ - uint32_t reserved_6_31 : 26; /* [31: 6], rsvd, 0x0 */ - } bf; - uint32_t word; - } GPIO_CFGCTL14; - - /* 0x13c reserved */ - - uint8_t reserved_0x13c[68]; - - /* 0x180 : GPIO_CFGCTL30 */ - - union - { - struct - { - uint32_t reg_gpio_0_i : 1; /* [ 0], r, 0x0 */ - uint32_t reg_gpio_1_i : 1; /* [ 1], r, 0x0 */ - uint32_t reg_gpio_2_i : 1; /* [ 2], r, 0x0 */ - uint32_t reg_gpio_3_i : 1; /* [ 3], r, 0x0 */ - uint32_t reg_gpio_4_i : 1; /* [ 4], r, 0x0 */ - uint32_t reg_gpio_5_i : 1; /* [ 5], r, 0x0 */ - uint32_t reg_gpio_6_i : 1; /* [ 6], r, 0x0 */ - uint32_t reg_gpio_7_i : 1; /* [ 7], r, 0x0 */ - uint32_t reg_gpio_8_i : 1; /* [ 8], r, 0x0 */ - uint32_t reg_gpio_9_i : 1; /* [ 9], r, 0x0 */ - uint32_t reg_gpio_10_i : 1; /* [ 10], r, 0x0 */ - uint32_t reg_gpio_11_i : 1; /* [ 11], r, 0x0 */ - uint32_t reg_gpio_12_i : 1; /* [ 12], r, 0x0 */ - uint32_t reg_gpio_13_i : 1; /* [ 13], r, 0x0 */ - uint32_t reg_gpio_14_i : 1; /* [ 14], r, 0x0 */ - uint32_t reg_gpio_15_i : 1; /* [ 15], r, 0x0 */ - uint32_t reg_gpio_16_i : 1; /* [ 16], r, 0x0 */ - uint32_t reg_gpio_17_i : 1; /* [ 17], r, 0x0 */ - uint32_t reg_gpio_18_i : 1; /* [ 18], r, 0x0 */ - uint32_t reg_gpio_19_i : 1; /* [ 19], r, 0x0 */ - uint32_t reg_gpio_20_i : 1; /* [ 20], r, 0x0 */ - uint32_t reg_gpio_21_i : 1; /* [ 21], r, 0x0 */ - uint32_t reg_gpio_22_i : 1; /* [ 22], r, 0x0 */ - uint32_t reserved_23_31 : 9; /* [31:23], rsvd, 0x0 */ - } bf; - uint32_t word; - } GPIO_CFGCTL30; - - /* 0x184 : GPIO_CFGCTL31 */ - - union - { - struct - { - uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */ - } bf; - uint32_t word; - } GPIO_CFGCTL31; - - /* 0x188 : GPIO_CFGCTL32 */ - - union - { - struct - { - uint32_t reg_gpio_0_o : 1; /* [ 0], r/w, 0x0 */ - uint32_t reg_gpio_1_o : 1; /* [ 1], r/w, 0x0 */ - uint32_t reg_gpio_2_o : 1; /* [ 2], r/w, 0x0 */ - uint32_t reg_gpio_3_o : 1; /* [ 3], r/w, 0x0 */ - uint32_t reg_gpio_4_o : 1; /* [ 4], r/w, 0x0 */ - uint32_t reg_gpio_5_o : 1; /* [ 5], r/w, 0x0 */ - uint32_t reg_gpio_6_o : 1; /* [ 6], r/w, 0x0 */ - uint32_t reg_gpio_7_o : 1; /* [ 7], r/w, 0x0 */ - uint32_t reg_gpio_8_o : 1; /* [ 8], r/w, 0x0 */ - uint32_t reg_gpio_9_o : 1; /* [ 9], r/w, 0x0 */ - uint32_t reg_gpio_10_o : 1; /* [ 10], r/w, 0x0 */ - uint32_t reg_gpio_11_o : 1; /* [ 11], r/w, 0x0 */ - uint32_t reg_gpio_12_o : 1; /* [ 12], r/w, 0x0 */ - uint32_t reg_gpio_13_o : 1; /* [ 13], r/w, 0x0 */ - uint32_t reg_gpio_14_o : 1; /* [ 14], r/w, 0x0 */ - uint32_t reg_gpio_15_o : 1; /* [ 15], r/w, 0x0 */ - uint32_t reg_gpio_16_o : 1; /* [ 16], r/w, 0x0 */ - uint32_t reg_gpio_17_o : 1; /* [ 17], r/w, 0x0 */ - uint32_t reg_gpio_18_o : 1; /* [ 18], r/w, 0x0 */ - uint32_t reg_gpio_19_o : 1; /* [ 19], r/w, 0x0 */ - uint32_t reg_gpio_20_o : 1; /* [ 20], r/w, 0x0 */ - uint32_t reg_gpio_21_o : 1; /* [ 21], r/w, 0x0 */ - uint32_t reg_gpio_22_o : 1; /* [ 22], r/w, 0x0 */ - uint32_t reserved_23_31 : 9; /* [31:23], rsvd, 0x0 */ - } bf; - uint32_t word; - } GPIO_CFGCTL32; - - /* 0x18C : GPIO_CFGCTL33 */ - - union - { - struct - { - uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */ - } bf; - uint32_t word; - } GPIO_CFGCTL33; - - /* 0x190 : GPIO_CFGCTL34 */ - - union - { - struct - { - uint32_t reg_gpio_0_oe : 1; /* [ 0], r/w, 0x0 */ - uint32_t reg_gpio_1_oe : 1; /* [ 1], r/w, 0x0 */ - uint32_t reg_gpio_2_oe : 1; /* [ 2], r/w, 0x0 */ - uint32_t reg_gpio_3_oe : 1; /* [ 3], r/w, 0x0 */ - uint32_t reg_gpio_4_oe : 1; /* [ 4], r/w, 0x0 */ - uint32_t reg_gpio_5_oe : 1; /* [ 5], r/w, 0x0 */ - uint32_t reg_gpio_6_oe : 1; /* [ 6], r/w, 0x0 */ - uint32_t reg_gpio_7_oe : 1; /* [ 7], r/w, 0x0 */ - uint32_t reg_gpio_8_oe : 1; /* [ 8], r/w, 0x0 */ - uint32_t reg_gpio_9_oe : 1; /* [ 9], r/w, 0x0 */ - uint32_t reg_gpio_10_oe : 1; /* [ 10], r/w, 0x0 */ - uint32_t reg_gpio_11_oe : 1; /* [ 11], r/w, 0x0 */ - uint32_t reg_gpio_12_oe : 1; /* [ 12], r/w, 0x0 */ - uint32_t reg_gpio_13_oe : 1; /* [ 13], r/w, 0x0 */ - uint32_t reg_gpio_14_oe : 1; /* [ 14], r/w, 0x0 */ - uint32_t reg_gpio_15_oe : 1; /* [ 15], r/w, 0x0 */ - uint32_t reg_gpio_16_oe : 1; /* [ 16], r/w, 0x0 */ - uint32_t reg_gpio_17_oe : 1; /* [ 17], r/w, 0x0 */ - uint32_t reg_gpio_18_oe : 1; /* [ 18], r/w, 0x0 */ - uint32_t reg_gpio_19_oe : 1; /* [ 19], r/w, 0x0 */ - uint32_t reg_gpio_20_oe : 1; /* [ 20], r/w, 0x0 */ - uint32_t reg_gpio_21_oe : 1; /* [ 21], r/w, 0x0 */ - uint32_t reg_gpio_22_oe : 1; /* [ 22], r/w, 0x0 */ - uint32_t reserved_23_31 : 9; /* [31:23], rsvd, 0x0 */ - } bf; - uint32_t word; - } GPIO_CFGCTL34; - - /* 0x194 : GPIO_CFGCTL35 */ - - union - { - struct - { - uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */ - } bf; - uint32_t word; - } GPIO_CFGCTL35; - - /* 0x198 reserved */ - - uint8_t reserved_0x198[8]; - - /* 0x1A0 : GPIO_INT_MASK1 */ - - union - { - struct - { - uint32_t reg_gpio_int_mask1 : 32; /* [31: 0], r/w, 0xffffffffL */ - } bf; - uint32_t word; - } GPIO_INT_MASK1; - - /* 0x1a4 reserved */ - - uint8_t reserved_0x1a4[4]; - - /* 0x1A8 : GPIO_INT_STAT1 */ - - union - { - struct - { - uint32_t gpio_int_stat1 : 32; /* [31: 0], r, 0x0 */ - } bf; - uint32_t word; - } GPIO_INT_STAT1; - - /* 0x1ac reserved */ - - uint8_t reserved_0x1ac[4]; - - /* 0x1B0 : GPIO_INT_CLR1 */ - - union - { - struct - { - uint32_t reg_gpio_int_clr1 : 32; /* [31: 0], r/w, 0x0 */ - } bf; - uint32_t word; - } GPIO_INT_CLR1; - - /* 0x1b4 reserved */ - - uint8_t reserved_0x1b4[12]; - - /* 0x1C0 : GPIO_INT_MODE_SET1 */ - - union - { - struct - { - uint32_t reg_gpio_int_mode_set1 : 32; /* [31: 0], r/w, 0x0 */ - } bf; - uint32_t word; - } GPIO_INT_MODE_SET1; - - /* 0x1C4 : GPIO_INT_MODE_SET2 */ - - union - { - struct - { - uint32_t reg_gpio_int_mode_set2 : 32; /* [31: 0], r/w, 0x0 */ - } bf; - uint32_t word; - } GPIO_INT_MODE_SET2; - - /* 0x1C8 : GPIO_INT_MODE_SET3 */ - - union - { - struct - { - uint32_t reg_gpio_int_mode_set3 : 32; /* [31: 0], r/w, 0x0 */ - } bf; - uint32_t word; - } GPIO_INT_MODE_SET3; - - /* 0x1cc reserved */ - - uint8_t reserved_0x1cc[88]; - - /* 0x224 : led_driver */ - - union - { - struct - { - uint32_t led_din_reg : 1; /* [ 0], r/w, 0x0 */ - uint32_t led_din_sel : 1; /* [ 1], r/w, 0x0 */ - uint32_t led_din_polarity_sel : 1; /* [ 2], r/w, 0x0 */ - uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */ - uint32_t leddrv_ibias : 4; /* [ 7: 4], r/w, 0x8 */ - uint32_t ir_rx_gpio_sel : 2; /* [ 9: 8], r/w, 0x0 */ - uint32_t reserved_10_30 : 21; /* [30:10], rsvd, 0x0 */ - uint32_t pu_leddrv : 1; /* [ 31], r/w, 0x0 */ - } bf; - uint32_t word; - } led_driver; - - /* 0x228 reserved */ - - uint8_t reserved_0x228[224]; - - /* 0x308 : gpdac_ctrl */ - - union - { - struct - { - uint32_t gpdaca_rstn_ana : 1; /* [ 0], r/w, 0x1 */ - uint32_t gpdacb_rstn_ana : 1; /* [ 1], r/w, 0x1 */ - uint32_t reserved_2_6 : 5; /* [ 6: 2], rsvd, 0x0 */ - uint32_t gpdac_test_en : 1; /* [ 7], r/w, 0x0 */ - uint32_t gpdac_ref_sel : 1; /* [ 8], r/w, 0x0 */ - uint32_t gpdac_test_sel : 3; /* [11: 9], r/w, 0x0 */ - uint32_t reserved_12_23 : 12; /* [23:12], rsvd, 0x0 */ - uint32_t gpdac_reserved : 8; /* [31:24], r/w, 0xf */ - } bf; - uint32_t word; - } gpdac_ctrl; - - /* 0x30C : gpdac_actrl */ - - union - { - struct - { - uint32_t gpdac_a_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t gpdac_ioa_en : 1; /* [ 1], r/w, 0x0 */ - uint32_t reserved_2_17 : 16; /* [17: 2], rsvd, 0x0 */ - uint32_t gpdac_a_rng : 2; /* [19:18], r/w, 0x3 */ - uint32_t gpdac_a_outmux : 3; /* [22:20], r/w, 0x0 */ - uint32_t reserved_23_31 : 9; /* [31:23], rsvd, 0x0 */ - } bf; - uint32_t word; - } gpdac_actrl; - - /* 0x310 : gpdac_bctrl */ - - union - { - struct - { - uint32_t gpdac_b_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t gpdac_iob_en : 1; /* [ 1], r/w, 0x0 */ - uint32_t reserved_2_17 : 16; /* [17: 2], rsvd, 0x0 */ - uint32_t gpdac_b_rng : 2; /* [19:18], r/w, 0x3 */ - uint32_t gpdac_b_outmux : 3; /* [22:20], r/w, 0x0 */ - uint32_t reserved_23_31 : 9; /* [31:23], rsvd, 0x0 */ - } bf; - uint32_t word; - } gpdac_bctrl; - - /* 0x314 : gpdac_data */ - - union - { - struct - { - uint32_t gpdac_b_data : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t gpdac_a_data : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } bf; - uint32_t word; - } gpdac_data; - - /* 0x318 reserved */ - - uint8_t reserved_0x318[3048]; - - /* 0xF00 : tzc_glb_ctrl_0 */ - - union - { - struct - { - uint32_t tzc_glb_swrst_s00_lock : 1; /* [ 0], r, 0x0 */ - uint32_t tzc_glb_swrst_s01_lock : 1; /* [ 1], r, 0x0 */ - uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */ - uint32_t tzc_glb_swrst_s30_lock : 1; /* [ 8], r, 0x0 */ - uint32_t reserved_9_11 : 3; /* [11: 9], rsvd, 0x0 */ - uint32_t tzc_glb_ctrl_pwron_rst_lock : 1; /* [ 12], r, 0x0 */ - uint32_t tzc_glb_ctrl_cpu_reset_lock : 1; /* [ 13], r, 0x0 */ - uint32_t tzc_glb_ctrl_sys_reset_lock : 1; /* [ 14], r, 0x0 */ - uint32_t tzc_glb_ctrl_ungated_ap_lock : 1; /* [ 15], r, 0x0 */ - uint32_t reserved_16_24 : 9; /* [24:16], rsvd, 0x0 */ - uint32_t tzc_glb_misc_lock : 1; /* [ 25], r, 0x0 */ - uint32_t tzc_glb_sram_lock : 1; /* [ 26], r, 0x0 */ - uint32_t tzc_glb_l2c_lock : 1; /* [ 27], r, 0x0 */ - uint32_t tzc_glb_bmx_lock : 1; /* [ 28], r, 0x0 */ - uint32_t tzc_glb_dbg_lock : 1; /* [ 29], r, 0x0 */ - uint32_t tzc_glb_mbist_lock : 1; /* [ 30], r, 0x0 */ - uint32_t tzc_glb_clk_lock : 1; /* [ 31], r, 0x0 */ - } bf; - uint32_t word; - } tzc_glb_ctrl_0; - - /* 0xF04 : tzc_glb_ctrl_1 */ - - union - { - struct - { - uint32_t tzc_glb_swrst_s20_lock : 1; /* [ 0], r, 0x0 */ - uint32_t tzc_glb_swrst_s21_lock : 1; /* [ 1], r, 0x0 */ - uint32_t tzc_glb_swrst_s22_lock : 1; /* [ 2], r, 0x0 */ - uint32_t tzc_glb_swrst_s23_lock : 1; /* [ 3], r, 0x0 */ - uint32_t tzc_glb_swrst_s24_lock : 1; /* [ 4], r, 0x0 */ - uint32_t tzc_glb_swrst_s25_lock : 1; /* [ 5], r, 0x0 */ - uint32_t tzc_glb_swrst_s26_lock : 1; /* [ 6], r, 0x0 */ - uint32_t tzc_glb_swrst_s27_lock : 1; /* [ 7], r, 0x0 */ - uint32_t tzc_glb_swrst_s28_lock : 1; /* [ 8], r, 0x0 */ - uint32_t tzc_glb_swrst_s29_lock : 1; /* [ 9], r, 0x0 */ - uint32_t tzc_glb_swrst_s2a_lock : 1; /* [ 10], r, 0x0 */ - uint32_t tzc_glb_swrst_s2b_lock : 1; /* [ 11], r, 0x0 */ - uint32_t tzc_glb_swrst_s2c_lock : 1; /* [ 12], r, 0x0 */ - uint32_t tzc_glb_swrst_s2d_lock : 1; /* [ 13], r, 0x0 */ - uint32_t tzc_glb_swrst_s2e_lock : 1; /* [ 14], r, 0x0 */ - uint32_t tzc_glb_swrst_s2f_lock : 1; /* [ 15], r, 0x0 */ - uint32_t tzc_glb_swrst_s10_lock : 1; /* [ 16], r, 0x0 */ - uint32_t tzc_glb_swrst_s11_lock : 1; /* [ 17], r, 0x0 */ - uint32_t tzc_glb_swrst_s12_lock : 1; /* [ 18], r, 0x0 */ - uint32_t tzc_glb_swrst_s13_lock : 1; /* [ 19], r, 0x0 */ - uint32_t tzc_glb_swrst_s14_lock : 1; /* [ 20], r, 0x0 */ - uint32_t tzc_glb_swrst_s15_lock : 1; /* [ 21], r, 0x0 */ - uint32_t tzc_glb_swrst_s16_lock : 1; /* [ 22], r, 0x0 */ - uint32_t tzc_glb_swrst_s17_lock : 1; /* [ 23], r, 0x0 */ - uint32_t tzc_glb_swrst_s18_lock : 1; /* [ 24], r, 0x0 */ - uint32_t tzc_glb_swrst_s19_lock : 1; /* [ 25], r, 0x0 */ - uint32_t tzc_glb_swrst_s1a_lock : 1; /* [ 26], r, 0x0 */ - uint32_t tzc_glb_swrst_s1b_lock : 1; /* [ 27], r, 0x0 */ - uint32_t tzc_glb_swrst_s1c_lock : 1; /* [ 28], r, 0x0 */ - uint32_t tzc_glb_swrst_s1d_lock : 1; /* [ 29], r, 0x0 */ - uint32_t tzc_glb_swrst_s1e_lock : 1; /* [ 30], r, 0x0 */ - uint32_t tzc_glb_swrst_s1f_lock : 1; /* [ 31], r, 0x0 */ - } bf; - uint32_t word; - } tzc_glb_ctrl_1; - - /* 0xF08 : tzc_glb_ctrl_2 */ - - union - { - struct - { - uint32_t tzc_glb_gpio_0_lock : 1; /* [ 0], r, 0x0 */ - uint32_t tzc_glb_gpio_1_lock : 1; /* [ 1], r, 0x0 */ - uint32_t tzc_glb_gpio_2_lock : 1; /* [ 2], r, 0x0 */ - uint32_t tzc_glb_gpio_3_lock : 1; /* [ 3], r, 0x0 */ - uint32_t tzc_glb_gpio_4_lock : 1; /* [ 4], r, 0x0 */ - uint32_t tzc_glb_gpio_5_lock : 1; /* [ 5], r, 0x0 */ - uint32_t tzc_glb_gpio_6_lock : 1; /* [ 6], r, 0x0 */ - uint32_t tzc_glb_gpio_7_lock : 1; /* [ 7], r, 0x0 */ - uint32_t tzc_glb_gpio_8_lock : 1; /* [ 8], r, 0x0 */ - uint32_t tzc_glb_gpio_9_lock : 1; /* [ 9], r, 0x0 */ - uint32_t tzc_glb_gpio_10_lock : 1; /* [ 10], r, 0x0 */ - uint32_t tzc_glb_gpio_11_lock : 1; /* [ 11], r, 0x0 */ - uint32_t tzc_glb_gpio_12_lock : 1; /* [ 12], r, 0x0 */ - uint32_t tzc_glb_gpio_13_lock : 1; /* [ 13], r, 0x0 */ - uint32_t tzc_glb_gpio_14_lock : 1; /* [ 14], r, 0x0 */ - uint32_t tzc_glb_gpio_15_lock : 1; /* [ 15], r, 0x0 */ - uint32_t tzc_glb_gpio_16_lock : 1; /* [ 16], r, 0x0 */ - uint32_t tzc_glb_gpio_17_lock : 1; /* [ 17], r, 0x0 */ - uint32_t tzc_glb_gpio_18_lock : 1; /* [ 18], r, 0x0 */ - uint32_t tzc_glb_gpio_19_lock : 1; /* [ 19], r, 0x0 */ - uint32_t tzc_glb_gpio_20_lock : 1; /* [ 20], r, 0x0 */ - uint32_t tzc_glb_gpio_21_lock : 1; /* [ 21], r, 0x0 */ - uint32_t tzc_glb_gpio_22_lock : 1; /* [ 22], r, 0x0 */ - uint32_t tzc_glb_gpio_23_lock : 1; /* [ 23], r, 0x0 */ - uint32_t tzc_glb_gpio_24_lock : 1; /* [ 24], r, 0x0 */ - uint32_t tzc_glb_gpio_25_lock : 1; /* [ 25], r, 0x0 */ - uint32_t tzc_glb_gpio_26_lock : 1; /* [ 26], r, 0x0 */ - uint32_t tzc_glb_gpio_27_lock : 1; /* [ 27], r, 0x0 */ - uint32_t tzc_glb_gpio_28_lock : 1; /* [ 28], r, 0x0 */ - uint32_t reserved_29_31 : 3; /* [31:29], rsvd, 0x0 */ - } bf; - uint32_t word; - } tzc_glb_ctrl_2; - - /* 0xF0C : tzc_glb_ctrl_3 */ - - union - { - struct - { - uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */ - } bf; - uint32_t word; - } tzc_glb_ctrl_3; -}; - -typedef volatile struct glb_reg_s glb_reg_t; - -struct glb_gpio_reg_s -{ - /* 0x0 : GPIO_CFGCTL */ - - union - { - struct - { - uint32_t reg_gpio_0_ie : 1; /* [ 0], r/w, 0x1 */ - uint32_t reg_gpio_0_smt : 1; /* [ 1], r/w, 0x1 */ - uint32_t reg_gpio_0_drv : 2; /* [ 3: 2], r/w, 0x0 */ - uint32_t reg_gpio_0_pu : 1; /* [ 4], r/w, 0x0 */ - uint32_t reg_gpio_0_pd : 1; /* [ 5], r/w, 0x0 */ - uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ - uint32_t reg_gpio_0_func_sel : 4; /* [11: 8], r/w, 0x1 */ - uint32_t real_gpio_0_func_sel : 4; /* [15:12], r, 0x1 */ - uint32_t reg_gpio_1_ie : 1; /* [ 16], r/w, 0x1 */ - uint32_t reg_gpio_1_smt : 1; /* [ 17], r/w, 0x1 */ - uint32_t reg_gpio_1_drv : 2; /* [19:18], r/w, 0x0 */ - uint32_t reg_gpio_1_pu : 1; /* [ 20], r/w, 0x0 */ - uint32_t reg_gpio_1_pd : 1; /* [ 21], r/w, 0x0 */ - uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ - uint32_t reg_gpio_1_func_sel : 4; /* [27:24], r/w, 0x1 */ - uint32_t real_gpio_1_func_sel : 4; /* [31:28], r, 0x1 */ - } bf; - uint32_t word; - } GPIO_CFGCTL; -}; - -typedef volatile struct glb_gpio_reg_s glb_gpio_reg_t; - /**************************************************************************** * Public Data ****************************************************************************/ @@ -5767,34 +4228,7 @@ extern "C" #endif /**************************************************************************** - * Inline Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: - * - * Description: - * Description of the operation of the inline function. - * - * Input Parameters: - * A list of input parameters, one-per-line, appears here along with a - * description of each input parameter. - * - * Returned Value: - * Description of the value returned by this function (if any), - * including an enumeration of all possible error values. - * - * Assumptions/Limitations: - * Anything else that one might need to know to use this function. - * - ****************************************************************************/ - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: + * Name: bl602_glb_uart_fun_sel * * Description: * Select UART signal function. @@ -5808,10 +4242,10 @@ extern "C" * ****************************************************************************/ -void glb_uart_fun_sel(enum glb_uart_sig_e sig, enum glb_uart_sig_fun_e fun); +void bl602_glb_uart_fun_sel(int sig, int fun); /**************************************************************************** - * Name: glb_ahb_slave1_reset + * Name: bl602_glb_ahb_slave1_reset * * Description: * Select UART signal function. @@ -5825,7 +4259,7 @@ void glb_uart_fun_sel(enum glb_uart_sig_e sig, enum glb_uart_sig_fun_e fun); * ****************************************************************************/ -void glb_ahb_slave1_reset(enum bl_ahb_slave1_e slave1); +void bl602_glb_ahb_slave1_reset(uint32_t slave1); #undef EXTERN #ifdef __cplusplus diff --git a/arch/risc-v/src/bl602/hardware/bl602_gpio.h b/arch/risc-v/src/bl602/hardware/bl602_gpio.h index 2b21aedf749..e7fb15019a0 100644 --- a/arch/risc-v/src/bl602/hardware/bl602_gpio.h +++ b/arch/risc-v/src/bl602/hardware/bl602_gpio.h @@ -1,6 +1,9 @@ /**************************************************************************** * arch/risc-v/src/bl602/hardware/bl602_gpio.h * + * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with * this work for additional information regarding copyright ownership. The @@ -33,27 +36,27 @@ /* Input Floating Mode */ -#define GPIO_MODE_INPUT ((uint32_t)0x00000000U) +#define GPIO_MODE_INPUT (0x00000000) /* Output Push Pull Mode */ -#define GPIO_MODE_OUTPUT ((uint32_t)0x00000001U) +#define GPIO_MODE_OUTPUT (0x00000001) /* Alternate function */ -#define GPIO_MODE_AF ((uint32_t)0x00000002U) +#define GPIO_MODE_AF (0x00000002) /* GPIO pull up */ -#define GPIO_PULL_UP ((uint32_t)0x00000000U) +#define GPIO_PULL_UP (0x00000000) /* GPIO pull down */ -#define GPIO_PULL_DOWN ((uint32_t)0x00000001U) +#define GPIO_PULL_DOWN (0x00000001) /* GPIO no pull up or down */ -#define GPIO_PULL_NONE ((uint32_t)0x00000002U) +#define GPIO_PULL_NONE (0x00000002) /* GPIO0 function definition */ @@ -406,56 +409,50 @@ #ifndef __ASSEMBLY__ -enum gpio_pins_e -{ - GLB_GPIO_PIN_0 = 0, - GLB_GPIO_PIN_1, - GLB_GPIO_PIN_2, - GLB_GPIO_PIN_3, - GLB_GPIO_PIN_4, - GLB_GPIO_PIN_5, - GLB_GPIO_PIN_6, - GLB_GPIO_PIN_7, - GLB_GPIO_PIN_8, - GLB_GPIO_PIN_9, - GLB_GPIO_PIN_10, - GLB_GPIO_PIN_11, - GLB_GPIO_PIN_12, - GLB_GPIO_PIN_13, - GLB_GPIO_PIN_14, - GLB_GPIO_PIN_15, - GLB_GPIO_PIN_16, - GLB_GPIO_PIN_17, - GLB_GPIO_PIN_18, - GLB_GPIO_PIN_19, - GLB_GPIO_PIN_20, - GLB_GPIO_PIN_21, - GLB_GPIO_PIN_22, - GLB_GPIO_PIN_MAX -}; +#define GLB_GPIO_PIN_0 0 +#define GLB_GPIO_PIN_1 1 +#define GLB_GPIO_PIN_2 2 +#define GLB_GPIO_PIN_3 3 +#define GLB_GPIO_PIN_4 4 +#define GLB_GPIO_PIN_5 5 +#define GLB_GPIO_PIN_6 6 +#define GLB_GPIO_PIN_7 7 +#define GLB_GPIO_PIN_8 8 +#define GLB_GPIO_PIN_9 9 +#define GLB_GPIO_PIN_10 10 +#define GLB_GPIO_PIN_11 11 +#define GLB_GPIO_PIN_12 12 +#define GLB_GPIO_PIN_13 13 +#define GLB_GPIO_PIN_14 14 +#define GLB_GPIO_PIN_15 15 +#define GLB_GPIO_PIN_16 16 +#define GLB_GPIO_PIN_17 17 +#define GLB_GPIO_PIN_18 18 +#define GLB_GPIO_PIN_19 19 +#define GLB_GPIO_PIN_20 20 +#define GLB_GPIO_PIN_21 21 +#define GLB_GPIO_PIN_22 22 +#define GLB_GPIO_PIN_MA 23 -enum gpio_fun_e -{ - GPIO_FUN_SDIO = 1, - GPIO_FUN_FLASH = 2, - GPIO_FUN_SPI = 4, - GPIO_FUN_I2C = 6, - GPIO_FUN_UART = 7, - GPIO_FUN_PWM = 8, - GPIO_FUN_EXT_PA = 8, - GPIO_FUN_ANALOG = 10, - GPIO_FUN_SWGPIO = 11, - GPIO_FUN_JTAG = 14 -}; +#define GPIO_FUN_SDIO 1 +#define GPIO_FUN_FLASH 2 +#define GPIO_FUN_SPI 4 +#define GPIO_FUN_I2C 6 +#define GPIO_FUN_UART 7 +#define GPIO_FUN_PWM 8 +#define GPIO_FUN_EXT_PA 8 +#define GPIO_FUN_ANALOG 10 +#define GPIO_FUN_SWGPIO 11 +#define GPIO_FUN_JTAG 14 struct gpio_cfg_s { - enum gpio_pins_e gpio_pin; - enum gpio_fun_e gpio_fun; - int gpio_mode; - int pull_type; - int drive; - int smt_ctrl; + int gpio_pin; + int gpio_fun; + int gpio_mode; + int pull_type; + int drive; + int smt_ctrl; }; /**************************************************************************** @@ -479,7 +476,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: gpio_init + * Name: bl602_gpio_init * * Description: * Init a gpio pin. @@ -496,7 +493,7 @@ extern "C" * ****************************************************************************/ -EXTERN void gpio_init(struct gpio_cfg_s *cfg); +EXTERN void bl602_gpio_init(struct gpio_cfg_s *cfg); #undef EXTERN #ifdef __cplusplus diff --git a/arch/risc-v/src/bl602/hardware/bl602_hbn.h b/arch/risc-v/src/bl602/hardware/bl602_hbn.h index 4493110b2ae..96babd8f22d 100644 --- a/arch/risc-v/src/bl602/hardware/bl602_hbn.h +++ b/arch/risc-v/src/bl602/hardware/bl602_hbn.h @@ -1,6 +1,9 @@ /**************************************************************************** * arch/risc-v/src/bl602/hardware/bl602_hbn.h * + * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with * this work for additional information regarding copyright ownership. The @@ -35,601 +38,599 @@ #define HBN_CTL_OFFSET (0x0) #define HBN_RTC_CTL HBN_RTC_CTL -#define HBN_RTC_CTL_POS (0U) -#define HBN_RTC_CTL_LEN (7U) -#define HBN_RTC_CTL_MSK (((1U << HBN_RTC_CTL_LEN) - 1) << HBN_RTC_CTL_POS) -#define HBN_RTC_CTL_UMSK (~(((1U << HBN_RTC_CTL_LEN) - 1) << HBN_RTC_CTL_POS)) +#define HBN_RTC_CTL_POS (0) +#define HBN_RTC_CTL_LEN (7) +#define HBN_RTC_CTL_MSK (((1 << HBN_RTC_CTL_LEN) - 1) << HBN_RTC_CTL_POS) +#define HBN_RTC_CTL_UMSK (~(((1 << HBN_RTC_CTL_LEN) - 1) << HBN_RTC_CTL_POS)) #define HBN_MODE HBN_MODE -#define HBN_MODE_POS (7U) -#define HBN_MODE_LEN (1U) -#define HBN_MODE_MSK (((1U << HBN_MODE_LEN) - 1) << HBN_MODE_POS) -#define HBN_MODE_UMSK (~(((1U << HBN_MODE_LEN) - 1) << HBN_MODE_POS)) +#define HBN_MODE_POS (7) +#define HBN_MODE_LEN (1) +#define HBN_MODE_MSK (((1 << HBN_MODE_LEN) - 1) << HBN_MODE_POS) +#define HBN_MODE_UMSK (~(((1 << HBN_MODE_LEN) - 1) << HBN_MODE_POS)) #define HBN_TRAP_MODE HBN_TRAP_MODE -#define HBN_TRAP_MODE_POS (8U) -#define HBN_TRAP_MODE_LEN (1U) +#define HBN_TRAP_MODE_POS (8) +#define HBN_TRAP_MODE_LEN (1) #define HBN_TRAP_MODE_MSK \ - (((1U << HBN_TRAP_MODE_LEN) - 1) << HBN_TRAP_MODE_POS) + (((1 << HBN_TRAP_MODE_LEN) - 1) << HBN_TRAP_MODE_POS) #define HBN_TRAP_MODE_UMSK \ - (~(((1U << HBN_TRAP_MODE_LEN) - 1) << HBN_TRAP_MODE_POS)) + (~(((1 << HBN_TRAP_MODE_LEN) - 1) << HBN_TRAP_MODE_POS)) #define HBN_PWRDN_HBN_CORE HBN_PWRDN_HBN_CORE -#define HBN_PWRDN_HBN_CORE_POS (9U) -#define HBN_PWRDN_HBN_CORE_LEN (1U) +#define HBN_PWRDN_HBN_CORE_POS (9) +#define HBN_PWRDN_HBN_CORE_LEN (1) #define HBN_PWRDN_HBN_CORE_MSK \ - (((1U << HBN_PWRDN_HBN_CORE_LEN) - 1) << HBN_PWRDN_HBN_CORE_POS) + (((1 << HBN_PWRDN_HBN_CORE_LEN) - 1) << HBN_PWRDN_HBN_CORE_POS) #define HBN_PWRDN_HBN_CORE_UMSK \ - (~(((1U << HBN_PWRDN_HBN_CORE_LEN) - 1) << HBN_PWRDN_HBN_CORE_POS)) + (~(((1 << HBN_PWRDN_HBN_CORE_LEN) - 1) << HBN_PWRDN_HBN_CORE_POS)) #define HBN_PWRDN_HBN_RTC HBN_PWRDN_HBN_RTC -#define HBN_PWRDN_HBN_RTC_POS (11U) -#define HBN_PWRDN_HBN_RTC_LEN (1U) +#define HBN_PWRDN_HBN_RTC_POS (11) +#define HBN_PWRDN_HBN_RTC_LEN (1) #define HBN_PWRDN_HBN_RTC_MSK \ - (((1U << HBN_PWRDN_HBN_RTC_LEN) - 1) << HBN_PWRDN_HBN_RTC_POS) + (((1 << HBN_PWRDN_HBN_RTC_LEN) - 1) << HBN_PWRDN_HBN_RTC_POS) #define HBN_PWRDN_HBN_RTC_UMSK \ - (~(((1U << HBN_PWRDN_HBN_RTC_LEN) - 1) << HBN_PWRDN_HBN_RTC_POS)) + (~(((1 << HBN_PWRDN_HBN_RTC_LEN) - 1) << HBN_PWRDN_HBN_RTC_POS)) #define HBN_SW_RST HBN_SW_RST -#define HBN_SW_RST_POS (12U) -#define HBN_SW_RST_LEN (1U) -#define HBN_SW_RST_MSK (((1U << HBN_SW_RST_LEN) - 1) << HBN_SW_RST_POS) -#define HBN_SW_RST_UMSK (~(((1U << HBN_SW_RST_LEN) - 1) << HBN_SW_RST_POS)) +#define HBN_SW_RST_POS (12) +#define HBN_SW_RST_LEN (1) +#define HBN_SW_RST_MSK (((1 << HBN_SW_RST_LEN) - 1) << HBN_SW_RST_POS) +#define HBN_SW_RST_UMSK (~(((1 << HBN_SW_RST_LEN) - 1) << HBN_SW_RST_POS)) #define HBN_DIS_PWR_OFF_LDO11 HBN_DIS_PWR_OFF_LDO11 -#define HBN_DIS_PWR_OFF_LDO11_POS (13U) -#define HBN_DIS_PWR_OFF_LDO11_LEN (1U) +#define HBN_DIS_PWR_OFF_LDO11_POS (13) +#define HBN_DIS_PWR_OFF_LDO11_LEN (1) #define HBN_DIS_PWR_OFF_LDO11_MSK \ - (((1U << HBN_DIS_PWR_OFF_LDO11_LEN) - 1) << HBN_DIS_PWR_OFF_LDO11_POS) + (((1 << HBN_DIS_PWR_OFF_LDO11_LEN) - 1) << HBN_DIS_PWR_OFF_LDO11_POS) #define HBN_DIS_PWR_OFF_LDO11_UMSK \ - (~(((1U << HBN_DIS_PWR_OFF_LDO11_LEN) - 1) << HBN_DIS_PWR_OFF_LDO11_POS)) + (~(((1 << HBN_DIS_PWR_OFF_LDO11_LEN) - 1) << HBN_DIS_PWR_OFF_LDO11_POS)) #define HBN_DIS_PWR_OFF_LDO11_RT HBN_DIS_PWR_OFF_LDO11_RT -#define HBN_DIS_PWR_OFF_LDO11_RT_POS (14U) -#define HBN_DIS_PWR_OFF_LDO11_RT_LEN (1U) +#define HBN_DIS_PWR_OFF_LDO11_RT_POS (14) +#define HBN_DIS_PWR_OFF_LDO11_RT_LEN (1) #define HBN_DIS_PWR_OFF_LDO11_RT_MSK \ - (((1U << HBN_DIS_PWR_OFF_LDO11_RT_LEN) - 1) << HBN_DIS_PWR_OFF_LDO11_RT_POS) + (((1 << HBN_DIS_PWR_OFF_LDO11_RT_LEN) - 1) << HBN_DIS_PWR_OFF_LDO11_RT_POS) #define HBN_DIS_PWR_OFF_LDO11_RT_UMSK \ - (~(((1U << HBN_DIS_PWR_OFF_LDO11_RT_LEN) - 1) \ + (~(((1 << HBN_DIS_PWR_OFF_LDO11_RT_LEN) - 1) \ << HBN_DIS_PWR_OFF_LDO11_RT_POS)) #define HBN_LDO11_RT_VOUT_SEL HBN_LDO11_RT_VOUT_SEL -#define HBN_LDO11_RT_VOUT_SEL_POS (15U) -#define HBN_LDO11_RT_VOUT_SEL_LEN (4U) +#define HBN_LDO11_RT_VOUT_SEL_POS (15) +#define HBN_LDO11_RT_VOUT_SEL_LEN (4) #define HBN_LDO11_RT_VOUT_SEL_MSK \ - (((1U << HBN_LDO11_RT_VOUT_SEL_LEN) - 1) << HBN_LDO11_RT_VOUT_SEL_POS) + (((1 << HBN_LDO11_RT_VOUT_SEL_LEN) - 1) << HBN_LDO11_RT_VOUT_SEL_POS) #define HBN_LDO11_RT_VOUT_SEL_UMSK \ - (~(((1U << HBN_LDO11_RT_VOUT_SEL_LEN) - 1) << HBN_LDO11_RT_VOUT_SEL_POS)) + (~(((1 << HBN_LDO11_RT_VOUT_SEL_LEN) - 1) << HBN_LDO11_RT_VOUT_SEL_POS)) #define HBN_LDO11_AON_VOUT_SEL HBN_LDO11_AON_VOUT_SEL -#define HBN_LDO11_AON_VOUT_SEL_POS (19U) -#define HBN_LDO11_AON_VOUT_SEL_LEN (4U) +#define HBN_LDO11_AON_VOUT_SEL_POS (19) +#define HBN_LDO11_AON_VOUT_SEL_LEN (4) #define HBN_LDO11_AON_VOUT_SEL_MSK \ - (((1U << HBN_LDO11_AON_VOUT_SEL_LEN) - 1) << HBN_LDO11_AON_VOUT_SEL_POS) + (((1 << HBN_LDO11_AON_VOUT_SEL_LEN) - 1) << HBN_LDO11_AON_VOUT_SEL_POS) #define HBN_LDO11_AON_VOUT_SEL_UMSK \ - (~(((1U << HBN_LDO11_AON_VOUT_SEL_LEN) - 1) << HBN_LDO11_AON_VOUT_SEL_POS)) + (~(((1 << HBN_LDO11_AON_VOUT_SEL_LEN) - 1) << HBN_LDO11_AON_VOUT_SEL_POS)) #define HBN_PU_DCDC18_AON HBN_PU_DCDC18_AON -#define HBN_PU_DCDC18_AON_POS (23U) -#define HBN_PU_DCDC18_AON_LEN (1U) +#define HBN_PU_DCDC18_AON_POS (23) +#define HBN_PU_DCDC18_AON_LEN (1) #define HBN_PU_DCDC18_AON_MSK \ - (((1U << HBN_PU_DCDC18_AON_LEN) - 1) << HBN_PU_DCDC18_AON_POS) + (((1 << HBN_PU_DCDC18_AON_LEN) - 1) << HBN_PU_DCDC18_AON_POS) #define HBN_PU_DCDC18_AON_UMSK \ - (~(((1U << HBN_PU_DCDC18_AON_LEN) - 1) << HBN_PU_DCDC18_AON_POS)) + (~(((1 << HBN_PU_DCDC18_AON_LEN) - 1) << HBN_PU_DCDC18_AON_POS)) #define HBN_RTC_DLY_OPTION HBN_RTC_DLY_OPTION -#define HBN_RTC_DLY_OPTION_POS (24U) -#define HBN_RTC_DLY_OPTION_LEN (1U) +#define HBN_RTC_DLY_OPTION_POS (24) +#define HBN_RTC_DLY_OPTION_LEN (1) #define HBN_RTC_DLY_OPTION_MSK \ - (((1U << HBN_RTC_DLY_OPTION_LEN) - 1) << HBN_RTC_DLY_OPTION_POS) + (((1 << HBN_RTC_DLY_OPTION_LEN) - 1) << HBN_RTC_DLY_OPTION_POS) #define HBN_RTC_DLY_OPTION_UMSK \ - (~(((1U << HBN_RTC_DLY_OPTION_LEN) - 1) << HBN_RTC_DLY_OPTION_POS)) + (~(((1 << HBN_RTC_DLY_OPTION_LEN) - 1) << HBN_RTC_DLY_OPTION_POS)) #define HBN_PWR_ON_OPTION HBN_PWR_ON_OPTION -#define HBN_PWR_ON_OPTION_POS (25U) -#define HBN_PWR_ON_OPTION_LEN (1U) +#define HBN_PWR_ON_OPTION_POS (25) +#define HBN_PWR_ON_OPTION_LEN (1) #define HBN_PWR_ON_OPTION_MSK \ - (((1U << HBN_PWR_ON_OPTION_LEN) - 1) << HBN_PWR_ON_OPTION_POS) + (((1 << HBN_PWR_ON_OPTION_LEN) - 1) << HBN_PWR_ON_OPTION_POS) #define HBN_PWR_ON_OPTION_UMSK \ - (~(((1U << HBN_PWR_ON_OPTION_LEN) - 1) << HBN_PWR_ON_OPTION_POS)) + (~(((1 << HBN_PWR_ON_OPTION_LEN) - 1) << HBN_PWR_ON_OPTION_POS)) #define HBN_SRAM_SLP_OPTION HBN_SRAM_SLP_OPTION -#define HBN_SRAM_SLP_OPTION_POS (26U) -#define HBN_SRAM_SLP_OPTION_LEN (1U) +#define HBN_SRAM_SLP_OPTION_POS (26) +#define HBN_SRAM_SLP_OPTION_LEN (1) #define HBN_SRAM_SLP_OPTION_MSK \ - (((1U << HBN_SRAM_SLP_OPTION_LEN) - 1) << HBN_SRAM_SLP_OPTION_POS) + (((1 << HBN_SRAM_SLP_OPTION_LEN) - 1) << HBN_SRAM_SLP_OPTION_POS) #define HBN_SRAM_SLP_OPTION_UMSK \ - (~(((1U << HBN_SRAM_SLP_OPTION_LEN) - 1) << HBN_SRAM_SLP_OPTION_POS)) + (~(((1 << HBN_SRAM_SLP_OPTION_LEN) - 1) << HBN_SRAM_SLP_OPTION_POS)) #define HBN_SRAM_SLP HBN_SRAM_SLP -#define HBN_SRAM_SLP_POS (27U) -#define HBN_SRAM_SLP_LEN (1U) -#define HBN_SRAM_SLP_MSK (((1U << HBN_SRAM_SLP_LEN) - 1) << HBN_SRAM_SLP_POS) +#define HBN_SRAM_SLP_POS (27) +#define HBN_SRAM_SLP_LEN (1) +#define HBN_SRAM_SLP_MSK (((1 << HBN_SRAM_SLP_LEN) - 1) << HBN_SRAM_SLP_POS) #define HBN_SRAM_SLP_UMSK \ - (~(((1U << HBN_SRAM_SLP_LEN) - 1) << HBN_SRAM_SLP_POS)) + (~(((1 << HBN_SRAM_SLP_LEN) - 1) << HBN_SRAM_SLP_POS)) #define HBN_STATE HBN_STATE -#define HBN_STATE_POS (28U) -#define HBN_STATE_LEN (4U) -#define HBN_STATE_MSK (((1U << HBN_STATE_LEN) - 1) << HBN_STATE_POS) -#define HBN_STATE_UMSK (~(((1U << HBN_STATE_LEN) - 1) << HBN_STATE_POS)) +#define HBN_STATE_POS (28) +#define HBN_STATE_LEN (4) +#define HBN_STATE_MSK (((1 << HBN_STATE_LEN) - 1) << HBN_STATE_POS) +#define HBN_STATE_UMSK (~(((1 << HBN_STATE_LEN) - 1) << HBN_STATE_POS)) /* 0x4 : HBN_TIME_L */ #define HBN_TIME_L_OFFSET (0x4) #define HBN_TIME_L HBN_TIME_L -#define HBN_TIME_L_POS (0U) -#define HBN_TIME_L_LEN (32U) -#define HBN_TIME_L_MSK (((1U << HBN_TIME_L_LEN) - 1) << HBN_TIME_L_POS) -#define HBN_TIME_L_UMSK (~(((1U << HBN_TIME_L_LEN) - 1) << HBN_TIME_L_POS)) +#define HBN_TIME_L_POS (0) +#define HBN_TIME_L_LEN (32) +#define HBN_TIME_L_MSK (((1 << HBN_TIME_L_LEN) - 1) << HBN_TIME_L_POS) +#define HBN_TIME_L_UMSK (~(((1 << HBN_TIME_L_LEN) - 1) << HBN_TIME_L_POS)) /* 0x8 : HBN_TIME_H */ #define HBN_TIME_H_OFFSET (0x8) #define HBN_TIME_H HBN_TIME_H -#define HBN_TIME_H_POS (0U) -#define HBN_TIME_H_LEN (8U) -#define HBN_TIME_H_MSK (((1U << HBN_TIME_H_LEN) - 1) << HBN_TIME_H_POS) -#define HBN_TIME_H_UMSK (~(((1U << HBN_TIME_H_LEN) - 1) << HBN_TIME_H_POS)) +#define HBN_TIME_H_POS (0) +#define HBN_TIME_H_LEN (8) +#define HBN_TIME_H_MSK (((1 << HBN_TIME_H_LEN) - 1) << HBN_TIME_H_POS) +#define HBN_TIME_H_UMSK (~(((1 << HBN_TIME_H_LEN) - 1) << HBN_TIME_H_POS)) /* 0xC : RTC_TIME_L */ #define HBN_RTC_TIME_L_OFFSET (0xC) #define HBN_RTC_TIME_LATCH_L HBN_RTC_TIME_LATCH_L -#define HBN_RTC_TIME_LATCH_L_POS (0U) -#define HBN_RTC_TIME_LATCH_L_LEN (32U) +#define HBN_RTC_TIME_LATCH_L_POS (0) +#define HBN_RTC_TIME_LATCH_L_LEN (32) #define HBN_RTC_TIME_LATCH_L_MSK \ - (((1U << HBN_RTC_TIME_LATCH_L_LEN) - 1) << HBN_RTC_TIME_LATCH_L_POS) + (((1 << HBN_RTC_TIME_LATCH_L_LEN) - 1) << HBN_RTC_TIME_LATCH_L_POS) #define HBN_RTC_TIME_LATCH_L_UMSK \ - (~(((1U << HBN_RTC_TIME_LATCH_L_LEN) - 1) << HBN_RTC_TIME_LATCH_L_POS)) + (~(((1 << HBN_RTC_TIME_LATCH_L_LEN) - 1) << HBN_RTC_TIME_LATCH_L_POS)) /* 0x10 : RTC_TIME_H */ #define HBN_RTC_TIME_H_OFFSET (0x10) #define HBN_RTC_TIME_LATCH_H HBN_RTC_TIME_LATCH_H -#define HBN_RTC_TIME_LATCH_H_POS (0U) -#define HBN_RTC_TIME_LATCH_H_LEN (8U) +#define HBN_RTC_TIME_LATCH_H_POS (0) +#define HBN_RTC_TIME_LATCH_H_LEN (8) #define HBN_RTC_TIME_LATCH_H_MSK \ - (((1U << HBN_RTC_TIME_LATCH_H_LEN) - 1) << HBN_RTC_TIME_LATCH_H_POS) + (((1 << HBN_RTC_TIME_LATCH_H_LEN) - 1) << HBN_RTC_TIME_LATCH_H_POS) #define HBN_RTC_TIME_LATCH_H_UMSK \ - (~(((1U << HBN_RTC_TIME_LATCH_H_LEN) - 1) << HBN_RTC_TIME_LATCH_H_POS)) + (~(((1 << HBN_RTC_TIME_LATCH_H_LEN) - 1) << HBN_RTC_TIME_LATCH_H_POS)) #define HBN_RTC_TIME_LATCH HBN_RTC_TIME_LATCH -#define HBN_RTC_TIME_LATCH_POS (31U) -#define HBN_RTC_TIME_LATCH_LEN (1U) +#define HBN_RTC_TIME_LATCH_POS (31) +#define HBN_RTC_TIME_LATCH_LEN (1) #define HBN_RTC_TIME_LATCH_MSK \ - (((1U << HBN_RTC_TIME_LATCH_LEN) - 1) << HBN_RTC_TIME_LATCH_POS) + (((1 << HBN_RTC_TIME_LATCH_LEN) - 1) << HBN_RTC_TIME_LATCH_POS) #define HBN_RTC_TIME_LATCH_UMSK \ - (~(((1U << HBN_RTC_TIME_LATCH_LEN) - 1) << HBN_RTC_TIME_LATCH_POS)) + (~(((1 << HBN_RTC_TIME_LATCH_LEN) - 1) << HBN_RTC_TIME_LATCH_POS)) /* 0x14 : HBN_IRQ_MODE */ #define HBN_IRQ_MODE_OFFSET (0x14) #define HBN_PIN_WAKEUP_MODE HBN_PIN_WAKEUP_MODE -#define HBN_PIN_WAKEUP_MODE_POS (0U) -#define HBN_PIN_WAKEUP_MODE_LEN (3U) +#define HBN_PIN_WAKEUP_MODE_POS (0) +#define HBN_PIN_WAKEUP_MODE_LEN (3) #define HBN_PIN_WAKEUP_MODE_MSK \ - (((1U << HBN_PIN_WAKEUP_MODE_LEN) - 1) << HBN_PIN_WAKEUP_MODE_POS) + (((1 << HBN_PIN_WAKEUP_MODE_LEN) - 1) << HBN_PIN_WAKEUP_MODE_POS) #define HBN_PIN_WAKEUP_MODE_UMSK \ - (~(((1U << HBN_PIN_WAKEUP_MODE_LEN) - 1) << HBN_PIN_WAKEUP_MODE_POS)) + (~(((1 << HBN_PIN_WAKEUP_MODE_LEN) - 1) << HBN_PIN_WAKEUP_MODE_POS)) #define HBN_PIN_WAKEUP_MASK HBN_PIN_WAKEUP_MASK -#define HBN_PIN_WAKEUP_MASK_POS (3U) -#define HBN_PIN_WAKEUP_MASK_LEN (2U) +#define HBN_PIN_WAKEUP_MASK_POS (3) +#define HBN_PIN_WAKEUP_MASK_LEN (2) #define HBN_PIN_WAKEUP_MASK_MSK \ - (((1U << HBN_PIN_WAKEUP_MASK_LEN) - 1) << HBN_PIN_WAKEUP_MASK_POS) + (((1 << HBN_PIN_WAKEUP_MASK_LEN) - 1) << HBN_PIN_WAKEUP_MASK_POS) #define HBN_PIN_WAKEUP_MASK_UMSK \ - (~(((1U << HBN_PIN_WAKEUP_MASK_LEN) - 1) << HBN_PIN_WAKEUP_MASK_POS)) + (~(((1 << HBN_PIN_WAKEUP_MASK_LEN) - 1) << HBN_PIN_WAKEUP_MASK_POS)) #define HBN_REG_AON_PAD_IE_SMT HBN_REG_AON_PAD_IE_SMT -#define HBN_REG_AON_PAD_IE_SMT_POS (8U) -#define HBN_REG_AON_PAD_IE_SMT_LEN (1U) +#define HBN_REG_AON_PAD_IE_SMT_POS (8) +#define HBN_REG_AON_PAD_IE_SMT_LEN (1) #define HBN_REG_AON_PAD_IE_SMT_MSK \ - (((1U << HBN_REG_AON_PAD_IE_SMT_LEN) - 1) << HBN_REG_AON_PAD_IE_SMT_POS) + (((1 << HBN_REG_AON_PAD_IE_SMT_LEN) - 1) << HBN_REG_AON_PAD_IE_SMT_POS) #define HBN_REG_AON_PAD_IE_SMT_UMSK \ - (~(((1U << HBN_REG_AON_PAD_IE_SMT_LEN) - 1) << HBN_REG_AON_PAD_IE_SMT_POS)) + (~(((1 << HBN_REG_AON_PAD_IE_SMT_LEN) - 1) << HBN_REG_AON_PAD_IE_SMT_POS)) #define HBN_REG_EN_HW_PU_PD HBN_REG_EN_HW_PU_PD -#define HBN_REG_EN_HW_PU_PD_POS (16U) -#define HBN_REG_EN_HW_PU_PD_LEN (1U) +#define HBN_REG_EN_HW_PU_PD_POS (16) +#define HBN_REG_EN_HW_PU_PD_LEN (1) #define HBN_REG_EN_HW_PU_PD_MSK \ - (((1U << HBN_REG_EN_HW_PU_PD_LEN) - 1) << HBN_REG_EN_HW_PU_PD_POS) + (((1 << HBN_REG_EN_HW_PU_PD_LEN) - 1) << HBN_REG_EN_HW_PU_PD_POS) #define HBN_REG_EN_HW_PU_PD_UMSK \ - (~(((1U << HBN_REG_EN_HW_PU_PD_LEN) - 1) << HBN_REG_EN_HW_PU_PD_POS)) + (~(((1 << HBN_REG_EN_HW_PU_PD_LEN) - 1) << HBN_REG_EN_HW_PU_PD_POS)) #define HBN_IRQ_BOR_EN HBN_IRQ_BOR_EN -#define HBN_IRQ_BOR_EN_POS (18U) -#define HBN_IRQ_BOR_EN_LEN (1U) +#define HBN_IRQ_BOR_EN_POS (18) +#define HBN_IRQ_BOR_EN_LEN (1) #define HBN_IRQ_BOR_EN_MSK \ - (((1U << HBN_IRQ_BOR_EN_LEN) - 1) << HBN_IRQ_BOR_EN_POS) + (((1 << HBN_IRQ_BOR_EN_LEN) - 1) << HBN_IRQ_BOR_EN_POS) #define HBN_IRQ_BOR_EN_UMSK \ - (~(((1U << HBN_IRQ_BOR_EN_LEN) - 1) << HBN_IRQ_BOR_EN_POS)) + (~(((1 << HBN_IRQ_BOR_EN_LEN) - 1) << HBN_IRQ_BOR_EN_POS)) #define HBN_IRQ_ACOMP0_EN HBN_IRQ_ACOMP0_EN -#define HBN_IRQ_ACOMP0_EN_POS (20U) -#define HBN_IRQ_ACOMP0_EN_LEN (2U) +#define HBN_IRQ_ACOMP0_EN_POS (20) +#define HBN_IRQ_ACOMP0_EN_LEN (2) #define HBN_IRQ_ACOMP0_EN_MSK \ - (((1U << HBN_IRQ_ACOMP0_EN_LEN) - 1) << HBN_IRQ_ACOMP0_EN_POS) + (((1 << HBN_IRQ_ACOMP0_EN_LEN) - 1) << HBN_IRQ_ACOMP0_EN_POS) #define HBN_IRQ_ACOMP0_EN_UMSK \ - (~(((1U << HBN_IRQ_ACOMP0_EN_LEN) - 1) << HBN_IRQ_ACOMP0_EN_POS)) + (~(((1 << HBN_IRQ_ACOMP0_EN_LEN) - 1) << HBN_IRQ_ACOMP0_EN_POS)) #define HBN_IRQ_ACOMP1_EN HBN_IRQ_ACOMP1_EN -#define HBN_IRQ_ACOMP1_EN_POS (22U) -#define HBN_IRQ_ACOMP1_EN_LEN (2U) +#define HBN_IRQ_ACOMP1_EN_POS (22) +#define HBN_IRQ_ACOMP1_EN_LEN (2) #define HBN_IRQ_ACOMP1_EN_MSK \ - (((1U << HBN_IRQ_ACOMP1_EN_LEN) - 1) << HBN_IRQ_ACOMP1_EN_POS) + (((1 << HBN_IRQ_ACOMP1_EN_LEN) - 1) << HBN_IRQ_ACOMP1_EN_POS) #define HBN_IRQ_ACOMP1_EN_UMSK \ - (~(((1U << HBN_IRQ_ACOMP1_EN_LEN) - 1) << HBN_IRQ_ACOMP1_EN_POS)) + (~(((1 << HBN_IRQ_ACOMP1_EN_LEN) - 1) << HBN_IRQ_ACOMP1_EN_POS)) #define HBN_PIN_WAKEUP_SEL HBN_PIN_WAKEUP_SEL -#define HBN_PIN_WAKEUP_SEL_POS (24U) -#define HBN_PIN_WAKEUP_SEL_LEN (3U) +#define HBN_PIN_WAKEUP_SEL_POS (24) +#define HBN_PIN_WAKEUP_SEL_LEN (3) #define HBN_PIN_WAKEUP_SEL_MSK \ - (((1U << HBN_PIN_WAKEUP_SEL_LEN) - 1) << HBN_PIN_WAKEUP_SEL_POS) + (((1 << HBN_PIN_WAKEUP_SEL_LEN) - 1) << HBN_PIN_WAKEUP_SEL_POS) #define HBN_PIN_WAKEUP_SEL_UMSK \ - (~(((1U << HBN_PIN_WAKEUP_SEL_LEN) - 1) << HBN_PIN_WAKEUP_SEL_POS)) + (~(((1 << HBN_PIN_WAKEUP_SEL_LEN) - 1) << HBN_PIN_WAKEUP_SEL_POS)) #define HBN_PIN_WAKEUP_EN HBN_PIN_WAKEUP_EN -#define HBN_PIN_WAKEUP_EN_POS (27U) -#define HBN_PIN_WAKEUP_EN_LEN (1U) +#define HBN_PIN_WAKEUP_EN_POS (27) +#define HBN_PIN_WAKEUP_EN_LEN (1) #define HBN_PIN_WAKEUP_EN_MSK \ - (((1U << HBN_PIN_WAKEUP_EN_LEN) - 1) << HBN_PIN_WAKEUP_EN_POS) + (((1 << HBN_PIN_WAKEUP_EN_LEN) - 1) << HBN_PIN_WAKEUP_EN_POS) #define HBN_PIN_WAKEUP_EN_UMSK \ - (~(((1U << HBN_PIN_WAKEUP_EN_LEN) - 1) << HBN_PIN_WAKEUP_EN_POS)) + (~(((1 << HBN_PIN_WAKEUP_EN_LEN) - 1) << HBN_PIN_WAKEUP_EN_POS)) /* 0x18 : HBN_IRQ_STAT */ #define HBN_IRQ_STAT_OFFSET (0x18) #define HBN_IRQ_STAT HBN_IRQ_STAT -#define HBN_IRQ_STAT_POS (0U) -#define HBN_IRQ_STAT_LEN (32U) -#define HBN_IRQ_STAT_MSK (((1U << HBN_IRQ_STAT_LEN) - 1) << HBN_IRQ_STAT_POS) +#define HBN_IRQ_STAT_POS (0) +#define HBN_IRQ_STAT_LEN (32) +#define HBN_IRQ_STAT_MSK (((1 << HBN_IRQ_STAT_LEN) - 1) << HBN_IRQ_STAT_POS) #define HBN_IRQ_STAT_UMSK \ - (~(((1U << HBN_IRQ_STAT_LEN) - 1) << HBN_IRQ_STAT_POS)) + (~(((1 << HBN_IRQ_STAT_LEN) - 1) << HBN_IRQ_STAT_POS)) /* 0x1C : HBN_IRQ_CLR */ #define HBN_IRQ_CLR_OFFSET (0x1C) #define HBN_IRQ_CLR HBN_IRQ_CLR -#define HBN_IRQ_CLR_POS (0U) -#define HBN_IRQ_CLR_LEN (32U) -#define HBN_IRQ_CLR_MSK (((1U << HBN_IRQ_CLR_LEN) - 1) << HBN_IRQ_CLR_POS) -#define HBN_IRQ_CLR_UMSK (~(((1U << HBN_IRQ_CLR_LEN) - 1) << HBN_IRQ_CLR_POS)) +#define HBN_IRQ_CLR_POS (0) +#define HBN_IRQ_CLR_LEN (32) +#define HBN_IRQ_CLR_MSK (((1 << HBN_IRQ_CLR_LEN) - 1) << HBN_IRQ_CLR_POS) +#define HBN_IRQ_CLR_UMSK (~(((1 << HBN_IRQ_CLR_LEN) - 1) << HBN_IRQ_CLR_POS)) /* 0x20 : HBN_PIR_CFG */ #define HBN_PIR_CFG_OFFSET (0x20) #define HBN_PIR_HPF_SEL HBN_PIR_HPF_SEL -#define HBN_PIR_HPF_SEL_POS (0U) -#define HBN_PIR_HPF_SEL_LEN (2U) +#define HBN_PIR_HPF_SEL_POS (0) +#define HBN_PIR_HPF_SEL_LEN (2) #define HBN_PIR_HPF_SEL_MSK \ - (((1U << HBN_PIR_HPF_SEL_LEN) - 1) << HBN_PIR_HPF_SEL_POS) + (((1 << HBN_PIR_HPF_SEL_LEN) - 1) << HBN_PIR_HPF_SEL_POS) #define HBN_PIR_HPF_SEL_UMSK \ - (~(((1U << HBN_PIR_HPF_SEL_LEN) - 1) << HBN_PIR_HPF_SEL_POS)) + (~(((1 << HBN_PIR_HPF_SEL_LEN) - 1) << HBN_PIR_HPF_SEL_POS)) #define HBN_PIR_LPF_SEL HBN_PIR_LPF_SEL -#define HBN_PIR_LPF_SEL_POS (2U) -#define HBN_PIR_LPF_SEL_LEN (1U) +#define HBN_PIR_LPF_SEL_POS (2) +#define HBN_PIR_LPF_SEL_LEN (1) #define HBN_PIR_LPF_SEL_MSK \ - (((1U << HBN_PIR_LPF_SEL_LEN) - 1) << HBN_PIR_LPF_SEL_POS) + (((1 << HBN_PIR_LPF_SEL_LEN) - 1) << HBN_PIR_LPF_SEL_POS) #define HBN_PIR_LPF_SEL_UMSK \ - (~(((1U << HBN_PIR_LPF_SEL_LEN) - 1) << HBN_PIR_LPF_SEL_POS)) + (~(((1 << HBN_PIR_LPF_SEL_LEN) - 1) << HBN_PIR_LPF_SEL_POS)) #define HBN_PIR_DIS HBN_PIR_DIS -#define HBN_PIR_DIS_POS (4U) -#define HBN_PIR_DIS_LEN (2U) -#define HBN_PIR_DIS_MSK (((1U << HBN_PIR_DIS_LEN) - 1) << HBN_PIR_DIS_POS) -#define HBN_PIR_DIS_UMSK (~(((1U << HBN_PIR_DIS_LEN) - 1) << HBN_PIR_DIS_POS)) +#define HBN_PIR_DIS_POS (4) +#define HBN_PIR_DIS_LEN (2) +#define HBN_PIR_DIS_MSK (((1 << HBN_PIR_DIS_LEN) - 1) << HBN_PIR_DIS_POS) +#define HBN_PIR_DIS_UMSK (~(((1 << HBN_PIR_DIS_LEN) - 1) << HBN_PIR_DIS_POS)) #define HBN_PIR_EN HBN_PIR_EN -#define HBN_PIR_EN_POS (7U) -#define HBN_PIR_EN_LEN (1U) -#define HBN_PIR_EN_MSK (((1U << HBN_PIR_EN_LEN) - 1) << HBN_PIR_EN_POS) -#define HBN_PIR_EN_UMSK (~(((1U << HBN_PIR_EN_LEN) - 1) << HBN_PIR_EN_POS)) +#define HBN_PIR_EN_POS (7) +#define HBN_PIR_EN_LEN (1) +#define HBN_PIR_EN_MSK (((1 << HBN_PIR_EN_LEN) - 1) << HBN_PIR_EN_POS) +#define HBN_PIR_EN_UMSK (~(((1 << HBN_PIR_EN_LEN) - 1) << HBN_PIR_EN_POS)) #define HBN_GPADC_CGEN HBN_GPADC_CGEN -#define HBN_GPADC_CGEN_POS (8U) -#define HBN_GPADC_CGEN_LEN (1U) +#define HBN_GPADC_CGEN_POS (8) +#define HBN_GPADC_CGEN_LEN (1) #define HBN_GPADC_CGEN_MSK \ - (((1U << HBN_GPADC_CGEN_LEN) - 1) << HBN_GPADC_CGEN_POS) + (((1 << HBN_GPADC_CGEN_LEN) - 1) << HBN_GPADC_CGEN_POS) #define HBN_GPADC_CGEN_UMSK \ - (~(((1U << HBN_GPADC_CGEN_LEN) - 1) << HBN_GPADC_CGEN_POS)) + (~(((1 << HBN_GPADC_CGEN_LEN) - 1) << HBN_GPADC_CGEN_POS)) #define HBN_GPADC_NOSYNC HBN_GPADC_NOSYNC -#define HBN_GPADC_NOSYNC_POS (9U) -#define HBN_GPADC_NOSYNC_LEN (1U) +#define HBN_GPADC_NOSYNC_POS (9) +#define HBN_GPADC_NOSYNC_LEN (1) #define HBN_GPADC_NOSYNC_MSK \ - (((1U << HBN_GPADC_NOSYNC_LEN) - 1) << HBN_GPADC_NOSYNC_POS) + (((1 << HBN_GPADC_NOSYNC_LEN) - 1) << HBN_GPADC_NOSYNC_POS) #define HBN_GPADC_NOSYNC_UMSK \ - (~(((1U << HBN_GPADC_NOSYNC_LEN) - 1) << HBN_GPADC_NOSYNC_POS)) + (~(((1 << HBN_GPADC_NOSYNC_LEN) - 1) << HBN_GPADC_NOSYNC_POS)) /* 0x24 : HBN_PIR_VTH */ #define HBN_PIR_VTH_OFFSET (0x24) #define HBN_PIR_VTH HBN_PIR_VTH -#define HBN_PIR_VTH_POS (0U) -#define HBN_PIR_VTH_LEN (14U) -#define HBN_PIR_VTH_MSK (((1U << HBN_PIR_VTH_LEN) - 1) << HBN_PIR_VTH_POS) -#define HBN_PIR_VTH_UMSK (~(((1U << HBN_PIR_VTH_LEN) - 1) << HBN_PIR_VTH_POS)) +#define HBN_PIR_VTH_POS (0) +#define HBN_PIR_VTH_LEN (14) +#define HBN_PIR_VTH_MSK (((1 << HBN_PIR_VTH_LEN) - 1) << HBN_PIR_VTH_POS) +#define HBN_PIR_VTH_UMSK (~(((1 << HBN_PIR_VTH_LEN) - 1) << HBN_PIR_VTH_POS)) /* 0x28 : HBN_PIR_INTERVAL */ #define HBN_PIR_INTERVAL_OFFSET (0x28) #define HBN_PIR_INTERVAL HBN_PIR_INTERVAL -#define HBN_PIR_INTERVAL_POS (0U) -#define HBN_PIR_INTERVAL_LEN (12U) +#define HBN_PIR_INTERVAL_POS (0) +#define HBN_PIR_INTERVAL_LEN (12) #define HBN_PIR_INTERVAL_MSK \ - (((1U << HBN_PIR_INTERVAL_LEN) - 1) << HBN_PIR_INTERVAL_POS) + (((1 << HBN_PIR_INTERVAL_LEN) - 1) << HBN_PIR_INTERVAL_POS) #define HBN_PIR_INTERVAL_UMSK \ - (~(((1U << HBN_PIR_INTERVAL_LEN) - 1) << HBN_PIR_INTERVAL_POS)) + (~(((1 << HBN_PIR_INTERVAL_LEN) - 1) << HBN_PIR_INTERVAL_POS)) /* 0x2C : HBN_BOR_CFG */ #define HBN_BOR_CFG_OFFSET (0x2C) #define HBN_BOR_SEL HBN_BOR_SEL -#define HBN_BOR_SEL_POS (0U) -#define HBN_BOR_SEL_LEN (1U) -#define HBN_BOR_SEL_MSK (((1U << HBN_BOR_SEL_LEN) - 1) << HBN_BOR_SEL_POS) -#define HBN_BOR_SEL_UMSK (~(((1U << HBN_BOR_SEL_LEN) - 1) << HBN_BOR_SEL_POS)) +#define HBN_BOR_SEL_POS (0) +#define HBN_BOR_SEL_LEN (1) +#define HBN_BOR_SEL_MSK (((1 << HBN_BOR_SEL_LEN) - 1) << HBN_BOR_SEL_POS) +#define HBN_BOR_SEL_UMSK (~(((1 << HBN_BOR_SEL_LEN) - 1) << HBN_BOR_SEL_POS)) #define HBN_BOR_VTH HBN_BOR_VTH -#define HBN_BOR_VTH_POS (1U) -#define HBN_BOR_VTH_LEN (1U) -#define HBN_BOR_VTH_MSK (((1U << HBN_BOR_VTH_LEN) - 1) << HBN_BOR_VTH_POS) -#define HBN_BOR_VTH_UMSK (~(((1U << HBN_BOR_VTH_LEN) - 1) << HBN_BOR_VTH_POS)) +#define HBN_BOR_VTH_POS (1) +#define HBN_BOR_VTH_LEN (1) +#define HBN_BOR_VTH_MSK (((1 << HBN_BOR_VTH_LEN) - 1) << HBN_BOR_VTH_POS) +#define HBN_BOR_VTH_UMSK (~(((1 << HBN_BOR_VTH_LEN) - 1) << HBN_BOR_VTH_POS)) #define HBN_PU_BOR HBN_PU_BOR -#define HBN_PU_BOR_POS (2U) -#define HBN_PU_BOR_LEN (1U) -#define HBN_PU_BOR_MSK (((1U << HBN_PU_BOR_LEN) - 1) << HBN_PU_BOR_POS) -#define HBN_PU_BOR_UMSK (~(((1U << HBN_PU_BOR_LEN) - 1) << HBN_PU_BOR_POS)) +#define HBN_PU_BOR_POS (2) +#define HBN_PU_BOR_LEN (1) +#define HBN_PU_BOR_MSK (((1 << HBN_PU_BOR_LEN) - 1) << HBN_PU_BOR_POS) +#define HBN_PU_BOR_UMSK (~(((1 << HBN_PU_BOR_LEN) - 1) << HBN_PU_BOR_POS)) #define HBN_R_BOR_OUT HBN_R_BOR_OUT -#define HBN_R_BOR_OUT_POS (3U) -#define HBN_R_BOR_OUT_LEN (1U) +#define HBN_R_BOR_OUT_POS (3) +#define HBN_R_BOR_OUT_LEN (1) #define HBN_R_BOR_OUT_MSK \ - (((1U << HBN_R_BOR_OUT_LEN) - 1) << HBN_R_BOR_OUT_POS) + (((1 << HBN_R_BOR_OUT_LEN) - 1) << HBN_R_BOR_OUT_POS) #define HBN_R_BOR_OUT_UMSK \ - (~(((1U << HBN_R_BOR_OUT_LEN) - 1) << HBN_R_BOR_OUT_POS)) + (~(((1 << HBN_R_BOR_OUT_LEN) - 1) << HBN_R_BOR_OUT_POS)) /* 0x30 : HBN_GLB */ #define HBN_GLB_OFFSET (0x30) #define HBN_ROOT_CLK_SEL HBN_ROOT_CLK_SEL -#define HBN_ROOT_CLK_SEL_POS (0U) -#define HBN_ROOT_CLK_SEL_LEN (2U) +#define HBN_ROOT_CLK_SEL_POS (0) +#define HBN_ROOT_CLK_SEL_LEN (2) #define HBN_ROOT_CLK_SEL_MSK \ - (((1U << HBN_ROOT_CLK_SEL_LEN) - 1) << HBN_ROOT_CLK_SEL_POS) + (((1 << HBN_ROOT_CLK_SEL_LEN) - 1) << HBN_ROOT_CLK_SEL_POS) #define HBN_ROOT_CLK_SEL_UMSK \ - (~(((1U << HBN_ROOT_CLK_SEL_LEN) - 1) << HBN_ROOT_CLK_SEL_POS)) + (~(((1 << HBN_ROOT_CLK_SEL_LEN) - 1) << HBN_ROOT_CLK_SEL_POS)) #define HBN_UART_CLK_SEL HBN_UART_CLK_SEL -#define HBN_UART_CLK_SEL_POS (2U) -#define HBN_UART_CLK_SEL_LEN (1U) +#define HBN_UART_CLK_SEL_POS (2) +#define HBN_UART_CLK_SEL_LEN (1) #define HBN_UART_CLK_SEL_MSK \ - (((1U << HBN_UART_CLK_SEL_LEN) - 1) << HBN_UART_CLK_SEL_POS) + (((1 << HBN_UART_CLK_SEL_LEN) - 1) << HBN_UART_CLK_SEL_POS) #define HBN_UART_CLK_SEL_UMSK \ - (~(((1U << HBN_UART_CLK_SEL_LEN) - 1) << HBN_UART_CLK_SEL_POS)) + (~(((1 << HBN_UART_CLK_SEL_LEN) - 1) << HBN_UART_CLK_SEL_POS)) #define HBN_F32K_SEL HBN_F32K_SEL -#define HBN_F32K_SEL_POS (3U) -#define HBN_F32K_SEL_LEN (2U) -#define HBN_F32K_SEL_MSK (((1U << HBN_F32K_SEL_LEN) - 1) << HBN_F32K_SEL_POS) +#define HBN_F32K_SEL_POS (3) +#define HBN_F32K_SEL_LEN (2) +#define HBN_F32K_SEL_MSK (((1 << HBN_F32K_SEL_LEN) - 1) << HBN_F32K_SEL_POS) #define HBN_F32K_SEL_UMSK \ - (~(((1U << HBN_F32K_SEL_LEN) - 1) << HBN_F32K_SEL_POS)) + (~(((1 << HBN_F32K_SEL_LEN) - 1) << HBN_F32K_SEL_POS)) #define HBN_PU_RC32K HBN_PU_RC32K -#define HBN_PU_RC32K_POS (5U) -#define HBN_PU_RC32K_LEN (1U) -#define HBN_PU_RC32K_MSK (((1U << HBN_PU_RC32K_LEN) - 1) << HBN_PU_RC32K_POS) +#define HBN_PU_RC32K_POS (5) +#define HBN_PU_RC32K_LEN (1) +#define HBN_PU_RC32K_MSK (((1 << HBN_PU_RC32K_LEN) - 1) << HBN_PU_RC32K_POS) #define HBN_PU_RC32K_UMSK \ - (~(((1U << HBN_PU_RC32K_LEN) - 1) << HBN_PU_RC32K_POS)) + (~(((1 << HBN_PU_RC32K_LEN) - 1) << HBN_PU_RC32K_POS)) #define HBN_SW_LDO11SOC_VOUT_SEL_AON HBN_SW_LDO11SOC_VOUT_SEL_AON -#define HBN_SW_LDO11SOC_VOUT_SEL_AON_POS (16U) -#define HBN_SW_LDO11SOC_VOUT_SEL_AON_LEN (4U) +#define HBN_SW_LDO11SOC_VOUT_SEL_AON_POS (16) +#define HBN_SW_LDO11SOC_VOUT_SEL_AON_LEN (4) #define HBN_SW_LDO11SOC_VOUT_SEL_AON_MSK \ - (((1U << HBN_SW_LDO11SOC_VOUT_SEL_AON_LEN) - 1) \ + (((1 << HBN_SW_LDO11SOC_VOUT_SEL_AON_LEN) - 1) \ << HBN_SW_LDO11SOC_VOUT_SEL_AON_POS) #define HBN_SW_LDO11SOC_VOUT_SEL_AON_UMSK \ - (~(((1U << HBN_SW_LDO11SOC_VOUT_SEL_AON_LEN) - 1) \ + (~(((1 << HBN_SW_LDO11SOC_VOUT_SEL_AON_LEN) - 1) \ << HBN_SW_LDO11SOC_VOUT_SEL_AON_POS)) #define HBN_SW_LDO11_RT_VOUT_SEL HBN_SW_LDO11_RT_VOUT_SEL -#define HBN_SW_LDO11_RT_VOUT_SEL_POS (24U) -#define HBN_SW_LDO11_RT_VOUT_SEL_LEN (4U) +#define HBN_SW_LDO11_RT_VOUT_SEL_POS (24) +#define HBN_SW_LDO11_RT_VOUT_SEL_LEN (4) #define HBN_SW_LDO11_RT_VOUT_SEL_MSK \ - (((1U << HBN_SW_LDO11_RT_VOUT_SEL_LEN) - 1) << HBN_SW_LDO11_RT_VOUT_SEL_POS) + (((1 << HBN_SW_LDO11_RT_VOUT_SEL_LEN) - 1) << HBN_SW_LDO11_RT_VOUT_SEL_POS) #define HBN_SW_LDO11_RT_VOUT_SEL_UMSK \ - (~(((1U << HBN_SW_LDO11_RT_VOUT_SEL_LEN) - 1) \ + (~(((1 << HBN_SW_LDO11_RT_VOUT_SEL_LEN) - 1) \ << HBN_SW_LDO11_RT_VOUT_SEL_POS)) #define HBN_SW_LDO11_AON_VOUT_SEL HBN_SW_LDO11_AON_VOUT_SEL -#define HBN_SW_LDO11_AON_VOUT_SEL_POS (28U) -#define HBN_SW_LDO11_AON_VOUT_SEL_LEN (4U) +#define HBN_SW_LDO11_AON_VOUT_SEL_POS (28) +#define HBN_SW_LDO11_AON_VOUT_SEL_LEN (4) #define HBN_SW_LDO11_AON_VOUT_SEL_MSK \ - (((1U << HBN_SW_LDO11_AON_VOUT_SEL_LEN) - 1) \ + (((1 << HBN_SW_LDO11_AON_VOUT_SEL_LEN) - 1) \ << HBN_SW_LDO11_AON_VOUT_SEL_POS) #define HBN_SW_LDO11_AON_VOUT_SEL_UMSK \ - (~(((1U << HBN_SW_LDO11_AON_VOUT_SEL_LEN) - 1) \ + (~(((1 << HBN_SW_LDO11_AON_VOUT_SEL_LEN) - 1) \ << HBN_SW_LDO11_AON_VOUT_SEL_POS)) /* 0x34 : HBN_SRAM */ #define HBN_SRAM_OFFSET (0x34) #define HBN_RETRAM_RET HBN_RETRAM_RET -#define HBN_RETRAM_RET_POS (6U) -#define HBN_RETRAM_RET_LEN (1U) +#define HBN_RETRAM_RET_POS (6) +#define HBN_RETRAM_RET_LEN (1) #define HBN_RETRAM_RET_MSK \ - (((1U << HBN_RETRAM_RET_LEN) - 1) << HBN_RETRAM_RET_POS) + (((1 << HBN_RETRAM_RET_LEN) - 1) << HBN_RETRAM_RET_POS) #define HBN_RETRAM_RET_UMSK \ - (~(((1U << HBN_RETRAM_RET_LEN) - 1) << HBN_RETRAM_RET_POS)) + (~(((1 << HBN_RETRAM_RET_LEN) - 1) << HBN_RETRAM_RET_POS)) #define HBN_RETRAM_SLP HBN_RETRAM_SLP -#define HBN_RETRAM_SLP_POS (7U) -#define HBN_RETRAM_SLP_LEN (1U) +#define HBN_RETRAM_SLP_POS (7) +#define HBN_RETRAM_SLP_LEN (1) #define HBN_RETRAM_SLP_MSK \ - (((1U << HBN_RETRAM_SLP_LEN) - 1) << HBN_RETRAM_SLP_POS) + (((1 << HBN_RETRAM_SLP_LEN) - 1) << HBN_RETRAM_SLP_POS) #define HBN_RETRAM_SLP_UMSK \ - (~(((1U << HBN_RETRAM_SLP_LEN) - 1) << HBN_RETRAM_SLP_POS)) + (~(((1 << HBN_RETRAM_SLP_LEN) - 1) << HBN_RETRAM_SLP_POS)) /* 0x100 : HBN_RSV0 */ #define HBN_RSV0_OFFSET (0x100) #define HBN_RSV0 HBN_RSV0 -#define HBN_RSV0_POS (0U) -#define HBN_RSV0_LEN (32U) -#define HBN_RSV0_MSK (((1U << HBN_RSV0_LEN) - 1) << HBN_RSV0_POS) -#define HBN_RSV0_UMSK (~(((1U << HBN_RSV0_LEN) - 1) << HBN_RSV0_POS)) +#define HBN_RSV0_POS (0) +#define HBN_RSV0_LEN (32) +#define HBN_RSV0_MSK (((1 << HBN_RSV0_LEN) - 1) << HBN_RSV0_POS) +#define HBN_RSV0_UMSK (~(((1 << HBN_RSV0_LEN) - 1) << HBN_RSV0_POS)) /* 0x104 : HBN_RSV1 */ #define HBN_RSV1_OFFSET (0x104) #define HBN_RSV1 HBN_RSV1 -#define HBN_RSV1_POS (0U) -#define HBN_RSV1_LEN (32U) -#define HBN_RSV1_MSK (((1U << HBN_RSV1_LEN) - 1) << HBN_RSV1_POS) -#define HBN_RSV1_UMSK (~(((1U << HBN_RSV1_LEN) - 1) << HBN_RSV1_POS)) +#define HBN_RSV1_POS (0) +#define HBN_RSV1_LEN (32) +#define HBN_RSV1_MSK (((1 << HBN_RSV1_LEN) - 1) << HBN_RSV1_POS) +#define HBN_RSV1_UMSK (~(((1 << HBN_RSV1_LEN) - 1) << HBN_RSV1_POS)) /* 0x108 : HBN_RSV2 */ #define HBN_RSV2_OFFSET (0x108) #define HBN_RSV2 HBN_RSV2 -#define HBN_RSV2_POS (0U) -#define HBN_RSV2_LEN (32U) -#define HBN_RSV2_MSK (((1U << HBN_RSV2_LEN) - 1) << HBN_RSV2_POS) -#define HBN_RSV2_UMSK (~(((1U << HBN_RSV2_LEN) - 1) << HBN_RSV2_POS)) +#define HBN_RSV2_POS (0) +#define HBN_RSV2_LEN (32) +#define HBN_RSV2_MSK (((1 << HBN_RSV2_LEN) - 1) << HBN_RSV2_POS) +#define HBN_RSV2_UMSK (~(((1 << HBN_RSV2_LEN) - 1) << HBN_RSV2_POS)) /* 0x10C : HBN_RSV3 */ #define HBN_RSV3_OFFSET (0x10C) #define HBN_RSV3 HBN_RSV3 -#define HBN_RSV3_POS (0U) -#define HBN_RSV3_LEN (32U) -#define HBN_RSV3_MSK (((1U << HBN_RSV3_LEN) - 1) << HBN_RSV3_POS) -#define HBN_RSV3_UMSK (~(((1U << HBN_RSV3_LEN) - 1) << HBN_RSV3_POS)) +#define HBN_RSV3_POS (0) +#define HBN_RSV3_LEN (32) +#define HBN_RSV3_MSK (((1 << HBN_RSV3_LEN) - 1) << HBN_RSV3_POS) +#define HBN_RSV3_UMSK (~(((1 << HBN_RSV3_LEN) - 1) << HBN_RSV3_POS)) /* 0x200 : rc32k_ctrl0 */ #define HBN_RC32K_CTRL0_OFFSET (0x200) #define HBN_RC32K_CAL_DONE HBN_RC32K_CAL_DONE -#define HBN_RC32K_CAL_DONE_POS (0U) -#define HBN_RC32K_CAL_DONE_LEN (1U) +#define HBN_RC32K_CAL_DONE_POS (0) +#define HBN_RC32K_CAL_DONE_LEN (1) #define HBN_RC32K_CAL_DONE_MSK \ - (((1U << HBN_RC32K_CAL_DONE_LEN) - 1) << HBN_RC32K_CAL_DONE_POS) + (((1 << HBN_RC32K_CAL_DONE_LEN) - 1) << HBN_RC32K_CAL_DONE_POS) #define HBN_RC32K_CAL_DONE_UMSK \ - (~(((1U << HBN_RC32K_CAL_DONE_LEN) - 1) << HBN_RC32K_CAL_DONE_POS)) + (~(((1 << HBN_RC32K_CAL_DONE_LEN) - 1) << HBN_RC32K_CAL_DONE_POS)) #define HBN_RC32K_RDY HBN_RC32K_RDY -#define HBN_RC32K_RDY_POS (1U) -#define HBN_RC32K_RDY_LEN (1U) +#define HBN_RC32K_RDY_POS (1) +#define HBN_RC32K_RDY_LEN (1) #define HBN_RC32K_RDY_MSK \ - (((1U << HBN_RC32K_RDY_LEN) - 1) << HBN_RC32K_RDY_POS) + (((1 << HBN_RC32K_RDY_LEN) - 1) << HBN_RC32K_RDY_POS) #define HBN_RC32K_RDY_UMSK \ - (~(((1U << HBN_RC32K_RDY_LEN) - 1) << HBN_RC32K_RDY_POS)) + (~(((1 << HBN_RC32K_RDY_LEN) - 1) << HBN_RC32K_RDY_POS)) #define HBN_RC32K_CAL_INPROGRESS HBN_RC32K_CAL_INPROGRESS -#define HBN_RC32K_CAL_INPROGRESS_POS (2U) -#define HBN_RC32K_CAL_INPROGRESS_LEN (1U) +#define HBN_RC32K_CAL_INPROGRESS_POS (2) +#define HBN_RC32K_CAL_INPROGRESS_LEN (1) #define HBN_RC32K_CAL_INPROGRESS_MSK \ - (((1U << HBN_RC32K_CAL_INPROGRESS_LEN) - 1) << HBN_RC32K_CAL_INPROGRESS_POS) + (((1 << HBN_RC32K_CAL_INPROGRESS_LEN) - 1) << HBN_RC32K_CAL_INPROGRESS_POS) #define HBN_RC32K_CAL_INPROGRESS_UMSK \ - (~(((1U << HBN_RC32K_CAL_INPROGRESS_LEN) - 1) \ + (~(((1 << HBN_RC32K_CAL_INPROGRESS_LEN) - 1) \ << HBN_RC32K_CAL_INPROGRESS_POS)) #define HBN_RC32K_CAL_DIV HBN_RC32K_CAL_DIV -#define HBN_RC32K_CAL_DIV_POS (3U) -#define HBN_RC32K_CAL_DIV_LEN (2U) +#define HBN_RC32K_CAL_DIV_POS (3) +#define HBN_RC32K_CAL_DIV_LEN (2) #define HBN_RC32K_CAL_DIV_MSK \ - (((1U << HBN_RC32K_CAL_DIV_LEN) - 1) << HBN_RC32K_CAL_DIV_POS) + (((1 << HBN_RC32K_CAL_DIV_LEN) - 1) << HBN_RC32K_CAL_DIV_POS) #define HBN_RC32K_CAL_DIV_UMSK \ - (~(((1U << HBN_RC32K_CAL_DIV_LEN) - 1) << HBN_RC32K_CAL_DIV_POS)) + (~(((1 << HBN_RC32K_CAL_DIV_LEN) - 1) << HBN_RC32K_CAL_DIV_POS)) #define HBN_RC32K_CAL_PRECHARGE HBN_RC32K_CAL_PRECHARGE -#define HBN_RC32K_CAL_PRECHARGE_POS (5U) -#define HBN_RC32K_CAL_PRECHARGE_LEN (1U) +#define HBN_RC32K_CAL_PRECHARGE_POS (5) +#define HBN_RC32K_CAL_PRECHARGE_LEN (1) #define HBN_RC32K_CAL_PRECHARGE_MSK \ - (((1U << HBN_RC32K_CAL_PRECHARGE_LEN) - 1) << HBN_RC32K_CAL_PRECHARGE_POS) + (((1 << HBN_RC32K_CAL_PRECHARGE_LEN) - 1) << HBN_RC32K_CAL_PRECHARGE_POS) #define HBN_RC32K_CAL_PRECHARGE_UMSK \ - (~(((1U << HBN_RC32K_CAL_PRECHARGE_LEN) - 1) \ - << HBN_RC32K_CAL_PRECHARGE_POS)) + (~(((1 << HBN_RC32K_CAL_PRECHARGE_LEN) - 1) << HBN_RC32K_CAL_PRECHARGE_POS)) #define HBN_RC32K_DIG_CODE_FR_CAL HBN_RC32K_DIG_CODE_FR_CAL -#define HBN_RC32K_DIG_CODE_FR_CAL_POS (6U) -#define HBN_RC32K_DIG_CODE_FR_CAL_LEN (10U) +#define HBN_RC32K_DIG_CODE_FR_CAL_POS (6) +#define HBN_RC32K_DIG_CODE_FR_CAL_LEN (10) #define HBN_RC32K_DIG_CODE_FR_CAL_MSK \ - (((1U << HBN_RC32K_DIG_CODE_FR_CAL_LEN) - 1) \ + (((1 << HBN_RC32K_DIG_CODE_FR_CAL_LEN) - 1) \ << HBN_RC32K_DIG_CODE_FR_CAL_POS) #define HBN_RC32K_DIG_CODE_FR_CAL_UMSK \ - (~(((1U << HBN_RC32K_DIG_CODE_FR_CAL_LEN) - 1) \ + (~(((1 << HBN_RC32K_DIG_CODE_FR_CAL_LEN) - 1) \ << HBN_RC32K_DIG_CODE_FR_CAL_POS)) #define HBN_RC32K_VREF_DLY HBN_RC32K_VREF_DLY -#define HBN_RC32K_VREF_DLY_POS (16U) -#define HBN_RC32K_VREF_DLY_LEN (2U) +#define HBN_RC32K_VREF_DLY_POS (16) +#define HBN_RC32K_VREF_DLY_LEN (2) #define HBN_RC32K_VREF_DLY_MSK \ - (((1U << HBN_RC32K_VREF_DLY_LEN) - 1) << HBN_RC32K_VREF_DLY_POS) + (((1 << HBN_RC32K_VREF_DLY_LEN) - 1) << HBN_RC32K_VREF_DLY_POS) #define HBN_RC32K_VREF_DLY_UMSK \ - (~(((1U << HBN_RC32K_VREF_DLY_LEN) - 1) << HBN_RC32K_VREF_DLY_POS)) + (~(((1 << HBN_RC32K_VREF_DLY_LEN) - 1) << HBN_RC32K_VREF_DLY_POS)) #define HBN_RC32K_ALLOW_CAL HBN_RC32K_ALLOW_CAL -#define HBN_RC32K_ALLOW_CAL_POS (18U) -#define HBN_RC32K_ALLOW_CAL_LEN (1U) +#define HBN_RC32K_ALLOW_CAL_POS (18) +#define HBN_RC32K_ALLOW_CAL_LEN (1) #define HBN_RC32K_ALLOW_CAL_MSK \ - (((1U << HBN_RC32K_ALLOW_CAL_LEN) - 1) << HBN_RC32K_ALLOW_CAL_POS) + (((1 << HBN_RC32K_ALLOW_CAL_LEN) - 1) << HBN_RC32K_ALLOW_CAL_POS) #define HBN_RC32K_ALLOW_CAL_UMSK \ - (~(((1U << HBN_RC32K_ALLOW_CAL_LEN) - 1) << HBN_RC32K_ALLOW_CAL_POS)) + (~(((1 << HBN_RC32K_ALLOW_CAL_LEN) - 1) << HBN_RC32K_ALLOW_CAL_POS)) #define HBN_RC32K_EXT_CODE_EN HBN_RC32K_EXT_CODE_EN -#define HBN_RC32K_EXT_CODE_EN_POS (19U) -#define HBN_RC32K_EXT_CODE_EN_LEN (1U) +#define HBN_RC32K_EXT_CODE_EN_POS (19) +#define HBN_RC32K_EXT_CODE_EN_LEN (1) #define HBN_RC32K_EXT_CODE_EN_MSK \ - (((1U << HBN_RC32K_EXT_CODE_EN_LEN) - 1) << HBN_RC32K_EXT_CODE_EN_POS) + (((1 << HBN_RC32K_EXT_CODE_EN_LEN) - 1) << HBN_RC32K_EXT_CODE_EN_POS) #define HBN_RC32K_EXT_CODE_EN_UMSK \ - (~(((1U << HBN_RC32K_EXT_CODE_EN_LEN) - 1) << HBN_RC32K_EXT_CODE_EN_POS)) + (~(((1 << HBN_RC32K_EXT_CODE_EN_LEN) - 1) << HBN_RC32K_EXT_CODE_EN_POS)) #define HBN_RC32K_CAL_EN HBN_RC32K_CAL_EN -#define HBN_RC32K_CAL_EN_POS (20U) -#define HBN_RC32K_CAL_EN_LEN (1U) +#define HBN_RC32K_CAL_EN_POS (20) +#define HBN_RC32K_CAL_EN_LEN (1) #define HBN_RC32K_CAL_EN_MSK \ - (((1U << HBN_RC32K_CAL_EN_LEN) - 1) << HBN_RC32K_CAL_EN_POS) + (((1 << HBN_RC32K_CAL_EN_LEN) - 1) << HBN_RC32K_CAL_EN_POS) #define HBN_RC32K_CAL_EN_UMSK \ - (~(((1U << HBN_RC32K_CAL_EN_LEN) - 1) << HBN_RC32K_CAL_EN_POS)) + (~(((1 << HBN_RC32K_CAL_EN_LEN) - 1) << HBN_RC32K_CAL_EN_POS)) #define HBN_RC32K_CODE_FR_EXT HBN_RC32K_CODE_FR_EXT -#define HBN_RC32K_CODE_FR_EXT_POS (22U) -#define HBN_RC32K_CODE_FR_EXT_LEN (10U) +#define HBN_RC32K_CODE_FR_EXT_POS (22) +#define HBN_RC32K_CODE_FR_EXT_LEN (10) #define HBN_RC32K_CODE_FR_EXT_MSK \ - (((1U << HBN_RC32K_CODE_FR_EXT_LEN) - 1) << HBN_RC32K_CODE_FR_EXT_POS) + (((1 << HBN_RC32K_CODE_FR_EXT_LEN) - 1) << HBN_RC32K_CODE_FR_EXT_POS) #define HBN_RC32K_CODE_FR_EXT_UMSK \ - (~(((1U << HBN_RC32K_CODE_FR_EXT_LEN) - 1) << HBN_RC32K_CODE_FR_EXT_POS)) + (~(((1 << HBN_RC32K_CODE_FR_EXT_LEN) - 1) << HBN_RC32K_CODE_FR_EXT_POS)) /* 0x204 : xtal32k */ #define HBN_XTAL32K_OFFSET (0x204) #define HBN_XTAL32K_EXT_SEL HBN_XTAL32K_EXT_SEL -#define HBN_XTAL32K_EXT_SEL_POS (2U) -#define HBN_XTAL32K_EXT_SEL_LEN (1U) +#define HBN_XTAL32K_EXT_SEL_POS (2) +#define HBN_XTAL32K_EXT_SEL_LEN (1) #define HBN_XTAL32K_EXT_SEL_MSK \ - (((1U << HBN_XTAL32K_EXT_SEL_LEN) - 1) << HBN_XTAL32K_EXT_SEL_POS) + (((1 << HBN_XTAL32K_EXT_SEL_LEN) - 1) << HBN_XTAL32K_EXT_SEL_POS) #define HBN_XTAL32K_EXT_SEL_UMSK \ - (~(((1U << HBN_XTAL32K_EXT_SEL_LEN) - 1) << HBN_XTAL32K_EXT_SEL_POS)) + (~(((1 << HBN_XTAL32K_EXT_SEL_LEN) - 1) << HBN_XTAL32K_EXT_SEL_POS)) #define HBN_XTAL32K_AMP_CTRL HBN_XTAL32K_AMP_CTRL -#define HBN_XTAL32K_AMP_CTRL_POS (3U) -#define HBN_XTAL32K_AMP_CTRL_LEN (2U) +#define HBN_XTAL32K_AMP_CTRL_POS (3) +#define HBN_XTAL32K_AMP_CTRL_LEN (2) #define HBN_XTAL32K_AMP_CTRL_MSK \ - (((1U << HBN_XTAL32K_AMP_CTRL_LEN) - 1) << HBN_XTAL32K_AMP_CTRL_POS) + (((1 << HBN_XTAL32K_AMP_CTRL_LEN) - 1) << HBN_XTAL32K_AMP_CTRL_POS) #define HBN_XTAL32K_AMP_CTRL_UMSK \ - (~(((1U << HBN_XTAL32K_AMP_CTRL_LEN) - 1) << HBN_XTAL32K_AMP_CTRL_POS)) + (~(((1 << HBN_XTAL32K_AMP_CTRL_LEN) - 1) << HBN_XTAL32K_AMP_CTRL_POS)) #define HBN_XTAL32K_REG HBN_XTAL32K_REG -#define HBN_XTAL32K_REG_POS (5U) -#define HBN_XTAL32K_REG_LEN (2U) +#define HBN_XTAL32K_REG_POS (5) +#define HBN_XTAL32K_REG_LEN (2) #define HBN_XTAL32K_REG_MSK \ - (((1U << HBN_XTAL32K_REG_LEN) - 1) << HBN_XTAL32K_REG_POS) + (((1 << HBN_XTAL32K_REG_LEN) - 1) << HBN_XTAL32K_REG_POS) #define HBN_XTAL32K_REG_UMSK \ - (~(((1U << HBN_XTAL32K_REG_LEN) - 1) << HBN_XTAL32K_REG_POS)) + (~(((1 << HBN_XTAL32K_REG_LEN) - 1) << HBN_XTAL32K_REG_POS)) #define HBN_XTAL32K_OUTBUF_STRE HBN_XTAL32K_OUTBUF_STRE -#define HBN_XTAL32K_OUTBUF_STRE_POS (7U) -#define HBN_XTAL32K_OUTBUF_STRE_LEN (1U) +#define HBN_XTAL32K_OUTBUF_STRE_POS (7) +#define HBN_XTAL32K_OUTBUF_STRE_LEN (1) #define HBN_XTAL32K_OUTBUF_STRE_MSK \ - (((1U << HBN_XTAL32K_OUTBUF_STRE_LEN) - 1) << HBN_XTAL32K_OUTBUF_STRE_POS) + (((1 << HBN_XTAL32K_OUTBUF_STRE_LEN) - 1) << HBN_XTAL32K_OUTBUF_STRE_POS) #define HBN_XTAL32K_OUTBUF_STRE_UMSK \ - (~(((1U << HBN_XTAL32K_OUTBUF_STRE_LEN) - 1) \ - << HBN_XTAL32K_OUTBUF_STRE_POS)) + (~(((1 << HBN_XTAL32K_OUTBUF_STRE_LEN) - 1) << HBN_XTAL32K_OUTBUF_STRE_POS)) #define HBN_XTAL32K_OTF_SHORT HBN_XTAL32K_OTF_SHORT -#define HBN_XTAL32K_OTF_SHORT_POS (8U) -#define HBN_XTAL32K_OTF_SHORT_LEN (1U) +#define HBN_XTAL32K_OTF_SHORT_POS (8) +#define HBN_XTAL32K_OTF_SHORT_LEN (1) #define HBN_XTAL32K_OTF_SHORT_MSK \ - (((1U << HBN_XTAL32K_OTF_SHORT_LEN) - 1) << HBN_XTAL32K_OTF_SHORT_POS) + (((1 << HBN_XTAL32K_OTF_SHORT_LEN) - 1) << HBN_XTAL32K_OTF_SHORT_POS) #define HBN_XTAL32K_OTF_SHORT_UMSK \ - (~(((1U << HBN_XTAL32K_OTF_SHORT_LEN) - 1) << HBN_XTAL32K_OTF_SHORT_POS)) + (~(((1 << HBN_XTAL32K_OTF_SHORT_LEN) - 1) << HBN_XTAL32K_OTF_SHORT_POS)) #define HBN_XTAL32K_INV_STRE HBN_XTAL32K_INV_STRE -#define HBN_XTAL32K_INV_STRE_POS (9U) -#define HBN_XTAL32K_INV_STRE_LEN (2U) +#define HBN_XTAL32K_INV_STRE_POS (9) +#define HBN_XTAL32K_INV_STRE_LEN (2) #define HBN_XTAL32K_INV_STRE_MSK \ - (((1U << HBN_XTAL32K_INV_STRE_LEN) - 1) << HBN_XTAL32K_INV_STRE_POS) + (((1 << HBN_XTAL32K_INV_STRE_LEN) - 1) << HBN_XTAL32K_INV_STRE_POS) #define HBN_XTAL32K_INV_STRE_UMSK \ - (~(((1U << HBN_XTAL32K_INV_STRE_LEN) - 1) << HBN_XTAL32K_INV_STRE_POS)) + (~(((1 << HBN_XTAL32K_INV_STRE_LEN) - 1) << HBN_XTAL32K_INV_STRE_POS)) #define HBN_XTAL32K_CAPBANK HBN_XTAL32K_CAPBANK -#define HBN_XTAL32K_CAPBANK_POS (11U) -#define HBN_XTAL32K_CAPBANK_LEN (6U) +#define HBN_XTAL32K_CAPBANK_POS (11) +#define HBN_XTAL32K_CAPBANK_LEN (6) #define HBN_XTAL32K_CAPBANK_MSK \ - (((1U << HBN_XTAL32K_CAPBANK_LEN) - 1) << HBN_XTAL32K_CAPBANK_POS) + (((1 << HBN_XTAL32K_CAPBANK_LEN) - 1) << HBN_XTAL32K_CAPBANK_POS) #define HBN_XTAL32K_CAPBANK_UMSK \ - (~(((1U << HBN_XTAL32K_CAPBANK_LEN) - 1) << HBN_XTAL32K_CAPBANK_POS)) + (~(((1 << HBN_XTAL32K_CAPBANK_LEN) - 1) << HBN_XTAL32K_CAPBANK_POS)) #define HBN_XTAL32K_AC_CAP_SHORT HBN_XTAL32K_AC_CAP_SHORT -#define HBN_XTAL32K_AC_CAP_SHORT_POS (17U) -#define HBN_XTAL32K_AC_CAP_SHORT_LEN (1U) +#define HBN_XTAL32K_AC_CAP_SHORT_POS (17) +#define HBN_XTAL32K_AC_CAP_SHORT_LEN (1) #define HBN_XTAL32K_AC_CAP_SHORT_MSK \ - (((1U << HBN_XTAL32K_AC_CAP_SHORT_LEN) - 1) << HBN_XTAL32K_AC_CAP_SHORT_POS) + (((1 << HBN_XTAL32K_AC_CAP_SHORT_LEN) - 1) << HBN_XTAL32K_AC_CAP_SHORT_POS) #define HBN_XTAL32K_AC_CAP_SHORT_UMSK \ - (~(((1U << HBN_XTAL32K_AC_CAP_SHORT_LEN) - 1) \ + (~(((1 << HBN_XTAL32K_AC_CAP_SHORT_LEN) - 1) \ << HBN_XTAL32K_AC_CAP_SHORT_POS)) #define HBN_PU_XTAL32K_BUF HBN_PU_XTAL32K_BUF -#define HBN_PU_XTAL32K_BUF_POS (18U) -#define HBN_PU_XTAL32K_BUF_LEN (1U) +#define HBN_PU_XTAL32K_BUF_POS (18) +#define HBN_PU_XTAL32K_BUF_LEN (1) #define HBN_PU_XTAL32K_BUF_MSK \ - (((1U << HBN_PU_XTAL32K_BUF_LEN) - 1) << HBN_PU_XTAL32K_BUF_POS) + (((1 << HBN_PU_XTAL32K_BUF_LEN) - 1) << HBN_PU_XTAL32K_BUF_POS) #define HBN_PU_XTAL32K_BUF_UMSK \ - (~(((1U << HBN_PU_XTAL32K_BUF_LEN) - 1) << HBN_PU_XTAL32K_BUF_POS)) + (~(((1 << HBN_PU_XTAL32K_BUF_LEN) - 1) << HBN_PU_XTAL32K_BUF_POS)) #define HBN_PU_XTAL32K HBN_PU_XTAL32K -#define HBN_PU_XTAL32K_POS (19U) -#define HBN_PU_XTAL32K_LEN (1U) +#define HBN_PU_XTAL32K_POS (19) +#define HBN_PU_XTAL32K_LEN (1) #define HBN_PU_XTAL32K_MSK \ - (((1U << HBN_PU_XTAL32K_LEN) - 1) << HBN_PU_XTAL32K_POS) + (((1 << HBN_PU_XTAL32K_LEN) - 1) << HBN_PU_XTAL32K_POS) #define HBN_PU_XTAL32K_UMSK \ - (~(((1U << HBN_PU_XTAL32K_LEN) - 1) << HBN_PU_XTAL32K_POS)) + (~(((1 << HBN_PU_XTAL32K_LEN) - 1) << HBN_PU_XTAL32K_POS)) /**************************************************************************** * Public Types @@ -638,323 +639,8 @@ #ifndef __ASSEMBLY__ /* HBN UART clock type definition */ -enum hbn_uart_clk_type_e -{ - HBN_UART_CLK_FCLK = 0, /* Select FCLK as UART clock */ - HBN_UART_CLK_160M /* Select 160M as UART clock */ -}; - -struct hbn_reg_s -{ - /* 0x0 : HBN_CTL */ - - union - { - struct - { - uint32_t rtc_ctl : 7; /* [ 6: 0], r/w, 0x0 */ - uint32_t hbn_mode : 1; /* [ 7], w, 0x0 */ - uint32_t trap_mode : 1; /* [ 8], r, 0x0 */ - uint32_t pwrdn_hbn_core : 1; /* [ 9], r/w, 0x0 */ - uint32_t reserved_10 : 1; /* [ 10], rsvd, 0x0 */ - uint32_t pwrdn_hbn_rtc : 1; /* [ 11], r/w, 0x0 */ - uint32_t sw_rst : 1; /* [ 12], r/w, 0x0 */ - uint32_t hbn_dis_pwr_off_ldo11 : 1; /* [ 13], r/w, 0x0 */ - uint32_t hbn_dis_pwr_off_ldo11_rt : 1; /* [ 14], r/w, 0x0 */ - uint32_t hbn_ldo11_rt_vout_sel : 4; /* [18:15], r/w, 0xa */ - uint32_t hbn_ldo11_aon_vout_sel : 4; /* [22:19], r/w, 0xa */ - uint32_t pu_dcdc18_aon : 1; /* [ 23], r/w, 0x1 */ - uint32_t rtc_dly_option : 1; /* [ 24], r/w, 0x0 */ - uint32_t pwr_on_option : 1; /* [ 25], r/w, 0x0 */ - uint32_t sram_slp_option : 1; /* [ 26], r/w, 0x0 */ - uint32_t sram_slp : 1; /* [ 27], r, 0x0 */ - uint32_t hbn_state : 4; /* [31:28], r, 0x0 */ - } bf; - uint32_t word; - } HBN_CTL; - - /* 0x4 : HBN_TIME_L */ - - union - { - struct - { - uint32_t hbn_time_l : 32; /* [31: 0], r/w, 0x0 */ - } bf; - uint32_t word; - } HBN_TIME_L; - - /* 0x8 : HBN_TIME_H */ - - union - { - struct - { - uint32_t hbn_time_h : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } bf; - uint32_t word; - } HBN_TIME_H; - - /* 0xC : RTC_TIME_L */ - - union - { - struct - { - uint32_t rtc_time_latch_l : 32; /* [31: 0], r, 0x0 */ - } bf; - uint32_t word; - } RTC_TIME_L; - - /* 0x10 : RTC_TIME_H */ - - union - { - struct - { - uint32_t rtc_time_latch_h : 8; /* [ 7: 0], r, 0x0 */ - uint32_t reserved_8_30 : 23; /* [30: 8], rsvd, 0x0 */ - uint32_t rtc_time_latch : 1; /* [ 31], w, 0x0 */ - } bf; - uint32_t word; - } RTC_TIME_H; - - /* 0x14 : HBN_IRQ_MODE */ - - union - { - struct - { - uint32_t hbn_pin_wakeup_mode : 3; /* [ 2: 0], r/w, 0x5 */ - uint32_t hbn_pin_wakeup_mask : 2; /* [ 4: 3], r/w, 0x0 */ - uint32_t reserved_5_7 : 3; /* [ 7: 5], rsvd, 0x0 */ - uint32_t reg_aon_pad_ie_smt : 1; /* [ 8], r/w, 0x1 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t reg_en_hw_pu_pd : 1; /* [ 16], r/w, 0x1 */ - uint32_t reserved_17 : 1; /* [ 17], rsvd, 0x0 */ - uint32_t irq_bor_en : 1; /* [ 18], r/w, 0x0 */ - uint32_t reserved_19 : 1; /* [ 19], rsvd, 0x0 */ - uint32_t irq_acomp0_en : 2; /* [21:20], r/w, 0x0 */ - uint32_t irq_acomp1_en : 2; /* [23:22], r/w, 0x0 */ - uint32_t pin_wakeup_sel : 3; /* [26:24], r/w, 0x3 */ - uint32_t pin_wakeup_en : 1; /* [ 27], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } bf; - uint32_t word; - } HBN_IRQ_MODE; - - /* 0x18 : HBN_IRQ_STAT */ - - union - { - struct - { - uint32_t irq_stat : 32; /* [31: 0], r, 0x0 */ - } bf; - uint32_t word; - } HBN_IRQ_STAT; - - /* 0x1C : HBN_IRQ_CLR */ - - union - { - struct - { - uint32_t irq_clr : 32; /* [31: 0], w, 0x0 */ - } bf; - uint32_t word; - } HBN_IRQ_CLR; - - /* 0x20 : HBN_PIR_CFG */ - - union - { - struct - { - uint32_t pir_hpf_sel : 2; /* [ 1: 0], r/w, 0x0 */ - uint32_t pir_lpf_sel : 1; /* [ 2], r/w, 0x0 */ - uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */ - uint32_t pir_dis : 2; /* [ 5: 4], r/w, 0x0 */ - uint32_t reserved_6 : 1; /* [ 6], rsvd, 0x0 */ - uint32_t pir_en : 1; /* [ 7], r/w, 0x0 */ - uint32_t gpadc_cgen : 1; /* [ 8], r/w, 0x0 */ - uint32_t gpadc_nosync : 1; /* [ 9], r/w, 0x0 */ - uint32_t reserved_10_31 : 22; /* [31:10], rsvd, 0x0 */ - } bf; - uint32_t word; - } HBN_PIR_CFG; - - /* 0x24 : HBN_PIR_VTH */ - - union - { - struct - { - uint32_t pir_vth : 14; /* [13: 0], r/w, 0x3ff */ - uint32_t reserved_14_31 : 18; /* [31:14], rsvd, 0x0 */ - } bf; - uint32_t word; - } HBN_PIR_VTH; - - /* 0x28 : HBN_PIR_INTERVAL */ - - union - { - struct - { - uint32_t pir_interval : 12; /* [11: 0], r/w, 0xa3d */ - uint32_t reserved_12_31 : 20; /* [31:12], rsvd, 0x0 */ - } bf; - uint32_t word; - } HBN_PIR_INTERVAL; - - /* 0x2C : HBN_BOR_CFG */ - - union - { - struct - { - uint32_t bor_sel : 1; /* [ 0], r/w, 0x0 */ - uint32_t bor_vth : 1; /* [ 1], r/w, 0x1 */ - uint32_t pu_bor : 1; /* [ 2], r/w, 0x0 */ - uint32_t r_bor_out : 1; /* [ 3], r, 0x0 */ - uint32_t reserved_4_31 : 28; /* [31: 4], rsvd, 0x0 */ - } bf; - uint32_t word; - } HBN_BOR_CFG; - - /* 0x30 : HBN_GLB */ - - union - { - struct - { - uint32_t hbn_root_clk_sel : 2; /* [ 1: 0], r/w, 0x0 */ - uint32_t hbn_uart_clk_sel : 1; /* [ 2], r/w, 0x0 */ - uint32_t hbn_f32k_sel : 2; /* [ 4: 3], r/w, 0x0 */ - uint32_t hbn_pu_rc32k : 1; /* [ 5], r/w, 0x1 */ - uint32_t reserved_6_15 : 10; /* [15: 6], rsvd, 0x0 */ - uint32_t sw_ldo11soc_vout_sel_aon : 4; /* [19:16], r/w, 0xa */ - uint32_t reserved_20_23 : 4; /* [23:20], rsvd, 0x0 */ - uint32_t sw_ldo11_rt_vout_sel : 4; /* [27:24], r/w, 0xa */ - uint32_t sw_ldo11_aon_vout_sel : 4; /* [31:28], r/w, 0xa */ - } bf; - uint32_t word; - } HBN_GLB; - - /* 0x34 : HBN_SRAM */ - - union - { - struct - { - uint32_t reserved_0_5 : 6; /* [ 5: 0], rsvd, 0x0 */ - uint32_t retram_ret : 1; /* [ 6], r/w, 0x0 */ - uint32_t retram_slp : 1; /* [ 7], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } bf; - uint32_t word; - } HBN_SRAM; - - /* 0x38 reserved */ - - uint8_t reserved_0x38[200]; - - /* 0x100 : HBN_RSV0 */ - - union - { - struct - { - uint32_t HBN_RSV0 : 32; /* [31: 0], r/w, 0x0 */ - } bf; - uint32_t word; - } HBN_RSV0; - - /* 0x104 : HBN_RSV1 */ - - union - { - struct - { - uint32_t HBN_RSV1 : 32; /* [31: 0], r/w, 0xffffffffL */ - } bf; - uint32_t word; - } HBN_RSV1; - - /* 0x108 : HBN_RSV2 */ - - union - { - struct - { - uint32_t HBN_RSV2 : 32; /* [31: 0], r/w, 0x0 */ - } bf; - uint32_t word; - } HBN_RSV2; - - /* 0x10C : HBN_RSV3 */ - - union - { - struct - { - uint32_t HBN_RSV3 : 32; /* [31: 0], r/w, 0xffffffffL */ - } bf; - uint32_t word; - } HBN_RSV3; - - /* 0x110 reserved */ - - uint8_t reserved_0x110[240]; - - /* 0x200 : rc32k_ctrl0 */ - - union - { - struct - { - uint32_t rc32k_cal_done : 1; /* [ 0], r, 0x1 */ - uint32_t rc32k_rdy : 1; /* [ 1], r, 0x1 */ - uint32_t rc32k_cal_inprogress : 1; /* [ 2], r, 0x0 */ - uint32_t rc32k_cal_div : 2; /* [ 4: 3], r/w, 0x3 */ - uint32_t rc32k_cal_precharge : 1; /* [ 5], r, 0x0 */ - uint32_t rc32k_dig_code_fr_cal : 10; /* [15: 6], r, 0x200 */ - uint32_t rc32k_vref_dly : 2; /* [17:16], r/w, 0x0 */ - uint32_t rc32k_allow_cal : 1; /* [ 18], r/w, 0x0 */ - uint32_t rc32k_ext_code_en : 1; /* [ 19], r/w, 0x1 */ - uint32_t rc32k_cal_en : 1; /* [ 20], r/w, 0x0 */ - uint32_t reserved_21 : 1; /* [ 21], rsvd, 0x0 */ - uint32_t rc32k_code_fr_ext : 10; /* [31:22], r/w, 0x140 */ - } bf; - uint32_t word; - } rc32k_ctrl0; - - /* 0x204 : xtal32k */ - - union - { - struct - { - uint32_t reserved_0_1 : 2; /* [ 1: 0], rsvd, 0x0 */ - uint32_t xtal32k_ext_sel : 1; /* [ 2], r/w, 0x0 */ - uint32_t xtal32k_amp_ctrl : 2; /* [ 4: 3], r/w, 0x1 */ - uint32_t xtal32k_reg : 2; /* [ 6: 5], r/w, 0x1 */ - uint32_t xtal32k_outbuf_stre : 1; /* [ 7], r/w, 0x0 */ - uint32_t xtal32k_otf_short : 1; /* [ 8], r/w, 0x0 */ - uint32_t xtal32k_inv_stre : 2; /* [10: 9], r/w, 0x1 */ - uint32_t xtal32k_capbank : 6; /* [16:11], r/w, 0x20 */ - uint32_t xtal32k_ac_cap_short : 1; /* [ 17], r/w, 0x1 */ - uint32_t pu_xtal32k_buf : 1; /* [ 18], r/w, 0x1 */ - uint32_t pu_xtal32k : 1; /* [ 19], r/w, 0x1 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } bf; - uint32_t word; - } xtal32k; -}; - -typedef volatile struct hbn_reg hbn_reg_t; +#define HBN_UART_CLK_FCLK 0 /* Select FCLK as UART clock */ +#define HBN_UART_CLK_160M 1 /* Select 160M as UART clock */ /**************************************************************************** * Public Data @@ -968,35 +654,12 @@ extern "C" #define EXTERN extern #endif -/**************************************************************************** - * Inline Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: - * - * Description: - * Description of the operation of the inline function. - * - * Input Parameters: - * A list of input parameters, one-per-line, appears here along with a - * description of each input parameter. - * - * Returned Value: - * Description of the value returned by this function (if any), - * including an enumeration of all possible error values. - * - * Assumptions/Limitations: - * Anything else that one might need to know to use this function. - * - ****************************************************************************/ - /**************************************************************************** * Public Function Prototypes ****************************************************************************/ /**************************************************************************** - * Name: hbn_set_uart_clk_sel + * Name: bl602_hbn_set_uart_clk_sel * * Description: * Select uart clock source. @@ -1013,7 +676,7 @@ extern "C" * ****************************************************************************/ -EXTERN void hbn_set_uart_clk_sel(enum hbn_uart_clk_type_e clk_sel); +EXTERN void bl602_hbn_set_uart_clk_sel(int clk_sel); #undef EXTERN #ifdef __cplusplus diff --git a/arch/risc-v/src/bl602/hardware/bl602_timer.h b/arch/risc-v/src/bl602/hardware/bl602_timer.h index 97538ba5c68..46f211b81eb 100644 --- a/arch/risc-v/src/bl602/hardware/bl602_timer.h +++ b/arch/risc-v/src/bl602/hardware/bl602_timer.h @@ -1,6 +1,9 @@ /**************************************************************************** * arch/risc-v/src/bl602/hardware/bl602_timer.h * + * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with * this work for additional information regarding copyright ownership. The @@ -500,116 +503,85 @@ #define TIMER_WCDR_MSK (((1U << TIMER_WCDR_LEN) - 1) << TIMER_WCDR_POS) #define TIMER_WCDR_UMSK (~(((1U << TIMER_WCDR_LEN) - 1) << TIMER_WCDR_POS)) -#define WDT_ENABLE_ACCESS() \ - { \ - BL_WR_REG(TIMER_BASE, \ - TIMER_WFAR, \ - BL_SET_REG_BITS_VAL( \ - BL_RD_REG(TIMER_BASE, TIMER_WFAR), TIMER_WFAR, 0xBABA)); \ - BL_WR_REG(TIMER_BASE, \ - TIMER_WSAR, \ - BL_SET_REG_BITS_VAL( \ - BL_RD_REG(TIMER_BASE, TIMER_WSAR), TIMER_WSAR, 0xEB10)); \ - } +/* TIMER channel type definition */ + +#define TIMER_CH0 0 /* TIMER channel 0 port define */ +#define TIMER_CH1 1 /* TIMER channel 1 port define */ +#define TIMER_CH_MAX 2 + +/* TIMER clock source type definition */ + +#define TIMER_CLKSRC_FCLK 0 /* TIMER clock source :System CLK */ +#define TIMER_CLKSRC_32K 1 /* TIMER clock source :32K CLK */ +#define TIMER_CLKSRC_1K 2 /* TIMER clock source :1K CLK,Only for + * Timer not for Watchdog */ + +#define TIMER_CLKSRC_XTAL 3 /* TIMER clock source :XTAL CLK */ + +/* TIMER match compare ID type definition */ + +#define TIMER_COMP_ID_0 0 /* TIMER match compare ID 0 define */ +#define TIMER_COMP_ID_1 1 /* TIMER match compare ID 1 define */ +#define TIMER_COMP_ID_2 2 /* TIMER match compare ID 2 define */ + +/* TIMER preload source type definition */ + +#define TIMER_PRELOAD_TRIG_NONE 0 /* TIMER no preload source, just free run \ + */ +#define TIMER_PRELOAD_TRIG_COMP0 \ + 1 /* TIMER count register preload triggered by \ + * comparator 0 */ + +#define TIMER_PRELOAD_TRIG_COMP1 \ + 2 /* TIMER count register preload triggered by \ + * comparator 1 */ + +#define TIMER_PRELOAD_TRIG_COMP2 \ + 3 /* TIMER count register preload triggered by \ + * comparator 2 */ + +/* TIMER count register run mode type definition */ + +#define TIMER_COUNT_PRELOAD \ + 0 /* TIMER count register preload from comparator \ + * register */ + +#define TIMER_COUNT_FREERUN 1 /* TIMER count register free run */ + +/* TIMER interrupt type definition */ + +#define TIMER_INT_COMP_0 0 /* Comparator 0 match cause interrupt */ +#define TIMER_INT_COMP_1 1 /* Comparator 1 match cause interrupt */ +#define TIMER_INT_COMP_2 2 /* Comparator 2 match cause interrupt */ +#define TIMER_INT_ALL 3 + +/* Watchdog timer interrupt type definition */ + +#define WDT_INT 0 /* Comparator 0 match cause interrupt */ +#define WDT_INT_ALL 1 /**************************************************************************** * Public Types ****************************************************************************/ #ifndef __ASSEMBLY__ -/* TIMER channel type definition */ - -enum timer_chan_e -{ - TIMER_CH0, /* TIMER channel 0 port define */ - TIMER_CH1, /* TIMER channel 1 port define */ - TIMER_CH_MAX -}; -typedef enum timer_chan_e timer_chan_t; - -/* TIMER clock source type definition */ - -enum timer_clksrc_e -{ - TIMER_CLKSRC_FCLK, /* TIMER clock source :System CLK */ - TIMER_CLKSRC_32K, /* TIMER clock source :32K CLK */ - TIMER_CLKSRC_1K, /* TIMER clock source :1K CLK,Only for Timer not for - * Watchdog */ - TIMER_CLKSRC_XTAL /* TIMER clock source :XTAL CLK */ -}; -typedef enum timer_clksrc_e timer_clksrc_t; - -/* TIMER match compare ID type definition */ - -enum timer_comp_id_e -{ - TIMER_COMP_ID_0, /* TIMER match compare ID 0 define */ - TIMER_COMP_ID_1, /* TIMER match compare ID 1 define */ - TIMER_COMP_ID_2 /* TIMER match compare ID 2 define */ -}; -typedef enum timer_comp_id_e timer_comp_id_t; - -/* TIMER preload source type definition */ - -enum timer_preload_trig_e -{ - TIMER_PRELOAD_TRIG_NONE, /* TIMER no preload source, just free run */ - TIMER_PRELOAD_TRIG_COMP0, /* TIMER count register preload triggered by - * comparator 0 */ - TIMER_PRELOAD_TRIG_COMP1, /* TIMER count register preload triggered by - * comparator 1 */ - TIMER_PRELOAD_TRIG_COMP2 /* TIMER count register preload triggered by - * comparator 2 */ -}; -typedef enum timer_preload_trig_e timer_preload_trig_t; - -/* TIMER count register run mode type definition */ - -enum timer_countmode_e -{ - TIMER_COUNT_PRELOAD, /* TIMER count register preload from comparator - * register */ - TIMER_COUNT_FREERUN /* TIMER count register free run */ -}; -typedef enum timer_countmode_e timer_countmode_t; - -/* TIMER interrupt type definition */ - -enum timer_int_e -{ - TIMER_INT_COMP_0, /* Comparator 0 match cause interrupt */ - TIMER_INT_COMP_1, /* Comparator 1 match cause interrupt */ - TIMER_INT_COMP_2, /* Comparator 2 match cause interrupt */ - TIMER_INT_ALL -}; -typedef enum timer_int_e timer_int_t; - -/* Watchdog timer interrupt type definition */ - -enum wdt_int_e -{ - WDT_INT, /* Comparator 0 match cause interrupt */ - WDT_INT_ALL -}; -typedef enum wdt_int_e wdt_int_t; - /* TIMER configuration structure type definition */ struct timer_cfg_s { - timer_chan_t timer_ch; /* Timer channel */ - timer_clksrc_t clk_src; /* Timer clock source */ + uint32_t timer_ch; /* Timer channel */ + uint32_t clk_src; /* Timer clock source */ /* Timer count register preload trigger source slelect */ - timer_preload_trig_t pl_trig_src; + uint32_t pl_trig_src; - timer_countmode_t count_mode; /* Timer count mode */ - uint8_t clock_division; /* Timer clock divison value */ - uint32_t match_val0; /* Timer match 0 value 0 */ - uint32_t match_val1; /* Timer match 1 value 0 */ - uint32_t match_val2; /* Timer match 2 value 0 */ - uint32_t pre_load_val; /* Timer preload value */ + uint32_t count_mode; /* Timer count mode */ + uint8_t clock_division; /* Timer clock divison value */ + uint32_t match_val0; /* Timer match 0 value 0 */ + uint32_t match_val1; /* Timer match 1 value 0 */ + uint32_t match_val2; /* Timer match 2 value 0 */ + uint32_t pre_load_val; /* Timer preload value */ }; typedef struct timer_cfg_s timer_cfg_t; @@ -626,37 +598,33 @@ extern "C" * Public Function Prototypes ****************************************************************************/ -EXTERN uint32_t timer_getcompvalue(timer_chan_t timer_ch, - timer_comp_id_t cmp_no); -EXTERN void timer_setcompvalue(timer_chan_t timer_ch, - timer_comp_id_t cmp_no, - uint32_t val); -EXTERN uint32_t timer_getcountervalue(timer_chan_t timer_ch); -EXTERN uint32_t timer_getmatchstatus(timer_chan_t timer_ch, - timer_comp_id_t cmp_no); -EXTERN uint32_t timer_getpreloadvalue(timer_chan_t timer_ch); -EXTERN void timer_setpreloadvalue(timer_chan_t timer_ch, uint32_t val); -EXTERN void timer_setpreloadtrigsrc(timer_chan_t timer_ch, - timer_preload_trig_t pl_src); -EXTERN void timer_setcountmode(timer_chan_t timer_ch, - timer_countmode_t count_mode); -EXTERN void timer_clearintstatus(timer_chan_t timer_ch, - timer_comp_id_t cmp_no); -EXTERN void timer_init(timer_cfg_t *timer_cfg); -EXTERN void timer_enable(timer_chan_t timer_ch); -EXTERN void timer_disable(timer_chan_t timer_ch); -EXTERN void timer_intmask(timer_chan_t timer_ch, - timer_int_t int_type, uint32_t int_mask); -EXTERN void wdt_set_clock(timer_clksrc_t clk_src, uint8_t div); -EXTERN uint32_t wdt_getmatchvalue(void); -EXTERN void wdt_setcompvalue(uint16_t val); -EXTERN uint16_t wdt_getcountervalue(void); -EXTERN void wdt_resetcountervalue(void); -EXTERN uint32_t wdt_getresetstatus(void); -EXTERN void wdt_clearresetstatus(void); -EXTERN void wdt_enable(void); -EXTERN void wdt_disable(void); -EXTERN void wdt_intmask(wdt_int_t int_type, uint32_t int_mask); +EXTERN uint32_t bl602_timer_getcompvalue(uint32_t timer_ch, uint32_t cmp_no); +EXTERN void bl602_timer_setcompvalue(uint32_t timer_ch, uint32_t cmp_no, + uint32_t val); +EXTERN uint32_t bl602_timer_getcountervalue(uint32_t timer_ch); +EXTERN uint32_t bl602_timer_getmatchstatus(uint32_t timer_ch, + uint32_t cmp_no); +EXTERN uint32_t bl602_timer_getpreloadvalue(uint32_t timer_ch); +EXTERN void bl602_timer_setpreloadvalue(uint32_t timer_ch, uint32_t val); +EXTERN void bl602_timer_setpreloadtrigsrc(uint32_t timer_ch, + uint32_t pl_src); +EXTERN void bl602_timer_setcountmode(uint32_t timer_ch, uint32_t count_mode); +EXTERN void bl602_timer_clearintstatus(uint32_t timer_ch, uint32_t cmp_no); +EXTERN void bl602_timer_init(timer_cfg_t *timer_cfg); +EXTERN void bl602_timer_enable(uint32_t timer_ch); +EXTERN void bl602_timer_disable(uint32_t timer_ch); +EXTERN void bl602_timer_intmask(uint32_t timer_ch, uint32_t int_type, + uint32_t int_mask); +EXTERN void bl602_wdt_set_clock(uint32_t clk_src, uint8_t div); +EXTERN uint32_t bl602_wdt_getmatchvalue(void); +EXTERN void bl602_wdt_setcompvalue(uint16_t val); +EXTERN uint16_t bl602_wdt_getcountervalue(void); +EXTERN void bl602_wdt_resetcountervalue(void); +EXTERN uint32_t bl602_wdt_getresetstatus(void); +EXTERN void bl602_wdt_clearresetstatus(void); +EXTERN void bl602_wdt_enable(void); +EXTERN void bl602_wdt_disable(void); +EXTERN void bl602_wdt_intmask(uint32_t int_type, uint32_t int_mask); #undef EXTERN #if defined(__cplusplus) diff --git a/arch/risc-v/src/bl602/hardware/bl602_uart.h b/arch/risc-v/src/bl602/hardware/bl602_uart.h index 786c5765951..19ceb64e8b8 100644 --- a/arch/risc-v/src/bl602/hardware/bl602_uart.h +++ b/arch/risc-v/src/bl602/hardware/bl602_uart.h @@ -1,6 +1,9 @@ /**************************************************************************** * arch/risc-v/src/bl602/hardware/bl602_uart.h * + * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with * this work for additional information regarding copyright ownership. The @@ -35,599 +38,661 @@ #define UART_UTX_CONFIG_OFFSET (0x0) #define UART_CR_UTX_EN UART_CR_UTX_EN -#define UART_CR_UTX_EN_POS (0U) -#define UART_CR_UTX_EN_LEN (1U) +#define UART_CR_UTX_EN_POS (0) +#define UART_CR_UTX_EN_LEN (1) #define UART_CR_UTX_EN_MSK \ - (((1U << UART_CR_UTX_EN_LEN) - 1) << UART_CR_UTX_EN_POS) + (((1 << UART_CR_UTX_EN_LEN) - 1) << UART_CR_UTX_EN_POS) #define UART_CR_UTX_EN_UMSK \ - (~(((1U << UART_CR_UTX_EN_LEN) - 1) << UART_CR_UTX_EN_POS)) + (~(((1 << UART_CR_UTX_EN_LEN) - 1) << UART_CR_UTX_EN_POS)) #define UART_CR_UTX_CTS_EN UART_CR_UTX_CTS_EN -#define UART_CR_UTX_CTS_EN_POS (1U) -#define UART_CR_UTX_CTS_EN_LEN (1U) +#define UART_CR_UTX_CTS_EN_POS (1) +#define UART_CR_UTX_CTS_EN_LEN (1) #define UART_CR_UTX_CTS_EN_MSK \ - (((1U << UART_CR_UTX_CTS_EN_LEN) - 1) << UART_CR_UTX_CTS_EN_POS) + (((1 << UART_CR_UTX_CTS_EN_LEN) - 1) << UART_CR_UTX_CTS_EN_POS) #define UART_CR_UTX_CTS_EN_UMSK \ - (~(((1U << UART_CR_UTX_CTS_EN_LEN) - 1) << UART_CR_UTX_CTS_EN_POS)) + (~(((1 << UART_CR_UTX_CTS_EN_LEN) - 1) << UART_CR_UTX_CTS_EN_POS)) #define UART_CR_UTX_FRM_EN UART_CR_UTX_FRM_EN -#define UART_CR_UTX_FRM_EN_POS (2U) -#define UART_CR_UTX_FRM_EN_LEN (1U) +#define UART_CR_UTX_FRM_EN_POS (2) +#define UART_CR_UTX_FRM_EN_LEN (1) #define UART_CR_UTX_FRM_EN_MSK \ - (((1U << UART_CR_UTX_FRM_EN_LEN) - 1) << UART_CR_UTX_FRM_EN_POS) + (((1 << UART_CR_UTX_FRM_EN_LEN) - 1) << UART_CR_UTX_FRM_EN_POS) #define UART_CR_UTX_FRM_EN_UMSK \ - (~(((1U << UART_CR_UTX_FRM_EN_LEN) - 1) << UART_CR_UTX_FRM_EN_POS)) + (~(((1 << UART_CR_UTX_FRM_EN_LEN) - 1) << UART_CR_UTX_FRM_EN_POS)) #define UART_CR_UTX_PRT_EN UART_CR_UTX_PRT_EN -#define UART_CR_UTX_PRT_EN_POS (4U) -#define UART_CR_UTX_PRT_EN_LEN (1U) +#define UART_CR_UTX_PRT_EN_POS (4) +#define UART_CR_UTX_PRT_EN_LEN (1) #define UART_CR_UTX_PRT_EN_MSK \ - (((1U << UART_CR_UTX_PRT_EN_LEN) - 1) << UART_CR_UTX_PRT_EN_POS) + (((1 << UART_CR_UTX_PRT_EN_LEN) - 1) << UART_CR_UTX_PRT_EN_POS) #define UART_CR_UTX_PRT_EN_UMSK \ - (~(((1U << UART_CR_UTX_PRT_EN_LEN) - 1) << UART_CR_UTX_PRT_EN_POS)) + (~(((1 << UART_CR_UTX_PRT_EN_LEN) - 1) << UART_CR_UTX_PRT_EN_POS)) #define UART_CR_UTX_PRT_SEL UART_CR_UTX_PRT_SEL -#define UART_CR_UTX_PRT_SEL_POS (5U) -#define UART_CR_UTX_PRT_SEL_LEN (1U) +#define UART_CR_UTX_PRT_SEL_POS (5) +#define UART_CR_UTX_PRT_SEL_LEN (1) #define UART_CR_UTX_PRT_SEL_MSK \ - (((1U << UART_CR_UTX_PRT_SEL_LEN) - 1) << UART_CR_UTX_PRT_SEL_POS) + (((1 << UART_CR_UTX_PRT_SEL_LEN) - 1) << UART_CR_UTX_PRT_SEL_POS) #define UART_CR_UTX_PRT_SEL_UMSK \ - (~(((1U << UART_CR_UTX_PRT_SEL_LEN) - 1) << UART_CR_UTX_PRT_SEL_POS)) + (~(((1 << UART_CR_UTX_PRT_SEL_LEN) - 1) << UART_CR_UTX_PRT_SEL_POS)) #define UART_CR_UTX_IR_EN UART_CR_UTX_IR_EN -#define UART_CR_UTX_IR_EN_POS (6U) -#define UART_CR_UTX_IR_EN_LEN (1U) +#define UART_CR_UTX_IR_EN_POS (6) +#define UART_CR_UTX_IR_EN_LEN (1) #define UART_CR_UTX_IR_EN_MSK \ - (((1U << UART_CR_UTX_IR_EN_LEN) - 1) << UART_CR_UTX_IR_EN_POS) + (((1 << UART_CR_UTX_IR_EN_LEN) - 1) << UART_CR_UTX_IR_EN_POS) #define UART_CR_UTX_IR_EN_UMSK \ - (~(((1U << UART_CR_UTX_IR_EN_LEN) - 1) << UART_CR_UTX_IR_EN_POS)) + (~(((1 << UART_CR_UTX_IR_EN_LEN) - 1) << UART_CR_UTX_IR_EN_POS)) #define UART_CR_UTX_IR_INV UART_CR_UTX_IR_INV -#define UART_CR_UTX_IR_INV_POS (7U) -#define UART_CR_UTX_IR_INV_LEN (1U) +#define UART_CR_UTX_IR_INV_POS (7) +#define UART_CR_UTX_IR_INV_LEN (1) #define UART_CR_UTX_IR_INV_MSK \ - (((1U << UART_CR_UTX_IR_INV_LEN) - 1) << UART_CR_UTX_IR_INV_POS) + (((1 << UART_CR_UTX_IR_INV_LEN) - 1) << UART_CR_UTX_IR_INV_POS) #define UART_CR_UTX_IR_INV_UMSK \ - (~(((1U << UART_CR_UTX_IR_INV_LEN) - 1) << UART_CR_UTX_IR_INV_POS)) + (~(((1 << UART_CR_UTX_IR_INV_LEN) - 1) << UART_CR_UTX_IR_INV_POS)) #define UART_CR_UTX_BIT_CNT_D UART_CR_UTX_BIT_CNT_D -#define UART_CR_UTX_BIT_CNT_D_POS (8U) -#define UART_CR_UTX_BIT_CNT_D_LEN (3U) +#define UART_CR_UTX_BIT_CNT_D_POS (8) +#define UART_CR_UTX_BIT_CNT_D_LEN (3) #define UART_CR_UTX_BIT_CNT_D_MSK \ - (((1U << UART_CR_UTX_BIT_CNT_D_LEN) - 1) << UART_CR_UTX_BIT_CNT_D_POS) + (((1 << UART_CR_UTX_BIT_CNT_D_LEN) - 1) << UART_CR_UTX_BIT_CNT_D_POS) #define UART_CR_UTX_BIT_CNT_D_UMSK \ - (~(((1U << UART_CR_UTX_BIT_CNT_D_LEN) - 1) << UART_CR_UTX_BIT_CNT_D_POS)) + (~(((1 << UART_CR_UTX_BIT_CNT_D_LEN) - 1) << UART_CR_UTX_BIT_CNT_D_POS)) #define UART_CR_UTX_BIT_CNT_P UART_CR_UTX_BIT_CNT_P -#define UART_CR_UTX_BIT_CNT_P_POS (12U) -#define UART_CR_UTX_BIT_CNT_P_LEN (2U) +#define UART_CR_UTX_BIT_CNT_P_POS (12) +#define UART_CR_UTX_BIT_CNT_P_LEN (2) #define UART_CR_UTX_BIT_CNT_P_MSK \ - (((1U << UART_CR_UTX_BIT_CNT_P_LEN) - 1) << UART_CR_UTX_BIT_CNT_P_POS) + (((1 << UART_CR_UTX_BIT_CNT_P_LEN) - 1) << UART_CR_UTX_BIT_CNT_P_POS) #define UART_CR_UTX_BIT_CNT_P_UMSK \ - (~(((1U << UART_CR_UTX_BIT_CNT_P_LEN) - 1) << UART_CR_UTX_BIT_CNT_P_POS)) + (~(((1 << UART_CR_UTX_BIT_CNT_P_LEN) - 1) << UART_CR_UTX_BIT_CNT_P_POS)) #define UART_CR_UTX_LEN UART_CR_UTX_LEN -#define UART_CR_UTX_LEN_POS (16U) -#define UART_CR_UTX_LEN_LEN (16U) +#define UART_CR_UTX_LEN_POS (16) +#define UART_CR_UTX_LEN_LEN (16) #define UART_CR_UTX_LEN_MSK \ - (((1U << UART_CR_UTX_LEN_LEN) - 1) << UART_CR_UTX_LEN_POS) + (((1 << UART_CR_UTX_LEN_LEN) - 1) << UART_CR_UTX_LEN_POS) #define UART_CR_UTX_LEN_UMSK \ - (~(((1U << UART_CR_UTX_LEN_LEN) - 1) << UART_CR_UTX_LEN_POS)) + (~(((1 << UART_CR_UTX_LEN_LEN) - 1) << UART_CR_UTX_LEN_POS)) /* 0x4 : urx_config */ #define UART_URX_CONFIG_OFFSET (0x4) #define UART_CR_URX_EN UART_CR_URX_EN -#define UART_CR_URX_EN_POS (0U) -#define UART_CR_URX_EN_LEN (1U) +#define UART_CR_URX_EN_POS (0) +#define UART_CR_URX_EN_LEN (1) #define UART_CR_URX_EN_MSK \ - (((1U << UART_CR_URX_EN_LEN) - 1) << UART_CR_URX_EN_POS) + (((1 << UART_CR_URX_EN_LEN) - 1) << UART_CR_URX_EN_POS) #define UART_CR_URX_EN_UMSK \ - (~(((1U << UART_CR_URX_EN_LEN) - 1) << UART_CR_URX_EN_POS)) + (~(((1 << UART_CR_URX_EN_LEN) - 1) << UART_CR_URX_EN_POS)) #define UART_CR_URX_RTS_SW_MODE UART_CR_URX_RTS_SW_MODE -#define UART_CR_URX_RTS_SW_MODE_POS (1U) -#define UART_CR_URX_RTS_SW_MODE_LEN (1U) +#define UART_CR_URX_RTS_SW_MODE_POS (1) +#define UART_CR_URX_RTS_SW_MODE_LEN (1) #define UART_CR_URX_RTS_SW_MODE_MSK \ - (((1U << UART_CR_URX_RTS_SW_MODE_LEN) - 1) << UART_CR_URX_RTS_SW_MODE_POS) + (((1 << UART_CR_URX_RTS_SW_MODE_LEN) - 1) << UART_CR_URX_RTS_SW_MODE_POS) #define UART_CR_URX_RTS_SW_MODE_UMSK \ - (~(((1U << UART_CR_URX_RTS_SW_MODE_LEN) - 1) \ - << UART_CR_URX_RTS_SW_MODE_POS)) + (~(((1 << UART_CR_URX_RTS_SW_MODE_LEN) - 1) << UART_CR_URX_RTS_SW_MODE_POS)) #define UART_CR_URX_RTS_SW_VAL UART_CR_URX_RTS_SW_VAL -#define UART_CR_URX_RTS_SW_VAL_POS (2U) -#define UART_CR_URX_RTS_SW_VAL_LEN (1U) +#define UART_CR_URX_RTS_SW_VAL_POS (2) +#define UART_CR_URX_RTS_SW_VAL_LEN (1) #define UART_CR_URX_RTS_SW_VAL_MSK \ - (((1U << UART_CR_URX_RTS_SW_VAL_LEN) - 1) << UART_CR_URX_RTS_SW_VAL_POS) + (((1 << UART_CR_URX_RTS_SW_VAL_LEN) - 1) << UART_CR_URX_RTS_SW_VAL_POS) #define UART_CR_URX_RTS_SW_VAL_UMSK \ - (~(((1U << UART_CR_URX_RTS_SW_VAL_LEN) - 1) << UART_CR_URX_RTS_SW_VAL_POS)) + (~(((1 << UART_CR_URX_RTS_SW_VAL_LEN) - 1) << UART_CR_URX_RTS_SW_VAL_POS)) #define UART_CR_URX_ABR_EN UART_CR_URX_ABR_EN -#define UART_CR_URX_ABR_EN_POS (3U) -#define UART_CR_URX_ABR_EN_LEN (1U) +#define UART_CR_URX_ABR_EN_POS (3) +#define UART_CR_URX_ABR_EN_LEN (1) #define UART_CR_URX_ABR_EN_MSK \ - (((1U << UART_CR_URX_ABR_EN_LEN) - 1) << UART_CR_URX_ABR_EN_POS) + (((1 << UART_CR_URX_ABR_EN_LEN) - 1) << UART_CR_URX_ABR_EN_POS) #define UART_CR_URX_ABR_EN_UMSK \ - (~(((1U << UART_CR_URX_ABR_EN_LEN) - 1) << UART_CR_URX_ABR_EN_POS)) + (~(((1 << UART_CR_URX_ABR_EN_LEN) - 1) << UART_CR_URX_ABR_EN_POS)) #define UART_CR_URX_PRT_EN UART_CR_URX_PRT_EN -#define UART_CR_URX_PRT_EN_POS (4U) -#define UART_CR_URX_PRT_EN_LEN (1U) +#define UART_CR_URX_PRT_EN_POS (4) +#define UART_CR_URX_PRT_EN_LEN (1) #define UART_CR_URX_PRT_EN_MSK \ - (((1U << UART_CR_URX_PRT_EN_LEN) - 1) << UART_CR_URX_PRT_EN_POS) + (((1 << UART_CR_URX_PRT_EN_LEN) - 1) << UART_CR_URX_PRT_EN_POS) #define UART_CR_URX_PRT_EN_UMSK \ - (~(((1U << UART_CR_URX_PRT_EN_LEN) - 1) << UART_CR_URX_PRT_EN_POS)) + (~(((1 << UART_CR_URX_PRT_EN_LEN) - 1) << UART_CR_URX_PRT_EN_POS)) #define UART_CR_URX_PRT_SEL UART_CR_URX_PRT_SEL -#define UART_CR_URX_PRT_SEL_POS (5U) -#define UART_CR_URX_PRT_SEL_LEN (1U) +#define UART_CR_URX_PRT_SEL_POS (5) +#define UART_CR_URX_PRT_SEL_LEN (1) #define UART_CR_URX_PRT_SEL_MSK \ - (((1U << UART_CR_URX_PRT_SEL_LEN) - 1) << UART_CR_URX_PRT_SEL_POS) + (((1 << UART_CR_URX_PRT_SEL_LEN) - 1) << UART_CR_URX_PRT_SEL_POS) #define UART_CR_URX_PRT_SEL_UMSK \ - (~(((1U << UART_CR_URX_PRT_SEL_LEN) - 1) << UART_CR_URX_PRT_SEL_POS)) + (~(((1 << UART_CR_URX_PRT_SEL_LEN) - 1) << UART_CR_URX_PRT_SEL_POS)) #define UART_CR_URX_IR_EN UART_CR_URX_IR_EN -#define UART_CR_URX_IR_EN_POS (6U) -#define UART_CR_URX_IR_EN_LEN (1U) +#define UART_CR_URX_IR_EN_POS (6) +#define UART_CR_URX_IR_EN_LEN (1) #define UART_CR_URX_IR_EN_MSK \ - (((1U << UART_CR_URX_IR_EN_LEN) - 1) << UART_CR_URX_IR_EN_POS) + (((1 << UART_CR_URX_IR_EN_LEN) - 1) << UART_CR_URX_IR_EN_POS) #define UART_CR_URX_IR_EN_UMSK \ - (~(((1U << UART_CR_URX_IR_EN_LEN) - 1) << UART_CR_URX_IR_EN_POS)) + (~(((1 << UART_CR_URX_IR_EN_LEN) - 1) << UART_CR_URX_IR_EN_POS)) #define UART_CR_URX_IR_INV UART_CR_URX_IR_INV -#define UART_CR_URX_IR_INV_POS (7U) -#define UART_CR_URX_IR_INV_LEN (1U) +#define UART_CR_URX_IR_INV_POS (7) +#define UART_CR_URX_IR_INV_LEN (1) #define UART_CR_URX_IR_INV_MSK \ - (((1U << UART_CR_URX_IR_INV_LEN) - 1) << UART_CR_URX_IR_INV_POS) + (((1 << UART_CR_URX_IR_INV_LEN) - 1) << UART_CR_URX_IR_INV_POS) #define UART_CR_URX_IR_INV_UMSK \ - (~(((1U << UART_CR_URX_IR_INV_LEN) - 1) << UART_CR_URX_IR_INV_POS)) + (~(((1 << UART_CR_URX_IR_INV_LEN) - 1) << UART_CR_URX_IR_INV_POS)) #define UART_CR_URX_BIT_CNT_D UART_CR_URX_BIT_CNT_D -#define UART_CR_URX_BIT_CNT_D_POS (8U) -#define UART_CR_URX_BIT_CNT_D_LEN (3U) +#define UART_CR_URX_BIT_CNT_D_POS (8) +#define UART_CR_URX_BIT_CNT_D_LEN (3) #define UART_CR_URX_BIT_CNT_D_MSK \ - (((1U << UART_CR_URX_BIT_CNT_D_LEN) - 1) << UART_CR_URX_BIT_CNT_D_POS) + (((1 << UART_CR_URX_BIT_CNT_D_LEN) - 1) << UART_CR_URX_BIT_CNT_D_POS) #define UART_CR_URX_BIT_CNT_D_UMSK \ - (~(((1U << UART_CR_URX_BIT_CNT_D_LEN) - 1) << UART_CR_URX_BIT_CNT_D_POS)) + (~(((1 << UART_CR_URX_BIT_CNT_D_LEN) - 1) << UART_CR_URX_BIT_CNT_D_POS)) #define UART_CR_URX_DEG_EN UART_CR_URX_DEG_EN -#define UART_CR_URX_DEG_EN_POS (11U) -#define UART_CR_URX_DEG_EN_LEN (1U) +#define UART_CR_URX_DEG_EN_POS (11) +#define UART_CR_URX_DEG_EN_LEN (1) #define UART_CR_URX_DEG_EN_MSK \ - (((1U << UART_CR_URX_DEG_EN_LEN) - 1) << UART_CR_URX_DEG_EN_POS) + (((1 << UART_CR_URX_DEG_EN_LEN) - 1) << UART_CR_URX_DEG_EN_POS) #define UART_CR_URX_DEG_EN_UMSK \ - (~(((1U << UART_CR_URX_DEG_EN_LEN) - 1) << UART_CR_URX_DEG_EN_POS)) + (~(((1 << UART_CR_URX_DEG_EN_LEN) - 1) << UART_CR_URX_DEG_EN_POS)) #define UART_CR_URX_DEG_CNT UART_CR_URX_DEG_CNT -#define UART_CR_URX_DEG_CNT_POS (12U) -#define UART_CR_URX_DEG_CNT_LEN (4U) +#define UART_CR_URX_DEG_CNT_POS (12) +#define UART_CR_URX_DEG_CNT_LEN (4) #define UART_CR_URX_DEG_CNT_MSK \ - (((1U << UART_CR_URX_DEG_CNT_LEN) - 1) << UART_CR_URX_DEG_CNT_POS) + (((1 << UART_CR_URX_DEG_CNT_LEN) - 1) << UART_CR_URX_DEG_CNT_POS) #define UART_CR_URX_DEG_CNT_UMSK \ - (~(((1U << UART_CR_URX_DEG_CNT_LEN) - 1) << UART_CR_URX_DEG_CNT_POS)) + (~(((1 << UART_CR_URX_DEG_CNT_LEN) - 1) << UART_CR_URX_DEG_CNT_POS)) #define UART_CR_URX_LEN UART_CR_URX_LEN -#define UART_CR_URX_LEN_POS (16U) -#define UART_CR_URX_LEN_LEN (16U) +#define UART_CR_URX_LEN_POS (16) +#define UART_CR_URX_LEN_LEN (16) #define UART_CR_URX_LEN_MSK \ - (((1U << UART_CR_URX_LEN_LEN) - 1) << UART_CR_URX_LEN_POS) + (((1 << UART_CR_URX_LEN_LEN) - 1) << UART_CR_URX_LEN_POS) #define UART_CR_URX_LEN_UMSK \ - (~(((1U << UART_CR_URX_LEN_LEN) - 1) << UART_CR_URX_LEN_POS)) + (~(((1 << UART_CR_URX_LEN_LEN) - 1) << UART_CR_URX_LEN_POS)) /* 0x8 : uart_bit_prd */ #define UART_BIT_PRD_OFFSET (0x8) #define UART_CR_UTX_BIT_PRD UART_CR_UTX_BIT_PRD -#define UART_CR_UTX_BIT_PRD_POS (0U) -#define UART_CR_UTX_BIT_PRD_LEN (16U) +#define UART_CR_UTX_BIT_PRD_POS (0) +#define UART_CR_UTX_BIT_PRD_LEN (16) #define UART_CR_UTX_BIT_PRD_MSK \ - (((1U << UART_CR_UTX_BIT_PRD_LEN) - 1) << UART_CR_UTX_BIT_PRD_POS) + (((1 << UART_CR_UTX_BIT_PRD_LEN) - 1) << UART_CR_UTX_BIT_PRD_POS) #define UART_CR_UTX_BIT_PRD_UMSK \ - (~(((1U << UART_CR_UTX_BIT_PRD_LEN) - 1) << UART_CR_UTX_BIT_PRD_POS)) + (~(((1 << UART_CR_UTX_BIT_PRD_LEN) - 1) << UART_CR_UTX_BIT_PRD_POS)) #define UART_CR_URX_BIT_PRD UART_CR_URX_BIT_PRD -#define UART_CR_URX_BIT_PRD_POS (16U) -#define UART_CR_URX_BIT_PRD_LEN (16U) +#define UART_CR_URX_BIT_PRD_POS (16) +#define UART_CR_URX_BIT_PRD_LEN (16) #define UART_CR_URX_BIT_PRD_MSK \ - (((1U << UART_CR_URX_BIT_PRD_LEN) - 1) << UART_CR_URX_BIT_PRD_POS) + (((1 << UART_CR_URX_BIT_PRD_LEN) - 1) << UART_CR_URX_BIT_PRD_POS) #define UART_CR_URX_BIT_PRD_UMSK \ - (~(((1U << UART_CR_URX_BIT_PRD_LEN) - 1) << UART_CR_URX_BIT_PRD_POS)) + (~(((1 << UART_CR_URX_BIT_PRD_LEN) - 1) << UART_CR_URX_BIT_PRD_POS)) /* 0xC : data_config */ #define UART_DATA_CONFIG_OFFSET (0xC) #define UART_CR_UART_BIT_INV UART_CR_UART_BIT_INV -#define UART_CR_UART_BIT_INV_POS (0U) -#define UART_CR_UART_BIT_INV_LEN (1U) +#define UART_CR_UART_BIT_INV_POS (0) +#define UART_CR_UART_BIT_INV_LEN (1) #define UART_CR_UART_BIT_INV_MSK \ - (((1U << UART_CR_UART_BIT_INV_LEN) - 1) << UART_CR_UART_BIT_INV_POS) + (((1 << UART_CR_UART_BIT_INV_LEN) - 1) << UART_CR_UART_BIT_INV_POS) #define UART_CR_UART_BIT_INV_UMSK \ - (~(((1U << UART_CR_UART_BIT_INV_LEN) - 1) << UART_CR_UART_BIT_INV_POS)) + (~(((1 << UART_CR_UART_BIT_INV_LEN) - 1) << UART_CR_UART_BIT_INV_POS)) /* 0x10 : utx_ir_position */ #define UART_UTX_IR_POSITION_OFFSET (0x10) #define UART_CR_UTX_IR_POS_S UART_CR_UTX_IR_POS_S -#define UART_CR_UTX_IR_POS_S_POS (0U) -#define UART_CR_UTX_IR_POS_S_LEN (16U) +#define UART_CR_UTX_IR_POS_S_POS (0) +#define UART_CR_UTX_IR_POS_S_LEN (16) #define UART_CR_UTX_IR_POS_S_MSK \ - (((1U << UART_CR_UTX_IR_POS_S_LEN) - 1) << UART_CR_UTX_IR_POS_S_POS) + (((1 << UART_CR_UTX_IR_POS_S_LEN) - 1) << UART_CR_UTX_IR_POS_S_POS) #define UART_CR_UTX_IR_POS_S_UMSK \ - (~(((1U << UART_CR_UTX_IR_POS_S_LEN) - 1) << UART_CR_UTX_IR_POS_S_POS)) + (~(((1 << UART_CR_UTX_IR_POS_S_LEN) - 1) << UART_CR_UTX_IR_POS_S_POS)) #define UART_CR_UTX_IR_POS_P UART_CR_UTX_IR_POS_P -#define UART_CR_UTX_IR_POS_P_POS (16U) -#define UART_CR_UTX_IR_POS_P_LEN (16U) +#define UART_CR_UTX_IR_POS_P_POS (16) +#define UART_CR_UTX_IR_POS_P_LEN (16) #define UART_CR_UTX_IR_POS_P_MSK \ - (((1U << UART_CR_UTX_IR_POS_P_LEN) - 1) << UART_CR_UTX_IR_POS_P_POS) + (((1 << UART_CR_UTX_IR_POS_P_LEN) - 1) << UART_CR_UTX_IR_POS_P_POS) #define UART_CR_UTX_IR_POS_P_UMSK \ - (~(((1U << UART_CR_UTX_IR_POS_P_LEN) - 1) << UART_CR_UTX_IR_POS_P_POS)) + (~(((1 << UART_CR_UTX_IR_POS_P_LEN) - 1) << UART_CR_UTX_IR_POS_P_POS)) /* 0x14 : urx_ir_position */ #define UART_URX_IR_POSITION_OFFSET (0x14) #define UART_CR_URX_IR_POS_S UART_CR_URX_IR_POS_S -#define UART_CR_URX_IR_POS_S_POS (0U) -#define UART_CR_URX_IR_POS_S_LEN (16U) +#define UART_CR_URX_IR_POS_S_POS (0) +#define UART_CR_URX_IR_POS_S_LEN (16) #define UART_CR_URX_IR_POS_S_MSK \ - (((1U << UART_CR_URX_IR_POS_S_LEN) - 1) << UART_CR_URX_IR_POS_S_POS) + (((1 << UART_CR_URX_IR_POS_S_LEN) - 1) << UART_CR_URX_IR_POS_S_POS) #define UART_CR_URX_IR_POS_S_UMSK \ - (~(((1U << UART_CR_URX_IR_POS_S_LEN) - 1) << UART_CR_URX_IR_POS_S_POS)) + (~(((1 << UART_CR_URX_IR_POS_S_LEN) - 1) << UART_CR_URX_IR_POS_S_POS)) /* 0x18 : urx_rto_timer */ #define UART_URX_RTO_TIMER_OFFSET (0x18) #define UART_CR_URX_RTO_VALUE UART_CR_URX_RTO_VALUE -#define UART_CR_URX_RTO_VALUE_POS (0U) -#define UART_CR_URX_RTO_VALUE_LEN (8U) +#define UART_CR_URX_RTO_VALUE_POS (0) +#define UART_CR_URX_RTO_VALUE_LEN (8) #define UART_CR_URX_RTO_VALUE_MSK \ - (((1U << UART_CR_URX_RTO_VALUE_LEN) - 1) << UART_CR_URX_RTO_VALUE_POS) + (((1 << UART_CR_URX_RTO_VALUE_LEN) - 1) << UART_CR_URX_RTO_VALUE_POS) #define UART_CR_URX_RTO_VALUE_UMSK \ - (~(((1U << UART_CR_URX_RTO_VALUE_LEN) - 1) << UART_CR_URX_RTO_VALUE_POS)) + (~(((1 << UART_CR_URX_RTO_VALUE_LEN) - 1) << UART_CR_URX_RTO_VALUE_POS)) /* 0x20 : UART interrupt status */ #define UART_INT_STS_OFFSET (0x20) #define UART_UTX_END_INT UART_UTX_END_INT -#define UART_UTX_END_INT_POS (0U) -#define UART_UTX_END_INT_LEN (1U) +#define UART_UTX_END_INT_POS (0) +#define UART_UTX_END_INT_LEN (1) #define UART_UTX_END_INT_MSK \ - (((1U << UART_UTX_END_INT_LEN) - 1) << UART_UTX_END_INT_POS) + (((1 << UART_UTX_END_INT_LEN) - 1) << UART_UTX_END_INT_POS) #define UART_UTX_END_INT_UMSK \ - (~(((1U << UART_UTX_END_INT_LEN) - 1) << UART_UTX_END_INT_POS)) + (~(((1 << UART_UTX_END_INT_LEN) - 1) << UART_UTX_END_INT_POS)) #define UART_URX_END_INT UART_URX_END_INT -#define UART_URX_END_INT_POS (1U) -#define UART_URX_END_INT_LEN (1U) +#define UART_URX_END_INT_POS (1) +#define UART_URX_END_INT_LEN (1) #define UART_URX_END_INT_MSK \ - (((1U << UART_URX_END_INT_LEN) - 1) << UART_URX_END_INT_POS) + (((1 << UART_URX_END_INT_LEN) - 1) << UART_URX_END_INT_POS) #define UART_URX_END_INT_UMSK \ - (~(((1U << UART_URX_END_INT_LEN) - 1) << UART_URX_END_INT_POS)) + (~(((1 << UART_URX_END_INT_LEN) - 1) << UART_URX_END_INT_POS)) #define UART_UTX_FIFO_INT UART_UTX_FIFO_INT -#define UART_UTX_FIFO_INT_POS (2U) -#define UART_UTX_FIFO_INT_LEN (1U) +#define UART_UTX_FIFO_INT_POS (2) +#define UART_UTX_FIFO_INT_LEN (1) #define UART_UTX_FIFO_INT_MSK \ - (((1U << UART_UTX_FIFO_INT_LEN) - 1) << UART_UTX_FIFO_INT_POS) + (((1 << UART_UTX_FIFO_INT_LEN) - 1) << UART_UTX_FIFO_INT_POS) #define UART_UTX_FIFO_INT_UMSK \ - (~(((1U << UART_UTX_FIFO_INT_LEN) - 1) << UART_UTX_FIFO_INT_POS)) + (~(((1 << UART_UTX_FIFO_INT_LEN) - 1) << UART_UTX_FIFO_INT_POS)) #define UART_URX_FIFO_INT UART_URX_FIFO_INT -#define UART_URX_FIFO_INT_POS (3U) -#define UART_URX_FIFO_INT_LEN (1U) +#define UART_URX_FIFO_INT_POS (3) +#define UART_URX_FIFO_INT_LEN (1) #define UART_URX_FIFO_INT_MSK \ - (((1U << UART_URX_FIFO_INT_LEN) - 1) << UART_URX_FIFO_INT_POS) + (((1 << UART_URX_FIFO_INT_LEN) - 1) << UART_URX_FIFO_INT_POS) #define UART_URX_FIFO_INT_UMSK \ - (~(((1U << UART_URX_FIFO_INT_LEN) - 1) << UART_URX_FIFO_INT_POS)) + (~(((1 << UART_URX_FIFO_INT_LEN) - 1) << UART_URX_FIFO_INT_POS)) #define UART_URX_RTO_INT UART_URX_RTO_INT -#define UART_URX_RTO_INT_POS (4U) -#define UART_URX_RTO_INT_LEN (1U) +#define UART_URX_RTO_INT_POS (4) +#define UART_URX_RTO_INT_LEN (1) #define UART_URX_RTO_INT_MSK \ - (((1U << UART_URX_RTO_INT_LEN) - 1) << UART_URX_RTO_INT_POS) + (((1 << UART_URX_RTO_INT_LEN) - 1) << UART_URX_RTO_INT_POS) #define UART_URX_RTO_INT_UMSK \ - (~(((1U << UART_URX_RTO_INT_LEN) - 1) << UART_URX_RTO_INT_POS)) + (~(((1 << UART_URX_RTO_INT_LEN) - 1) << UART_URX_RTO_INT_POS)) #define UART_URX_PCE_INT UART_URX_PCE_INT -#define UART_URX_PCE_INT_POS (5U) -#define UART_URX_PCE_INT_LEN (1U) +#define UART_URX_PCE_INT_POS (5) +#define UART_URX_PCE_INT_LEN (1) #define UART_URX_PCE_INT_MSK \ - (((1U << UART_URX_PCE_INT_LEN) - 1) << UART_URX_PCE_INT_POS) + (((1 << UART_URX_PCE_INT_LEN) - 1) << UART_URX_PCE_INT_POS) #define UART_URX_PCE_INT_UMSK \ - (~(((1U << UART_URX_PCE_INT_LEN) - 1) << UART_URX_PCE_INT_POS)) + (~(((1 << UART_URX_PCE_INT_LEN) - 1) << UART_URX_PCE_INT_POS)) #define UART_UTX_FER_INT UART_UTX_FER_INT -#define UART_UTX_FER_INT_POS (6U) -#define UART_UTX_FER_INT_LEN (1U) +#define UART_UTX_FER_INT_POS (6) +#define UART_UTX_FER_INT_LEN (1) #define UART_UTX_FER_INT_MSK \ - (((1U << UART_UTX_FER_INT_LEN) - 1) << UART_UTX_FER_INT_POS) + (((1 << UART_UTX_FER_INT_LEN) - 1) << UART_UTX_FER_INT_POS) #define UART_UTX_FER_INT_UMSK \ - (~(((1U << UART_UTX_FER_INT_LEN) - 1) << UART_UTX_FER_INT_POS)) + (~(((1 << UART_UTX_FER_INT_LEN) - 1) << UART_UTX_FER_INT_POS)) #define UART_URX_FER_INT UART_URX_FER_INT -#define UART_URX_FER_INT_POS (7U) -#define UART_URX_FER_INT_LEN (1U) +#define UART_URX_FER_INT_POS (7) +#define UART_URX_FER_INT_LEN (1) #define UART_URX_FER_INT_MSK \ - (((1U << UART_URX_FER_INT_LEN) - 1) << UART_URX_FER_INT_POS) + (((1 << UART_URX_FER_INT_LEN) - 1) << UART_URX_FER_INT_POS) #define UART_URX_FER_INT_UMSK \ - (~(((1U << UART_URX_FER_INT_LEN) - 1) << UART_URX_FER_INT_POS)) + (~(((1 << UART_URX_FER_INT_LEN) - 1) << UART_URX_FER_INT_POS)) /* 0x24 : UART interrupt mask */ #define UART_INT_MASK_OFFSET (0x24) #define UART_CR_UTX_END_MASK UART_CR_UTX_END_MASK -#define UART_CR_UTX_END_MASK_POS (0U) -#define UART_CR_UTX_END_MASK_LEN (1U) +#define UART_CR_UTX_END_MASK_POS (0) +#define UART_CR_UTX_END_MASK_LEN (1) #define UART_CR_UTX_END_MASK_MSK \ - (((1U << UART_CR_UTX_END_MASK_LEN) - 1) << UART_CR_UTX_END_MASK_POS) + (((1 << UART_CR_UTX_END_MASK_LEN) - 1) << UART_CR_UTX_END_MASK_POS) #define UART_CR_UTX_END_MASK_UMSK \ - (~(((1U << UART_CR_UTX_END_MASK_LEN) - 1) << UART_CR_UTX_END_MASK_POS)) + (~(((1 << UART_CR_UTX_END_MASK_LEN) - 1) << UART_CR_UTX_END_MASK_POS)) #define UART_CR_URX_END_MASK UART_CR_URX_END_MASK -#define UART_CR_URX_END_MASK_POS (1U) -#define UART_CR_URX_END_MASK_LEN (1U) +#define UART_CR_URX_END_MASK_POS (1) +#define UART_CR_URX_END_MASK_LEN (1) #define UART_CR_URX_END_MASK_MSK \ - (((1U << UART_CR_URX_END_MASK_LEN) - 1) << UART_CR_URX_END_MASK_POS) + (((1 << UART_CR_URX_END_MASK_LEN) - 1) << UART_CR_URX_END_MASK_POS) #define UART_CR_URX_END_MASK_UMSK \ - (~(((1U << UART_CR_URX_END_MASK_LEN) - 1) << UART_CR_URX_END_MASK_POS)) + (~(((1 << UART_CR_URX_END_MASK_LEN) - 1) << UART_CR_URX_END_MASK_POS)) #define UART_CR_UTX_FIFO_MASK UART_CR_UTX_FIFO_MASK -#define UART_CR_UTX_FIFO_MASK_POS (2U) -#define UART_CR_UTX_FIFO_MASK_LEN (1U) +#define UART_CR_UTX_FIFO_MASK_POS (2) +#define UART_CR_UTX_FIFO_MASK_LEN (1) #define UART_CR_UTX_FIFO_MASK_MSK \ - (((1U << UART_CR_UTX_FIFO_MASK_LEN) - 1) << UART_CR_UTX_FIFO_MASK_POS) + (((1 << UART_CR_UTX_FIFO_MASK_LEN) - 1) << UART_CR_UTX_FIFO_MASK_POS) #define UART_CR_UTX_FIFO_MASK_UMSK \ - (~(((1U << UART_CR_UTX_FIFO_MASK_LEN) - 1) << UART_CR_UTX_FIFO_MASK_POS)) + (~(((1 << UART_CR_UTX_FIFO_MASK_LEN) - 1) << UART_CR_UTX_FIFO_MASK_POS)) #define UART_CR_URX_FIFO_MASK UART_CR_URX_FIFO_MASK -#define UART_CR_URX_FIFO_MASK_POS (3U) -#define UART_CR_URX_FIFO_MASK_LEN (1U) +#define UART_CR_URX_FIFO_MASK_POS (3) +#define UART_CR_URX_FIFO_MASK_LEN (1) #define UART_CR_URX_FIFO_MASK_MSK \ - (((1U << UART_CR_URX_FIFO_MASK_LEN) - 1) << UART_CR_URX_FIFO_MASK_POS) + (((1 << UART_CR_URX_FIFO_MASK_LEN) - 1) << UART_CR_URX_FIFO_MASK_POS) #define UART_CR_URX_FIFO_MASK_UMSK \ - (~(((1U << UART_CR_URX_FIFO_MASK_LEN) - 1) << UART_CR_URX_FIFO_MASK_POS)) + (~(((1 << UART_CR_URX_FIFO_MASK_LEN) - 1) << UART_CR_URX_FIFO_MASK_POS)) #define UART_CR_URX_RTO_MASK UART_CR_URX_RTO_MASK -#define UART_CR_URX_RTO_MASK_POS (4U) -#define UART_CR_URX_RTO_MASK_LEN (1U) +#define UART_CR_URX_RTO_MASK_POS (4) +#define UART_CR_URX_RTO_MASK_LEN (1) #define UART_CR_URX_RTO_MASK_MSK \ - (((1U << UART_CR_URX_RTO_MASK_LEN) - 1) << UART_CR_URX_RTO_MASK_POS) + (((1 << UART_CR_URX_RTO_MASK_LEN) - 1) << UART_CR_URX_RTO_MASK_POS) #define UART_CR_URX_RTO_MASK_UMSK \ - (~(((1U << UART_CR_URX_RTO_MASK_LEN) - 1) << UART_CR_URX_RTO_MASK_POS)) + (~(((1 << UART_CR_URX_RTO_MASK_LEN) - 1) << UART_CR_URX_RTO_MASK_POS)) #define UART_CR_URX_PCE_MASK UART_CR_URX_PCE_MASK -#define UART_CR_URX_PCE_MASK_POS (5U) -#define UART_CR_URX_PCE_MASK_LEN (1U) +#define UART_CR_URX_PCE_MASK_POS (5) +#define UART_CR_URX_PCE_MASK_LEN (1) #define UART_CR_URX_PCE_MASK_MSK \ - (((1U << UART_CR_URX_PCE_MASK_LEN) - 1) << UART_CR_URX_PCE_MASK_POS) + (((1 << UART_CR_URX_PCE_MASK_LEN) - 1) << UART_CR_URX_PCE_MASK_POS) #define UART_CR_URX_PCE_MASK_UMSK \ - (~(((1U << UART_CR_URX_PCE_MASK_LEN) - 1) << UART_CR_URX_PCE_MASK_POS)) + (~(((1 << UART_CR_URX_PCE_MASK_LEN) - 1) << UART_CR_URX_PCE_MASK_POS)) #define UART_CR_UTX_FER_MASK UART_CR_UTX_FER_MASK -#define UART_CR_UTX_FER_MASK_POS (6U) -#define UART_CR_UTX_FER_MASK_LEN (1U) +#define UART_CR_UTX_FER_MASK_POS (6) +#define UART_CR_UTX_FER_MASK_LEN (1) #define UART_CR_UTX_FER_MASK_MSK \ - (((1U << UART_CR_UTX_FER_MASK_LEN) - 1) << UART_CR_UTX_FER_MASK_POS) + (((1 << UART_CR_UTX_FER_MASK_LEN) - 1) << UART_CR_UTX_FER_MASK_POS) #define UART_CR_UTX_FER_MASK_UMSK \ - (~(((1U << UART_CR_UTX_FER_MASK_LEN) - 1) << UART_CR_UTX_FER_MASK_POS)) + (~(((1 << UART_CR_UTX_FER_MASK_LEN) - 1) << UART_CR_UTX_FER_MASK_POS)) #define UART_CR_URX_FER_MASK UART_CR_URX_FER_MASK -#define UART_CR_URX_FER_MASK_POS (7U) -#define UART_CR_URX_FER_MASK_LEN (1U) +#define UART_CR_URX_FER_MASK_POS (7) +#define UART_CR_URX_FER_MASK_LEN (1) #define UART_CR_URX_FER_MASK_MSK \ - (((1U << UART_CR_URX_FER_MASK_LEN) - 1) << UART_CR_URX_FER_MASK_POS) + (((1 << UART_CR_URX_FER_MASK_LEN) - 1) << UART_CR_URX_FER_MASK_POS) #define UART_CR_URX_FER_MASK_UMSK \ - (~(((1U << UART_CR_URX_FER_MASK_LEN) - 1) << UART_CR_URX_FER_MASK_POS)) + (~(((1 << UART_CR_URX_FER_MASK_LEN) - 1) << UART_CR_URX_FER_MASK_POS)) /* 0x28 : UART interrupt clear */ #define UART_INT_CLEAR_OFFSET (0x28) #define UART_CR_UTX_END_CLR UART_CR_UTX_END_CLR -#define UART_CR_UTX_END_CLR_POS (0U) -#define UART_CR_UTX_END_CLR_LEN (1U) +#define UART_CR_UTX_END_CLR_POS (0) +#define UART_CR_UTX_END_CLR_LEN (1) #define UART_CR_UTX_END_CLR_MSK \ - (((1U << UART_CR_UTX_END_CLR_LEN) - 1) << UART_CR_UTX_END_CLR_POS) + (((1 << UART_CR_UTX_END_CLR_LEN) - 1) << UART_CR_UTX_END_CLR_POS) #define UART_CR_UTX_END_CLR_UMSK \ - (~(((1U << UART_CR_UTX_END_CLR_LEN) - 1) << UART_CR_UTX_END_CLR_POS)) + (~(((1 << UART_CR_UTX_END_CLR_LEN) - 1) << UART_CR_UTX_END_CLR_POS)) #define UART_CR_URX_END_CLR UART_CR_URX_END_CLR -#define UART_CR_URX_END_CLR_POS (1U) -#define UART_CR_URX_END_CLR_LEN (1U) +#define UART_CR_URX_END_CLR_POS (1) +#define UART_CR_URX_END_CLR_LEN (1) #define UART_CR_URX_END_CLR_MSK \ - (((1U << UART_CR_URX_END_CLR_LEN) - 1) << UART_CR_URX_END_CLR_POS) + (((1 << UART_CR_URX_END_CLR_LEN) - 1) << UART_CR_URX_END_CLR_POS) #define UART_CR_URX_END_CLR_UMSK \ - (~(((1U << UART_CR_URX_END_CLR_LEN) - 1) << UART_CR_URX_END_CLR_POS)) + (~(((1 << UART_CR_URX_END_CLR_LEN) - 1) << UART_CR_URX_END_CLR_POS)) #define UART_CR_URX_RTO_CLR UART_CR_URX_RTO_CLR -#define UART_CR_URX_RTO_CLR_POS (4U) -#define UART_CR_URX_RTO_CLR_LEN (1U) +#define UART_CR_URX_RTO_CLR_POS (4) +#define UART_CR_URX_RTO_CLR_LEN (1) #define UART_CR_URX_RTO_CLR_MSK \ - (((1U << UART_CR_URX_RTO_CLR_LEN) - 1) << UART_CR_URX_RTO_CLR_POS) + (((1 << UART_CR_URX_RTO_CLR_LEN) - 1) << UART_CR_URX_RTO_CLR_POS) #define UART_CR_URX_RTO_CLR_UMSK \ - (~(((1U << UART_CR_URX_RTO_CLR_LEN) - 1) << UART_CR_URX_RTO_CLR_POS)) + (~(((1 << UART_CR_URX_RTO_CLR_LEN) - 1) << UART_CR_URX_RTO_CLR_POS)) #define UART_CR_URX_PCE_CLR UART_CR_URX_PCE_CLR -#define UART_CR_URX_PCE_CLR_POS (5U) -#define UART_CR_URX_PCE_CLR_LEN (1U) +#define UART_CR_URX_PCE_CLR_POS (5) +#define UART_CR_URX_PCE_CLR_LEN (1) #define UART_CR_URX_PCE_CLR_MSK \ - (((1U << UART_CR_URX_PCE_CLR_LEN) - 1) << UART_CR_URX_PCE_CLR_POS) + (((1 << UART_CR_URX_PCE_CLR_LEN) - 1) << UART_CR_URX_PCE_CLR_POS) #define UART_CR_URX_PCE_CLR_UMSK \ - (~(((1U << UART_CR_URX_PCE_CLR_LEN) - 1) << UART_CR_URX_PCE_CLR_POS)) + (~(((1 << UART_CR_URX_PCE_CLR_LEN) - 1) << UART_CR_URX_PCE_CLR_POS)) /* 0x2C : UART interrupt enable */ #define UART_INT_EN_OFFSET (0x2C) #define UART_CR_UTX_END_EN UART_CR_UTX_END_EN -#define UART_CR_UTX_END_EN_POS (0U) -#define UART_CR_UTX_END_EN_LEN (1U) +#define UART_CR_UTX_END_EN_POS (0) +#define UART_CR_UTX_END_EN_LEN (1) #define UART_CR_UTX_END_EN_MSK \ - (((1U << UART_CR_UTX_END_EN_LEN) - 1) << UART_CR_UTX_END_EN_POS) + (((1 << UART_CR_UTX_END_EN_LEN) - 1) << UART_CR_UTX_END_EN_POS) #define UART_CR_UTX_END_EN_UMSK \ - (~(((1U << UART_CR_UTX_END_EN_LEN) - 1) << UART_CR_UTX_END_EN_POS)) + (~(((1 << UART_CR_UTX_END_EN_LEN) - 1) << UART_CR_UTX_END_EN_POS)) #define UART_CR_URX_END_EN UART_CR_URX_END_EN -#define UART_CR_URX_END_EN_POS (1U) -#define UART_CR_URX_END_EN_LEN (1U) +#define UART_CR_URX_END_EN_POS (1) +#define UART_CR_URX_END_EN_LEN (1) #define UART_CR_URX_END_EN_MSK \ - (((1U << UART_CR_URX_END_EN_LEN) - 1) << UART_CR_URX_END_EN_POS) + (((1 << UART_CR_URX_END_EN_LEN) - 1) << UART_CR_URX_END_EN_POS) #define UART_CR_URX_END_EN_UMSK \ - (~(((1U << UART_CR_URX_END_EN_LEN) - 1) << UART_CR_URX_END_EN_POS)) + (~(((1 << UART_CR_URX_END_EN_LEN) - 1) << UART_CR_URX_END_EN_POS)) #define UART_CR_UTX_FIFO_EN UART_CR_UTX_FIFO_EN -#define UART_CR_UTX_FIFO_EN_POS (2U) -#define UART_CR_UTX_FIFO_EN_LEN (1U) +#define UART_CR_UTX_FIFO_EN_POS (2) +#define UART_CR_UTX_FIFO_EN_LEN (1) #define UART_CR_UTX_FIFO_EN_MSK \ - (((1U << UART_CR_UTX_FIFO_EN_LEN) - 1) << UART_CR_UTX_FIFO_EN_POS) + (((1 << UART_CR_UTX_FIFO_EN_LEN) - 1) << UART_CR_UTX_FIFO_EN_POS) #define UART_CR_UTX_FIFO_EN_UMSK \ - (~(((1U << UART_CR_UTX_FIFO_EN_LEN) - 1) << UART_CR_UTX_FIFO_EN_POS)) + (~(((1 << UART_CR_UTX_FIFO_EN_LEN) - 1) << UART_CR_UTX_FIFO_EN_POS)) #define UART_CR_URX_FIFO_EN UART_CR_URX_FIFO_EN -#define UART_CR_URX_FIFO_EN_POS (3U) -#define UART_CR_URX_FIFO_EN_LEN (1U) +#define UART_CR_URX_FIFO_EN_POS (3) +#define UART_CR_URX_FIFO_EN_LEN (1) #define UART_CR_URX_FIFO_EN_MSK \ - (((1U << UART_CR_URX_FIFO_EN_LEN) - 1) << UART_CR_URX_FIFO_EN_POS) + (((1 << UART_CR_URX_FIFO_EN_LEN) - 1) << UART_CR_URX_FIFO_EN_POS) #define UART_CR_URX_FIFO_EN_UMSK \ - (~(((1U << UART_CR_URX_FIFO_EN_LEN) - 1) << UART_CR_URX_FIFO_EN_POS)) + (~(((1 << UART_CR_URX_FIFO_EN_LEN) - 1) << UART_CR_URX_FIFO_EN_POS)) #define UART_CR_URX_RTO_EN UART_CR_URX_RTO_EN -#define UART_CR_URX_RTO_EN_POS (4U) -#define UART_CR_URX_RTO_EN_LEN (1U) +#define UART_CR_URX_RTO_EN_POS (4) +#define UART_CR_URX_RTO_EN_LEN (1) #define UART_CR_URX_RTO_EN_MSK \ - (((1U << UART_CR_URX_RTO_EN_LEN) - 1) << UART_CR_URX_RTO_EN_POS) + (((1 << UART_CR_URX_RTO_EN_LEN) - 1) << UART_CR_URX_RTO_EN_POS) #define UART_CR_URX_RTO_EN_UMSK \ - (~(((1U << UART_CR_URX_RTO_EN_LEN) - 1) << UART_CR_URX_RTO_EN_POS)) + (~(((1 << UART_CR_URX_RTO_EN_LEN) - 1) << UART_CR_URX_RTO_EN_POS)) #define UART_CR_URX_PCE_EN UART_CR_URX_PCE_EN -#define UART_CR_URX_PCE_EN_POS (5U) -#define UART_CR_URX_PCE_EN_LEN (1U) +#define UART_CR_URX_PCE_EN_POS (5) +#define UART_CR_URX_PCE_EN_LEN (1) #define UART_CR_URX_PCE_EN_MSK \ - (((1U << UART_CR_URX_PCE_EN_LEN) - 1) << UART_CR_URX_PCE_EN_POS) + (((1 << UART_CR_URX_PCE_EN_LEN) - 1) << UART_CR_URX_PCE_EN_POS) #define UART_CR_URX_PCE_EN_UMSK \ - (~(((1U << UART_CR_URX_PCE_EN_LEN) - 1) << UART_CR_URX_PCE_EN_POS)) + (~(((1 << UART_CR_URX_PCE_EN_LEN) - 1) << UART_CR_URX_PCE_EN_POS)) #define UART_CR_UTX_FER_EN UART_CR_UTX_FER_EN -#define UART_CR_UTX_FER_EN_POS (6U) -#define UART_CR_UTX_FER_EN_LEN (1U) +#define UART_CR_UTX_FER_EN_POS (6) +#define UART_CR_UTX_FER_EN_LEN (1) #define UART_CR_UTX_FER_EN_MSK \ - (((1U << UART_CR_UTX_FER_EN_LEN) - 1) << UART_CR_UTX_FER_EN_POS) + (((1 << UART_CR_UTX_FER_EN_LEN) - 1) << UART_CR_UTX_FER_EN_POS) #define UART_CR_UTX_FER_EN_UMSK \ - (~(((1U << UART_CR_UTX_FER_EN_LEN) - 1) << UART_CR_UTX_FER_EN_POS)) + (~(((1 << UART_CR_UTX_FER_EN_LEN) - 1) << UART_CR_UTX_FER_EN_POS)) #define UART_CR_URX_FER_EN UART_CR_URX_FER_EN -#define UART_CR_URX_FER_EN_POS (7U) -#define UART_CR_URX_FER_EN_LEN (1U) +#define UART_CR_URX_FER_EN_POS (7) +#define UART_CR_URX_FER_EN_LEN (1) #define UART_CR_URX_FER_EN_MSK \ - (((1U << UART_CR_URX_FER_EN_LEN) - 1) << UART_CR_URX_FER_EN_POS) + (((1 << UART_CR_URX_FER_EN_LEN) - 1) << UART_CR_URX_FER_EN_POS) #define UART_CR_URX_FER_EN_UMSK \ - (~(((1U << UART_CR_URX_FER_EN_LEN) - 1) << UART_CR_URX_FER_EN_POS)) + (~(((1 << UART_CR_URX_FER_EN_LEN) - 1) << UART_CR_URX_FER_EN_POS)) /* 0x30 : uart_status */ #define UART_STATUS_OFFSET (0x30) #define UART_STS_UTX_BUS_BUSY UART_STS_UTX_BUS_BUSY -#define UART_STS_UTX_BUS_BUSY_POS (0U) -#define UART_STS_UTX_BUS_BUSY_LEN (1U) +#define UART_STS_UTX_BUS_BUSY_POS (0) +#define UART_STS_UTX_BUS_BUSY_LEN (1) #define UART_STS_UTX_BUS_BUSY_MSK \ - (((1U << UART_STS_UTX_BUS_BUSY_LEN) - 1) << UART_STS_UTX_BUS_BUSY_POS) + (((1 << UART_STS_UTX_BUS_BUSY_LEN) - 1) << UART_STS_UTX_BUS_BUSY_POS) #define UART_STS_UTX_BUS_BUSY_UMSK \ - (~(((1U << UART_STS_UTX_BUS_BUSY_LEN) - 1) << UART_STS_UTX_BUS_BUSY_POS)) + (~(((1 << UART_STS_UTX_BUS_BUSY_LEN) - 1) << UART_STS_UTX_BUS_BUSY_POS)) #define UART_STS_URX_BUS_BUSY UART_STS_URX_BUS_BUSY -#define UART_STS_URX_BUS_BUSY_POS (1U) -#define UART_STS_URX_BUS_BUSY_LEN (1U) +#define UART_STS_URX_BUS_BUSY_POS (1) +#define UART_STS_URX_BUS_BUSY_LEN (1) #define UART_STS_URX_BUS_BUSY_MSK \ - (((1U << UART_STS_URX_BUS_BUSY_LEN) - 1) << UART_STS_URX_BUS_BUSY_POS) + (((1 << UART_STS_URX_BUS_BUSY_LEN) - 1) << UART_STS_URX_BUS_BUSY_POS) #define UART_STS_URX_BUS_BUSY_UMSK \ - (~(((1U << UART_STS_URX_BUS_BUSY_LEN) - 1) << UART_STS_URX_BUS_BUSY_POS)) + (~(((1 << UART_STS_URX_BUS_BUSY_LEN) - 1) << UART_STS_URX_BUS_BUSY_POS)) /* 0x34 : sts_urx_abr_prd */ #define UART_STS_URX_ABR_PRD_OFFSET (0x34) #define UART_STS_URX_ABR_PRD_START UART_STS_URX_ABR_PRD_START -#define UART_STS_URX_ABR_PRD_START_POS (0U) -#define UART_STS_URX_ABR_PRD_START_LEN (16U) +#define UART_STS_URX_ABR_PRD_START_POS (0) +#define UART_STS_URX_ABR_PRD_START_LEN (16) #define UART_STS_URX_ABR_PRD_START_MSK \ - (((1U << UART_STS_URX_ABR_PRD_START_LEN) - 1) \ + (((1 << UART_STS_URX_ABR_PRD_START_LEN) - 1) \ << UART_STS_URX_ABR_PRD_START_POS) #define UART_STS_URX_ABR_PRD_START_UMSK \ - (~(((1U << UART_STS_URX_ABR_PRD_START_LEN) - 1) \ + (~(((1 << UART_STS_URX_ABR_PRD_START_LEN) - 1) \ << UART_STS_URX_ABR_PRD_START_POS)) #define UART_STS_URX_ABR_PRD_0X55 UART_STS_URX_ABR_PRD_0X55 -#define UART_STS_URX_ABR_PRD_0X55_POS (16U) -#define UART_STS_URX_ABR_PRD_0X55_LEN (16U) +#define UART_STS_URX_ABR_PRD_0X55_POS (16) +#define UART_STS_URX_ABR_PRD_0X55_LEN (16) #define UART_STS_URX_ABR_PRD_0X55_MSK \ - (((1U << UART_STS_URX_ABR_PRD_0X55_LEN) - 1) \ + (((1 << UART_STS_URX_ABR_PRD_0X55_LEN) - 1) \ << UART_STS_URX_ABR_PRD_0X55_POS) #define UART_STS_URX_ABR_PRD_0X55_UMSK \ - (~(((1U << UART_STS_URX_ABR_PRD_0X55_LEN) - 1) \ + (~(((1 << UART_STS_URX_ABR_PRD_0X55_LEN) - 1) \ << UART_STS_URX_ABR_PRD_0X55_POS)) /* 0x80 : uart_fifo_config_0 */ #define UART_FIFO_CONFIG_0_OFFSET (0x80) #define UART_DMA_TX_EN UART_DMA_TX_EN -#define UART_DMA_TX_EN_POS (0U) -#define UART_DMA_TX_EN_LEN (1U) +#define UART_DMA_TX_EN_POS (0) +#define UART_DMA_TX_EN_LEN (1) #define UART_DMA_TX_EN_MSK \ - (((1U << UART_DMA_TX_EN_LEN) - 1) << UART_DMA_TX_EN_POS) + (((1 << UART_DMA_TX_EN_LEN) - 1) << UART_DMA_TX_EN_POS) #define UART_DMA_TX_EN_UMSK \ - (~(((1U << UART_DMA_TX_EN_LEN) - 1) << UART_DMA_TX_EN_POS)) + (~(((1 << UART_DMA_TX_EN_LEN) - 1) << UART_DMA_TX_EN_POS)) #define UART_DMA_RX_EN UART_DMA_RX_EN -#define UART_DMA_RX_EN_POS (1U) -#define UART_DMA_RX_EN_LEN (1U) +#define UART_DMA_RX_EN_POS (1) +#define UART_DMA_RX_EN_LEN (1) #define UART_DMA_RX_EN_MSK \ - (((1U << UART_DMA_RX_EN_LEN) - 1) << UART_DMA_RX_EN_POS) + (((1 << UART_DMA_RX_EN_LEN) - 1) << UART_DMA_RX_EN_POS) #define UART_DMA_RX_EN_UMSK \ - (~(((1U << UART_DMA_RX_EN_LEN) - 1) << UART_DMA_RX_EN_POS)) + (~(((1 << UART_DMA_RX_EN_LEN) - 1) << UART_DMA_RX_EN_POS)) #define UART_TX_FIFO_CLR UART_TX_FIFO_CLR -#define UART_TX_FIFO_CLR_POS (2U) -#define UART_TX_FIFO_CLR_LEN (1U) +#define UART_TX_FIFO_CLR_POS (2) +#define UART_TX_FIFO_CLR_LEN (1) #define UART_TX_FIFO_CLR_MSK \ - (((1U << UART_TX_FIFO_CLR_LEN) - 1) << UART_TX_FIFO_CLR_POS) + (((1 << UART_TX_FIFO_CLR_LEN) - 1) << UART_TX_FIFO_CLR_POS) #define UART_TX_FIFO_CLR_UMSK \ - (~(((1U << UART_TX_FIFO_CLR_LEN) - 1) << UART_TX_FIFO_CLR_POS)) + (~(((1 << UART_TX_FIFO_CLR_LEN) - 1) << UART_TX_FIFO_CLR_POS)) #define UART_RX_FIFO_CLR UART_RX_FIFO_CLR -#define UART_RX_FIFO_CLR_POS (3U) -#define UART_RX_FIFO_CLR_LEN (1U) +#define UART_RX_FIFO_CLR_POS (3) +#define UART_RX_FIFO_CLR_LEN (1) #define UART_RX_FIFO_CLR_MSK \ - (((1U << UART_RX_FIFO_CLR_LEN) - 1) << UART_RX_FIFO_CLR_POS) + (((1 << UART_RX_FIFO_CLR_LEN) - 1) << UART_RX_FIFO_CLR_POS) #define UART_RX_FIFO_CLR_UMSK \ - (~(((1U << UART_RX_FIFO_CLR_LEN) - 1) << UART_RX_FIFO_CLR_POS)) + (~(((1 << UART_RX_FIFO_CLR_LEN) - 1) << UART_RX_FIFO_CLR_POS)) #define UART_TX_FIFO_OVERFLOW UART_TX_FIFO_OVERFLOW -#define UART_TX_FIFO_OVERFLOW_POS (4U) -#define UART_TX_FIFO_OVERFLOW_LEN (1U) +#define UART_TX_FIFO_OVERFLOW_POS (4) +#define UART_TX_FIFO_OVERFLOW_LEN (1) #define UART_TX_FIFO_OVERFLOW_MSK \ - (((1U << UART_TX_FIFO_OVERFLOW_LEN) - 1) << UART_TX_FIFO_OVERFLOW_POS) + (((1 << UART_TX_FIFO_OVERFLOW_LEN) - 1) << UART_TX_FIFO_OVERFLOW_POS) #define UART_TX_FIFO_OVERFLOW_UMSK \ - (~(((1U << UART_TX_FIFO_OVERFLOW_LEN) - 1) << UART_TX_FIFO_OVERFLOW_POS)) + (~(((1 << UART_TX_FIFO_OVERFLOW_LEN) - 1) << UART_TX_FIFO_OVERFLOW_POS)) #define UART_TX_FIFO_UNDERFLOW UART_TX_FIFO_UNDERFLOW -#define UART_TX_FIFO_UNDERFLOW_POS (5U) -#define UART_TX_FIFO_UNDERFLOW_LEN (1U) +#define UART_TX_FIFO_UNDERFLOW_POS (5) +#define UART_TX_FIFO_UNDERFLOW_LEN (1) #define UART_TX_FIFO_UNDERFLOW_MSK \ - (((1U << UART_TX_FIFO_UNDERFLOW_LEN) - 1) << UART_TX_FIFO_UNDERFLOW_POS) + (((1 << UART_TX_FIFO_UNDERFLOW_LEN) - 1) << UART_TX_FIFO_UNDERFLOW_POS) #define UART_TX_FIFO_UNDERFLOW_UMSK \ - (~(((1U << UART_TX_FIFO_UNDERFLOW_LEN) - 1) << UART_TX_FIFO_UNDERFLOW_POS)) + (~(((1 << UART_TX_FIFO_UNDERFLOW_LEN) - 1) << UART_TX_FIFO_UNDERFLOW_POS)) #define UART_RX_FIFO_OVERFLOW UART_RX_FIFO_OVERFLOW -#define UART_RX_FIFO_OVERFLOW_POS (6U) -#define UART_RX_FIFO_OVERFLOW_LEN (1U) +#define UART_RX_FIFO_OVERFLOW_POS (6) +#define UART_RX_FIFO_OVERFLOW_LEN (1) #define UART_RX_FIFO_OVERFLOW_MSK \ - (((1U << UART_RX_FIFO_OVERFLOW_LEN) - 1) << UART_RX_FIFO_OVERFLOW_POS) + (((1 << UART_RX_FIFO_OVERFLOW_LEN) - 1) << UART_RX_FIFO_OVERFLOW_POS) #define UART_RX_FIFO_OVERFLOW_UMSK \ - (~(((1U << UART_RX_FIFO_OVERFLOW_LEN) - 1) << UART_RX_FIFO_OVERFLOW_POS)) + (~(((1 << UART_RX_FIFO_OVERFLOW_LEN) - 1) << UART_RX_FIFO_OVERFLOW_POS)) #define UART_RX_FIFO_UNDERFLOW UART_RX_FIFO_UNDERFLOW -#define UART_RX_FIFO_UNDERFLOW_POS (7U) -#define UART_RX_FIFO_UNDERFLOW_LEN (1U) +#define UART_RX_FIFO_UNDERFLOW_POS (7) +#define UART_RX_FIFO_UNDERFLOW_LEN (1) #define UART_RX_FIFO_UNDERFLOW_MSK \ - (((1U << UART_RX_FIFO_UNDERFLOW_LEN) - 1) << UART_RX_FIFO_UNDERFLOW_POS) + (((1 << UART_RX_FIFO_UNDERFLOW_LEN) - 1) << UART_RX_FIFO_UNDERFLOW_POS) #define UART_RX_FIFO_UNDERFLOW_UMSK \ - (~(((1U << UART_RX_FIFO_UNDERFLOW_LEN) - 1) << UART_RX_FIFO_UNDERFLOW_POS)) + (~(((1 << UART_RX_FIFO_UNDERFLOW_LEN) - 1) << UART_RX_FIFO_UNDERFLOW_POS)) /* 0x84 : uart_fifo_config_1 */ #define UART_FIFO_CONFIG_1_OFFSET (0x84) #define UART_TX_FIFO_CNT UART_TX_FIFO_CNT -#define UART_TX_FIFO_CNT_POS (0U) -#define UART_TX_FIFO_CNT_LEN (6U) +#define UART_TX_FIFO_CNT_POS (0) +#define UART_TX_FIFO_CNT_LEN (6) #define UART_TX_FIFO_CNT_MSK \ - (((1U << UART_TX_FIFO_CNT_LEN) - 1) << UART_TX_FIFO_CNT_POS) + (((1 << UART_TX_FIFO_CNT_LEN) - 1) << UART_TX_FIFO_CNT_POS) #define UART_TX_FIFO_CNT_UMSK \ - (~(((1U << UART_TX_FIFO_CNT_LEN) - 1) << UART_TX_FIFO_CNT_POS)) + (~(((1 << UART_TX_FIFO_CNT_LEN) - 1) << UART_TX_FIFO_CNT_POS)) #define UART_RX_FIFO_CNT UART_RX_FIFO_CNT -#define UART_RX_FIFO_CNT_POS (8U) -#define UART_RX_FIFO_CNT_LEN (6U) +#define UART_RX_FIFO_CNT_POS (8) +#define UART_RX_FIFO_CNT_LEN (6) #define UART_RX_FIFO_CNT_MSK \ - (((1U << UART_RX_FIFO_CNT_LEN) - 1) << UART_RX_FIFO_CNT_POS) + (((1 << UART_RX_FIFO_CNT_LEN) - 1) << UART_RX_FIFO_CNT_POS) #define UART_RX_FIFO_CNT_UMSK \ - (~(((1U << UART_RX_FIFO_CNT_LEN) - 1) << UART_RX_FIFO_CNT_POS)) + (~(((1 << UART_RX_FIFO_CNT_LEN) - 1) << UART_RX_FIFO_CNT_POS)) #define UART_TX_FIFO_TH UART_TX_FIFO_TH -#define UART_TX_FIFO_TH_POS (16U) -#define UART_TX_FIFO_TH_LEN (5U) +#define UART_TX_FIFO_TH_POS (16) +#define UART_TX_FIFO_TH_LEN (5) #define UART_TX_FIFO_TH_MSK \ - (((1U << UART_TX_FIFO_TH_LEN) - 1) << UART_TX_FIFO_TH_POS) + (((1 << UART_TX_FIFO_TH_LEN) - 1) << UART_TX_FIFO_TH_POS) #define UART_TX_FIFO_TH_UMSK \ - (~(((1U << UART_TX_FIFO_TH_LEN) - 1) << UART_TX_FIFO_TH_POS)) + (~(((1 << UART_TX_FIFO_TH_LEN) - 1) << UART_TX_FIFO_TH_POS)) #define UART_RX_FIFO_TH UART_RX_FIFO_TH -#define UART_RX_FIFO_TH_POS (24U) -#define UART_RX_FIFO_TH_LEN (5U) +#define UART_RX_FIFO_TH_POS (24) +#define UART_RX_FIFO_TH_LEN (5) #define UART_RX_FIFO_TH_MSK \ - (((1U << UART_RX_FIFO_TH_LEN) - 1) << UART_RX_FIFO_TH_POS) + (((1 << UART_RX_FIFO_TH_LEN) - 1) << UART_RX_FIFO_TH_POS) #define UART_RX_FIFO_TH_UMSK \ - (~(((1U << UART_RX_FIFO_TH_LEN) - 1) << UART_RX_FIFO_TH_POS)) + (~(((1 << UART_RX_FIFO_TH_LEN) - 1) << UART_RX_FIFO_TH_POS)) /* 0x88 : uart_fifo_wdata */ #define UART_FIFO_WDATA_OFFSET (0x88) #define UART_FIFO_WDATA UART_FIFO_WDATA -#define UART_FIFO_WDATA_POS (0U) -#define UART_FIFO_WDATA_LEN (8U) +#define UART_FIFO_WDATA_POS (0) +#define UART_FIFO_WDATA_LEN (8) #define UART_FIFO_WDATA_MSK \ - (((1U << UART_FIFO_WDATA_LEN) - 1) << UART_FIFO_WDATA_POS) + (((1 << UART_FIFO_WDATA_LEN) - 1) << UART_FIFO_WDATA_POS) #define UART_FIFO_WDATA_UMSK \ - (~(((1U << UART_FIFO_WDATA_LEN) - 1) << UART_FIFO_WDATA_POS)) + (~(((1 << UART_FIFO_WDATA_LEN) - 1) << UART_FIFO_WDATA_POS)) /* 0x8C : uart_fifo_rdata */ #define UART_FIFO_RDATA_OFFSET (0x8C) #define UART_FIFO_RDATA UART_FIFO_RDATA -#define UART_FIFO_RDATA_POS (0U) -#define UART_FIFO_RDATA_LEN (8U) +#define UART_FIFO_RDATA_POS (0) +#define UART_FIFO_RDATA_LEN (8) #define UART_FIFO_RDATA_MSK \ - (((1U << UART_FIFO_RDATA_LEN) - 1) << UART_FIFO_RDATA_POS) + (((1 << UART_FIFO_RDATA_LEN) - 1) << UART_FIFO_RDATA_POS) #define UART_FIFO_RDATA_UMSK \ - (~(((1U << UART_FIFO_RDATA_LEN) - 1) << UART_FIFO_RDATA_POS)) + (~(((1 << UART_FIFO_RDATA_LEN) - 1) << UART_FIFO_RDATA_POS)) + +/* UART port type definition */ + +#define UART0_ID 0 /* UART0 port define */ +#define UART1_ID 1 /* UART1 port define */ +#define UART_ID_MAX 2 /* UART MAX ID define */ + +/* UART parity type definition */ + +#define UART_PARITY_NONE 0 /* UART parity none define */ +#define UART_PARITY_ODD 1 /* UART parity odd define */ +#define UART_PARITY_EVEN 2 /* UART parity even define */ + +/* UART data bits type definiton */ + +#define UART_DATABITS_5 0 /* UART data bits length:5 bits */ +#define UART_DATABITS_6 1 /* UART data bits length:6 bits */ +#define UART_DATABITS_7 2 /* UART data bits length:7 bits */ +#define UART_DATABITS_8 3 /* UART data bits length:8 bits */ + +/* UART stop bits type definiton */ + +#define UART_STOPBITS_1 0 /* UART data stop bits length:1 bits */ +#define UART_STOPBITS_1_5 1 /* UART data stop bits length:1.5 bits */ +#define UART_STOPBITS_2 2 /* UART data stop bits length:2 bits */ + +/* UART each data byte is send out LSB-first or MSB-first type definiton */ + +#define UART_LSB_FIRST 0 /* UART each byte is send out LSB-first */ +#define UART_MSB_FIRST 1 /* UART each byte is send out MSB-first */ + +/* UART auto baudrate detection using codeword 0x55 */ + +#define UART_AUTOBAUD_0X55 0 + +/* UART auto baudrate detection using start bit */ + +#define UART_AUTOBAUD_STARTBIT 1 + +/* UART interrupt type definition */ + +#define UART_INT_TX_END 0 /* UART tx transfer end interrupt */ +#define UART_INT_RX_END 1 /* UART rx transfer end interrupt */ +#define UART_INT_TX_FIFO_REQ \ + 2 /* UART tx fifo interrupt when tx fifo count \ + * reaches,auto clear */ +#define UART_INT_RX_FIFO_REQ \ + 3 /* UART rx fifo interrupt when rx fifo count \ + * reaches,auto clear */ +#define UART_INT_RTO 4 /* UART rx time-out interrupt */ +#define UART_INT_PCE 5 /* UART rx parity check error interrupt */ +#define UART_INT_TX_FER \ + 6 /* UART tx fifo overflow/underflow error interrupt */ +#define UART_INT_RX_FER \ + 7 /* UART rx fifo overflow/underflow error interrupt */ +#define UART_INT_ALL 8 /* All the interrupt */ + +/* UART overflow or underflow type definition */ + +#define UART_TX_OVERFLOW 0 /* UART tx fifo overflow */ +#define UART_TX_UNDERFLOW 1 /* UART tx fifo underflow */ +#define UART_RX_OVERFLOW 2 /* UART rx fifo overflow */ +#define UART_RX_UNDERFLOW 3 /* UART rx fifo underflow */ /**************************************************************************** * Public Types @@ -635,381 +700,5 @@ #ifndef __ASSEMBLY__ -/* UART port type definition */ - -enum uart_id_e -{ - UART0_ID, /* UART0 port define */ - UART1_ID, /* UART1 port define */ - UART_ID_MAX /* UART MAX ID define */ -}; - -/* UART direction type definition */ - -enum uart_direction_e -{ - UART_TX, /* UART TX Direction */ - UART_RX, /* UART RX Direction */ - UART_TXRX /* UART TX and RX Direction */ -}; - -/* UART parity type definition */ - -enum uart_parity_e -{ - UART_PARITY_NONE, /* UART parity none define */ - UART_PARITY_ODD, /* UART parity odd define */ - UART_PARITY_EVEN /* UART parity even define */ -}; - -/* UART data bits type definiton */ - -enum uart_databits_e -{ - UART_DATABITS_5, /* UART data bits length:5 bits */ - UART_DATABITS_6, /* UART data bits length:6 bits */ - UART_DATABITS_7, /* UART data bits length:7 bits */ - UART_DATABITS_8 /* UART data bits length:8 bits */ -}; - -/* UART stop bits type definiton */ - -enum uart_stopbits_e -{ - UART_STOPBITS_1, /* UART data stop bits length:1 bits */ - UART_STOPBITS_1_5, /* UART data stop bits length:1.5 bits */ - UART_STOPBITS_2 /* UART data stop bits length:2 bits */ -}; - -/* UART each data byte is send out LSB-first or MSB-first type definiton */ - -enum uart_bytebits_inverse_e -{ - UART_LSB_FIRST, /* UART each byte is send out LSB-first */ - UART_MSB_FIRST /* UART each byte is send out MSB-first */ -}; - -/* UART auto baudrate detection using codeword 0x55 or start bit definiton */ - -enum uart_auto_baudrate_detection_e -{ - /* UART auto baudrate detection using codeword 0x55 */ - - UART_AUTOBAUD_0X55, - - /* UART auto baudrate detection using start bit */ - - UART_AUTOBAUD_STARTBIT -}; - -/* UART interrupt type definition */ - -enum uart_int_type_e -{ - UART_INT_TX_END, /* UART tx transfer end interrupt */ - UART_INT_RX_END, /* UART rx transfer end interrupt */ - UART_INT_TX_FIFO_REQ, /* UART tx fifo interrupt when tx fifo count - * reaches,auto clear */ - UART_INT_RX_FIFO_REQ, /* UART rx fifo interrupt when rx fifo count - * reaches,auto clear */ - UART_INT_RTO, /* UART rx time-out interrupt */ - UART_INT_PCE, /* UART rx parity check error interrupt */ - UART_INT_TX_FER, /* UART tx fifo overflow/underflow error interrupt */ - UART_INT_RX_FER, /* UART rx fifo overflow/underflow error interrupt */ - UART_INT_ALL /* All the interrupt */ -}; - -/* UART overflow or underflow type definition */ - -enum uart_overflow_e -{ - UART_TX_OVERFLOW, /* UART tx fifo overflow */ - UART_TX_UNDERFLOW, /* UART tx fifo underflow */ - UART_RX_OVERFLOW, /* UART rx fifo overflow */ - UART_RX_UNDERFLOW /* UART rx fifo underflow */ -}; - -struct uart_reg_s -{ - /* 0x0 : utx_config */ - - union - { - struct - { - uint32_t cr_utx_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t cr_utx_cts_en : 1; /* [ 1], r/w, 0x0 */ - uint32_t cr_utx_frm_en : 1; /* [ 2], r/w, 0x0 */ - uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */ - uint32_t cr_utx_prt_en : 1; /* [ 4], r/w, 0x0 */ - uint32_t cr_utx_prt_sel : 1; /* [ 5], r/w, 0x0 */ - uint32_t cr_utx_ir_en : 1; /* [ 6], r/w, 0x0 */ - uint32_t cr_utx_ir_inv : 1; /* [ 7], r/w, 0x0 */ - uint32_t cr_utx_bit_cnt_d : 3; /* [10: 8], r/w, 0x7 */ - uint32_t reserved_11 : 1; /* [ 11], rsvd, 0x0 */ - uint32_t cr_utx_bit_cnt_p : 2; /* [13:12], r/w, 0x1 */ - uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */ - uint32_t cr_utx_len : 16; /* [31:16], r/w, 0x0 */ - } bf; - uint32_t word; - } utx_config; - - /* 0x4 : urx_config */ - - union - { - struct - { - uint32_t cr_urx_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t cr_urx_rts_sw_mode : 1; /* [ 1], r/w, 0x0 */ - uint32_t cr_urx_rts_sw_val : 1; /* [ 2], r/w, 0x0 */ - uint32_t cr_urx_abr_en : 1; /* [ 3], r/w, 0x0 */ - uint32_t cr_urx_prt_en : 1; /* [ 4], r/w, 0x0 */ - uint32_t cr_urx_prt_sel : 1; /* [ 5], r/w, 0x0 */ - uint32_t cr_urx_ir_en : 1; /* [ 6], r/w, 0x0 */ - uint32_t cr_urx_ir_inv : 1; /* [ 7], r/w, 0x0 */ - uint32_t cr_urx_bit_cnt_d : 3; /* [10: 8], r/w, 0x7 */ - uint32_t cr_urx_deg_en : 1; /* [ 11], r/w, 0x0 */ - uint32_t cr_urx_deg_cnt : 4; /* [15:12], r/w, 0x0 */ - uint32_t cr_urx_len : 16; /* [31:16], r/w, 0x0 */ - } bf; - uint32_t word; - } urx_config; - - /* 0x8 : uart_bit_prd */ - - union - { - struct - { - uint32_t cr_utx_bit_prd : 16; /* [15: 0], r/w, 0xff */ - uint32_t cr_urx_bit_prd : 16; /* [31:16], r/w, 0xff */ - } bf; - uint32_t word; - } uart_bit_prd; - - /* 0xC : data_config */ - - union - { - struct - { - uint32_t cr_uart_bit_inv : 1; /* [ 0], r/w, 0x0 */ - uint32_t reserved_1_31 : 31; /* [31: 1], rsvd, 0x0 */ - } bf; - uint32_t word; - } data_config; - - /* 0x10 : utx_ir_position */ - - union - { - struct - { - uint32_t cr_utx_ir_pos_s : 16; /* [15: 0], r/w, 0x70 */ - uint32_t cr_utx_ir_pos_p : 16; /* [31:16], r/w, 0x9f */ - } bf; - uint32_t word; - } utx_ir_position; - - /* 0x14 : urx_ir_position */ - - union - { - struct - { - uint32_t cr_urx_ir_pos_s : 16; /* [15: 0], r/w, 0x6f */ - uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ - } bf; - uint32_t word; - } urx_ir_position; - - /* 0x18 : urx_rto_timer */ - - union - { - struct - { - uint32_t cr_urx_rto_value : 8; /* [ 7: 0], r/w, 0xf */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } bf; - uint32_t word; - } urx_rto_timer; - - /* 0x1c reserved */ - - uint8_t reserved_0x1c[4]; - - /* 0x20 : UART interrupt status */ - - union - { - struct - { - uint32_t utx_end_int : 1; /* [ 0], r, 0x0 */ - uint32_t urx_end_int : 1; /* [ 1], r, 0x0 */ - uint32_t utx_fifo_int : 1; /* [ 2], r, 0x0 */ - uint32_t urx_fifo_int : 1; /* [ 3], r, 0x0 */ - uint32_t urx_rto_int : 1; /* [ 4], r, 0x0 */ - uint32_t urx_pce_int : 1; /* [ 5], r, 0x0 */ - uint32_t utx_fer_int : 1; /* [ 6], r, 0x0 */ - uint32_t urx_fer_int : 1; /* [ 7], r, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } bf; - uint32_t word; - } uart_int_sts; - - /* 0x24 : UART interrupt mask */ - - union - { - struct - { - uint32_t cr_utx_end_mask : 1; /* [ 0], r/w, 0x1 */ - uint32_t cr_urx_end_mask : 1; /* [ 1], r/w, 0x1 */ - uint32_t cr_utx_fifo_mask : 1; /* [ 2], r/w, 0x1 */ - uint32_t cr_urx_fifo_mask : 1; /* [ 3], r/w, 0x1 */ - uint32_t cr_urx_rto_mask : 1; /* [ 4], r/w, 0x1 */ - uint32_t cr_urx_pce_mask : 1; /* [ 5], r/w, 0x1 */ - uint32_t cr_utx_fer_mask : 1; /* [ 6], r/w, 0x1 */ - uint32_t cr_urx_fer_mask : 1; /* [ 7], r/w, 0x1 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } bf; - uint32_t word; - } uart_int_mask; - - /* 0x28 : UART interrupt clear */ - - union - { - struct - { - uint32_t cr_utx_end_clr : 1; /* [ 0], w1c, 0x0 */ - uint32_t cr_urx_end_clr : 1; /* [ 1], w1c, 0x0 */ - uint32_t rsvd_2 : 1; /* [ 2], rsvd, 0x0 */ - uint32_t rsvd_3 : 1; /* [ 3], rsvd, 0x0 */ - uint32_t cr_urx_rto_clr : 1; /* [ 4], w1c, 0x0 */ - uint32_t cr_urx_pce_clr : 1; /* [ 5], w1c, 0x0 */ - uint32_t rsvd_6 : 1; /* [ 6], rsvd, 0x0 */ - uint32_t rsvd_7 : 1; /* [ 7], rsvd, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } bf; - uint32_t word; - } uart_int_clear; - - /* 0x2C : UART interrupt enable */ - - union - { - struct - { - uint32_t cr_utx_end_en : 1; /* [ 0], r/w, 0x1 */ - uint32_t cr_urx_end_en : 1; /* [ 1], r/w, 0x1 */ - uint32_t cr_utx_fifo_en : 1; /* [ 2], r/w, 0x1 */ - uint32_t cr_urx_fifo_en : 1; /* [ 3], r/w, 0x1 */ - uint32_t cr_urx_rto_en : 1; /* [ 4], r/w, 0x1 */ - uint32_t cr_urx_pce_en : 1; /* [ 5], r/w, 0x1 */ - uint32_t cr_utx_fer_en : 1; /* [ 6], r/w, 0x1 */ - uint32_t cr_urx_fer_en : 1; /* [ 7], r/w, 0x1 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } bf; - uint32_t word; - } uart_int_en; - - /* 0x30 : uart_status */ - - union - { - struct - { - uint32_t sts_utx_bus_busy : 1; /* [ 0], r, 0x0 */ - uint32_t sts_urx_bus_busy : 1; /* [ 1], r, 0x0 */ - uint32_t reserved_2_31 : 30; /* [31: 2], rsvd, 0x0 */ - } bf; - uint32_t word; - } uart_status; - - /* 0x34 : sts_urx_abr_prd */ - - union - { - struct - { - uint32_t - sts_urx_abr_prd_start : 16; /* [15: 0], r, 0x0 */ - uint32_t - sts_urx_abr_prd_0x55 : 16; /* [31:16], r, 0x0 */ - } bf; - uint32_t word; - } sts_urx_abr_prd; - - /* 0x38 reserved */ - - uint8_t reserved_0x38[72]; - - /* 0x80 : uart_fifo_config_0 */ - - union - { - struct - { - uint32_t uart_dma_tx_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t uart_dma_rx_en : 1; /* [ 1], r/w, 0x0 */ - uint32_t tx_fifo_clr : 1; /* [ 2], w1c, 0x0 */ - uint32_t rx_fifo_clr : 1; /* [ 3], w1c, 0x0 */ - uint32_t tx_fifo_overflow : 1; /* [ 4], r, 0x0 */ - uint32_t tx_fifo_underflow : 1; /* [ 5], r, 0x0 */ - uint32_t rx_fifo_overflow : 1; /* [ 6], r, 0x0 */ - uint32_t rx_fifo_underflow : 1; /* [ 7], r, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } bf; - uint32_t word; - } uart_fifo_config_0; - - /* 0x84 : uart_fifo_config_1 */ - - union - { - struct - { - uint32_t tx_fifo_cnt : 6; /* [ 5: 0], r, 0x20 */ - uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ - uint32_t rx_fifo_cnt : 6; /* [13: 8], r, 0x0 */ - uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */ - uint32_t tx_fifo_th : 5; /* [20:16], r/w, 0x0 */ - uint32_t reserved_21_23 : 3; /* [23:21], rsvd, 0x0 */ - uint32_t rx_fifo_th : 5; /* [28:24], r/w, 0x0 */ - uint32_t reserved_29_31 : 3; /* [31:29], rsvd, 0x0 */ - } bf; - uint32_t word; - } uart_fifo_config_1; - - /* 0x88 : uart_fifo_wdata */ - - union - { - struct - { - uint32_t uart_fifo_wdata : 8; /* [ 7: 0], w, x */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } bf; - uint32_t word; - } uart_fifo_wdata; - - /* 0x8C : uart_fifo_rdata */ - - union - { - struct - { - uint32_t uart_fifo_rdata : 8; /* [ 7: 0], r, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } bf; - uint32_t word; - } uart_fifo_rdata; -}; - -typedef volatile struct uart_reg_s uart_reg_t; - #endif /* __ASSEMBLY__ */ #endif /* __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_UART_H */ diff --git a/arch/risc-v/src/bl602/hardware/clic.h b/arch/risc-v/src/bl602/hardware/clic.h index 00297990aa8..24d3f4fd185 100644 --- a/arch/risc-v/src/bl602/hardware/clic.h +++ b/arch/risc-v/src/bl602/hardware/clic.h @@ -1,6 +1,9 @@ /**************************************************************************** * arch/risc-v/src/bl602/hardware/clic.h * + * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with * this work for additional information regarding copyright ownership. The @@ -25,8 +28,8 @@ * Pre-processor Definitions ****************************************************************************/ -#define CLIC_CTRL_ADDR 0x02000000UL -#define CLIC_HART0_ADDR 0x02800000UL +#define CLIC_CTRL_ADDR 0x02000000 +#define CLIC_HART0_ADDR 0x02800000 #define CLIC_MSIP 0x0000 #define CLIC_MSIP_size 0x4 diff --git a/arch/risc-v/src/common/riscv_arch.h b/arch/risc-v/src/common/riscv_arch.h index 7c3806c72cc..c49e05c65e8 100644 --- a/arch/risc-v/src/common/riscv_arch.h +++ b/arch/risc-v/src/common/riscv_arch.h @@ -61,6 +61,7 @@ # define putreg16(v,a) (*(volatile uint16_t *)(a) = (v)) # define getreg32(a) (*(volatile uint32_t *)(a)) # define putreg32(v,a) (*(volatile uint32_t *)(a) = (v)) +# define getreg64(a) (*(volatile uint64_t *)(a)) # define putreg64(v,a) (*(volatile uint64_t *)(a) = (v)) /**************************************************************************** diff --git a/boards/risc-v/bl602/bl602evb/README.txt b/boards/risc-v/bl602/bl602evb/README.txt index 5fd2e7b79fd..6f6306815d7 100644 --- a/boards/risc-v/bl602/bl602evb/README.txt +++ b/boards/risc-v/bl602/bl602evb/README.txt @@ -4,7 +4,7 @@ 2. Download Bouffalo lab flash tools - $ git clone https://github.com/bouffalo/flash_tools.git + $ git clone https://github.com/bouffalolab/flash_tools.git 3. Configure and build NuttX diff --git a/boards/risc-v/bl602/bl602evb/configs/nsh/defconfig b/boards/risc-v/bl602/bl602evb/configs/nsh/defconfig index a2f07c324a8..0b2c10e50be 100644 --- a/boards/risc-v/bl602/bl602evb/configs/nsh/defconfig +++ b/boards/risc-v/bl602/bl602evb/configs/nsh/defconfig @@ -1,70 +1,1136 @@ # -# This file is autogenerated: PLEASE DO NOT EDIT IT. +# Automatically generated file; DO NOT EDIT. +# NuttX/x86_64 Configuration # -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. + # -# CONFIG_NSH_DISABLEBG is not set -# CONFIG_NSH_DISABLE_LOSMART is not set -# CONFIG_NSH_DISABLE_UNAME is not set -CONFIG_ARCH="risc-v" -CONFIG_ARCH_BOARD="bl602evb" -CONFIG_ARCH_BOARD_BL602EVB=y -CONFIG_ARCH_CHIP="bl602" -CONFIG_ARCH_CHIP_BL602=y -CONFIG_ARCH_INTERRUPTSTACK=8192 -CONFIG_ARCH_RISCV=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BINFMT_DISABLE=y -CONFIG_BL602_HAVE_UART0=y -CONFIG_BOARD_LOOPSPERMSEC=10000 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FEATURES=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y +# Build Setup +# +# CONFIG_EXPERIMENTAL is not set CONFIG_DEFAULT_SMALL=y -CONFIG_DEV_ZERO=y -CONFIG_DISABLE_MQUEUE=y -CONFIG_EXAMPLES_HELLO=y -CONFIG_EXAMPLES_HELLO_STACKSIZE=8192 -CONFIG_FS_PROCFS=y -CONFIG_IDLETHREAD_STACKSIZE=8192 +CONFIG_DEFAULT_TASK_STACKSIZE=2048 +CONFIG_HOST_LINUX=y +# CONFIG_HOST_MACOS is not set +# CONFIG_HOST_WINDOWS is not set +# CONFIG_HOST_OTHER is not set + +# +# Build Configuration +# +CONFIG_APPS_DIR="../apps" +CONFIG_BUILD_FLAT=y +# CONFIG_BUILD_2PASS is not set + +# +# Binary Output Formats +# CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_PERROR_STDOUT=y -CONFIG_LIBC_STRERROR=y +# CONFIG_MOTOROLA_SREC is not set +CONFIG_RAW_BINARY=y +# CONFIG_UBOOT_UIMAGE is not set +# CONFIG_DFU_BINARY is not set + +# +# Customize Header Files +# +# CONFIG_ARCH_HAVE_STDINT_H is not set +# CONFIG_ARCH_HAVE_STDBOOL_H is not set +# CONFIG_ARCH_HAVE_MATH_H is not set +# CONFIG_ARCH_FLOAT_H is not set +CONFIG_ARCH_HAVE_STDARG_H=y +# CONFIG_ARCH_STDARG_H is not set +CONFIG_ARCH_HAVE_SETJMP=y +# CONFIG_ARCH_SETJMP_H is not set +CONFIG_ARCH_NONE_DEBUG_H=y +# CONFIG_ARCH_DEBUG_H is not set +# CONFIG_ARCH_CHIP_DEBUG_H is not set + +# +# Debug Options +# +CONFIG_DEBUG_ALERT=y +CONFIG_DEBUG_FEATURES=y + +# +# Debug SYSLOG Output Controls +# +# CONFIG_DEBUG_ERROR is not set +# CONFIG_DEBUG_ASSERTIONS is not set + +# +# Subsystem Debug Options +# +# CONFIG_DEBUG_FS is not set +# CONFIG_DEBUG_GRAPHICS is not set +# CONFIG_DEBUG_LIB is not set +# CONFIG_DEBUG_MM is not set +# CONFIG_DEBUG_POWER is not set +# CONFIG_DEBUG_SCHED is not set + +# +# OS Function Debug Options +# +# CONFIG_DEBUG_IRQ is not set + +# +# Driver Debug Options +# +# CONFIG_DEBUG_GPIO is not set +# CONFIG_DEBUG_TIMER is not set +CONFIG_ARCH_HAVE_STACKCHECK=y +CONFIG_STACK_COLORATION=y +# CONFIG_STACK_CANARIES is not set +# CONFIG_ARCH_HAVE_HEAPCHECK is not set +CONFIG_DEBUG_SYMBOLS=y +CONFIG_ARCH_HAVE_CUSTOMOPT=y +# CONFIG_DEBUG_NOOPT is not set +# CONFIG_DEBUG_CUSTOMOPT is not set +CONFIG_DEBUG_FULLOPT=y + +# +# System Type +# +# CONFIG_ARCH_ARM is not set +# CONFIG_ARCH_AVR is not set +# CONFIG_ARCH_HC is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set +# CONFIG_ARCH_RENESAS is not set +CONFIG_ARCH_RISCV=y +# CONFIG_ARCH_SIM is not set +# CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_X86_64 is not set +# CONFIG_ARCH_XTENSA is not set +# CONFIG_ARCH_Z16 is not set +# CONFIG_ARCH_Z80 is not set +# CONFIG_ARCH_OR1K is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_FAMILY="rv32im" +CONFIG_ARCH_CHIP="bl602" + +# +# RISC-V Options +# +# CONFIG_ARCH_CHIP_FE310 is not set +# CONFIG_ARCH_CHIP_K210 is not set +# CONFIG_ARCH_CHIP_LITEX is not set +# CONFIG_ARCH_CHIP_NR5 is not set +# CONFIG_ARCH_CHIP_GAP8 is not set +CONFIG_ARCH_CHIP_BL602=y +# CONFIG_ARCH_CHIP_RISCV_CUSTOM is not set +# CONFIG_ARCH_RV32I is not set +CONFIG_ARCH_RV32IM=y +# CONFIG_ARCH_RV64GC is not set + +# +# RV32IM Configuration Options +# +CONFIG_RV32IM_TOOLCHAIN_GNU_RVGL=y +# CONFIG_RI5CY_GAP8_TOOLCHAIN is not set +# CONFIG_RV32IM_HW_MULDIV is not set +# CONFIG_RV32IM_SYSTEM_CSRRS_SUPPORT is not set +CONFIG_RV32IM_CUSTOM_IRQ_SUPPORT=y + +# +# BL602 Configuration Options +# + +# +# BL602 Peripheral Support +# +CONFIG_BL602_HAVE_UART0=y +CONFIG_BL602_UART0=y +CONFIG_BL602_UART0_TX_PIN=16 +CONFIG_BL602_UART0_RX_PIN=7 +CONFIG_BL602_UART0_RTS_PIN=-1 +CONFIG_BL602_UART0_CTS_PIN=-1 +# CONFIG_BL602_HAVE_UART1 is not set +# CONFIG_BL602_UART1 is not set +CONFIG_BL602_TIMER0=y +# CONFIG_BL602_TIMER1 is not set +CONFIG_ARCH_BOARD="bl602evb" +# CONFIG_ARCH_CHIP_CUSTOM is not set +# CONFIG_ARCH_TOOLCHAIN_IAR is not set +CONFIG_ARCH_TOOLCHAIN_GNU=y +# CONFIG_ARCH_GNU_NO_WEAKFUNCTIONS is not set +# CONFIG_ARCH_SIZET_LONG is not set + +# +# Architecture Options +# +# CONFIG_ARCH_NOINTC is not set +# CONFIG_ARCH_VECNOTIRQ is not set +# CONFIG_ARCH_HAVE_IRQTRIGGER is not set +# CONFIG_ARCH_DMA is not set +# CONFIG_ARCH_HAVE_IRQPRIO is not set +# CONFIG_ARCH_ICACHE is not set +# CONFIG_ARCH_DCACHE is not set +# CONFIG_ARCH_L2CACHE is not set +# CONFIG_ARCH_HAVE_ADDRENV is not set +# CONFIG_ARCH_NEED_ADDRENV_MAPPING is not set +# CONFIG_ARCH_HAVE_MODULE_TEXT is not set +# CONFIG_ARCH_HAVE_MULTICPU is not set +# CONFIG_ARCH_HAVE_VFORK is not set +# CONFIG_ARCH_HAVE_FPU is not set +# CONFIG_ARCH_HAVE_DPFPU is not set +# CONFIG_ARCH_HAVE_MMU is not set +# CONFIG_ARCH_HAVE_MPU is not set +# CONFIG_ARCH_NAND_HWECC is not set +# CONFIG_ARCH_HAVE_EXTCLK is not set +# CONFIG_ARCH_HAVE_POWEROFF is not set +# CONFIG_ARCH_HAVE_PROGMEM is not set +# CONFIG_ARCH_HAVE_RESET is not set +# CONFIG_ARCH_HAVE_TESTSET is not set +# CONFIG_ARCH_HAVE_FETCHADD is not set +# CONFIG_ARCH_HAVE_RTC_SUBSECONDS is not set +CONFIG_ARCH_HAVE_SYSCALL_HOOKS=y +CONFIG_ARCH_STACKDUMP=y +# CONFIG_ARCH_IDLE_CUSTOM is not set +# CONFIG_ARCH_HAVE_RAMFUNCS is not set +# CONFIG_ARCH_HAVE_RAMVECTORS is not set +# CONFIG_ARCH_MINIMAL_VECTORTABLE is not set + +# +# Board Settings +# +CONFIG_BOARD_LOOPSPERMSEC=10000 + +# +# Interrupt options +# +CONFIG_ARCH_HAVE_INTERRUPTSTACK=y +CONFIG_ARCH_INTERRUPTSTACK=8192 +# CONFIG_ARCH_HAVE_HIPRI_INTERRUPT is not set + +# +# Boot options +# +# CONFIG_BOOT_RUNFROMEXTSRAM is not set +CONFIG_BOOT_RUNFROMFLASH=y +# CONFIG_BOOT_RUNFROMISRAM is not set +# CONFIG_BOOT_RUNFROMSDRAM is not set +# CONFIG_BOOT_COPYTORAM is not set + +# +# Boot Memory Configuration +# +CONFIG_RAM_START=0xc0800000 +CONFIG_RAM_SIZE=134217728 +# CONFIG_ARCH_HAVE_SDRAM is not set + +# +# Board Selection +# +CONFIG_ARCH_BOARD_BL602EVB=y +# CONFIG_ARCH_BOARD_CUSTOM is not set + +# +# Common Board Options +# + +# +# Board-Specific Options +# +# CONFIG_BOARD_CRASHDUMP is not set +CONFIG_LIB_BOARDCTL=y +# CONFIG_BOARDCTL_FINALINIT is not set +# CONFIG_BOARDCTL_UNIQUEID is not set +# CONFIG_BOARDCTL_MKRD is not set +# CONFIG_BOARDCTL_ROMDISK is not set +# CONFIG_BOARDCTL_APP_SYMTAB is not set +# CONFIG_BOARDCTL_TESTSET is not set +# CONFIG_BOARDCTL_IOCTL is not set + +# +# RTOS Features +# +CONFIG_DISABLE_OS_API=y +CONFIG_DISABLE_POSIX_TIMERS=y +# CONFIG_DISABLE_PTHREAD is not set +CONFIG_DISABLE_MQUEUE=y +CONFIG_DISABLE_ENVIRON=y + +# +# Clocks and Timers +# +CONFIG_ARCH_HAVE_TICKLESS=y +# CONFIG_SCHED_TICKLESS is not set +CONFIG_USEC_PER_TICK=10000 +# CONFIG_SYSTEMTICK_HOOK is not set +# CONFIG_SYSTEM_TIME64 is not set +# CONFIG_CLOCK_MONOTONIC is not set +CONFIG_ARCH_HAVE_TIMEKEEPING=y +# CONFIG_JULIAN_TIME is not set +CONFIG_START_YEAR=2020 +CONFIG_START_MONTH=3 +CONFIG_START_DAY=20 +CONFIG_PREALLOC_TIMERS=0 + +# +# Tasks and Scheduling +# +# CONFIG_SPINLOCK_IRQ is not set +# CONFIG_IRQCHAIN is not set +# CONFIG_IRQCOUNT is not set +# CONFIG_INIT_NONE is not set +CONFIG_INIT_ENTRYPOINT=y +CONFIG_INIT_ARGS="" +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_USERMAIN_STACKSIZE=8192 +CONFIG_USERMAIN_PRIORITY=100 +CONFIG_RR_INTERVAL=200 +# CONFIG_SCHED_SPORADIC is not set +CONFIG_TASK_NAME_SIZE=12 CONFIG_MAX_TASKS=8 +# CONFIG_SCHED_HAVE_PARENT is not set +CONFIG_SCHED_WAITPID=y +# CONFIG_SCHED_USER_IDENTITY is not set + +# +# Pthread Options +# +# CONFIG_PTHREAD_MUTEX_TYPES is not set +# CONFIG_PTHREAD_MUTEX_ROBUST is not set +CONFIG_PTHREAD_MUTEX_UNSAFE=y +# CONFIG_PTHREAD_MUTEX_BOTH is not set +# CONFIG_PTHREAD_CLEANUP is not set +# CONFIG_CANCELLATION_POINTS is not set + +# +# Performance Monitoring +# +# CONFIG_SCHED_SUSPENDSCHEDULER is not set +# CONFIG_SCHED_RESUMESCHEDULER is not set +# CONFIG_SCHED_IRQMONITOR is not set +# CONFIG_SCHED_CRITMONITOR is not set +# CONFIG_SCHED_CPULOAD is not set +# CONFIG_SCHED_INSTRUMENTATION is not set + +# +# Files and I/O +# +CONFIG_DEV_CONSOLE=y +# CONFIG_FDCLONE_DISABLE is not set +# CONFIG_FDCLONE_STDIO is not set +# CONFIG_SDCLONE_DISABLE is not set CONFIG_NFILE_DESCRIPTORS=6 -CONFIG_NSH_ARCHINIT=y +CONFIG_FILE_STREAM=y +CONFIG_NAME_MAX=32 +CONFIG_PATH_MAX=256 +# CONFIG_PRIORITY_INHERITANCE is not set + +# +# RTOS hooks +# +# CONFIG_BOARD_EARLY_INITIALIZE is not set +# CONFIG_BOARD_LATE_INITIALIZE is not set +# CONFIG_SCHED_STARTHOOK is not set +# CONFIG_SCHED_ATEXIT is not set +# CONFIG_SCHED_ONEXIT is not set + +# +# Signal Configuration +# +CONFIG_SIG_PREALLOC_IRQ_ACTIONS=8 +# CONFIG_SIG_DEFAULT is not set + +# +# Signal Numbers +# + +# +# Standard Signal Numbers +# +CONFIG_SIG_SIGUSR1=1 +CONFIG_SIG_SIGUSR2=2 +CONFIG_SIG_SIGALRM=3 +CONFIG_SIG_PIPE=13 + +# +# Non-standard Signal Numbers +# +CONFIG_SIG_SIGCONDTIMEDOUT=16 +# CONFIG_MODULE is not set + +# +# Work queue support +# +# CONFIG_SCHED_WORKQUEUE is not set +# CONFIG_SCHED_HPWORK is not set +# CONFIG_SCHED_LPWORK is not set + +# +# Stack and heap information +# +CONFIG_IDLETHREAD_STACKSIZE=8192 +CONFIG_PTHREAD_STACK_MIN=256 +CONFIG_PTHREAD_STACK_DEFAULT=8192 +# CONFIG_LIB_SYSCALL is not set + +# +# Device Drivers +# +# CONFIG_DEV_SIMPLE_ADDRENV is not set +CONFIG_DEV_NULL=y +CONFIG_DEV_ZERO=y +# CONFIG_DRVR_MKRD is not set + +# +# Buffering +# +# CONFIG_DRVR_WRITEBUFFER is not set +# CONFIG_DRVR_READAHEAD is not set +# CONFIG_SPECIFIC_DRIVERS is not set +# CONFIG_DEV_URANDOM is not set +# CONFIG_DEV_LOOP is not set +# CONFIG_ARCH_HAVE_CAN_ERRORS is not set +# CONFIG_CAN is not set +# CONFIG_ARCH_HAVE_I2CRESET is not set +# CONFIG_I2C is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set +# CONFIG_SPI is not set +# CONFIG_I2S is not set + +# +# Timer Driver Support +# +# CONFIG_ARCH_HAVE_PWM_PULSECOUNT is not set +# CONFIG_ARCH_HAVE_PWM_MULTICHAN is not set +# CONFIG_PWM is not set +CONFIG_TIMER=y +CONFIG_TIMER_ARCH=y +# CONFIG_ONESHOT is not set +# CONFIG_RTC is not set +# CONFIG_WATCHDOG is not set +# CONFIG_ANALOG is not set +# CONFIG_DRIVERS_AUDIO is not set +# CONFIG_FB_CMAP is not set +# CONFIG_FB_TRANSPARENCY is not set +# CONFIG_FB_UPDATE is not set +# CONFIG_FB_SYNC is not set +# CONFIG_FB_OVERLAY is not set +# CONFIG_DRIVERS_VIDEO is not set +# CONFIG_BCH is not set +# CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# +# CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set + +# +# LCD Driver Support +# +# CONFIG_LCD is not set + +# +# Character/Segment LCD Devices +# +# CONFIG_SLCD is not set + +# +# Other LCD-related Devices +# +# CONFIG_LCD_OTHER is not set + +# +# LED Support +# +# CONFIG_USERLED is not set +# CONFIG_LEDS_APA102 is not set +# CONFIG_LEDS_MAX7219 is not set +# CONFIG_RGBLED is not set +# CONFIG_PCA9635PW is not set +# CONFIG_NCP5623C is not set +# CONFIG_WS2812 is not set +# CONFIG_ARCH_HAVE_SDIO is not set +# CONFIG_ARCH_HAVE_SDIOWAIT_WRCOMPLETE is not set +# CONFIG_ARCH_HAVE_SDIO_PREFLIGHT is not set +# CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT is not set +# CONFIG_MMCSD is not set +# CONFIG_MODEM is not set +# CONFIG_MTD is not set +# CONFIG_EEPROM is not set +# CONFIG_PIPES is not set +# CONFIG_PM is not set +# CONFIG_DRIVERS_POWERLED is not set +# CONFIG_DRIVERS_SMPS is not set +# CONFIG_DRIVERS_MOTOR is not set +# CONFIG_POWER is not set +# CONFIG_SENSORS is not set +CONFIG_ARCH_HAVE_SERIAL_TERMIOS=y +CONFIG_SERIAL=y +# CONFIG_SERIAL_REMOVABLE is not set +CONFIG_SERIAL_CONSOLE=y +# CONFIG_16550_UART is not set +# CONFIG_OTHER_UART_SERIALDRIVER is not set +CONFIG_MCU_SERIAL=y +CONFIG_STANDARD_SERIAL=y +CONFIG_SERIAL_NPOLLWAITERS=2 +# CONFIG_SERIAL_IFLOWCONTROL is not set +# CONFIG_SERIAL_RS485CONTROL is not set +# CONFIG_SERIAL_OFLOWCONTROL is not set +# CONFIG_SERIAL_TXDMA is not set +# CONFIG_SERIAL_RXDMA is not set +# CONFIG_SERIAL_TIOCSERGSTRUCT is not set +# CONFIG_SERIAL_TERMIOS is not set +CONFIG_UART0_SERIAL_CONSOLE=y +# CONFIG_OTHER_SERIAL_CONSOLE is not set +# CONFIG_NO_SERIAL_CONSOLE is not set +# CONFIG_UART_SERIALDRIVER is not set +CONFIG_UART0_SERIALDRIVER=y +# CONFIG_UART1_SERIALDRIVER is not set +# CONFIG_UART2_SERIALDRIVER is not set +# CONFIG_UART3_SERIALDRIVER is not set +# CONFIG_UART4_SERIALDRIVER is not set +# CONFIG_UART5_SERIALDRIVER is not set +# CONFIG_UART6_SERIALDRIVER is not set +# CONFIG_UART7_SERIALDRIVER is not set +# CONFIG_UART8_SERIALDRIVER is not set + +# +# UART0 Configuration +# +CONFIG_UART0_RXBUFSIZE=128 +CONFIG_UART0_TXBUFSIZE=128 +CONFIG_UART0_BAUD=2000000 +CONFIG_UART0_BITS=8 +CONFIG_UART0_PARITY=0 +CONFIG_UART0_2STOP=0 +# CONFIG_UART0_IFLOWCONTROL is not set +# CONFIG_UART0_OFLOWCONTROL is not set +# CONFIG_UART0_RXDMA is not set +# CONFIG_UART0_TXDMA is not set +# CONFIG_LPUART_SERIALDRIVER is not set +# CONFIG_LPUART0_SERIALDRIVER is not set +# CONFIG_LPUART1_SERIALDRIVER is not set +# CONFIG_LPUART2_SERIALDRIVER is not set +# CONFIG_LPUART3_SERIALDRIVER is not set +# CONFIG_LPUART4_SERIALDRIVER is not set +# CONFIG_LPUART5_SERIALDRIVER is not set +# CONFIG_LPUART6_SERIALDRIVER is not set +# CONFIG_LPUART7_SERIALDRIVER is not set +# CONFIG_LPUART8_SERIALDRIVER is not set +# CONFIG_USART0_SERIALDRIVER is not set +# CONFIG_USART1_SERIALDRIVER is not set +# CONFIG_USART2_SERIALDRIVER is not set +# CONFIG_USART3_SERIALDRIVER is not set +# CONFIG_USART4_SERIALDRIVER is not set +# CONFIG_USART5_SERIALDRIVER is not set +# CONFIG_USART6_SERIALDRIVER is not set +# CONFIG_USART7_SERIALDRIVER is not set +# CONFIG_USART8_SERIALDRIVER is not set +# CONFIG_USART9_SERIALDRIVER is not set +# CONFIG_SCI0_SERIALDRIVER is not set +# CONFIG_SCI1_SERIALDRIVER is not set +# CONFIG_SCI2_SERIALDRIVER is not set +# CONFIG_SCI3_SERIALDRIVER is not set +# CONFIG_SCI4_SERIALDRIVER is not set +# CONFIG_SCI5_SERIALDRIVER is not set +# CONFIG_SCI6_SERIALDRIVER is not set +# CONFIG_SCI7_SERIALDRIVER is not set +# CONFIG_SCI8_SERIALDRIVER is not set +# CONFIG_SCI9_SERIALDRIVER is not set +# CONFIG_SCI10_SERIALDRIVER is not set +# CONFIG_SCI11_SERIALDRIVER is not set +# CONFIG_SCI12_SERIALDRIVER is not set +# CONFIG_PSEUDOTERM is not set +# CONFIG_USBDEV is not set +# CONFIG_USBHOST_HAVE_ASYNCH is not set +# CONFIG_USBHOST is not set +# CONFIG_USBMISC is not set +# CONFIG_HAVE_USBTRACE is not set +# CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set +# CONFIG_1WIRE is not set + +# +# System Logging +# +# CONFIG_ARCH_SYSLOG is not set +# CONFIG_SYSLOG_WRITE is not set +# CONFIG_RAMLOG is not set +# CONFIG_SYSLOG_INTBUFFER is not set +# CONFIG_SYSLOG_TIMESTAMP is not set +# CONFIG_SYSLOG_PREFIX is not set +# CONFIG_SYSLOG_CHAR is not set +# CONFIG_SYSLOG_CONSOLE is not set +CONFIG_SYSLOG_DEFAULT=y +# CONFIG_SYSLOG_FILE is not set +# CONFIG_CONSOLE_SYSLOG is not set +# CONFIG_SYSLOG_CHARDEV is not set +# CONFIG_DRIVERS_RF is not set +# CONFIG_DRIVERS_RC is not set + +# +# Networking Support +# +# CONFIG_ARCH_HAVE_NET is not set +# CONFIG_ARCH_HAVE_PHY is not set +# CONFIG_ARCH_PHY_INTERRUPT is not set +# CONFIG_ARCH_PHY_POLLED is not set +# CONFIG_ARCH_HAVE_NETDEV_STATISTICS is not set +# CONFIG_NET_WRITE_BUFFERS is not set +# CONFIG_NET_READAHEAD is not set +# CONFIG_NET_MCASTGROUP is not set +# CONFIG_NET is not set + +# +# Crypto API +# +# CONFIG_CRYPTO is not set + +# +# File Systems +# + +# +# File system configuration +# +# CONFIG_DISABLE_MOUNTPOINT is not set +# CONFIG_FS_AUTOMOUNTER is not set +CONFIG_FS_NEPOLL_DESCRIPTORS=8 +CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y +# CONFIG_EVENT_FD is not set +# CONFIG_FS_NAMED_SEMAPHORES is not set +# CONFIG_FS_RAMMAP is not set + +# +# Partition Table +# +# CONFIG_PTABLE_PARTITION is not set +# CONFIG_FS_FAT is not set +# CONFIG_NFS is not set +# CONFIG_FS_NXFFS is not set +# CONFIG_FS_ROMFS is not set +# CONFIG_FS_CROMFS is not set +# CONFIG_FS_TMPFS is not set +# CONFIG_FS_SMARTFS is not set +# CONFIG_FS_BINFS is not set +CONFIG_FS_PROCFS=y +# CONFIG_FS_PROCFS_REGISTER is not set + +# +# Exclude individual procfs entries +# +# CONFIG_FS_PROCFS_EXCLUDE_PROCESS is not set +CONFIG_FS_PROCFS_EXCLUDE_ENVIRON=y +# CONFIG_FS_PROCFS_EXCLUDE_BLOCKS is not set +# CONFIG_FS_PROCFS_EXCLUDE_MOUNT is not set +# CONFIG_FS_PROCFS_EXCLUDE_USAGE is not set +# CONFIG_FS_PROCFS_EXCLUDE_UPTIME is not set +# CONFIG_FS_PROCFS_EXCLUDE_VERSION is not set +# CONFIG_FS_PROCFS_EXCLUDE_MEMINFO is not set +# CONFIG_FS_PROCFS_EXCLUDE_MOUNTS is not set +# CONFIG_FS_SPIFFS is not set +# CONFIG_FS_LITTLEFS is not set +# CONFIG_FS_UNIONFS is not set +# CONFIG_FS_HOSTFS is not set + +# +# Graphics Support +# +# CONFIG_NX is not set +# CONFIG_NXFONTS is not set + +# +# Font Cache Pixel Depths +# +# CONFIG_NXFONTS_DISABLE_1BPP is not set +# CONFIG_NXFONTS_DISABLE_2BPP is not set +# CONFIG_NXFONTS_DISABLE_4BPP is not set +# CONFIG_NXFONTS_DISABLE_8BPP is not set +# CONFIG_NXFONTS_DISABLE_16BPP is not set +# CONFIG_NXFONTS_DISABLE_24BPP is not set +# CONFIG_NXFONTS_DISABLE_32BPP is not set +CONFIG_NXFONTS_PACKEDMSFIRST=y +# CONFIG_NXGLIB is not set + +# +# Memory Management +# +# CONFIG_MM_SMALL is not set +CONFIG_MM_REGIONS=1 +# CONFIG_ARCH_HAVE_HEAP2 is not set +# CONFIG_GRAN is not set +# CONFIG_MM_FILL_ALLOCATIONS is not set +# CONFIG_MM_CIRCBUF is not set + +# +# Common I/O Buffer Support +# +# CONFIG_MM_IOB is not set + +# +# Audio Support +# +# CONFIG_AUDIO is not set + +# +# Video Support +# + +# +# Video subsystem +# +# CONFIG_VIDEO is not set + +# +# Wireless Support +# +# CONFIG_WIRELESS is not set + +# +# Binary Loader +# +CONFIG_BINFMT_DISABLE=y +# CONFIG_SYMTAB_ORDEREDBYNAME is not set + +# +# Library Routines +# + +# +# Standard C Library Options +# + +# +# Standard C I/O +# +CONFIG_STDIO_DISABLE_BUFFERING=y +CONFIG_NUNGET_CHARS=2 +# CONFIG_LIBC_PRINT_LEGACY is not set +# CONFIG_LIBC_FLOATINGPOINT is not set +# CONFIG_LIBC_LONG_LONG is not set +# CONFIG_LIBC_SCANSET is not set +# CONFIG_EOL_IS_CR is not set +# CONFIG_EOL_IS_LF is not set +# CONFIG_EOL_IS_BOTH_CRLF is not set +CONFIG_EOL_IS_EITHER_CRLF=y +# CONFIG_AUDIO_SRC is not set +# CONFIG_LIBM is not set + +# +# Architecture-Specific Support +# +CONFIG_ARCH_LOWPUTC=y +# CONFIG_ARCH_ROMGETC is not set +# CONFIG_LIBC_ARCH_MEMCPY is not set +# CONFIG_LIBC_ARCH_MEMCMP is not set +# CONFIG_LIBC_ARCH_MEMMOVE is not set +# CONFIG_LIBC_ARCH_MEMSET is not set +# CONFIG_LIBC_ARCH_STRCHR is not set +# CONFIG_LIBC_ARCH_STRCMP is not set +# CONFIG_LIBC_ARCH_STRCPY is not set +# CONFIG_LIBC_ARCH_STRLCPY is not set +# CONFIG_LIBC_ARCH_STRNCPY is not set +# CONFIG_LIBC_ARCH_STRLEN is not set +# CONFIG_LIBC_ARCH_STRNLEN is not set +# CONFIG_LIBC_ARCH_ELF is not set + +# +# stdlib Options +# +CONFIG_LIB_RAND_ORDER=1 +CONFIG_LIBC_TMPDIR="/tmp" +CONFIG_LIBC_MAX_TMPFILE=32 + +# +# Program Execution Options +# +CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=1024 +CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=8192 +CONFIG_LIB_HOSTNAME="" + +# +# errno Decode Support +# +CONFIG_LIBC_STRERROR=y +# CONFIG_LIBC_STRERROR_SHORT is not set +CONFIG_LIBC_PERROR_STDOUT=y + +# +# memcpy/memset Options +# +# CONFIG_MEMCPY_VIK is not set +# CONFIG_MEMSET_OPTSPEED is not set + +# +# pthread support +# +# CONFIG_LIBC_DLFCN is not set +# CONFIG_LIBC_MODLIB is not set +# CONFIG_LIBC_GROUP_FILE is not set +# CONFIG_LIBC_PASSWD_FILE is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set +# CONFIG_LIBC_LZF is not set + +# +# Time/Time Zone Support +# + +# +# Thread Local Storage (TLS) +# +# CONFIG_TLS_ALIGNED is not set +CONFIG_TLS_NELEM=4 + +# +# Network-Related Options +# +# CONFIG_LIBC_IPv4_ADDRCONV is not set +# CONFIG_LIBC_IPv6_ADDRCONV is not set +# CONFIG_LIBC_NETDB is not set + +# +# NETDB Support +# +# CONFIG_LIBC_GAISTRERROR is not set +CONFIG_NETDB_BUFSIZE=256 +CONFIG_NETDB_MAX_IPADDR=1 +# CONFIG_NETDB_HOSTFILE is not set +CONFIG_LIB_SENDFILE_BUFSIZE=512 + +# +# Non-standard Library Support +# +# CONFIG_LIB_CRC64_FAST is not set +# CONFIG_LIB_KBDCODEC is not set +# CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set +CONFIG_BUILTIN=y + +# +# Basic CXX Support +# +# CONFIG_C99_BOOL8 is not set +# CONFIG_HAVE_CXX is not set +# CONFIG_LIBDSP is not set + +# +# Open Asymmetric Multi Processing +# +# CONFIG_OPENAMP is not set + +# +# Application Configuration +# + +# +# CAN Utilities +# + +# +# Examples +# +# CONFIG_EXAMPLES_ABNTCODI is not set +# CONFIG_EXAMPLES_ADXL372_TEST is not set +# CONFIG_EXAMPLES_APA102 is not set +# CONFIG_EXAMPLES_AUDIO_SOUND is not set +# CONFIG_EXAMPLES_BATTERY is not set +# CONFIG_EXAMPLES_SIXAXIS is not set +# CONFIG_EXAMPLES_CALIB_UDELAY is not set +# CONFIG_EXAMPLES_CAMERA is not set +# CONFIG_EXAMPLES_CCTYPE is not set +# CONFIG_EXAMPLES_CHARGER is not set +# CONFIG_EXAMPLES_CHAT is not set +# CONFIG_EXAMPLES_CHRONO is not set +# CONFIG_EXAMPLES_CONFIGDATA is not set +# CONFIG_EXAMPLES_DHCPD is not set +# CONFIG_EXAMPLES_DHTXX is not set +# CONFIG_EXAMPLES_DSPTEST is not set +# CONFIG_EXAMPLES_ESP32_HIMEM is not set +# CONFIG_EXAMPLES_FTPC is not set +# CONFIG_EXAMPLES_FTPD is not set +# CONFIG_EXAMPLES_FXOS8700CQ is not set +# CONFIG_EXAMPLES_GPS is not set +# CONFIG_EXAMPLES_HDC1008 is not set +CONFIG_EXAMPLES_HELLO=y +CONFIG_EXAMPLES_HELLO_PROGNAME="hello" +CONFIG_EXAMPLES_HELLO_PRIORITY=100 +CONFIG_EXAMPLES_HELLO_STACKSIZE=8192 +# CONFIG_EXAMPLES_HIDKBD is not set +# CONFIG_EXAMPLES_IGMP is not set +# CONFIG_EXAMPLES_INA219 is not set +# CONFIG_EXAMPLES_INA226 is not set +# CONFIG_EXAMPLES_LSM330SPI_TEST is not set +# CONFIG_EXAMPLES_LVGLDEMO is not set +# CONFIG_EXAMPLES_MAX31855 is not set +# CONFIG_EXAMPLES_MEDIA is not set +# CONFIG_EXAMPLES_MLX90614 is not set +# CONFIG_EXAMPLES_MODBUS is not set +# CONFIG_EXAMPLES_MODBUSMASTER is not set +# CONFIG_EXAMPLES_MOUNT is not set +# CONFIG_EXAMPLES_NULL is not set +# CONFIG_EXAMPLES_NXDEMO is not set +# CONFIG_EXAMPLES_OBD2 is not set +# CONFIG_EXAMPLES_PCA9635 is not set +# CONFIG_EXAMPLES_PDCURSES is not set +# CONFIG_EXAMPLES_POSIXSPAWN is not set +# CONFIG_EXAMPLES_POWERLED is not set +# CONFIG_EXAMPLES_POWERMONITOR is not set +# CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set +# CONFIG_EXAMPLES_RGBLED is not set +# CONFIG_EXAMPLES_SERIALBLASTER is not set +# CONFIG_EXAMPLES_SERIALRX is not set +# CONFIG_EXAMPLES_SERLOOP is not set +# CONFIG_EXAMPLES_SLCD is not set +# CONFIG_EXAMPLES_SMPS is not set +# CONFIG_EXAMPLES_STAT is not set +# CONFIG_EXAMPLES_TCPECHO is not set +# CONFIG_EXAMPLES_TIFF is not set +CONFIG_EXAMPLES_TIMER=y +CONFIG_EXAMPLES_TIMER_DEVNAME="/dev/timer0" +CONFIG_EXAMPLES_TIMER_INTERVAL=1000000 +CONFIG_EXAMPLES_TIMER_DELAY=100000 +CONFIG_EXAMPLES_TIMER_NSAMPLES=20 +CONFIG_EXAMPLES_TIMER_SIGNO=17 +CONFIG_EXAMPLES_TIMER_STACKSIZE=2048 +CONFIG_EXAMPLES_TIMER_PRIORITY=100 +CONFIG_EXAMPLES_TIMER_PROGNAME="timer" +# CONFIG_EXAMPLES_TOUCHSCREEN is not set +# CONFIG_EXAMPLES_UID is not set +# CONFIG_EXAMPLES_USBSERIAL is not set +# CONFIG_EXAMPLES_USERFS is not set +# CONFIG_EXAMPLES_WATCHDOG is not set +# CONFIG_EXAMPLES_WEBSERVER is not set +# CONFIG_EXAMPLES_XBC_TEST is not set + +# +# File System Utilities +# +# CONFIG_FSUTILS_INIFILE is not set +# CONFIG_FSUTILS_INIH is not set +# CONFIG_FSUTILS_PASSWD is not set + +# +# GPS Utilities +# +# CONFIG_GPSUTILS_MINMEA_LIB is not set + +# +# Graphics Support +# +# CONFIG_GRAPHICS_FT80X is not set +# CONFIG_GRAPHICS_LVGL is not set + +# +# NxWidgets +# + +# +# NxWM +# +# CONFIG_GRAPHICS_PDCURSES is not set +# CONFIG_TIFF is not set + +# +# Industrial Applications +# +# CONFIG_INDUSTRY_ABNT_CODI_LIB is not set + +# +# Interpreters +# +# CONFIG_INTERPRETERS_BAS is not set +# CONFIG_INTERPRETERS_DUKTAPE is not set +# CONFIG_INTERPRETERS_FICL is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set +# CONFIG_INTERPRETERS_QUICKJS is not set +# CONFIG_INTERPRETERS_WAMR is not set +# CONFIG_INTERPRETERS_WASM3 is not set + +# +# FreeModBus +# +# CONFIG_MODBUS is not set + +# +# Network Utilities +# +# CONFIG_NETUTILS_CHAT is not set +# CONFIG_NETUTILS_CJSON is not set +# CONFIG_NETUTILS_CODECS is not set +# CONFIG_NETUTILS_ESP8266 is not set +# CONFIG_NETUTILS_FTPC is not set + +# +# NSH Library +# +CONFIG_NSH_LIBRARY=y +# CONFIG_NSH_MOTD is not set + +# +# Command Line Configuration +# +CONFIG_NSH_PROMPT_STRING="nsh> " +CONFIG_NSH_READLINE=y +# CONFIG_NSH_CLE is not set +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_DISABLE_SEMICOLON=y +# CONFIG_NSH_QUOTE is not set +# CONFIG_NSH_CMDPARMS is not set +CONFIG_NSH_MAXARGUMENTS=7 +# CONFIG_NSH_ARGCAT is not set +CONFIG_NSH_NESTDEPTH=3 +# CONFIG_NSH_DISABLEBG is not set CONFIG_NSH_BUILTIN_APPS=y + +# +# Disable Individual commands +# +CONFIG_NSH_DISABLE_BASENAME=y +# CONFIG_NSH_DISABLE_CAT is not set CONFIG_NSH_DISABLE_CD=y CONFIG_NSH_DISABLE_CP=y +CONFIG_NSH_DISABLE_CMP=y +CONFIG_NSH_DISABLE_DATE=y +CONFIG_NSH_DISABLE_DD=y +CONFIG_NSH_DISABLE_DF=y +CONFIG_NSH_DISABLE_DIRNAME=y +# CONFIG_NSH_DISABLE_ECHO is not set +# CONFIG_NSH_DISABLE_ENV is not set +CONFIG_NSH_DISABLE_EXEC=y +CONFIG_NSH_DISABLE_EXIT=y +# CONFIG_NSH_DISABLE_EXPORT is not set +# CONFIG_NSH_DISABLE_FREE is not set +CONFIG_NSH_DISABLE_GET=y +# CONFIG_NSH_DISABLE_HELP is not set +CONFIG_NSH_DISABLE_HEXDUMP=y +# CONFIG_NSH_DISABLE_IFCONFIG is not set CONFIG_NSH_DISABLE_IFUPDOWN=y +# CONFIG_NSH_DISABLE_KILL is not set +CONFIG_NSH_DISABLE_LOSETUP=y +# CONFIG_NSH_DISABLE_LOSMART is not set +# CONFIG_NSH_DISABLE_LS is not set +# CONFIG_NSH_DISABLE_MB is not set CONFIG_NSH_DISABLE_MKDIR=y +CONFIG_NSH_DISABLE_MKRD=y +# CONFIG_NSH_DISABLE_MH is not set +# CONFIG_NSH_DISABLE_MOUNT is not set +# CONFIG_NSH_DISABLE_MV is not set +# CONFIG_NSH_DISABLE_MW is not set +CONFIG_NSH_DISABLE_PRINTF=y +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PSSTACKUSAGE is not set +CONFIG_NSH_DISABLE_PUT=y +# CONFIG_NSH_DISABLE_PWD is not set CONFIG_NSH_DISABLE_RM=y CONFIG_NSH_DISABLE_RMDIR=y +# CONFIG_NSH_DISABLE_SET is not set +# CONFIG_NSH_DISABLE_SOURCE is not set +# CONFIG_NSH_DISABLE_SLEEP is not set +CONFIG_NSH_DISABLE_TIME=y +# CONFIG_NSH_DISABLE_TEST is not set +# CONFIG_NSH_DISABLE_TELNETD is not set +CONFIG_NSH_DISABLE_TRUNCATE=y CONFIG_NSH_DISABLE_UMOUNT=y +# CONFIG_NSH_DISABLE_UNAME is not set +# CONFIG_NSH_DISABLE_UNSET is not set +# CONFIG_NSH_DISABLE_USLEEP is not set +CONFIG_NSH_DISABLE_WGET=y +CONFIG_NSH_DISABLE_XD=y +CONFIG_NSH_MMCSDMINOR=0 + +# +# Configure Command Options +# +# CONFIG_NSH_VARS is not set +CONFIG_NSH_CODECS_BUFSIZE=128 +CONFIG_NSH_PROC_MOUNTPOINT="/proc" CONFIG_NSH_FILEIOSIZE=64 CONFIG_NSH_STRERROR=y -CONFIG_PREALLOC_TIMERS=0 -CONFIG_PTHREAD_STACK_DEFAULT=8192 -CONFIG_RAM_SIZE=134217728 -CONFIG_RAM_START=0xc0800000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_RV32IM_CUSTOM_IRQ_SUPPORT=y -CONFIG_SCHED_WAITPID=y -CONFIG_STACK_COLORATION=y -CONFIG_START_DAY=20 -CONFIG_START_MONTH=3 -CONFIG_START_YEAR=2020 -CONFIG_STDIO_DISABLE_BUFFERING=y + +# +# Scripting Support +# +CONFIG_NSH_DISABLESCRIPT=y + +# +# Console Configuration +# +CONFIG_NSH_CONSOLE=y +# CONFIG_NSH_ALTCONDEV is not set +CONFIG_NSH_ARCHINIT=y +# CONFIG_NSH_LOGIN is not set +# CONFIG_NSH_CONSOLE_LOGIN is not set + +# +# Platform-specific Support +# +# CONFIG_PLATFORM_CONFIGDATA is not set + +# +# System Libraries and NSH Add-Ons +# +# CONFIG_SYSTEM_ADBD is not set +# CONFIG_SYSTEM_CLE is not set +# CONFIG_SYSTEM_CUTERM is not set +# CONFIG_SYSTEM_EMBEDLOG is not set +# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_SYSTEM_HEXED is not set + +# +# libuv async i/o Library +# +# CONFIG_LIBUV is not set CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=12 -CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=8192 +CONFIG_SYSTEM_NSH_PRIORITY=100 +CONFIG_SYSTEM_NSH_STACKSIZE=2048 +CONFIG_SYSTEM_NSH_PROGNAME="nsh" +# CONFIG_SYSTEM_POPEN is not set +# CONFIG_SYSTEM_RAMTEST is not set +CONFIG_READLINE_HAVE_EXTMATCH=y +CONFIG_SYSTEM_READLINE=y +CONFIG_READLINE_ECHO=y +# CONFIG_READLINE_TABCOMPLETION is not set +# CONFIG_READLINE_CMD_HISTORY is not set +# CONFIG_SYSTEM_SETLOGMASK is not set +# CONFIG_SYSTEM_STACKMONITOR is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set +# CONFIG_SYSTEM_TERMCURSES is not set +# CONFIG_SYSTEM_UBLOXMODEM is not set +# CONFIG_SYSTEM_VI is not set +# CONFIG_SYSTEM_ZMODEM is not set + +# +# Testing +# +# CONFIG_TESTING_FATUTF8 is not set +# CONFIG_TESTING_FSTEST is not set CONFIG_TESTING_GETPRIME=y -CONFIG_UART0_RXBUFSIZE=128 -CONFIG_UART0_SERIAL_CONSOLE=y -CONFIG_UART0_TXBUFSIZE=128 -CONFIG_USERMAIN_STACKSIZE=8192 -CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_TESTING_GETPRIME_PROGNAME="getprime" +CONFIG_TESTING_GETPRIME_PRIORITY=50 +CONFIG_TESTING_GETPRIME_STACKSIZE=2048 +# CONFIG_TESTING_IRTEST is not set +# CONFIG_TESTING_MM is not set +# CONFIG_TESTING_NXFFS is not set +# CONFIG_TESTING_OSTEST is not set +# CONFIG_TESTING_SCANFTEST is not set +# CONFIG_TESTING_SENSORTEST is not set +# CONFIG_TESTING_SMART is not set +# CONFIG_TESTING_SMART_TEST is not set +# CONFIG_TESTING_UNITY is not set + +# +# Wireless Libraries and NSH Add-Ons +# + +# +# Bluetooth applications +# +# CONFIG_BTSAK is not set +# CONFIG_NIMBLE is not set + +# +# IEEE 802.15.4 applications +# +# CONFIG_IEEE802154_I8SAK is not set +# CONFIG_IEEE802154_LIBMAC is not set +# CONFIG_IEEE802154_LIBUTILS is not set diff --git a/boards/risc-v/bl602/bl602evb/include/board.h b/boards/risc-v/bl602/bl602evb/include/board.h index be3f80850d9..0da525bc8fa 100644 --- a/boards/risc-v/bl602/bl602evb/include/board.h +++ b/boards/risc-v/bl602/bl602evb/include/board.h @@ -1,6 +1,9 @@ /**************************************************************************** * boards/risc-v/bl602/bl602evb/include/board.h * + * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with * this work for additional information regarding copyright ownership. The diff --git a/boards/risc-v/bl602/bl602evb/scripts/ld.script b/boards/risc-v/bl602/bl602evb/scripts/ld.script index e013ed8b375..22012719150 100644 --- a/boards/risc-v/bl602/bl602evb/scripts/ld.script +++ b/boards/risc-v/bl602/bl602evb/scripts/ld.script @@ -37,47 +37,13 @@ SECTIONS *(.rodata .rodata.*) *(.sdata2.*) - /* static cli cmds */ - . = ALIGN(4); - _bl_static_cli_cmds_start = .; - KEEP(*(.static_cli_cmds)) - *(.static_cli_cmds) - _bl_static_cli_cmds_end = .; - /* static fw attribute entry */ . = ALIGN(4); _bl_static_fw_cfg_entry_start = .; KEEP(*(.wifi.cfg.entry)) _bl_static_fw_cfg_entry_end = .; - /* static blog code1 */ - . = ALIGN(4); - _bl_static_blogcomponent_code_start = .; - KEEP(SORT(*)(.static_blogcomponent_code*)) - *(.static_blogcomponent_code*) - _bl_static_blogcomponent_code_end = .; - - /* static blog code2 */ - . = ALIGN(4); - _bl_static_blogfile_code_start = .; - KEEP(SORT(*)(.static_blogfile_code*)) - *(.static_blogfile_code*) - _bl_static_blogfile_code_end = .; - - /* static blog code3 */ - . = ALIGN(4); - _bl_static_blogpri_code_start = .; - KEEP(SORT(*)(.static_blogpri_code*)) - *(.static_blogpri_code*) - _bl_static_blogpri_code_end = .; - *(.gnu.linkonce.r.*) - - /*Framework table section, use ALIGN here to avoid fill section*/ - . = ALIGN(4); - _rom_framework_audio_device_start = .; - KEEP(*(.framework.audio_device)) - _rom_framework_audio_device_end = .; } > flash /*put wifibss in the first place*/ @@ -108,8 +74,6 @@ SECTIONS .romdata : { - /*always put freetos under global_pointer with the following order. No change!*/ - PROVIDE( __global_pointer_head$ = . ); PROVIDE( __global_pointer$ = . + 0x7F0 ); . = . + 0x498; } > ram_tcm AT > flash @@ -181,29 +145,17 @@ SECTIONS PROVIDE( _heap_start = . ); PROVIDE( _heap_size = ADDR(.stack) - _heap_start ); - .stack ORIGIN(ram_tcm) + LENGTH(ram_tcm) - __stack_size (NOLOAD) : { . = . + __stack_size; PROVIDE( _sp_main = . ); - __freertos_irq_stack_top = .; } >ram_tcm /*CFG FW used in code*/ PROVIDE( _ld_bl_static_cfg_entry_start = _bl_static_fw_cfg_entry_start ); PROVIDE( _ld_bl_static_cfg_entry_end = _bl_static_fw_cfg_entry_end ); - PROVIDE( _ld_ram_size0 = LENGTH(flash) ); - PROVIDE( _ld_ram_addr0 = ORIGIN(flash) ); - PROVIDE( _ld_ram_size1 = LENGTH(ram_tcm) ); - PROVIDE( _ld_ram_addr1 = ORIGIN(ram_tcm) ); - PROVIDE( _ld_ram_size2 = LENGTH(ram_wifi) ); - PROVIDE( _ld_ram_addr2 = ORIGIN(ram_wifi) ); - - /*BOOT2 sections*/ PROVIDE ( __boot2_pt_addr_src = BOOT2_PT_ADDR ); PROVIDE ( __boot2_flash_cfg_src = BOOT2_FLASHCFG_ADDR ); - - PROVIDE (__LD_CONFIG_EM_SEL = __EM_SIZE); } diff --git a/boards/risc-v/bl602/bl602evb/src/bl602_appinit.c b/boards/risc-v/bl602/bl602evb/src/bl602_appinit.c index 2c22feb04e1..094be4bff2c 100644 --- a/boards/risc-v/bl602/bl602evb/src/bl602_appinit.c +++ b/boards/risc-v/bl602/bl602evb/src/bl602_appinit.c @@ -1,6 +1,9 @@ /**************************************************************************** * boards/risc-v/bl602/evb/src/bl602_appinit.c * + * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with * this work for additional information regarding copyright ownership. The diff --git a/boards/risc-v/bl602/bl602evb/src/bl602_boot.c b/boards/risc-v/bl602/bl602evb/src/bl602_boot.c index d28ba44de0b..846d4e35b97 100644 --- a/boards/risc-v/bl602/bl602evb/src/bl602_boot.c +++ b/boards/risc-v/bl602/bl602evb/src/bl602_boot.c @@ -1,6 +1,9 @@ /**************************************************************************** * boards/risc-v/bl602/evb/src/bl602_boot.c * + * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with * this work for additional information regarding copyright ownership. The diff --git a/boards/risc-v/bl602/bl602evb/src/bl602_bringup.c b/boards/risc-v/bl602/bl602evb/src/bl602_bringup.c index fdc7235b671..5a65e40cc58 100644 --- a/boards/risc-v/bl602/bl602evb/src/bl602_bringup.c +++ b/boards/risc-v/bl602/bl602evb/src/bl602_bringup.c @@ -1,6 +1,9 @@ /**************************************************************************** * boards/risc-v/bl602/evb/src/bl602_bringup.c * + * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with * this work for additional information regarding copyright ownership. The diff --git a/boards/risc-v/bl602/bl602evb/src/bl602evb.h b/boards/risc-v/bl602/bl602evb/src/bl602evb.h index d58c1a7ce85..caefa092f1f 100644 --- a/boards/risc-v/bl602/bl602evb/src/bl602evb.h +++ b/boards/risc-v/bl602/bl602evb/src/bl602evb.h @@ -1,6 +1,9 @@ /**************************************************************************** * boards/risc-v/bl602/bl602evb/src/bl602evb.h * + * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with * this work for additional information regarding copyright ownership. The