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https://github.com/apache/nuttx.git
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Merged in ebsong/nuttx (pull request #712)
Pull request for cortex-r4 codes
* arm/armv7-r: Add general interrupt controller.
This is based on armv7-a gic controller code.
Signed-off-by: EunBong Song <eunb.song@samsung.com>
* arm/armv7-r: add invalidate dcache in arm_head.S
Adding invalidate dcache as a comment in arm_head.S.
Signed-off-by: EunBong Song <eunb.song@samsung.com>
* arm/armv7-r: Fix some wrong configuration of program status register.
PSR_E_BIT bit should be set for big endian system.
PSR_A_BIT bis is set automatically as arm cortex-r4 reference manual 3.7.4.
So we don't need to set this bit.
Signed-off-by: EunBong Song <eunb.song@samsung.com>
* arm/armv7-r: Fix some wrong MPU register definition.
Change MPU_RBAR_ADDR_MASK and MPU_RACR_TEX_SHIFT mask as
arm cortex-r4 reference manual.
Region Base Address Register 0-4 bits are reserved.
MPU Region Access control register type 3-5 bits.
Signed-off-by: EunBong Song <eunb.song@samsung.com>
* driver/mtd: fix compilation error.
This commit fixes below compilation errors.
CC: mtd/smart.c
mtd/smart.c:182:22: error: 'gWearBitToLevelMap4' defined but not used [-Werror=unused-const-variable=]
static const uint8_t gWearBitToLevelMap4[] =
^~~~~~~~~~~~~~~~~~~
mtd/smart.c:170:22: error: 'gWearLevelToBitMap4' defined but not used [-Werror=unused-const-variable=]
static const uint8_t gWearLevelToBitMap4[] =
^~~~~~~~~~~~~~~~~~~
cc1: all warnings being treated as errors
make[1]: *** [smart.o] Error 1
Signed-off-by: Junyeon LEE <junyeon2.lee@samsung.com>
Approved-by: GregoryN <gnutt@nuttx.org>
This commit is contained in:
EunBong Song
GregoryN
@@ -5,6 +5,13 @@
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comment "ARMv7-R Configuration Options"
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config ARMV7R_HAVE_GICv2
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bool "ARMV7R_GICv2 support"
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default y
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---help---
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Selected by the configuration tool if the architecture supports the
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Generic Interrupt Controller (GIC)
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config ARMV7R_MEMINIT
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bool
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default y if BOOT_SDRAM_DATA
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File diff suppressed because it is too large
Load Diff
@@ -190,6 +190,7 @@ __start:
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mov r0, #0
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mcr CP15_BPIALL(r0) /* Invalidate entire branch prediction array */
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mcr CP15_ICIALLU(r0) /* Invalidate I-cache */
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mcr CP15_DCIALLU(r0) /* Invalidate D-cache */
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/* Configure the system control register (see sctrl.h) */
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@@ -131,9 +131,15 @@ void up_initial_state(struct tcb_s *tcb)
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#ifndef CONFIG_ARMV7R_DECODEFIQ
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cpsr |= (PSR_F_BIT | PSR_A_BIT | PSR_E_BIT);
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cpsr |= PSR_F_BIT;
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#endif /* !CONFIG_ARMV7R_DECODEFIQ */
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#ifdef CONFIG_ENDIAN_BIG
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cpsr |= PSR_E_BIT;
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#endif /* CONFIG_ENDIAN_BIG */
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#endif /* CONFIG_SUPPRESS_INTERRUPTS */
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xcp->regs[REG_CPSR] = cpsr;
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@@ -151,7 +151,11 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
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*/
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CURRENT_REGS[REG_PC] = (uint32_t)up_sigdeliver;
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CURRENT_REGS[REG_CPSR] = (PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT | PSR_A_BIT | PSR_E_BIT);
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CURRENT_REGS[REG_CPSR] = (PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT);
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#ifdef CONFIG_ENDIAN_BIG
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CURRENT_REGS[REG_CPSR] |= PSR_E_BIT;
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#endif
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/* And make sure that the saved context in the TCB is the same
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* as the interrupt return context.
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@@ -182,7 +186,11 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
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*/
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tcb->xcp.regs[REG_PC] = (uint32_t)up_sigdeliver;
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tcb->xcp.regs[REG_CPSR] = (PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT | PSR_A_BIT | PSR_E_BIT);
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tcb->xcp.regs[REG_CPSR] = (PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT);
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#ifdef CONFIG_ENDIAN_BIG
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tcb->xcp.regs[REG_CPSR] |= PSR_E_BIT;
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#endif
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}
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}
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@@ -165,5 +165,6 @@
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#define CP15_CNTVCT(r,n) _CP15(1, r, c14, c14, n) /* Virtual Count register */
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#define CP15_CNTP_CVAL(r,n) _CP15(2, r, c14, c14, n) /* PL1 Physical Timer CompareValue register */
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#define CP15_CNTV_CVAL(r,n) _CP15(3, r, c14, c14, n) /* Virtual Timer CompareValue register */
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#define CP15_DCIALLU(r) _CP15(0, r, c15, c5, 0) /* Invalidate data cache */
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#endif /* __ARCH_ARM_SRC_ARMV7_R_CP15_H */
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,78 @@
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/****************************************************************************
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* arch/arm/src/armv7-r/mpcore.h
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* Generic Interrupt Controller Definitions
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*
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* Copyright (C) 2018 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Reference:
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* Cortex™-A9 MPCore, Revision: r4p1, Technical Reference Manual, ARM DDI
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* 0407I (ID091612).
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_ARMV7_R_MPCORE_H
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#define __ARCH_ARM_SRC_ARMV7_R_MPCORE_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include "chip.h" /* For CHIP_MPCORE_VBASE */
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* MPCore registers are memory mapped and accessed through a processor
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* specific private address space via the SCU. The Cortex-A9 MCU chip.h
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* header file must provide the definition CHIP_MPCORE_VBASE to access this
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* the registers in this memory region.
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*/
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/* Peripheral Base Offsets **************************************************/
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#define MPCORE_SCU_OFFSET 0x0000 /* 0x0000-0x00fc SCU registers */
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#define MPCORE_ICC_OFFSET 0x2000 /* 0x0000-0x00FC Interrupt conroller interface */
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#define MPCORE_GTM_OFFSET 0x0200 /* 0x0200-0x02ff Global timer */
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/* 0x0300-0x05ff Reserved */
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#define MPCORE_PTM_OFFSET 0x0600 /* 0x0600-0x06ff Private timers and watchdogs */
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/* 0x0700-0x07ff Reserved */
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#define MPCORE_ICD_OFFSET 0x1000 /* 0x1000-0x1fff Interrupt Distributor */
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/* Peripheral Base Addresses ************************************************/
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#define MPCORE_SCU_VBASE (CHIP_MPCORE_VBASE+MPCORE_SCU_OFFSET)
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#define MPCORE_ICC_VBASE (CHIP_MPCORE_VBASE+MPCORE_ICC_OFFSET)
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#define MPCORE_GTM_VBASE (CHIP_MPCORE_VBASE+MPCORE_GTM_OFFSET)
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#define MPCORE_PTM_VBASE (CHIP_MPCORE_VBASE+MPCORE_PTM_OFFSET)
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#define MPCORE_ICD_VBASE (CHIP_MPCORE_VBASE+MPCORE_ICD_OFFSET)
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#endif /* __ARCH_ARM_SRC_ARMV7_R_MPCORE_H */
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@@ -66,9 +66,10 @@
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#define MPUIR_IREGION_SHIFT (16) /* Bits 16-23: Number MPU instruction regions */
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#define MPUIR_IREGION_MASK (0xff << MPUIR_IREGION_SHIFT)
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/* Region Base Address Register Definitions */
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#define MPU_RBAR_ADDR_MASK 0xfffffffc
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/* Region Base Address Register Definitions
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* [31:5] Physical base address. Defines the base address of a region.
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*/
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#define MPU_RBAR_ADDR_MASK 0xffffffe0
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/* Region Size and Enable Register */
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@@ -93,7 +94,7 @@
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#define MPU_RACR_B (1 << 0) /* Bit 0: Bufferable */
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#define MPU_RACR_C (1 << 1) /* Bit 1: Cacheable */
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#define MPU_RACR_S (1 << 2) /* Bit 2: Shareable */
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#define MPU_RACR_TEX_SHIFT (8) /* Bits 0-2: Memory attributes (with C and B) */
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#define MPU_RACR_TEX_SHIFT (3) /* Bits 3-5: Type extension */
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#define MPU_RACR_TEX_MASK (7 << MPU_RACR_TEX_SHIFT)
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# define MPU_RACR_TEX(n) ((uint32_t)(n) << MPU_RACR_TEX_SHIFT)
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#define MPU_RACR_AP_SHIFT (8) /* Bits 8-10: Access permission */
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@@ -486,6 +487,52 @@ static inline void mpu_user_flash(uintptr_t base, size_t size)
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mpu_set_drsr(regval);
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}
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/****************************************************************************
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* Name: mpu_priv_noncache
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*
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* Description:
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* Configure a non-cacheable region as privileged internal memory
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*
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****************************************************************************/
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static inline void mpu_priv_noncache(uintptr_t base, size_t size)
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{
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unsigned int region = mpu_allocregion();
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uint32_t regval;
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uint8_t l2size;
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uint8_t subregions;
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/* Select the region */
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mpu_set_rgnr(region);
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/* Select the region base address */
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mpu_set_drbar(base & MPU_RBAR_ADDR_MASK);
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/* Select the region size and the sub-region map */
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l2size = mpu_log2regionceil(size);
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subregions = mpu_subregion(base, size, l2size);
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/* The configure the region
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* inner/outer non-cache : TEX(4), C(0), B(0), S(1)
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*/
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regval = /* Not Cacheable */
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/* Not Bufferable */
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MPU_RACR_S | /* Shareable */
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MPU_RACR_TEX(4) | /* TEX */
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MPU_RACR_AP_RWRW | /* P:RO U:None */
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MPU_RACR_XN; /* Instruction access disable */
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mpu_set_dracr(regval);
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regval = MPU_RASR_ENABLE | /* Enable region */
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MPU_RASR_RSIZE_LOG2((uint32_t)l2size) | /* Region size */
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((uint32_t)subregions << MPU_RASR_SRD_SHIFT); /* Sub-regions */
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mpu_set_drsr(regval);
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}
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/****************************************************************************
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* Name: mpu_priv_flash
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*
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@@ -734,6 +781,51 @@ static inline void mpu_peripheral(uintptr_t base, size_t size)
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mpu_set_drsr(regval);
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}
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/****************************************************************************
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* Name: mpu_user_intsram_wb
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*
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* Description:
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* Configure a region as user internal SRAM
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* Unlike a mpu_user_intsram, this regions includes WB/WA cache policy
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*
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****************************************************************************/
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static inline void mpu_user_intsram_wb(uintptr_t base, size_t size)
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{
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unsigned int region = mpu_allocregion();
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uint32_t regval;
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uint8_t l2size;
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uint8_t subregions;
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/* Select the region */
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mpu_set_rgnr(region);
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/* Select the region base address */
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mpu_set_drbar(base & MPU_RBAR_ADDR_MASK);
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/* Select the region size and the sub-region map */
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l2size = mpu_log2regionceil(size);
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subregions = mpu_subregion(base, size, l2size);
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/* The configure the region
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* WB/Write Allocate: TEX(5), C(0), B(1), S(1)
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*/
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regval = /* Not Cacheable */
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MPU_RACR_B | /* Not Bufferable */
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MPU_RACR_TEX(5) | /* TEX */
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MPU_RACR_AP_RWRW; /* P:RW U:RW */
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mpu_set_dracr(regval);
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regval = MPU_RASR_ENABLE | /* Enable region */
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MPU_RASR_RSIZE_LOG2((uint32_t)l2size) | /* Region size */
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((uint32_t)subregions << MPU_RASR_SRD_SHIFT); /* Sub-regions */
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mpu_set_drsr(regval);
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}
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#undef EXTERN
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#if defined(__cplusplus)
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}
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@@ -152,6 +152,8 @@
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#define SMART_WEAR_ZERO_MASK 0x0f
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#define SMART_WEAR_BLOCK_MASK 0x01
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#ifdef CONFIG_MTD_SMART_WEAR_LEVEL
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/* Bit mapping for wear level bits */
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/* These are defined to allow updating the wear leveling with the minimum
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* number of sector relocations / maximum use of 1 --> 0 transitions when
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@@ -184,6 +186,7 @@ static const uint8_t gWearBitToLevelMap4[] =
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7, 13, 10, 14, 6, 15, 5, 4,
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3, 12, 9, 8, 2, 11, 1, 0
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};
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#endif
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/****************************************************************************
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* Private Types
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