mirror of
https://github.com/apache/nuttx.git
synced 2026-05-21 13:13:08 +08:00
Merged in raiden00/nuttx_pe (pull request #771)
Use STM32 DMA IP core version instead of chip family names and some minor improvements arch/arm/src/stm32/chip/stm32_adc.h: raise error if two IP cores seleceted libs/libdsp/Kconfig: cosmetic change arch/arm/src/stm32/Kconfig: hide TIMER menu, HRTIM menu and USB Host debug menu if peripherals not enabled configs/stm32f429i-disco/highpri/defconfig: fix configuration warning Approved-by: GregoryN <gnutt@nuttx.org>
This commit is contained in:
Mateusz Szafoni
committed by
GregoryN
GregoryN
parent
7c77eb738e
commit
d2b98cc150
+67
-30
@@ -1491,6 +1491,7 @@ config STM32_STM32L15XX
|
||||
select STM32_HAVE_RTC_SUBSECONDS if !STM32_LOWDENSITY
|
||||
select STM32_HAVE_IP_TIMERS_V1
|
||||
select STM32_HAVE_IP_ADC_V1
|
||||
select STM32_HAVE_IP_DMA_V1
|
||||
|
||||
config STM32_ENERGYLITE
|
||||
bool
|
||||
@@ -1513,6 +1514,7 @@ config STM32_STM32F10XX
|
||||
select STM32_HAVE_TIM3
|
||||
select STM32_HAVE_IP_TIMERS_V1
|
||||
select STM32_HAVE_IP_ADC_V1_BASIC
|
||||
select STM32_HAVE_IP_DMA_V1
|
||||
|
||||
config STM32_VALUELINE
|
||||
bool
|
||||
@@ -1625,6 +1627,7 @@ config STM32_STM32F20XX
|
||||
select STM32_HAVE_IOCOMPENSATION
|
||||
select STM32_HAVE_IP_TIMERS_V1
|
||||
select STM32_HAVE_IP_ADC_V1
|
||||
select STM32_HAVE_IP_DMA_V2
|
||||
|
||||
config STM32_STM32F205
|
||||
bool
|
||||
@@ -1709,6 +1712,7 @@ config STM32_STM32F30XX
|
||||
select STM32_HAVE_TIM17
|
||||
select STM32_HAVE_IP_TIMERS_V2
|
||||
select STM32_HAVE_IP_ADC_V2
|
||||
select STM32_HAVE_IP_DMA_V1
|
||||
|
||||
config STM32_STM32F302
|
||||
bool
|
||||
@@ -1752,6 +1756,7 @@ config STM32_STM32F33XX
|
||||
select STM32_HAVE_USART3
|
||||
select STM32_HAVE_IP_TIMERS_V2
|
||||
select STM32_HAVE_IP_ADC_V2
|
||||
select STM32_HAVE_IP_DMA_V1
|
||||
|
||||
config STM32_STM32F37XX
|
||||
bool
|
||||
@@ -1777,6 +1782,7 @@ config STM32_STM32F37XX
|
||||
select STM32_HAVE_USART3
|
||||
select STM32_HAVE_IP_TIMERS_V1
|
||||
select STM32_HAVE_IP_ADC_V1_BASIC
|
||||
select STM32_HAVE_IP_DMA_V1
|
||||
|
||||
config STM32_STM32F4XXX
|
||||
bool
|
||||
@@ -1786,6 +1792,7 @@ config STM32_STM32F4XXX
|
||||
select STM32_HAVE_IOCOMPENSATION
|
||||
select STM32_HAVE_IP_TIMERS_V1
|
||||
select STM32_HAVE_IP_ADC_V1
|
||||
select STM32_HAVE_IP_DMA_V2
|
||||
|
||||
config STM32_STM32F401xBC
|
||||
bool
|
||||
@@ -2151,14 +2158,6 @@ config STM32_HAVE_UART8
|
||||
bool
|
||||
default n
|
||||
|
||||
config STM32_HAVE_IP_TIMERS_V1
|
||||
bool
|
||||
default n
|
||||
|
||||
config STM32_HAVE_IP_TIMERS_V2
|
||||
bool
|
||||
default n
|
||||
|
||||
config STM32_HAVE_TIM1
|
||||
bool
|
||||
default n
|
||||
@@ -2227,24 +2226,6 @@ config STM32_HAVE_TIM17
|
||||
bool
|
||||
default n
|
||||
|
||||
config STM32_HAVE_IP_ADC_V1
|
||||
bool
|
||||
default n
|
||||
|
||||
config STM32_HAVE_IP_ADC_V1_BASIC
|
||||
bool
|
||||
default n
|
||||
select STM32_HAVE_IP_ADC_V1
|
||||
|
||||
config STM32_HAVE_IP_ADC_V2
|
||||
bool
|
||||
default n
|
||||
|
||||
config STM32_HAVE_IP_ADC_V2_BASIC
|
||||
bool
|
||||
default n
|
||||
select STM32_HAVE_IP_ADC_V2
|
||||
|
||||
config STM32_HAVE_ADC2
|
||||
bool
|
||||
default n
|
||||
@@ -2405,6 +2386,42 @@ config STM32_HAVE_OPAMP4
|
||||
bool
|
||||
default n
|
||||
|
||||
# These are STM32 peripherals IP blocks
|
||||
|
||||
config STM32_HAVE_IP_DMA_V1
|
||||
bool
|
||||
default n
|
||||
|
||||
config STM32_HAVE_IP_DMA_V2
|
||||
bool
|
||||
default n
|
||||
|
||||
config STM32_HAVE_IP_TIMERS_V1
|
||||
bool
|
||||
default n
|
||||
|
||||
config STM32_HAVE_IP_TIMERS_V2
|
||||
bool
|
||||
default n
|
||||
|
||||
config STM32_HAVE_IP_ADC_V1
|
||||
bool
|
||||
default n
|
||||
|
||||
config STM32_HAVE_IP_ADC_V1_BASIC
|
||||
bool
|
||||
default n
|
||||
select STM32_HAVE_IP_ADC_V1
|
||||
|
||||
config STM32_HAVE_IP_ADC_V2
|
||||
bool
|
||||
default n
|
||||
|
||||
config STM32_HAVE_IP_ADC_V2_BASIC
|
||||
bool
|
||||
default n
|
||||
select STM32_HAVE_IP_ADC_V2
|
||||
|
||||
# These are the peripheral selections proper
|
||||
|
||||
config STM32_ADC1
|
||||
@@ -2824,85 +2841,102 @@ config STM32_TIM1
|
||||
bool "TIM1"
|
||||
default n
|
||||
depends on STM32_HAVE_TIM1
|
||||
select STM32_TIM
|
||||
|
||||
config STM32_TIM2
|
||||
bool "TIM2"
|
||||
default n
|
||||
select STM32_TIM
|
||||
|
||||
config STM32_TIM3
|
||||
bool "TIM3"
|
||||
default n
|
||||
depends on STM32_HAVE_TIM3
|
||||
select STM32_TIM
|
||||
|
||||
config STM32_TIM4
|
||||
bool "TIM4"
|
||||
default n
|
||||
depends on STM32_HAVE_TIM4
|
||||
select STM32_TIM
|
||||
|
||||
config STM32_TIM5
|
||||
bool "TIM5"
|
||||
default n
|
||||
depends on STM32_HAVE_TIM5
|
||||
select STM32_TIM
|
||||
|
||||
config STM32_TIM6
|
||||
bool "TIM6"
|
||||
default n
|
||||
depends on STM32_HAVE_TIM6
|
||||
select STM32_TIM
|
||||
|
||||
config STM32_TIM7
|
||||
bool "TIM7"
|
||||
default n
|
||||
depends on STM32_HAVE_TIM7
|
||||
select STM32_TIM
|
||||
|
||||
config STM32_TIM8
|
||||
bool "TIM8"
|
||||
default n
|
||||
depends on STM32_HAVE_TIM8
|
||||
select STM32_TIM
|
||||
|
||||
config STM32_TIM9
|
||||
bool "TIM9"
|
||||
default n
|
||||
depends on STM32_HAVE_TIM9
|
||||
select STM32_TIM
|
||||
|
||||
config STM32_TIM10
|
||||
bool "TIM10"
|
||||
default n
|
||||
depends on STM32_HAVE_TIM10
|
||||
select STM32_TIM
|
||||
|
||||
config STM32_TIM11
|
||||
bool "TIM11"
|
||||
default n
|
||||
depends on STM32_HAVE_TIM11
|
||||
select STM32_TIM
|
||||
|
||||
config STM32_TIM12
|
||||
bool "TIM12"
|
||||
default n
|
||||
depends on STM32_HAVE_TIM12
|
||||
select STM32_TIM
|
||||
|
||||
config STM32_TIM13
|
||||
bool "TIM13"
|
||||
default n
|
||||
depends on STM32_HAVE_TIM13
|
||||
select STM32_TIM
|
||||
|
||||
config STM32_TIM14
|
||||
bool "TIM14"
|
||||
default n
|
||||
depends on STM32_HAVE_TIM14
|
||||
select STM32_TIM
|
||||
|
||||
config STM32_TIM15
|
||||
bool "TIM15"
|
||||
default n
|
||||
depends on STM32_HAVE_TIM15
|
||||
select STM32_TIM
|
||||
|
||||
config STM32_TIM16
|
||||
bool "TIM16"
|
||||
default n
|
||||
depends on STM32_HAVE_TIM16
|
||||
select STM32_TIM
|
||||
|
||||
config STM32_TIM17
|
||||
bool "TIM17"
|
||||
default n
|
||||
depends on STM32_HAVE_TIM17
|
||||
select STM32_TIM
|
||||
|
||||
config STM32_TSC
|
||||
bool "TSC"
|
||||
@@ -2996,6 +3030,10 @@ config STM32_I2C
|
||||
config STM32_CAN
|
||||
bool
|
||||
|
||||
config STM32_TIM
|
||||
bool
|
||||
default n
|
||||
|
||||
config STM32_NOEXT_VECTORS
|
||||
bool "Disable the ARMv7-M EXT vectors"
|
||||
default n
|
||||
@@ -3316,6 +3354,7 @@ config STM32_FSMC_SRAM
|
||||
In addition to internal SRAM, SRAM may also be available through the FSMC.
|
||||
|
||||
menu "Timer Configuration"
|
||||
depends on STM32_TIM
|
||||
|
||||
if SCHED_TICKLESS
|
||||
|
||||
@@ -7051,8 +7090,7 @@ endmenu #STM32 TIMx Outputs Configuration
|
||||
endmenu # Timer Configuration
|
||||
|
||||
menu "HRTIM Configuration"
|
||||
|
||||
if STM32_HRTIM1
|
||||
depends on STM32_HRTIM
|
||||
|
||||
config STM32_HRTIM_DISABLE_CHARDRV
|
||||
bool "HRTIM Disable Character Driver"
|
||||
@@ -7629,8 +7667,6 @@ config STM32_HRTIM_TIME_PSHPLL
|
||||
|
||||
endmenu # "HRTIM Timer E Configuration"
|
||||
|
||||
endif # STM32_HRTIM1
|
||||
|
||||
endmenu # "HRTIM Configuration"
|
||||
|
||||
menu "ADC Configuration"
|
||||
@@ -9356,6 +9392,7 @@ config STM32_OTGHS_SOFINTR
|
||||
endmenu
|
||||
|
||||
menu "USB Host Debug Configuration"
|
||||
depends on STM32_USBHOST
|
||||
|
||||
config STM32_USBHOST_REGDEBUG
|
||||
bool "Register-Level Debug"
|
||||
|
||||
@@ -56,6 +56,10 @@
|
||||
* which differs too much to keep it in the same file as ADC IPv1.
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_STM32_HAVE_IP_ADC_V1) && defined(CONFIG_STM32_HAVE_IP_ADC_V2)
|
||||
# error Only one STM32 ADC IP version must be selected
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_HAVE_IP_ADC_V1)
|
||||
# if defined(CONFIG_STM32_STM32L15XX)
|
||||
# include "stm32_adc_v1l1.h" /* Special case for L1 */
|
||||
|
||||
@@ -0,0 +1,64 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32/chip/stm32_dma.h
|
||||
*
|
||||
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
* Author: Mateusz Szafoni <raiden00@railab.me>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_DMA_H
|
||||
#define __ARCH_ARM_SRC_STM32_CHIP_STM32_DMA_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
/* Include the correct DMA register definitions for selected STM32 DMA IP core:
|
||||
* - STM32 DMA IP version 1 - F0, F1, F3, L0, L1, L4
|
||||
* - STM32 DMA IP version 2 - F2, F4, F7, H7
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_STM32_HAVE_IP_DMA_V1) && defined(CONFIG_STM32_HAVE_IP_DMA_V2)
|
||||
# error Only one STM32 DMA IP version must be selected
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_HAVE_IP_DMA_V1)
|
||||
# include "stm32_dma_v1.h"
|
||||
#elif defined(CONFIG_STM32_HAVE_IP_DMA_V2)
|
||||
# include "stm32_dma_v2.h"
|
||||
#else
|
||||
# error "STM32 DMA IP version not specified"
|
||||
#endif
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_DMA_H */
|
||||
@@ -1,5 +1,5 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32/chip/stm32f10xxx_dma.h
|
||||
* arch/arm/src/stm32/chip/stm32_dma_v1.h
|
||||
*
|
||||
* Copyright (C) 2009, 2011-2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
@@ -33,12 +33,18 @@
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F10XXX_DMA_H
|
||||
#define __ARCH_ARM_SRC_STM32_CHIP_STM32F10XXX_DMA_H
|
||||
#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_DMA_V1_DMA_H
|
||||
#define __ARCH_ARM_SRC_STM32_CHIP_STM32_DMA_V1_DMA_H
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* This is implementation for STM32 DMA IP version 1 - F0, F1, F3, L0, L1, L4 */
|
||||
|
||||
#define HAVE_IP_DMA_V1 1
|
||||
#undef HAVE_IP_DMA_V2
|
||||
|
||||
/* These definitions apply to both the STM32 F1 and F3 families */
|
||||
/* 12 Channels Total: 7 DMA1 Channels(1-7) and 5 DMA2 channels (1-5) */
|
||||
|
||||
@@ -520,6 +526,75 @@
|
||||
# define DMACHAN_UART4_TX STM32_DMA2_CHAN5
|
||||
# define DMACHAN_TIM8_CH2 STM32_DMA2_CHAN5
|
||||
|
||||
#elif defined(CONFIG_STM32_STM32F33XX)
|
||||
|
||||
# define DMACHAN_ADC1 STM32_DMA1_CHAN1
|
||||
# define DMACHAN_TIM2_CH3 STM32_DMA1_CHAN1
|
||||
# define DMACHAN_TIM17_CH1_1 STM32_DMA1_CHAN1
|
||||
# define DMACHAN_TIM17_UP_1 STM32_DMA1_CHAN1
|
||||
|
||||
# define DMACHAN_ADC2_1 STM32_DMA1_CHAN2
|
||||
# define DMACHAN_SPI1_RX_1 STM32_DMA1_CHAN2
|
||||
# define DMACHAN_USART3_TX STM32_DMA1_CHAN2
|
||||
# define DMACHAN_I2C1_TX_3 STM32_DMA1_CHAN4
|
||||
# define DMACHAN_TIM1_CH1 STM32_DMA1_CHAN2
|
||||
# define DMACHAN_TIM2_UP STM32_DMA1_CHAN2
|
||||
# define DMACHAN_TIM3_CH3 STM32_DMA1_CHAN2
|
||||
# define DMACHAN_HRTIM1_M STM32_DMA1_CHAN2
|
||||
|
||||
# define DMACHAN_SPI1_TX_1 STM32_DMA1_CHAN3
|
||||
# define DMACHAN_USART3_RX STM32_DMA1_CHAN3
|
||||
# define DMACHAN_I2C1_RX_2 STM32_DMA1_CHAN3
|
||||
# define DMACHAN_TIM3_CH4 STM32_DMA1_CHAN3
|
||||
# define DMACHAN_TIM3_UP STM32_DMA1_CHAN3
|
||||
# define DMACHAN_TIM6_UP STM32_DMA1_CHAN3
|
||||
# define DMACHAN_DAC1_CH1 STM32_DMA1_CHAN3
|
||||
# define DMACHAN_TIM16_CH1_1 STM32_DMA1_CHAN3
|
||||
# define DMACHAN_TIM16_UP_1 STM32_DMA1_CHAN3
|
||||
# define DMACHAN_HRTIM1_A STM32_DMA1_CHAN3
|
||||
|
||||
# define DMACHAN_ADC2_2 STM32_DMA1_CHAN4
|
||||
# define DMACHAN_SPI1_RX_2 STM32_DMA1_CHAN4
|
||||
# define DMACHAN_USART1_TX STM32_DMA1_CHAN4
|
||||
# define DMACHAN_I2C1_TX_3 STM32_DMA1_CHAN4
|
||||
# define DMACHAN_TIM1_CH4 STM32_DMA1_CHAN4
|
||||
# define DMACHAN_TIM1_TRIG STM32_DMA1_CHAN4
|
||||
# define DMACHAN_TIM1_COM STM32_DMA1_CHAN4
|
||||
# define DMACHAN_TIM7_UP STM32_DMA1_CHAN4
|
||||
# define DMACHAN_DAC1_CH2 STM32_DMA1_CHAN4
|
||||
# define DMACHAN_HRTIM1_B STM32_DMA1_CHAN4
|
||||
|
||||
# define DMACHAN_SPI1_TX_2 STM32_DMA1_CHAN5
|
||||
# define DMACHAN_USART1_RX STM32_DMA1_CHAN5
|
||||
# define DMACHAN_I2C1_RX_3 STM32_DMA1_CHAN5
|
||||
# define DMACHAN_TIM1_UP STM32_DMA1_CHAN5
|
||||
# define DMACHAN_TIM2_CH1 STM32_DMA1_CHAN5
|
||||
# define DMACHAN_DAC2_CH1 STM32_DMA1_CHAN5
|
||||
# define DMACHAN_TIM15_CH1 STM32_DMA1_CHAN5
|
||||
# define DMACHAN_TIM15_UP STM32_DMA1_CHAN5
|
||||
# define DMACHAN_TIM15_TRIG STM32_DMA1_CHAN5
|
||||
# define DMACHAN_TIM15_COM STM32_DMA1_CHAN5
|
||||
# define DMACHAN_HRTIM1_C STM32_DMA1_CHAN5
|
||||
|
||||
# define DMACHAN_SPI1_RX_3 STM32_DMA1_CHAN6
|
||||
# define DMACHAN_USART2_RX STM32_DMA1_CHAN6
|
||||
# define DMACHAN_I2C1_TX_1 STM32_DMA1_CHAN6
|
||||
# define DMACHAN_TIM1_CH3 STM32_DMA1_CHAN6
|
||||
# define DMACHAN_TIM3_CH1 STM32_DMA1_CHAN6
|
||||
# define DMACHAN_TIM3_TRIG STM32_DMA1_CHAN6
|
||||
# define DMACHAN_TIM16_CH1_2 STM32_DMA1_CHAN6
|
||||
# define DMACHAN_TIM16_UP_2 STM32_DMA1_CHAN6
|
||||
# define DMACHAN_HRTIM1_D STM32_DMA1_CHAN6
|
||||
|
||||
# define DMACHAN_SPI1_TX_3 STM32_DMA1_CHAN7
|
||||
# define DMACHAN_USART2_TX STM32_DMA1_CHAN7
|
||||
# define DMACHAN_I2C1_RX_1 STM32_DMA1_CHAN7
|
||||
# define DMACHAN_TIM2_CH2 STM32_DMA1_CHAN7
|
||||
# define DMACHAN_TIM2_CH4 STM32_DMA1_CHAN7
|
||||
# define DMACHAN_TIM17_CH1_2 STM32_DMA1_CHAN7
|
||||
# define DMACHAN_TIM17_UP_2 STM32_DMA1_CHAN7
|
||||
# define DMACHAN_HRTIM1_E STM32_DMA1_CHAN7
|
||||
|
||||
#elif defined(CONFIG_STM32_STM32F37XX)
|
||||
|
||||
# define DMACHAN_ADC1 STM32_DMA1_CHAN1
|
||||
@@ -605,4 +680,4 @@
|
||||
# error "Unknown DMA channel assignments"
|
||||
#endif
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F10XXX_DMA_H */
|
||||
#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_DMA_V1_DMA_H */
|
||||
@@ -1,5 +1,5 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32/chip/stm32f40xxx_dma.h
|
||||
* arch/arm/src/stm32/chip/stm32_dma_v2.h
|
||||
*
|
||||
* Copyright (C) 2011-2012, 2014-2015 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2016 Omni Hoverboards Inc. All rights reserved.
|
||||
@@ -36,13 +36,18 @@
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F40XXX_DMA_H
|
||||
#define __ARCH_ARM_SRC_STM32_CHIP_STM32F40XXX_DMA_H
|
||||
#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_DMA_V2_DMA_H
|
||||
#define __ARCH_ARM_SRC_STM32_CHIP_STM32_DMA_V2_DMA_H
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* This is implementation for STM32 DMA IP version 2 - F2, F4, F7, H7 */
|
||||
|
||||
#define HAVE_IP_DMA_V2 1
|
||||
#undef HAVE_IP_DMA_V1
|
||||
|
||||
/* 2 DMA controllers */
|
||||
|
||||
#define DMA1 (0)
|
||||
@@ -558,4 +563,4 @@
|
||||
#define DMAMAP_TIM8_TRIG STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN7)
|
||||
#define DMAMAP_TIM8_COM STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN7)
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F40XXX_DMA_H */
|
||||
#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_DMA_V2_DMA_H */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,366 +0,0 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32/chip/stm32f33xxx_dma.h
|
||||
*
|
||||
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* Mateusz Szafoni <raiden00@railab.me>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F33XXX_DMA_H
|
||||
#define __ARCH_ARM_SRC_STM32_CHIP_STM32F33XXX_DMA_H
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* 12 Channels Total: 7 DMA1 Channels(1-7) and 5 DMA2 channels (1-5) */
|
||||
|
||||
#define DMA1 0
|
||||
#define DMA2 1
|
||||
#define DMA3 2
|
||||
#define DMA4 3
|
||||
#define DMA5 4
|
||||
#define DMA6 5
|
||||
#define DMA7 6
|
||||
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
#define STM32_DMA_ISR_OFFSET 0x0000 /* DMA interrupt status register */
|
||||
#define STM32_DMA_IFCR_OFFSET 0x0004 /* DMA interrupt flag clear register */
|
||||
|
||||
#define STM32_DMACHAN_OFFSET(n) (0x0014*(n))
|
||||
#define STM32_DMACHAN1_OFFSET 0x0000
|
||||
#define STM32_DMACHAN2_OFFSET 0x0014
|
||||
#define STM32_DMACHAN3_OFFSET 0x0028
|
||||
#define STM32_DMACHAN4_OFFSET 0x003c
|
||||
#define STM32_DMACHAN5_OFFSET 0x0050
|
||||
#define STM32_DMACHAN6_OFFSET 0x0064
|
||||
#define STM32_DMACHAN7_OFFSET 0x0078
|
||||
|
||||
#define STM32_DMACHAN_CCR_OFFSET 0x0008 /* DMA channel configuration register */
|
||||
#define STM32_DMACHAN_CNDTR_OFFSET 0x000c /* DMA channel number of data register */
|
||||
#define STM32_DMACHAN_CPAR_OFFSET 0x0010 /* DMA channel peripheral address register */
|
||||
#define STM32_DMACHAN_CMAR_OFFSET 0x0014 /* DMA channel 1 memory address register */
|
||||
|
||||
#define STM32_DMA_CCR_OFFSET(n) (STM32_DMACHAN_CCR_OFFSET+STM32_DMACHAN_OFFSET(n))
|
||||
#define STM32_DMA_CNDTR_OFFSET(n) (STM32_DMACHAN_CNDTR_OFFSET+STM32_DMACHAN_OFFSET(n))
|
||||
#define STM32_DMA_CPAR_OFFSET(n) (STM32_DMACHAN_CPAR_OFFSET+STM32_DMACHAN_OFFSET(n))
|
||||
#define STM32_DMA_CMAR_OFFSET(n) (STM32_DMACHAN_CMAR_OFFSET+STM32_DMACHAN_OFFSET(n))
|
||||
|
||||
#define STM32_DMA_CCR1_OFFSET 0x0008 /* DMA channel 1 configuration register */
|
||||
#define STM32_DMA_CCR2_OFFSET 0x001c /* DMA channel 2 configuration register */
|
||||
#define STM32_DMA_CCR3_OFFSET 0x0030 /* DMA channel 3 configuration register */
|
||||
#define STM32_DMA_CCR4_OFFSET 0x0044 /* DMA channel 4 configuration register */
|
||||
#define STM32_DMA_CCR5_OFFSET 0x0058 /* DMA channel 5 configuration register */
|
||||
#define STM32_DMA_CCR6_OFFSET 0x006c /* DMA channel 6 configuration register */
|
||||
#define STM32_DMA_CCR7_OFFSET 0x0080 /* DMA channel 7 configuration register */
|
||||
|
||||
#define STM32_DMA_CNDTR1_OFFSET 0x000c /* DMA channel 1 number of data register */
|
||||
#define STM32_DMA_CNDTR2_OFFSET 0x0020 /* DMA channel 2 number of data register */
|
||||
#define STM32_DMA_CNDTR3_OFFSET 0x0034 /* DMA channel 3 number of data register */
|
||||
#define STM32_DMA_CNDTR4_OFFSET 0x0048 /* DMA channel 4 number of data register */
|
||||
#define STM32_DMA_CNDTR5_OFFSET 0x005c /* DMA channel 5 number of data register */
|
||||
#define STM32_DMA_CNDTR6_OFFSET 0x0070 /* DMA channel 6 number of data register */
|
||||
#define STM32_DMA_CNDTR7_OFFSET 0x0084 /* DMA channel 7 number of data register */
|
||||
|
||||
#define STM32_DMA_CPAR1_OFFSET 0x0010 /* DMA channel 1 peripheral address register */
|
||||
#define STM32_DMA_CPAR2_OFFSET 0x0024 /* DMA channel 2 peripheral address register */
|
||||
#define STM32_DMA_CPAR3_OFFSET 0x0038 /* DMA channel 3 peripheral address register */
|
||||
#define STM32_DMA_CPAR4_OFFSET 0x004c /* DMA channel 4 peripheral address register */
|
||||
#define STM32_DMA_CPAR5_OFFSET 0x0060 /* DMA channel 5 peripheral address register */
|
||||
#define STM32_DMA_CPAR6_OFFSET 0x0074 /* DMA channel 6 peripheral address register */
|
||||
#define STM32_DMA_CPAR7_OFFSET 0x0088 /* DMA channel 7 peripheral address register */
|
||||
|
||||
#define STM32_DMA_CMAR1_OFFSET 0x0014 /* DMA channel 1 memory address register */
|
||||
#define STM32_DMA_CMAR2_OFFSET 0x0028 /* DMA channel 2 memory address register */
|
||||
#define STM32_DMA_CMAR3_OFFSET 0x003c /* DMA channel 3 memory address register */
|
||||
#define STM32_DMA_CMAR4_OFFSET 0x0050 /* DMA channel 4 memory address register */
|
||||
#define STM32_DMA_CMAR5_OFFSET 0x0064 /* DMA channel 5 memory address register */
|
||||
#define STM32_DMA_CMAR6_OFFSET 0x0078 /* DMA channel 6 memory address register */
|
||||
#define STM32_DMA_CMAR7_OFFSET 0x008c /* DMA channel 7 memory address register */
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
#define STM32_DMA1_ISRC (STM32_DMA1_BASE+STM32_DMA_ISR_OFFSET)
|
||||
#define STM32_DMA1_IFCR (STM32_DMA1_BASE+STM32_DMA_IFCR_OFFSET)
|
||||
|
||||
#define STM32_DMA1_CCR(n) (STM32_DMA1_BASE+STM32_DMA_CCR_OFFSET(n))
|
||||
#define STM32_DMA1_CCR1 (STM32_DMA1_BASE+STM32_DMA_CCR1_OFFSET)
|
||||
#define STM32_DMA1_CCR2 (STM32_DMA1_BASE+STM32_DMA_CCR2_OFFSET)
|
||||
#define STM32_DMA1_CCR3 (STM32_DMA1_BASE+STM32_DMA_CCR3_OFFSET)
|
||||
#define STM32_DMA1_CCR4 (STM32_DMA1_BASE+STM32_DMA_CCR4_OFFSET)
|
||||
#define STM32_DMA1_CCR5 (STM32_DMA1_BASE+STM32_DMA_CCR5_OFFSET)
|
||||
#define STM32_DMA1_CCR6 (STM32_DMA1_BASE+STM32_DMA_CCR6_OFFSET)
|
||||
#define STM32_DMA1_CCR7 (STM32_DMA1_BASE+STM32_DMA_CCR7_OFFSET)
|
||||
|
||||
#define STM32_DMA1_CNDTR(n) (STM32_DMA1_BASE+STM32_DMA_CNDTR_OFFSET(n))
|
||||
#define STM32_DMA1_CNDTR1 (STM32_DMA1_BASE+STM32_DMA_CNDTR1_OFFSET)
|
||||
#define STM32_DMA1_CNDTR2 (STM32_DMA1_BASE+STM32_DMA_CNDTR2_OFFSET)
|
||||
#define STM32_DMA1_CNDTR3 (STM32_DMA1_BASE+STM32_DMA_CNDTR3_OFFSET)
|
||||
#define STM32_DMA1_CNDTR4 (STM32_DMA1_BASE+STM32_DMA_CNDTR4_OFFSET)
|
||||
#define STM32_DMA1_CNDTR5 (STM32_DMA1_BASE+STM32_DMA_CNDTR5_OFFSET)
|
||||
#define STM32_DMA1_CNDTR6 (STM32_DMA1_BASE+STM32_DMA_CNDTR6_OFFSET)
|
||||
#define STM32_DMA1_CNDTR7 (STM32_DMA1_BASE+STM32_DMA_CNDTR7_OFFSET)
|
||||
|
||||
#define STM32_DMA1_CPAR(n) (STM32_DMA1_BASE+STM32_DMA_CPAR_OFFSET(n))
|
||||
#define STM32_DMA1_CPAR1 (STM32_DMA1_BASE+STM32_DMA_CPAR1_OFFSET)
|
||||
#define STM32_DMA1_CPAR2 (STM32_DMA1_BASE+STM32_DMA_CPAR2_OFFSET)
|
||||
#define STM32_DMA1_CPAR3 (STM32_DMA1_BASE+STM32_DMA_CPAR3_OFFSET)
|
||||
#define STM32_DMA1_CPAR4 (STM32_DMA1_BASE+STM32_DMA_CPAR4_OFFSET)
|
||||
#define STM32_DMA1_CPAR5 (STM32_DMA1_BASE+STM32_DMA_CPAR5_OFFSET)
|
||||
#define STM32_DMA1_CPAR6 (STM32_DMA1_BASE+STM32_DMA_CPAR6_OFFSET)
|
||||
#define STM32_DMA1_CPAR7 (STM32_DMA1_BASE+STM32_DMA_CPAR7_OFFSET)
|
||||
|
||||
#define STM32_DMA1_CMAR(n) (STM32_DMA1_BASE+STM32_DMA_CMAR_OFFSET(n))
|
||||
#define STM32_DMA1_CMAR1 (STM32_DMA1_BASE+STM32_DMA_CMAR1_OFFSET)
|
||||
#define STM32_DMA1_CMAR2 (STM32_DMA1_BASE+STM32_DMA_CMAR2_OFFSET)
|
||||
#define STM32_DMA1_CMAR3 (STM32_DMA1_BASE+STM32_DMA_CMAR3_OFFSET)
|
||||
#define STM32_DMA1_CMAR4 (STM32_DMA1_BASE+STM32_DMA_CMAR4_OFFSET)
|
||||
#define STM32_DMA1_CMAR5 (STM32_DMA1_BASE+STM32_DMA_CMAR5_OFFSET)
|
||||
#define STM32_DMA1_CMAR6 (STM32_DMA1_BASE+STM32_DMA_CMAR6_OFFSET)
|
||||
#define STM32_DMA1_CMAR7 (STM32_DMA1_BASE+STM32_DMA_CMAR7_OFFSET)
|
||||
|
||||
#define STM32_DMA2_ISRC (STM32_DMA2_BASE+STM32_DMA_ISR_OFFSET)
|
||||
#define STM32_DMA2_IFCR (STM32_DMA2_BASE+STM32_DMA_IFCR_OFFSET)
|
||||
|
||||
#define STM32_DMA2_CCR(n) (STM32_DMA2_BASE+STM32_DMA_CCR_OFFSET(n))
|
||||
#define STM32_DMA2_CCR1 (STM32_DMA2_BASE+STM32_DMA_CCR1_OFFSET)
|
||||
#define STM32_DMA2_CCR2 (STM32_DMA2_BASE+STM32_DMA_CCR2_OFFSET)
|
||||
#define STM32_DMA2_CCR3 (STM32_DMA2_BASE+STM32_DMA_CCR3_OFFSET)
|
||||
#define STM32_DMA2_CCR4 (STM32_DMA2_BASE+STM32_DMA_CCR4_OFFSET)
|
||||
#define STM32_DMA2_CCR5 (STM32_DMA2_BASE+STM32_DMA_CCR5_OFFSET)
|
||||
|
||||
#define STM32_DMA2_CNDTR(n) (STM32_DMA2_BASE+STM32_DMA_CNDTR_OFFSET(n))
|
||||
#define STM32_DMA2_CNDTR1 (STM32_DMA2_BASE+STM32_DMA_CNDTR1_OFFSET)
|
||||
#define STM32_DMA2_CNDTR2 (STM32_DMA2_BASE+STM32_DMA_CNDTR2_OFFSET)
|
||||
#define STM32_DMA2_CNDTR3 (STM32_DMA2_BASE+STM32_DMA_CNDTR3_OFFSET)
|
||||
#define STM32_DMA2_CNDTR4 (STM32_DMA2_BASE+STM32_DMA_CNDTR4_OFFSET)
|
||||
#define STM32_DMA2_CNDTR5 (STM32_DMA2_BASE+STM32_DMA_CNDTR5_OFFSET)
|
||||
|
||||
#define STM32_DMA2_CPAR(n) (STM32_DMA2_BASE+STM32_DMA_CPAR_OFFSET(n))
|
||||
#define STM32_DMA2_CPAR1 (STM32_DMA2_BASE+STM32_DMA_CPAR1_OFFSET)
|
||||
#define STM32_DMA2_CPAR2 (STM32_DMA2_BASE+STM32_DMA_CPAR2_OFFSET)
|
||||
#define STM32_DMA2_CPAR3 (STM32_DMA2_BASE+STM32_DMA_CPAR3_OFFSET)
|
||||
#define STM32_DMA2_CPAR4 (STM32_DMA2_BASE+STM32_DMA_CPAR4_OFFSET)
|
||||
#define STM32_DMA2_CPAR5 (STM32_DMA2_BASE+STM32_DMA_CPAR5_OFFSET)
|
||||
|
||||
#define STM32_DMA2_CMAR(n) (STM32_DMA2_BASE+STM32_DMA_CMAR_OFFSET(n))
|
||||
#define STM32_DMA2_CMAR1 (STM32_DMA2_BASE+STM32_DMA_CMAR1_OFFSET)
|
||||
#define STM32_DMA2_CMAR2 (STM32_DMA2_BASE+STM32_DMA_CMAR2_OFFSET)
|
||||
#define STM32_DMA2_CMAR3 (STM32_DMA2_BASE+STM32_DMA_CMAR3_OFFSET)
|
||||
#define STM32_DMA2_CMAR4 (STM32_DMA2_BASE+STM32_DMA_CMAR4_OFFSET)
|
||||
#define STM32_DMA2_CMAR5 (STM32_DMA2_BASE+STM32_DMA_CMAR5_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
|
||||
#define DMA_CHAN_SHIFT(n) ((n) << 2)
|
||||
#define DMA_CHAN_MASK 0x0f
|
||||
#define DMA_CHAN_GIF_BIT (1 << 0) /* Bit 0: Channel Global interrupt flag */
|
||||
#define DMA_CHAN_TCIF_BIT (1 << 1) /* Bit 1: Channel Transfer Complete flag */
|
||||
#define DMA_CHAN_HTIF_BIT (1 << 2) /* Bit 2: Channel Half Transfer flag */
|
||||
#define DMA_CHAN_TEIF_BIT (1 << 3) /* Bit 3: Channel Transfer Error flag */
|
||||
|
||||
/* DMA interrupt status register */
|
||||
|
||||
#define DMA_ISR_CHAN_SHIFT(n) DMA_CHAN_SHIFT(n)
|
||||
#define DMA_ISR_CHAN_MASK(n) (DMA_CHAN_MASK << DMA_ISR_CHAN_SHIFT(n))
|
||||
#define DMA_ISR_CHAN1_SHIFT (0) /* Bits 3-0: DMA Channel 1 interrupt status */
|
||||
#define DMA_ISR_CHAN1_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN1_SHIFT)
|
||||
#define DMA_ISR_CHAN2_SHIFT (4) /* Bits 7-4: DMA Channel 2 interrupt status */
|
||||
#define DMA_ISR_CHAN2_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN2_SHIFT)
|
||||
#define DMA_ISR_CHAN3_SHIFT (8) /* Bits 11-8: DMA Channel 3 interrupt status */
|
||||
#define DMA_ISR_CHAN3_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN3_SHIFT)
|
||||
#define DMA_ISR_CHAN4_SHIFT (12) /* Bits 15-12: DMA Channel 4 interrupt status */
|
||||
#define DMA_ISR_CHAN4_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN4_SHIFT)
|
||||
#define DMA_ISR_CHAN5_SHIFT (16) /* Bits 19-16: DMA Channel 5 interrupt status */
|
||||
#define DMA_ISR_CHAN5_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN5_SHIFT)
|
||||
#define DMA_ISR_CHAN6_SHIFT (20) /* Bits 23-20: DMA Channel 6 interrupt status */
|
||||
#define DMA_ISR_CHAN6_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN6_SHIFT)
|
||||
#define DMA_ISR_CHAN7_SHIFT (24) /* Bits 27-24: DMA Channel 7 interrupt status */
|
||||
#define DMA_ISR_CHAN7_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN7_SHIFT)
|
||||
|
||||
#define DMA_ISR_GIF(n) (DMA_CHAN_GIF_BIT << DMA_ISR_CHAN_SHIFT(n))
|
||||
#define DMA_ISR_TCIF(n) (DMA_CHAN_TCIF_BIT << DMA_ISR_CHAN_SHIFT(n))
|
||||
#define DMA_ISR_HTIF(n) (DMA_CHAN_HTIF_BIT << DMA_ISR_CHAN_SHIFT(n))
|
||||
#define DMA_ISR_TEIF(n) (DMA_CHAN_TEIF_BIT << DMA_ISR_CHAN_SHIFT(n))
|
||||
|
||||
/* DMA interrupt flag clear register */
|
||||
|
||||
#define DMA_IFCR_CHAN_SHIFT(n) DMA_CHAN_SHIFT(n)
|
||||
#define DMA_IFCR_CHAN_MASK(n) (DMA_CHAN_MASK << DMA_IFCR_CHAN_SHIFT(n))
|
||||
#define DMA_IFCR_CHAN1_SHIFT (0) /* Bits 3-0: DMA Channel 1 interrupt flag clear */
|
||||
#define DMA_IFCR_CHAN1_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN1_SHIFT)
|
||||
#define DMA_IFCR_CHAN2_SHIFT (4) /* Bits 7-4: DMA Channel 2 interrupt flag clear */
|
||||
#define DMA_IFCR_CHAN2_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN2_SHIFT)
|
||||
#define DMA_IFCR_CHAN3_SHIFT (8) /* Bits 11-8: DMA Channel 3 interrupt flag clear */
|
||||
#define DMA_IFCR_CHAN3_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN3_SHIFT)
|
||||
#define DMA_IFCR_CHAN4_SHIFT (12) /* Bits 15-12: DMA Channel 4 interrupt flag clear */
|
||||
#define DMA_IFCR_CHAN4_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN4_SHIFT)
|
||||
#define DMA_IFCR_CHAN5_SHIFT (16) /* Bits 19-16: DMA Channel 5 interrupt flag clear */
|
||||
#define DMA_IFCR_CHAN5_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN5_SHIFT)
|
||||
#define DMA_IFCR_CHAN6_SHIFT (20) /* Bits 23-20: DMA Channel 6 interrupt flag clear */
|
||||
#define DMA_IFCR_CHAN6_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN6_SHIFT)
|
||||
#define DMA_IFCR_CHAN7_SHIFT (24) /* Bits 27-24: DMA Channel 7 interrupt flag clear */
|
||||
#define DMA_IFCR_CHAN7_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN7_SHIFT)
|
||||
#define DMA_IFCR_ALLCHANNELS (0x0fffffff)
|
||||
|
||||
#define DMA_IFCR_CGIF(n) (DMA_CHAN_GIF_BIT << DMA_IFCR_CHAN_SHIFT(n))
|
||||
#define DMA_IFCR_CTCIF(n) (DMA_CHAN_TCIF_BIT << DMA_IFCR_CHAN_SHIFT(n))
|
||||
#define DMA_IFCR_CHTIF(n) (DMA_CHAN_HTIF_BIT << DMA_IFCR_CHAN_SHIFT(n))
|
||||
#define DMA_IFCR_CTEIF(n) (DMA_CHAN_TEIF_BIT << DMA_IFCR_CHAN_SHIFT(n))
|
||||
|
||||
/* DMA channel configuration register */
|
||||
|
||||
#define DMA_CCR_EN (1 << 0) /* Bit 0: Channel enable */
|
||||
#define DMA_CCR_TCIE (1 << 1) /* Bit 1: Transfer complete interrupt enable */
|
||||
#define DMA_CCR_HTIE (1 << 2) /* Bit 2: Half Transfer interrupt enable */
|
||||
#define DMA_CCR_TEIE (1 << 3) /* Bit 3: Transfer error interrupt enable */
|
||||
#define DMA_CCR_DIR (1 << 4) /* Bit 4: Data transfer direction */
|
||||
#define DMA_CCR_CIRC (1 << 5) /* Bit 5: Circular mode */
|
||||
#define DMA_CCR_PINC (1 << 6) /* Bit 6: Peripheral increment mode */
|
||||
#define DMA_CCR_MINC (1 << 7) /* Bit 7: Memory increment mode */
|
||||
#define DMA_CCR_PSIZE_SHIFT (8) /* Bits 8-9: Peripheral size */
|
||||
#define DMA_CCR_PSIZE_MASK (3 << DMA_CCR_PSIZE_SHIFT)
|
||||
# define DMA_CCR_PSIZE_8BITS (0 << DMA_CCR_PSIZE_SHIFT) /* 00: 8-bits */
|
||||
# define DMA_CCR_PSIZE_16BITS (1 << DMA_CCR_PSIZE_SHIFT) /* 01: 16-bits */
|
||||
# define DMA_CCR_PSIZE_32BITS (2 << DMA_CCR_PSIZE_SHIFT) /* 10: 32-bits */
|
||||
#define DMA_CCR_MSIZE_SHIFT (10) /* Bits 10-11: Memory size */
|
||||
#define DMA_CCR_MSIZE_MASK (3 << DMA_CCR_MSIZE_SHIFT)
|
||||
# define DMA_CCR_MSIZE_8BITS (0 << DMA_CCR_MSIZE_SHIFT) /* 00: 8-bits */
|
||||
# define DMA_CCR_MSIZE_16BITS (1 << DMA_CCR_MSIZE_SHIFT) /* 01: 16-bits */
|
||||
# define DMA_CCR_MSIZE_32BITS (2 << DMA_CCR_MSIZE_SHIFT) /* 10: 32-bits */
|
||||
#define DMA_CCR_PL_SHIFT (12) /* Bits 12-13: Channel Priority level */
|
||||
#define DMA_CCR_PL_MASK (3 << DMA_CCR_PL_SHIFT)
|
||||
# define DMA_CCR_PRILO (0 << DMA_CCR_PL_SHIFT) /* 00: Low */
|
||||
# define DMA_CCR_PRIMED (1 << DMA_CCR_PL_SHIFT) /* 01: Medium */
|
||||
# define DMA_CCR_PRIHI (2 << DMA_CCR_PL_SHIFT) /* 10: High */
|
||||
# define DMA_CCR_PRIVERYHI (3 << DMA_CCR_PL_SHIFT) /* 11: Very high */
|
||||
#define DMA_CCR_MEM2MEM (1 << 14) /* Bit 14: Memory to memory mode */
|
||||
|
||||
#define DMA_CCR_ALLINTS (DMA_CCR_TEIE|DMA_CCR_HTIE|DMA_CCR_TCIE)
|
||||
|
||||
/* DMA channel number of data register */
|
||||
|
||||
#define DMA_CNDTR_NDT_SHIFT (0) /* Bits 15-0: Number of data to Transfer */
|
||||
#define DMA_CNDTR_NDT_MASK (0xffff << DMA_CNDTR_NDT_SHIFT)
|
||||
|
||||
/* DMA Channel mapping. Each DMA channel has a mapping to several possible
|
||||
* sources/sinks of data. The requests from peripherals assigned to a channel
|
||||
* are simply OR'ed together before entering the DMA block. This means that only
|
||||
* one request on a given channel can be enabled at once.
|
||||
*
|
||||
* Alternative DMA channel selections are provided with a numeric suffix like _1,
|
||||
* _2, etc. Drivers, however, will use the pin selection without the numeric suffix.
|
||||
* Additional definitions are required in the board.h file.
|
||||
*/
|
||||
|
||||
#define STM32_DMA1_CHAN1 (0)
|
||||
#define STM32_DMA1_CHAN2 (1)
|
||||
#define STM32_DMA1_CHAN3 (2)
|
||||
#define STM32_DMA1_CHAN4 (3)
|
||||
#define STM32_DMA1_CHAN5 (4)
|
||||
#define STM32_DMA1_CHAN6 (5)
|
||||
#define STM32_DMA1_CHAN7 (6)
|
||||
|
||||
#define STM32_DMA2_CHAN1 (7)
|
||||
#define STM32_DMA2_CHAN2 (8)
|
||||
#define STM32_DMA2_CHAN3 (9)
|
||||
#define STM32_DMA2_CHAN4 (10)
|
||||
#define STM32_DMA2_CHAN5 (11)
|
||||
|
||||
#define DMACHAN_ADC1 STM32_DMA1_CHAN1
|
||||
#define DMACHAN_TIM2_CH3 STM32_DMA1_CHAN1
|
||||
#define DMACHAN_TIM17_CH1_1 STM32_DMA1_CHAN1
|
||||
#define DMACHAN_TIM17_UP_1 STM32_DMA1_CHAN1
|
||||
|
||||
#define DMACHAN_ADC2_1 STM32_DMA1_CHAN2
|
||||
#define DMACHAN_SPI1_RX_1 STM32_DMA1_CHAN2
|
||||
#define DMACHAN_USART3_TX STM32_DMA1_CHAN2
|
||||
#define DMACHAN_I2C1_TX_3 STM32_DMA1_CHAN4
|
||||
#define DMACHAN_TIM1_CH1 STM32_DMA1_CHAN2
|
||||
#define DMACHAN_TIM2_UP STM32_DMA1_CHAN2
|
||||
#define DMACHAN_TIM3_CH3 STM32_DMA1_CHAN2
|
||||
#define DMACHAN_HRTIM1_M STM32_DMA1_CHAN2
|
||||
|
||||
#define DMACHAN_SPI1_TX_1 STM32_DMA1_CHAN3
|
||||
#define DMACHAN_USART3_RX STM32_DMA1_CHAN3
|
||||
#define DMACHAN_I2C1_RX_2 STM32_DMA1_CHAN3
|
||||
#define DMACHAN_TIM3_CH4 STM32_DMA1_CHAN3
|
||||
#define DMACHAN_TIM3_UP STM32_DMA1_CHAN3
|
||||
#define DMACHAN_TIM6_UP STM32_DMA1_CHAN3
|
||||
#define DMACHAN_DAC1_CH1 STM32_DMA1_CHAN3
|
||||
#define DMACHAN_TIM16_CH1_1 STM32_DMA1_CHAN3
|
||||
#define DMACHAN_TIM16_UP_1 STM32_DMA1_CHAN3
|
||||
#define DMACHAN_HRTIM1_A STM32_DMA1_CHAN3
|
||||
|
||||
#define DMACHAN_ADC2_2 STM32_DMA1_CHAN4
|
||||
#define DMACHAN_SPI1_RX_2 STM32_DMA1_CHAN4
|
||||
#define DMACHAN_USART1_TX STM32_DMA1_CHAN4
|
||||
#define DMACHAN_I2C1_TX_3 STM32_DMA1_CHAN4
|
||||
#define DMACHAN_TIM1_CH4 STM32_DMA1_CHAN4
|
||||
#define DMACHAN_TIM1_TRIG STM32_DMA1_CHAN4
|
||||
#define DMACHAN_TIM1_COM STM32_DMA1_CHAN4
|
||||
#define DMACHAN_TIM7_UP STM32_DMA1_CHAN4
|
||||
#define DMACHAN_DAC1_CH2 STM32_DMA1_CHAN4
|
||||
#define DMACHAN_HRTIM1_B STM32_DMA1_CHAN4
|
||||
|
||||
#define DMACHAN_SPI1_TX_2 STM32_DMA1_CHAN5
|
||||
#define DMACHAN_USART1_RX STM32_DMA1_CHAN5
|
||||
#define DMACHAN_I2C1_RX_3 STM32_DMA1_CHAN5
|
||||
#define DMACHAN_TIM1_UP STM32_DMA1_CHAN5
|
||||
#define DMACHAN_TIM2_CH1 STM32_DMA1_CHAN5
|
||||
#define DMACHAN_DAC2_CH1 STM32_DMA1_CHAN5
|
||||
#define DMACHAN_TIM15_CH1 STM32_DMA1_CHAN5
|
||||
#define DMACHAN_TIM15_UP STM32_DMA1_CHAN5
|
||||
#define DMACHAN_TIM15_TRIG STM32_DMA1_CHAN5
|
||||
#define DMACHAN_TIM15_COM STM32_DMA1_CHAN5
|
||||
#define DMACHAN_HRTIM1_C STM32_DMA1_CHAN5
|
||||
|
||||
#define DMACHAN_SPI1_RX_3 STM32_DMA1_CHAN6
|
||||
#define DMACHAN_USART2_RX STM32_DMA1_CHAN6
|
||||
#define DMACHAN_I2C1_TX_1 STM32_DMA1_CHAN6
|
||||
#define DMACHAN_TIM1_CH3 STM32_DMA1_CHAN6
|
||||
#define DMACHAN_TIM3_CH1 STM32_DMA1_CHAN6
|
||||
#define DMACHAN_TIM3_TRIG STM32_DMA1_CHAN6
|
||||
#define DMACHAN_TIM16_CH1_2 STM32_DMA1_CHAN6
|
||||
#define DMACHAN_TIM16_UP_2 STM32_DMA1_CHAN6
|
||||
#define DMACHAN_HRTIM1_D STM32_DMA1_CHAN6
|
||||
|
||||
#define DMACHAN_SPI1_TX_3 STM32_DMA1_CHAN7
|
||||
#define DMACHAN_USART2_TX STM32_DMA1_CHAN7
|
||||
#define DMACHAN_I2C1_RX_1 STM32_DMA1_CHAN7
|
||||
#define DMACHAN_TIM2_CH2 STM32_DMA1_CHAN7
|
||||
#define DMACHAN_TIM2_CH4 STM32_DMA1_CHAN7
|
||||
#define DMACHAN_TIM17_CH1_2 STM32_DMA1_CHAN7
|
||||
#define DMACHAN_TIM17_UP_2 STM32_DMA1_CHAN7
|
||||
#define DMACHAN_HRTIM1_E STM32_DMA1_CHAN7
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F33XXX_DMA_H */
|
||||
@@ -46,25 +46,17 @@
|
||||
****************************************************************************/
|
||||
|
||||
/* This file is only a thin shell that includes the correct DMA implementation
|
||||
* for the selected STM32 family. The correct file cannot be selected by
|
||||
* the make system because it needs the intelligence that only exists in
|
||||
* chip.h that can associate an STM32 part number with an STM32 family.
|
||||
* for the selected STM32 IP core:
|
||||
* - STM32 DMA IP version 1 - F0, F1, F3, L0, L1, L4
|
||||
* - STM32 DMA IP version 2 - F2, F4, F7, H7
|
||||
*
|
||||
* The STM32 F4 DMA differs from the F1 DMA primarily in that it adds the
|
||||
* concept of "streams" that are used to associate DMA sources with DMA
|
||||
* channels.
|
||||
*
|
||||
* TODO: use STM32 DMA IP version instead of chip faimily:
|
||||
* - STM32 DMA IP core version 1 - F0, F1, F3, L1
|
||||
* - STM32 DMA IP core version 2 - F2, F4, F7, H7
|
||||
* The STM32 DMA IPv2 differs from the STM32 DMA IPv1 primarily in that it
|
||||
* adds the concept of "streams" that are used to associate DMA sources with
|
||||
* DMA channels.
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || \
|
||||
defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \
|
||||
defined(CONFIG_STM32_STM32F37XX)
|
||||
# include "stm32f10xxx_dma.c"
|
||||
#elif defined(CONFIG_STM32_STM32F20XX)
|
||||
# include "stm32f20xxx_dma.c"
|
||||
#elif defined(CONFIG_STM32_STM32F4XXX)
|
||||
# include "stm32f40xxx_dma.c"
|
||||
#if defined(CONFIG_STM32_HAVE_IP_DMA_V1)
|
||||
# include "stm32_dma_v1.c"
|
||||
#elif defined(CONFIG_STM32_HAVE_IP_DMA_V2)
|
||||
# include "stm32_dma_v2.c"
|
||||
#endif
|
||||
|
||||
@@ -45,54 +45,19 @@
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
/* Include the correct DMA register definitions for this STM32 family */
|
||||
|
||||
#if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || \
|
||||
defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX)
|
||||
# include "chip/stm32f10xxx_dma.h"
|
||||
#elif defined(CONFIG_STM32_STM32F33XX)
|
||||
# include "chip/stm32f33xxx_dma.h"
|
||||
#elif defined(CONFIG_STM32_STM32F20XX)
|
||||
# include "chip/stm32f20xxx_dma.h"
|
||||
#elif defined(CONFIG_STM32_STM32F4XXX)
|
||||
# include "chip/stm32f40xxx_dma.h"
|
||||
#else
|
||||
# error "Unknown STM32 DMA"
|
||||
#endif
|
||||
|
||||
/* Support for STM32 DMA IP version 1 - F0, F1, F3, L0, L1
|
||||
* REVISIT: move this to Kconfig
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || \
|
||||
defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \
|
||||
defined(CONFIG_STM32_STM32F37XX)
|
||||
# define HAVE_IP_DMA_V1
|
||||
#endif
|
||||
|
||||
/* Support for STM32 DMA IP version 2 - F2, F4, F7, H7 */
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
|
||||
# define HAVE_IP_DMA_V2
|
||||
#endif
|
||||
|
||||
#if !defined(HAVE_IP_DMA_V1) && !defined(HAVE_IP_DMA_V2)
|
||||
# error Unknown STM32 DMA IP version
|
||||
#endif
|
||||
#include "chip/stm32_dma.h"
|
||||
|
||||
/* These definitions provide the bit encoding of the 'status' parameter passed to the
|
||||
* DMA callback function (see dma_callback_t).
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || \
|
||||
defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \
|
||||
defined(CONFIG_STM32_STM32F37XX)
|
||||
#if defined(HAVE_IP_DMA_V1)
|
||||
# define DMA_STATUS_FEIF 0 /* (Not available in F1) */
|
||||
# define DMA_STATUS_DMEIF 0 /* (Not available in F1) */
|
||||
# define DMA_STATUS_TEIF DMA_CHAN_TEIF_BIT /* Channel Transfer Error */
|
||||
# define DMA_STATUS_HTIF DMA_CHAN_HTIF_BIT /* Channel Half Transfer */
|
||||
# define DMA_STATUS_TCIF DMA_CHAN_TCIF_BIT /* Channel Transfer Complete */
|
||||
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
|
||||
#elif defined(HAVE_IP_DMA_V2)
|
||||
# define DMA_STATUS_FEIF 0 /* Stream FIFO error (ignored) */
|
||||
# define DMA_STATUS_DMEIF DMA_STREAM_DMEIF_BIT /* Stream direct mode error */
|
||||
# define DMA_STATUS_TEIF DMA_STREAM_TEIF_BIT /* Stream Transfer Error */
|
||||
@@ -128,9 +93,8 @@ typedef FAR void *DMA_HANDLE;
|
||||
typedef void (*dma_callback_t)(DMA_HANDLE handle, uint8_t status, void *arg);
|
||||
|
||||
#ifdef CONFIG_DEBUG_DMA_INFO
|
||||
#if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || \
|
||||
defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \
|
||||
defined(CONFIG_STM32_STM32F37XX)
|
||||
|
||||
#if defined(HAVE_IP_DMA_V1)
|
||||
struct stm32_dmaregs_s
|
||||
{
|
||||
uint32_t isr;
|
||||
@@ -139,7 +103,7 @@ struct stm32_dmaregs_s
|
||||
uint32_t cpar;
|
||||
uint32_t cmar;
|
||||
};
|
||||
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
|
||||
#elif defined(HAVE_IP_DMA_V2)
|
||||
struct stm32_dmaregs_s
|
||||
{
|
||||
uint32_t lisr;
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/stm32/stm32f10xxx_dma.c
|
||||
* arch/arm/src/stm32/stm32_dma_v1.c
|
||||
*
|
||||
* Copyright (C) 2009, 2011-2013, 2016-2017 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
@@ -55,9 +55,7 @@
|
||||
#include "stm32_dma.h"
|
||||
#include "stm32.h"
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) || \
|
||||
defined(CONFIG_STM32_STM32F33XX) || defined(CONFIG_STM32_STM32F37XX) || \
|
||||
defined(CONFIG_STM32_STM32L15XX)
|
||||
/* This file supports the STM32 DMA IP core version 1 - F0, F1, F3, L1, L4 */
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
@@ -787,5 +785,3 @@ uint32_t stm32_dma_intget(unsigned int chndx)
|
||||
return dmabase_getreg(dmach, STM32_DMA_ISR_OFFSET) & DMA_ISR_CHAN_MASK(dmach->chan);
|
||||
}
|
||||
#endif /* CONFIG_ARCH_HIPRI_INTERRUPT */
|
||||
|
||||
#endif /* CONFIG_STM32_STM32F10XX */
|
||||
@@ -1,5 +1,5 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/stm32/stm32f40xxx_dma.c
|
||||
* arch/arm/src/stm32/stm32_dma_v2.c
|
||||
*
|
||||
* Copyright (C) 2011-2013, 2016-2017 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
@@ -55,12 +55,11 @@
|
||||
#include "stm32_dma.h"
|
||||
#include "stm32.h"
|
||||
|
||||
/* This file supports only the STM32 F4 family (an probably the F2 family
|
||||
* as well?)
|
||||
/* This file supports the STM32 DMA IP core version 2 - F2, F4, F7, H7
|
||||
* NOTE: F7 and H7 need support for DCACHE which is not implemented here
|
||||
* but otherwise DMA IP cores look the same.
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F4XXX)
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
@@ -1131,5 +1130,3 @@ uint8_t stm32_dma_intget(unsigned int controller, uint8_t stream)
|
||||
return (uint8_t)regval;
|
||||
}
|
||||
#endif /* CONFIG_ARCH_HIPRI_INTERRUPT */
|
||||
|
||||
#endif /* CONFIG_STM32_STM32F4XXX */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,5 +1,3 @@
|
||||
# CONFIG_ARCH_FPU is not set
|
||||
# CONFIG_STM32_CCMEXCLUDE is not set
|
||||
# CONFIG_STM32_FLASH_PREFETCH is not set
|
||||
CONFIG_ADC=y
|
||||
CONFIG_ANALOG=y
|
||||
|
||||
+4
-1
@@ -9,9 +9,10 @@ config LIBDSP
|
||||
---help---
|
||||
Enable build for various DSP functions
|
||||
|
||||
if LIBDSP
|
||||
|
||||
config LIBDSP_DEBUG
|
||||
bool "Libdsp debugging"
|
||||
depends on LIBDSP
|
||||
default n
|
||||
---help---
|
||||
Enable debugging for libdsp. This option enables additional parameters
|
||||
@@ -28,3 +29,5 @@ config LIBDSP_PRECISION
|
||||
0 - the fastest calculation but the lowest precision
|
||||
1 - a little better precision than above, but slowest
|
||||
2 - the most accuracte but the slowest one, use standard math functions.
|
||||
|
||||
endif # LIBDSP
|
||||
|
||||
Reference in New Issue
Block a user