mirror of
https://github.com/apache/nuttx.git
synced 2026-06-07 17:33:08 +08:00
Interrupt priority fix + new LM3S header files
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4792 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
@@ -203,6 +203,7 @@
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#define NVIC_ISAR3_OFFSET 0x0d6c /* ISA feature register 3 */
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#define NVIC_ISAR4_OFFSET 0x0d70 /* ISA feature register 4 */
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#define NVIC_CPACR_OFFSET 0x0d88 /* Coprocessor Access Control Register */
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#define NVIC_ICTR_OFFSET 0x0004 /* Interrupt controller type register */
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#define NVIC_STIR_OFFSET 0x0f00 /* Software trigger interrupt register */
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#define NVIC_FPCCR_OFFSET 0x0f34 /* Floating-point Context Control Register */
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#define NVIC_FPCAR_OFFSET 0x0f38 /* Floating-point Context Address Register */
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@@ -372,6 +373,7 @@
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#define NVIC_ISAR3 (ARMV7M_NVIC_BASE + NVIC_ISAR3_OFFSET)
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#define NVIC_ISAR4 (ARMV7M_NVIC_BASE + NVIC_ISAR4_OFFSET)
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#define NVIC_CPACR (ARMV7M_NVIC_BASE + NVIC_CPACR_OFFSET)
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#define NVIC_ICTR (ARMV7M_NVIC_BASE + NVIC_ICTR_OFFSET)
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#define NVIC_STIR (ARMV7M_NVIC_BASE + NVIC_STIR_OFFSET)
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#define NVIC_FPCCR (ARMV7M_NVIC_BASE + NVIC_FPCCR_OFFSET)
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#define NVIC_PID4 (ARMV7M_NVIC_BASE + NVIC_PID4_OFFSET)
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Executable
+113
@@ -0,0 +1,113 @@
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/************************************************************************************
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* arch/arm/src/lm3s/lm3s_epi.h
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*
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* Copyright (C) 2009-2012 Max Neklyudov. All rights reserved.
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* Author: Max Neklyudov <macscomp@gmail.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_LM3S_LM3S_EPI_H
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#define __ARCH_ARM_SRC_LM3S_LM3S_EPI_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* External Peripheral Interface Register Offsets ***********************************/
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#define LM3S_EPI_CFG_OFFSET 0x000
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#define LM3S_EPI_SDRAMCFG_OFFSET 0x010
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#define LM3S_EPI_ADDRMAP_OFFSET 0x01C
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#define LM3S_EPI_STAT_OFFSET 0x060
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#define LM3S_EPI_BAUD_OFFSET 0x004
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/* External Peripheral Interface Register Addresses *********************************/
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#define LM3S_EPI0_CFG (LM3S_EPI0_BASE + LM3S_EPI_CFG_OFFSET)
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#define LM3S_EPI0_SDRAMCFG (LM3S_EPI0_BASE + LM3S_EPI_SDRAMCFG_OFFSET)
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#define LM3S_EPI0_ADDRMAP (LM3S_EPI0_BASE + LM3S_EPI_ADDRMAP_OFFSET)
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#define LM3S_EPI0_STAT (LM3S_EPI0_BASE + LM3S_EPI_STAT_OFFSET)
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#define LM3S_EPI0_BAUD (LM3S_EPI0_BASE + LM3S_EPI_BAUD_OFFSET)
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/* External Peripheral Interface Register Bit Definitions ***************************/
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/* EPI Configuration (EPICFG), offset 0x000 */
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#define EPI_CFG_MODE_SHIFT 0 /* Bits 3-0: Mode Select */
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#define EPI_CFG_MODE_MASK (0x1f << EPI_CFG_MODE_SHIFT)
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# define EPI_CFG_MODE_SDRAM (0x11 << EPI_CFG_MODE_SHIFT) /* SDRAM + BLKEN */
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/* EPI Address Map (EPIADDRMAP), offset 0x01C */
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#define EPI_ADDRMAP_ERADR_SHIFT 0 /* Bits 1-0: External RAM Address */
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#define EPI_ADDRMAP_ERADR_MASK (0x3 << EPI_ADDRMAP_ERADR_SHIFT)
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# define EPI_ADDRMAP_ERADR_6 (0x1 << EPI_ADDRMAP_ERADR_SHIFT)
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# define EPI_ADDRMAP_ERADR_8 (0x2 << EPI_ADDRMAP_ERADR_SHIFT)
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#define EPI_ADDRMAP_ERSZ_SHIFT 2 /* Bits 3-2: External RAM Size */
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#define EPI_ADDRMAP_ERSZ_MASK (0x3 << EPI_ADDRMAP_ERSZ_SHIFT)
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# define EPI_ADDRMAP_ERSZ_256B (0x0 << EPI_ADDRMAP_ERSZ_SHIFT)
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# define EPI_ADDRMAP_ERSZ_64KB (0x1 << EPI_ADDRMAP_ERSZ_SHIFT)
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# define EPI_ADDRMAP_ERSZ_16MB (0x2 << EPI_ADDRMAP_ERSZ_SHIFT)
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# define EPI_ADDRMAP_ERSZ_512MB (0x3 << EPI_ADDRMAP_ERSZ_SHIFT)
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/* EPI Status (EPISTAT), offset 0x060 */
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#define EPI_STAT_INITSEQ_SHIFT 6 /* Bits 6: Initialization Sequence */
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#define EPI_STAT_INITSEQ_MASK (0x1 << EPI_STAT_INITSEQ_SHIFT)
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/* EPI SDRAM Configuration (EPISDRAMCFG), offset 0x010 */
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#define EPI_SDRAMCFG_SIZE_SHIFT 0 /* Bits 1-0: Size of SDRAM */
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#define EPI_SDRAMCFG_SIZE_MASK (3 << EPI_SDRAMCFG_SIZE_SHIFT)
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# define EPI_SDRAMCFG_SIZE_8MB (0x0 << EPI_SDRAMCFG_SIZE_SHIFT)
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# define EPI_SDRAMCFG_SIZE_16MB (0x1 << EPI_SDRAMCFG_SIZE_SHIFT)
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# define EPI_SDRAMCFG_SIZE_32MB (0x2 << EPI_SDRAMCFG_SIZE_SHIFT)
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# define EPI_SDRAMCFG_SIZE_64MB (0x3 << EPI_SDRAMCFG_SIZE_SHIFT)
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#define EPI_SDRAMCFG_RFSH_SHIFT 16 /* Bits 26-16: Refresh Counter */
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#define EPI_SDRAMCFG_RFSH_MASK (0x7FF << EPI_SDRAMCFG_RFSH_SHIFT)
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# define EPI_SDRAMCFG_RFSH(n) ((n) << EPI_SDRAMCFG_RFSH_SHIFT)
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#define EPI_SDRAMCFG_FREQ_SHIFT 30 /* EPI Frequency Range */
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#define EPI_SDRAMCFG_FREQ_MASK (3 << EPI_SDRAMCFG_FREQ_SHIFT)
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# define EPI_SDRAMCFG_FREQ_0_15MHZ (0x0 << EPI_SDRAMCFG_FREQ_SHIFT)
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# define EPI_SDRAMCFG_FREQ_15_30MHZ (0x1 << EPI_SDRAMCFG_FREQ_SHIFT)
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# define EPI_SDRAMCFG_FREQ_30_50MHZ (0x2 << EPI_SDRAMCFG_FREQ_SHIFT)
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# define EPI_SDRAMCFG_FREQ_50_100MHZ (0x3 << EPI_SDRAMCFG_FREQ_SHIFT)
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/* EPI Main Baud Rate (EPIBAUD), offset 0x004 */
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#define EPI_BAUD_COUNT0_SHIFT 0
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#define EPI_BAUD_COUNT0_MASK (0xFFFF << EPI_BAUD_COUNT0_SHIFT)
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# define EPI_BAUD_COUNT0(n) ((n) << EPI_BAUD_COUNT0_SHIFT)
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#endif /* __ARCH_ARM_SRC_LM3S_LM3S_EPI_H */
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Executable
+125
@@ -0,0 +1,125 @@
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/************************************************************************************
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* arch/arm/src/lm3s/lm3s_timer.h
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*
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* Copyright (C) 2012 Max Nekludov. All rights reserved.
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* Author: Max Nekludov <macscomp@gmail.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_LM3S_LM3S_TIMER_H
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#define __ARCH_ARM_SRC_LM3S_LM3S_TIMER_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Timer register offsets ***********************************************************/
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#define TIMER_GPTMCFG_OFFSET 0x000
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#define TIMER_GPTMTAMR_OFFSET 0x004
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#define TIMER_GPTMCTL_OFFSET 0x00C
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#define TIMER_GPTMIMR_OFFSET 0x018
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#define TIMER_GPTMRIS_OFFSET 0x01C
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#define TIMER_GPTMICR_OFFSET 0x024
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#define TIMER_GPTMTAILR_OFFSET 0x028
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#define TIMER_GPTMTAR_OFFSET 0x048
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/* SSI register addresses ***********************************************************/
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#define LM3S_TIMER_BASE(n) (LM3S_TIMER0_BASE + (n)*0x01000)
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#define LM3S_TIMER_GPTMCFG(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMCFG_OFFSET)
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#define LM3S_TIMER_GPTMTAMR(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMTAMR_OFFSET)
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#define LM3S_TIMER_GPTMCTL(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMCTL_OFFSET)
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#define LM3S_TIMER_GPTMIMR(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMIMR_OFFSET)
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#define LM3S_TIMER_GPTMRIS(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMRIS_OFFSET)
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#define LM3S_TIMER_GPTMICR(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMICR_OFFSET)
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#define LM3S_TIMER_GPTMTAILR(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMTAILR_OFFSET)
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#define LM3S_TIMER_GPTMTAR(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMTAR_OFFSET)
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/* SSI register bit defitiions ******************************************************/
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/* GPTM Configuration (GPTMCFG), offset 0x000 */
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#define TIMER_GPTMCFG_CFG_SHIFT 0 /* Bits 2-0: GPTM Configuration */
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#define TIMER_GPTM_CFG_MASK (0x07 << TIMER_GPTMCFG_CFG_SHIFT)
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#define TIMER_GPTMCFG_CFG_32 (0 << TIMER_GPTMCFG_CFG_SHIFT) /* 32-bit timer configuration */
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#define TIMER_GPTMCFG_CFG_RTC (1 << TIMER_GPTMCFG_CFG_SHIFT) /* 32-bit real-time clock (RTC) counter configuration */
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#define TIMER_GPTMCFG_CFG_16 (1 << TIMER_GPTMCFG_CFG_SHIFT) /* 16-bit timer configuration */
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/* GPTM Timer A Mode (GPTMTAMR), offset 0x004 */
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#define TIMER_GPTMTAMR_TAMR_SHIFT 0 /* Bits 1-0: GPTM Timer A Mode */
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#define TIMER_GPTMTAMR_TAMR_MASK (0x03 << TIMER_GPTMTAMR_TAMR_SHIFT)
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#define TIMER_GPTMTAMR_TAMR_ONESHOT (1 << TIMER_GPTMTAMR_TAMR_SHIFT) /* One-Shot Timer mode */
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#define TIMER_GPTMTAMR_TAMR_PERIODIC (2 << TIMER_GPTMTAMR_TAMR_SHIFT) /* Periodic Timer mode */
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#define TIMER_GPTMTAMR_TAMR_CAPTURE (3 << TIMER_GPTMTAMR_TAMR_SHIFT) /* Capture mode */
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#define TIMER_GPTMTAMR_TACMR_SHIFT 2 /* Bits 2: GPTM Timer A Capture Mode */
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#define TIMER_GPTMTAMR_TACMR_MASK (0x01 << TIMER_GPTMTAMR_TACMR_SHIFT)
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#define TIMER_GPTMTAMR_TACMR_EDGECOUNT (0 << TIMER_GPTMTAMR_TACMR_SHIFT) /* Edge-Count mode */
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#define TIMER_GPTMTAMR_TACMR_EDGETIME (1 << TIMER_GPTMTAMR_TACMR_SHIFT) /* Edge-Time mode */
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#define TIMER_GPTMTAMR_TAAMS_SHIFT 3 /* Bits 3: GPTM Timer A Alternate Mode Select */
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#define TIMER_GPTMTAMR_TAAMS_MASK (0x01 << TIMER_GPTMTAMR_TAAMS_SHIFT)
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#define TIMER_GPTMTAMR_TAAMS_CAPTURE (0 << TIMER_GPTMTAMR_TAAMS_SHIFT) /* Capture mode is enabled */
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#define TIMER_GPTMTAMR_TAAMS_PWM (1 << TIMER_GPTMTAMR_TAAMS_SHIFT) /* PWM mode is enabled */
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#define TIMER_GPTMTAMR_TACDIR_SHIFT 4 /* Bits 4: GPTM Timer A Count Direction */
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#define TIMER_GPTMTAMR_TACDIR_MASK (0x01 << TIMER_GPTMTAMR_TACDIR_SHIFT)
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#define TIMER_GPTMTAMR_TACDIR_DOWN (0 << TIMER_GPTMTAMR_TACDIR_SHIFT) /* The timer counts down */
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#define TIMER_GPTMTAMR_TACDIR_UP (1 << TIMER_GPTMTAMR_TACDIR_SHIFT) /* When in one-shot or periodic mode, the timer counts up */
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#define TIMER_GPTMTAMR_TAMIE_SHIFT 5 /* Bits 5: GPTM Timer A Match Interrupt Enable */
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#define TIMER_GPTMTAMR_TAMIE_MASK (0x01 << TIMER_GPTMTAMR_TAMIE_SHIFT)
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/* GPTM Control (GPTMCTL), offset 0x00C */
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#define TIMER_GPTMCTL_TAEN_SHIFT 0 /* Bits 0: GPTM Timer A Enable */
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#define TIMER_GPTMCTL_TAEN_MASK (0x01 << TIMER_GPTMCTL_TAEN_SHIFT)
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#define TIMER_GPTMCTL_TASTALL_SHIFT 1 /* Bits 1: GPTM Timer A Stall Enable */
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#define TIMER_GPTMCTL_TASTALL_MASK (0x01 << TIMER_GPTMCTL_TASTALL_SHIFT)
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/* GPTM Interrupt Mask (GPTMIMR), offset 0x018 */
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#define TIMER_GPTMIMR_TATOIM_SHIFT 0 /* Bits 0: GPTM Timer A Time-Out Interrupt Mask */
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#define TIMER_GPTMIMR_TATOIM_MASK (0x01 << TIMER_GPTMIMR_TATOIM_SHIFT)
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/* GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C */
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#define TIMER_GPTMRIS_TATORIS_SHIFT 0 /* Bits 0: GPTM Timer A Time-Out Raw Interrupt */
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#define TIMER_GPTMRIS_TATORIS_MASK (0x01 << TIMER_GPTMRIS_TATORIS_SHIFT)
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/* GPTM Interrupt Clear (GPTMICR), offset 0x024 */
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#define TIMER_GPTMICR_TATOCINT_SHIFT 0 /* Bits 0: GPTM Timer A Time-Out Raw Interrupt Clear*/
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#define TIMER_GPTMICR_TATOCINT_MASK (0x01 << TIMER_GPTMICR_TATOCINT_SHIFT)
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#endif /* __ARCH_ARM_SRC_LM3S_LM3S_TIMER_H */
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@@ -2,8 +2,8 @@
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* arch/arm/src/stm32/stm32_irq.c
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* arch/arm/src/chip/stm32_irq.c
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*
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* Copyright (C) 2009-2011 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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* Copyright (C) 2009-2012 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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@@ -273,6 +273,9 @@ static int stm32_irqinfo(int irq, uint32_t *regaddr, uint32_t *bit)
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void up_irqinitialize(void)
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{
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uint32_t regaddr;
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int num_priority_registers;
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/* Disable all interrupts */
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putreg32(0, NVIC_IRQ0_31_ENABLE);
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@@ -294,23 +297,25 @@ void up_irqinitialize(void)
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putreg32(DEFPRIORITY32, NVIC_SYSH8_11_PRIORITY);
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putreg32(DEFPRIORITY32, NVIC_SYSH12_15_PRIORITY);
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putreg32(DEFPRIORITY32, NVIC_IRQ0_3_PRIORITY);
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putreg32(DEFPRIORITY32, NVIC_IRQ4_7_PRIORITY);
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putreg32(DEFPRIORITY32, NVIC_IRQ8_11_PRIORITY);
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putreg32(DEFPRIORITY32, NVIC_IRQ12_15_PRIORITY);
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putreg32(DEFPRIORITY32, NVIC_IRQ16_19_PRIORITY);
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putreg32(DEFPRIORITY32, NVIC_IRQ20_23_PRIORITY);
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putreg32(DEFPRIORITY32, NVIC_IRQ24_27_PRIORITY);
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putreg32(DEFPRIORITY32, NVIC_IRQ28_31_PRIORITY);
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putreg32(DEFPRIORITY32, NVIC_IRQ32_35_PRIORITY);
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putreg32(DEFPRIORITY32, NVIC_IRQ36_39_PRIORITY);
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putreg32(DEFPRIORITY32, NVIC_IRQ40_43_PRIORITY);
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putreg32(DEFPRIORITY32, NVIC_IRQ44_47_PRIORITY);
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putreg32(DEFPRIORITY32, NVIC_IRQ48_51_PRIORITY);
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putreg32(DEFPRIORITY32, NVIC_IRQ52_55_PRIORITY);
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putreg32(DEFPRIORITY32, NVIC_IRQ56_59_PRIORITY);
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putreg32(DEFPRIORITY32, NVIC_IRQ60_63_PRIORITY);
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putreg32(DEFPRIORITY32, NVIC_IRQ64_67_PRIORITY);
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/* The NVIC ICTR register (bits 0-4) holds the number of of interrupt
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* lines that the NVIC supports:
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*
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* 0 -> 32 interrupt lines, 8 priority registers
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* 1 -> 64 " " " ", 16 priority registers
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* 2 -> 96 " " " ", 32 priority registers
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* ...
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*/
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num_priority_registers = (getreg32(NVIC_ICTR) + 1) * 8;
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/* Now set all of the interrupt lines to the default priority */
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regaddr = NVIC_IRQ0_3_PRIORITY;
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while (num_priority_registers--)
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{
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putreg32(DEFPRIORITY32, regaddr);
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regaddr += 4;
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}
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/* currents_regs is non-NULL only while processing an interrupt */
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