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Initialize global mutext/sem by NXMUTEX_INITIALIZER and SEM_INITIALIZER

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Signed-off-by: anjiahao <anjiahao@xiaomi.com>
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
This commit is contained in:
anjiahao
2022-09-06 14:18:45 +08:00
committed by Masayuki Ishikawa
parent 9f029194e1
commit d07792a343
225 changed files with 1930 additions and 2163 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm/src/cxd56xx/cxd56_adc.c
+11 -12
View File
@@ -223,6 +223,7 @@ static struct cxd56adc_dev_s g_lpadc0priv =
.wm = NULL,
.filter = NULL,
.notify = NULL,
.lock = NXMUTEX_INITIALIZER,
.crefs = 0,
};
#endif
@@ -239,6 +240,7 @@ static struct cxd56adc_dev_s g_lpadc1priv =
.wm = NULL,
.filter = NULL,
.notify = NULL,
.lock = NXMUTEX_INITIALIZER,
.crefs = 0,
};
#endif
@@ -255,6 +257,7 @@ static struct cxd56adc_dev_s g_lpadc2priv =
.wm = NULL,
.filter = NULL,
.notify = NULL,
.lock = NXMUTEX_INITIALIZER,
.crefs = 0,
};
#endif
@@ -271,6 +274,7 @@ static struct cxd56adc_dev_s g_lpadc3priv =
.wm = NULL,
.filter = NULL,
.notify = NULL,
.lock = NXMUTEX_INITIALIZER,
.crefs = 0,
};
#endif
@@ -287,6 +291,7 @@ static struct cxd56adc_dev_s g_hpadc0priv =
.wm = NULL,
.filter = NULL,
.notify = NULL,
.lock = NXMUTEX_INITIALIZER,
.crefs = 0,
};
#endif
@@ -303,6 +308,7 @@ static struct cxd56adc_dev_s g_hpadc1priv =
.wm = NULL,
.filter = NULL,
.notify = NULL,
.lock = NXMUTEX_INITIALIZER,
.crefs = 0,
};
#endif
@@ -1107,9 +1113,8 @@ int cxd56_adcinitialize(void)
aerr("Failed to register driver(lpadc0): %d\n", ret);
return ret;
}
nxmutex_init(&g_lpadc0priv.lock);
#endif
#if defined (CONFIG_CXD56_LPADC1) || defined (CONFIG_CXD56_LPADC0_1) || defined (CONFIG_CXD56_LPADC_ALL)
ret = register_driver("/dev/lpadc1", &g_adcops, 0666, &g_lpadc1priv);
if (ret < 0)
@@ -1117,9 +1122,8 @@ int cxd56_adcinitialize(void)
aerr("Failed to register driver(lpadc1): %d\n", ret);
return ret;
}
nxmutex_init(&g_lpadc1priv.lock);
#endif
#if defined (CONFIG_CXD56_LPADC2) || defined (CONFIG_CXD56_LPADC_ALL)
ret = register_driver("/dev/lpadc2", &g_adcops, 0666, &g_lpadc2priv);
if (ret < 0)
@@ -1127,9 +1131,8 @@ int cxd56_adcinitialize(void)
aerr("Failed to register driver(lpadc2): %d\n", ret);
return ret;
}
nxmutex_init(&g_lpadc2priv.lock);
#endif
#if defined (CONFIG_CXD56_LPADC3) || defined (CONFIG_CXD56_LPADC_ALL)
ret = register_driver("/dev/lpadc3", &g_adcops, 0666, &g_lpadc3priv);
if (ret < 0)
@@ -1137,9 +1140,8 @@ int cxd56_adcinitialize(void)
aerr("Failed to register driver(lpadc3): %d\n", ret);
return ret;
}
nxmutex_init(&g_lpadc3priv.lock);
#endif
#ifdef CONFIG_CXD56_HPADC0
ret = register_driver("/dev/hpadc0", &g_adcops, 0666, &g_hpadc0priv);
if (ret < 0)
@@ -1147,9 +1149,8 @@ int cxd56_adcinitialize(void)
aerr("Failed to register driver(hpadc0): %d\n", ret);
return ret;
}
nxmutex_init(&g_hpadc0priv.lock);
#endif
#ifdef CONFIG_CXD56_HPADC1
ret = register_driver("/dev/hpadc1", &g_adcops, 0666, &g_hpadc1priv);
if (ret < 0)
@@ -1157,8 +1158,6 @@ int cxd56_adcinitialize(void)
aerr("Failed to register driver(hpadc1): %d\n", ret);
return ret;
}
nxmutex_init(&g_hpadc1priv.lock);
#endif
return ret;
arch/arm/src/cxd56xx/cxd56_charger.c
+4 -5
View File
@@ -103,7 +103,10 @@ static const struct file_operations g_chargerops =
#endif
};
static struct charger_dev_s g_chargerdev;
static struct charger_dev_s g_chargerdev =
{
.batlock = NXMUTEX_INITIALIZER,
};
/****************************************************************************
* Private Functions
@@ -621,10 +624,6 @@ int cxd56_charger_initialize(const char *devpath)
struct charger_dev_s *priv = &g_chargerdev;
int ret;
/* Initialize the CXD5247 device structure */
nxmutex_init(&priv->batlock);
/* Register battery driver */
ret = register_driver(devpath, &g_chargerops, 0666, priv);
arch/arm/src/cxd56xx/cxd56_dmac.c
+1 -3
View File
@@ -290,7 +290,7 @@ struct dma_channel_s
/* This is the array of all DMA channels */
static struct dma_channel_s g_dmach[NCHANNELS];
static mutex_t g_dmalock;
static mutex_t g_dmalock = NXMUTEX_INITIALIZER;
static int dma_init(int ch);
static int dma_uninit(int ch);
@@ -726,8 +726,6 @@ void weak_function arm_dma_initialize(void)
g_dmach[i].chan = i;
up_enable_irq(irq_map[i]);
}
nxmutex_init(&g_dmalock);
}
/****************************************************************************
arch/arm/src/cxd56xx/cxd56_emmc.c
+5 -6
View File
@@ -137,8 +137,11 @@ static const struct block_operations g_bops =
NULL /* ioctl */
};
static sem_t g_waitsem;
struct cxd56_emmc_state_s g_emmcdev;
static sem_t g_waitsem = SEM_INITIALIZER(0);
struct cxd56_emmc_state_s g_emmcdev =
{
.lock = NXMUTEX_INITIALIZER,
};
/****************************************************************************
* Private Functions
@@ -939,10 +942,6 @@ int cxd56_emmcinitialize(void)
priv = &g_emmcdev;
memset(priv, 0, sizeof(struct cxd56_emmc_state_s));
nxmutex_init(&priv->lock);
nxsem_init(&g_waitsem, 0, 0);
ret = emmc_hwinitialize();
if (ret != OK)
{
arch/arm/src/cxd56xx/cxd56_farapi.c
+2 -5
View File
@@ -113,8 +113,8 @@ extern struct modulelist_s _image_modlist_base[];
* Private Data
****************************************************************************/
static sem_t g_farwait;
static mutex_t g_farlock;
static sem_t g_farwait = SEM_INITIALIZER(0);
static mutex_t g_farlock = NXMUTEX_INITIALIZER;
static struct pm_cpu_wakelock_s g_wlock =
{
.count = 0,
@@ -288,10 +288,7 @@ void cxd56_farapiinitialize(void)
PANIC();
# endif
}
#endif
nxmutex_init(&g_farlock);
nxsem_init(&g_farwait, 0, 0);
cxd56_iccinit(CXD56_PROTO_MBX);
cxd56_iccinit(CXD56_PROTO_FLG);
arch/arm/src/cxd56xx/cxd56_gauge.c
+4 -5
View File
@@ -88,7 +88,10 @@ static const struct file_operations g_gaugeops =
#endif
};
static struct bat_gauge_dev_s g_gaugedev;
static struct bat_gauge_dev_s g_gaugedev =
{
.batlock = NXMUTEX_INITIALIZER,
};
/****************************************************************************
* Private Functions
@@ -345,10 +348,6 @@ int cxd56_gauge_initialize(const char *devpath)
struct bat_gauge_dev_s *priv = &g_gaugedev;
int ret;
/* Initialize the CXD5247 device structure */
nxmutex_init(&priv->batlock);
/* Register battery driver */
ret = register_driver(devpath, &g_gaugeops, 0666, priv);
arch/arm/src/cxd56xx/cxd56_ge2d.c
+2 -9
View File
@@ -64,8 +64,8 @@ static const struct file_operations g_ge2dfops =
.ioctl = ge2d_ioctl
};
static sem_t g_wait;
static mutex_t g_lock;
static sem_t g_wait = SEM_INITIALIZER(0);
static mutex_t g_lock = NXMUTEX_INITIALIZER;
/****************************************************************************
* Private Functions
@@ -184,9 +184,6 @@ int cxd56_ge2dinitialize(const char *devname)
{
int ret;
nxmutex_init(&g_lock);
nxsem_init(&g_wait, 0, 0);
ret = register_driver(devname, &g_ge2dfops, 0666, NULL);
if (ret != 0)
{
@@ -215,9 +212,5 @@ void cxd56_ge2duninitialize(const char *devname)
irq_detach(CXD56_IRQ_GE2D);
cxd56_img_ge2d_clock_disable();
nxmutex_destroy(&g_lock);
nxsem_destroy(&g_wait);
unregister_driver(devname);
}
arch/arm/src/cxd56xx/cxd56_hostif.c
+4 -5
View File
@@ -130,7 +130,10 @@ static int hif_unlink(struct inode *inode);
/* Host interface driver */
static struct cxd56_hifdrv_s g_hifdrv;
static struct cxd56_hifdrv_s g_hifdrv =
{
.sync = SEM_INITIALIZER(0),
};
/* Host interface operations */
@@ -379,8 +382,6 @@ static int hif_initialize(struct hostif_buff_s *buffer)
DEBUGASSERT(buffer);
memset(drv, 0, sizeof(struct cxd56_hifdrv_s));
/* Get the number of devices */
for (num = 0; num < MAX_BUFFER_NUM; num++)
@@ -441,8 +442,6 @@ static int hif_initialize(struct hostif_buff_s *buffer)
cxd56_iccinit(CXD56_PROTO_HOSTIF);
nxsem_init(&drv->sync, 0, 0);
ret = cxd56_iccregisterhandler(CXD56_PROTO_HOSTIF, hif_rxhandler, NULL);
return ret;
arch/arm/src/cxd56xx/cxd56_powermgr.c
+4 -29
View File
@@ -166,10 +166,10 @@ static int cxd56_pmmsghandler(int cpuid, int protoid, uint32_t pdata,
static struct cxd56_pm_target_id_s g_target_id_table;
static struct file g_queuedesc;
static sem_t g_bootsync;
static mutex_t g_regcblock;
static mutex_t g_freqlock;
static sem_t g_freqlockwait;
static sem_t g_bootsync = SEM_INITIALIZER(0);
static mutex_t g_regcblock = NXMUTEX_INITIALIZER;
static mutex_t g_freqlock = NXMUTEX_INITIALIZER;
static sem_t g_freqlockwait = SEM_INITIALIZER(0);
static dq_queue_t g_cbqueue;
static sq_queue_t g_freqlockqueue;
static sq_queue_t g_wakelockqueue;
@@ -818,36 +818,11 @@ int cxd56_pm_hotsleep(int idletime)
int cxd56_pm_initialize(void)
{
int taskid;
int ret;
dq_init(&g_cbqueue);
sq_init(&g_freqlockqueue);
sq_init(&g_wakelockqueue);
ret = nxmutex_init(&g_regcblock);
if (ret < 0)
{
return ret;
}
ret = nxmutex_init(&g_freqlock);
if (ret < 0)
{
return ret;
}
ret = nxsem_init(&g_freqlockwait, 0, 0);
if (ret < 0)
{
return ret;
}
ret = nxsem_init(&g_bootsync, 0, 0);
if (ret < 0)
{
return ret;
}
taskid = task_create("cxd56_pm_task", CXD56_PM_TASK_PRIO,
CXD56_PM_TASK_STACKSIZE, cxd56_pm_maintask,
NULL);
arch/arm/src/cxd56xx/cxd56_scu.c
+11 -25
View File
@@ -315,7 +315,17 @@ static void seq_handleisopdoneintr(struct cxd56_scudev_s *priv,
* Private Data
****************************************************************************/
struct cxd56_scudev_s g_scudev;
struct cxd56_scudev_s g_scudev =
{
.syncwait = SEM_INITIALIZER(0),
.synclock = NXMUTEX_INITIALIZER,
.oneshotwait =
{
SEM_INITIALIZER(0),
SEM_INITIALIZER(0),
SEM_INITIALIZER(0),
},
};
/****************************************************************************
* Public Data
@@ -3417,23 +3427,10 @@ void seq_close(struct seq_s *seq)
void scu_initialize(void)
{
struct cxd56_scudev_s *priv = &g_scudev;
int i;
#ifdef CONFIG_CXD56_UDMAC
cxd56_udmainitialize();
#endif
memset(priv, 0, sizeof(struct cxd56_scudev_s));
nxmutex_init(&priv->synclock);
nxsem_init(&priv->syncwait, 0, 0);
for (i = 0; i < 3; i++)
{
nxsem_init(&priv->oneshotwait[i], 0, 0);
}
scufifo_initialize();
/**
@@ -3486,9 +3483,6 @@ void scu_initialize(void)
void scu_uninitialize(void)
{
struct cxd56_scudev_s *priv = &g_scudev;
int i;
/* Request don't sleep */
seq_inhibitrequest(REQ_SLEEP, true);
@@ -3496,12 +3490,4 @@ void scu_uninitialize(void)
up_disable_irq(CXD56_IRQ_SCU_3);
cxd56_scuseq_clock_disable();
nxsem_destroy(&priv->syncwait);
nxmutex_destroy(&priv->synclock);
for (i = 0; i < 3; i++)
{
nxsem_destroy(&priv->oneshotwait[i]);
}
}
arch/arm/src/cxd56xx/cxd56_sdhci.c
+1 -4
View File
@@ -464,6 +464,7 @@ struct cxd56_sdiodev_s g_sdhcdev =
.dmasendsetup = cxd56_sdio_sendsetup,
#endif
},
.waitsem = SEM_INITIALIZER(0),
};
/* Register logging support */
@@ -1315,10 +1316,6 @@ static void cxd56_sdio_sdhci_reset(struct sdio_dev_s *dev)
/* Initialize the SDHC slot structure data structure */
/* Initialize semaphores */
nxsem_init(&priv->waitsem, 0, 0);
/* The next phase of the hardware reset would be to set the SYSCTRL INITA
* bit to send 80 clock ticks for card to power up and then reset the card
* with CMD0. This is done elsewhere.
arch/arm/src/cxd56xx/cxd56_spi.c
+17 -21
View File
@@ -77,7 +77,6 @@ struct cxd56_spidev_s
uint8_t port; /* Port number */
int initialized; /* Initialized flag */
#ifdef CONFIG_CXD56_DMAC
bool dmaenable; /* Use DMA or not */
DMA_HANDLE rxdmach; /* RX DMA channel handle */
DMA_HANDLE txdmach; /* TX DMA channel handle */
sem_t dmasem; /* Wait for DMA to complete */
@@ -188,6 +187,10 @@ static struct cxd56_spidev_s g_spi4dev =
.initialized = 0,
#ifdef CONFIG_CXD56_SPI_INTERRUPTS
.spiirq = CXD56_IRQ_IMG_SPI,
#endif
.lock = NXMUTEX_INITIALIZER,
#ifdef CONFIG_CXD56_DMAC
.dmasem = SEM_INITIALIZER(0),
#endif
};
@@ -231,6 +234,10 @@ static struct cxd56_spidev_s g_spi5dev =
.initialized = 0,
#ifdef CONFIG_CXD56_SPI_INTERRUPTS
.spiirq = CXD56_IRQ_IMG_WSPI,
#endif
.lock = NXMUTEX_INITIALIZER,
#ifdef CONFIG_CXD56_DMAC
.dmasem = SEM_INITIALIZER(0),
#endif
};
#endif
@@ -273,6 +280,10 @@ static struct cxd56_spidev_s g_spi0dev =
.initialized = 0,
#ifdef CONFIG_CXD56_SPI_INTERRUPTS
.spiirq = CXD56_IRQ_SPIM,
#endif
.lock = NXMUTEX_INITIALIZER,
#ifdef CONFIG_CXD56_DMAC
.dmasem = SEM_INITIALIZER(0),
#endif
};
#endif
@@ -315,6 +326,10 @@ static struct cxd56_spidev_s g_spi3dev =
.initialized = 0,
#ifdef CONFIG_CXD56_SPI_INTERRUPTS
.spiirq = CXD56_IRQ_SCU_SPI,
#endif
.lock = NXMUTEX_INITIALIZER,
#ifdef CONFIG_CXD56_DMAC
.dmasem = SEM_INITIALIZER(0),
#endif
};
#endif
@@ -863,15 +878,13 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
void *rxbuffer, size_t nwords)
{
#ifdef CONFIG_CXD56_DMAC
struct cxd56_spidev_s *priv = (struct cxd56_spidev_s *)dev;
#ifdef CONFIG_CXD56_SPI_DMATHRESHOLD
size_t dmath = CONFIG_CXD56_SPI_DMATHRESHOLD;
#else
size_t dmath = 0;
#endif
if (priv->dmaenable && dmath < nwords)
if (dmath < nwords)
{
spi_dmaexchange(dev, txbuffer, rxbuffer, nwords);
}
@@ -1204,7 +1217,6 @@ struct spi_dev_s *cxd56_spibus_initialize(int port)
/* DMA settings */
#ifdef CONFIG_CXD56_DMAC
priv->dmaenable = false;
priv->txdmach = NULL;
priv->rxdmach = NULL;
#endif
@@ -1244,10 +1256,6 @@ struct spi_dev_s *cxd56_spibus_initialize(int port)
spi_setfrequency((struct spi_dev_s *)priv, 400000);
/* Initialize the SPI mutex that enforces mutually exclusive access */
nxmutex_init(&priv->lock);
#ifdef CONFIG_CXD56_SPI3_SCUSEQ
/* Enable the SPI, but not enable port 3 when SCU support enabled.
* Because this enabler will be controlled by SCU.
@@ -1328,12 +1336,6 @@ void cxd56_spi_dmaconfig(int port, int chtype, DMA_HANDLE handle,
priv->txdmach = handle;
memcpy(&priv->txconfig, conf, sizeof(dma_config_t));
if (!priv->dmaenable)
{
nxsem_init(&priv->dmasem, 0, 0);
priv->dmaenable = true;
}
}
else if ((chtype == CXD56_SPI_DMAC_CHTYPE_RX) && (!priv->rxdmach))
{
@@ -1341,12 +1343,6 @@ void cxd56_spi_dmaconfig(int port, int chtype, DMA_HANDLE handle,
priv->rxdmach = handle;
memcpy(&priv->rxconfig, conf, sizeof(dma_config_t));
if (!priv->dmaenable)
{
nxsem_init(&priv->dmasem, 0, 0);
priv->dmaenable = true;
}
}
}
}
arch/arm/src/cxd56xx/cxd56_sysctl.c
+2 -7
View File
@@ -66,8 +66,8 @@ static int sysctl_rxhandler(int cpuid, int protoid,
* Private Data
****************************************************************************/
static mutex_t g_lock;
static sem_t g_sync;
static mutex_t g_lock = NXMUTEX_INITIALIZER;
static sem_t g_sync = SEM_INITIALIZER(0);
static int g_errcode = 0;
static const struct file_operations g_sysctlfops =
@@ -159,11 +159,6 @@ int cxd56_sysctlcmd(uint8_t id, uint32_t data)
void cxd56_sysctlinitialize(void)
{
cxd56_iccinit(CXD56_PROTO_SYSCTL);
nxmutex_init(&g_lock);
nxsem_init(&g_sync, 0, 0);
cxd56_iccregisterhandler(CXD56_PROTO_SYSCTL, sysctl_rxhandler, NULL);
register_driver("/dev/sysctl", &g_sysctlfops, 0666, NULL);
}
arch/arm/src/cxd56xx/cxd56_uart0.c
+1 -4
View File
@@ -97,7 +97,7 @@ static const struct file_operations g_uart0fops =
.write = uart0_write
};
static mutex_t g_lock;
static mutex_t g_lock = NXMUTEX_INITIALIZER;
/****************************************************************************
* Private Functions
@@ -233,8 +233,6 @@ int cxd56_uart0initialize(const char *devname)
{
int ret;
nxmutex_init(&g_lock);
ret = register_driver(devname, &g_uart0fops, 0666, NULL);
if (ret != 0)
{
@@ -251,7 +249,6 @@ int cxd56_uart0initialize(const char *devname)
void cxd56_uart0uninitialize(const char *devname)
{
unregister_driver(devname);
nxmutex_destroy(&g_lock);
}
#endif /* CONFIG_CXD56_UART0 */
arch/arm/src/cxd56xx/cxd56_udmac.c
+5 -4
View File
@@ -78,7 +78,11 @@ struct dma_controller_s
/* This is the overall state of the DMA controller */
static struct dma_controller_s g_dmac;
static struct dma_controller_s g_dmac =
{
.lock = NXMUTEX_INITIALIZER,
.chansem = SEM_INITIALIZER(CXD56_DMA_NCHANNELS),
};
/* This is the array of all DMA channels */
@@ -239,9 +243,6 @@ void cxd56_udmainitialize(void)
/* Initialize the channel list */
nxmutex_init(&g_dmac.lock);
nxsem_init(&g_dmac.chansem, 0, CXD56_DMA_NCHANNELS);
for (i = 0; i < CXD56_DMA_NCHANNELS; i++)
{
g_dmach[i].chan = i;
arch/arm/src/efm32/efm32_dma.c
+5 -4
View File
@@ -78,7 +78,11 @@ struct dma_controller_s
/* This is the overall state of the DMA controller */
static struct dma_controller_s g_dmac;
static struct dma_controller_s g_dmac =
{
.lock = NXMUTEX_INITIALIZER,
.chansem = SEM_INITIALIZER(EFM32_DMA_NCHANNELS),
};
/* This is the array of all DMA channels */
@@ -266,9 +270,6 @@ void weak_function arm_dma_initialize(void)
/* Initialize the channel list */
nxmutex_init(&g_dmac.lock);
nxsem_init(&g_dmac.chansem, 0, EFM32_DMA_NCHANNELS);
for (i = 0; i < EFM32_DMA_NCHANNELS; i++)
{
g_dmach[i].chan = i;
arch/arm/src/efm32/efm32_spi.c
+27 -13
View File
@@ -226,7 +226,15 @@ static const struct spi_ops_s g_spiops =
#ifdef CONFIG_EFM32_USART0_ISSPI
/* Support for SPI on USART0 */
static struct efm32_spidev_s g_spi0dev;
static struct efm32_spidev_s g_spi0dev =
{
#ifdef CONFIG_EFM32_SPI_DMA
.rxdmasem = SEM_INITIALIZER(0),
.txdmasem = SEM_INITIALIZER(0),
#endif
.lock = NXMUTEX_INITIALIZER,
};
static const struct efm32_spiconfig_s g_spi0config =
{
.base = EFM32_USART0_BASE,
@@ -249,7 +257,15 @@ static const struct efm32_spiconfig_s g_spi0config =
#ifdef CONFIG_EFM32_USART1_ISSPI
/* Support for SPI on USART1 */
static struct efm32_spidev_s g_spi1dev;
static struct efm32_spidev_s g_spi1dev =
{
#ifdef CONFIG_EFM32_SPI_DMA
.rxdmasem = SEM_INITIALIZER(0),
.txdmasem = SEM_INITIALIZER(0),
#endif
.lock = NXMUTEX_INITIALIZER,
};
static const struct efm32_spiconfig_s g_spi1config =
{
.base = EFM32_USART1_BASE,
@@ -272,7 +288,15 @@ static const struct efm32_spiconfig_s g_spi1config =
#ifdef CONFIG_EFM32_USART2_ISSPI
/* Support for SPI on USART2 */
static struct efm32_spidev_s g_spi2dev;
static struct efm32_spidev_s g_spi2dev =
{
#ifdef CONFIG_EFM32_SPI_DMA
.rxdmasem = SEM_INITIALIZER(0),
.txdmasem = SEM_INITIALIZER(0),
#endif
.lock = NXMUTEX_INITIALIZER,
};
static const struct efm32_spiconfig_s g_spi2config =
{
.base = EFM32_USART2_BASE,
@@ -1577,10 +1601,6 @@ static int spi_portinitialize(struct efm32_spidev_s *priv)
spi_putreg(config, EFM32_USART_CMD_OFFSET, USART_CMD_MASTEREN);
/* Initialize the SPI mutex that enforces mutually exclusive access */
nxmutex_init(&priv->lock);
#ifdef CONFIG_EFM32_SPI_DMA
/* Allocate two DMA channels... one for the RX and one for the TX side of
* the transfer.
@@ -1601,12 +1621,6 @@ static int spi_portinitialize(struct efm32_spidev_s *priv)
port);
goto errout_with_rxdmach;
}
/* Initialized semaphores used to wait for DMA completion */
nxsem_init(&priv->rxdmasem, 0, 0);
nxsem_init(&priv->txdmasem, 0, 0);
#endif
/* Enable SPI */
arch/arm/src/efm32/efm32_usbhost.c
+5 -6
View File
@@ -484,7 +484,11 @@ static inline int efm32_hw_initialize(struct efm32_usbhost_s *priv);
* single global instance.
*/
static struct efm32_usbhost_s g_usbhost;
static struct efm32_usbhost_s g_usbhost =
{
.lock = NXMUTEX_INITIALIZER,
.pscsem = SEM_INITIALIZER(0),
};
/* This is the connection/enumeration interface */
@@ -5259,11 +5263,6 @@ static inline void efm32_sw_initialize(struct efm32_usbhost_s *priv)
usbhost_devaddr_initialize(&priv->rhport);
/* Initialize semaphores & mutex */
nxsem_init(&priv->pscsem, 0, 0);
nxmutex_init(&priv->lock);
/* Initialize the driver state data */
priv->smstate = SMSTATE_DETACHED;
arch/arm/src/gd32f4/gd32f4xx_dma.c
+16 -2
View File
@@ -90,82 +90,98 @@ static struct gd32_dma_channel_s g_dmachan[DMA_NCHANNELS] =
{
.chan_num = GD32_DMA_CH0,
.irq = GD32_IRQ_DMA0_CHANNEL0,
.chsem = SEM_INITIALIZER(1),
.dmabase = GD32_DMA0,
},
{
.chan_num = GD32_DMA_CH1,
.irq = GD32_IRQ_DMA0_CHANNEL1,
.chsem = SEM_INITIALIZER(1),
.dmabase = GD32_DMA0,
},
{
.chan_num = GD32_DMA_CH2,
.irq = GD32_IRQ_DMA0_CHANNEL2,
.chsem = SEM_INITIALIZER(1),
.dmabase = GD32_DMA0,
},
{
.chan_num = GD32_DMA_CH3,
.irq = GD32_IRQ_DMA0_CHANNEL3,
.chsem = SEM_INITIALIZER(1),
.dmabase = GD32_DMA0,
},
{
.chan_num = GD32_DMA_CH4,
.irq = GD32_IRQ_DMA0_CHANNEL4,
.chsem = SEM_INITIALIZER(1),
.dmabase = GD32_DMA0,
},
{
.chan_num = GD32_DMA_CH5,
.irq = GD32_IRQ_DMA0_CHANNEL5,
.chsem = SEM_INITIALIZER(1),
.dmabase = GD32_DMA0,
},
{
.chan_num = GD32_DMA_CH6,
.irq = GD32_IRQ_DMA0_CHANNEL6,
.chsem = SEM_INITIALIZER(1),
.dmabase = GD32_DMA0,
},
{
.chan_num = GD32_DMA_CH7,
.irq = GD32_IRQ_DMA0_CHANNEL7,
.chsem = SEM_INITIALIZER(1),
.dmabase = GD32_DMA0,
},
{
.chan_num = GD32_DMA_CH0,
.irq = GD32_IRQ_DMA1_CHANNEL0,
.chsem = SEM_INITIALIZER(1),
.dmabase = GD32_DMA1,
},
{
.chan_num = GD32_DMA_CH1,
.irq = GD32_IRQ_DMA1_CHANNEL1,
.chsem = SEM_INITIALIZER(1),
.dmabase = GD32_DMA1,
},
{
.chan_num = GD32_DMA_CH2,
.irq = GD32_IRQ_DMA1_CHANNEL2,
.chsem = SEM_INITIALIZER(1),
.dmabase = GD32_DMA1,
},
{
.chan_num = GD32_DMA_CH3,
.irq = GD32_IRQ_DMA1_CHANNEL3,
.chsem = SEM_INITIALIZER(1),
.dmabase = GD32_DMA1,
},
{
.chan_num = GD32_DMA_CH4,
.irq = GD32_IRQ_DMA1_CHANNEL4,
.chsem = SEM_INITIALIZER(1),
.dmabase = GD32_DMA1,
},
{
.chan_num = GD32_DMA_CH5,
.irq = GD32_IRQ_DMA1_CHANNEL5,
.chsem = SEM_INITIALIZER(1),
.dmabase = GD32_DMA1,
},
{
.chan_num = GD32_DMA_CH6,
.irq = GD32_IRQ_DMA1_CHANNEL6,
.chsem = SEM_INITIALIZER(1),
.dmabase = GD32_DMA1,
},
{
.chan_num = GD32_DMA_CH7,
.irq = GD32_IRQ_DMA1_CHANNEL7,
.chsem = SEM_INITIALIZER(1),
.dmabase = GD32_DMA1,
},
};
@@ -517,8 +533,6 @@ void weak_function arm_dma_initialize(void)
DEBUGASSERT(dmachan != NULL);
nxsem_init(&dmachan->chsem, 0, 1);
/* Attach DMA interrupt vectors */
irq_attach(dmachan->irq, gd32_dma_interrupt, dmachan);
arch/arm/src/gd32f4/gd32f4xx_spi.c
+18 -12
View File
@@ -298,6 +298,7 @@ static struct gd32_spidev_s g_spi0dev =
},
.spibase = GD32_SPI0,
.spiclock = GD32_PCLK2_FREQUENCY,
.lock = NXMUTEX_INITIALIZER,
#ifdef CONFIG_GD32F4_SPI_INTERRUPT
.spiirq = GD32_IRQ_SPI0,
#endif
@@ -314,6 +315,8 @@ static struct gd32_spidev_s g_spi0dev =
.rxch = 0,
.txch = 0,
# endif
.rxsem = SEM_INITIALIZER(0),
.txsem = SEM_INITIALIZER(0),
#endif
};
#endif
@@ -363,6 +366,7 @@ static struct gd32_spidev_s g_spi1dev =
},
.spibase = GD32_SPI1,
.spiclock = GD32_PCLK1_FREQUENCY,
.lock = NXMUTEX_INITIALIZER,
#ifdef CONFIG_GD32F4_SPI_INTERRUPT
.spiirq = GD32_IRQ_SPI1,
#endif
@@ -379,6 +383,8 @@ static struct gd32_spidev_s g_spi1dev =
.rxch = 0,
.txch = 0,
# endif
.rxsem = SEM_INITIALIZER(0),
.txsem = SEM_INITIALIZER(0),
#endif
};
#endif
@@ -428,6 +434,7 @@ static struct gd32_spidev_s g_spi2dev =
},
.spibase = GD32_SPI2,
.spiclock = GD32_PCLK1_FREQUENCY,
.lock = NXMUTEX_INITIALIZER,
#ifdef CONFIG_GD32F4_SPI_INTERRUPT
.spiirq = GD32_IRQ_SPI2,
#endif
@@ -444,6 +451,8 @@ static struct gd32_spidev_s g_spi2dev =
.rxch = 0,
.txch = 0,
# endif
.rxsem = SEM_INITIALIZER(0),
.txsem = SEM_INITIALIZER(0),
#endif
};
#endif
@@ -493,6 +502,7 @@ static struct gd32_spidev_s g_spi3dev =
},
.spibase = GD32_SPI3,
.spiclock = GD32_PCLK2_FREQUENCY,
.lock = NXMUTEX_INITIALIZER,
#ifdef CONFIG_GD32F4_SPI_INTERRUPT
.spiirq = GD32_IRQ_SPI3,
#endif
@@ -509,6 +519,8 @@ static struct gd32_spidev_s g_spi3dev =
.rxch = 0,
.txch = 0,
# endif
.rxsem = SEM_INITIALIZER(0),
.txsem = SEM_INITIALIZER(0),
#endif
};
#endif
@@ -558,6 +570,7 @@ static struct gd32_spidev_s g_spi4dev =
},
.spibase = GD32_SPI4,
.spiclock = GD32_PCLK2_FREQUENCY,
.lock = NXMUTEX_INITIALIZER,
#ifdef CONFIG_GD32F4_SPI_INTERRUPT
.spiirq = GD32_IRQ_SPI4,
#endif
@@ -574,6 +587,8 @@ static struct gd32_spidev_s g_spi4dev =
.rxch = 0,
.txch = 0,
# endif
.rxsem = SEM_INITIALIZER(0),
.txsem = SEM_INITIALIZER(0),
#endif
};
#endif
@@ -623,6 +638,7 @@ static struct gd32_spidev_s g_spi5dev =
},
.spibase = GD32_SPI5,
.spiclock = GD32_PCLK2_FREQUENCY,
.lock = NXMUTEX_INITIALIZER,
#ifdef CONFIG_GD32F5_SPI_INTERRUPT
.spiirq = GD32_IRQ_SPI5,
#endif
@@ -639,6 +655,8 @@ static struct gd32_spidev_s g_spi5dev =
.rxch = 0,
.txch = 0,
# endif
.rxsem = SEM_INITIALIZER(0),
.txsem = SEM_INITIALIZER(0),
#endif
};
#endif
@@ -2041,23 +2059,11 @@ static void spi_bus_initialize(struct gd32_spidev_s *priv)
spi_setfrequency((struct spi_dev_s *)priv, 400000);
/* Initialize the SPI lock that enforces mutually exclusive access */
nxmutex_init(&priv->lock);
#ifdef CONFIG_GD32F4_SPI_DMA
/* Initialize the SPI semaphores that is used to wait for DMA completion.
* This semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
*/
if (priv->rxch && priv->txch)
{
if (priv->txdma == NULL && priv->rxdma == NULL)
{
nxsem_init(&priv->rxsem, 0, 0);
nxsem_init(&priv->txsem, 0, 0);
/* Get DMA channels */
priv->rxdma = gd32_dma_channel_alloc(priv->rxch);
arch/arm/src/imx1/imx_spi.c
+4 -5
View File
@@ -209,7 +209,9 @@ static struct imx_spidev_s g_spidev[] =
{
.ops = &g_spiops,
.base = IMX_CSPI1_VBASE,
.lock = NXMUTEX_INITIALIZER,
#ifndef CONFIG_SPI_POLLWAIT
.waitsem = SEM_INITIALIZER(0),
.irq = IMX_IRQ_CSPI1,
#endif
},
@@ -218,7 +220,9 @@ static struct imx_spidev_s g_spidev[] =
{
.ops = &g_spiops,
.base = IMX_CSPI2_VBASE,
.lock = NXMUTEX_INITIALIZER,
#ifndef CONFIG_SPI_POLLWAIT
.waitsem = SEM_INITIALIZER(0),
.irq = IMX_IRQ_CSPI2,
#endif
},
@@ -1108,11 +1112,6 @@ struct spi_dev_s *imx_spibus_initialize(int port)
/* Initialize the state structure */
#ifndef CONFIG_SPI_POLLWAIT
nxsem_init(&priv->waitsem, 0, 0);
#endif
nxmutex_init(&priv->lock);
/* Initialize control register:
* min frequency, ignore ready, master mode, mode=0, 8-bit
*/
arch/arm/src/imx6/imx_ecspi.c
+10 -7
View File
@@ -268,7 +268,9 @@ static struct imx_spidev_s g_spidev[] =
.ops = &g_spiops,
.base = IMX_ECSPI1_VBASE,
.spindx = SPI1_NDX,
.lock = NXMUTEX_INITIALIZER,
#ifndef CONFIG_SPI_POLLWAIT
.waitsem = SEM_INITIALIZER(0),
.irq = IMX_IRQ_ECSPI1,
#endif
.select = imx_spi1select,
@@ -284,7 +286,9 @@ static struct imx_spidev_s g_spidev[] =
.ops = &g_spiops,
.base = IMX_ECSPI2_VBASE,
.spindx = SPI2_NDX,
.lock = NXMUTEX_INITIALIZER,
#ifndef CONFIG_SPI_POLLWAIT
.waitsem = SEM_INITIALIZER(0),
.irq = IMX_IRQ_ECSPI2,
#endif
.select = imx_spi2select,
@@ -300,7 +304,9 @@ static struct imx_spidev_s g_spidev[] =
.ops = &g_spiops,
.base = IMX_ECSPI3_VBASE,
.spindx = SPI3_NDX,
.lock = NXMUTEX_INITIALIZER,
#ifndef CONFIG_SPI_POLLWAIT
.waitsem = SEM_INITIALIZER(0),
.irq = IMX_IRQ_ECSPI3,
#endif
.select = imx_spi3select,
@@ -316,7 +322,9 @@ static struct imx_spidev_s g_spidev[] =
.ops = &g_spiops,
.base = IMX_ECSPI4_VBASE,
.spindx = SPI4_NDX,
.lock = NXMUTEX_INITIALIZER,
#ifndef CONFIG_SPI_POLLWAIT
.waitsem = SEM_INITIALIZER(0),
.irq = IMX_IRQ_ECSPI4,
#endif
.select = imx_spi4select,
@@ -332,7 +340,9 @@ static struct imx_spidev_s g_spidev[] =
.ops = &g_spiops,
.base = IMX_ECSPI5_VBASE,
.spindx = SPI5_NDX,
.lock = NXMUTEX_INITIALIZER,
#ifndef CONFIG_SPI_POLLWAIT
.waitsem = SEM_INITIALIZER(0),
.irq = IMX_IRQ_ECSPI5,
#endif
.select = imx_spi5select,
@@ -1282,13 +1292,6 @@ struct spi_dev_s *imx_spibus_initialize(int port)
/* Initialize the state structure */
/* Initialize Semaphores */
#ifndef CONFIG_SPI_POLLWAIT
nxsem_init(&priv->waitsem, 0, 0);
#endif
nxmutex_init(&priv->lock);
/* Initialize control register:
* min frequency, ignore ready, master mode, mode=0, 8-bit
*/
arch/arm/src/imxrt/imxrt_edma.c
+7 -7
View File
@@ -155,7 +155,13 @@ struct imxrt_edma_s
/* The state of the eDMA */
static struct imxrt_edma_s g_edma;
static struct imxrt_edma_s g_edma =
{
.chlock = NXMUTEX_INITIALIZER,
#if CONFIG_IMXRT_EDMA_NTCD > 0
.dsem = SEM_INITIALIZER(CONFIG_IMXRT_EDMA_NTCD),
#endif
};
#if CONFIG_IMXRT_EDMA_NTCD > 0
/* This is a singly-linked list of free TCDs */
@@ -740,18 +746,12 @@ void weak_function arm_dma_initialize(void)
/* Initialize data structures */
memset(&g_edma, 0, sizeof(struct imxrt_edma_s));
for (i = 0; i < IMXRT_EDMA_NCHANNELS; i++)
{
g_edma.dmach[i].chan = i;
}
/* Initialize mutex & semaphores */
nxmutex_init(&g_edma.chlock);
#if CONFIG_IMXRT_EDMA_NTCD > 0
nxsem_init(&g_edma.dsem, 0, CONFIG_IMXRT_EDMA_NTCD);
/* Initialize the list of free TCDs from the pool of pre-allocated TCDs. */
imxrt_tcd_initialize();
arch/arm/src/imxrt/imxrt_ehci.c
+6 -10
View File
@@ -567,7 +567,12 @@ static int imxrt_reset(void);
* single global instance.
*/
static struct imxrt_ehci_s g_ehci;
static struct imxrt_ehci_s g_ehci =
{
.lock = NXMUTEX_INITIALIZER,
.pscsem = SEM_INITIALIZER(0),
.ep0.iocsem = SEM_INITIALIZER(1),
};
/* This is the connection/enumeration interface */
@@ -4993,15 +4998,6 @@ struct usbhost_connection_s *imxrt_ehci_initialize(int controller)
usbhost_vtrace1(EHCI_VTRACE1_INITIALIZING, 0);
/* Initialize the EHCI state data structure */
nxmutex_init(&g_ehci.lock);
nxsem_init(&g_ehci.pscsem, 0, 0);
/* Initialize EP0 */
nxsem_init(&g_ehci.ep0.iocsem, 0, 1);
/* Initialize the root hub port structures */
for (i = 0; i < IMXRT_EHCI_NRHPORT; i++)
arch/arm/src/imxrt/imxrt_enc.c
+4 -4
View File
@@ -403,6 +403,7 @@ static struct imxrt_enc_lowerhalf_s imxrt_enc1_priv =
.ops = &g_qecallbacks,
.config = &imxrt_enc1_config,
.data = &imxrt_enc1_data,
.lock = NXMUTEX_INITIALIZER,
};
#endif
@@ -441,6 +442,7 @@ static struct imxrt_enc_lowerhalf_s imxrt_enc2_priv =
.ops = &g_qecallbacks,
.config = &imxrt_enc2_config,
.data = &imxrt_enc2_data,
.lock = NXMUTEX_INITIALIZER,
};
#endif
@@ -479,6 +481,7 @@ static struct imxrt_enc_lowerhalf_s imxrt_enc3_priv =
.ops = &g_qecallbacks,
.config = &imxrt_enc3_config,
.data = &imxrt_enc3_data,
.lock = NXMUTEX_INITIALIZER,
};
#endif
@@ -517,6 +520,7 @@ static struct imxrt_enc_lowerhalf_s imxrt_enc4_priv =
.ops = &g_qecallbacks,
.config = &imxrt_enc4_config,
.data = &imxrt_enc4_data,
.lock = NXMUTEX_INITIALIZER,
};
#endif
@@ -1225,10 +1229,6 @@ int imxrt_qeinitialize(const char *devpath, int enc)
return -ENODEV;
}
/* Initialize private data */
nxmutex_init(&priv->lock);
/* Register the upper-half driver */
int ret = qe_register(devpath, (struct qe_lowerhalf_s *)priv);
arch/arm/src/imxrt/imxrt_flexspi.c
+1 -6
View File
@@ -113,6 +113,7 @@ static struct imxrt_flexspidev_s g_flexspi0dev =
.ops = &g_flexspi0ops,
},
.base = (struct flexspi_type_s *) IMXRT_FLEXSPIC_BASE,
.lock = NXMUTEX_INITIALIZER,
};
#define FREQ_1MHz (1000000ul)
@@ -1268,12 +1269,6 @@ struct flexspi_dev_s *imxrt_flexspi_initialize(int intf)
{
/* No perform one time initialization */
/* Initialize the FlexSPI mutex that enforces mutually exclusive
* access to the FlexSPI registers.
*/
nxmutex_init(&priv->lock);
/* Perform hardware initialization. Puts the FlexSPI into an active
* state.
*/
arch/arm/src/imxrt/imxrt_lpspi.c
+12 -12
View File
@@ -248,9 +248,12 @@ static struct imxrt_lpspidev_s g_lpspi1dev =
#ifdef CONFIG_IMXRT_LPSPI_INTERRUPTS
.spiirq = IMXRT_IRQ_LPSPI1,
#endif
.lock = NXMUTEX_INITIALIZER,
#ifdef CONFIG_IMXRT_LPSPI1_DMA
.rxch = IMXRT_DMACHAN_LPSPI1_RX,
.txch = IMXRT_DMACHAN_LPSPI1_TX,
.rxsem = SEM_INITIALIZER(0),
.txsem = SEM_INITIALIZER(0),
#endif
};
#endif
@@ -294,9 +297,12 @@ static struct imxrt_lpspidev_s g_lpspi2dev =
#ifdef CONFIG_IMXRT_LPSPI_INTERRUPTS
.spiirq = IMXRT_IRQ_LPSPI2,
#endif
.lock = NXMUTEX_INITIALIZER,
#ifdef CONFIG_IMXRT_LPSPI2_DMA
.rxch = IMXRT_DMACHAN_LPSPI2_RX,
.txch = IMXRT_DMACHAN_LPSPI2_TX,
.rxsem = SEM_INITIALIZER(0),
.txsem = SEM_INITIALIZER(0),
#endif
};
#endif
@@ -340,9 +346,12 @@ static struct imxrt_lpspidev_s g_lpspi3dev =
#ifdef CONFIG_IMXRT_LPSPI_INTERRUPTS
.spiirq = IMXRT_IRQ_LPSPI3,
#endif
.lock = NXMUTEX_INITIALIZER,
#ifdef CONFIG_IMXRT_LPSPI3_DMA
.rxch = IMXRT_DMACHAN_LPSPI3_RX,
.txch = IMXRT_DMACHAN_LPSPI3_TX,
.rxsem = SEM_INITIALIZER(0),
.txsem = SEM_INITIALIZER(0),
#endif
};
#endif
@@ -386,9 +395,12 @@ static struct imxrt_lpspidev_s g_lpspi4dev =
#ifdef CONFIG_IMXRT_LPSPI_INTERRUPTS
.spiirq = IMXRT_IRQ_LPSPI4,
#endif
.lock = NXMUTEX_INITIALIZER,
#ifdef CONFIG_IMXRT_LPSPI4_DMA
.rxch = IMXRT_DMACHAN_LPSPI4_RX,
.txch = IMXRT_DMACHAN_LPSPI4_TX,
.rxsem = SEM_INITIALIZER(0),
.txsem = SEM_INITIALIZER(0),
#endif
};
#endif
@@ -1691,10 +1703,6 @@ static void imxrt_lpspi_bus_initialize(struct imxrt_lpspidev_s *priv)
imxrt_lpspi_setmode((struct spi_dev_s *)priv, SPIDEV_MODE0);
/* Initialize the SPI mutex that enforces mutually exclusive access */
nxmutex_init(&priv->lock);
/* Enable LPSPI */
imxrt_lpspi_modifyreg32(priv, IMXRT_LPSPI_CR_OFFSET, 0, LPSPI_CR_MEN);
@@ -2021,18 +2029,10 @@ struct spi_dev_s *imxrt_lpspibus_initialize(int bus)
}
#ifdef CONFIG_IMXRT_LPSPI_DMA
/* Initialize the SPI semaphores that is used to wait for DMA completion.
* This semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
*/
if (priv->rxch && priv->txch)
{
if (priv->txdma == NULL && priv->rxdma == NULL)
{
nxsem_init(&priv->rxsem, 0, 0);
nxsem_init(&priv->txsem, 0, 0);
priv->txdma = imxrt_dmach_alloc(priv->txch | DMAMUX_CHCFG_ENBL,
0);
priv->rxdma = imxrt_dmach_alloc(priv->rxch | DMAMUX_CHCFG_ENBL,
arch/arm/src/imxrt/imxrt_rtc_lowerhalf.c
+2 -2
View File
@@ -128,7 +128,8 @@ static const struct rtc_ops_s g_rtc_ops =
static struct imxrt_lowerhalf_s g_rtc_lowerhalf =
{
.ops = &g_rtc_ops,
.ops = &g_rtc_ops,
.devlock = NXMUTEX_INITIALIZER,
};
/****************************************************************************
@@ -514,7 +515,6 @@ static int imxrt_rdalarm(struct rtc_lowerhalf_s *lower,
struct rtc_lowerhalf_s *imxrt_rtc_lowerhalf(void)
{
nxmutex_init(&g_rtc_lowerhalf.devlock);
return (struct rtc_lowerhalf_s *)&g_rtc_lowerhalf;
}
arch/arm/src/imxrt/imxrt_serial.c
+8 -3
View File
@@ -846,6 +846,7 @@ static struct imxrt_uart_s g_lpuart1priv =
#ifdef CONFIG_LPUART1_TXDMA
.dma_txreqsrc = IMXRT_DMACHAN_LPUART1_TX,
.txdmasem = SEM_INITIALIZER(1),
#endif
#ifdef CONFIG_LPUART1_RXDMA
.dma_rxreqsrc = IMXRT_DMACHAN_LPUART1_RX,
@@ -914,6 +915,7 @@ static struct imxrt_uart_s g_lpuart2priv =
#ifdef CONFIG_LPUART2_TXDMA
.dma_txreqsrc = IMXRT_DMACHAN_LPUART2_TX,
.txdmasem = SEM_INITIALIZER(1),
#endif
#ifdef CONFIG_LPUART2_RXDMA
.dma_rxreqsrc = IMXRT_DMACHAN_LPUART2_RX,
@@ -980,6 +982,7 @@ static struct imxrt_uart_s g_lpuart3priv =
#ifdef CONFIG_LPUART3_TXDMA
.dma_txreqsrc = IMXRT_DMACHAN_LPUART3_TX,
.txdmasem = SEM_INITIALIZER(1),
#endif
#ifdef CONFIG_LPUART3_RXDMA
.dma_rxreqsrc = IMXRT_DMACHAN_LPUART3_RX,
@@ -1046,6 +1049,7 @@ static struct imxrt_uart_s g_lpuart4priv =
#ifdef CONFIG_LPUART4_TXDMA
.dma_txreqsrc = IMXRT_DMACHAN_LPUART4_TX,
.txdmasem = SEM_INITIALIZER(1),
#endif
#ifdef CONFIG_LPUART4_RXDMA
.dma_rxreqsrc = IMXRT_DMACHAN_LPUART4_RX,
@@ -1112,6 +1116,7 @@ static struct imxrt_uart_s g_lpuart5priv =
#ifdef CONFIG_LPUART5_TXDMA
.dma_txreqsrc = IMXRT_DMACHAN_LPUART5_TX,
.txdmasem = SEM_INITIALIZER(1),
#endif
#ifdef CONFIG_LPUART5_RXDMA
.dma_rxreqsrc = IMXRT_DMACHAN_LPUART5_RX,
@@ -1178,6 +1183,7 @@ static struct imxrt_uart_s g_lpuart6priv =
#ifdef CONFIG_LPUART6_TXDMA
.dma_txreqsrc = IMXRT_DMACHAN_LPUART6_TX,
.txdmasem = SEM_INITIALIZER(1),
#endif
#ifdef CONFIG_LPUART6_RXDMA
.dma_rxreqsrc = IMXRT_DMACHAN_LPUART6_RX,
@@ -1244,6 +1250,7 @@ static struct imxrt_uart_s g_lpuart7priv =
#ifdef CONFIG_LPUART7_TXDMA
.dma_txreqsrc = IMXRT_DMACHAN_LPUART7_TX,
.txdmasem = SEM_INITIALIZER(1),
#endif
#ifdef CONFIG_LPUART7_RXDMA
.dma_rxreqsrc = IMXRT_DMACHAN_LPUART7_RX,
@@ -1310,6 +1317,7 @@ static struct imxrt_uart_s g_lpuart8priv =
#ifdef CONFIG_LPUART8_TXDMA
.dma_txreqsrc = IMXRT_DMACHAN_LPUART8_TX,
.txdmasem = SEM_INITIALIZER(1),
#endif
#ifdef CONFIG_LPUART8_RXDMA
.dma_rxreqsrc = IMXRT_DMACHAN_LPUART8_RX,
@@ -1457,8 +1465,6 @@ static int imxrt_dma_setup(struct uart_dev_s *dev)
{
return -EBUSY;
}
nxsem_init(&priv->txdmasem, 0, 1);
}
/* Enable Tx DMA for the UART */
@@ -1659,7 +1665,6 @@ static void imxrt_dma_shutdown(struct uart_dev_s *dev)
imxrt_dmach_free(priv->txdma);
priv->txdma = NULL;
nxsem_destroy(&priv->txdmasem);
}
#endif
}
arch/arm/src/imxrt/imxrt_usdhc.c
+5 -6
View File
@@ -422,7 +422,8 @@ struct imxrt_dev_s g_sdhcdev[IMXRT_MAX_SDHC_DEV_SLOTS] =
.dmasendsetup = imxrt_sendsetup,
#endif
#endif
}
},
.waitsem = SEM_INITIALIZER(0),
},
#endif
@@ -479,7 +480,8 @@ struct imxrt_dev_s g_sdhcdev[IMXRT_MAX_SDHC_DEV_SLOTS] =
.dmarecvsetup = imxrt_recvsetup,
.dmasendsetup = imxrt_sendsetup,
#endif
}
},
.waitsem = SEM_INITIALIZER(0),
}
#endif
#endif
@@ -3215,11 +3217,8 @@ struct sdio_dev_s *imxrt_usdhc_initialize(int slotno)
DEBUGASSERT(slotno < IMXRT_MAX_SDHC_DEV_SLOTS);
struct imxrt_dev_s *priv = &g_sdhcdev[slotno];
/* Initialize the USDHC slot structure data structure
* Initialize semaphores
*/
/* Initialize the USDHC slot structure data structure */
nxsem_init(&priv->waitsem, 0, 0);
switch (priv->addr)
{
case IMXRT_USDHC1_BASE:
arch/arm/src/kinetis/kinetis_edma.c
+7 -7
View File
@@ -157,7 +157,13 @@ struct kinetis_edma_s
/* The state of the eDMA */
static struct kinetis_edma_s g_edma;
static struct kinetis_edma_s g_edma =
{
.chlock = NXMUTEX_INITIALIZER,
#if CONFIG_KINETIS_EDMA_NTCD > 0
.dsem = SEM_INITIALIZER(CONFIG_KINETIS_EDMA_NTCD),
#endif
};
#if CONFIG_KINETIS_EDMA_NTCD > 0
/* This is a singly-linked list of free TCDs */
@@ -721,18 +727,12 @@ void weak_function arm_dma_initialize(void)
/* Initialize data structures */
memset(&g_edma, 0, sizeof(struct kinetis_edma_s));
for (i = 0; i < KINETIS_EDMA_NCHANNELS; i++)
{
g_edma.dmach[i].chan = i;
}
/* Initialize mutex & semaphore */
nxmutex_init(&g_edma.chlock);
#if CONFIG_KINETIS_EDMA_NTCD > 0
nxsem_init(&g_edma.dsem, 0, CONFIG_KINETIS_EDMA_NTCD);
/* Initialize the list of free TCDs from the pool of pre-allocated TCDs. */
kinetis_tcd_initialize();
arch/arm/src/kinetis/kinetis_sdhc.c
+1 -4
View File
@@ -397,6 +397,7 @@ struct kinetis_dev_s g_sdhcdev =
#endif
#endif
},
.waitsem = SEM_INITIALIZER(0),
};
/* Register logging support */
@@ -2851,10 +2852,6 @@ struct sdio_dev_s *sdhc_initialize(int slotno)
/* Initialize the SDHC slot structure data structure */
/* Initialize semaphores */
nxsem_init(&priv->waitsem, 0, 0);
/* In addition to the system clock, the SDHC module needs a clock for the
* base for the external card clock. There are four possible sources for
* this clock, selected by the SIM's SOPT2 register:
arch/arm/src/kinetis/kinetis_spi.c
+9 -11
View File
@@ -226,6 +226,7 @@ static struct kinetis_spidev_s g_spi0dev =
&g_spi0ops
},
.spibase = KINETIS_SPI0_BASE,
.lock = NXMUTEX_INITIALIZER,
.ctarsel = KINETIS_SPI_CTAR0_OFFSET,
#ifdef CONFIG_KINETIS_SPI_DMA
# ifdef CONFIG_KINETIS_SPI0_DMA
@@ -235,6 +236,8 @@ static struct kinetis_spidev_s g_spi0dev =
.rxch = 0,
.txch = 0,
# endif
.rxsem = SEM_INITIALIZER(0),
.txsem = SEM_INITIALIZER(0),
#endif
};
#endif
@@ -275,6 +278,7 @@ static struct kinetis_spidev_s g_spi1dev =
&g_spi1ops
},
.spibase = KINETIS_SPI1_BASE,
.lock = NXMUTEX_INITIALIZER,
.ctarsel = KINETIS_SPI_CTAR0_OFFSET,
#ifdef CONFIG_KINETIS_SPI_DMA
# ifdef CONFIG_KINETIS_SPI1_DMA
@@ -284,6 +288,8 @@ static struct kinetis_spidev_s g_spi1dev =
.rxch = 0,
.txch = 0,
# endif
.rxsem = SEM_INITIALIZER(0),
.txsem = SEM_INITIALIZER(0),
#endif
};
#endif
@@ -324,6 +330,7 @@ static struct kinetis_spidev_s g_spi2dev =
&g_spi2ops
},
.spibase = KINETIS_SPI2_BASE,
.lock = NXMUTEX_INITIALIZER,
.ctarsel = KINETIS_SPI_CTAR0_OFFSET,
#ifdef CONFIG_KINETIS_SPI_DMA
# ifdef CONFIG_KINETIS_SPI2_DMA
@@ -333,6 +340,8 @@ static struct kinetis_spidev_s g_spi2dev =
.rxch = 0,
.txch = 0,
# endif
.rxsem = SEM_INITIALIZER(0),
.txsem = SEM_INITIALIZER(0),
#endif
};
#endif
@@ -1666,22 +1675,11 @@ struct spi_dev_s *kinetis_spibus_initialize(int port)
priv->frequency = 0;
spi_setfrequency(&priv->spidev, KINETIS_SPI_CLK_INIT);
/* Initialize the SPI mutex that enforces mutually exclusive access */
nxmutex_init(&priv->lock);
#ifdef CONFIG_KINETIS_SPI_DMA
/* Initialize the SPI semaphores that is used to wait for DMA completion.
* This semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
*/
if (priv->rxch && priv->txch)
{
if (priv->txdma == NULL && priv->rxdma == NULL)
{
nxsem_init(&priv->rxsem, 0, 0);
nxsem_init(&priv->txsem, 0, 0);
priv->txdma = kinetis_dmach_alloc(priv->txch | DMAMUX_CHCFG_ENBL,
0);
priv->rxdma = kinetis_dmach_alloc(priv->rxch | DMAMUX_CHCFG_ENBL,
arch/arm/src/kinetis/kinetis_usbhshost.c
+6 -10
View File
@@ -588,7 +588,12 @@ static int kinetis_reset(void);
* single global instance.
*/
static struct kinetis_ehci_s g_ehci;
static struct kinetis_ehci_s g_ehci =
{
.lock = NXMUTEX_INITIALIZER,
.pscsem = SEM_INITIALIZER(0),
.ep0.iocsem = SEM_INITIALIZER(1),
};
/* This is the connection/enumeration interface */
@@ -5067,15 +5072,6 @@ struct usbhost_connection_s *kinetis_ehci_initialize(int controller)
usbhost_vtrace1(EHCI_VTRACE1_INITIALIZING, 0);
/* Initialize the EHCI state data structure */
nxmutex_init(&g_ehci.lock);
nxsem_init(&g_ehci.pscsem, 0, 0);
/* Initialize EP0 */
nxsem_init(&g_ehci.ep0.iocsem, 0, 1);
/* Initialize the root hub port structures */
for (i = 0; i < KINETIS_EHCI_NRHPORT; i++)
arch/arm/src/kl/kl_spi.c
+2 -4
View File
@@ -126,6 +126,7 @@ static struct kl_spidev_s g_spi0dev =
&g_spi0ops
},
.spibase = KL_SPI0_BASE,
.lock = NXMUTEX_INITIALIZER,
};
#endif
@@ -158,6 +159,7 @@ static struct kl_spidev_s g_spi1dev =
&g_spi1ops
},
.spibase = KL_SPI1_BASE,
.lock = NXMUTEX_INITIALIZER,
};
#endif
@@ -688,10 +690,6 @@ struct spi_dev_s *kl_spibus_initialize(int port)
/* Select a default frequency of approx. 400KHz */
spi_setfrequency((struct spi_dev_s *)priv, 400000);
/* Initialize the SPI mutex that enforces mutually exclusive access */
nxmutex_init(&priv->lock);
return &priv->spidev;
}
arch/arm/src/lc823450/lc823450_dma.c
+4 -3
View File
@@ -122,7 +122,10 @@ static int phydmastart(struct lc823450_phydmach_s *pdmach);
* Private Data
****************************************************************************/
static struct lc823450_dma_s g_dma;
static struct lc823450_dma_s g_dma =
{
.lock = NXMUTEX_INITIALIZER,
};
volatile uint8_t g_dma_inprogress;
/****************************************************************************
@@ -342,8 +345,6 @@ void arm_dma_initialize(void)
sq_init(&g_dma.phydmach[i].req_q);
}
nxmutex_init(&g_dma.lock);
if (irq_attach(LC823450_IRQ_DMAC, dma_interrupt, NULL) != 0)
{
return;
arch/arm/src/lc823450/lc823450_i2s.c
+4 -9
View File
@@ -234,12 +234,12 @@ static const struct i2s_ops_s g_i2sops =
};
static DMA_HANDLE _hrxdma;
static sem_t _sem_rxdma;
static sem_t _sem_buf_over;
static sem_t _sem_rxdma = SEM_INITIALIZER(0);
static sem_t _sem_buf_over = SEM_INITIALIZER(0);
static DMA_HANDLE _htxdma;
static sem_t _sem_txdma;
static sem_t _sem_buf_under;
static sem_t _sem_txdma = SEM_INITIALIZER(0);
static sem_t _sem_buf_under = SEM_INITIALIZER(0);
/****************************************************************************
* Public Data
@@ -1034,12 +1034,7 @@ struct i2s_dev_s *lc823450_i2sdev_initialize(void)
#endif
_hrxdma = lc823450_dmachannel(DMA_CHANNEL_VIRTUAL);
nxsem_init(&_sem_rxdma, 0, 0);
nxsem_init(&_sem_buf_over, 0, 0);
_htxdma = lc823450_dmachannel(DMA_CHANNEL_VIRTUAL);
nxsem_init(&_sem_txdma, 0, 0);
nxsem_init(&_sem_buf_under, 0, 0);
#ifdef CONFIG_SMP
cpu_set_t cpuset0;
arch/arm/src/lc823450/lc823450_sddrv_dep.c
+10 -4
View File
@@ -81,9 +81,17 @@
#ifdef CONFIG_LC823450_SDC_DMA
static DMA_HANDLE _hrdma[2];
static sem_t _sem_rwait[2];
static sem_t _sem_rwait[2] =
{
SEM_INITIALIZER(0),
SEM_INITIALIZER(0),
};
static DMA_HANDLE _hwdma[2];
static sem_t _sem_wwait[2];
static sem_t _sem_wwait[2] =
{
SEM_INITIALIZER(0),
SEM_INITIALIZER(0),
};
#endif /* CONFIG_LC823450_SDC_DMA */
static uint64_t _sddep_timeout = (10 * 100); /* 10sec (in tick) */
@@ -281,9 +289,7 @@ SINT_T sddep_os_init(struct sddrcfg_s *cfg)
#ifdef CONFIG_LC823450_SDC_DMA
_hrdma[ch] = lc823450_dmachannel(DMA_CHANNEL_VIRTUAL);
nxsem_init(&_sem_rwait[ch], 0, 0);
_hwdma[ch] = lc823450_dmachannel(DMA_CHANNEL_VIRTUAL);
nxsem_init(&_sem_wwait[ch], 0, 0);
#endif /* CONFIG_LC823450_SDC_DMA */
return 0;
}
arch/arm/src/lc823450/lc823450_serial.c
+12 -2
View File
@@ -253,6 +253,10 @@ static struct up_dev_s g_uart0priv =
.parity = CONFIG_UART0_PARITY,
.bits = CONFIG_UART0_BITS,
.stopbits2 = CONFIG_UART0_2STOP,
#ifdef CONFIG_HSUART
.rxdma_wait = SEM_INITIALIZER(0),
.txdma_wait = SEM_INITIALIZER(1),
#endif
};
static uart_dev_t g_uart0port =
@@ -283,6 +287,10 @@ static struct up_dev_s g_uart1priv =
.parity = CONFIG_UART1_PARITY,
.bits = CONFIG_UART1_BITS,
.stopbits2 = CONFIG_UART1_2STOP,
#ifdef CONFIG_HSUART
.rxdma_wait = SEM_INITIALIZER(0),
.txdma_wait = SEM_INITIALIZER(1),
#endif
};
static uart_dev_t g_uart1port =
@@ -313,6 +321,10 @@ static struct up_dev_s g_uart2priv =
.parity = CONFIG_UART2_PARITY,
.bits = CONFIG_UART2_BITS,
.stopbits2 = CONFIG_UART2_2STOP,
#ifdef CONFIG_HSUART
.rxdma_wait = SEM_INITIALIZER(0),
.txdma_wait = SEM_INITIALIZER(1),
#endif
};
static uart_dev_t g_uart2port =
@@ -1329,11 +1341,9 @@ void arm_serialinit(void)
#ifdef TTYS1_DEV
uart_register("/dev/ttyS1", &TTYS1_DEV);
#ifdef CONFIG_HSUART
nxsem_init(&g_uart1priv.txdma_wait, 0, 1);
g_uart1priv.htxdma = lc823450_dmachannel(DMA_CHANNEL_UART1TX);
lc823450_dmarequest(g_uart1priv.htxdma, DMA_REQUEST_UART1TX);
nxsem_init(&g_uart1priv.rxdma_wait, 0, 0);
g_uart1priv.hrxdma = lc823450_dmachannel(DMA_CHANNEL_UART1RX);
lc823450_dmarequest(g_uart1priv.hrxdma, DMA_REQUEST_UART1RX);
arch/arm/src/lc823450/lc823450_spi.c
+6 -5
View File
@@ -130,6 +130,12 @@ static struct lc823450_spidev_s g_spidev =
{
&g_spiops
},
#ifndef CONFIG_SPI_OWNBUS
.lock = NXMUTEX_INITIALIZER,
#endif
#ifdef CONFIG_LC823450_SPI_DMA
.dma_wait = SEM_INITIALIZER(0),
#endif
};
/****************************************************************************
@@ -523,10 +529,6 @@ struct spi_dev_s *lc823450_spibus_initialize(int port)
modifyreg32(MCLKCNTAPB, 0, MCLKCNTAPB_PORT5_CLKEN);
modifyreg32(MRSTCNTAPB, 0, MRSTCNTAPB_PORT5_RSTB);
#ifndef CONFIG_SPI_OWNBUS
nxmutex_init(&priv->lock);
#endif
/* Initialize SPI mode. It must be done before starting SPI transfer */
/* PO: SPI Mode3 (default) */
@@ -543,7 +545,6 @@ struct spi_dev_s *lc823450_spibus_initialize(int port)
lc823450_spiinitialize();
#ifdef CONFIG_LC823450_SPI_DMA
nxsem_init(&priv->dma_wait, 0, 0);
priv->hdma = lc823450_dmachannel(DMA_CHANNEL_SIOTX);
lc823450_dmarequest(priv->hdma, DMA_REQUEST_SIOTX);
arch/arm/src/lc823450/lc823450_usbdev.c
+1 -4
View File
@@ -189,7 +189,7 @@ extern int lc823450_dvfs_boost(int timeout);
static struct lc823450_usbdev_s g_usbdev;
static DMA_HANDLE g_hdma;
static sem_t dma_wait;
static sem_t dma_wait = SEM_INITIALIZER(0);
#ifdef CONFIG_USBMSC_OPT
static struct lc823450_dma_llist g_dma_list[16];
@@ -1453,7 +1453,6 @@ void arm_usbinitialize(void)
return;
}
nxsem_init(&dma_wait, 0, 0);
g_hdma = lc823450_dmachannel(DMA_CHANNEL_USBDEV);
lc823450_dmarequest(g_hdma, DMA_REQUEST_USBDEV);
@@ -1722,7 +1721,6 @@ void usbdev_msc_read_enter()
privep->epcmd &= ~USB_EPCMD_EMPTY_EN;
epcmd_write(CONFIG_USBMSC_EPBULKIN, (privep->epcmd));
lc823450_dmareauest_dir(g_hdma, DMA_REQUEST_USBDEV, 1);
nxsem_init(&dma_wait, 0, 0);
}
/****************************************************************************
@@ -1825,7 +1823,6 @@ void usbdev_msc_write_enter0(void)
privep->epcmd &= ~USB_EPCMD_READY_EN;
epcmd_write(CONFIG_USBMSC_EPBULKOUT, (privep->epcmd));
lc823450_dmareauest_dir(g_hdma, DMA_REQUEST_USBDEV, 0);
nxsem_init(&dma_wait, 0, 0);
}
/****************************************************************************
arch/arm/src/lpc17xx_40xx/lpc17_40_gpdma.c
+4 -3
View File
@@ -84,7 +84,10 @@ struct lpc17_40_gpdma_s
/* The state of the LPC17 DMA block */
static struct lpc17_40_gpdma_s g_gpdma;
static struct lpc17_40_gpdma_s g_gpdma =
{
.lock = NXMUTEX_INITIALIZER,
};
/****************************************************************************
* Public Data
@@ -291,8 +294,6 @@ void weak_function arm_dma_initialize(void)
/* Initialize the DMA state structure */
nxmutex_init(&g_gpdma.lock);
for (i = 0; i < LPC17_40_NDMACH; i++)
{
g_gpdma.dmach[i].chn = i; /* Channel number */
arch/arm/src/lpc17xx_40xx/lpc17_40_i2c.c
+15 -13
View File
@@ -147,13 +147,25 @@ static int lpc17_40_i2c_reset(struct i2c_master_s * dev);
****************************************************************************/
#ifdef CONFIG_LPC17_40_I2C0
static struct lpc17_40_i2cdev_s g_i2c0dev;
static struct lpc17_40_i2cdev_s g_i2c0dev =
{
.lock = NXMUTEX_INITIALIZER,
.wait = SEM_INITIALIZER(0),
};
#endif
#ifdef CONFIG_LPC17_40_I2C1
static struct lpc17_40_i2cdev_s g_i2c1dev;
static struct lpc17_40_i2cdev_s g_i2c1dev =
{
.lock = NXMUTEX_INITIALIZER,
.wait = SEM_INITIALIZER(0),
};
#endif
#ifdef CONFIG_LPC17_40_I2C2
static struct lpc17_40_i2cdev_s g_i2c2dev;
static struct lpc17_40_i2cdev_s g_i2c2dev =
{
.lock = NXMUTEX_INITIALIZER,
.wait = SEM_INITIALIZER(0),
};
#endif
struct i2c_ops_s lpc17_40_i2c_ops =
@@ -617,11 +629,6 @@ struct i2c_master_s *lpc17_40_i2cbus_initialize(int port)
putreg32(I2C_CONSET_I2EN, priv->base + LPC17_40_I2C_CONSET_OFFSET);
/* Initialize mutex & semaphores */
nxmutex_init(&priv->lock);
nxsem_init(&priv->wait, 0, 0);
/* Attach Interrupt Handler */
irq_attach(priv->irqid, lpc17_40_i2c_interrupt, priv);
@@ -652,11 +659,6 @@ int lpc17_40_i2cbus_uninitialize(struct i2c_master_s * dev)
putreg32(I2C_CONCLRT_I2ENC, priv->base + LPC17_40_I2C_CONCLR_OFFSET);
/* Reset data structures */
nxmutex_destroy(&priv->lock);
nxsem_destroy(&priv->wait);
/* Cancel the watchdog timer */
wd_cancel(&priv->timeout);
arch/arm/src/lpc17xx_40xx/lpc17_40_sdcard.c
+1 -4
View File
@@ -444,6 +444,7 @@ struct lpc17_40_dev_s g_scard_dev =
#endif
#endif
},
.waitsem = SEM_INITIALIZER(0),
};
/* Register logging support */
@@ -2719,10 +2720,6 @@ struct sdio_dev_s *sdio_initialize(int slotno)
/* Initialize the SD card slot structure */
/* Initialize semaphores */
nxsem_init(&priv->waitsem, 0, 0);
#ifdef CONFIG_LPC17_40_SDCARD_DMA
/* Configure the SDCARD DMA request */
arch/arm/src/lpc17xx_40xx/lpc17_40_spi.c
+1 -4
View File
@@ -142,6 +142,7 @@ static struct lpc17_40_spidev_s g_spidev =
{
&g_spiops
},
.lock = NXMUTEX_INITIALIZER,
};
/****************************************************************************
@@ -563,10 +564,6 @@ struct spi_dev_s *lpc17_40_spibus_initialize(int port)
/* Select a default frequency of approx. 400KHz */
spi_setfrequency((struct spi_dev_s *)priv, 400000);
/* Initialize the SPI mutex that enforces mutually exclusive access */
nxmutex_init(&priv->lock);
return &priv->spidev;
}
arch/arm/src/lpc17xx_40xx/lpc17_40_ssp.c
+3 -4
View File
@@ -184,6 +184,7 @@ static struct lpc17_40_sspdev_s g_ssp0dev =
#ifdef CONFIG_LPC17_40_SSP_INTERRUPTS
.sspirq = LPC17_40_IRQ_SSP0,
#endif
.lock = NXMUTEX_INITIALIZER,
};
#endif /* CONFIG_LPC17_40_SSP0 */
@@ -219,6 +220,7 @@ static struct lpc17_40_sspdev_s g_ssp1dev =
#ifdef CONFIG_LPC17_40_SSP_INTERRUPTS
.sspirq = LPC17_40_IRQ_SSP1,
#endif
.lock = NXMUTEX_INITIALIZER,
};
#endif /* CONFIG_LPC17_40_SSP1 */
@@ -254,6 +256,7 @@ static struct lpc17_40_sspdev_s g_ssp2dev =
#ifdef CONFIG_LPC17_40_SSP_INTERRUPTS
.sspirq = LPC17_40_IRQ_SSP2,
#endif
.lock = NXMUTEX_INITIALIZER,
};
#endif /* CONFIG_LPC17_40_SSP2 */
@@ -993,10 +996,6 @@ struct spi_dev_s *lpc17_40_sspbus_initialize(int port)
ssp_setfrequency((struct spi_dev_s *)priv, 400000);
/* Initialize the SPI mutex that enforces mutually exclusive access */
nxmutex_init(&priv->lock);
/* Enable the SPI */
regval = ssp_getreg(priv, LPC17_40_SSP_CR1_OFFSET);
arch/arm/src/lpc17xx_40xx/lpc17_40_usbhost.c
+5 -6
View File
@@ -411,7 +411,11 @@ static inline void lpc17_40_ep0init(struct lpc17_40_usbhost_s *priv);
* single global instance.
*/
static struct lpc17_40_usbhost_s g_usbhost;
static struct lpc17_40_usbhost_s g_usbhost =
{
.lock = NXMUTEX_INITIALIZER,
.pscsem = SEM_INITIALIZER(0),
};
/* This is the connection/enumeration interface */
@@ -3736,11 +3740,6 @@ struct usbhost_connection_s *lpc17_40_usbhost_initialize(int controller)
usbhost_devaddr_initialize(&priv->rhport);
/* Initialize semaphores & mutex */
nxsem_init(&priv->pscsem, 0, 0);
nxmutex_init(&priv->lock);
#ifndef CONFIG_USBHOST_INT_DISABLE
priv->ininterval = MAX_PERINTERVAL;
priv->outinterval = MAX_PERINTERVAL;
arch/arm/src/lpc2378/lpc23xx_i2c.c
+15 -13
View File
@@ -153,13 +153,25 @@ static int lpc2378_i2c_reset(struct i2c_master_s * dev);
****************************************************************************/
#ifdef CONFIG_LPC2378_I2C0
static struct lpc2378_i2cdev_s g_i2c0dev;
static struct lpc2378_i2cdev_s g_i2c0dev =
{
.lock = NXMUTEX_INITIALIZER,
.wait = SEM_INITIALIZER(0),
};
#endif
#ifdef CONFIG_LPC2378_I2C1
static struct lpc2378_i2cdev_s g_i2c1dev;
static struct lpc2378_i2cdev_s g_i2c1dev =
{
.lock = NXMUTEX_INITIALIZER,
.wait = SEM_INITIALIZER(0),
};
#endif
#ifdef CONFIG_LPC2378_I2C2
static struct lpc2378_i2cdev_s g_i2c2dev;
static struct lpc2378_i2cdev_s g_i2c2dev =
{
.lock = NXMUTEX_INITIALIZER,
.wait = SEM_INITIALIZER(0),
};
#endif
struct i2c_ops_s lpc2378_i2c_ops =
@@ -580,11 +592,6 @@ struct i2c_master_s *lpc2378_i2cbus_initialize(int port)
putreg32(I2C_CONSET_I2EN, priv->base + I2C_CONSET_OFFSET);
/* Initialize mutex & semaphores */
nxmutex_init(&priv->lock);
nxsem_init(&priv->wait, 0, 0);
/* Attach Interrupt Handler */
irq_attach(priv->irqid, lpc2378_i2c_interrupt, priv);
@@ -615,11 +622,6 @@ int lpc2378_i2cbus_uninitialize(struct i2c_master_s * dev)
putreg32(I2C_CONCLRT_I2ENC, priv->base + I2C_CONCLR_OFFSET);
/* Reset data structures */
nxmutex_destroy(&priv->lock);
nxsem_destroy(&priv->wait);
/* Cancel the watchdog timer */
wd_cancel(&priv->timeout);
arch/arm/src/lpc2378/lpc23xx_spi.c
+1 -4
View File
@@ -161,6 +161,7 @@ static struct lpc23xx_spidev_s g_spidev =
{
&g_spiops
},
.lock = NXMUTEX_INITIALIZER,
};
/****************************************************************************
@@ -588,10 +589,6 @@ struct spi_dev_s *lpc23_spibus_initialize(int port)
/* Select a default frequency of approx. 400KHz */
spi_setfrequency((struct spi_dev_s *)priv, 400000);
/* Initialize the SPI mutex that enforces mutually exclusive access */
nxmutex_init(&priv->lock);
return &priv->spidev;
}
arch/arm/src/lpc31xx/lpc31_ehci.c
+6 -10
View File
@@ -565,7 +565,12 @@ static int lpc31_reset(void);
* global instance.
*/
static struct lpc31_ehci_s g_ehci;
static struct lpc31_ehci_s g_ehci =
{
.lock = NXMUTEX_INITIALIZER,
.pscsem = SEM_INITIALIZER(0),
.ep0.iocsem = SEM_INITIALIZER(1),
};
/* This is the connection/enumeration interface */
@@ -5016,15 +5021,6 @@ struct usbhost_connection_s *lpc31_ehci_initialize(int controller)
usbhost_vtrace1(EHCI_VTRACE1_INITIALIZING, 0);
/* Initialize the EHCI state data structure */
nxmutex_init(&g_ehci.lock);
nxsem_init(&g_ehci.pscsem, 0, 0);
/* Initialize EP0 */
nxsem_init(&g_ehci.ep0.iocsem, 0, 1);
/* Initialize the root hub port structures */
for (i = 0; i < LPC31_EHCI_NRHPORT; i++)

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