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LM: Don't initialize .data if running in SRAM. Global missing intialize type. SAMA5 NAND: Fix for read nand in smaller chunks

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This commit is contained in:
Gregory Nutt
2013-12-05 10:37:55 -06:00
parent 10143f89f4
commit d01808c603
44 changed files with 85 additions and 166 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/8051/src/up_initialstate.c
+1 -1
View File
@@ -106,7 +106,7 @@ void up_initial_state(FAR struct tcb_s *tcb)
frame[FRAME_IE] = 0x80;
/* Save the number of bytes in the frame (which will be used
* to intialize the stack pointer when the task is started).
* to initialize the stack pointer when the task is started).
*/
tcb->xcp.nbytes = FRAME_SIZE;
arch/arm/src/common/up_initialize.c
+1 -1
View File
@@ -127,7 +127,7 @@ void up_initialize(void)
up_irqinitialize();
/* Initialize the power management subsystem. This MCU-specific function
* must be called *very* early in the intialization sequence *before* any
* must be called *very* early in the initialization sequence *before* any
* other device drivers are initialized (since they may attempt to register
* with the power management subsystem).
*/
arch/arm/src/kinetis/kinetis_start.c
+1 -1
View File
@@ -100,7 +100,7 @@ void __start(void)
*dest++ = 0;
}
/* Move the intialized data section from his temporary holding spot in
/* Move the initialized data section from his temporary holding spot in
* FLASH into the correct place in SRAM. The correct place in SRAM is
* give by _sdata and _edata. The temporary location is in FLASH at the
* end of all of the other read-only data (.text, .rodata) at _eronly.
arch/arm/src/kl/kl_start.c
+1 -1
View File
@@ -137,7 +137,7 @@ void __start(void)
}
showprogress('B');
/* Move the intialized data section from his temporary holding spot in
/* Move the initialized data section from his temporary holding spot in
* FLASH into the correct place in SRAM. The correct place in SRAM is
* give by _sdata and _edata. The temporary location is in FLASH at the
* end of all of the other read-only data (.text, .rodata) at _eronly.
arch/arm/src/lm/lm_start.c
+3 -1
View File
@@ -119,7 +119,8 @@ void __start(void)
}
showprogress('B');
/* Move the intialized data section from his temporary holding spot in
#ifdef CONFIG_BOOT_RUNFROMFLASH
/* Move the initialized data section from his temporary holding spot in
* FLASH into the correct place in SRAM. The correct place in SRAM is
* give by _sdata and _edata. The temporary location is in FLASH at the
* end of all of the other read-only data (.text, .rodata) at _eronly.
@@ -130,6 +131,7 @@ void __start(void)
*dest++ = *src++;
}
showprogress('C');
#endif
/* Perform early serial initialization */
arch/arm/src/lpc17xx/lpc17_start.c
+1 -1
View File
@@ -213,7 +213,7 @@ void __start(void)
showprogress('B');
/* Move the intialized data section from his temporary holding spot in
/* Move the initialized data section from his temporary holding spot in
* FLASH into the correct place in SRAM. The correct place in SRAM is
* give by _sdata and _edata. The temporary location is in FLASH at the
* end of all of the other read-only data (.text, .rodata) at _eronly.
arch/arm/src/lpc17xx/lpc17_usbhost.c
+1 -1
View File
@@ -2509,7 +2509,7 @@ static inline void lpc17_ep0init(struct lpc17_usbhost_s *priv)
*
* Input Parameters:
* controller -- If the device supports more than USB host controller, then
* this identifies which controller is being intialized. Normally, this
* this identifies which controller is being initialized. Normally, this
* is just zero.
*
* Returned Value:
arch/arm/src/lpc17xx/lpc17_usbhost.h
+1 -1
View File
@@ -77,7 +77,7 @@ extern "C"
*
* Input Parameters:
* controller -- If the device supports more than USB host controller, then
* this identifies which controller is being intialized. Normally, this
* this identifies which controller is being initializeed. Normally, this
* is just zero.
*
* Returned Value:
arch/arm/src/lpc31xx/lpc31_ehci.c
+1 -1
View File
@@ -4160,7 +4160,7 @@ static int lpc31_reset(void)
*
* Input Parameters:
* controller -- If the device supports more than one EHCI interface, then
* this identifies which controller is being intialized. Normally, this
* this identifies which controller is being initialized. Normally, this
* is just zero.
*
* Returned Value:
arch/arm/src/lpc31xx/lpc31_internal.h
+1 -1
View File
@@ -248,7 +248,7 @@ void lpc31_usbsuspend(FAR struct usbdev_s *dev, bool resume);
*
* Input Parameters:
* controller -- If the device supports more than one EHCI interface, then
* this identifies which controller is being intialized. Normally, this
* this identifies which controller is being initializeed. Normally, this
* is just zero.
*
* Returned Value:
arch/arm/src/lpc43xx/lpc43_start.c
+1 -1
View File
@@ -309,7 +309,7 @@ void __start(void)
}
showprogress('B');
/* Move the intialized data section from his temporary holding spot in
/* Move the initialized data section from his temporary holding spot in
* FLASH into the correct place in SRAM. The correct place in SRAM is
* give by _sdata and _edata. The temporary location is in FLASH at the
* end of all of the other read-only data (.text, .rodata) at _eronly.
arch/arm/src/nuc1xx/nuc_start.c
+1 -1
View File
@@ -131,7 +131,7 @@ void __start(void)
}
showprogress('B');
/* Move the intialized data section from his temporary holding spot in
/* Move the initialized data section from his temporary holding spot in
* FLASH into the correct place in SRAM. The correct place in SRAM is
* give by _sdata and _edata. The temporary location is in FLASH at the
* end of all of the other read-only data (.text, .rodata) at _eronly.
arch/arm/src/sam34/sam_start.c
+1 -1
View File
@@ -112,7 +112,7 @@ void __start(void)
*dest++ = 0;
}
/* Move the intialized data section from his temporary holding spot in
/* Move the initialized data section from his temporary holding spot in
* FLASH into the correct place in SRAM. The correct place in SRAM is
* give by _sdata and _edata. The temporary location is in FLASH at the
* end of all of the other read-only data (.text, .rodata) at _eronly.
arch/arm/src/sama5/sam_ehci.c
+1 -1
View File
@@ -4000,7 +4000,7 @@ static int sam_reset(void)
*
* Input Parameters:
* controller -- If the device supports more than one EHCI interface, then
* this identifies which controller is being intialized. Normally, this
* this identifies which controller is being initialized. Normally, this
* is just zero.
*
* Returned Value:
arch/arm/src/sama5/sam_irq.c
+1 -1
View File
@@ -213,7 +213,7 @@ void up_irqinitialize(void)
int i;
/* The following operations need to be atomic, but since this function is
* called early in the intialization sequence, we expect to have exclusive
* called early in the initialization sequence, we expect to have exclusive
* access to the AIC.
*/
arch/arm/src/sama5/sam_nand.c
+37 -120
View File
@@ -221,11 +221,8 @@ static int nand_dma_write(struct sam_nandcs_s *priv,
static int nand_nfcsram_read(uintptr_t src, uint8_t *dest,
size_t buflen);
static int nand_smc_read8(uintptr_t src, uint8_t *dest, size_t buflen);
static int nand_smc_read16(uintptr_t src, uint8_t *dest,
size_t buflen);
static int nand_read(struct sam_nandcs_s *priv, bool nfcsram,
uint8_t *buffer, size_t buflen);
static int nand_read(struct sam_nandcs_s *priv, uint8_t *buffer,
uint16_t buflen, uint16_t offset);
#ifdef CONFIG_SAMA5_HAVE_PMECC
static int nand_read_pmecc(struct sam_nandcs_s *priv, off_t block,
@@ -1480,83 +1477,26 @@ static int nand_nfcsram_read(uintptr_t src, uint8_t *dest, size_t buflen)
return OK;
}
/****************************************************************************
* Name: nand_smc_read8
*
* Description:
* Read 8-bit data from NAND using the NAND data address (without DMA)
*
* Input Parameters:
* src - NAND data source address
* dest - Buffer that will receive the data from the read
* buflen - The number of bytes to transfer
*
* Returned Value
* OK always
*
****************************************************************************/
static int nand_smc_read8(uintptr_t src, uint8_t *dest, size_t buflen)
{
volatile uint8_t *src8 = (volatile uint8_t *)src;
for (; buflen > 0; buflen--)
{
*dest++ = *src8;
}
return OK;
}
/****************************************************************************
* Name: nand_smc_read16
*
* Description:
* Read 16-bit data from NAND using the NAND data address (without DMA)
*
* Input Parameters:
* src - NAND data source address
* dest - Buffer that will receive the data from the read
* buflen - The number of bytes to transfer
*
* Returned Value
* OK always
*
****************************************************************************/
static int nand_smc_read16(uintptr_t src, uint8_t *dest, size_t buflen)
{
volatile uint16_t *src16 = (volatile uint16_t *)src;
uint16_t *dest16 = (uint16_t *)dest;
DEBUGASSERT(((uintptr_t)dest & 1) == 0);
for (; buflen > 1; buflen -= sizeof(uint16_t))
{
*dest16++ = *src16;
}
return OK;
}
/****************************************************************************
* Name: nand_read
*
* Description:
* Read data from NAND using the appropriate method
* Read data from NAND using the NFC SRAM
*
* Input Parameters:
* priv - Lower-half, private NAND FLASH device state
* nfcsram - True: Use NFC Host SRAM
* buffer - Buffer that provides the data for the write
* buflen - The amount of data to read into the buffer
* offset - If reading from NFC SRAM, this is the offset into
* the SRAM.
*
* Returned Value
* OK on success; a negated errno value on failure.
*
****************************************************************************/
static int nand_read(struct sam_nandcs_s *priv, bool nfcsram,
uint8_t *buffer, size_t buflen)
static int nand_read(struct sam_nandcs_s *priv, uint8_t *buffer,
uint16_t buflen, uint16_t offset)
{
uintptr_t src;
#ifdef CONFIG_SAMA5_NAND_DMA
@@ -1565,48 +1505,32 @@ static int nand_read(struct sam_nandcs_s *priv, bool nfcsram,
int buswidth;
int ret;
fvdbg("nfcsram=%d buffer=%p buflen=%d\n", nfcsram, buffer, (int)buflen);
fvdbg("buffer=%p buflen=%d offset=%d\n", buffer, buflen, offset);
/* Get the data source: NFC SRAM (perhaps with an offset)
* NOTE: We could use the address priv->raw.dataaddr if we want to
* bypass NFC SRAM.
*/
src = NFCSRAM_BASE + offset;
/* Get the buswidth */
buswidth = nandmodel_getbuswidth(&priv->raw.model);
/* Pick the data source: The NFC SRAM or the NAND data address */
if (nfcsram)
{
/* Source is NFC SRAM */
src = NFCSRAM_BASE;
#ifdef CONFIG_SAMA5_NAND_DMA
/* Select NFC SRAM DMA */
dmaflags = (buswidth == 16 ? NFCSRAM_DMA_FLAGS16 : NFCSRAM_DMA_FLAGS8);
#endif
}
else
{
/* Source is NFC NAND */
src = priv->raw.dataaddr;
#ifdef CONFIG_SAMA5_NAND_DMA
/* Select NAND DMA */
dmaflags = (buswidth == 16 ? NAND_DMA_FLAGS16 : NAND_DMA_FLAGS8);
#endif
}
#ifdef CONFIG_SAMA5_NAND_DMA
/* Then perform the transfer via memory-to-memory DMA or not, depending
* on if we have a DMA channel assigned and if the transfer is
* sufficiently large. Small DMAs (e.g., for spare data) are not peformed
* sufficiently large. Small DMAs (e.g., for spare data) are not performed
* because the DMA context switch can take more time that the DMA itself.
*/
if (priv->dma && buflen > CONFIG_SAMA5_NAND_DMA_THRESHOLD)
{
/* Select NFC SRAM DMA */
dmaflags = (buswidth == 16 ? NFCSRAM_DMA_FLAGS16 : NFCSRAM_DMA_FLAGS8);
/* Transfer using DMA */
ret = nand_dma_read(priv, src, (uintptr_t)buffer, buflen, dmaflags);
@@ -1616,23 +1540,9 @@ static int nand_read(struct sam_nandcs_s *priv, bool nfcsram,
/* Transfer without DMA */
if (nfcsram)
{
ret = nand_nfcsram_read(src, buffer, buflen);
}
else
{
/* Check the data bus width of the NAND FLASH */
if (buswidth == 16)
{
ret = nand_smc_read16(src, buffer, buflen);
}
else
{
ret = nand_smc_read8(src, buffer, buflen);
}
}
nand_dump("NAND Read", buffer, buflen);
return ret;
@@ -1724,9 +1634,11 @@ static int nand_read_pmecc(struct sam_nandcs_s *priv, off_t block,
regval |= HSMC_PMECCFG_AUTO_ENABLE;
}
regval |= HSMC_PMECCTRL_DATA;
nand_putreg(SAM_HSMC_PMECCFG, regval);
/* Start the data phase and perform the transfer */
nand_putreg(SAM_HSMC_PMECCTRL, HSMC_PMECCTRL_DATA);
nand_nfc_cleale(priv,
HSMC_ALE_COL_EN | HSMC_ALE_ROW_EN | HSMC_CLE_VCMD2_EN | HSMC_CLE_DATA_EN,
COMMAND_READ_1, COMMAND_READ_2, 0, rowaddr);
@@ -1739,18 +1651,20 @@ static int nand_read_pmecc(struct sam_nandcs_s *priv, off_t block,
nand_putreg(SAM_HSMC_PMECCTRL, HSMC_PMECCTRL_DATA);
/* Read the data area */
/* Read the data area into the caller provided buffer (pagesize bytes) */
ret = nand_read(priv, true, (uint8_t *)data, pagesize);
ret = nand_read(priv, (uint8_t *)data, pagesize, 0);
if (ret < 0)
{
fdbg("ERROR: nand_read for data region failed: %d\n", ret);
return ret;
}
/* Read the spare area into priv->raw.spare */
/* Read the spare area into priv->raw.spare. The data to be read lies at
* offset pagesize in NFC SRAM.
*/
ret = nand_read(priv, true, priv->raw.spare, priv->raw.model.sparesize);
ret = nand_read(priv, priv->raw.spare, priv->raw.model.sparesize, pagesize);
if (ret < 0)
{
fdbg("ERROR: nand_read for spare region failed: %d\n", ret);
@@ -2044,7 +1958,7 @@ static int nand_readpage_noecc(struct sam_nandcs_s *priv, off_t block,
if (data)
{
ret = nand_read(priv, true, (uint8_t *)data, pagesize);
ret = nand_read(priv, (uint8_t *)data, pagesize, 0);
if (ret < 0)
{
fdbg("ERROR: nand_read for data region failed: %d\n", ret);
@@ -2052,11 +1966,14 @@ static int nand_readpage_noecc(struct sam_nandcs_s *priv, off_t block,
}
}
/* Read the spare area if so requested */
/* Read the spare area if so requested. Read NFS SRAM from offset 0 in any
* case because the coladdr was appropiately set above for the case where
* there is no data.
*/
if (spare)
{
ret = nand_read(priv, true, (uint8_t *)spare, sparesize);
ret = nand_read(priv, (uint8_t *)spare, sparesize, 0);
if (ret < 0)
{
fdbg("ERROR: nand_read for spare region failed: %d\n", ret);
@@ -3018,7 +2935,7 @@ struct mtd_dev_s *sam_nand_initialize(int cs)
}
/* Initialize the NAND hardware for this CS */
/* Perform board-specific SMC intialization for this CS. This should include:
/* Perform board-specific SMC initialization for this CS. This should include:
*
* 1. Enabling of clocking to the HSMC
* 2. Configuration of timing for the HSMC NAND CS
arch/arm/src/sama5/sam_ohci.c
+1 -1
View File
@@ -3089,7 +3089,7 @@ static void sam_disconnect(FAR struct usbhost_driver_s *drvr)
*
* Input Parameters:
* controller -- If the device supports more than one OHCI interface, then
* this identifies which controller is being intialized. Normally, this
* this identifies which controller is being initialized. Normally, this
* is just zero.
*
* Returned Value:
arch/arm/src/sama5/sam_pmecc.c
+2 -2
View File
@@ -924,9 +924,9 @@ static int pmecc_pagelayout(uint16_t datasize, uint16_t eccsize)
correctability512 = nsectors512 * g_correctability[bcherr512];
correctability1K = nsectors1k * g_correctability[bcherr1k];
/* Use 1K sectors unless we can do better with 512B sectors */
/* Use 512B sectors unless we can do better with 1K sectors */
if (correctability512 > correctability1K)
if (correctability512 >= correctability1K)
{
g_pmecc.sector1k = false;
g_pmecc.nsectors = nsectors512;
arch/arm/src/sama5/sam_rtc.c
+1 -1
View File
@@ -380,7 +380,7 @@ int up_rtcinitialize(void)
* Get the current date and time from the date/time RTC. This interface
* is only supported by the date/time RTC hardware implementation.
* It is used to replace the system timer. It is only used by the RTOS during
* intialization to set up the system time when CONFIG_RTC and CONFIG_RTC_DATETIME
* initialization to set up the system time when CONFIG_RTC and CONFIG_RTC_DATETIME
* are selected (and CONFIG_RTC_HIRES is not).
*
* NOTE: Some date/time RTC hardware is capability of sub-second accuracy. That
arch/arm/src/sama5/sam_ssc.c
+1 -1
View File
@@ -879,7 +879,7 @@ static void ssc_buf_free(struct sam_ssc_s *priv, struct sam_buffer_s *bfcontaine
* None
*
* Assumptions:
* Called early in SSC intialization so that there are no issues with
* Called early in SSC initialization so that there are no issues with
* concurrency.
*
****************************************************************************/
arch/arm/src/sama5/sam_usbhost.h
+2 -2
View File
@@ -230,7 +230,7 @@ extern "C"
*
* Input Parameters:
* controller -- If the device supports more than one USB OHCI interface, then
* this identifies which controller is being intialized. Normally, this
* this identifies which controller is being initializeed. Normally, this
* is just zero.
*
* Returned Value:
@@ -274,7 +274,7 @@ int sam_ohci_tophalf(int irq, FAR void *context);
*
* Input Parameters:
* controller -- If the device supports more than one EHCI interface, then
* this identifies which controller is being intialized. Normally, this
* this identifies which controller is being initializeed. Normally, this
* is just zero.
*
* Returned Value:
arch/arm/src/sama5/sam_wdt.c
+1 -1
View File
@@ -649,7 +649,7 @@ static int sam_ioctl(FAR struct watchdog_lowerhalf_s *lower, int cmd,
* Name: up_wdginitialize
*
* Description:
* Initialize the WDT watchdog time. The watchdog timer is intialized and
* Initialize the WDT watchdog time. The watchdog timer is initialized and
* registered as 'devpath. The initial state of the watchdog time is
* disabled.
*
arch/arm/src/stm32/stm32_iwdg.c
+1 -1
View File
@@ -641,7 +641,7 @@ static int stm32_settimeout(FAR struct watchdog_lowerhalf_s *lower,
* Name: stm32_iwdginitialize
*
* Description:
* Initialize the IWDG watchdog time. The watchdog timer is intialized and
* Initialize the IWDG watchdog time. The watchdog timer is initialized and
* registers as 'devpath. The initial state of the watchdog time is
* disabled.
*
arch/arm/src/stm32/stm32_otgfs.h
+1 -1
View File
@@ -81,7 +81,7 @@ extern "C"
*
* Input Parameters:
* controller -- If the device supports more than USB host controller, then
* this identifies which controller is being intialized. Normally, this
* this identifies which controller is being initializeed. Normally, this
* is just zero.
*
* Returned Value:
arch/arm/src/stm32/stm32_otgfshost.c
+1 -1
View File
@@ -4255,7 +4255,7 @@ static inline int stm32_hw_initialize(FAR struct stm32_usbhost_s *priv)
*
* Input Parameters:
* controller -- If the device supports more than USB host controller, then
* this identifies which controller is being intialized. Normally, this
* this identifies which controller is being initialized. Normally, this
* is just zero.
*
* Returned Value:
arch/arm/src/stm32/stm32_pminitialize.c
+1 -1
View File
@@ -72,7 +72,7 @@
* Description:
* This function is called by MCU-specific logic at power-on reset in
* order to provide one-time initialization the power management subystem.
* This function must be called *very* early in the intialization sequence
* This function must be called *very* early in the initialization sequence
* *before* any other device drivers are initialized (since they may
* attempt to register with the power management subsystem).
*
arch/arm/src/stm32/stm32_rtcc.c
+1 -1
View File
@@ -644,7 +644,7 @@ int up_rtcinitialize(void)
* Get the current date and time from the date/time RTC. This interface
* is only supported by the date/time RTC hardware implementation.
* It is used to replace the system timer. It is only used by the RTOS during
* intialization to set up the system time when CONFIG_RTC and CONFIG_RTC_DATETIME
* initialization to set up the system time when CONFIG_RTC and CONFIG_RTC_DATETIME
* are selected (and CONFIG_RTC_HIRES is not).
*
* NOTE: Some date/time RTC hardware is capability of sub-second accuracy. That
arch/arm/src/stm32/stm32_rtcounter.c
+1 -1
View File
@@ -413,7 +413,7 @@ int up_rtcinitialize(void)
* Get the current time in seconds. This is similar to the standard time()
* function. This interface is only required if the low-resolution RTC/counter
* hardware implementation selected. It is only used by the RTOS during
* intialization to set up the system time when CONFIG_RTC is set but neither
* initialization to set up the system time when CONFIG_RTC is set but neither
* CONFIG_RTC_HIRES nor CONFIG_RTC_DATETIME are set.
*
* Input Parameters:
arch/arm/src/stm32/stm32_start.c
+1 -1
View File
@@ -254,7 +254,7 @@ void __start(void)
showprogress('B');
/* Move the intialized data section from his temporary holding spot in
/* Move the initialized data section from his temporary holding spot in
* FLASH into the correct place in SRAM. The correct place in SRAM is
* give by _sdata and _edata. The temporary location is in FLASH at the
* end of all of the other read-only data (.text, .rodata) at _eronly.
arch/arm/src/stm32/stm32_wdg.h
+2 -2
View File
@@ -69,7 +69,7 @@ extern "C" {
* Name: stm32_iwdginitialize
*
* Description:
* Initialize the IWDG watchdog time. The watchdog timer is intialized and
* Initialize the IWDG watchdog time. The watchdog timer is initializeed and
* registers as 'devpath. The initial state of the watchdog time is
* disabled.
*
@@ -91,7 +91,7 @@ EXTERN void stm32_iwdginitialize(FAR const char *devpath, uint32_t lsifreq);
* Name: stm32_wwdginitialize
*
* Description:
* Initialize the WWDG watchdog time. The watchdog timer is intialized and
* Initialize the WWDG watchdog time. The watchdog timer is initializeed and
* registers as 'devpath. The initial state of the watchdog time is
* disabled.
*
arch/arm/src/stm32/stm32_wwdg.c
+1 -1
View File
@@ -742,7 +742,7 @@ static int stm32_ioctl(FAR struct watchdog_lowerhalf_s *lower, int cmd,
* Name: stm32_wwdginitialize
*
* Description:
* Initialize the WWDG watchdog time. The watchdog timer is intialized and
* Initialize the WWDG watchdog time. The watchdog timer is initialized and
* registers as 'devpath. The initial state of the watchdog time is
* disabled.
*
arch/arm/src/str71x/str71x_decodeirq.c
+1 -1
View File
@@ -80,7 +80,7 @@
* up_decodeirq()
*
* Description:
* Read the IRQ number from the IVR register. During intialization, the IVR
* Read the IRQ number from the IVR register. During initialization, the IVR
* register was set to zero. Each SIR[n] register was programmed to contain
* the IRQ number. At IRQ processing time (when this function run), the IVR
* should contain the desired IRQ number.
arch/arm/src/str71x/str71x_head.S
+1 -1
View File
@@ -336,7 +336,7 @@ eicloop:
add \irqno, \irqno, #1
/* Continue to loop until all of the SIR registers have been
* intialized.
* initializeed.
*/
cmp \irqno, #STR71X_EIC_NCHANNELS
arch/avr/src/at32uc3/at32uc3_internal.h
+1 -1
View File
@@ -210,7 +210,7 @@ void usart_configure(uintptr_t usart_base, uint32_t baud, unsigned int parity,
*
* Description:
* Initialize a console for debug output. This function is called very
* early in the intialization sequence to configure the serial console
* early in the initializeation sequence to configure the serial console
* uart (only).
*
****************************************************************************/
arch/avr/src/at32uc3/at32uc3_lowconsole.c
+1 -1
View File
@@ -295,7 +295,7 @@ void usart_configure(uintptr_t usart_base, uint32_t baud, unsigned int parity,
*
* Description:
* Initialize a console for debug output. This function is called very
* early in the intialization sequence to configure the serial console uart
* early in the initialization sequence to configure the serial console uart
* (only).
*
******************************************************************************/
arch/avr/src/at90usb/at90usb_internal.h
+1 -1
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@@ -115,7 +115,7 @@ EXTERN void usart1_configure(void);
*
* Description:
* Initialize a console for debug output. This function is called very
* early in the intialization sequence to configure the serial console
* early in the initializeation sequence to configure the serial console
* uart (only).
*
****************************************************************************/
arch/avr/src/at90usb/at90usb_lowconsole.c
+1 -1
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@@ -254,7 +254,7 @@ void usart1_configure(void)
*
* Description:
* Initialize a console for debug output. This function is called very
* early in the intialization sequence to configure the serial console uart
* early in the initialization sequence to configure the serial console uart
* (only).
*
******************************************************************************/
arch/avr/src/atmega/atmega_internal.h
+1 -1
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@@ -117,7 +117,7 @@ EXTERN void usart1_configure(void);
*
* Description:
* Initialize a console for debug output. This function is called very
* early in the intialization sequence to configure the serial console
* early in the initializeation sequence to configure the serial console
* uart (only).
*
****************************************************************************/
arch/avr/src/atmega/atmega_lowconsole.c
+1 -1
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@@ -413,7 +413,7 @@ void usart1_configure(void)
*
* Description:
* Initialize a console for debug output. This function is called very
* early in the intialization sequence to configure the serial console uart
* early in the initialization sequence to configure the serial console uart
* (only).
*
******************************************************************************/
arch/mips/src/pic32mx/pic32mx-lowconsole.c
+1 -1
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@@ -321,7 +321,7 @@ void pic32mx_uartconfigure(uintptr_t uart_base, uint32_t baudrate,
*
* Description:
* Initialize a low-level console for debug output. This function is called
* very early in the intialization sequence to configure the serial console
* very early in the initialization sequence to configure the serial console
* UART (only).
*
******************************************************************************/
arch/mips/src/pic32mx/pic32mx-usbdev.c
+1 -1
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@@ -4283,7 +4283,7 @@ void up_usbinitialize(void)
pic32mx_stateinit(priv);
/* Then perform a few one-time intialization operstions. First, initialize
/* Then perform a few one-time initialization operstions. First, initialize
* the watchdog timer that is used to perform a delayed queue restart
* after recovering from a stall.
*/
arch/rgmp/src/nuttx.c
+1 -1
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@@ -84,7 +84,7 @@ void up_initialize(void)
extern void vdev_init(void);
extern void nuttx_arch_init(void);
// intialize the current_task to g_idletcb
// initialize the current_task to g_idletcb
current_task = g_pidhash[PIDHASH(0)].tcb;
// OS memory alloc system is ready
arch/x86/src/qemu/qemu_internal.h
+1 -1
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@@ -386,7 +386,7 @@ EXTERN void i486_dmadump(DMA_HANDLE handle, const struct i486_dmaregs_s *regs,
* Description:
* These are the various ISR/IRQ vector address exported from
* qemu_vectors.S. These addresses need to have global scope so that they
* can be known to the interrupt intialization logic in qemu_irq.c.
* can be known to the interrupt initializeation logic in qemu_irq.c.
*
****************************************************************************/
arch/z80/src/ez80/ez80_startup.asm
+1 -1
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@@ -139,7 +139,7 @@ _ez80_datadone:
ldir ; Copy the code section
_ez80_codedone:
; Perform board-specific intialization
; Perform board-specific initializeation
call _ez80_lowinit