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Change order of includes in apps/Makefile; add clock frequencies to shenzhou, fire, and olimex-stm32 board.h files

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5210 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
2012-10-04 15:07:06 +00:00
parent 2df382be20
commit cfbbbcffd3
5 changed files with 34 additions and 4 deletions
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ChangeLog
+3
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@@ -3458,3 +3458,6 @@
* arch/arm/src/stm32/stm32_rng.c, chip/stm32_rng.h, and other files:
Implementation of /dev/random using the STM32 Random Number
Generator (RNG).
* board.h file for shenzhou, fire-stm32v2, and olimex-stm32-p107:
Add frequencies for HSE, HSI, LSE, and LSI. These are needed
by the STM32 watchdog driver.
arch/arm/src/stm32/stm32_eth.c
+1 -1
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@@ -1956,7 +1956,7 @@ static void stm32_polltimer(int argc, uint32_t arg, ...)
/* Check if the next TX descriptor is owned by the Ethernet DMA or CPU. We
* cannot perform the timer poll if we are unable to accept another packet
* for transmission. Hmmm.. might be bug here. Does this mean if there is
* a transmit in progress, we will missing TCP time state updates?
* a transmit in progress, we will miss TCP time state updates?
*
* In a race condition, ETH_TDES0_OWN may be cleared BUT still not available
* because stm32_freeframe() has not yet run. If stm32_freeframe() has run,
configs/fire-stm32v2/include/board.h
+10 -1
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@@ -55,10 +55,19 @@
/* Clocking *************************************************************************/
/* On-board crystal frequency is 8MHz (HSE) */
/* HSI - 8 MHz RC factory-trimmed
* LSI - 40 KHz RC (30-60KHz, uncalibrated)
* HSE - On-board crystal frequency is 8MHz
* LSE - 32.768 kHz crytal
*/
#define STM32_BOARD_XTAL 8000000ul
#define STM32_HSI_FREQUENCY 8000000ul
#define STM32_LSI_FREQUENCY 40000
#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
#define STM32_LSE_FREQUENCY 32768
/* PLL source is HSE/1, PLL multipler is 9: PLL frequency is 8MHz (XTAL) x 9 = 72MHz */
#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC
configs/olimex-stm32-p107/include/board.h
+10 -1
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@@ -55,10 +55,19 @@
/* Clocking *************************************************************************/
/* On-board crystal frequency is 25MHz (HSE) */
/* HSI - 8 MHz RC factory-trimmed
* LSI - 40 KHz RC (30-60KHz, uncalibrated)
* HSE - On-board crystal frequency is 25MHz
* LSE - 32.768 kHz
*/
#define STM32_BOARD_XTAL 25000000ul
#define STM32_HSI_FREQUENCY 8000000ul
#define STM32_LSI_FREQUENCY 40000
#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
#define STM32_LSE_FREQUENCY 32768
/* PLL ouput is 72MHz */
#define STM32_PLL_PREDIV2 RCC_CFGR2_PREDIV2d5 /* 25MHz / 5 => 5MHz */
configs/shenzhou/include/board.h
+10 -1
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@@ -55,10 +55,19 @@
/* Clocking *************************************************************************/
/* On-board crystal frequency is 25MHz (HSE) */
/* HSI - 8 MHz RC factory-trimmed
* LSI - 40 KHz RC (30-60KHz, uncalibrated)
* HSE - On-board crystal frequency is 25MHz
* LSE - 32.768 kHz
*/
#define STM32_BOARD_XTAL 25000000ul
#define STM32_HSI_FREQUENCY 8000000ul
#define STM32_LSI_FREQUENCY 40000
#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
#define STM32_LSE_FREQUENCY 32768
/* PLL ouput is 72MHz */
#define STM32_PLL_PREDIV2 RCC_CFGR2_PREDIV2d5 /* 25MHz / 5 => 5MHz */