diff --git a/ChangeLog b/ChangeLog
index 55a06aeecd4..4ea03f34f82 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -3458,3 +3458,6 @@
 	* arch/arm/src/stm32/stm32_rng.c, chip/stm32_rng.h, and other files:
 	  Implementation of /dev/random using the STM32 Random Number
 	  Generator (RNG).
+	* board.h file for shenzhou, fire-stm32v2, and olimex-stm32-p107:
+	  Add frequencies for HSE, HSI, LSE, and LSI.  These are needed
+	  by the STM32 watchdog driver.
diff --git a/arch/arm/src/stm32/stm32_eth.c b/arch/arm/src/stm32/stm32_eth.c
index 81345fabf2a..13f02679fdf 100644
--- a/arch/arm/src/stm32/stm32_eth.c
+++ b/arch/arm/src/stm32/stm32_eth.c
@@ -1956,7 +1956,7 @@ static void stm32_polltimer(int argc, uint32_t arg, ...)
   /* Check if the next TX descriptor is owned by the Ethernet DMA or CPU.  We
    * cannot perform the timer poll if we are unable to accept another packet
    * for transmission.  Hmmm.. might be bug here.  Does this mean if there is
-   * a transmit in progress, we will missing TCP time state updates?
+   * a transmit in progress, we will miss TCP time state updates?
    *
    * In a race condition, ETH_TDES0_OWN may be cleared BUT still not available
    * because stm32_freeframe() has not yet run.  If stm32_freeframe() has run,
diff --git a/configs/fire-stm32v2/include/board.h b/configs/fire-stm32v2/include/board.h
index 9a5d309ab6f..acd70933a28 100644
--- a/configs/fire-stm32v2/include/board.h
+++ b/configs/fire-stm32v2/include/board.h
@@ -55,10 +55,19 @@
 
 /* Clocking *************************************************************************/
 
-/* On-board crystal frequency is 8MHz (HSE) */
+/* HSI - 8 MHz RC factory-trimmed
+ * LSI - 40 KHz RC (30-60KHz, uncalibrated)
+ * HSE - On-board crystal frequency is 8MHz
+ * LSE - 32.768 kHz crytal
+ */
 
 #define STM32_BOARD_XTAL        8000000ul
 
+#define STM32_HSI_FREQUENCY     8000000ul
+#define STM32_LSI_FREQUENCY     40000
+#define STM32_HSE_FREQUENCY     STM32_BOARD_XTAL
+#define STM32_LSE_FREQUENCY     32768
+
 /* PLL source is HSE/1, PLL multipler is 9: PLL frequency is 8MHz (XTAL) x 9 = 72MHz */
 
 #define STM32_CFGR_PLLSRC       RCC_CFGR_PLLSRC
diff --git a/configs/olimex-stm32-p107/include/board.h b/configs/olimex-stm32-p107/include/board.h
index ce0c82472f3..96051e25c29 100644
--- a/configs/olimex-stm32-p107/include/board.h
+++ b/configs/olimex-stm32-p107/include/board.h
@@ -55,10 +55,19 @@
 
 /* Clocking *************************************************************************/
 
-/* On-board crystal frequency is 25MHz (HSE) */
+/* HSI - 8 MHz RC factory-trimmed
+ * LSI - 40 KHz RC (30-60KHz, uncalibrated)
+ * HSE - On-board crystal frequency is 25MHz
+ * LSE - 32.768 kHz
+ */
 
 #define STM32_BOARD_XTAL        25000000ul
 
+#define STM32_HSI_FREQUENCY     8000000ul
+#define STM32_LSI_FREQUENCY     40000
+#define STM32_HSE_FREQUENCY     STM32_BOARD_XTAL
+#define STM32_LSE_FREQUENCY     32768
+
 /* PLL ouput is 72MHz */
 
 #define STM32_PLL_PREDIV2       RCC_CFGR2_PREDIV2d5   /* 25MHz / 5 => 5MHz */
diff --git a/configs/shenzhou/include/board.h b/configs/shenzhou/include/board.h
index c105d4ab5ea..2897ac21986 100644
--- a/configs/shenzhou/include/board.h
+++ b/configs/shenzhou/include/board.h
@@ -55,10 +55,19 @@
 
 /* Clocking *************************************************************************/
 
-/* On-board crystal frequency is 25MHz (HSE) */
+/* HSI - 8 MHz RC factory-trimmed
+ * LSI - 40 KHz RC (30-60KHz, uncalibrated)
+ * HSE - On-board crystal frequency is 25MHz
+ * LSE - 32.768 kHz
+ */
 
 #define STM32_BOARD_XTAL        25000000ul
 
+#define STM32_HSI_FREQUENCY     8000000ul
+#define STM32_LSI_FREQUENCY     40000
+#define STM32_HSE_FREQUENCY     STM32_BOARD_XTAL
+#define STM32_LSE_FREQUENCY     32768
+
 /* PLL ouput is 72MHz */
 
 #define STM32_PLL_PREDIV2       RCC_CFGR2_PREDIV2d5   /* 25MHz / 5 => 5MHz */