This commit brings in basic support fo the i.MX RT 1050 'crossover' SoC. The basic support is complete and compiles without error, but is still untested.

This port was the joing effort of Janne Rosberg, Ivan Ucherdzhiev, and myself.  I give credit to Ivan for the kill because he is the one to held on to the end.

Squashed commit of the following:

  Author: Gregory Nutt <gnutt@nuttx.org>
    configs/imxrt1050-evk/scripts:  Add section to linker script to handle the case where RAMFUNCs are enabled.  RAMFUNCs appear to be enabled in the default configuration ... they probably should not be enabled.

  Author: Ivan Ucherdzhiev <ivanucherdjiev@gmail.com>
    arch/arm/src/imxrt:  imxrt_lowputc.c is finished. Now everything needed for the initial port is done and ready for testing.
    arch/arm/src/imxrt:  Add logic to imxrt_lowputc.c.  Still incomplete.

  Author: Ivan Ucherdzhiev <ivanucherdjiev@gmail.com>
    arch/arm/src/imxrt:  Add serial support.  configs/imxrt1050-evk:  Add linker script.

  Author: Gregory Nutt <gnutt@nuttx.org>
    arch/arm/src/imxrt:  Add initial cut at imxrt_allocateheap.c

  Author: Ivan Ucherdzhiev <ivanucherdjiev@gmail.com>
    arm/arm/src/imxrt:  Completes all definitions for PADMUX, CTLMUX, and IOMUX_INPUT and mapping tables on imxrt_gpio.c and imxr_iomuxc.c.
    arch/arm/src/imxrt/chip:  Add definitions for IMXRT_PADCTL and IMXRT_PADMUX registers.  Only the IMXRT_INPUT definitions in this commit.
    arch/arm/src/imxrt/chip:  Add more IOMUXC register definitions.

  Author: Gregory Nutt <gnutt@nuttx.org>
    configs/imxrt1050-evk:  Add STRIP definition to Make.defs.
    arch/arm/src/imxrt:  Bring in i.MX6 memory configuration settings.
    arch/arm/src/imxrt:  Remove call to non-existent imxrt_gpioinit() from imxrt_start.c.
    arch/arm/src/imxrt:  Bring in incomplete imxrt_iomuxc.c file from i.mx6.
    arch/arm/src/imxrt:  Add first cut at GPIO interrupt logic.
    arch/arm/include:  Add definitions to support a second level of GPIO pin interrupts.

  Author: Janne Rosberg <janne.rosberg@offcode.fi>
    arch/arm/src/imxrt:  Add imxrt_wdog.c/.h

  Author: Gregory Nutt <gnutt@nuttx.org>
    arch/arm/src/imxrt:  Port SAMv7 interrupt logic to imxrt_irq.c.
    arch/arm/src/imxrt:  More clarification of the start-up memory map.
    arch/arm/src/imxrt:  Some mostly cosmetic clean-up to the imxrt_start.c file that was so rudely taken from the SAMv7.
    arch/arm/src/imxrt:  Add imxrt_start.c.  Initial commit is the the SAMv7 startup logic with name changes.

  Author: Ivan Ucherdzhiev <ivanucherdjiev@gmail.com>
    arch/arm/src/imxrt:  Adds a few IOMUXC register definitions.

  Author: Janne Rosberg <janne.rosberg@offcode.fi>
    arch/arm/src/imxrt:  Add imxrt_clockconfig.c/.h
    configs/imxrt1050-evk:  Add clock configuration definitions to board.h
    arch/arm/src/imxrt:  Fix CCM register name; Fix doubly defined in LPUART bit field.
    arch/arm/src/imxrt:  Add analog defines to CCM register definition header file.

  Author: Gregory Nutt <gnutt@nuttx.org>
    arch/arm/src/imxrt:  Bring in GPIO C files from i.MX6.  Things are in disarray now because that GPIO logic depends on IOMUXC logic which is not yet in place.
    arch/arm/src/imxrt:  Add a few more GPIO definitions to make the header file compatible with i.MX6
    arch/arm/src/imxrt/chip:  Add GPIO register definition file.

  Author: Janne Rosberg <janne.rosberg@offcode.fi>
    arch/arm/src/imxrt:  Add DCDC register definitions.
    arch/arm/srch/imxrt: Add CCM register bit definitions

  Author: Gregory Nutt <gnutt@nuttx.org>
    Purely cosmetic
    arch/arm/src/imxrt:  Add system reset controller register definition header file.
    Embarassingly trivial change left in compiler.
    arch/arm/src/imxrt:  Finishes i.MX RT1050 LPUART register definition header file.
    arch/arm/src/imxrt:  Beginning of an i.MX RT1050 LPUART register definition header file.
    Some trivial things

  Author: Janne Rosberg <janne.rosberg@offcode.fi>
    arch/arm/src/imxrt:  Add imxrt_wdog.h
    arch/arm/src/imxrt:  Add initial imxrt_ccm.h

  Author: Gregory Nutt <gnutt@nuttx.org>
    Trivial update to README.
    arch/arm/src/imxrt:  The i.MX Rt implements 4 bits of interrupt priority, not two.  Thanks, Janne.
    arch/arm/src/imxrt:  Fix some initial compile issues.  Still a long way from complete, but there is a buildable environment now for the imxrt1050-evk.
    configs/imxrt1050-evk:  Add an initial NSH configuration for testing.
    configs/Kconfig:  Hook the i.MX RT 1050 board configuration into the NuttX configuration system.
    configs/imxrt_evk:  Add the framework for i.MX RT 1050 board support.
    arch/arm/src/imxrt:  Bring in a few more files from LPC54xxx.
    arch/arm/src/imxrt:  Bring in imxrt_clrpend() from the LPC54xxx.
    arch/arm/src/imxrt:  Bring in Cortex-M7 SysTick setup from the SAMv7.
    arch/arm/src/imxrt:  Add a few easy files.
    arch/arm/src/imxrt/chip:  Add memory map header files.
    arch/arm/src/imxrt:  A few basic files to start the port to the i.MX RT 1050.

Documentation/README.html

@@ -116,6 +116,8 @@ nuttx/
  |   |- hymini-stm32v/
  |   |   |- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/hymini-stm32v/RIDE/README.txt" target="_blank">RIDE/README.txt</a>
  |   |   `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/hymini-stm32v/README.txt" target="_blank"><b><i>README.txt</i></b></a>
+ |   |- imxrt1050-evk/
+ |   |   `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/imxrt1050-evk/README.txt" target="_blank"><b><i>README.txt</i></b></a>
  |   |- indium-f7/
  |   |   `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/indium-f7/README.txt" target="_blank"><b><i>README.txt</i></b></a>
  |   |- kwikstik-k40/

README.txt

@@ -1685,6 +1685,8 @@ nuttx/
  |   |   `- README.txt
  |   |- hymini-stm32v/
  |   |   `- README.txt
+ |   |- imxrt1050-evk
+ |   |   `- README.txt
  |   |- indium-f7
  |   |   `- README.txt
  |   |- kwikstik-k40/

arch/arm/Kconfig

@@ -79,6 +79,22 @@ config ARCH_CHIP_IMX6
 	---help---
 		Freescale iMX.6 architectures (Cortex-A9)
 
+config ARCH_CHIP_IMXRT
+	bool "NXP/Freescale iMX.RT"
+	select ARCH_HAVE_CMNVECTOR
+	select ARCH_CORTEXM7
+	select ARCH_HAVE_MPU
+	select ARCH_HAVE_FETCHADD
+	select ARCH_HAVE_RAMFUNCS
+	select ARCH_HAVE_TICKLESS
+	select ARCH_HAVE_I2CRESET
+	select ARCH_HAVE_SPI_CS_CONTROL
+	select ARM_HAVE_MPU_UNIFIED
+	select ARMV7M_CMNVECTOR
+	select ARMV7M_HAVE_STACKCHECK
+	---help---
+		NXP i.MX RT (ARM Cortex-M7) architectures
+
 config ARCH_CHIP_KINETIS
 	bool "NXP/Freescale Kinetis"
 	select ARCH_CORTEXM4
@@ -550,6 +566,7 @@ config ARCH_CHIP
 	default "efm32"		if ARCH_CHIP_EFM32
 	default "imx1"		if ARCH_CHIP_IMX1
 	default "imx6"		if ARCH_CHIP_IMX6
+	default "imxrt"		if ARCH_CHIP_IMXRT
 	default "kinetis"	if ARCH_CHIP_KINETIS
 	default "kl"		if ARCH_CHIP_KL
 	default "lc823450"	if ARCH_CHIP_LC823450
@@ -773,6 +790,9 @@ endif
 if ARCH_CHIP_IMX6
 source arch/arm/src/imx6/Kconfig
 endif
+if ARCH_CHIP_IMXRT
+source arch/arm/src/imxrt/Kconfig
+endif
 if ARCH_CHIP_KINETIS
 source arch/arm/src/kinetis/Kconfig
 endif

arch/arm/include/imxrt/chip.h

@@ -0,0 +1,139 @@
+/************************************************************************************
+ * arch/arm/include/imxrt/chip.h
+ *
+ *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_INCLUDE_IMXRT_CHIP_H
+#define __ARCH_ARM_INCLUDE_IMXRT_CHIP_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Get customizations for each supported chip */
+
+/* MIMXRT1051CVL5A - Industrial, Reduced Features, 528MHz
+ * MIMXRT1051CVL5A - Consumer, Reduced Features, 600MHz
+ * MIMXRT1052CVL5A - Industrial, Full Feature, 528MHz
+ * MIMXRT1052CVL5A - Consumer, Full Feature, 600MHz
+ */
+
+#if defined(CONFIG_ARCH_CHIP_MIMXRT1051DVL6A) || \
+    defined(CONFIG_ARCH_CHIP_MIMXRT1051CVL5A) || \
+    defined(CONFIG_ARCH_CHIP_MIMXRT1052DVL6A) || \
+    defined(CONFIG_ARCH_CHIP_MIMXRT1052CVL5A)
+
+#define IMXRT_OCRAM_SIZE              (512 * 1024) /* 512Kb OCRAM */
+#else
+#  error "Unknown i.MX RT chip type"
+#endif
+
+/* NVIC priority levels *************************************************************/
+/* Each priority field holds an 8-bit priority value, 0-15. The lower the value, the
+ * greater the priority of the corresponding interrupt.  The i.MX RT processor
+ * implements only  bits[7:4] of each field, bits[3:0] read as zero and ignore writes.
+ */
+
+#define NVIC_SYSH_PRIORITY_MIN        0xf0 /* All bits[7:4] set is minimum priority */
+#define NVIC_SYSH_PRIORITY_DEFAULT    0x80 /* Midpoint is the default */
+#define NVIC_SYSH_PRIORITY_MAX        0x00 /* Zero is maximum priority */
+#define NVIC_SYSH_PRIORITY_STEP       0x40 /* Two bits of interrupt priority used */
+
+/* If CONFIG_ARMV7M_USEBASEPRI is selected, then interrupts will be disabled
+ * by setting the BASEPRI register to NVIC_SYSH_DISABLE_PRIORITY so that most
+ * interrupts will not have execution priority.  SVCall must have execution
+ * priority in all cases.
+ *
+ * In the normal cases, interrupts are not nest-able and all interrupts run
+ * at an execution priority between NVIC_SYSH_PRIORITY_MIN and
+ * NVIC_SYSH_PRIORITY_MAX (with NVIC_SYSH_PRIORITY_MAX reserved for SVCall).
+ *
+ * If, in addition, CONFIG_ARCH_HIPRI_INTERRUPT is defined, then special
+ * high priority interrupts are supported.  These are not "nested" in the
+ * normal sense of the word.  These high priority interrupts can interrupt
+ * normal processing but execute outside of OS (although they can "get back
+ * into the game" via a PendSV interrupt).
+ *
+ * In the normal course of things, interrupts must occasionally be disabled
+ * using the up_irq_save() inline function to prevent contention in use of
+ * resources that may be shared between interrupt level and non-interrupt
+ * level logic.  Now the question arises, if CONFIG_ARCH_HIPRI_INTERRUPT,
+ * do we disable all interrupts (except SVCall), or do we only disable the
+ * "normal" interrupts.  Since the high priority interrupts cannot interact
+ * with the OS, you may want to permit the high priority interrupts even if
+ * interrupts are disabled.  The setting CONFIG_ARCH_INT_DISABLEALL can be
+ * used to select either behavior:
+ *
+ *   ----------------------------+--------------+----------------------------
+ *   CONFIG_ARCH_HIPRI_INTERRUPT |      NO      |             YES
+ *   ----------------------------+--------------+--------------+-------------
+ *   CONFIG_ARCH_INT_DISABLEALL  |     N/A      |     YES      |      NO
+ *   ----------------------------+--------------+--------------+-------------
+ *                               |              |              |    SVCall
+ *                               |    SVCall    |    SVCall    |    HIGH
+ *   Disable here and below --------> MAXNORMAL ---> HIGH --------> MAXNORMAL
+ *                               |              |    MAXNORMAL |
+ *   ----------------------------+--------------+--------------+-------------
+ */
+
+#if defined(CONFIG_ARCH_HIPRI_INTERRUPT) && defined(CONFIG_ARCH_INT_DISABLEALL)
+#  define NVIC_SYSH_MAXNORMAL_PRIORITY  (NVIC_SYSH_PRIORITY_MAX + 2*NVIC_SYSH_PRIORITY_STEP)
+#  define NVIC_SYSH_HIGH_PRIORITY       (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP)
+#  define NVIC_SYSH_DISABLE_PRIORITY    NVIC_SYSH_HIGH_PRIORITY
+#  define NVIC_SYSH_SVCALL_PRIORITY     NVIC_SYSH_PRIORITY_MAX
+#else
+#  define NVIC_SYSH_MAXNORMAL_PRIORITY  (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP)
+#  define NVIC_SYSH_HIGH_PRIORITY       NVIC_SYSH_PRIORITY_MAX
+#  define NVIC_SYSH_DISABLE_PRIORITY    NVIC_SYSH_MAXNORMAL_PRIORITY
+#  define NVIC_SYSH_SVCALL_PRIORITY     NVIC_SYSH_PRIORITY_MAX
+#endif
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_INCLUDE_IMXRT_CHIP_H */

arch/arm/include/imxrt/imxrt105x_irq.h

@@ -0,0 +1,467 @@
+/****************************************************************************************
+ * arch/arm/include/imxrt/imxrt105x_irq.h
+ *
+ *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************************/
+
+/* This file should never be included directed but, rather, only indirectly through
+ * nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM_INCLUDE_IMXRT_IMXRT105X_IRQ_H
+#define __ARCH_ARM_INCLUDE_IMXRT_IMXRT105X_IRQ_H
+
+/****************************************************************************************
+ * Included Files
+ ****************************************************************************************/
+
+/****************************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************************/
+
+/* External interrupts (priority levels >= 256) *****************************************/
+
+#define IMXRT_IRQ_EDMA0_16     (IMXRT_IRQ_EXTINT + 0)   /* eDMA Channel 0/16 Transfer Complete */
+#define IMXRT_IRQ_EDMA1_17     (IMXRT_IRQ_EXTINT + 1)   /* eDMA Channel 1/17 Transfer Complete */
+#define IMXRT_IRQ_EDMA2_18     (IMXRT_IRQ_EXTINT + 2)   /* eDMA Channel 2/18 Transfer Complete */
+#define IMXRT_IRQ_EDMA3_19     (IMXRT_IRQ_EXTINT + 3)   /* eDMA Channel 3/19 Transfer Complete */
+#define IMXRT_IRQ_EDMA4_20     (IMXRT_IRQ_EXTINT + 4)   /* eDMA Channel 4/20 Transfer Complete */
+#define IMXRT_IRQ_EDMA5_21     (IMXRT_IRQ_EXTINT + 5)   /* eDMA Channel 5/21 Transfer Complete */
+#define IMXRT_IRQ_EDMA6_22     (IMXRT_IRQ_EXTINT + 6)   /* eDMA Channel 6/22 Transfer Complete */
+#define IMXRT_IRQ_EDMA7_23     (IMXRT_IRQ_EXTINT + 7)   /* eDMA Channel 7/23 Transfer Complete */
+#define IMXRT_IRQ_EDMA8_24     (IMXRT_IRQ_EXTINT + 8)   /* eDMA Channel 8/24 Transfer Complete */
+#define IMXRT_IRQ_EDMA9_25     (IMXRT_IRQ_EXTINT + 9)   /* eDMA Channel 9/25 Transfer Complete */
+#define IMXRT_IRQ_EDMA0_26     (IMXRT_IRQ_EXTINT + 10)  /* eDMA Channel 10/26 Transfer Complete */
+#define IMXRT_IRQ_EDMA1_27     (IMXRT_IRQ_EXTINT + 11)  /* eDMA Channel 11/27 Transfer Complete */
+#define IMXRT_IRQ_EDMA2_28     (IMXRT_IRQ_EXTINT + 12)  /* eDMA Channel 12/28 Transfer Complete */
+#define IMXRT_IRQ_EDMA3_29     (IMXRT_IRQ_EXTINT + 13)  /* eDMA Channel 13/29 Transfer Complete */
+#define IMXRT_IRQ_EDMA4_30     (IMXRT_IRQ_EXTINT + 14)  /* eDMA Channel 14/30 Transfer Complete */
+#define IMXRT_IRQ_EDMA5_31     (IMXRT_IRQ_EXTINT + 15)  /* eDMA Channel 15/31 Transfer Complete */
+#define IMXRT_IRQ_EDMA_ERROR   (IMXRT_IRQ_EXTINT + 16)  /* Error Interrupt, Channels 0-15 / 16-31 */
+#define IMXRT_IRQ_CM70         (IMXRT_IRQ_EXTINT + 17)  /* CTI trigger outputs (internal: CTIIRQ[0]) */
+#define IMXRT_IRQ_CM71         (IMXRT_IRQ_EXTINT + 18)  /* CTI trigger outputs (internal: CTIIRQ[1]) */
+#define IMXRT_IRQ_CM7CP        (IMXRT_IRQ_EXTINT + 19)  /* CorePlatform exception IRQ */
+#define IMXRT_IRQ_LPUART1      (IMXRT_IRQ_EXTINT + 20)  /* UART1 TX/RX interrupt */
+#define IMXRT_IRQ_LPUART2      (IMXRT_IRQ_EXTINT + 21)  /* UART2 TX/RX interrupt */
+#define IMXRT_IRQ_LPUART3      (IMXRT_IRQ_EXTINT + 22)  /* UART3 TX/RX interrupt */
+#define IMXRT_IRQ_LPUART4      (IMXRT_IRQ_EXTINT + 23)  /* UART4 TX/RX interrupt */
+#define IMXRT_IRQ_LPUART5      (IMXRT_IRQ_EXTINT + 24)  /* UART5 TX/RX interrupt */
+#define IMXRT_IRQ_LPUART6      (IMXRT_IRQ_EXTINT + 25)  /* UART6 TX/RX interrupt */
+#define IMXRT_IRQ_LPUART7      (IMXRT_IRQ_EXTINT + 26)  /* UART7 TX/RX interrupt */
+#define IMXRT_IRQ_LPUART8      (IMXRT_IRQ_EXTINT + 27)  /* UART8 TX/RX interrupt */
+#define IMXRT_IRQ_LPI2C1       (IMXRT_IRQ_EXTINT + 28)  /* I2C1 Interrupt */
+#define IMXRT_IRQ_LPI2C2       (IMXRT_IRQ_EXTINT + 29)  /* I2C2 Interrupt */
+#define IMXRT_IRQ_LPI2C3       (IMXRT_IRQ_EXTINT + 30)  /* I2C3 Interrupt */
+#define IMXRT_IRQ_LPI2C4       (IMXRT_IRQ_EXTINT + 31)  /* I2C- Interrupt */
+#define IMXRT_IRQ_LPSPI1       (IMXRT_IRQ_EXTINT + 32)  /* LPSPI1 interrupt */
+#define IMXRT_IRQ_LPSPI2       (IMXRT_IRQ_EXTINT + 33)  /* LPSPI2 interrupt */
+#define IMXRT_IRQ_LPSPI3       (IMXRT_IRQ_EXTINT + 34)  /* LPSPI3 interrupt */
+#define IMXRT_IRQ_LPSPI4       (IMXRT_IRQ_EXTINT + 35)  /* LPSPI4 interrupt */
+#define IMXRT_IRQ_CAN1         (IMXRT_IRQ_EXTINT + 36)  /* CAN1 interrupt */
+#define IMXRT_IRQ_CAN2         (IMXRT_IRQ_EXTINT + 37)  /* CAN2 interrupt */
+#define IMXRT_IRQ_CM7FR        (IMXRT_IRQ_EXTINT + 38)  /* FlexRAM address fault */
+#define IMXRT_IRQ_KPP          (IMXRT_IRQ_EXTINT + 39)  /* Keypad Interrupt */
+#define IMXRT_IRQ_TSCDIG       (IMXRT_IRQ_EXTINT + 40)  /* TSC interrupt */
+#define IMXRT_IRQ_GPRIRQ       (IMXRT_IRQ_EXTINT + 41)  /* Notify cores on exception while boot */
+#define IMXRT_IRQ_LCDIF        (IMXRT_IRQ_EXTINT + 42)  /* LCDIF Sync Interrupt */
+#define IMXRT_IRQ_CSI          (IMXRT_IRQ_EXTINT + 43)  /* CSI interrupt */
+#define IMXRT_IRQ_PXP          (IMXRT_IRQ_EXTINT + 44)  /* PXP interrupt */
+#define IMXRT_IRQ_WDOG2        (IMXRT_IRQ_EXTINT + 45)  /* Watchdog Timer reset */
+#define IMXRT_IRQ_SNVS         (IMXRT_IRQ_EXTINT + 46)  /* SNVS Functional Interrupt */
+#define IMXRT_IRQ_SNVSSEC      (IMXRT_IRQ_EXTINT + 47)  /* SNVS Security Interrupt */
+#define IMXRT_IRQ_SNVSSB       (IMXRT_IRQ_EXTINT + 48)  /* ON-OFF short button press */
+#define IMXRT_IRQ_CSU          (IMXRT_IRQ_EXTINT + 49)  /* CSU Interrupt Request 1 */
+#define IMXRT_IRQ_DCP          (IMXRT_IRQ_EXTINT + 50)  /* DCP channel/CRC interrupts (channel != 0) */
+#define IMXRT_IRQ_DCP0         (IMXRT_IRQ_EXTINT + 51)  /* DCP channel 0 interrupt */
+#define IMXRT_IRQ_RESERVED52   (IMXRT_IRQ_EXTINT + 52)  /* Reserved */
+#define IMXRT_IRQ_TRNG         (IMXRT_IRQ_EXTINT + 53)  /* TRNG Interrupt */
+#define IMXRT_IRQ_SJC          (IMXRT_IRQ_EXTINT + 54)  /* SJC Interrupt from General Purpose register */
+#define IMXRT_IRQ_BEE          (IMXRT_IRQ_EXTINT + 55)  /* BEE IRQ */
+#define IMXRT_IRQ_SAI1         (IMXRT_IRQ_EXTINT + 56)  /* SAI1 interrupt */
+#define IMXRT_IRQ_SAI2         (IMXRT_IRQ_EXTINT + 57)  /* SAI2 interrupt */
+#define IMXRT_IRQ_SAI3RX       (IMXRT_IRQ_EXTINT + 58)  /* SAI3 RX interrupt */
+#define IMXRT_IRQ_SAI3TX       (IMXRT_IRQ_EXTINT + 59)  /* SAI3 TX interrupt */
+#define IMXRT_IRQ_SPDIF        (IMXRT_IRQ_EXTINT + 60)  /* SPDIF interrupt */
+#define IMXRT_IRQ_PMU          (IMXRT_IRQ_EXTINT + 61)  /* Brown-out event 1.1, 2.5 or 3.0 regulators */
+#define IMXRT_IRQ_RESERVED62   (IMXRT_IRQ_EXTINT + 62)  /* Reserved */
+#define IMXRT_IRQ_TEMP         (IMXRT_IRQ_EXTINT + 63)  /* Temperature Monitor */
+#define IMXRT_IRQ_TEMPPANIC    (IMXRT_IRQ_EXTINT + 64)  /* TempSensor panic */
+#define IMXRT_IRQ_USBPHY0      (IMXRT_IRQ_EXTINT + 65)  /* USBPHY (UTMI0) interrupt */
+#define IMXRT_IRQ_USBPHY1      (IMXRT_IRQ_EXTINT + 66)  /* USBPHY (UTMI1) interrupt */
+#define IMXRT_IRQ_ADC1         (IMXRT_IRQ_EXTINT + 67)  /* ADC1 interrupt */
+#define IMXRT_IRQ_ADC2         (IMXRT_IRQ_EXTINT + 68)  /* ADC2 interrupt */
+#define IMXRT_IRQ_DCDC         (IMXRT_IRQ_EXTINT + 69)  /* DCDC interrupt */
+#define IMXRT_IRQ_RESERVED70   (IMXRT_IRQ_EXTINT + 70)  /* Reserved */
+#define IMXRT_IRQ_RESERVED71   (IMXRT_IRQ_EXTINT + 71)  /* Reserved */
+#define IMXRT_IRQ_GPIO1_0      (IMXRT_IRQ_EXTINT + 72)  /* GPIO1 INT0 interrupt */
+#define IMXRT_IRQ_GPIO1_1      (IMXRT_IRQ_EXTINT + 73)  /* GPIO1 INT1 interrupt */
+#define IMXRT_IRQ_GPIO1_2      (IMXRT_IRQ_EXTINT + 74)  /* GPIO1 INT2 interrupt */
+#define IMXRT_IRQ_GPIO1_3      (IMXRT_IRQ_EXTINT + 75)  /* GPIO1 INT3 interrupt */
+#define IMXRT_IRQ_GPIO1_4      (IMXRT_IRQ_EXTINT + 76)  /* GPIO1 INT4 interrupt */
+#define IMXRT_IRQ_GPIO1_5      (IMXRT_IRQ_EXTINT + 77)  /* GPIO1 INT5 interrupt */
+#define IMXRT_IRQ_GPIO1_6      (IMXRT_IRQ_EXTINT + 78)  /* GPIO1 INT6 interrupt */
+#define IMXRT_IRQ_GPIO1_7      (IMXRT_IRQ_EXTINT + 79)  /* GPIO1 INT7 interrupt */
+#define IMXRT_IRQ_GPIO1_0_15   (IMXRT_IRQ_EXTINT + 80)  /* GPIO1 INT0-15 interrupt */
+#define IMXRT_IRQ_GPIO1_16_31  (IMXRT_IRQ_EXTINT + 81)  /* GPIO1 INT16-31 interrupt */
+#define IMXRT_IRQ_GPIO2_0_15   (IMXRT_IRQ_EXTINT + 82)  /* GPIO2 INT0-15 interrupt */
+#define IMXRT_IRQ_GPIO2_16_31  (IMXRT_IRQ_EXTINT + 83)  /* GPIO2 INT16-31 interrupt */
+#define IMXRT_IRQ_GPIO3_0_15   (IMXRT_IRQ_EXTINT + 84)  /* GPIO3 INT0-15 interrupt */
+#define IMXRT_IRQ_GPIO3_16_31  (IMXRT_IRQ_EXTINT + 85)  /* GPIO3 INT16-31 interrupt */
+#define IMXRT_IRQ_GPIO4_0_15   (IMXRT_IRQ_EXTINT + 86)  /* GPIO4 INT0-15 interrupt */
+#define IMXRT_IRQ_GPIO4_16_31  (IMXRT_IRQ_EXTINT + 87)  /* GPIO4 INT16-31 interrupt */
+#define IMXRT_IRQ_GPIO5_0_15   (IMXRT_IRQ_EXTINT + 88)  /* GPIO5 INT0-15 interrupt */
+#define IMXRT_IRQ_GPIO5_16_31  (IMXRT_IRQ_EXTINT + 89)  /* GPIO5 INT16-31 interrupt */
+#define IMXRT_IRQ_FLEXIO1      (IMXRT_IRQ_EXTINT + 90)  /* IPI compare interrupt */
+#define IMXRT_IRQ_FLEXIO2      (IMXRT_IRQ_EXTINT + 91)  /* IPI compare interrupt */
+#define IMXRT_IRQ_WDOG1        (IMXRT_IRQ_EXTINT + 92)  /* Watchdog Timer reset */
+#define IMXRT_IRQ_RTWDOG       (IMXRT_IRQ_EXTINT + 93)  /* Watchdog Timer reset */
+#define IMXRT_IRQ_EWM          (IMXRT_IRQ_EXTINT + 94)  /* EWM interrupt */
+#define IMXRT_IRQ_CCM_1        (IMXRT_IRQ_EXTINT + 95)  /* CCM interrupt 1 */
+#define IMXRT_IRQ_CCM_2        (IMXRT_IRQ_EXTINT + 96)  /* CCM interrupt 2 */
+#define IMXRT_IRQ_GPC          (IMXRT_IRQ_EXTINT + 97)  /* GPC interrupt 1 */
+#define IMXRT_IRQ_SRC          (IMXRT_IRQ_EXTINT + 98)  /* SRC interrupt */
+#define IMXRT_IRQ_RESERVED99   (IMXRT_IRQ_EXTINT + 99)  /* Reserved */
+#define IMXRT_IRQ_GPT1         (IMXRT_IRQ_EXTINT + 100) /* GPT1 interrupt */
+#define IMXRT_IRQ_GPT2         (IMXRT_IRQ_EXTINT + 101) /*  GPT2 interrupt */
+#define IMXRT_IRQ_FLEXPWM1_0   (IMXRT_IRQ_EXTINT + 102) /* FLEXPWM1 capture/compare/reload 0 interrupt */
+#define IMXRT_IRQ_FLEXPWM1_1   (IMXRT_IRQ_EXTINT + 103) /* FLEXPWM1 capture/compare/reload 1 interrupt */
+#define IMXRT_IRQ_FLEXPWM1_2   (IMXRT_IRQ_EXTINT + 104) /* FLEXPWM1 capture/compare/reload 2 interrupt */
+#define IMXRT_IRQ_FLEXPWM1_3   (IMXRT_IRQ_EXTINT + 105) /* FLEXPWM1 capture/compare/reload 3 interrupt */
+#define IMXRT_IRQ_FLEXPWM1_F   (IMXRT_IRQ_EXTINT + 106) /* FLEXPWM1 fault interrupt */
+#define IMXRT_IRQ_RESERVED107  (IMXRT_IRQ_EXTINT + 107) /* Reserved */
+#define IMXRT_IRQ_FLEXSPI      (IMXRT_IRQ_EXTINT + 108) /* FlexSPI interrupt */
+#define IMXRT_IRQ_SEMC         (IMXRT_IRQ_EXTINT + 109) /* SEMC interrupt */
+#define IMXRT_IRQ_USDHC1       (IMXRT_IRQ_EXTINT + 110) /* USDHC1 interrupt */
+#define IMXRT_IRQ_USDHC2       (IMXRT_IRQ_EXTINT + 111) /* USDHC2 interrupt */
+#define IMXRT_IRQ_USBOTG2      (IMXRT_IRQ_EXTINT + 112) /* USBO2 USB OTG2 interrupt */
+#define IMXRT_IRQ_USBOTG1      (IMXRT_IRQ_EXTINT + 113) /* USBO2 USB OTG1 interrupt */
+#define IMXRT_IRQ_ENET         (IMXRT_IRQ_EXTINT + 114) /* ENET MAC 0 interrupt */
+#define IMXRT_IRQ_ENET1588     (IMXRT_IRQ_EXTINT + 115) /* ENET MAC 0 1588 Timer Interrupt */
+#define IMXRT_IRQ_XBAR1_0_1    (IMXRT_IRQ_EXTINT + 116) /* XBAR1 interrupt 0/1 */
+#define IMXRT_IRQ_XBAR1_2_3    (IMXRT_IRQ_EXTINT + 117) /* XBAR1 interrupt 2/3 */
+#define IMXRT_IRQ_ADCETC_0     (IMXRT_IRQ_EXTINT + 118) /* ADC_ETC interrupt 0 */
+#define IMXRT_IRQ_ADCETC_1     (IMXRT_IRQ_EXTINT + 119) /* ADC_ETC interrupt 1 */
+#define IMXRT_IRQ_ADCETC_2     (IMXRT_IRQ_EXTINT + 120) /* ADC_ETC interrupt 2 */
+#define IMXRT_IRQ_ADCETC_ERR   (IMXRT_IRQ_EXTINT + 121) /* ADC_ETC error interrupt */
+#define IMXRT_IRQ_PIT          (IMXRT_IRQ_EXTINT + 122) /* PIT interrupt */
+#define IMXRT_IRQ_ACMP1        (IMXRT_IRQ_EXTINT + 123) /* ACMP1 interrupt */
+#define IMXRT_IRQ_ACMP2        (IMXRT_IRQ_EXTINT + 124) /* ACMP2 interrupt */
+#define IMXRT_IRQ_ACMP3        (IMXRT_IRQ_EXTINT + 125) /* ACMP3 interrupt */
+#define IMXRT_IRQ_ACMP4        (IMXRT_IRQ_EXTINT + 126) /* ACMP4 interrupt */
+#define IMXRT_IRQ_RESERVED127  (IMXRT_IRQ_EXTINT + 127) /* Reserved */
+#define IMXRT_IRQ_RESERVED128  (IMXRT_IRQ_EXTINT + 128) /* Reserved  */
+#define IMXRT_IRQ_ENC1         (IMXRT_IRQ_EXTINT + 129) /* ENC1 interrupt */
+#define IMXRT_IRQ_ENC2         (IMXRT_IRQ_EXTINT + 130) /* ENC2 interrupt */
+#define IMXRT_IRQ_ENC3         (IMXRT_IRQ_EXTINT + 131) /* ENC3 interrupt */
+#define IMXRT_IRQ_ENC4         (IMXRT_IRQ_EXTINT + 132) /* ENC4 interrupt */
+#define IMXRT_IRQ_QTIMER1      (IMXRT_IRQ_EXTINT + 133) /* QTIMER1 timer 0-3 interrupt */
+#define IMXRT_IRQ_QTIMER2      (IMXRT_IRQ_EXTINT + 134) /* QTIMER2 timer 0-3 interrupt */
+#define IMXRT_IRQ_QTIMER3      (IMXRT_IRQ_EXTINT + 135) /* QTIMER3 timer 0-3 interrupt */
+#define IMXRT_IRQ_QTIMER4      (IMXRT_IRQ_EXTINT + 136) /* QTIMER4 timer 0-3 interrupt */
+#define IMXRT_IRQ_FLEXPWM2_0   (IMXRT_IRQ_EXTINT + 137) /* LEXPWM2 capture/compare/reload 0 interrupt */
+#define IMXRT_IRQ_FLEXPWM2_1   (IMXRT_IRQ_EXTINT + 138) /* LEXPWM2 capture/compare/reload 1 interrupt */
+#define IMXRT_IRQ_FLEXPWM2_2   (IMXRT_IRQ_EXTINT + 139) /* LEXPWM2 capture/compare/reload 1 interrupt */
+#define IMXRT_IRQ_FLEXPWM2_3   (IMXRT_IRQ_EXTINT + 140) /* LEXPWM2 capture/compare/reload 3 interrupt */
+#define IMXRT_IRQ_FLEXPWM2_F   (IMXRT_IRQ_EXTINT + 141) /* LEXPWM2 fault interrupt */
+#define IMXRT_IRQ_FLEXPWM3_0   (IMXRT_IRQ_EXTINT + 142) /* LEXPWM3 capture/compare/reload 0 interrupt */
+#define IMXRT_IRQ_FLEXPWM3_1   (IMXRT_IRQ_EXTINT + 143) /* LEXPWM3 capture/compare/reload 1 interrupt */
+#define IMXRT_IRQ_FLEXPWM3_2   (IMXRT_IRQ_EXTINT + 144) /* LEXPWM3 capture/compare/reload 2 interrupt */
+#define IMXRT_IRQ_FLEXPWM3_F   (IMXRT_IRQ_EXTINT + 146) /* LEXPWM3 fault interrupt */
+#define IMXRT_IRQ_FLEXPWM4_0   (IMXRT_IRQ_EXTINT + 147) /* LEXPWM4 capture/compare/reload 0 interrupt */
+#define IMXRT_IRQ_FLEXPWM4_1   (IMXRT_IRQ_EXTINT + 148) /* LEXPWM4 capture/compare/reload 1 interrupt */
+#define IMXRT_IRQ_FLEXPWM4_2   (IMXRT_IRQ_EXTINT + 149) /* LEXPWM4 capture/compare/reload 2 interrupt */
+#define IMXRT_IRQ_FLEXPWM4_3   (IMXRT_IRQ_EXTINT + 150) /* LEXPWM4 capture/compare/reload 3 interrupt */
+#define IMXRT_IRQ_FLEXPWM4_F   (IMXRT_IRQ_EXTINT + 151) /* LEXPWM4 fault interrupt */
+#define IMXRT_IRQ_RESERVED152  (IMXRT_IRQ_EXTINT + 152) /* Reserved */
+#define IMXRT_IRQ_RESERVED153  (IMXRT_IRQ_EXTINT + 153) /* Reserved */
+#define IMXRT_IRQ_RESERVED154  (IMXRT_IRQ_EXTINT + 154) /* Reserved */
+#define IMXRT_IRQ_RESERVED155  (IMXRT_IRQ_EXTINT + 155) /* Reserved */
+#define IMXRT_IRQ_RESERVED156  (IMXRT_IRQ_EXTINT + 156) /* Reserved */
+#define IMXRT_IRQ_RESERVED157  (IMXRT_IRQ_EXTINT + 157) /* Reserved */
+#define IMXRT_IRQ_RESERVED158  (IMXRT_IRQ_EXTINT + 158) /* Reserved */
+#define IMXRT_IRQ_RESERVED159  (IMXRT_IRQ_EXTINT + 159) /* Reserved */
+
+#define IMXRT_IRQ_NEXTINT      160
+
+/* GPIO second level interrupt **********************************************************/
+
+#define IMXRT_GPIO_IRQ_FIRST   (IMXRT_IRQ_EXTINT + IMXRT_IRQ_NEXTINT)
+#define _IMXRT_GPIO1_0_15_BASE IMXRT_GPIO_IRQ_FIRST
+
+#ifdef CONFIG_IMXRT_GPIO1_0_15_IRQ
+  /* GPIO1 has dedicated interrupts for pins 0-7
+   * REVISIT:  I am assuming that you really cannot use the dedicated and the multiplex
+   * interrupts concurrently.
+   */
+
+#  define IMXRT_IRQ_GPIO1_0    (_IMXRT_GPIO1_0_15_BASE + 0)   /* GPIO1 pin 8 interrupt */
+#  define IMXRT_IRQ_GPIO1_1    (_IMXRT_GPIO1_0_15_BASE + 1)   /* GPIO1 pin 8 interrupt */
+#  define IMXRT_IRQ_GPIO1_2    (_IMXRT_GPIO1_0_15_BASE + 2)   /* GPIO1 pin 8 interrupt */
+#  define IMXRT_IRQ_GPIO1_3    (_IMXRT_GPIO1_0_15_BASE + 3)   /* GPIO1 pin 8 interrupt */
+#  define IMXRT_IRQ_GPIO1_4    (_IMXRT_GPIO1_0_15_BASE + 4)   /* GPIO1 pin 8 interrupt */
+#  define IMXRT_IRQ_GPIO1_5    (_IMXRT_GPIO1_0_15_BASE + 5)   /* GPIO1 pin 8 interrupt */
+#  define IMXRT_IRQ_GPIO1_6    (_IMXRT_GPIO1_0_15_BASE + 6)   /* GPIO1 pin 8 interrupt */
+#  define IMXRT_IRQ_GPIO1_7    (_IMXRT_GPIO1_0_15_BASE + 7)   /* GPIO1 pin 8 interrupt */
+#  define IMXRT_IRQ_GPIO1_8    (_IMXRT_GPIO1_0_15_BASE + 8)   /* GPIO1 pin 8 interrupt */
+#  define IMXRT_IRQ_GPIO1_9    (_IMXRT_GPIO1_0_15_BASE + 9)   /* GPIO1 pin 9 interrupt */
+#  define IMXRT_IRQ_GPIO1_10   (_IMXRT_GPIO1_0_15_BASE + 10)  /* GPIO1 pin 10 interrupt */
+#  define IMXRT_IRQ_GPIO1_11   (_IMXRT_GPIO1_0_15_BASE + 11)  /* GPIO1 pin 11 interrupt */
+#  define IMXRT_IRQ_GPIO1_12   (_IMXRT_GPIO1_0_15_BASE + 12)  /* GPIO1 pin 12 interrupt */
+#  define IMXRT_IRQ_GPIO1_13   (_IMXRT_GPIO1_0_15_BASE + 13)  /* GPIO1 pin 13 interrupt */
+#  define IMXRT_IRQ_GPIO1_14   (_IMXRT_GPIO1_0_15_BASE + 14)  /* GPIO1 pin 14 interrupt */
+#  define IMXRT_IRQ_GPIO1_15   (_IMXRT_GPIO1_0_15_BASE + 15)  /* GPIO1 pin 15 interrupt */
+
+#  define _IMXRT_GPIO1_8_15_NIRQS 16
+#  define _IMXRT_GPIO1_16_31_BASE (_IMXRT_GPIO1_0_15_BASE + _IMXRT_GPIO1_8_15_NIRQS)
+#else
+#  define _IMXRT_GPIO1_8_15_NIRQS 0
+#  define _IMXRT_GPIO1_16_31_BASE _IMXRT_GPIO1_0_15_BASE
+#endif
+
+#ifdef CONFIG_IMXRT_GPIO1_16_31_IRQ
+#  define IMXRT_IRQ_GPIO1_16   (_IMXRT_GPIO1_16_31_BASE + 0)  /* GPIO1 pin 16 interrupt */
+#  define IMXRT_IRQ_GPIO1_17   (_IMXRT_GPIO1_16_31_BASE + 1)  /* GPIO1 pin 17 interrupt */
+#  define IMXRT_IRQ_GPIO1_18   (_IMXRT_GPIO1_16_31_BASE + 2)  /* GPIO1 pin 18 interrupt */
+#  define IMXRT_IRQ_GPIO1_19   (_IMXRT_GPIO1_16_31_BASE + 3)  /* GPIO1 pin 19 interrupt */
+#  define IMXRT_IRQ_GPIO1_20   (_IMXRT_GPIO1_16_31_BASE + 4)  /* GPIO1 pin 10 interrupt */
+#  define IMXRT_IRQ_GPIO1_21   (_IMXRT_GPIO1_16_31_BASE + 5)  /* GPIO1 pin 21 interrupt */
+#  define IMXRT_IRQ_GPIO1_22   (_IMXRT_GPIO1_16_31_BASE + 6)  /* GPIO1 pin 22 interrupt */
+#  define IMXRT_IRQ_GPIO1_23   (_IMXRT_GPIO1_16_31_BASE + 7)  /* GPIO1 pin 23 interrupt */
+#  define IMXRT_IRQ_GPIO1_24   (_IMXRT_GPIO1_16_31_BASE + 8)  /* GPIO1 pin 24 interrupt */
+#  define IMXRT_IRQ_GPIO1_25   (_IMXRT_GPIO1_16_31_BASE + 9)  /* GPIO1 pin 25 interrupt */
+#  define IMXRT_IRQ_GPIO1_26   (_IMXRT_GPIO1_16_31_BASE + 10) /* GPIO1 pin 26 interrupt */
+#  define IMXRT_IRQ_GPIO1_27   (_IMXRT_GPIO1_16_31_BASE + 11) /* GPIO1 pin 27 interrupt */
+#  define IMXRT_IRQ_GPIO1_28   (_IMXRT_GPIO1_16_31_BASE + 12) /* GPIO1 pin 28 interrupt */
+#  define IMXRT_IRQ_GPIO1_29   (_IMXRT_GPIO1_16_31_BASE + 13) /* GPIO1 pin 29 interrupt */
+#  define IMXRT_IRQ_GPIO1_30   (_IMXRT_GPIO1_16_31_BASE + 14) /* GPIO1 pin 30 interrupt */
+#  define IMXRT_IRQ_GPIO1_31   (_IMXRT_GPIO1_16_31_BASE + 15) /* GPIO1 pin 31 interrupt */
+
+#  define _IMXRT_GPIO1_16_31_NIRQS 16
+#  define _IMXRT_GPIO2_0_15_BASE (_IMXRT_GPIO1_16_31_BASE + _IMXRT_GPIO1_16_31_NIRQS)
+#  define IMXRT_GPIO1_NIRQS    (_IMXRT_GPIO1_8_15_NIRQS + _IMXRT_GPIO1_16_31_NIRQS)
+#else
+#  define _IMXRT_GPIO2_0_15_BASE _IMXRT_GPIO1_16_31_BASE
+#  define IMXRT_GPIO1_NIRQS    _IMXRT_GPIO1_8_15_NIRQS
+#endif
+
+#ifdef CONFIG_IMXRT_GPIO2_0_15_IRQ
+#  define IMXRT_IRQ_GPIO2_16   (_IMXRT_GPIO2_0_15_BASE + 0)   /* GPIO2 pin 0 interrupt */
+#  define IMXRT_IRQ_GPIO2_17   (_IMXRT_GPIO2_0_15_BASE + 1)   /* GPIO2 pin 1 interrupt */
+#  define IMXRT_IRQ_GPIO2_18   (_IMXRT_GPIO2_0_15_BASE + 2)   /* GPIO2 pin 2 interrupt */
+#  define IMXRT_IRQ_GPIO2_19   (_IMXRT_GPIO2_0_15_BASE + 3)   /* GPIO2 pin 3 interrupt */
+#  define IMXRT_IRQ_GPIO2_20   (_IMXRT_GPIO2_0_15_BASE + 4)   /* GPIO2 pin 4 interrupt */
+#  define IMXRT_IRQ_GPIO2_21   (_IMXRT_GPIO2_0_15_BASE + 5)   /* GPIO2 pin 5 interrupt */
+#  define IMXRT_IRQ_GPIO2_22   (_IMXRT_GPIO2_0_15_BASE + 6)   /* GPIO2 pin 6 interrupt */
+#  define IMXRT_IRQ_GPIO2_23   (_IMXRT_GPIO2_0_15_BASE + 7)   /* GPIO2 pin 7 interrupt */
+#  define IMXRT_IRQ_GPIO2_24   (_IMXRT_GPIO2_0_15_BASE + 8)   /* GPIO2 pin 8 interrupt */
+#  define IMXRT_IRQ_GPIO2_25   (_IMXRT_GPIO2_0_15_BASE + 9)   /* GPIO2 pin 9 interrupt */
+#  define IMXRT_IRQ_GPIO2_26   (_IMXRT_GPIO2_0_15_BASE + 10)  /* GPIO2 pin 10 interrupt */
+#  define IMXRT_IRQ_GPIO2_27   (_IMXRT_GPIO2_0_15_BASE + 11)  /* GPIO2 pin 11 interrupt */
+#  define IMXRT_IRQ_GPIO2_28   (_IMXRT_GPIO2_0_15_BASE + 12)  /* GPIO2 pin 12 interrupt */
+#  define IMXRT_IRQ_GPIO2_29   (_IMXRT_GPIO2_0_15_BASE + 13)  /* GPIO2 pin 13 interrupt */
+#  define IMXRT_IRQ_GPIO2_30   (_IMXRT_GPIO2_0_15_BASE + 14)  /* GPIO2 pin 14 interrupt */
+#  define IMXRT_IRQ_GPIO2_31   (_IMXRT_GPIO2_0_15_BASE + 15)  /* GPIO2 pin 15 interrupt */
+
+#  define _IMXRT_GPIO2_0_15_NIRQS 16
+#  define _IMXRT_GPIO2_16_31_BASE (_IMXRT_GPIO2_0_15_BASE + _IMXRT_GPIO2_0_15_NIRQS)
+#else
+#  define _IMXRT_GPIO2_0_15_NIRQS 0
+#  define _IMXRT_GPIO2_16_31_BASE _IMXRT_GPIO2_0_15_BASE
+#endif
+
+#ifdef CONFIG_IMXRT_GPIO2_16_31_IRQ
+#  define IMXRT_IRQ_GPIO2_16   (_IMXRT_GPIO2_16_31_BASE + 0)  /* GPIO2 pin 16 interrupt */
+#  define IMXRT_IRQ_GPIO2_17   (_IMXRT_GPIO2_16_31_BASE + 1)  /* GPIO2 pin 17 interrupt */
+#  define IMXRT_IRQ_GPIO2_18   (_IMXRT_GPIO2_16_31_BASE + 2)  /* GPIO2 pin 18 interrupt */
+#  define IMXRT_IRQ_GPIO2_19   (_IMXRT_GPIO2_16_31_BASE + 3)  /* GPIO2 pin 19 interrupt */
+#  define IMXRT_IRQ_GPIO2_20   (_IMXRT_GPIO2_16_31_BASE + 4)  /* GPIO2 pin 20 interrupt */
+#  define IMXRT_IRQ_GPIO2_21   (_IMXRT_GPIO2_16_31_BASE + 5)  /* GPIO2 pin 21 interrupt */
+#  define IMXRT_IRQ_GPIO2_22   (_IMXRT_GPIO2_16_31_BASE + 6)  /* GPIO2 pin 22 interrupt */
+#  define IMXRT_IRQ_GPIO2_23   (_IMXRT_GPIO2_16_31_BASE + 7)  /* GPIO2 pin 23 interrupt */
+#  define IMXRT_IRQ_GPIO2_24   (_IMXRT_GPIO2_16_31_BASE + 8)  /* GPIO2 pin 24 interrupt */
+#  define IMXRT_IRQ_GPIO2_25   (_IMXRT_GPIO2_16_31_BASE + 9)  /* GPIO2 pin 25 interrupt */
+#  define IMXRT_IRQ_GPIO2_26   (_IMXRT_GPIO2_16_31_BASE + 10) /* GPIO2 pin 26 interrupt */
+#  define IMXRT_IRQ_GPIO2_27   (_IMXRT_GPIO2_16_31_BASE + 11) /* GPIO2 pin 27 interrupt */
+#  define IMXRT_IRQ_GPIO2_28   (_IMXRT_GPIO2_16_31_BASE + 12) /* GPIO2 pin 28 interrupt */
+#  define IMXRT_IRQ_GPIO2_29   (_IMXRT_GPIO2_16_31_BASE + 13) /* GPIO2 pin 29 interrupt */
+#  define IMXRT_IRQ_GPIO2_30   (_IMXRT_GPIO2_16_31_BASE + 14) /* GPIO2 pin 30 interrupt */
+#  define IMXRT_IRQ_GPIO2_31   (_IMXRT_GPIO2_16_31_BASE + 15) /* GPIO2 pin 31 interrupt */
+
+#  define _IMXRT_GPIO2_16_31_NIRQS 16
+#  define _IMXRT_GPIO3_0_15_BASE (_IMXRT_GPIO2_16_31_BASE + _IMXRT_GPIO2_16_31_NIRQS)
+#  define IMXRT_GPIO2_NIRQS    (_IMXRT_GPIO2_0_15_NIRQS + _IMXRT_GPIO2_16_31_NIRQS)
+#else
+#  define _IMXRT_GPIO3_0_15_BASE _IMXRT_GPIO2_16_31_BASE
+#  define IMXRT_GPIO2_NIRQS    _IMXRT_GPIO2_0_15_NIRQS
+#endif
+
+#ifdef CONFIG_IMXRT_GPIO3_0_15_IRQ
+#  define IMXRT_IRQ_GPIO3_16   (_IMXRT_GPIO3_0_15_BASE + 0)   /* GPIO3 pin 0 interrupt */
+#  define IMXRT_IRQ_GPIO3_17   (_IMXRT_GPIO3_0_15_BASE + 1)   /* GPIO3 pin 1 interrupt */
+#  define IMXRT_IRQ_GPIO3_18   (_IMXRT_GPIO3_0_15_BASE + 2)   /* GPIO3 pin 2 interrupt */
+#  define IMXRT_IRQ_GPIO3_19   (_IMXRT_GPIO3_0_15_BASE + 3)   /* GPIO3 pin 3 interrupt */
+#  define IMXRT_IRQ_GPIO3_20   (_IMXRT_GPIO3_0_15_BASE + 4)   /* GPIO3 pin 4 interrupt */
+#  define IMXRT_IRQ_GPIO3_21   (_IMXRT_GPIO3_0_15_BASE + 5)   /* GPIO3 pin 5 interrupt */
+#  define IMXRT_IRQ_GPIO3_22   (_IMXRT_GPIO3_0_15_BASE + 6)   /* GPIO3 pin 6 interrupt */
+#  define IMXRT_IRQ_GPIO3_23   (_IMXRT_GPIO3_0_15_BASE + 7)   /* GPIO3 pin 7 interrupt */
+#  define IMXRT_IRQ_GPIO3_24   (_IMXRT_GPIO3_0_15_BASE + 8)   /* GPIO3 pin 8 interrupt */
+#  define IMXRT_IRQ_GPIO3_25   (_IMXRT_GPIO3_0_15_BASE + 9)   /* GPIO3 pin 9 interrupt */
+#  define IMXRT_IRQ_GPIO3_26   (_IMXRT_GPIO3_0_15_BASE + 10)  /* GPIO3 pin 10 interrupt */
+#  define IMXRT_IRQ_GPIO3_27   (_IMXRT_GPIO3_0_15_BASE + 11)  /* GPIO3 pin 11 interrupt */
+#  define IMXRT_IRQ_GPIO3_28   (_IMXRT_GPIO3_0_15_BASE + 12)  /* GPIO3 pin 12 interrupt */
+#  define IMXRT_IRQ_GPIO3_29   (_IMXRT_GPIO3_0_15_BASE + 13)  /* GPIO3 pin 13 interrupt */
+#  define IMXRT_IRQ_GPIO3_30   (_IMXRT_GPIO3_0_15_BASE + 14)  /* GPIO3 pin 14 interrupt */
+#  define IMXRT_IRQ_GPIO3_31   (_IMXRT_GPIO3_0_15_BASE + 15)  /* GPIO3 pin 15 interrupt */
+
+#  define _IMXRT_GPIO3_0_15_NIRQS 16
+#  define _IMXRT_GPIO3_16_31_BASE (_IMXRT_GPIO3_0_15_BASE + _IMXRT_GPIO3_0_15_NIRQS)
+#else
+#  define _IMXRT_GPIO3_0_15_NIRQS 0
+#  define _IMXRT_GPIO3_16_31_BASE _IMXRT_GPIO3_0_15_BASE
+#endif
+
+#ifdef CONFIG_IMXRT_GPIO3_16_31_IRQ
+#  define IMXRT_IRQ_GPIO3_16   (_IMXRT_GPIO3_16_31_BASE + 0)  /* GPIO3 pin 16 interrupt */
+#  define IMXRT_IRQ_GPIO3_17   (_IMXRT_GPIO3_16_31_BASE + 1)  /* GPIO3 pin 17 interrupt */
+#  define IMXRT_IRQ_GPIO3_18   (_IMXRT_GPIO3_16_31_BASE + 2)  /* GPIO3 pin 18 interrupt */
+#  define IMXRT_IRQ_GPIO3_19   (_IMXRT_GPIO3_16_31_BASE + 3)  /* GPIO3 pin 19 interrupt */
+#  define IMXRT_IRQ_GPIO3_20   (_IMXRT_GPIO3_16_31_BASE + 4)  /* GPIO3 pin 20 interrupt */
+#  define IMXRT_IRQ_GPIO3_21   (_IMXRT_GPIO3_16_31_BASE + 5)  /* GPIO3 pin 21 interrupt */
+#  define IMXRT_IRQ_GPIO3_22   (_IMXRT_GPIO3_16_31_BASE + 6)  /* GPIO3 pin 22 interrupt */
+#  define IMXRT_IRQ_GPIO3_23   (_IMXRT_GPIO3_16_31_BASE + 7)  /* GPIO3 pin 23 interrupt */
+#  define IMXRT_IRQ_GPIO3_24   (_IMXRT_GPIO3_16_31_BASE + 8)  /* GPIO3 pin 24 interrupt */
+#  define IMXRT_IRQ_GPIO3_25   (_IMXRT_GPIO3_16_31_BASE + 9)  /* GPIO3 pin 25 interrupt */
+#  define IMXRT_IRQ_GPIO3_26   (_IMXRT_GPIO3_16_31_BASE + 10) /* GPIO3 pin 26 interrupt */
+#  define IMXRT_IRQ_GPIO3_27   (_IMXRT_GPIO3_16_31_BASE + 11) /* GPIO3 pin 27 interrupt */
+#  define IMXRT_IRQ_GPIO3_28   (_IMXRT_GPIO3_16_31_BASE + 12) /* GPIO3 pin 28 interrupt */
+#  define IMXRT_IRQ_GPIO3_29   (_IMXRT_GPIO3_16_31_BASE + 13) /* GPIO3 pin 29 interrupt */
+#  define IMXRT_IRQ_GPIO3_30   (_IMXRT_GPIO3_16_31_BASE + 14) /* GPIO3 pin 30 interrupt */
+#  define IMXRT_IRQ_GPIO3_31   (_IMXRT_GPIO3_16_31_BASE + 15) /* GPIO3 pin 31 interrupt */
+
+#  define _IMXRT_GPIO3_16_31_NIRQS 16
+#  define _IMXRT_GPIO4_0_15_BASE (_IMXRT_GPIO3_16_31_BASE + _IMXRT_GPIO3_16_31_NIRQS)
+#  define IMXRT_GPIO3_NIRQS    (_IMXRT_GPIO3_0_15_NIRQS + _IMXRT_GPIO3_16_31_NIRQS)
+#else
+#  define _IMXRT_GPIO4_0_15_BASE _IMXRT_GPIO3_16_31_BASE
+#  define IMXRT_GPIO3_NIRQS    _IMXRT_GPIO3_0_15_NIRQS
+#endif
+
+#ifdef CONFIG_IMXRT_GPIO4_0_15_IRQ
+#  define IMXRT_IRQ_GPIO4_16   (_IMXRT_GPIO4_0_15_BASE + 0)   /* GPIO4 pin 0 interrupt */
+#  define IMXRT_IRQ_GPIO4_17   (_IMXRT_GPIO4_0_15_BASE + 1)   /* GPIO4 pin 1 interrupt */
+#  define IMXRT_IRQ_GPIO4_18   (_IMXRT_GPIO4_0_15_BASE + 2)   /* GPIO4 pin 2 interrupt */
+#  define IMXRT_IRQ_GPIO4_19   (_IMXRT_GPIO4_0_15_BASE + 3)   /* GPIO4 pin 3 interrupt */
+#  define IMXRT_IRQ_GPIO4_20   (_IMXRT_GPIO4_0_15_BASE + 4)   /* GPIO4 pin 4 interrupt */
+#  define IMXRT_IRQ_GPIO4_21   (_IMXRT_GPIO4_0_15_BASE + 5)   /* GPIO4 pin 5 interrupt */
+#  define IMXRT_IRQ_GPIO4_22   (_IMXRT_GPIO4_0_15_BASE + 6)   /* GPIO4 pin 6 interrupt */
+#  define IMXRT_IRQ_GPIO4_23   (_IMXRT_GPIO4_0_15_BASE + 7)   /* GPIO4 pin 7 interrupt */
+#  define IMXRT_IRQ_GPIO4_24   (_IMXRT_GPIO4_0_15_BASE + 8)   /* GPIO4 pin 8 interrupt */
+#  define IMXRT_IRQ_GPIO4_25   (_IMXRT_GPIO4_0_15_BASE + 9)   /* GPIO4 pin 9 interrupt */
+#  define IMXRT_IRQ_GPIO4_26   (_IMXRT_GPIO4_0_15_BASE + 10)  /* GPIO4 pin 10 interrupt */
+#  define IMXRT_IRQ_GPIO4_27   (_IMXRT_GPIO4_0_15_BASE + 11)  /* GPIO4 pin 11 interrupt */
+#  define IMXRT_IRQ_GPIO4_28   (_IMXRT_GPIO4_0_15_BASE + 12)  /* GPIO4 pin 12 interrupt */
+#  define IMXRT_IRQ_GPIO4_29   (_IMXRT_GPIO4_0_15_BASE + 13)  /* GPIO4 pin 13 interrupt */
+#  define IMXRT_IRQ_GPIO4_30   (_IMXRT_GPIO4_0_15_BASE + 14)  /* GPIO4 pin 14 interrupt */
+#  define IMXRT_IRQ_GPIO4_31   (_IMXRT_GPIO4_0_15_BASE + 15)  /* GPIO4 pin 15 interrupt */
+
+#  define _IMXRT_GPIO4_0_15_NIRQS 16
+#  define _IMXRT_GPIO4_16_31_BASE (_IMXRT_GPIO4_0_15_BASE + _IMXRT_GPIO4_0_15_NIRQS)
+#else
+#  define _IMXRT_GPIO4_0_15_NIRQS 0
+#  define _IMXRT_GPIO4_16_31_BASE _IMXRT_GPIO4_0_15_BASE
+#endif
+
+#ifdef CONFIG_IMXRT_GPIO4_16_31_IRQ
+#  define IMXRT_IRQ_GPIO4_16   (_IMXRT_GPIO4_16_31_BASE + 0)  /* GPIO4 pin 16 interrupt */
+#  define IMXRT_IRQ_GPIO4_17   (_IMXRT_GPIO4_16_31_BASE + 1)  /* GPIO4 pin 17 interrupt */
+#  define IMXRT_IRQ_GPIO4_18   (_IMXRT_GPIO4_16_31_BASE + 2)  /* GPIO4 pin 18 interrupt */
+#  define IMXRT_IRQ_GPIO4_19   (_IMXRT_GPIO4_16_31_BASE + 3)  /* GPIO4 pin 19 interrupt */
+#  define IMXRT_IRQ_GPIO4_20   (_IMXRT_GPIO4_16_31_BASE + 4)  /* GPIO4 pin 20 interrupt */
+#  define IMXRT_IRQ_GPIO4_21   (_IMXRT_GPIO4_16_31_BASE + 5)  /* GPIO4 pin 21 interrupt */
+#  define IMXRT_IRQ_GPIO4_22   (_IMXRT_GPIO4_16_31_BASE + 6)  /* GPIO4 pin 22 interrupt */
+#  define IMXRT_IRQ_GPIO4_23   (_IMXRT_GPIO4_16_31_BASE + 7)  /* GPIO4 pin 23 interrupt */
+#  define IMXRT_IRQ_GPIO4_24   (_IMXRT_GPIO4_16_31_BASE + 8)  /* GPIO4 pin 24 interrupt */
+#  define IMXRT_IRQ_GPIO4_25   (_IMXRT_GPIO4_16_31_BASE + 9)  /* GPIO4 pin 25 interrupt */
+#  define IMXRT_IRQ_GPIO4_26   (_IMXRT_GPIO4_16_31_BASE + 10) /* GPIO4 pin 26 interrupt */
+#  define IMXRT_IRQ_GPIO4_27   (_IMXRT_GPIO4_16_31_BASE + 11) /* GPIO4 pin 27 interrupt */
+#  define IMXRT_IRQ_GPIO4_28   (_IMXRT_GPIO4_16_31_BASE + 12) /* GPIO4 pin 28 interrupt */
+#  define IMXRT_IRQ_GPIO4_29   (_IMXRT_GPIO4_16_31_BASE + 13) /* GPIO4 pin 29 interrupt */
+#  define IMXRT_IRQ_GPIO4_30   (_IMXRT_GPIO4_16_31_BASE + 14) /* GPIO4 pin 30 interrupt */
+#  define IMXRT_IRQ_GPIO4_31   (_IMXRT_GPIO4_16_31_BASE + 15) /* GPIO4 pin 31 interrupt */
+
+#  define _IMXRT_GPIO4_16_31_NIRQS 16
+#  define IMXRT_GPIO4_NIRQS    (_IMXRT_GPIO4_0_15_NIRQS + _IMXRT_GPIO4_16_31_NIRQS)
+#else
+#  define IMXRT_GPIO4_NIRQS    _IMXRT_GPIO4_0_15_NIRQS
+#endif
+
+#define IMXRT_GPIO_NIRQS       (IMXRT_GPIO1_NIRQS + IMXRT_GPIO2_NIRQS + \
+                                IMXRT_GPIO3_NIRQS + IMXRT_GPIO4_NIRQS)
+#define IMXRT_GPIO_IRQ_LAST    (_IMXRT_GPIO1_0_15_BASE + IMXRT_GPIO_NIRQS)
+
+/* Total number of IRQ numbers **********************************************************/
+
+#define NR_VECTORS             IMXRT_IRQ_NIRQS
+#define NR_IRQS                (IMXRT_IRQ_EXTINT + IMXRT_IRQ_NEXTINT + IMXRT_GPIO_NIRQS)
+
+/****************************************************************************************
+ * Public Types
+ ****************************************************************************************/
+
+/****************************************************************************************
+ * Inline functions
+ ****************************************************************************************/
+
+/****************************************************************************************
+ * Public Data
+ ****************************************************************************************/
+
+/****************************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************************/
+
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+#endif
+
+#endif /* __ARCH_ARM_INCLUDE_IMXRT_IMXRT105X_IRQ_H */

arch/arm/include/imxrt/irq.h

@@ -0,0 +1,114 @@
+/****************************************************************************************
+ * arch/arm/include/imxrt/irq.h
+ *
+ *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************************/
+
+/* This file should never be included directed but, rather, only indirectly through
+ * nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM_INCLUDE_IMXRT_IRQ_H
+#define __ARCH_ARM_INCLUDE_IMXRT_IRQ_H
+
+/****************************************************************************************
+ * Included Files
+ ****************************************************************************************/
+
+#include <nuttx/config.h>
+#include <arch/imxrt/chip.h>
+
+/****************************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************************/
+
+/* IRQ numbers.  The IRQ number corresponds vector number and hence map directly to
+ * bits in the NVIC.  This does, however, waste several words of memory in the IRQ
+ * to handle mapping tables.
+ */
+
+/* Common Processor Exceptions (vectors 0-15) */
+
+#define IMXRT_IRQ_RESERVED       (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
+                                     /* Vector  0: Reset stack pointer value */
+                                     /* Vector  1: Reset (not handler as an IRQ) */
+#define IMXRT_IRQ_NMI            (2) /* Vector  2: Non-Maskable Interrupt (NMI) */
+#define IMXRT_IRQ_HARDFAULT      (3) /* Vector  3: Hard fault */
+#define IMXRT_IRQ_MEMFAULT       (4) /* Vector  4: Memory management (MPU) */
+#define IMXRT_IRQ_BUSFAULT       (5) /* Vector  5: Bus fault */
+#define IMXRT_IRQ_USAGEFAULT     (6) /* Vector  6: Usage fault */
+                                     /* Vectors 7-10: Reserved */
+#define IMXRT_IRQ_SVCALL        (11) /* Vector 11: SVC call */
+#define IMXRT_IRQ_DBGMONITOR    (12) /* Vector 12: Debug Monitor */
+                                     /* Vector 13: Reserved */
+#define IMXRT_IRQ_PENDSV        (14) /* Vector 14: Pendable system service request */
+#define IMXRT_IRQ_SYSTICK       (15) /* Vector 15: System tick */
+
+/* Chip-Specific External interrupts */
+
+#define IMXRT_IRQ_EXTINT        (16) /* Vector number of the first external interrupt */
+
+#if defined(CONFIG_ARCH_FAMILY_IMXRT105x)
+#  include <arch/imxrt/imxrt105x_irq.h>
+#else
+#  error Unrecognized i.MX RT architecture
+#endif
+
+/****************************************************************************************
+ * Public Types
+ ****************************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************************
+ * Public Data
+ ****************************************************************************************/
+
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************************/
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+#endif
+
+#endif /* __ARCH_ARM_INCLUDE_IMXRT_IRQ_H */

arch/arm/src/Makefile

@@ -1,7 +1,8 @@
 ############################################################################
 # arch/arm/src/Makefile
 #
-#   Copyright (C) 2007-2009, 2011-2012, 2014-2016 Gregory Nutt. All rights reserved.
+#   Copyright (C) 2007-2009, 2011-2012, 2014-2016 Gregory Nutt. All rights
+#     reserved.
 #   Author: Gregory Nutt <gnutt@nuttx.org>
 #
 # Redistribution and use in source and binary forms, with or without

arch/arm/src/imxrt/Kconfig

@@ -0,0 +1,316 @@
+#
+# For a description of the syntax of this configuration file,
+# see the file kconfig-language.txt in the NuttX tools repository.
+#
+
+if ARCH_CHIP_IMXRT
+
+comment "i.MX RT Configuration Options"
+
+choice
+	prompt "i.MX RT Chip Selection"
+	default ARCH_CHIP_MIMXRT1052DVL6A
+	depends on ARCH_CHIP_IMXRT
+
+config ARCH_CHIP_MIMXRT1051DVL6A
+	bool "MIMXRT1051DVL6A"
+	select ARCH_FAMILY_MXRT105xDVL6A
+
+config ARCH_CHIP_MIMXRT1051CVL5A
+	bool "MIMXRT1051CVL5A"
+	select ARCH_FAMILY_IMIMXRT105xCVL5A
+
+config ARCH_CHIP_MIMXRT1052DVL6A
+	bool "MIMXRT1052DVL6A"
+	select ARCH_FAMILY_MXRT105xDVL6A
+
+config ARCH_CHIP_MIMXRT1052CVL5A
+	bool "MIMXRT1052DVL6A"
+	select ARCH_FAMILY_MIMXRT1052CVL5A
+
+endchoice # i.MX RT Chip Selection
+
+# i.MX RT Families
+
+config ARCH_FAMILY_MXRT105xDVL6A
+	bool
+	default n
+	select ARCH_FAMILY_IMXRT105x
+	---help---
+		i.MX RT1050 Crossover Processors for Consumer Products
+
+config ARCH_FAMILY_MIMXRT1052CVL5A
+	bool
+	default n
+	select ARCH_FAMILY_IMXRT105x
+	---help---
+		i.MX RT1050 Crossover Processors for Industrial Products
+
+config ARCH_FAMILY_IMXRT105x
+	bool
+	default n
+
+# Peripheral support
+
+config IMXRT_HAVE_LPUART
+	bool
+	default n
+
+menu "i.MX RT Peripheral Selection"
+
+menu "FlexIO Peripherals"
+
+endmenu # FlexIO Peripherals
+
+menu "LPUART Peripherals"
+
+config IMXRT_LPUART1
+	bool "LPUART1"
+	default n
+	select LPUART1_SERIALDRIVER
+	select IMXRT_HAVE_LPUART
+
+config IMXRT_LPUART2
+	bool "LPUART2"
+	default n
+	select LPUART2_SERIALDRIVER
+	select IMXRT_HAVE_LPUART
+
+config IMXRT_LPUART3
+	bool "LPUART3"
+	default n
+	select LPUART3_SERIALDRIVER
+	select IMXRT_HAVE_LPUART
+
+config IMXRT_LPUART4
+	bool "LPUART4"
+	default n
+	select LPUART4_SERIALDRIVER
+	select IMXRT_HAVE_LPUART
+
+config IMXRT_LPUART5
+	bool "LPUART5"
+	default n
+	select LPUART5_SERIALDRIVER
+	select IMXRT_HAVE_LPUART
+
+config IMXRT_LPUART6
+	bool "LPUART6"
+	default n
+	select LPUART6_SERIALDRIVER
+	select IMXRT_HAVE_LPUART
+
+config IMXRT_LPUART7
+	bool "LPUART7"
+	default n
+	select LPUART7_SERIALDRIVER
+	select IMXRT_HAVE_LPUART
+
+config IMXRT_LPUART8
+	bool "LPUART8"
+	default n
+	select LPUART8_SERIALDRIVER
+	select IMXRT_HAVE_LPUART
+
+endmenu # LPUART Peripherals
+
+config IMXRT_SEMC
+	bool "Smart External Memory Controller (SEMC)"
+	default n
+
+endmenu # i.MX RT Peripheral Selection
+
+menuconfig IMXRT_GPIO_IRQ
+	bool "GPIO Interrupt Support"
+	default n
+
+if IMXRT_GPIO_IRQ
+
+config IMXRT_GPIO1_0_15_IRQ
+	bool "GPIO1 Pins 8-15 interrupts"
+	default n
+
+config IMXRT_GPIO1_16_31_IRQ
+	bool "GPIO1 Pins 16-31 interrupts"
+	default n
+
+config IMXRT_GPIO2_0_15_IRQ
+	bool "GPIO2 Pins 0-15 interrupts"
+	default n
+
+config IMXRT_GPIO2_16_31_IRQ
+	bool "GPIO2 Pins 16-31 interrupts"
+	default n
+
+config IMXRT_GPIO3_0_15_IRQ
+	bool "GPIO3 Pins 0-15 interrupts"
+	default n
+
+config IMXRT_GPIO3_16_31_IRQ
+	bool "GPIO3 Pins 16-31 interrupts"
+	default n
+
+config IMXRT_GPIO4_0_15_IRQ
+	bool "GPIO4 Pins 0-15 interrupts"
+	default n
+
+config IMXRT_GPIO4_16_31_IRQ
+	bool "GPIO4 Pins 16-31 interrupts"
+	default n
+
+endif # IMXRT_GPIO_IRQ
+
+menu "Memory Configuration"
+
+config IMXRT_DTCM
+	bool "Enable DTCM"
+	default n
+	depends on !IMXRT_OCRAM_PRIMARY && EXPERIMENTAL
+
+config IMXRT_ITCM
+	bool "Enable ITCM"
+	default n
+	depends on !IMXRT_OCRAM_PRIMARY && EXPERIMENTAL
+
+config IMXRT_SEMC_SDRAM
+	bool "External SDRAM installed"
+	default n
+	depends on IMXRT_SEMC
+
+if IMXRT_SEMC_SDRAM
+
+config IMXRT_SDRAM_START
+	hex "SDRAM start address"
+	default 0x10000000
+
+config IMXRT_SDRAM_SIZE
+	int "SDRAM size (bytes)"
+	default 268435456
+
+endif # IMXRT_SEMC_SDRAM
+
+config IMXRT_SEMC_SRAM
+	bool "External SRAM installed"
+	default n
+	depends on IMXRT_SEMC
+
+if IMXRT_SEMC_SRAM
+
+config IMXRT_SRAM_START
+	hex "SRAM start address"
+	default 0x10000000
+
+config IMXRT_SRAM_SIZE
+	int "SRAM size (bytes)"
+	default 268435456
+
+endif # IMXRT_SRAM_SIZE
+
+config IMXRT_SEMC_NOR
+	bool "External NOR FLASH installed"
+	default n
+	depends on IMXRT_SEMC
+
+choice
+	prompt "i.MX RT Boot Configuration"
+	default IMXRT_BOOT_NOR if IMXRT_SEMC_NOR
+	default IMXRT_BOOT_SDRAM if IMXRT_SEMC_SDRAM && !IMXRT_SEMC_NOR
+	default IMXRT_BOOT_SRAM if IMXRT_SEMC_SRAM && !IMXRT_SEMC_SDRAM  && !IMXRT_SEMC_NOR
+	default IMXRT_BOOT_OCRAM if !IMXRT_SEMC_SRAM && !IMXRT_SEMC_SDRAM  && !IMXRT_SEMC_NOR
+	---help---
+		The startup code needs to know if the code is running from internal
+		OCRAM, external SDRAM, external NOR, or external SDRAM in order to
+		initialize properly.  Note that the boot device is not known for
+		cases where the code is copied into RAM by a bootloader.
+
+config IMXRT_BOOT_OCRAM
+	bool "Running from internal OCRAM"
+	select BOOT_RUNFROMISRAM
+
+config IMXRT_BOOT_SDRAM
+	bool "Running from external SDRAM"
+	select BOOT_RUNFROMSDRAM
+	depends on IMXRT_SEMC_SDRAM
+
+config IMXRT_BOOT_NOR
+	bool "Running from external NOR FLASH"
+	select BOOT_RUNFROMFLASH
+	depends on IMXRT_SEMC_NOR
+
+config IMXRT_BOOT_SRAM
+	bool "Running from external SRAM"
+	select BOOT_RUNFROMEXTSRAM
+	depends on IMXRT_SEMC_SRAM
+
+endchoice # i.MX RT Boot Configuration
+
+choice
+	prompt "i.MX6 Primary RAM"
+	default IMXRT_OCRAM_PRIMARY
+	---help---
+		The primary RAM is the RAM that contains the system BLOB's .data and
+		.bss.  The unused portion of the primary RAM will automatically be
+		added to the system heap.
+
+config IMXRT_OCRAM_PRIMARY
+	bool "Internal OCRAM primary"
+
+config IMXRT_SDRAM_PRIMARY
+	bool "External SDRAM primary"
+	depends on IMXRT_SEMC_SDRAM
+
+config IMXRT_SRAM_PRIMARY
+	bool "External SRAM primary"
+	depends on IMXRT_SEMC_SRAM
+
+endchoice # i.MX6 Primary RAM
+
+menu "i.MX RT Heap Configuration"
+
+config IMXRT_OCRAM_HEAP
+	bool "Add OCRAM to heap"
+	depends on !IMXRT_OCRAM_PRIMARY
+	---help---
+		Select to add the entire OCRAM to the heap
+
+config IMXRT_SDRAM_HEAP
+	bool "Add SDRAM to heap"
+	depends on IMXRT_SEMC_SDRAM && !IMXRT_SDRAM_PRIMARY
+	---help---
+		Add a region of SDRAM to the heap.  A region of SDRAM will be added
+		to the heap that starts at (CONFIG_IMXRT_SDRAM_START +
+		CONFIG_IMXRT_SDRAM_HEAPOFFSET) and extends up to
+		(CONFIG_IMXRT_SDRAM_START + CONFIG_IMXRT_SDRAM_SIZE).  Note that the
+		START is the actual start of SDRAM but SIZE is not necessarily the
+		actual SIZE.
+
+config IMXRT_SDRAM_HEAPOFFSET
+	hex "SDRAM heap offset"
+	default 0x0
+	depends on IMXRT_SDRAM_HEAP
+	---help---
+		Used to reserve memory at the beginning of SDRAM for, as an example,
+		a framebuffer.
+
+config IMXRT_SRAM_HEAP
+	bool "Add SRAM to heap"
+	depends on IMXRT_SEMC_SRAM && !IMXRT_SRAM_PRIMARY
+	---help---
+		Add a region of SRAM to the heap.  A region of SDRAM will be added
+		to the heap that starts at (CONFIG_IMXRT_SRAM_START +
+		CONFIG_IMXRT_SRAM_HEAPOFFSET) and extends up to
+		(CONFIG_IMXRT_SRAM_START + CONFIG_IMXRT_SRAM_SIZE).  Note that the
+		START is the actual start of SRAM but SIZE is not necessarily the
+		actual SIZE.
+
+config IMXRT_SRAM_HEAPOFFSET
+	hex "SRAM heap offset"
+	default 0x0
+	depends on IMXRT_SRAM_HEAP
+	---help---
+		Used to reserve memory at the beginning of SRAM for, as an example,
+		a framebuffer.
+
+endmenu  # i.MX6 Primary RAM
+endmenu # Memory Configuration
+endif # ARCH_CHIP_IMXRT

arch/arm/src/imxrt/Make.defs

@@ -0,0 +1,108 @@
+############################################################################
+# arch/arm/src/imxrt/Make.defs
+#
+#   Copyright (C) 2018 Gregory Nutt. All rights reserved.
+#   Author: Gregory Nutt <gnutt@nuttx.org>
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in
+#    the documentation and/or other materials provided with the
+#    distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+#    used to endorse or promote products derived from this software
+#    without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+############################################################################
+
+HEAD_ASRC  =
+
+# Common ARM and Cortex-M7 files
+
+CMN_ASRCS  = up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S
+CMN_ASRCS += up_testset.S up_fetchadd.S vfork.S
+
+CMN_CSRCS  = up_assert.c up_blocktask.c up_copyfullstate.c
+CMN_CSRCS += up_createstack.c up_mdelay.c up_udelay.c up_exit.c
+CMN_CSRCS += up_initialize.c up_initialstate.c up_interruptcontext.c
+CMN_CSRCS += up_memfault.c up_modifyreg8.c up_modifyreg16.c up_modifyreg32.c
+CMN_CSRCS += up_releasepending.c up_releasestack.c up_reprioritizertr.c
+CMN_CSRCS += up_schedulesigaction.c up_sigdeliver.c up_stackframe.c
+CMN_CSRCS += up_unblocktask.c up_usestack.c up_doirq.c up_hardfault.c
+CMN_CSRCS += up_svcall.c up_vfork.c
+
+# Configuration-dependent common files
+
+ifeq ($(CONFIG_ARMV7M_LAZYFPU),y)
+CMN_ASRCS += up_lazyexception.S
+else
+CMN_ASRCS += up_exception.S
+endif
+CMN_CSRCS += up_vectors.c
+
+ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
+CMN_CSRCS += up_ramvec_initialize.c up_ramvec_attach.c
+endif
+
+ifeq ($(CONFIG_BUILD_PROTECTED),y)
+CMN_CSRCS += up_mpu.c up_task_start.c up_pthread_start.c
+ifneq ($(CONFIG_DISABLE_SIGNALS),y)
+CMN_CSRCS += up_signal_dispatch.c
+CMN_UASRCS += up_signal_handler.S
+endif
+endif
+
+ifeq ($(CONFIG_STACK_COLORATION),y)
+CMN_CSRCS += up_checkstack.c
+endif
+
+ifeq ($(CONFIG_ARCH_FPU),y)
+CMN_ASRCS += up_fpu.S
+ifneq ($(CONFIG_ARMV7M_CMNVECTOR),y)
+CMN_CSRCS += up_copyarmstate.c
+else ifeq ($(CONFIG_ARMV7M_LAZYFPU),y)
+CMN_CSRCS += up_copyarmstate.c
+endif
+endif
+
+# Required i.MX RT files
+
+CHIP_ASRCS  =
+CHIP_CSRCS  = imxrt_allocateheap.c imxrt_start.c imxrt_clockconfig.c imxrt_idle.c
+CHIP_CSRCS += imxrt_irq.c imxrt_clrpend.c imxrt_gpio.c imxrt_wdog.c imxrt_iomuxc.c
+CHIP_CSRCS += imxrt_serial.c imxrt_lowputc.c
+
+# Configuration-dependent i.MX RT files
+
+ifneq ($(CONFIG_SCHED_TICKLESS),y)
+CHIP_CSRCS += imxrt_timerisr.c
+endif
+
+ifeq ($(CONFIG_IMXRT_GPIO_IRQ),y)
+CHIP_CSRCS += imxrt_gpioirq.c
+endif
+
+ifeq ($(CONFIG_ARM_MPU),y)
+CHIP_CSRCS += imxrt_mpuinit.c
+ifeq ($(CONFIG_BUILD_PROTECTED),y)
+CHIP_CSRCS += imxrt_userspace.c
+endif
+endif

arch/arm/src/imxrt/chip.h

@@ -0,0 +1,81 @@
+/************************************************************************************
+ * arch/arm/src/imxrt/chip.h
+ *
+ *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_H
+#define __ARCH_ARM_SRC_IMXRT_CHIP_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+/* Include the memory map and the chip definitions file.  Other chip hardware files
+ * should then include this file for the proper setup.
+ */
+
+#include <arch/irq.h>
+#include <arch/imxrt/chip.h>
+#include "chip/imxrt_memorymap.h"
+
+/* If the common ARMv7-M vector handling logic is used, then it expects the following
+ * definition in this file that provides the number of supported vectors external
+ * interrupts.
+ */
+
+#define ARMV7M_PERIPHERAL_INTERRUPTS IMXRT_IRQ_NEXTINT
+
+/* Cache line sizes (in bytes)for the SAMV71 */
+
+#define ARMV7M_DCACHE_LINESIZE 32  /* 32 bytes (8 words) */
+#define ARMV7M_ICACHE_LINESIZE 32  /* 32 bytes (8 words) */
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_H */

arch/arm/src/imxrt/chip/imxrt105x_memorymap.h

@@ -0,0 +1,259 @@
+/************************************************************************************
+ * arch/arm/src/imxrt/chip/imxrt105x_memorymap.h
+ *
+ *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT105X_MEMORYMAP_H
+#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT105X_MEMORYMAP_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* System memory map */
+
+#define IMXRT_ITCM_BASE           0x00000000  /* 512KB ITCM */
+                               /* 0x00080000     512KB ITCM Reserved */
+                               /* 0x00100000     1MB ITCM Reserved */
+#define IMXRT_ROMCP_BASE          0x00200000  /* 96KB ROMCP */
+                               /* 0x00218000     416KB ROMCP Reserved */
+                               /* 0x00280000     1536KB Reserved */
+                               /* 0x00400000     128MB Reserved */
+#define IMXRT_FLEXSPI_BASE        0x08000000  /* 128MB FlexSPI (Aliased) */
+#define IMXRT_SEMCA_BASE          0x10000000  /* 256MB SEMC (Aliased) */
+#define IMXRT_DTCM_BASE           0x20000000  /* 512KB DTCM */
+                               /* 0x20080000     512KB DTCM Reserved */
+                               /* 0x20100000     1MB Reserved */
+#define IMXRT_OCRAM_BASE          0x20200000  /* 512KB OCRAM */
+                               /* 0x20280000     1536KB OCRAM Reserved */
+                               /* 0x20400000     252MB Reserved */
+                               /* 0x30000000     256MB Reserved */
+#define IMXRT_AIPS1_BASE          0x40000000  /* 1MB AIPS-1 */
+#define IMXRT_AIPS2_BASE          0x40100000  /* 1MB AIPS-2 */
+#define IMXRT_AIPS3_BASE          0x40200000  /* 1MB AIPS-3 */
+#define IMXRT_AIPS4_BASE          0x40300000  /* 1MB AIPS-4 */
+                               /* 40400000       12MB Reserved */
+#define IMXRT_MAINCNF_BASE        0x41000000  /* 1MB "main" configuration port */
+#define IMXRT_MCNF_BASE           0x41100000  /* 1MB "m" configuration port */
+                               /* 41200000       1MB Reserved for "per" GPV */
+                               /* 41300000       1MB Reserved for "ems" GPV */
+#define IMXRT_CPUCNF_BASE         0x41400000  /* 1MB "cpu" configuration port */
+                               /* 0x41500000     1MB GPV Reserved */
+                               /* 0x41600000     1MB GPV Reserved */
+                               /* 0x41700000     1MB GPV Reserved */
+                               /* 0x41800000     8MB Reserved */
+                               /* 0x42000000     32MB Reserved */
+                               /* 0x44000000     64MB Reserved */
+                               /* 0x48000000     384MB Reserved */
+#define IMXRT_FLEXCIPHER_BASE     0x60000000  /* 504MB FlexSPI/ FlexSPI ciphertext */
+#define IMXRT_FLEXSPITX_BASE      0x7f800000  /* 4MB FlexSPI TX FIFO */
+#define IMXRT_FLEXSPIRX_BASE      0x7fc00000  /* 4MB FlexSPI RX FIFO */
+#define IMXRT_EXTMEM_BASE         0x80000000  /* 1.5GB SEMC external memories shared memory space */
+#define IMXRT_CM7_BASE            0xe0000000  /* 1MB CM7 PPB */
+                               /* 0xe0100000     511MB Reserved */
+
+/* AIPS-1 memory map */
+
+                               /* 0x40000000     256KB Reserved */
+                               /* 0x40040000     240KB Reserved */
+#define IMXRT_AIPS1CNF_BASE       0x4007c000  /* 6KB AIPS-1 Configuration */
+#define IMXRT_DCDC_BASE           0x40080000  /* 16KB DCDC */
+#define IMXRT_PIT_BASE            0x40084000  /* 16KB PIT */
+                               /* 0x40088000     16KB Reserved */
+                               /* 0x4008c000     16KB Reserved */
+#define IMXRT_MTR_BASE            0x40090000  /* 16KB MTR */
+#define IMXRT_ACMP_BASE           0x40094000  /* 16KB ACMP */
+                               /* 0x40098000     16KB Reserved */
+                               /* 0x4009c000     16KB Reserved */
+                               /* 0x400a0000     16KB Reserved */
+#define IMXRT_IOMUXCSNVSGPR_BASE  0x400a4000  /* 16KB IOMUXC_SNVS_GPR */
+#define IMXRT_IOMUXCSNVS_BASE     0x400a8000  /* 16KB IOMUXC_SNVS */
+#define IMXRT_IOMUXCGPR_BASE      0x400ac000  /* 16KB IOMUXC_GPR */
+#define IMXRT_FLEXRAM_BASE        0x400b0000  /* 16KB CM7_MX6RT(FLEXRAM) */
+#define IMXRT_EWM_BASE            0x400b4000  /* 16KB EWM */
+#define IMXRT_WDOG1_BASE          0x400b8000  /* 16KB WDOG1 */
+#define IMXRT_WDOG3_BASE          0x400bc000  /* 16KB WDOG3 */
+#define IMXRT_GPIO5_BASE          0x400c0000  /* 16KB GPIO5 */
+#define IMXRT_ADC1_BASE           0x400c4000  /* 16KB ADC1 */
+#define IMXRT_ADC2_BASE           0x400c8000  /* 16KB ADC2 */
+#define IMXRT_TRNG_BASE           0x400cc000  /* 16KB TRNG */
+#define IMXRT_WDOG2_BASE          0x400d0000  /* 16KB WDOG2 */
+#define IMXRT_SNVSHP_BASE         0x400d4000  /* 16KB SNVS_HP */
+#define IMXRT_ANATOP_BASE         0x400d8000  /* 16KB ANATOP */
+#define IMXRT_CSU_BASE            0x400dc000  /* 16KB CSU */
+                               /* 0x400e0000     16KB Reserved */
+                               /* 0x400e4000     16KB Reserved */
+#define IMXRT_EDMA_BASE           0x400e8000  /* 16KB EDMA */
+#define IMXRT_DMACHMUX_BASE       0x400ec000  /* 16KB DMA_CH_MUX */
+                               /* 400f0000       16KB Reserved */
+#define IMXRT_GPC_BASE            0x400f4000  /* 16KB GPC */
+#define IMXRT_SRC_BASE            0x400f8000  /* 16KB SRC */
+#define IMXRT_CCM_BASE            0x400fc000  /* 16KB CCM */
+
+/* AIPS-2 memory map */
+
+                               /* 0x40100000     256KB Reserved */
+                               /* 0x40140000     240KB Reserved */
+#define IMXRT_AIPS2CNF_BASE       0x4017c000  /* 16KB AIPS-2 Configuration */
+#define IMXRT_ROMCPC_BASE         0x40180000  /* 16KB ROMCP controller*/
+#define IMXRT_LPUART1_BASE        0x40184000  /* 16KB LPUART1 */
+#define IMXRT_LPUART2_BASE        0x40188000  /* 16KB LPUART2 */
+#define IMXRT_LPUART3_BASE        0x4018c000  /* 16KB LPUART3 */
+#define IMXRT_LPUART4_BASE        0x40190000  /* 16KB LPUART4 */
+#define IMXRT_LPUART5_BASE        0x40194000  /* 16KB LPUART5 */
+#define IMXRT_LPUART6_BASE        0x40198000  /* 16KB LPUART6 */
+#define IMXRT_LPUART7_BASE        0x4019c000  /* 16KB LPUART7 */
+#define IMXRT_LPUART8_BASE        0x401a0000  /* 16KB LPUART8 */
+                               /* 0x401a4000     16KB Reserved */
+                               /* 0x401a8000     16KB Reserved */
+#define IMXRT_FLEXIO1_BASE        0x401ac000  /* 16KB FlexIO1 */
+#define IMXRT_FLEXIO2_BASE        0x401b0000  /* 16KB FlexIO2 */
+                               /* 0x401b4000     16KB Reserved */
+#define IMXRT_GPIO_BASE(n)        (0x401b8000 + ((n) << 14))
+#define IMXRT_GPIO1_BASE          0x401b8000  /* 16KB GPIO1 */
+#define IMXRT_GPIO2_BASE          0x401bc000  /* 16KB GPIO2 */
+#define IMXRT_GPIO3_BASE          0x401c0000  /* 16KB GPIO3 */
+#define IMXRT_GPIO4_BASE          0x401c4000  /* 16KB GPIO4 */
+                               /* 0x401c8000     16KB Reserved */
+                               /* 0x401cc000     16KB Reserved */
+#define IMXRT_CAN1_BASE           0x401d0000  /* 16KB CAN1 */
+#define IMXRT_CAN2_BASE           0x401d4000  /* 16KB CAN2 */
+                               /* 0x401d8000     16KB Reserved */
+#define IMXRT_QTIMER1_BASE        0x401dc000  /* 16KB QTimer1 */
+#define IMXRT_QTIMER2_BASE        0x401e0000  /* 16KB QTimer2 */
+#define IMXRT_QTIMER3_BASE        0x401e4000  /* 16KB QTimer3 */
+#define IMXRT_QTIMER4_BASE        0x401e8000  /* 16KB QTimer4 */
+#define IMXRT_GPT1_BASE           0x401ec000  /* 16KB GPT1 */
+#define IMXRT_GPT2_BASE           0x401f0000  /* 16KB GPT2 */
+#define IMXRT_OCOTP_BASE          0x401f4000  /* 16KB OCOTP */
+#define IMXRT_IOMUXC_BASE         0x401f8000  /* 16KB IOMUXC */
+#define IMXRT_KPP_BASE            0x401fc000  /* 16KB KPP */
+
+/* AIPS-3 memory map */
+
+                               /* 0x40200000     256KB Reserved */
+                               /* 0x40240000     240KB Reserved */
+#define IMXRT_AIOS3CNF_BASE       0x4027c000  /* 16KB AIPS-3 Configuration */
+                               /* 0x40280000     16KB Reserved */
+                               /* 0x40284000     16KB Reserved */
+                               /* 0x40288000     16KB Reserved */
+                               /* 0x4028c000     16KB Reserved */
+                               /* 0x40290000     16KB Reserved */
+                               /* 0x40294000     16KB Reserved */
+                               /* 0x40298000     16KB Reserved */
+                               /* 0x4029c000     16KB Reserved */
+                               /* 0x402a0000     16KB Reserved */
+                               /* 0x402a4000     16KB Reserved */
+#define IMXRT_FLEXSPIC_BASE       0x402a8000  /* 16KB FlexSPI controller */
+                               /* 0x402ac000     16KB Reserved */
+                               /* 0x402b0000     16KB Reserved */
+#define IMXRT_PXP_BASE            0x402b4000  /* 16KB PXP */
+#define IMXRT_LCDIF_BASE          0x402b8000  /* 16KB LCDIF */
+#define IMXRT_CSI_BASE            0x402bc000  /* 16KB CSI */
+#define IMXRT_USDHC1_BASE         0x402c0000  /* 16KB USDHC1 */
+#define IMXRT_USDHC2_BASE         0x402c4000  /* 16KB USDHC2 */
+                               /* 0x402c8000     16KB Reserved */
+                               /* 0x402cc000     16KB Reserved */
+                               /* 0x402d0000     16KB Reserved */
+                               /* 0x402d4000     16KB Reserved */
+#define IMXRT_ENET_BASE           0x402d8000  /* 16KB ENET */
+#define IMXRT_USBPL301_BASE       0x402dc000  /* 16KB USB(PL301) */
+#define IMXRT_USB_BASE            0x402e0000  /* 16KB USB(USB) */
+                               /* 0x402e4000     16KB Reserved */
+                               /* 0x402e8000     16KB Reserved */
+                               /* 0x402ec000     16KB Reserved */
+#define IMXRT_SEMC_BASE           0x402f0000  /* 16KB SEMC */
+                               /* 0x402f4000     16KB Reserved */
+                               /* 0x402f8000     16KB Reserved */
+#define IMXRT_DCP_BASE            0x402fc000  /* 16KB DCP */
+
+/* AIPS-4 memory map */
+
+                               /* 0x40300000     256KB Reserved */
+                               /* 0x40340000     240KB Reserved */
+#define IMXRT_AIPS4CNF_BASE       0x4037c000  /* 16KB AIPS-4 Configuration */
+#define IMXRT_SPDIF_BASE          0x40380000  /* 16KB SPDIF */
+#define IMXRT_SAI1_BASE           0x40384000  /* 16KB SAI1 */
+#define IMXRT_SAI2_BASE           0x40388000  /* 16KB SAI2 */
+#define IMXRT_SAI3_BASE           0x4038c000  /* 16KB SAI3 */
+                               /* 0x40390000     16KB Reserved */
+#define IMXRT_LPSPI1_BASE         0x40394000  /* 16KB LPSPI1 */
+#define IMXRT_LPSPI2_BASE         0x40398000  /* 16KB LPSPI2 */
+#define IMXRT_LPSPI3_BASE         0x4039c000  /* 16KB LPSPI3 */
+#define IMXRT_LPSPI4_BASE         0x403a0000  /* 16KB LPSPI4 */
+                               /* 0x403a4000     16KB Reserved */
+                               /* 0x403a8000     16KB Reserved */
+                               /* 0x403ac000     16KB Reserved */
+#define IMXRT_ADCETC_BASE         0x403b0000  /* 16KB ADC_ETC */
+#define IMXRT_AOI1_BASE           0x403b4000  /* 16KB AOI1 */
+#define IMXRT_AOI2_BASE           0x403b8000  /* 16KB AOI2 */
+#define IMXRT_XBAR1_BASE          0x403bc000  /* 16KB XBAR1 */
+#define IMXRT_XBAR2_BASE          0x403c0000  /* 16KB XBAR2 */
+#define IMXRT_XBAR3_BASE          0x403c4000  /* 16KB XBAR3 */
+#define IMXRT_ENC1_BASE           0x403c8000  /* 16KB ENC1 */
+#define IMXRT_ENC2_BASE           0x403cc000  /* 16KB ENC2 */
+#define IMXRT_ENC3_BASE           0x403d0000  /* 16KB ENC3 */
+#define IMXRT_ENC4_BASE           0x403d4000  /* 16KB ENC4 */
+                               /* 0x403d8000     16KB Reserved */
+#define IMXRT_FLEXPWM1_BASE       0x403dc000  /* 16KB FLEXPWM1 */
+#define IMXRT_FLEXPWM2_BASE       0x403e0000  /* 16KB FLEXPWM2 */
+#define IMXRT_FLEXPWM3_BASE       0x403e4000  /* 16KB FLEXPWM3 */
+#define IMXRT_FLEXPWM4_BASE       0x403e8000  /* 16KB FLEXPWM4 */
+#define IMXRT_BEE_BASE            0x403ec000  /* 16KB BEE */
+#define IMXRT_LPI2C1_BASE         0x403f0000  /* 16KB  */
+#define IMXRT_LPI2C2_BASE         0x403f4000  /* 16KB LPI2C2 */
+#define IMXRT_LPI2C3_BASE         0x403f8000  /* 16KB LPI2C3 */
+#define IMXRT_LPI2C4_BASE         0x403fc000  /* 16KB LPI2C4 */
+
+/* PPB memory map */
+
+#define IMXRT_TPIU_BASE           0xe0040000  /* 4KB TPIU */
+#define IMXRT_ETM_BASE            0xe0041000  /* 4KB ETM */
+#define IMXRT_CTI_BASE            0xe0042000  /* 4KB CTI */
+#define IMXRT_TSGEN_BASE          0xe0043000  /* 4KB TSGEN */
+#define IMXRT_PPBRES_BASE         0xe0044000  /* 4KB PPB RES */
+                               /* 0xe0045000     236KB PPB Reserved */
+#define IMXRT_MCM_BASE            0xe0080000  /* 4KB MCM */
+                               /* 0xe0081000     444KB PPB Reserved */
+                               /* 0xe00f0000     52KB PPB Reserved */
+#define IMXRT_SYSROM_BASE         0xe00fd000  /* 4KB SYS ROM */
+#define IMXRT_PROCROM_BASE        0xe00fe000  /* 4KB Processor ROM */
+#define IMXRT_PPBROM_BASE         0xe00ff000  /* 4KB PPB ROM */
+
+#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT105X_MEMORYMAP_H */

arch/arm/src/imxrt/chip/imxrt_dcdc.h

@@ -0,0 +1,152 @@
+/****************************************************************************************************
+ * arch/arm/src/imxrt/imxrt_dcdc.h
+ *
+ *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ *   Author:  Janne Rosberg <janne@offcode.fi>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_DCDC_H
+#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_DCDC_H
+
+/****************************************************************************************************
+ * Included Files
+ ****************************************************************************************************/
+
+#include <nuttx/config.h>
+#include "chip/imxrt_memorymap.h"
+
+/****************************************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************************************/
+
+/* Register offsets *********************************************************************************/
+
+#define IMXRT_DCDC_REG0_OFFSET              0x0000  /* DCDC Register 0 */
+#define IMXRT_DCDC_REG1_OFFSET              0x0004  /* DCDC Register 1 */
+#define IMXRT_DCDC_REG2_OFFSET              0x0008  /* DCDC Register 2 */
+#define IMXRT_DCDC_REG3_OFFSET              0x000c  /* DCDC Register 3 */
+
+/* Register addresses *******************************************************************************/
+
+#define IMXRT_DCDC_REG0                     (IMXRT_DCDC_BASE + IMXRT_DCDC_REG0_OFFSET)
+#define IMXRT_DCDC_REG1                     (IMXRT_DCDC_BASE + IMXRT_DCDC_REG1_OFFSET)
+#define IMXRT_DCDC_REG2                     (IMXRT_DCDC_BASE + IMXRT_DCDC_REG2_OFFSET)
+#define IMXRT_DCDC_REG3                     (IMXRT_DCDC_BASE + IMXRT_DCDC_REG3_OFFSET)
+
+/* Register bit definitions *************************************************************************/
+
+/* Register 0 */
+
+#define DCDC_REG0_PWD_ZCD                   (1 << 0)  /* Bit 0:  Power down the zero cross detection */
+#define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH   (1 << 1)  /* Bit 1:  Disable automatic clock switch */
+#define DCDC_REG0_SEL_CLK                   (1 << 2)  /* Bit 2:  Select 24 MHz Crystal clock */
+#define DCDC_REG0_PWD_OSC_INT               (1 << 3)  /* Bit 3:  Power down internal osc */
+#define DCDC_REG0_PWD_CUR_SNS_CMP           (1 << 4)  /* Bit 4:  The power down signal of the current detector */
+#define DCDC_REG0_CUR_SNS_THRSH_SHIFT       (5)       /* Bits 5-7: threshold of current detector */
+#define DCDC_REG0_CUR_SNS_THRSH_MASK        (0x7 << DCDC_REG0_CUR_SNS_THRSH_SHIFT)
+#  define DCDC_REG0_CUR_SNS_THRSH_150MA     ((uint32_t)(0) << DCDC_REG0_CUR_SNS_THRSH_SHIFT)
+#  define DCDC_REG0_CUR_SNS_THRSH_250MA     ((uint32_t)(1) << DCDC_REG0_CUR_SNS_THRSH_SHIFT)
+#  define DCDC_REG0_CUR_SNS_THRSH_350MA     ((uint32_t)(2) << DCDC_REG0_CUR_SNS_THRSH_SHIFT)
+#  define DCDC_REG0_CUR_SNS_THRSH_450MA     ((uint32_t)(3) << DCDC_REG0_CUR_SNS_THRSH_SHIFT)
+#  define DCDC_REG0_CUR_SNS_THRSH_550MA     ((uint32_t)(4) << DCDC_REG0_CUR_SNS_THRSH_SHIFT)
+#  define DCDC_REG0_CUR_SNS_THRSH_650MA     ((uint32_t)(5) << DCDC_REG0_CUR_SNS_THRSH_SHIFT)
+#define DCDC_REG0_PWD_OVERCUR_DET           (1 << 8)  /* Bit 8:  Power down overcurrent detection comparator */
+#define DCDC_REG0_OVERCUR_TIRG_ADJ_SHIFT    (9)       /* Bits 9-10:  The threshold of over current detection */
+#define DCDC_REG0_OVERCUR_TIRG_ADJ_MASK     (0x3 << DCDC_REG0_OVERCUR_TIRG_ADJ_SHIFT)
+#  define DCDC_REG0_OVERCUR_TIRG_ADJ_1A_025 ((uint32_t)(0) << DCDC_REG0_OVERCUR_TIRG_ADJ_SHIFT)
+#  define DCDC_REG0_OVERCUR_TIRG_ADJ_2A_025 ((uint32_t)(1) << DCDC_REG0_OVERCUR_TIRG_ADJ_SHIFT)
+#  define DCDC_REG0_OVERCUR_TIRG_ADJ_1A_02  ((uint32_t)(2) << DCDC_REG0_OVERCUR_TIRG_ADJ_SHIFT)
+#  define DCDC_REG0_OVERCUR_TIRG_ADJ_2A_02  ((uint32_t)(3) << DCDC_REG0_OVERCUR_TIRG_ADJ_SHIFT)
+#define DCDC_REG0_PWD_CMP_BATT_DET          (1 << 11) /* Bit 11: Power down the low voltage detection comparator */
+#define DCDC_REG0_ADJ_POSLIMIT_BUCK_SHIFT   (12)      /* Bits 12-15: Adjust value to poslimit_buck register */
+#define DCDC_REG0_ADJ_POSLIMIT_BUCK_MASK    (0xf << DCDC_REG0_ADJ_POSLIMIT_BUCK_SHIFT)
+#  define DCDC_REG0_ADJ_POSLIMIT_BUCK(n)    ((uint32_t)(n) << DCDC_REG0_ADJ_POSLIMIT_BUCK_SHIFT)
+#define DCDC_REG0_EN_LP_OVERLOAD_SNS        (1 << 16) /* Bit 16: Enable the overload detection in power save mode */
+#define DCDC_REG0_PWD_HIGH_VOLT_DET         (1 << 17) /* Bit 17: Power down overvoltage detection comparator */
+#define DCDC_REG0_LP_OVERLOAD_THRSH_SHIFT   (18)      /* Bits 18-19: the threshold of the counting number */
+#define DCDC_REG0_LP_OVERLOAD_THRSH_MASK    (0x3 << DCDC_REG0_LP_OVERLOAD_THRSH_SHIFT)
+#  define DCDC_REG0_LP_OVERLOAD_THRSH_32    ((uint32_t)(0) << DCDC_REG0_LP_OVERLOAD_THRSH_SHIFT)
+#  define DCDC_REG0_LP_OVERLOAD_THRSH_64    ((uint32_t)(1) << DCDC_REG0_LP_OVERLOAD_THRSH_SHIFT)
+#  define DCDC_REG0_LP_OVERLOAD_THRSH_16    ((uint32_t)(2) << DCDC_REG0_LP_OVERLOAD_THRSH_SHIFT)
+#  define DCDC_REG0_LP_OVERLOAD_THRSH_8     ((uint32_t)(3) << DCDC_REG0_LP_OVERLOAD_THRSH_SHIFT)
+#define DCDC_REG0_LP_OVERLOAD_FREQ_SEL      (1 << 20) /* Bit 20: The period of counting the charging times in power save mode */
+#define DCDC_REG0_LP_OVERLOAD_FREQ_SEL_8    (0 << 20) /* Bit 20: The period of counting the charging times in power save mode */
+#define DCDC_REG0_LP_OVERLOAD_FREQ_SEL_16   (1 << 20) /* Bit 20: Fhe period of counting the charging times in power save mode */
+#define DCDC_REG0_LP_HIGH_HYS               (1 << 21) /* Bit 21: Adjust hysteretic value in low power from 12.5mV to 25mV */
+                                                      /* Bits 22-26  Reserved */
+#define DCDC_REG0_XTALOK_DISABLE            (1 << 27) /* Bit 27: Disable xtalok detection circuit */
+#define DCDC_REG0_CURRENT_ALERT_RESET       (1 << 28) /* Bit 28: Reset current alert signal */
+#define DCDC_REG0_XTAL_24M_OK               (1 << 29) /* Bit 29: Set to 1 to switch internal ring osc to xtal 24M */
+                                                      /* Bit 30: Reserved */
+#define DCDC_REG0_STS_DC_OK                 (1 << 31) /* Bit 31: Status register to indicate DCDC status */
+
+/* Register 1 */
+
+#define DCDC_REG1_POSLIMIT_BUCK_IN_SHIFT    (0)       /* Bits 0-6: Upper limit duty cycle limit in DC-DC converter */
+#define DCDC_REG1_POSLIMIT_BUCK_IN_MASK     (0x7f << DCDC_REG1_POSLIMIT_BUCK_IN_SHIFT)
+#  define DCDC_REG1_POSLIMIT_BUCK_IN(n)     ((uint32_t)(n) << DCDC_REG1_POSLIMIT_BUCK_IN_SHIFT)
+#define DCDC_REG1_REG_FBK_SEL_SHIFT         (7)       /* Bits 7-8: Select the feedback point of the internal regulator */
+#define DCDC_REG1_REG_FBK_SEL_MASK          (0x3 << DCDC_REG1_REG_FBK_SEL_SHIFT)
+#  define DCDC_REG1_REG_FBK_SEL(n)          ((uint32_t)(n) << DCDC_REG1_REG_FBK_SEL_SHIFT)
+                                                      /* Bits 9-11: Reserved */
+#define DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT     (12)      /* Bits 12-13: Set the current bias of low power comparator */
+#define DCDC_REG1_LP_CMP_ISRC_SEL_MASK      (0x3 << DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT)
+#  define DCDC_REG1_LP_CMP_ISRC_SEL(n)      ((uint32_t)(n) << DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT)
+#define DCDC_REG1_NEGLIMIT_IN_SHIFT         (14)      /* Bits 14-20: Set the current bias of low power comparator */
+#define DCDC_REG1_NEGLIMIT_IN_MASK          (0x3f << DCDC_REG1_NEGLIMIT_IN_SHIFT)
+#  define DCDC_REG1_NEGLIMIT_IN(n)          ((uint32_t)(n) << DCDC_REG1_NEGLIMIT_IN_SHIFT)
+#define DCDC_REG1_LOOPCTRL_HST_THRESH       (1 << 21) /* Bit 21: Increase the threshold detection for common mode analog comparator */
+                                                      /* Bit 22: Reserved */
+#define DCDC_REG1_LOOPCTRL_EN_HYST          (1 << 23) /* Bit 23: Enable hysteresis in switching converter */
+#define DCDC_REG1_VBG_TRIM_SHIFT            (24)      /* Bits 24-28: Trim bandgap voltage */
+#define DCDC_REG1_VBG_TRIM_MASK             (0x1f << DCDC_REG1_VBG_TRIM_SHIFT)
+#  define DCDC_REG1_VBG_TRIM(n)             ((uint32_t)(n) << DCDC_REG1_VBG_TRIM_SHIFT)
+                                                      /* Bit 29-31: Reserved */
+
+/* Register 3 */
+
+#define DCDC_REG3_TRG_SHIFT                 (0)       /* Bits 0-4: Target value of VDD_SOC, 25 mV each step */
+#define DCDC_REG3_TRG_MASK                  (0x1f << DCDC_REG3_TRG_SHIFT)
+#  define DCDC_REG3_TRG(n)                  ((uint32_t)(n) << DCDC_REG3_TRG_SHIFT)
+                                                      /* Bit 5-7: Reserved */
+#define DCDC_REG3_TARGET_LP_SHIFT           (8)       /* Bits 8-10: Target value of standby (low power) mode */
+#define DCDC_REG3_TARGET_LP_MASK            (0x7 << DCDC_REG3_TARGET_LP_SHIFT)
+#  define DCDC_REG3_TARGET_LP_(n)           ((uint32_t)(n) << DCDC_REG3_TARGET_LP_SHIFT)
+                                                      /* Bit 11-23: Reserved */
+#define DCDC_REG3_MINPWR_DC_HALFCLK         (1 << 24) /* Bit 24: Set DCDC clock to half freqeuncy for continuous mode */
+                                                      /* Bit 25-26: Reserved */
+#define DCDC_REG3_MISC_DELAY_TIMING         (1 << 27) /* Bit 27: Adjust delay to reduce ground noise */
+#define DCDC_REG3_MISC_DISABLE_FET_LOGIC    (1 << 28) /* Bit 28: Datasheet: reserved? */
+                                                      /* Bit 29: Reserved */
+#define DCDC_REG3_DISABLE_STEP              (1 << 30) /* Bit 30: Disable stepping */
+                                                      /* Bit 31: Reserved */
+
+#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_DCDC_H */

arch/arm/src/imxrt/chip/imxrt_gpio.h

@@ -0,0 +1,136 @@
+/********************************************************************************************
+ * arch/arm/src/imxrt/imxrt_gpio.h
+ *
+ *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ *   Author:  Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ********************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_GPIO_H
+#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_GPIO_H
+
+/********************************************************************************************
+ * Included Files
+ ********************************************************************************************/
+
+#include <nuttx/config.h>
+#include "chip/imxrt_memorymap.h"
+
+/********************************************************************************************
+ * Pre-processor Definitions
+ ********************************************************************************************/
+
+#define GPIO1                     0      /* Port 1 index */
+#define GPIO2                     1      /* Port 2 index */
+#define GPIO3                     2      /* Port 3 index */
+#define GPIO4                     3      /* Port 4 index */
+
+#define IMXRT_GPIO_NPORTS         4      /* Four total ports */
+#define IMXRT_GPIO_NPINS         32      /* Up to 32 pins per port */
+
+/* Register offsets *************************************************************************/
+
+#define IMXRT_GPIO_DR_OFFSET     0x0000  /* GPIO data register */
+#define IMXRT_GPIO_GDIR_OFFSET   0x0004  /* GPIO direction register */
+#define IMXRT_GPIO_PSR_OFFSET    0x0008  /* GPIO pad status register */
+#define IMXRT_GPIO_ICR1_OFFSET   0x000c  /* GPIO interrupt configuration register1 */
+#define IMXRT_GPIO_ICR2_OFFSET   0x0010  /* GPIO interrupt configuration register2 */
+#define IMXRT_GPIO_IMR_OFFSET    0x0014  /* GPIO interrupt mask register */
+#define IMXRT_GPIO_ISR_OFFSET    0x0018  /* GPIO interrupt status register */
+#define IMXRT_GPIO_EDGE_OFFSET   0x001c  /* GPIO edge select register */
+
+/* Register addresses ***********************************************************************/
+
+#define IMXRT_GPIO_DR(n)         (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_DR_OFFSET)
+#define IMXRT_GPIO_GDIR(n)       (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_GDIR_OFFSET)
+#define IMXRT_GPIO_PSR(n)        (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_PSR_OFFSET)
+#define IMXRT_GPIO_ICR1(n)       (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_ICR1_OFFSET)
+#define IMXRT_GPIO_ICR2(n)       (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_ICR2_OFFSET)
+#define IMXRT_GPIO_IMR(n)        (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_IMR_OFFSET)
+#define IMXRT_GPIO_ISR(n)        (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_ISR_OFFSET)
+#define IMXRT_GPIO_EDGE(n)       (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_EDGE_OFFSET)
+
+#define IMXRT_GPIO1_DR           (IMXRT_GPIO1_BASE + IMXRT_GPIO_DR_OFFSET)
+#define IMXRT_GPIO1_GDIR         (IMXRT_GPIO1_BASE + IMXRT_GPIO_GDIR_OFFSET)
+#define IMXRT_GPIO1_PSR          (IMXRT_GPIO1_BASE + IMXRT_GPIO_PSR_OFFSET)
+#define IMXRT_GPIO1_ICR1         (IMXRT_GPIO1_BASE + IMXRT_GPIO_ICR1_OFFSET)
+#define IMXRT_GPIO1_ICR2         (IMXRT_GPIO1_BASE + IMXRT_GPIO_ICR2_OFFSET)
+#define IMXRT_GPIO1_IMR          (IMXRT_GPIO1_BASE + IMXRT_GPIO_IMR_OFFSET)
+#define IMXRT_GPIO1_ISR          (IMXRT_GPIO1_BASE + IMXRT_GPIO_ISR_OFFSET)
+#define IMXRT_GPIO1_EDGE         (IMXRT_GPIO1_BASE + IMXRT_GPIO_EDGE_OFFSET)
+
+#define IMXRT_GPIO2_DR           (IMXRT_GPIO2_BASE + IMXRT_GPIO_DR_OFFSET)
+#define IMXRT_GPIO2_GDIR         (IMXRT_GPIO2_BASE + IMXRT_GPIO_GDIR_OFFSET)
+#define IMXRT_GPIO2_PSR          (IMXRT_GPIO2_BASE + IMXRT_GPIO_PSR_OFFSET)
+#define IMXRT_GPIO2_ICR1         (IMXRT_GPIO2_BASE + IMXRT_GPIO_ICR1_OFFSET)
+#define IMXRT_GPIO2_ICR2         (IMXRT_GPIO2_BASE + IMXRT_GPIO_ICR2_OFFSET)
+#define IMXRT_GPIO2_IMR          (IMXRT_GPIO2_BASE + IMXRT_GPIO_IMR_OFFSET)
+#define IMXRT_GPIO2_ISR          (IMXRT_GPIO2_BASE + IMXRT_GPIO_ISR_OFFSET)
+#define IMXRT_GPIO2_EDGE         (IMXRT_GPIO2_BASE + IMXRT_GPIO_EDGE_OFFSET)
+
+#define IMXRT_GPIO3_DR           (IMXRT_GPIO3_BASE + IMXRT_GPIO_DR_OFFSET)
+#define IMXRT_GPIO3_GDIR         (IMXRT_GPIO3_BASE + IMXRT_GPIO_GDIR_OFFSET)
+#define IMXRT_GPIO3_PSR          (IMXRT_GPIO3_BASE + IMXRT_GPIO_PSR_OFFSET)
+#define IMXRT_GPIO3_ICR1         (IMXRT_GPIO3_BASE + IMXRT_GPIO_ICR1_OFFSET)
+#define IMXRT_GPIO3_ICR2         (IMXRT_GPIO3_BASE + IMXRT_GPIO_ICR2_OFFSET)
+#define IMXRT_GPIO3_IMR          (IMXRT_GPIO3_BASE + IMXRT_GPIO_IMR_OFFSET)
+#define IMXRT_GPIO3_ISR          (IMXRT_GPIO3_BASE + IMXRT_GPIO_ISR_OFFSET)
+#define IMXRT_GPIO3_EDGE         (IMXRT_GPIO3_BASE + IMXRT_GPIO_EDGE_OFFSET)
+
+#define IMXRT_GPIO4_DR           (IMXRT_GPIO4_BASE + IMXRT_GPIO_DR_OFFSET)
+#define IMXRT_GPIO4_GDIR         (IMXRT_GPIO4_BASE + IMXRT_GPIO_GDIR_OFFSET)
+#define IMXRT_GPIO4_PSR          (IMXRT_GPIO4_BASE + IMXRT_GPIO_PSR_OFFSET)
+#define IMXRT_GPIO4_ICR1         (IMXRT_GPIO4_BASE + IMXRT_GPIO_ICR1_OFFSET)
+#define IMXRT_GPIO4_ICR2         (IMXRT_GPIO4_BASE + IMXRT_GPIO_ICR2_OFFSET)
+#define IMXRT_GPIO4_IMR          (IMXRT_GPIO4_BASE + IMXRT_GPIO_IMR_OFFSET)
+#define IMXRT_GPIO4_ISR          (IMXRT_GPIO4_BASE + IMXRT_GPIO_ISR_OFFSET)
+#define IMXRT_GPIO4_EDGE         (IMXRT_GPIO4_BASE + IMXRT_GPIO_EDGE_OFFSET)
+
+/* Register bit definitions *****************************************************************/
+
+/* Most registers are laid out simply with one bit per pin */
+
+#define GPIO_PIN(n)              (1 << (n)) /* Bit n: Pin n, n=0-31 */
+
+/* GPIO interrupt configuration register 1/2 */
+
+#define GPIO_ICR_INDEX(n)        (((n) >> 4) & 1)
+#define GPIO_ICR_OFFSET(n)       (GPIO_ICR1_OFFSET + (GPIO_ICR_INDEX(n) << 2))
+
+#define GPIO_ICR_LOWLEVEL        0          /* Interrupt is low-level sensitive */
+#define GPIO_ICR_HIGHLEVEL       1          /* Interrupt is high-level sensitive */
+#define GPIO_ICR_RISINGEDGE      2          /* Interrupt is rising-edge sensitive */
+#define GPIO_ICR_FALLINGEDGE     3          /* Interrupt is falling-edge sensitive */
+
+#define GPIO_ICR_SHIFT(n)        (((n) & 15) << 1)
+#define GPIO_ICR_MASK(n)         (3 << GPIO_ICR_SHIFT(n))
+#define GPIO_ICR(i,n)            ((uint32_t)(i) << GPIO_ICR_SHIFT(n))
+
+#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_GPIO_H */

arch/arm/src/imxrt/chip/imxrt_lpuart.h

@@ -0,0 +1,416 @@
+/********************************************************************************************
+ * arch/arm/src/imxrt/imxrt_lpuart.h
+ *
+ *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ *   Author:  Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ********************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_LPUART_H
+#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_LPUART_H
+
+/********************************************************************************************
+ * Included Files
+ ********************************************************************************************/
+
+#include <nuttx/config.h>
+#include "chip/imxrt_memorymap.h"
+
+/********************************************************************************************
+ * Pre-processor Definitions
+ ********************************************************************************************/
+
+/* Register offsets *************************************************************************/
+
+#define IMXRT_LPUART_VERID_OFFSET      0x0000  /* Version ID Register */
+#define IMXRT_LPUART_PARAM_OFFSET      0x0004  /* Parameter Register */
+#define IMXRT_LPUART_GLOBAL_OFFSET     0x0008  /* LPUART Global Register */
+#define IMXRT_LPUART_PINCFG_OFFSET     0x000c  /* LPUART Pin Configuration Register */
+#define IMXRT_LPUART_BAUD_OFFSET       0x0010  /* LPUART Baud Rate Register */
+#define IMXRT_LPUART_STAT_OFFSET       0x0014  /* LPUART Status Register */
+#define IMXRT_LPUART_CTRL_OFFSET       0x0018  /* LPUART Control Register */
+#define IMXRT_LPUART_DATA_OFFSET       0x001c  /* LPUART Data Register */
+#define IMXRT_LPUART_MATCH_OFFSET      0x0020  /* LPUART Match Address Register */
+#define IMXRT_LPUART_MODIR_OFFSET      0x0024  /* LPUART Modem IrDA Register */
+#define IMXRT_LPUART_FIFO_OFFSET       0x0028  /* LPUART FIFO Register */
+#define IMXRT_LPUART_WATER_OFFSET      0x002c  /* LPUART Watermark Register */
+
+/* Register addresses ***********************************************************************/
+
+#define IMXRT_LPUART1_VERID            (IMXRT_LPUART1_BASE + IMXRT_LPUART_VERID_OFFSET)
+#define IMXRT_LPUART1_PARAM            (IMXRT_LPUART1_BASE + IMXRT_LPUART_PARAM_OFFSET)
+#define IMXRT_LPUART1_GLOBAL           (IMXRT_LPUART1_BASE + IMXRT_LPUART_GLOBAL_OFFSET)
+#define IMXRT_LPUART1_PINCFG           (IMXRT_LPUART1_BASE + IMXRT_LPUART_PINCFG_OFFSET)
+#define IMXRT_LPUART1_BAUD             (IMXRT_LPUART1_BASE + IMXRT_LPUART_BAUD_OFFSET)
+#define IMXRT_LPUART1_STAT             (IMXRT_LPUART1_BASE + IMXRT_LPUART_STAT_OFFSET)
+#define IMXRT_LPUART1_CTRL             (IMXRT_LPUART1_BASE + IMXRT_LPUART_CTRL_OFFSET)
+#define IMXRT_LPUART1_DATA             (IMXRT_LPUART1_BASE + IMXRT_LPUART_DATA_OFFSET)
+#define IMXRT_LPUART1_MATCH            (IMXRT_LPUART1_BASE + IMXRT_LPUART_MATCH_OFFSET)
+#define IMXRT_LPUART1_MODIR            (IMXRT_LPUART1_BASE + IMXRT_LPUART_MODIR_OFFSET)
+#define IMXRT_LPUART1_FIFO             (IMXRT_LPUART1_BASE + IMXRT_LPUART_FIFO_OFFSET)
+#define IMXRT_LPUART1_WATER            (IMXRT_LPUART1_BASE + IMXRT_LPUART_WATER_OFFSET)
+
+#define IMXRT_LPUART2_VERID            (IMXRT_LPUART2_BASE + IMXRT_LPUART_VERID_OFFSET)
+#define IMXRT_LPUART2_PARAM            (IMXRT_LPUART2_BASE + IMXRT_LPUART_PARAM_OFFSET)
+#define IMXRT_LPUART2_GLOBAL           (IMXRT_LPUART2_BASE + IMXRT_LPUART_GLOBAL_OFFSET)
+#define IMXRT_LPUART2_PINCFG           (IMXRT_LPUART2_BASE + IMXRT_LPUART_PINCFG_OFFSET)
+#define IMXRT_LPUART2_BAUD             (IMXRT_LPUART2_BASE + IMXRT_LPUART_BAUD_OFFSET)
+#define IMXRT_LPUART2_STAT             (IMXRT_LPUART2_BASE + IMXRT_LPUART_STAT_OFFSET)
+#define IMXRT_LPUART2_CTRL             (IMXRT_LPUART2_BASE + IMXRT_LPUART_CTRL_OFFSET)
+#define IMXRT_LPUART2_DATA             (IMXRT_LPUART2_BASE + IMXRT_LPUART_DATA_OFFSET)
+#define IMXRT_LPUART2_MATCH            (IMXRT_LPUART2_BASE + IMXRT_LPUART_MATCH_OFFSET)
+#define IMXRT_LPUART2_MODIR            (IMXRT_LPUART2_BASE + IMXRT_LPUART_MODIR_OFFSET)
+#define IMXRT_LPUART2_FIFO             (IMXRT_LPUART2_BASE + IMXRT_LPUART_FIFO_OFFSET)
+#define IMXRT_LPUART2_WATER            (IMXRT_LPUART2_BASE + IMXRT_LPUART_WATER_OFFSET)
+
+#define IMXRT_LPUART3_VERID            (IMXRT_LPUART3_BASE + IMXRT_LPUART_VERID_OFFSET)
+#define IMXRT_LPUART3_PARAM            (IMXRT_LPUART3_BASE + IMXRT_LPUART_PARAM_OFFSET)
+#define IMXRT_LPUART3_GLOBAL           (IMXRT_LPUART3_BASE + IMXRT_LPUART_GLOBAL_OFFSET)
+#define IMXRT_LPUART3_PINCFG           (IMXRT_LPUART3_BASE + IMXRT_LPUART_PINCFG_OFFSET)
+#define IMXRT_LPUART3_BAUD             (IMXRT_LPUART3_BASE + IMXRT_LPUART_BAUD_OFFSET)
+#define IMXRT_LPUART3_STAT             (IMXRT_LPUART3_BASE + IMXRT_LPUART_STAT_OFFSET)
+#define IMXRT_LPUART3_CTRL             (IMXRT_LPUART3_BASE + IMXRT_LPUART_CTRL_OFFSET)
+#define IMXRT_LPUART3_DATA             (IMXRT_LPUART3_BASE + IMXRT_LPUART_DATA_OFFSET)
+#define IMXRT_LPUART3_MATCH            (IMXRT_LPUART3_BASE + IMXRT_LPUART_MATCH_OFFSET)
+#define IMXRT_LPUART3_MODIR            (IMXRT_LPUART3_BASE + IMXRT_LPUART_MODIR_OFFSET)
+#define IMXRT_LPUART3_FIFO             (IMXRT_LPUART3_BASE + IMXRT_LPUART_FIFO_OFFSET)
+#define IMXRT_LPUART3_WATER            (IMXRT_LPUART3_BASE + IMXRT_LPUART_WATER_OFFSET)
+
+#define IMXRT_LPUART4_VERID            (IMXRT_LPUART4_BASE + IMXRT_LPUART_VERID_OFFSET)
+#define IMXRT_LPUART4_PARAM            (IMXRT_LPUART4_BASE + IMXRT_LPUART_PARAM_OFFSET)
+#define IMXRT_LPUART4_GLOBAL           (IMXRT_LPUART4_BASE + IMXRT_LPUART_GLOBAL_OFFSET)
+#define IMXRT_LPUART4_PINCFG           (IMXRT_LPUART4_BASE + IMXRT_LPUART_PINCFG_OFFSET)
+#define IMXRT_LPUART4_BAUD             (IMXRT_LPUART4_BASE + IMXRT_LPUART_BAUD_OFFSET)
+#define IMXRT_LPUART4_STAT             (IMXRT_LPUART4_BASE + IMXRT_LPUART_STAT_OFFSET)
+#define IMXRT_LPUART4_CTRL             (IMXRT_LPUART4_BASE + IMXRT_LPUART_CTRL_OFFSET)
+#define IMXRT_LPUART4_DATA             (IMXRT_LPUART4_BASE + IMXRT_LPUART_DATA_OFFSET)
+#define IMXRT_LPUART4_MATCH            (IMXRT_LPUART4_BASE + IMXRT_LPUART_MATCH_OFFSET)
+#define IMXRT_LPUART4_MODIR            (IMXRT_LPUART4_BASE + IMXRT_LPUART_MODIR_OFFSET)
+#define IMXRT_LPUART4_FIFO             (IMXRT_LPUART4_BASE + IMXRT_LPUART_FIFO_OFFSET)
+#define IMXRT_LPUART4_WATER            (IMXRT_LPUART4_BASE + IMXRT_LPUART_WATER_OFFSET)
+
+#define IMXRT_LPUART5_VERID            (IMXRT_LPUART5_BASE + IMXRT_LPUART_VERID_OFFSET)
+#define IMXRT_LPUART5_PARAM            (IMXRT_LPUART5_BASE + IMXRT_LPUART_PARAM_OFFSET)
+#define IMXRT_LPUART5_GLOBAL           (IMXRT_LPUART5_BASE + IMXRT_LPUART_GLOBAL_OFFSET)
+#define IMXRT_LPUART5_PINCFG           (IMXRT_LPUART5_BASE + IMXRT_LPUART_PINCFG_OFFSET)
+#define IMXRT_LPUART5_BAUD             (IMXRT_LPUART5_BASE + IMXRT_LPUART_BAUD_OFFSET)
+#define IMXRT_LPUART5_STAT             (IMXRT_LPUART5_BASE + IMXRT_LPUART_STAT_OFFSET)
+#define IMXRT_LPUART5_CTRL             (IMXRT_LPUART5_BASE + IMXRT_LPUART_CTRL_OFFSET)
+#define IMXRT_LPUART5_DATA             (IMXRT_LPUART5_BASE + IMXRT_LPUART_DATA_OFFSET)
+#define IMXRT_LPUART5_MATCH            (IMXRT_LPUART5_BASE + IMXRT_LPUART_MATCH_OFFSET)
+#define IMXRT_LPUART5_MODIR            (IMXRT_LPUART5_BASE + IMXRT_LPUART_MODIR_OFFSET)
+#define IMXRT_LPUART5_FIFO             (IMXRT_LPUART5_BASE + IMXRT_LPUART_FIFO_OFFSET)
+#define IMXRT_LPUART5_WATER            (IMXRT_LPUART5_BASE + IMXRT_LPUART_WATER_OFFSET)
+
+#define IMXRT_LPUART6_VERID            (IMXRT_LPUART6_BASE + IMXRT_LPUART_VERID_OFFSET)
+#define IMXRT_LPUART6_PARAM            (IMXRT_LPUART6_BASE + IMXRT_LPUART_PARAM_OFFSET)
+#define IMXRT_LPUART6_GLOBAL           (IMXRT_LPUART6_BASE + IMXRT_LPUART_GLOBAL_OFFSET)
+#define IMXRT_LPUART6_PINCFG           (IMXRT_LPUART6_BASE + IMXRT_LPUART_PINCFG_OFFSET)
+#define IMXRT_LPUART6_BAUD             (IMXRT_LPUART6_BASE + IMXRT_LPUART_BAUD_OFFSET)
+#define IMXRT_LPUART6_STAT             (IMXRT_LPUART6_BASE + IMXRT_LPUART_STAT_OFFSET)
+#define IMXRT_LPUART6_CTRL             (IMXRT_LPUART6_BASE + IMXRT_LPUART_CTRL_OFFSET)
+#define IMXRT_LPUART6_DATA             (IMXRT_LPUART6_BASE + IMXRT_LPUART_DATA_OFFSET)
+#define IMXRT_LPUART6_MATCH            (IMXRT_LPUART6_BASE + IMXRT_LPUART_MATCH_OFFSET)
+#define IMXRT_LPUART6_MODIR            (IMXRT_LPUART6_BASE + IMXRT_LPUART_MODIR_OFFSET)
+#define IMXRT_LPUART6_FIFO             (IMXRT_LPUART6_BASE + IMXRT_LPUART_FIFO_OFFSET)
+#define IMXRT_LPUART6_WATER            (IMXRT_LPUART6_BASE + IMXRT_LPUART_WATER_OFFSET)
+
+#define IMXRT_LPUART7_VERID            (IMXRT_LPUART7_BASE + IMXRT_LPUART_VERID_OFFSET)
+#define IMXRT_LPUART7_PARAM            (IMXRT_LPUART7_BASE + IMXRT_LPUART_PARAM_OFFSET)
+#define IMXRT_LPUART7_GLOBAL           (IMXRT_LPUART7_BASE + IMXRT_LPUART_GLOBAL_OFFSET)
+#define IMXRT_LPUART7_PINCFG           (IMXRT_LPUART7_BASE + IMXRT_LPUART_PINCFG_OFFSET)
+#define IMXRT_LPUART7_BAUD             (IMXRT_LPUART7_BASE + IMXRT_LPUART_BAUD_OFFSET)
+#define IMXRT_LPUART7_STAT             (IMXRT_LPUART7_BASE + IMXRT_LPUART_STAT_OFFSET)
+#define IMXRT_LPUART7_CTRL             (IMXRT_LPUART7_BASE + IMXRT_LPUART_CTRL_OFFSET)
+#define IMXRT_LPUART7_DATA             (IMXRT_LPUART7_BASE + IMXRT_LPUART_DATA_OFFSET)
+#define IMXRT_LPUART7_MATCH            (IMXRT_LPUART7_BASE + IMXRT_LPUART_MATCH_OFFSET)
+#define IMXRT_LPUART7_MODIR            (IMXRT_LPUART7_BASE + IMXRT_LPUART_MODIR_OFFSET)
+#define IMXRT_LPUART7_FIFO             (IMXRT_LPUART7_BASE + IMXRT_LPUART_FIFO_OFFSET)
+#define IMXRT_LPUART7_WATER            (IMXRT_LPUART7_BASE + IMXRT_LPUART_WATER_OFFSET)
+
+#define IMXRT_LPUART8_VERID            (IMXRT_LPUART8_BASE + IMXRT_LPUART_VERID_OFFSET)
+#define IMXRT_LPUART8_PARAM            (IMXRT_LPUART8_BASE + IMXRT_LPUART_PARAM_OFFSET)
+#define IMXRT_LPUART8_GLOBAL           (IMXRT_LPUART8_BASE + IMXRT_LPUART_GLOBAL_OFFSET)
+#define IMXRT_LPUART8_PINCFG           (IMXRT_LPUART8_BASE + IMXRT_LPUART_PINCFG_OFFSET)
+#define IMXRT_LPUART8_BAUD             (IMXRT_LPUART8_BASE + IMXRT_LPUART_BAUD_OFFSET)
+#define IMXRT_LPUART8_STAT             (IMXRT_LPUART8_BASE + IMXRT_LPUART_STAT_OFFSET)
+#define IMXRT_LPUART8_CTRL             (IMXRT_LPUART8_BASE + IMXRT_LPUART_CTRL_OFFSET)
+#define IMXRT_LPUART8_DATA             (IMXRT_LPUART8_BASE + IMXRT_LPUART_DATA_OFFSET)
+#define IMXRT_LPUART8_MATCH            (IMXRT_LPUART8_BASE + IMXRT_LPUART_MATCH_OFFSET)
+#define IMXRT_LPUART8_MODIR            (IMXRT_LPUART8_BASE + IMXRT_LPUART_MODIR_OFFSET)
+#define IMXRT_LPUART8_FIFO             (IMXRT_LPUART8_BASE + IMXRT_LPUART_FIFO_OFFSET)
+#define IMXRT_LPUART8_WATER            (IMXRT_LPUART8_BASE + IMXRT_LPUART_WATER_OFFSET)
+
+/* Register bit definitions *****************************************************************/
+
+/* Version ID Register */
+
+#define LPUART_VERID_FEATURE_SHIFT     (0)        /* Bits 0-15: Feature Identification Number */
+#define LPUART_VERID_FEATURE_MASK      (0xffff << LPUART_VERID_FEATURE_SHIFT)
+#  define LPUART_VERID_FEATURE_STD     (1 << LPUART_VERID_FEATURE_SHIFT) /* Standard feature set */
+#  define LPUART_VERID_FEATURE_MODEM   (3 << LPUART_VERID_FEATURE_SHIFT) /* MODEM/IrDA support */
+#define LPUART_VERID_MINOR_SHIFT       (16)       /* Bits 16-23: Minor Version Number */
+#define LPUART_VERID_MINOR_MASK        (0xff << LPUART_VERID_MINOR_SHIFT)
+#define LPUART_VERID_MAJOR_SHIFT       (24)       /* Bits 24-31: Major Version Number */
+#define LPUART_VERID_MAJOR_MASK        (0xff << LPUART_VERID_MAJOR_SHIFT)
+
+/* Parameter Register */
+
+#define LPUART_PARAM_TXFIFO_SHIFT      (0)       /* Bits 0-7: Transmit FIFO Size */
+#define LPUART_PARAM_TXFIFO_MASK       (0xff << LPUART_PARAM_TXFIFO_SHIFT)
+#define LPUART_PARAM_RXFIFO_SHIFT      (8)       /* Bits 8-15: Transmit FIFO Size */
+#define LPUART_PARAM_RXFIFO_MASK       (0xff << LPUART_PARAM_RXFIFO_SHIFT)
+                                                 /* Bits 16-31: Reserved */
+
+/* LPUART Global Register */
+
+                                                 /* Bit 0:  Reserved */
+#define LPUART_GLOBAL_RST              (1 << 1)  /* Bit 1: Software Reset */
+                                                 /* Bits 2-31:  Reserved */
+
+/* LPUART Pin Configuration Register */
+
+#define LPUART_PINCFG_TRGSEL_SHIFT     (0)       /* Bits 0-1:  Trigger Select */
+#define LPUART_PINCFG_TRGSEL_MASK      (3 << LPUART_PINCFG_TRGSEL_SHIFT)
+#  define LPUART_PINCFG_TRGSEL_DISABLE (0 << LPUART_PINCFG_TRGSEL_SHIFT) /* Trigger disabled */
+#  define LPUART_PINCFG_TRGSEL_RXD     (1 << LPUART_PINCFG_TRGSEL_SHIFT) /* Trigger used instead of RXD pin */
+#  define LPUART_PINCFG_TRGSEL_CTSB    (2 << LPUART_PINCFG_TRGSEL_SHIFT) /* Trigger used instead of CTS_B pin */
+#  define LPUART_PINCFG_TRGSEL_TXDMOD  (3 << LPUART_PINCFG_TRGSEL_SHIFT) /* Trigger used to modulate the TXD output */
+                                                 /* Bits 2-31:  Reserved */
+
+/* LPUART Baud Rate Register */
+
+#define LPUART_BAUD_SBR_SHIFT          (0)       /* Bits 0-12: Baud Rate Modulo Divisor. */
+#define LPUART_BAUD_SBR_MASK           (0x1fff << LPUART_BAUD_SBR_SHIFT)
+#  define LPUART_BAUD_SBR(n)           ((uint32_t)(n) << LPUART_BAUD_SBR_SHIFT)
+#define LPUART_BAUD_SBNS               (1 << 13) /* Bit 13: Stop Bit Number Select */
+#define LPUART_BAUD_RXEDGIE            (1 << 14) /* Bit 14: RX Input Active Edge Interrupt Enable */
+#define LPUART_BAUD_LBKDIE             (1 << 15) /* Bit 15: LIN Break Detect Interrupt Enable */
+#define LPUART_BAUD_RESYNCDIS          (1 << 16) /* Bit 16: Resynchronization Disable */
+#define LPUART_BAUD_BOTHEDGE           (1 << 17) /* Bit 17: Both Edge Sampling */
+#define LPUART_BAUD_MATCFG_SHIFT       (18)      /* Bits 18-19: Match Configuration */
+#define LPUART_BAUD_MATCFG_MASK        (3 << LPUART_BAUD_MATCFG_SHIFT)
+#  define LPUART_BAUD_MATCFG_ADDR      (0 << LPUART_BAUD_MATCFG_SHIFT) /* Address Match Wakeup */
+#  define LPUART_BAUD_MATCFG_IDLE      (1 << LPUART_BAUD_MATCFG_SHIFT) /* Idle Match Wakeup */
+#  define LPUART_BAUD_MATCFG_ONOFF     (2 << LPUART_BAUD_MATCFG_SHIFT) /* Match On and Match Off */
+#  define LPUART_BAUD_MATCFG_RWUENAB   (3 << LPUART_BAUD_MATCFG_SHIFT) /* Enables RWU on Data Match and Match
+                                                                        * On/Off for transmitter CTS input */
+                                                 /* Bit 20: Reserved */
+#define LPUART_BAUD_RDMAE              (1 << 21) /* Bit 21: Receiver Full DMA Enable */
+                                                 /* Bit 22: Reserved */
+#define LPUART_BAUD_TDMAE              (1 << 23) /* Bit 23: Transmitter DMA Enable */
+#define LPUART_BAUD_OSR_SHIFT          (28)      /* Bits 24-28: Oversampling Ratio */
+#define LPUART_BAUD_OSR_MASK           (31 << LPUART_BAUD_OSR_SHIFT)
+  #define LPUART_BAUD_OSR(n)           ((uint32_t)((n) - 1) << LPUART_BAUD_OSR_SHIFT)
+#define LPUART_BAUD_M10                (1 << 29) /* Bit 20: 10-bit Mode select */
+#define LPUART_BAUD_MAEN2              (1 << 30) /* Bit 30: Match Address Mode Enable 2 */
+#define LPUART_BAUD_MAEN1              (1 << 31) /* Bit 31: Match Address Mode Enable 1 */
+
+/* LPUART Status Register */
+
+                                                 /* Bits 0-13:  Reserved */
+#define LPUART_STAT_MA2F               (1 << 14) /* Bit 14: Match 2 Flag */
+#define LPUART_STAT_MA1F               (1 << 15) /* Bit 15: Match 1 Flag */
+#define LPUART_STAT_PF                 (1 << 16) /* Bit 16: Parity Error Flag */
+#define LPUART_STAT_FE                 (1 << 17) /* Bit 17: Framing Error Flag */
+#define LPUART_STAT_NF                 (1 << 18) /* Bit 18: Noise Flag */
+#define LPUART_STAT_OR                 (1 << 19) /* Bit 19: Receiver Overrun Flag */
+#define LPUART_STAT_IDLE               (1 << 20) /* Bit 20: Idle Line Flag */
+#define LPUART_STAT_RDRF               (1 << 21) /* Bit 21: Receive Data Register Full Flag */
+#define LPUART_STAT_TC                 (1 << 22) /* Bit 22: Transmission Complete Flag */
+#define LPUART_STAT_TDRE               (1 << 23) /* Bit 23: Transmit Data Register Empty Flag */
+#define LPUART_STAT_RAF                (1 << 24) /* Bit 24: Receiver Active Flag */
+#define LPUART_STAT_LBKDE              (1 << 25) /* Bit 25: LIN Break Detection Enable */
+#define LPUART_STAT_BRK13              (1 << 26) /* Bit 26: Break Character Generation Length */
+#define LPUART_STAT_RWUID              (1 << 27) /* Bit 27: Receive Wake Up Idle Detect */
+#define LPUART_STAT_RXINV              (1 << 28) /* Bit 28: Receive Data Inversion */
+#define LPUART_STAT_MSBF               (1 << 29) /* Bit 29: MSB First */
+#define LPUART_STAT_RXEDGIF            (1 << 30) /* Bit 30: RXD Pin Active Edge Interrupt Flag */
+#define LPUART_STAT_LBKDIF             (1 << 31) /* Bit 31: LIN Break Detect Interrupt Flag */
+
+/* LPUART Control Register */
+
+#define LPUART_CTRL_PT                 (1 << 0)  /* Bit 0:  Parity Type */
+#  define LPUART_CTRL_PT_EVEN          (0 << 0)  /*         Even parity */
+#  define LPUART_CTRL_PT_ODD           (1 << 0)  /*         Odd parity */
+#define LPUART_CTRL_PE                 (1 << 1)  /* Bit 1:  Parity Enable */
+#define LPUART_CTRL_ILT                (1 << 2)  /* Bit 2:  Idle Line Type Select */
+#define LPUART_CTRL_WAKE               (1 << 3)  /* Bit 3:  Receiver Wakeup Method Select */
+#define LPUART_CTRL_M                  (1 << 4)  /* Bit 4:  9-Bit or 8-Bit Mode Select */
+#define LPUART_CTRL_RSRC               (1 << 5)  /* Bit 5:  Receiver Source Select */
+#define LPUART_CTRL_DOZEEN             (1 << 6)  /* Bit 6:  Doze Enable */
+#define LPUART_CTRL_LOOPS              (1 << 7)  /* Bit 7:  Loop Mode Select */
+#define LPUART_CTRL_IDLECFG_SHIFT      (8)       /* Bits 8-10: Idle Configuration */
+#define LPUART_CTRL_IDLECFG_MASK       (7 << LPUART_CTRL_IDLECFG_SHIFT)
+#  define LPUART_CTRL_IDLECFG_1        (0 << LPUART_CTRL_IDLECFG_SHIFT) /* 1 idle character */
+#  define LPUART_CTRL_IDLECFG_2        (1 << LPUART_CTRL_IDLECFG_SHIFT) /* 2 idle characters */
+#  define LPUART_CTRL_IDLECFG_4        (2 << LPUART_CTRL_IDLECFG_SHIFT) /* 4 idle characters */
+#  define LPUART_CTRL_IDLECFG_8        (3 << LPUART_CTRL_IDLECFG_SHIFT) /* 8 idle characters */
+#  define LPUART_CTRL_IDLECFG_16       (4 << LPUART_CTRL_IDLECFG_SHIFT) /* 6 idle characters */
+#  define LPUART_CTRL_IDLECFG_32       (5 << LPUART_CTRL_IDLECFG_SHIFT) /* 32 idle characters */
+#  define LPUART_CTRL_IDLECFG_64       (6 << LPUART_CTRL_IDLECFG_SHIFT) /* 64 idle characters */
+#  define LPUART_CTRL_IDLECFG_128      (7 << LPUART_CTRL_IDLECFG_SHIFT) /* 128 idle characters */
+#define LPUART_CTRL_M7                 (1 << 11) /* Bit 11: 7-Bit Mode Select */
+                                                 /* Bits 12-13:  Reserved */
+#define LPUART_CTRL_MA2IE              (1 << 14) /* Bit 14: Match 2 Interrupt Enable */
+#define LPUART_CTRL_MA1IE              (1 << 15) /* Bit 15: Match 1 Interrupt Enable */
+#define LPUART_CTRL_SBK                (1 << 16) /* Bit 16: Send Break */
+#define LPUART_CTRL_RWU                (1 << 17) /* Bit 17: Receiver Wakeup Control */
+#define LPUART_CTRL_RE                 (1 << 18) /* Bit 18: Receiver Enable */
+#define LPUART_CTRL_TE                 (1 << 19) /* Bit 19: Transmitter Enable */
+#define LPUART_CTRL_ILIE               (1 << 20) /* Bit 20: Idle Line Interrupt Enable */
+#define LPUART_CTRL_RIE                (1 << 21) /* Bit 21: Receiver Interrupt Enable */
+#define LPUART_CTRL_TCIE               (1 << 22) /* Bit 22: Transmission Complete Interrupt Enable */
+#define LPUART_CTRL_TIE                (1 << 23) /* Bit 23: Transmit Interrupt Enable */
+#define LPUART_CTRL_PEIE               (1 << 24) /* Bit 24: Parity Error Interrupt Enable */
+#define LPUART_CTRL_FEIE               (1 << 25) /* Bit 25: Framing Error Interrupt Enable */
+#define LPUART_CTRL_NEIE               (1 << 26) /* Bit 26: Noise Error Interrupt Enable */
+#define LPUART_CTRL_ORIE               (1 << 27) /* Bit 27: Overrun Interrupt Enable */
+#define LPUART_CTRL_TXINV              (1 << 28) /* Bit 28: Transmit Data Inversion */
+#define LPUART_CTRL_TXDIR              (1 << 29) /* Bit 29: TXD Pin Direction in Single-Wire Mode */
+#define LPUART_CTRL_R9T8               (1 << 30) /* Bit 30: Receive Bit 9 / Transmit Bit 8 */
+#define LPUART_CTRL_R8T9               (1 << 31) /* Bit 31: Receive Bit 8 / Transmit Bit 9 */
+
+#define LPUART_ALL_INTS (LPUART_CTRL_ORIE | LPUART_CTRL_NEIE | LPUART_CTRL_FEIE |  \
+                         LPUART_CTRL_PEIE | LPUART_CTRL_TIE  | LPUART_CTRL_TCIE |  \
+                         LPUART_CTRL_RIE  | LPUART_CTRL_ILIE | LPUART_CTRL_MA1IE | \
+                         LPUART_CTRL_MA2IE)
+
+/* LPUART Data Register */
+
+#define LPUART_DATA_SHIFT              (0)       /* Bits 0-9: Data bits 0-9 */
+#define LPUART_DATA_MASK               (0x3ff << LPUART_DATA_SHIFT)
+                                                 /* Bit 10:  Reserved */
+#define LPUART_DATA_STATUS_SHIFT       (11)      /* Bit 11: Idle Line status */
+#define LPUART_DATA_IDLINE             (1 << 11) /* Bit 11: Idle Line */
+#define LPUART_DATA_RXEMPT             (1 << 12) /* Bit 12: Receive Buffer Empty */
+#define LPUART_DATA_FRETSC             (1 << 13) /* Bit 13: Frame Error / Transmit Special Character */
+#define LPUART_DATA_PARITYE            (1 << 14) /* Bit 14: Parity Error */
+#define LPUART_DATA_NOISY              (1 << 15) /* Bit 15: Noisy */
+                                                 /* Bits 16-31:  Reserved */
+
+/* LPUART Match Address Register */
+
+#define LPUART_MATCH_MA1_SHIFT         (0)       /* Bits 0-9: Match Address 1 */
+#define LPUART_MATCH_MA1_MASK          (0x3ff << LPUART_MATCH_MA1_SHIFT)
+#  define LPUART_MATCH_MA1(n)          ((uint32_t)(n) << LPUART_MATCH_MA1_SHIFT)
+                                                 /* Bits 10-15:  Reserved */
+#define LPUART_MATCH_MA2_SHIFT         (16)      /* Bits 16-25: Match Address 2 */
+#define LPUART_MATCH_MA2_MASK          (0x3ff << LPUART_MATCH_MA2_SHIFT)
+#  define LPUART_MATCH_MA2(n)          ((uint32_t)(n) << LPUART_MATCH_MA2_SHIFT)
+                                                 /* Bits 26-31:  Reserved */
+
+/* LPUART Modem IrDA Register */
+
+#define LPUART_MODIR_TXCTSE            (1 << 0)  /* Bit nn:  Transmitter clear-to-send enable */
+#define LPUART_MODIR_TXRTSE            (1 << 1)  /* Bit nn:  Transmitter request-to-send enable */
+#define LPUART_MODIR_TXRTSPOL          (1 << 2)  /* Bit nn:  Transmitter request-to-send polarity */
+#define LPUART_MODIR_RXRTSE            (1 << 3)  /* Bit nn:  Receiver request-to-send enable */
+#define LPUART_MODIR_TXCTSC            (1 << 4)  /* Bit nn:  Transmit CTS Configuration */
+#  define LPUART_MODIR_TXCTSC_START    (0 << 4)  /* CTS sampled at start of character */
+#  define LPUART_MODIR_TXCTSC_IDLE     (1 << 4)  /* CTS sampled when transmitter idle */
+#define LPUART_MODIR_TXCTSSRC          (1 << 5)  /* Bit nn:  Transmit CTS Source */
+#  define LPUART_MODIR_TXCTSSRC_CTSB   (0 << 5)  /* Bit nn:  CTS input is CTS_B pin */
+#  define LPUART_MODIR_TXCTSSRC_RXMAT  (1 << 5)  /* Bit nn:  Transmit CTS Source */
+                                                 /* Bits 6-7:  Reserved */
+#define LPUART_MODIR_RTSWATER          (8)       /* Bits 8-9: Receive RTS Configuration */
+                                                 /* Bits 10-15:  Reserved */
+#define LPUART_MODIR_TNP_SHIFT         (16)      /* Bits 16-17: Transmitter narrow pulse */
+#define LPUART_MODIR_TNP_MASK          (3 << LPUART_MODIR_TNP_SHIFT)
+#  define LPUART_MODIR_TNP(n)          ((uint32_t)((n) - 1) << LPUART_MODIR_TNP_SHIFT) /* n/OSR */
+#define LPUART_MODIR_IREN              (1 << 18) /* Bit nn: Infrared enable */
+                                                 /* Bits 19-31:  Reserved */
+
+/* LPUART FIFO Register */
+
+#define LPUART_FIFO_RXFIFOSIZE_SHIFT   (0)       /* Bits 0-2: Receive FIFO. Buffer Depth */
+#define LPUART_FIFO_RXFIFOSIZE_MASK    (7 << LPUART_FIFO_RXFIFOSIZE_SHIFT)
+#  define LPUART_FIFO_RXFIFOSIZE_1     (0 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 1 datawords */
+#  define LPUART_FIFO_RXFIFOSIZE_4     (1 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 4 datawords */
+#  define LPUART_FIFO_RXFIFOSIZE_8     (2 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 8 datawords */
+#  define LPUART_FIFO_RXFIFOSIZE_16    (3 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 16 datawords */
+#  define LPUART_FIFO_RXFIFOSIZE_32    (4 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 32 datawords */
+#  define LPUART_FIFO_RXFIFOSIZE_64    (5 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 64 datawords */
+#  define LPUART_FIFO_RXFIFOSIZE_128   (6 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 128 datawords */
+#  define LPUART_FIFO_RXFIFOSIZE_256   (7 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 256 datawords */
+#define LPUART_FIFO_TXFIFOSIZE_SHIFT   (4)       /* Bits 4-6: Transmit FIFO. Buffer Depth */
+#define LPUART_FIFO_TXFIFOSIZE_MASK    (7 << LPUART_FIFO_TXFIFOSIZE_SHIFT)
+#  define LPUART_FIFO_TXFIFOSIZE_1     (0 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* 1 datawords */
+#  define LPUART_FIFO_TXFIFOSIZE_4     (1 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* 4 datawords */
+#  define LPUART_FIFO_TXFIFOSIZE_8     (2 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* 8 datawords */
+#  define LPUART_FIFO_TXFIFOSIZE_16    (3 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* 16 datawords */
+#  define LPUART_FIFO_TXFIFOSIZE_32    (4 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* 32 datawords */
+#  define LPUART_FIFO_TXFIFOSIZE_64    (5 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* 64 datawords */
+#  define LPUART_FIFO_TXFIFOSIZE_128   (6 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* 128 datawords */
+#  define LPUART_FIFO_TXFIFOSIZE_256   (7 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* 256 datawords */
+
+#define LPUART_FIFO_TXFE               (1 << 7)  /* Bit 7:  Transmit FIFO Enable */
+#define LPUART_FIFO_RXUFE              (1 << 8)  /* Bit 8:  Receive FIFO Underflow Interrupt Enable */
+#define LPUART_FIFO_TXOFE              (1 << 9)  /* Bit 9:  Transmit FIFO Overflow Interrupt Enable */
+#define LPUART_FIFO_RXIDEN_SHIFT       (10)      /* Bits 10-12:  Receiver Idle Empty Enable */
+#define LPUART_FIFO_RXIDEN_MASK        (7 << LPUART_FIFO_RXIDEN_SHIFT)
+#  define LPUART_FIFO_RXIDEN_DISABLE   (0 << LPUART_FIFO_RXIDEN_SHIFT) /* Disable RDRF assertion when receiver is idle */
+#  define LPUART_FIFO_RXIDEN_1         (1 << LPUART_FIFO_RXIDEN_SHIFT) /* Enable RDRF assertion when receiver idle for 1 word */
+#  define LPUART_FIFO_RXIDEN_2         (2 << LPUART_FIFO_RXIDEN_SHIFT) /* Enable RDRF assertion when receiver idle for 2 words */
+#  define LPUART_FIFO_RXIDEN_4         (3 << LPUART_FIFO_RXIDEN_SHIFT) /* Enable RDRF assertion when receiver idle for 4 words */
+#  define LPUART_FIFO_RXIDEN_8         (4 << LPUART_FIFO_RXIDEN_SHIFT) /* Enable RDRF assertion when receiver idle for 8 words */
+#  define LPUART_FIFO_RXIDEN_16        (5 << LPUART_FIFO_RXIDEN_SHIFT) /* Enable RDRF assertion when receiver idle for 16 words */
+#  define LPUART_FIFO_RXIDEN_32        (6 << LPUART_FIFO_RXIDEN_SHIFT) /* Enable RDRF assertion when receiver idle for 32 words */
+#  define LPUART_FIFO_RXIDEN_64        (7 << LPUART_FIFO_RXIDEN_SHIFT) /* Enable RDRF assertion when receiver idle for 64 words */
+
+#define LPUART_FIFO_RXFLUSH            (1 << 14) /* Bit 14: Receive FIFO/Buffer Flush */
+#define LPUART_FIFO_TXFLUSH            (1 << 15) /* Bit 15: Transmit FIFO/Buffer Flush */
+#define LPUART_FIFO_RXUF               (1 << 16) /* Bit 16: Receiver Buffer Underflow Flag */
+#define LPUART_FIFO_TXOF               (1 << 17) /* Bit 17: Transmitter Buffer Overflow Flag */
+                                                 /* Bits 18-21:  Reserved */
+#define LPUART_FIFO_RXEMPT             (1 << 22) /* Bit 22: Receive Buffer/FIFO Empty */
+#define LPUART_FIFO_TXEMPT             (1 << 23) /* Bit 23: Transmit Buffer/FIFO Empty */
+                                                 /* Bits 24-31:  Reserved */
+
+/* LPUART Watermark Register */
+
+#define LPUART_WATER_TXWATER_SHIFT     (0)       /* Bits 0-1: Transmit Watermark */
+#define LPUART_WATER_TXWATER_MASK      (3 << LPUART_WATER_TXWATER_SHIFT)
+#  define LPUART_WATER_TXWATER(n)      ((uint32_t)(n) << LPUART_WATER_TXWATER_SHIFT)
+                                                 /* Bits 2-7:  Reserved */
+#define LPUART_WATER_TXCOUNT_SHIFT     (8)       /* Bits 8-10:Transmit Counter */
+#define LPUART_WATER_TXCOUNT_MASK      (7 << LPUART_WATER_TXCOUNT_SHIFT)
+#  define LPUART_WATER_TXCOUNT(n)      ((uint32_t)(n) << LPUART_WATER_TXCOUNT_SHIFT)
+                                                 /* Bits 11-15:  Reserved */
+#define LPUART_WATER_RXWATER_SHIFT     (16)      /* Bits 16-17: Receive Watermark */
+#define LPUART_WATER_RXWATER_MASK      (3 << LPUART_WATER_RXWATER_SHIFT)
+#  define LPUART_WATER_RXWATER(n)      ((uint32_t)(n) << LPUART_WATER_RXWATER_SHIFT)
+                                                 /* Bits 18-23:  Reserved */
+#define LPUART_WATER_RXCOUNT_SHIFT     (24)      /* Bits 24-26: Receive Counter */
+#define LPUART_WATER_RXCOUNT_MASK      (7 << LPUART_WATER_RXCOUNT_SHIFT)
+#  define LPUART_WATER_RXCOUNT(n)      ((uint32_t)(n) << LPUART_WATER_RXCOUNT_SHIFT)
+                                                 /* Bits 27-31:  Reserved */
+
+#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_LPUART_H */

arch/arm/src/imxrt/chip/imxrt_memorymap.h

@@ -0,0 +1,51 @@
+/************************************************************************************
+ * arch/arm/src/imxrt/chip/imxrt_memorymap.h
+ *
+ *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_MEMORYMAP_H
+#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_MEMORYMAP_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+#if defined(CONFIG_ARCH_FAMILY_IMXRT105x)
+#  include "chip/imxrt105x_memorymap.h"
+#else
+#  error Unrecognized i.MX RT architecture
+#endif
+
+#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_MEMORYMAP_H */

arch/arm/src/imxrt/chip/imxrt_src.h

@@ -0,0 +1,157 @@
+/********************************************************************************************
+ * arch/arm/src/imxrt/imxrt_src.h
+ *
+ *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ *   Author:  Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ********************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_SRC_H
+#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_SRC_H
+
+/********************************************************************************************
+ * Included Files
+ ********************************************************************************************/
+
+#include <nuttx/config.h>
+#include "chip/imxrt_memorymap.h"
+
+/********************************************************************************************
+ * Pre-processor Definitions
+ ********************************************************************************************/
+
+/* Register offsets *************************************************************************/
+
+#define IMXRT_SRC_SCR_OFFSET              0x0000  /* SRC Control Register */
+#define IMXRT_SRC_SBMR1_OFFSET            0x0004  /* SRC Boot Mode Register 1 */
+#define IMXRT_SRC_SRSR_OFFSET             0x0008  /* SRC Reset Status Register */
+#define IMXRT_SRC_SBMR2_OFFSET            0x001c  /* SRC Boot Mode Register 2 */
+#define IMXRT_SRC_GPR1_OFFSET             0x0020  /* SRC General Purpose Register 1 */
+#define IMXRT_SRC_GPR2_OFFSET             0x0024  /* SRC General Purpose Register 2 */
+#define IMXRT_SRC_GPR3_OFFSET             0x0028  /* SRC General Purpose Register 3 */
+#define IMXRT_SRC_GPR4_OFFSET             0x002c  /* SRC General Purpose Register 4 */
+#define IMXRT_SRC_GPR5_OFFSET             0x0030  /* SRC General Purpose Register 5 */
+#define IMXRT_SRC_GPR6_OFFSET             0x0034  /* SRC General Purpose Register 6 */
+#define IMXRT_SRC_GPR7_OFFSET             0x0038  /* SRC General Purpose Register 7 */
+#define IMXRT_SRC_GPR8_OFFSET             0x003c  /* SRC General Purpose Register 8 */
+#define IMXRT_SRC_GPR9_OFFSET             0x0040  /* SRC General Purpose Register 9 */
+#define IMXRT_SRC_GPR10_OFFSET            0x0044  /* SRC General Purpose Register 10 */
+
+/* Register addresses ***********************************************************************/
+
+#define IMXRT_SRC_SCR                     (IMXRT_SRC_BASE + IMXRT_SRC_SCR_OFFSET)
+#define IMXRT_SRC_SBMR1                   (IMXRT_SRC_BASE + IMXRT_SRC_SBMR1_OFFSET)
+#define IMXRT_SRC_SRSR                    (IMXRT_SRC_BASE + IMXRT_SRC_SRSR_OFFSET)
+#define IMXRT_SRC_SBMR2                   (IMXRT_SRC_BASE + IMXRT_SRC_SBMR2_OFFSET)
+#define IMXRT_SRC_GPR1                    (IMXRT_SRC_BASE + IMXRT_SRC_GPR1_OFFSET)
+#define IMXRT_SRC_GPR2                    (IMXRT_SRC_BASE + IMXRT_SRC_GPR2_OFFSET)
+#define IMXRT_SRC_GPR3                    (IMXRT_SRC_BASE + IMXRT_SRC_GPR3_OFFSET)
+#define IMXRT_SRC_GPR4                    (IMXRT_SRC_BASE + IMXRT_SRC_GPR4_OFFSET)
+#define IMXRT_SRC_GPR5                    (IMXRT_SRC_BASE + IMXRT_SRC_GPR5_OFFSET)
+#define IMXRT_SRC_GPR6                    (IMXRT_SRC_BASE + IMXRT_SRC_GPR6_OFFSET)
+#define IMXRT_SRC_GPR7                    (IMXRT_SRC_BASE + IMXRT_SRC_GPR7_OFFSET)
+#define IMXRT_SRC_GPR8                    (IMXRT_SRC_BASE + IMXRT_SRC_GPR8_OFFSET)
+#define IMXRT_SRC_GPR9                    (IMXRT_SRC_BASE + IMXRT_SRC_GPR9_OFFSET)
+#define IMXRT_SRC_GPR10                   (IMXRT_SRC_BASE + IMXRT_SRC_GPR10_OFFSET)
+
+/* Register bit definitions *****************************************************************/
+
+/* SRC Control Register */
+
+                                                    /* Bits 0-3: Reserved */
+#define SRC_SCR_LOCKUP_RST                (1 << 4)  /* Bit 4: Lockup reset enable bit */
+                                                    /* Bits 5-6: Reserved */
+#define SRC_SCR_MASK_WDOG_RST_SHIFT       (7)       /* Bits 7-10: Mask wdog_rst_b source */
+#define SRC_SCR_MASK_WDOG_RST_MASK        (15 << SRC_SCR_MASK_WDOG_RST_SHIFT)
+#  define SRC_SCR_MASK_WDOG_RST_MASKED    (5 << SRC_SCR_MASK_WDOG_RST_SHIFT)
+#  define SRC_SCR_MASK_WDOG_RST_UNMASKED  (10 << SRC_SCR_MASK_WDOG_RST_SHIFT)
+                                                    /* Bits 11-12: Reserved */
+#define SRC_SCR_CORE0_RST                 (1 << 13) /* Bit 13: Software reset for core0 only. */
+                                                    /* Bits 14-16: Reserved */
+#define SRC_SCR_CORE0_DBG_RST             (1 << 17) /* Bit 17: Software reset for core0 debug only */
+                                                    /* Bits 18-24: Reserved */
+#define SRC_SCR_DBG_RST_MSK_PG            (1 << 25) /* Bit 25: Do not assert debug resets
+                                                     * after power gating event of core */
+                                                    /* Bits 26-27: Reserved */
+#define SRC_SCR_MASK_WDOG3_RST_SHIFT      (28)      /* Bits 38-31: Mask wdog3_rst_b source */
+#define SRC_SCR_MASK_WDOG3_RST_MASK       (15 << SRC_SCR_MASK_WDOG3_RST_SHIFT)
+#  define SRC_SCR_MASK_WDOG3_RST_MASKED   (5 << SRC_SCR_MASK_WDOG3_RST_SHIFT)
+#  define SRC_SCR_MASK_WDOG3_RST_UNMASKED (10 << SRC_SCR_MASK_WDOG3_RST_SHIFT)
+
+/* SRC Boot Mode Register 1 */
+
+#define SRC_SBMR1_BOOT_CFG_SHIFT          (24)      /* Bits 24-31: Refer to fusemap */
+#define SRC_SBMR1_BOOT_CFG_MASK           (0xff << SRC_SBMR1_BOOT_CFG_SHIFT)
+#define SRC_SBMR1_BOOT_CFG2_SHIFT         (16)      /* Bits 16-23: Refer to fusemap */
+#define SRC_SBMR1_BOOT_CFG2_MASK          (0xff << SRC_SBMR1_BOOT_CFG2_SHIFT)
+#define SRC_SBMR1_BOOT_CFG3_SHIFT         (8)       /* Bits 8-15:  Refer to fusemap */
+#define SRC_SBMR1_BOOT_CFG3_MASK          (0xff << SRC_SBMR1_BOOT_CFG3_SHIFT)
+#define SRC_SBMR1_BOOT_CFG4_SHIFT         (0)       /* Bits 0-7:   Refer to fusemap */
+#define SRC_SBMR1_BOOT_CFG4_MASK          (0xff << SRC_SBMR1_BOOT_CFG4_SHIFT)
+
+/* SRC Reset Status Register */
+
+#define SRC_SRSR_IPP_RESET_B              (1 << 0)  /* Bit 0:  Indicates whether reset was the
+                                                     * result of ipp_reset_b pin (Power-up
+                                                     * sequence) */
+#define SRC_SRSR_LOCKUP_SYSRESETREQ       (1 << 1)  /* Bit 1:  Indicates a reset has been
+                                                     * caused by CPU lockup or software setting
+                                                     * of SYSRESETREQ bit */
+#define SRC_SRSR_CSU_RESET_B              (1 << 2)  /* Bit 2:  Indicates whether the reset was
+                                                     * the result of the csu_reset_b input */
+#define SRC_SRSR_IPP_USER_RESET_B         (1 << 3)  /* Bit 3:  Indicates whether the reset was
+                                                     * the result of the ipp_user_reset_b qualified
+                                                     * reset */
+#define SRC_SRSR_WDOG_RST_B               (1 << 4)  /* Bit 4:  IC Watchdog Time-out reset */
+#define SRC_SRSR_JTAG_RST_B               (1 << 5)  /* Bit 5:  HIGH - Z JTAG reset */
+#define SRC_SRSR_JTAG_SW_RST              (1 << 6)  /* Bit 6:  JTAG software reset */
+#define SRC_SRSR_WDOG3_RST_B              (1 << 7)  /* Bit 7:  IC Watchdog3 Time-out reset */
+#define SRC_SRSR_TEMPSENSE_RST_B          (1 << 8)  /* Bit 8:  Temper Sensor software reset */
+                                                    /* Bits 9-31: Reserved */
+
+/* SRC Boot Mode Register 2 */
+
+#define SRC_SBMR2_SEC_CONFIG_SHIFT        (0)       /* Bits 0-1:  State of the corresponding
+                                                     * SECONFIG fuse */
+                                                    /* Bit 2:  Reserved */
+#define SRC_SBMR2_DIR_BT_DIS              (1 << 3)  /* Bit 3:  State of the DIR_BT_DIS fuse */
+#define SRC_SBMR2_BT_FUSE_SEL             (1 << 4)  /* Bit 4:  State of the BT_FUSE_SEL fuse */
+                                                    /* Bits 5-23: Reserved */
+#define SRC_SBMR2_BMOD_SHIFT              (24)      /* Bits 24-25: Latched state of the BOOT_MODE
+                                                     *  and BOOT_MODE0 signals on POR.
+                                                    /* Bits 26-31: Reserved */
+
+/* SRC General Purpose Register 1 (32-bit values, some have reserved bits)
+ * NOTE:  Ald GPR registers are used by the ROM code and should not be used by application
+ * software.
+ */
+
+#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_SRC_H */
+

arch/arm/src/imxrt/chip/imxrt_wdog.h

@@ -0,0 +1,142 @@
+/************************************************************************************
+ * arch/arm/src/imxrt/imxrt_wdog.h
+ *
+ *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ *   Author:  Janne Rosberg <janne@offcode.fi>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_WDOG_H
+#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_WDOG_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#include "chip/imxrt_memorymap.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Register offsets *****************************************************************/
+
+#define IMXRT_WDOG_WCR_OFFSET       0x0000  /* Watchdog control register */
+#define IMXRT_WDOG_WSR_OFFSET       0x0002  /* Watchdog service register */
+#define IMXRT_WDOG_WRSR_OFFSET      0x0004  /* Watchdog reset status */
+#define IMXRT_WDOG_WICR_OFFSET      0x0006  /* Watchdog interrupt control */
+#define IMXRT_WDOG_WMCR_OFFSET      0x0008  /* Watchdog misc control */
+
+#define IMXRT_RTWDOG_CS_OFFSET      0x0000  /* Watchdog control and status register */
+#define IMXRT_RTWDOG_CNT_OFFSET     0x0004  /* Watchdog counter register */
+#define IMXRT_RTWDOG_TOVAL_OFFSET   0x0008  /* Watchdog timeout value register */
+#define IMXRT_RTWDOG_WIN_OFFSET     0x000c  /* Watchdog window register */
+
+/* Register addresses ***************************************************************/
+
+#define IMXRT_WDOG1_WCR             (IMXRT_WDOG1_BASE + IMXRT_WDOG_WCR_OFFSET)
+#define IMXRT_WDOG1_WSR             (IMXRT_WDOG1_BASE + IMXRT_WDOG_WSR_OFFSET)
+#define IMXRT_WDOG1_WRSR            (IMXRT_WDOG1_BASE + IMXRT_WDOG_WRSR_OFFSET)
+#define IMXRT_WDOG1_WICR            (IMXRT_WDOG1_BASE + IMXRT_WDOG_WICR_OFFSET)
+#define IMXRT_WDOG1_WMCR            (IMXRT_WDOG1_BASE + IMXRT_WDOG_WMCR_OFFSET)
+
+#define IMXRT_WDOG2_WCR             (IMXRT_WDOG2_BASE + IMXRT_WDOG_WCR_OFFSET)
+#define IMXRT_WDOG2_WSR             (IMXRT_WDOG2_BASE + IMXRT_WDOG_WSR_OFFSET)
+#define IMXRT_WDOG2_WRSR            (IMXRT_WDOG2_BASE + IMXRT_WDOG_WRSR_OFFSET)
+#define IMXRT_WDOG2_WMCR            (IMXRT_WDOG2_BASE + IMXRT_WDOG_WMCR_OFFSET)
+
+#define IMXRT_RTWDOG_CS             (IMXRT_WDOG3_BASE + IMXRT_RTWDOG_CS_OFFSET)
+#define IMXRT_RTWDOG_CNT            (IMXRT_WDOG3_BASE + IMXRT_RTWDOG_CNT_OFFSET)
+#define IMXRT_RTWDOG_TOVAL          (IMXRT_WDOG3_BASE + IMXRT_RTWDOG_TOVAL_OFFSET)
+#define IMXRT_RTWDOG_WIN            (IMXRT_WDOG3_BASE + IMXRT_RTWDOG_WIN_OFFSET)
+
+/* Register bit definitions *********************************************************/
+
+/* Watchdog control and status register */
+
+#define WDOG_WCR_WDZST              (1 << 0)  /* Bit 0:  Watchdog Low Power */
+#define WDOG_WCR_WDBG               (1 << 1)  /* Bit 1:  Watchdog DEBUG Enable */
+#define WDOG_WCR_WDE                (1 << 2)  /* Bit 2:  Watchdog Enable */
+#define WDOG_WCR_WDT                (1 << 3)  /* Bit 3:  WDOG_B Time-out assertion */
+#define WDOG_WCR_SRS                (1 << 4)  /* Bit 4:  Software Reset Signal */
+#define WDOG_WCR_WDA                (1 << 5)  /* Bit 5:  WDOG_B assertion */
+#define WDOG_WCR_SRE                (1 << 6)  /* Bit 6:  Software reset extension */
+#define WDOG_WCR_WDW                (1 << 7)  /* Bit 7:  Watchdog Disable for Wait */
+
+#define WDOG_WCR_WT_SHIFT           (8)       /* Bits 8-15: Watchdog time-out value */
+#define WDOG_WCR_WT_MASK            (0xff << WDOG_WCR_WT_SHIFT)
+#  define WDOG_WCR_WT(n)            ((uint16_t)((n)) << WDOG_WCR_WT_SHIFT)
+
+/* Watchdog reset status */
+
+#define WDOG_WRSR_SFTW              (1 << 0)  /* Bit 0:  Software Reset */
+#define WDOG_WRSR_TOUT              (1 << 1)  /* Bit 1:  Timeout */
+                                              /* Bits 2-3: reserved */
+#define WDOG_WRSR_POR               (1 << 4)  /* Bit 4:  Power on reset */
+                                              /* Bits 5-15: Reserved */
+/* Watchdog interrupt control  */
+
+#define WDOG_WICR_WICT_SHIFT        (0)       /* Bits 0-7: Watchdog Interrupt Count Time-out */
+#define WDOG_WICR_WICT_MASK         (0xff << WDOG_WCR_WT_SHIFT)
+#  define WDOG_WICR_WICT(n)         ((uint16_t)((n)) << WDOG_WICR_WICT_SHIFT)
+                                              /* Bits 8-13: Reserved */
+#define WDOG_WICR_WTIS              (1 << 14) /* Bit 14: Watchdog Timer Interrupt Status */
+#define WDOG_WICR_WIE               (1 << 15) /* Bit 15: Watchdog Timer Interrupt enable */
+
+/* Watchdog misc control */
+
+#define WDOG_WMCR_PDE               (1 << 0)  /* Bit 0:  Power Down Enable */
+                                              /* Bits 1-15: Reserved */
+/* RT Watchdog Control and Status Register */
+
+#define RTWDOG_CS_STOP              (1 << 0)  /* Bit 0:  Stop enable */
+#define RTWDOG_CS_WAIT              (1 << 1)  /* Bit 1:  Wait enable */
+#define RTWDOG_CS_DBG               (1 << 2)  /* Bit 2:  Debug Enable */
+#define RTWDOG_CS_TST_SHIFT         (3)       /* Bits 3-4: Enables the fast test mode */
+#define RTWDOG_CS_TST_MASK          (0x03 << RTWDOG_CS_TST_SHIFT)
+#  define RTWDOG_CS_TST(n)          ((uint32_t)((n)) << RTWDOG_CS_TST_SHIFT)
+#define RTWDOG_CS_UPDATE            (1 << 5)  /* Bit 5:  Update */
+#define RTWDOG_CS_INT               (1 << 6)  /* Bit 6:  Interrupt */
+#define RTWDOG_CS_EN                (1 << 7)  /* Bit 7:  Enable */
+#define RTWDOG_CS_CLK_SHIFT         (8)       /* Bits 8-9: Clock */
+#define RTWDOG_CS_CLK_MASK          (0x03 << RTWDOG_CS_CLK_SHIFT)
+#  define RTWDOG_CS_CLK(n)          ((uint32_t)((n)) << RTWDOG_CS_CLK_SHIFT)
+#define RTWDOG_CS_RCS               (1 << 10) /* Bit 10: Reconfiguration Success */
+#define RTWDOG_CS_ULK               (1 << 11) /* Bit 11: Unlock status */
+#define RTWDOG_CS_PRES              (1 << 12) /* Bit 12: Watchdog prescaler */
+#define RTWDOG_CS_CMD32EN           (1 << 13) /* Bit 13: WDOG support for 32-bit */
+#define RTWDOG_CS_FLG               (1 << 14) /* Bit 14: Interrupt Flag */
+#define RTWDOG_CS_WIN               (1 << 15) /* Bit 15: Watchdog Window */
+
+#define RTWDOG_UPDATE_KEY           (0xd928c520)
+#define RTWDOG_REFRESH_KEY          (0xb480a602)
+
+#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_WDOG_H */

arch/arm/src/imxrt/imxrt_allocateheap.c

@@ -0,0 +1,357 @@
+/****************************************************************************
+ * arch/arm/src/imxrt/imxrt_allocateheap.c
+ *
+ *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <assert.h>
+#include <debug.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/board.h>
+#include <nuttx/kmalloc.h>
+#include <nuttx/userspace.h>
+
+#include <arch/imxrt/chip.h>
+
+#include "up_arch.h"
+#include "up_internal.h"
+
+#include "chip/imxrt_memorymap.h"
+#include "imxrt_mpuinit.h"
+
+#include <arch/board/board.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+/* Configuration ************************************************************/
+/* Terminology.  In the flat build (CONFIG_BUILD_FLAT=y), there is only a
+ * single heap access with the standard allocations (malloc/free).  This
+ * heap is referred to as the user heap.  In the protected build
+ * (CONFIG_BUILD_PROTECTED=y) where an MPU is used to protect a region of
+ * otherwise flat memory, there will be two allocators:  One that allocates
+ * protected (kernel) memory and one that allocates unprotected (user)
+ * memory.  These are referred to as the kernel and user heaps,
+ * respectively.
+ *
+ * The ARMv7 has no MPU but does have an MMU.  Without an MMU, it cannot
+ * support the kernel build (CONFIG_BUILD_KERNEL=y).  In that configuration,
+ * there would is one kernel heap but multiple user heaps:  One per task
+ * group.  However, in this case, we need only be concerned about
+ * initializing the single kernel heap here.
+ *
+ * Primary RAM:  The Linker script positions the system BLOB's .data and
+ * .bss in some RAM.  We refer to that RAM as the primary RAM.  It also
+ * holds the IDLE threads stack and any remaining portion of the primary
+ * RAM is automatically added to the heap.  The start and size of the
+ * primary RAM are provided by CONFIG_RAM_START and CONFIG_RAM_SIZE.  The
+ * linker provided address, ... .sbss, .ebss, .sdat, etc. ...  are expected
+ * to lie in the the region defined by those configuration settings.
+ *
+ * Other RAM regions must be selected use configuration options and the
+ * start and end of those RAM regions must also be provided in the
+ * configuration.  CONFIG_MM_REGIONS must also be set to determined the
+ * number of regions to be added to the heap.
+ *
+ * REVISIT:  The i.MX RT SEMC will support up to 8 512Mbit memory regions.
+ * So it is possible that there could be multiple external SDRAM or SRAM
+ * banks.  This logic assumes that there is at most one of each (or at least
+ * only one contiguous block of addresses for each).  This would need to
+ * be exceed considerably to support multiple SDRAM or SRAM memory regions.
+ */
+
+#define IMXRT_DTCM_BASE           0x20000000  /* 512KB DTCM */
+                               /* 0x20080000     512KB DTCM Reserved */
+                               /* 0x20100000     1MB Reserved */
+#define IMXRT_OCRAM_BASE          0x20200000  /* 512KB OCRAM */
+
+/* There there then several memory configurations with a one primary memory
+ * region and up to two additional memory regions which may be OCRAM,
+ * external SDRAM, or external SRAM.
+ */
+
+#undef IMXRT_OCRAM_ASSIGNED
+#undef IMXRT_SDRAM_ASSIGNED
+#undef IMXRT_SRAM_ASSIGNED
+
+/* REVISIT: Assume that if OCRAM is the primary RAM, then DTCM and ITCM are
+ * not being used.
+ */
+
+#if defined(CONFIG_IMXRT_OCRAM_PRIMARY)
+#  define PRIMARY_RAM_START    IMXRT_OCRAM_BASE         /* CONFIG_RAM_START */
+#  define PRIMARY_RAM_SIZE     IMXRT_OCRAM_SIZE         /* CONFIG_RAM_SIZE */
+#  define IMXRT_OCRAM_ASSIGNED 1
+#elif defined(CONFIG_IMXRT_SDRAM_PRIMARY)
+#  define PRIMARY_RAM_START    CONFIG_IMXRT_SDRAM_START /* CONFIG_RAM_START */
+#  define PRIMARY_RAM_SIZE     CONFIG_IMXRT_SDRAM_SIZE  /* CONFIG_RAM_SIZE */
+#  define IMXRT_SDRAM_ASSIGNED 1
+#elif defined(CONFIG_IMXRT_SRAM_PRIMARY)
+#  define PRIMARY_RAM_START    CONFIG_IMXRT_SRAM_START /* CONFIG_RAM_START */
+#  define PRIMARY_RAM_SIZE     CONFIG_IMXRT_SRAM_SIZE  /* CONFIG_RAM_SIZE */
+#  define IMXRT_SRAM_ASSIGNED  1
+#else
+#  error No primary RAM defined
+#endif
+
+#define PRIMARY_RAM_END        (PRIMARY_RAM_START + PRIMARY_RAM_SIZE)
+
+/* REVISIT:  I am not sure how this works.  But I am assuming that if DTCM
+ * is enabled, then ITCM is not and we can just use the DTCM base address to
+ * access OCRAM.
+ */
+
+#ifdef CONFIG_IMXRT_DTCM
+#  define IMXRT_OCRAM_START    IMXRT_DTCM_BASE
+#else
+#  define IMXRT_OCRAM_START    IMXRT_OCRAM_BASE
+#endif
+
+#if CONFIG_MM_REGIONS > 1
+/* Pick the first region to add to the heap could be any one of OCRAM,
+ * SDRAM, or SRAM depending upon which are enabled and which has not
+ * already been assigned as the primary RAM.
+ */
+
+#if defined(CONFIG_IMXRT_OCRAM_HEAP) && !defined(IMXRT_OCRAM_ASSIGNED)
+#  define REGION1_RAM_START    IMXRT_OCRAM_START
+#  define REGION1_RAM_SIZE     IMXRT_OCRAM_SIZE
+#  define IMXRT_OCRAM_ASSIGNED 1
+#elif defined(CONFIG_IMXRT_SDRAM_HEAP) && !defined(IMXRT_SDRAM_ASSIGNED)
+#  define REGION1_RAM_START    (CONFIG_IMXRT_SDRAM_START + CONFIG_IMXRT_SDRAM_HEAPOFFSET)
+#  define REGION1_RAM_SIZE     (CONFIG_IMXRT_SDRAM_SIZE  - CONFIG_IMXRT_SDRAM_HEAPOFFSET)
+#  define IMXRT_SDRAM_ASSIGNED 1
+#elif defined(CONFIG_IMXRT_SDRAM_HEAP) && !defined(IMXRT_SDRAM_ASSIGNED)
+#  define REGION1_RAM_START    (CONFIG_IMXRT_SRAM_START  + CONFIG_IMXRT_SRAM_HEAPOFFSET)
+#  define REGION1_RAM_SIZE     (CONFIG_IMXRT_SRAM_SIZE   - CONFIG_IMXRT_SRAM_HEAPOFFSET)
+#  define IMXRT_SDRAM_ASSIGNED 1
+#else
+#  warning CONFIG_MM_REGIONS > 1 but no available memory region
+#endif
+
+#define REGION1_RAM_END        (REGION1_RAM_START + REGION1_RAM_SIZE)
+#endif
+
+#if CONFIG_MM_REGIONS > 2
+/* Pick the first region to add to the heap could be any one of OCRAM,
+ * SDRAM, or SRAM depending upon which are enabled and which has not
+ * already been assigned as the primary RAM.
+ */
+
+#if defined(CONFIG_IMXRT_OCRAM_HEAP) && !defined(IMXRT_OCRAM_ASSIGNED)
+#  define REGION2_RAM_START    IMXRT_OCRAM_START
+#  define REGION2_RAM_SIZE     IMXRT_OCRAM_SIZE
+#  define IMXRT_OCRAM_ASSIGNED 1
+#elif defined(CONFIG_IMXRT_SDRAM_HEAP) && !defined(IMXRT_SDRAM_ASSIGNED)
+#  define REGION2_RAM_START    (CONFIG_IMXRT_SDRAM_START + CONFIG_IMXRT_SDRAM_HEAPOFFSET)
+#  define REGION2_RAM_SIZE     (CONFIG_IMXRT_SDRAM_SIZE  - CONFIG_IMXRT_SDRAM_HEAPOFFSET)
+#  define IMXRT_SDRAM_ASSIGNED 1
+#elif defined(CONFIG_IMXRT_SDRAM_HEAP) && !defined(IMXRT_SDRAM_ASSIGNED)
+#  define REGION2_RAM_START    (CONFIG_IMXRT_SRAM_START  + CONFIG_IMXRT_SRAM_HEAPOFFSET)
+#  define REGION2_RAM_SIZE     (CONFIG_IMXRT_SRAM_SIZE   - CONFIG_IMXRT_SRAM_HEAPOFFSET)
+#  define IMXRT_SDRAM_ASSIGNED 1
+#else
+#  warning CONFIG_MM_REGIONS > 2 but no available memory region
+#endif
+
+#define REGION2_RAM_END        (REGION2_RAM_START + REGION2_RAM_SIZE)
+#endif
+
+#if CONFIG_MM_REGIONS > 3
+#  warning CONFIG_MM_REGIONS > 3 but no available memory region
+#endif
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/* _sbss is the start of the BSS region (see the linker script) _ebss is the
+ * end of the BSS regions (see the linker script). The idle task stack starts
+ * at the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE.  The IDLE
+ * thread is the thread that the system boots on and, eventually, becomes the
+ * idle, do nothing task that runs only when there is nothing else to run.
+ * The heap continues from there until the configured end of memory.
+ * g_idle_topstack is the beginning of this heap region (not necessarily
+ * aligned).
+ */
+
+const uintptr_t g_idle_topstack = (uintptr_t)&_ebss + CONFIG_IDLETHREAD_STACKSIZE;
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_allocate_heap/up_allocate_kheap
+ *
+ * Description:
+ *   This function will be called to dynamically set aside the heap region.
+ *
+ *   - For the normal "flat" build, this function returns the size of the
+ *     single heap.
+ *   - For the protected build (CONFIG_BUILD_PROTECTED=y) with both kernel-
+ *     and user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function
+ *     provides the size of the unprotected, user-space heap.
+ *   - For the kernel build (CONFIG_BUILD_KERNEL=y), this function provides
+ *     the size of the protected, kernel-space heap.
+ *
+ *   If a protected kernel-space heap is provided, the kernel heap must be
+ *   allocated by an analogous up_allocate_kheap(). A custom version of this
+ *   file is needed if memory protection of the kernel heap is required.
+ *
+ *   The following memory map is assumed for the flat build:
+ *
+ *     .data region.  Size determined at link time.
+ *     .bss  region  Size determined at link time.
+ *     IDLE thread stack.  Size determined by CONFIG_IDLETHREAD_STACKSIZE.
+ *     Heap.  Extends to the end of SRAM.
+ *
+ *   The following memory map is assumed for the kernel build:
+ *
+ *     Kernel .data region.  Size determined at link time.
+ *     Kernel .bss  region  Size determined at link time.
+ *     Kernel IDLE thread stack.  Size determined by CONFIG_IDLETHREAD_STACKSIZE.
+ *     Padding for alignment
+ *     User .data region.  Size determined at link time.
+ *     User .bss region  Size determined at link time.
+ *     Kernel heap.  Size determined by CONFIG_MM_KERNEL_HEAPSIZE.
+ *     User heap.  Extends to the end of SRAM.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_BUILD_KERNEL
+void up_allocate_kheap(FAR void **heap_start, size_t *heap_size)
+#else
+void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
+#endif
+{
+#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
+  /* Get the unaligned size and position of the user-space heap.
+   * This heap begins after the user-space .bss section at an offset
+   * of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment).
+   */
+
+  uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + CONFIG_MM_KERNEL_HEAPSIZE;
+  size_t    usize = PRIMARY_RAM_END - ubase;
+
+  DEBUGASSERT(ubase < (uintptr_t)PRIMARY_RAM_END);
+
+  /* Return the user-space heap settings */
+
+  board_autoled_on(LED_HEAPALLOCATE);
+  *heap_start = (FAR void *)ubase;
+  *heap_size  = usize;
+#else
+
+  /* Return the heap settings */
+
+  board_autoled_on(LED_HEAPALLOCATE);
+  *heap_start = (FAR void *)g_idle_topstack;
+  *heap_size  = PRIMARY_RAM_END - g_idle_topstack;
+#endif
+}
+
+/****************************************************************************
+ * Name: up_allocate_kheap
+ *
+ * Description:
+ *   For the kernel build (CONFIG_BUILD_PROTECTED/KERNEL=y) with both kernel-
+ *   and user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function allocates
+ *   the kernel-space heap.  A custom version of this function is needed if
+ *   memory protection of the kernel heap is required.
+ *
+ ****************************************************************************/
+
+#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
+void up_allocate_kheap(FAR void **heap_start, size_t *heap_size)
+{
+  /* Get the unaligned size and position of the user-space heap.
+   * This heap begins after the user-space .bss section at an offset
+   * of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment).
+   */
+
+  uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + CONFIG_MM_KERNEL_HEAPSIZE;
+  DEBUGASSERT(ubase < (uintptr_t)PRIMARY_RAM_END);
+
+  /* Return the kernel heap settings (i.e., the part of the heap region
+   * that was not dedicated to the user heap).
+   */
+
+  *heap_start = (FAR void *)USERSPACE->us_bssend;
+  *heap_size  = ubase - (uintptr_t)USERSPACE->us_bssend;
+}
+#endif
+
+/****************************************************************************
+ * Name: up_addregion
+ *
+ * Description:
+ *   Memory may be added in non-contiguous chunks.  Additional chunks are
+ *   added by calling this function.
+ *
+ ****************************************************************************/
+
+#if CONFIG_MM_REGIONS > 1
+void up_addregion(void)
+{
+  /* Add region 1 to the user heap */
+
+  kumm_addregion((FAR void *)REGION1_RAM_START, REGION1_RAM_SIZE);
+
+#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
+  /* Allow user-mode access to region 1 */
+
+  imxrt_mpu_uheap((uintptr_t)REGION1_RAM_START, REGION1_RAM_SIZE);
+#endif
+
+#if CONFIG_MM_REGIONS > 2
+  /* Add region 2 to the user heap */
+
+  kumm_addregion((FAR void *)REGION2_RAM_START, REGION2_RAM_SIZE);
+
+#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
+  /* Allow user-mode access to region 2 */
+
+  imxrt_mpu_uheap((uintptr_t)REGION2_RAM_START, REGION2_RAM_SIZE);
+#endif
+#endif /* CONFIG_MM_REGIONS > 2 */
+}
+#endif /* CONFIG_MM_REGIONS > 1 */

arch/arm/src/imxrt/imxrt_clockconfig.c

@@ -0,0 +1,159 @@
+/****************************************************************************
+ * arch/arm/src/imxrt/imxrt_clockconfig.c
+ *
+ *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ *   Author:  Janne Rosberg <janne@offcode.fi>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "up_arch.h"
+#include <arch/board/board.h>
+#include "chip/imxrt_ccm.h"
+#include "chip/imxrt_dcdc.h"
+#include "imxrt_clockconfig.h"
+#include "chip/imxrt105x_memorymap.h"
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: imxrt_clockconfig
+ *
+ * Description:
+ *   Called to initialize the i.MXRT.  This does whatever setup is needed to
+ *   put the SoC in a usable state.  This includes the initialization of
+ *   clocking using the settings in board.h.
+ *
+ ****************************************************************************/
+
+void imxrt_clockconfig(void)
+{
+  /* Don't change the current basic clock configuration if we are running
+   * from SDRAM.  In this case, some bootloader logic has already configured
+   * clocking and SDRAM.  We are pretty much committed to using things the
+   * way that the bootloader has left them.
+   */
+
+#ifndef CONFIG_IMXRT_BOOT_SDRAM
+  uint32_t reg;
+
+  /* Set clock mux and dividers */
+
+  /* Set PERIPH_CLK2 MUX to OSC */
+
+  reg = getreg32(IMXRT_CCM_CBCMR);
+  reg &= ~CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
+  reg |= CCM_CBCMR_PERIPH_CLK2_SEL_OSC_CLK;
+  putreg32(reg, IMXRT_CCM_CBCMR);
+
+  /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
+
+  reg = getreg32(IMXRT_CCM_CBCDR);
+  reg |= CCM_CBCDR_SEMC_PERIPH_CLK_SEL;
+  putreg32(reg, IMXRT_CCM_CBCDR);
+
+  /* Wait handshake */
+
+  while ((getreg32(IMXRT_CCM_CDHIPR) & CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY) == 1)
+    {
+    }
+
+  /* Set Soc VDD */
+
+  reg = getreg32(IMXRT_DCDC_REG3);
+  reg &= ~(DCDC_REG3_TRG_MASK);
+  reg |= DCDC_REG3_TRG(IMXRT_VDD_SOC);
+  putreg32(reg, IMXRT_DCDC_REG3);
+
+  /* Init Arm PLL1 */
+
+  reg = CCM_ANALOG_PLL_ARM_DIV_SELECT(IMXRT_ARM_PLL_SELECT) | CCM_ANALOG_PLL_ARM_ENABLE;
+  putreg32(reg, IMXRT_CCM_ANALOG_PLL_ARM);
+  while ((getreg32(IMXRT_CCM_ANALOG_PLL_ARM) & CCM_ANALOG_PLL_ARM_LOCK) == 0)
+    {
+    }
+
+  /* Init Sys PLL2 */
+
+  reg = CCM_ANALOG_PLL_SYS_DIV_SELECT(IMXRT_SYS_PLL_SELECT) | CCM_ANALOG_PLL_SYS_ENABLE;
+  putreg32(reg, IMXRT_CCM_ANALOG_PLL_SYS);
+  while ((getreg32(IMXRT_CCM_ANALOG_PLL_SYS) & CCM_ANALOG_PLL_SYS_LOCK) == 0)
+    {
+    }
+
+  /* TODO: other pll configs */
+
+  /* Set Dividers */
+
+  putreg32(CCM_CACRR_ARM_PODF(IMXRT_ARM_CLOCK_DIVIDER), IMXRT_CCM_CACRR);
+  putreg32(CCM_CBCDR_AHB_PODF(IMXRT_AHB_CLOCK_DIVIDER), IMXRT_CCM_CBCDR);
+  putreg32(CCM_CBCDR_IPG_PODF(IMXRT_IPG_CLOCK_DIVIDER), IMXRT_CCM_CBCDR);
+
+  /* Set PRE_PERIPH_CLK to PLL1 */
+
+  reg = getreg32(IMXRT_CCM_CBCMR);
+  reg &= ~CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
+  reg |= CCM_CBCMR_PRE_PERIPH_CLK_SEL_PLL1;
+  putreg32(reg, IMXRT_CCM_CBCMR);
+
+  /* Set PERIPH_CLK MUX to PRE_PERIPH_CLK2 */
+
+  reg = getreg32(IMXRT_CCM_CBCDR);
+  reg &= ~CCM_CBCDR_SEMC_PERIPH_CLK_SEL;
+  putreg32(reg, IMXRT_CCM_CBCDR);
+
+  /* Wait handshake */
+
+  while ((getreg32(IMXRT_CCM_CDHIPR) & CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY) == 1)
+  {
+  }
+
+  /* Set UART source to PLL3 80M */
+
+  reg = getreg32(IMXRT_CCM_CSCDR1);
+  reg &= CCM_CSCDR1_UART_CLK_SEL;
+  reg |= CCM_CSCDR1_UART_CLK_SEL_PLL3_80;
+  putreg32(reg, IMXRT_CCM_CBCDR);
+
+  /* Set UART divider to 1 */
+
+  reg = getreg32(IMXRT_CCM_CSCDR1);
+  reg &= CCM_CSCDR1_UART_CLK_PODF_MASK;
+  reg |= CCM_CSCDR1_UART_CLK_PODF(0);
+  putreg32(reg, IMXRT_CCM_CBCDR);
+#endif
+}

arch/arm/src/imxrt/imxrt_clockconfig.h

@@ -0,0 +1,61 @@
+/****************************************************************************
+ * arch/arm/src/imrt/imxrt_clockconfig.h
+ *
+ *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ *   Author:  Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_IMRT_IMX_CLOCKCONFIG_H
+#define __ARCH_ARM_SRC_IMRT_IMX_CLOCKCONFIG_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: imxrt_clockconfig
+ *
+ * Description:
+ *   Called to initialize the i.MXRT.  This does whatever setup is needed to
+ *   put the SoC in a usable state.  This includes the initialization of
+ *   clocking using the settings in board.h.
+ *
+ ****************************************************************************/
+
+void imxrt_clockconfig(void);
+
+#endif /* __ARCH_ARM_SRC_IMRT_IMX_CLOCKCONFIG_H */

arch/arm/src/imxrt/imxrt_clrpend.c

@@ -0,0 +1,106 @@
+/****************************************************************************
+ * arch/arm/src/imxrt/imxrt_clrpend.c
+ *
+ *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <arch/irq.h>
+
+#include "nvic.h"
+#include "up_arch.h"
+
+#include "imxrt_irq.h"
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: imxrt_clrpend
+ *
+ * Description:
+ *   Clear a pending interrupt at the NVIC.  This does not seem to be required
+ *   for most interrupts.  Don't know why... but the LPC54xx Ethernet EMAC
+ *   interrupt definitely needs it!
+ *
+ *   This function is logically a part of imxrt_irq.c, but I will keep it in
+ *   a separate file so that it will not increase the footprint on LPC54xx
+ *   platforms that do not need this function.
+ *
+ ****************************************************************************/
+
+void imxrt_clrpend(int irq)
+{
+  /* Check for external interrupt */
+
+  if (irq >= IMXRT_IRQ_EXTINT)
+    {
+      if (irq < (IMXRT_IRQ_EXTINT + 32))
+        {
+          putreg32(1 << (irq - IMXRT_IRQ_EXTINT), NVIC_IRQ0_31_CLRPEND);
+        }
+#if IMXRT_IRQ_NEXTINT >= 64
+      else if (irq < (IMXRT_IRQ_EXTINT + 64))
+        {
+          putreg32(1 << (irq - IMXRT_IRQ_EXTINT - 32), NVIC_IRQ32_63_CLRPEND);
+        }
+#endif
+#if IMXRT_IRQ_NEXTINT >= 96
+      else if (irq < (IMXRT_IRQ_EXTINT + 96))
+        {
+          putreg32(1 << (irq - IMXRT_IRQ_EXTINT - 64), NVIC_IRQ64_95_CLRPEND);
+        }
+#endif
+#if IMXRT_IRQ_NEXTINT >= 128
+      else if (irq < (IMXRT_IRQ_EXTINT + 128))
+        {
+          putreg32(1 << (irq - IMXRT_IRQ_EXTINT - 96), NVIC_IRQ96_127_CLRPEND);
+        }
+#endif
+#if IMXRT_IRQ_NEXTINT >= 160
+      else if (irq < (IMXRT_IRQ_EXTINT + 160))
+        {
+          putreg32(1 << (irq - IMXRT_IRQ_EXTINT - 128), NVIC_IRQ128_159_CLRPEND);
+        }
+#endif
+      else
+        {
+          DEBUGPANIC();
+        }
+    }
+}

arch/arm/src/imxrt/imxrt_config.h

@@ -0,0 +1,206 @@
+/************************************************************************************
+ * arch/arm/src/imxrt/imxrt_config.h
+ *
+ *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_IMXRT_IMXRT_CONFIG_H
+#define __ARCH_ARM_SRC_IMXRT_IMXRT_CONFIG_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#include <arch/board/board.h>
+
+#include "chip.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Configuration *********************************************************************/
+
+#undef HAVE_LPUART1
+#undef HAVE_LPUART2
+#undef HAVE_LPUART3
+#undef HAVE_LPUART4
+#undef HAVE_LPUART5
+#undef HAVE_LPUART6
+#undef HAVE_LPUART7
+#undef HAVE_LPUART8
+
+#ifdef CONFIG_IMXRT_LPUART1
+#  define HAVE_LPUART1 1
+#endif
+#ifdef CONFIG_IMXRT_LPUART2
+#  define HAVE_LPUART2 1
+#endif
+#ifdef CONFIG_IMXRT_LPUART3
+#  define HAVE_LPUART3 1
+#endif
+#ifdef CONFIG_IMXRT_LPUART4
+#  define HAVE_LPUART4 1
+#endif
+#ifdef CONFIG_IMXRT_LPUART5
+#  define HAVE_LPUART5 1
+#endif
+#ifdef CONFIG_IMXRT_LPUART6
+#  define HAVE_LPUART6 1
+#endif
+#ifdef CONFIG_IMXRT_LPUART7
+#  define HAVE_LPUART7 1
+#endif
+#ifdef CONFIG_IMXRT_LPUART8
+#  define HAVE_LPUART8 1
+#endif
+
+/* Check if we have a LPUART device */
+
+#undef CONFIG_IMXRT_HAVE_LPUART
+#undef HAVE_LPUART_DEVICE
+
+#if defined(HAVE_LPUART1) || defined(HAVE_LPUART2) || defined(HAVE_LPUART3) || \
+    defined(HAVE_LPUART4) || defined(HAVE_LPUART5) || defined(HAVE_LPUART6) || \
+    defined(HAVE_LPUART7) || defined(HAVE_LPUART8)
+#  define HAVE_LPUART_DEVICE 1
+#endif
+
+/* Is there a serial console? There should be at most one defined.  It could be on
+ * any LPUARTn, n=1,2,3,4,5,6,7,8
+ */
+
+#undef HAVE_LPUART_CONSOLE
+
+#if defined(CONFIG_LPUART1_SERIAL_CONSOLE) && defined(HAVE_LPUART1)
+#  undef CONFIG_LPUART2_SERIAL_CONSOLE
+#  undef CONFIG_LPUART3_SERIAL_CONSOLE
+#  undef CONFIG_LPUART4_SERIAL_CONSOLE
+#  undef CONFIG_LPUART5_SERIAL_CONSOLE
+#  undef CONFIG_LPUART6_SERIAL_CONSOLE
+#  undef CONFIG_LPUART7_SERIAL_CONSOLE
+#  undef CONFIG_LPUART8_SERIAL_CONSOLE
+#  define HAVE_LPUART_CONSOLE 1
+#elif defined(CONFIG_LPUART2_SERIAL_CONSOLE) && defined(HAVE_LPUART2)
+#  undef CONFIG_LPUART1_SERIAL_CONSOLE
+#  undef CONFIG_LPUART3_SERIAL_CONSOLE
+#  undef CONFIG_LPUART4_SERIAL_CONSOLE
+#  undef CONFIG_LPUART5_SERIAL_CONSOLE
+#  undef CONFIG_LPUART6_SERIAL_CONSOLE
+#  undef CONFIG_LPUART7_SERIAL_CONSOLE
+#  undef CONFIG_LPUART8_SERIAL_CONSOLE
+#  define HAVE_LPUART_CONSOLE 1
+#elif defined(CONFIG_LPUART3_SERIAL_CONSOLE) && defined(HAVE_LPUART3)
+#  undef CONFIG_LPUART1_SERIAL_CONSOLE
+#  undef CONFIG_LPUART2_SERIAL_CONSOLE
+#  undef CONFIG_LPUART4_SERIAL_CONSOLE
+#  undef CONFIG_LPUART5_SERIAL_CONSOLE
+#  undef CONFIG_LPUART6_SERIAL_CONSOLE
+#  undef CONFIG_LPUART7_SERIAL_CONSOLE
+#  undef CONFIG_LPUART8_SERIAL_CONSOLE
+#  define HAVE_LPUART_CONSOLE 1
+#elif defined(CONFIG_LPUART4_SERIAL_CONSOLE) && defined(HAVE_LPUART4)
+#  undef CONFIG_LPUART1_SERIAL_CONSOLE
+#  undef CONFIG_LPUART2_SERIAL_CONSOLE
+#  undef CONFIG_LPUART3_SERIAL_CONSOLE
+#  undef CONFIG_LPUART5_SERIAL_CONSOLE
+#  undef CONFIG_LPUART6_SERIAL_CONSOLE
+#  undef CONFIG_LPUART7_SERIAL_CONSOLE
+#  undef CONFIG_LPUART8_SERIAL_CONSOLE
+#  define HAVE_LPUART_CONSOLE 1
+#elif defined(CONFIG_LPUART5_SERIAL_CONSOLE) && defined(HAVE_LPUART5)
+#  undef CONFIG_LPUART1_SERIAL_CONSOLE
+#  undef CONFIG_LPUART2_SERIAL_CONSOLE
+#  undef CONFIG_LPUART3_SERIAL_CONSOLE
+#  undef CONFIG_LPUART4_SERIAL_CONSOLE
+#  undef CONFIG_LPUART6_SERIAL_CONSOLE
+#  undef CONFIG_LPUART7_SERIAL_CONSOLE
+#  undef CONFIG_LPUART8_SERIAL_CONSOLE
+#  define HAVE_LPUART_CONSOLE 1
+#elif defined(CONFIG_LPUART6_SERIAL_CONSOLE) && defined(HAVE_LPUART6)
+#  undef CONFIG_LPUART1_SERIAL_CONSOLE
+#  undef CONFIG_LPUART2_SERIAL_CONSOLE
+#  undef CONFIG_LPUART3_SERIAL_CONSOLE
+#  undef CONFIG_LPUART4_SERIAL_CONSOLE
+#  undef CONFIG_LPUART5_SERIAL_CONSOLE
+#  undef CONFIG_LPUART7_SERIAL_CONSOLE
+#  undef CONFIG_LPUART8_SERIAL_CONSOLE
+#  define HAVE_LPUART_CONSOLE 1
+#elif defined(CONFIG_LPUART7_SERIAL_CONSOLE) && defined(HAVE_LPUART7)
+#  undef CONFIG_LPUART1_SERIAL_CONSOLE
+#  undef CONFIG_LPUART2_SERIAL_CONSOLE
+#  undef CONFIG_LPUART3_SERIAL_CONSOLE
+#  undef CONFIG_LPUART4_SERIAL_CONSOLE
+#  undef CONFIG_LPUART5_SERIAL_CONSOLE
+#  undef CONFIG_LPUART6_SERIAL_CONSOLE
+#  undef CONFIG_LPUART8_SERIAL_CONSOLE
+#  define HAVE_LPUART_CONSOLE 1
+#elif defined(CONFIG_LPUART8_SERIAL_CONSOLE) && defined(HAVE_LPUART8)
+#  undef CONFIG_LPUART1_SERIAL_CONSOLE
+#  undef CONFIG_LPUART2_SERIAL_CONSOLE
+#  undef CONFIG_LPUART3_SERIAL_CONSOLE
+#  undef CONFIG_LPUART4_SERIAL_CONSOLE
+#  undef CONFIG_LPUART5_SERIAL_CONSOLE
+#  undef CONFIG_LPUART6_SERIAL_CONSOLE
+#  undef CONFIG_LPUART7_SERIAL_CONSOLE
+#  define HAVE_LPUART_CONSOLE 1
+#else
+#  ifdef CONFIG_DEV_CONSOLE
+#    warning "No valid CONFIG_[LP]LPUART[n]_SERIAL_CONSOLE Setting"
+#  endif
+#  undef CONFIG_LPUART1_SERIAL_CONSOLE
+#  undef CONFIG_LPUART2_SERIAL_CONSOLE
+#  undef CONFIG_LPUART3_SERIAL_CONSOLE
+#  undef CONFIG_LPUART4_SERIAL_CONSOLE
+#  undef CONFIG_LPUART5_SERIAL_CONSOLE
+#  undef CONFIG_LPUART6_SERIAL_CONSOLE
+#  undef CONFIG_LPUART7_SERIAL_CONSOLE
+#  undef CONFIG_LPUART8_SERIAL_CONSOLE
+#endif
+
+/* Check LPUART flow control (Not yet supported) */
+
+# undef CONFIG_LPUART1_FLOWCONTROL
+# undef CONFIG_LPUART2_FLOWCONTROL
+# undef CONFIG_LPUART3_FLOWCONTROL
+# undef CONFIG_LPUART4_FLOWCONTROL
+# undef CONFIG_LPUART5_FLOWCONTROL
+# undef CONFIG_LPUART6_FLOWCONTROL
+# undef CONFIG_LPUART7_FLOWCONTROL
+# undef CONFIG_LPUART8_FLOWCONTROL
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_IMXRT_IMXRT_CONFIG_H */

arch/arm/src/imxrt/imxrt_gpio.h

@@ -0,0 +1,311 @@
+/************************************************************************************
+ * arch/arm/src/imxrt/imxrt_gpio.h
+ *
+ *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_IMXRT_IMXRT_GPIO_H
+#define __ARCH_ARM_SRC_IMXRT_IMXRT_GPIO_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "chip/imxrt_gpio.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+/* 32-bit Encoding:
+ *
+ *   ENCODING    IIXX XXXX XXXX XXXX  MMMM MMMM MMMM MMMM
+ *   GPIO INPUT  00.. ..EE .GGP PPPP  MMMM MMMM MMMM MMMM
+ *   GPIO OUTPUT 01V. .... .GGP PPPP  MMMM MMMM MMMM MMMM
+ *   PERIPHERAL  10AA A... IIII IIII  MMMM MMMM MMMM MMMM
+ */
+
+/* Input/Output Selection:
+ *
+ *   ENCODING    II.. .... .... ....  .... .... .... ....
+ */
+
+#define GPIO_MODE_SHIFT        (30)      /* Bits 30-31: Pin mode */
+#define GPIO_MODE_MASK         (3 << GPIO_MODE_SHIFT)
+#  define GPIO_INPUT           (0 << GPIO_MODE_SHIFT) /* GPIO input */
+#  define GPIO_OUTPUT          (1 << GPIO_MODE_SHIFT) /* GPIO output */
+#  define GPIO_PERIPH          (2 << GPIO_MODE_SHIFT) /* Peripheral */
+#  define GPIO_INTERRUPT       (3 << GPIO_MODE_SHIFT) /* Interrupt input */
+
+/* Initial Ouptut Value:
+ *
+ *   GPIO OUTPUT 01V. .... .... ....  .... .... .... ....
+ */
+
+#define GPIO_OUTPUT_ZERO       (0)       /* Bit 29: 0=Initial output is low */
+#define GPIO_OUTPUT_ONE        (1 << 29) /* Bit 29: 1=Initial output is high */
+
+/* GPIO Port Number
+ *
+ *   GPIO INPUT  00.. .... .GG. ....  .... .... .... ....
+ *   GPIO OUTPUT 01.. .... .GG. ....  .... .... .... ....
+ */
+
+#define GPIO_PORT_SHIFT        (21)      /* Bits 21-23: GPIO port index */
+#define GPIO_PORT_MASK         (3 << GPIO_PORT_SHIFT)
+#  define GPIO_PORT1           (0 << GPIO_PORT_SHIFT) /* GPIO1 */
+#  define GPIO_PORT2           (1 << GPIO_PORT_SHIFT) /* GPIO2 */
+#  define GPIO_PORT3           (2 << GPIO_PORT_SHIFT) /* GPIO3 */
+#  define GPIO_PORT4           (3 << GPIO_PORT_SHIFT) /* GPIO4 */
+
+/* GPIO Pin Number:
+ *
+ *   GPIO INPUT  00.. .... ...P PPPP  .... .... .... ....
+ *   GPIO OUTPUT 01.. .... ...P PPPP  .... .... .... ....
+ */
+
+#define GPIO_PIN_SHIFT         (16)      /* Bits 16-20: GPIO pin number */
+#define GPIO_PIN_MASK          (15 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN0            (0 << GPIO_PIN_SHIFT)  /* Pin  0 */
+#  define GPIO_PIN1            (1 << GPIO_PIN_SHIFT)  /* Pin  1 */
+#  define GPIO_PIN2            (2 << GPIO_PIN_SHIFT)  /* Pin  2 */
+#  define GPIO_PIN3            (3 << GPIO_PIN_SHIFT)  /* Pin  3 */
+#  define GPIO_PIN4            (4 << GPIO_PIN_SHIFT)  /* Pin  4 */
+#  define GPIO_PIN5            (5 << GPIO_PIN_SHIFT)  /* Pin  5 */
+#  define GPIO_PIN6            (6 << GPIO_PIN_SHIFT)  /* Pin  6 */
+#  define GPIO_PIN7            (7 << GPIO_PIN_SHIFT)  /* Pin  7 */
+#  define GPIO_PIN8            (8 << GPIO_PIN_SHIFT)  /* Pin  8 */
+#  define GPIO_PIN9            (9 << GPIO_PIN_SHIFT)  /* Pin  9 */
+#  define GPIO_PIN10           (10 << GPIO_PIN_SHIFT) /* Pin 10 */
+#  define GPIO_PIN11           (11 << GPIO_PIN_SHIFT) /* Pin 11 */
+#  define GPIO_PIN12           (12 << GPIO_PIN_SHIFT) /* Pin 12 */
+#  define GPIO_PIN13           (13 << GPIO_PIN_SHIFT) /* Pin 13 */
+#  define GPIO_PIN14           (14 << GPIO_PIN_SHIFT) /* Pin 14 */
+#  define GPIO_PIN15           (15 << GPIO_PIN_SHIFT) /* Pin 15 */
+#  define GPIO_PIN16           (16 << GPIO_PIN_SHIFT) /* Pin 16 */
+#  define GPIO_PIN17           (17 << GPIO_PIN_SHIFT) /* Pin 17 */
+#  define GPIO_PIN18           (18 << GPIO_PIN_SHIFT) /* Pin 18 */
+#  define GPIO_PIN19           (19 << GPIO_PIN_SHIFT) /* Pin 19 */
+#  define GPIO_PIN20           (20 << GPIO_PIN_SHIFT) /* Pin 20 */
+#  define GPIO_PIN21           (21 << GPIO_PIN_SHIFT) /* Pin 21 */
+#  define GPIO_PIN22           (22 << GPIO_PIN_SHIFT) /* Pin 22 */
+#  define GPIO_PIN23           (23 << GPIO_PIN_SHIFT) /* Pin 23 */
+#  define GPIO_PIN24           (24 << GPIO_PIN_SHIFT) /* Pin 24 */
+#  define GPIO_PIN25           (25 << GPIO_PIN_SHIFT) /* Pin 25 */
+#  define GPIO_PIN26           (26 << GPIO_PIN_SHIFT) /* Pin 26 */
+#  define GPIO_PIN27           (27 << GPIO_PIN_SHIFT) /* Pin 27 */
+#  define GPIO_PIN28           (28 << GPIO_PIN_SHIFT) /* Pin 28 */
+#  define GPIO_PIN29           (29 << GPIO_PIN_SHIFT) /* Pin 29 */
+#  define GPIO_PIN30           (30 << GPIO_PIN_SHIFT) /* Pin 30 */
+#  define GPIO_PIN31           (31 << GPIO_PIN_SHIFT) /* Pin 31 */
+
+/* Peripheral Alternate Function:
+ *
+ *   PERIPHERAL  10AA A... .... ....  MMMM MMMM MMMM MMMM
+ */
+
+#define GPIO_ALT_SHIFT         (27)      /* Bits 27-29: Peripheral alternate function */
+#define GPIO_ALT_MASK          (15 << GPIO_ALT_SHIFT)
+#  define GPIO_ALT0            (0 << GPIO_ALT_SHIFT)  /* Alternate function 1 */
+#  define GPIO_ALT1            (1 << GPIO_ALT_SHIFT)  /* Alternate function 2 */
+#  define GPIO_ALT2            (2 << GPIO_ALT_SHIFT)  /* Alternate function 3 */
+#  define GPIO_ALT3            (3 << GPIO_ALT_SHIFT)  /* Alternate function 4 */
+#  define GPIO_ALT4            (4 << GPIO_ALT_SHIFT)  /* Alternate function 5 */
+                                                      /* Alternate function 5 is GPIO */
+#  define GPIO_ALT6            (6 << GPIO_ALT_SHIFT)  /* Alternate function 1 */
+#  define GPIO_ALT7            (7 << GPIO_ALT_SHIFT)  /* Alternate function 1 */
+
+/* Interrupt edge/level configuration
+ *
+ *   GPIO INPUT  ... ..EE .... ....  .... .... .... ....
+ */
+
+#define GPIO_INTCFG_SHIFT      (24)      /* Bits 24-25: Interrupt edge/level configuration */
+#define GPIO_INTCFG_MASK       (3 << GPIO_INTCFG_SHIFT)
+#  define GPIO_INT_LOWLEVEL    (GPIO_ICR_LOWLEVEL << GPIO_INTCFG_SHIFT)
+#  define GPIO_INT_HIGHLEVEL   (GPIO_ICR_HIGHLEVEL << GPIO_INTCFG_SHIFT)
+#  define GPIO_INT_RISINGEDGE  (GPIO_ICR_RISINGEDGE << GPIO_INTCFG_SHIFT)
+#  define GPIO_INT_FALLINGEDGE (GPIO_ICR_FALLINGEDGE << GPIO_INTCFG_SHIFT)
+
+/* Pad Mux Register Index:
+ *
+ *   PERIPHERAL  .... .... IIII IIII  .... .... .... ....
+ */
+
+#define GPIO_PADMUX_SHIFT      (16)      /* Bits 16-23: Peripheral alternate function */
+#define GPIO_PADMUX_MASK       (0xff << GPIO_PADMUX_SHIFT)
+#  define GPIO_PADMUX(n)       ((uint32_t)(n) << GPIO_PADMUX_SHIFT)
+
+/* IOMUX Pin Configuration:
+ *
+ *   ENCODING    .... .... .... ....  MMMM MMMM MMMM MMMM
+ *
+ * See imxrt_iomuxc.h for detailed content.
+ */
+
+#define GPIO_IOMUX_SHIFT       (0)       /* Bits 9-15: IOMUX pin configuration */
+#define GPIO_IOMUX_MASK        (0xffff << GPIO_IOMUX_SHIFT)
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/* The smallest integer type that can hold the GPIO encoding */
+
+typedef uint32_t gpio_pinset_t;
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/************************************************************************************
+ * Public Function Prototypes
+ ************************************************************************************/
+
+/************************************************************************************
+ * Name: imxrt_gpioirq_initialize
+ *
+ * Description:
+ *   Initialize logic to support a second level of interrupt decoding for GPIO pins.
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_IMXRT_GPIO_IRQ
+void imxrt_gpioirq_initialize(void);
+#else
+#  define imxrt_gpioirq_initialize()
+#endif
+
+/************************************************************************************
+ * Name: imxrt_config_gpio
+ *
+ * Description:
+ *   Configure a GPIO pin based on bit-encoded description of the pin.
+ *
+ ************************************************************************************/
+
+int imxrt_config_gpio(gpio_pinset_t pinset);
+
+/************************************************************************************
+ * Name: imxrt_gpio_write
+ *
+ * Description:
+ *   Write one or zero to the selected GPIO pin
+ *
+ ************************************************************************************/
+
+void imxrt_gpio_write(gpio_pinset_t pinset, bool value);
+
+/************************************************************************************
+ * Name: imxrt_gpio_read
+ *
+ * Description:
+ *   Read one or zero from the selected GPIO pin
+ *
+ ************************************************************************************/
+
+bool imxrt_gpio_read(gpio_pinset_t pinset);
+
+/************************************************************************************
+ * Name: imxrt_gpioirq_configure
+ *
+ * Description:
+ *   Configure an interrupt for the specified GPIO pin.
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_IMXRT_GPIO_IRQ
+int imxrt_gpioirq_configure(gpio_pinset_t pinset);
+#else
+#  define imxrt_gpioirq_configure(pinset)
+#endif
+
+/************************************************************************************
+ * Name: imxrt_gpioirq_enable
+ *
+ * Description:
+ *   Enable the interrupt for specified GPIO IRQ
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_IMXRT_GPIO_IRQ
+int imxrt_gpioirq_enable(int irq);
+#else
+#  define imxrt_gpioirq_enable(irq)
+#endif
+
+/************************************************************************************
+ * Name: imxrt_gpioirq_disable
+ *
+ * Description:
+ *   Disable the interrupt for specified GPIO IRQ
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_IMXRT_GPIO_IRQ
+int imxrt_gpioirq_disable(int irq);
+#else
+#  define imxrt_gpioirq_disable(irq)
+#endif
+
+/************************************************************************************
+ * Function:  imxrt_dump_gpio
+ *
+ * Description:
+ *   Dump all GPIO registers associated with the base address of the provided pinset.
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_DEBUG_GPIO_INFO
+int imxrt_dump_gpio(uint32_t pinset, const char *msg);
+#else
+#  define imxrt_dumpgpio(p,m)
+#endif
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+#endif  /* __ARCH_ARM_SRC_IMXRT_IMXRT_GPIO_H */

arch/arm/src/imxrt/imxrt_idle.c

@@ -0,0 +1,188 @@
+/****************************************************************************
+ *  arch/arm/src/imxrt/imxrt_idle.c
+ *
+ *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ *   Author: Ivan Ucherdzhiev <ivanucherdjiev@gmail.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <arch/board/board.h>
+#include <nuttx/config.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/board.h>
+#include <nuttx/power/pm.h>
+
+#include <nuttx/irq.h>
+
+#include "chip.h"
+#include "up_internal.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Does the board support an IDLE LED to indicate that the board is in the
+ * IDLE state?
+ */
+
+#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE)
+#  define BEGIN_IDLE() board_autoled_on(LED_IDLE)
+#  define END_IDLE()   board_autoled_off(LED_IDLE)
+#else
+#  define BEGIN_IDLE()
+#  define END_IDLE()
+#endif
+
+#define PM_IDLE_DOMAIN 0 /* Revisit */
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_idlepm
+ *
+ * Description:
+ *   Perform IDLE state power management.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_PM
+static void up_idlepm(void)
+{
+  static enum pm_state_e oldstate = PM_NORMAL;
+  enum pm_state_e newstate;
+  irqstate_t flags;
+  int ret;
+
+  /* Decide, which power saving level can be obtained */
+
+  newstate = pm_checkstate(PM_IDLE_DOMAIN);
+
+  /* Check for state changes */
+
+  if (newstate != oldstate)
+    {
+      flags = enter_critical_section();
+
+      /* Perform board-specific, state-dependent logic here */
+
+      pwrinfo("newstate= %d oldstate=%d\n", newstate, oldstate);
+
+      /* Then force the global state change */
+
+      ret = pm_changestate(PM_IDLE_DOMAIN, newstate);
+      if (ret < 0)
+        {
+          /* The new state change failed, revert to the preceding state */
+
+          (void)pm_changestate(PM_IDLE_DOMAIN, oldstate);
+        }
+      else
+        {
+          /* Save the new state */
+
+          oldstate = newstate;
+        }
+
+      /* MCU-specific power management logic */
+
+      switch (newstate)
+        {
+        case PM_NORMAL:
+          break;
+
+        case PM_IDLE:
+          break;
+
+        case PM_STANDBY:
+          imxrt_pmstop(true);
+          break;
+
+        case PM_SLEEP:
+          (void)imxrt_pmstandby();
+          break;
+
+        default:
+          break;
+        }
+
+      leave_critical_section(flags);
+    }
+}
+#else
+#  define up_idlepm()
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_idle
+ *
+ * Description:
+ *   up_idle() is the logic that will be executed when their is no other
+ *   ready-to-run task.  This is processor idle time and will continue until
+ *   some interrupt occurs to cause a context switch from the idle task.
+ *
+ *   Processing in this state may be processor-specific. e.g., this is where
+ *   power management operations might be performed.
+ *
+ ****************************************************************************/
+
+void up_idle(void)
+{
+#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS)
+  /* If the system is idle and there are no timer interrupts, then process
+   * "fake" timer interrupts. Hopefully, something will wake up.
+   */
+
+  sched_process_timer();
+#else
+
+  /* Perform IDLE mode power management */
+
+  up_idlepm();
+
+#if 0 /* REVISIT */
+  /* Sleep until an interrupt occurs to save power. */
+
+  BEGIN_IDLE();
+  asm("WFI");
+  END_IDLE();
+#endif
+#endif
+}

arch/arm/src/imxrt/imxrt_iomuxc.c

@@ -0,0 +1,298 @@
+/****************************************************************************
+ * arch/arm/src/imxrt/imxrt_irq.c
+ *
+ *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <assert.h>
+#include <errno.h>
+
+#include "up_arch.h"
+#include "chip/imxrt_ccm.h"
+#include "imxrt_iomuxc.h"
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/* This table is indexed by the Pad Mux register index and provides the index
+ * to the corresponding Pad Control register.
+ *
+ * REVISIT:  This could be greatly simplified:  The Pad Control registers
+ * map 1-to-1 with the Pad Mux registers except for two regions where
+ * there are no corresponding Pad Mux registers.  The entire table could be
+ * replaced to two range checks and the appropriate offset added to the Pad
+ * Mux Register index.
+ */
+
+static const uint8_t g_mux2ctl_map[IMXRT_PADMUX_NREGISTERS] =
+{
+  /* The first mappings are simple 1-to-1 mappings.  This may be a little wasteful */
+
+  IMXRT_PADCTL_GPIO_EMC_00_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_01_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_02_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_03_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_04_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_05_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_06_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_07_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_08_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_09_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_10_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_11_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_12_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_13_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_14_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_15_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_16_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_17_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_18_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_19_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_20_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_21_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_22_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_23_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_24_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_25_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_26_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_27_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_28_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_29_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_30_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_31_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_32_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_33_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_34_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_35_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_36_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_37_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_38_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_39_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_40_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_41_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B0_00_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B0_01_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B0_02_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B0_03_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B0_04_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B0_05_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B0_06_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B0_07_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B0_08_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B0_09_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B0_10_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B0_11_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B0_12_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B0_13_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B0_14_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B0_15_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B1_00_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B1_01_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B1_02_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B1_03_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B1_04_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B1_05_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B1_06_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B1_07_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B1_08_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B1_09_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B1_10_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B1_11_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B1_12_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B1_13_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B1_14_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B1_15_INDEX,
+  IMXRT_PADCTL_GPIO_B0_00_INDEX,
+  IMXRT_PADCTL_GPIO_B0_01_INDEX,
+  IMXRT_PADCTL_GPIO_B0_02_INDEX,
+  IMXRT_PADCTL_GPIO_B0_03_INDEX,
+  IMXRT_PADCTL_GPIO_B0_04_INDEX,
+  IMXRT_PADCTL_GPIO_B0_05_INDEX,
+  IMXRT_PADCTL_GPIO_B0_06_INDEX,
+  IMXRT_PADCTL_GPIO_B0_07_INDEX,
+  IMXRT_PADCTL_GPIO_B0_08_INDEX,
+  IMXRT_PADCTL_GPIO_B0_09_INDEX,
+  IMXRT_PADCTL_GPIO_B0_10_INDEX,
+  IMXRT_PADCTL_GPIO_B0_11_INDEX,
+  IMXRT_PADCTL_GPIO_B0_12_INDEX,
+  IMXRT_PADCTL_GPIO_B0_13_INDEX,
+  IMXRT_PADCTL_GPIO_B0_14_INDEX,
+  IMXRT_PADCTL_GPIO_B0_15_INDEX,
+  IMXRT_PADCTL_GPIO_B1_00_INDEX,
+  IMXRT_PADCTL_GPIO_B1_01_INDEX,
+  IMXRT_PADCTL_GPIO_B1_02_INDEX,
+  IMXRT_PADCTL_GPIO_B1_03_INDEX,
+  IMXRT_PADCTL_GPIO_B1_04_INDEX,
+  IMXRT_PADCTL_GPIO_B1_05_INDEX,
+  IMXRT_PADCTL_GPIO_B1_06_INDEX,
+  IMXRT_PADCTL_GPIO_B1_07_INDEX,
+  IMXRT_PADCTL_GPIO_B1_08_INDEX,
+  IMXRT_PADCTL_GPIO_B1_09_INDEX,
+  IMXRT_PADCTL_GPIO_B1_10_INDEX,
+  IMXRT_PADCTL_GPIO_B1_11_INDEX,
+  IMXRT_PADCTL_GPIO_B1_12_INDEX,
+  IMXRT_PADCTL_GPIO_B1_13_INDEX,
+  IMXRT_PADCTL_GPIO_B1_14_INDEX,
+  IMXRT_PADCTL_GPIO_B1_15_INDEX,
+  IMXRT_PADCTL_GPIO_SD_B0_00_INDEX,
+  IMXRT_PADCTL_GPIO_SD_B0_01_INDEX,
+  IMXRT_PADCTL_GPIO_SD_B0_02_INDEX,
+  IMXRT_PADCTL_GPIO_SD_B0_03_INDEX,
+  IMXRT_PADCTL_GPIO_SD_B0_04_INDEX,
+  IMXRT_PADCTL_GPIO_SD_B0_05_INDEX,
+  IMXRT_PADCTL_GPIO_SD_B1_00_INDEX,
+  IMXRT_PADCTL_GPIO_SD_B1_01_INDEX,
+  IMXRT_PADCTL_GPIO_SD_B1_02_INDEX,
+  IMXRT_PADCTL_GPIO_SD_B1_03_INDEX,
+  IMXRT_PADCTL_GPIO_SD_B1_04_INDEX,
+  IMXRT_PADCTL_GPIO_SD_B1_05_INDEX,
+  IMXRT_PADCTL_GPIO_SD_B1_06_INDEX,
+  IMXRT_PADCTL_GPIO_SD_B1_07_INDEX,
+  IMXRT_PADCTL_GPIO_SD_B1_08_INDEX,
+  IMXRT_PADCTL_GPIO_SD_B1_09_INDEX,
+  IMXRT_PADCTL_GPIO_SD_B1_10_INDEX,
+  IMXRT_PADCTL_GPIO_SD_B1_11_INDEX
+};
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: imxrt_padmux_map
+ *
+ * Description:
+ *   This function map a Pad Mux register index to the corresponding Pad
+ *   Control register index.
+ *
+ ****************************************************************************/
+
+unsigned int imxrt_padmux_map(unsigned int padmux)
+{
+  DEBUGASSERT(padmux < IMX_PADMUX_NREGISTERS);
+  return (unsigned int)g_mux2ctl_map[padmux];
+}
+
+/****************************************************************************
+ * Name: imxrt_iomux_configure
+ *
+ * Description:
+ *   This function writes the encoded pad configuration to the Pad Control
+ *   register.
+ *
+ ****************************************************************************/
+
+int imxrt_iomux_configure(uintptr_t padctl, iomux_pinset_t ioset)
+{
+  uint32_t regval = 0;
+  uint32_t value;
+
+  /* Enable IOMUXC clock if it is not enabled*/
+
+  regval = getreg32(IMXRT_CCM_CCGR2);
+  if ((regval & CCM_CCGRX_CG2_MASK) == 0)
+    {
+      putreg32(CCM_CG_ALL << CCM_CCGRX_CG2_SHIFT, IMXRT_CCM_CCGR2);
+    }
+
+  /* Select CMOS input or Schmitt Trigger input */
+
+  if ((ioset & IOMUX_SCHMITT_TRIGGER) != 0)
+    {
+      regval |= PADCTL_SRE;
+    }
+
+  /* Select drive strength */
+
+  value = (ioset & IOMUX_DRIVE_MASK) >> IOMUX_DRIVE_SHIFT;
+  regval |= PADCTL_DSE(value);
+
+  /* Select spped */
+
+  value = (ioset & IOMUX_SPEED_MASK) >> IOMUX_SPEED_SHIFT;
+  regval |= PADCTL_SPEED(value);
+
+  /* Select CMOS output or Open Drain outpout */
+
+  if ((ioset & IOMUX_OPENDRAIN) != 0)
+    {
+      regval |= PADCTL_ODE;
+    }
+
+  /* Handle pull/keep selection */
+
+  switch (ioset & _IOMUX_PULLTYPE_MASK)
+    {
+      default:
+      case _IOMUX_PULL_NONE:
+        break;
+
+      case _IOMUX_PULL_KEEP:
+        {
+          regval |= PADCTL_PKE;
+        }
+        break;
+
+      case _IOMUX_PULL_ENABLE:
+        {
+          regval |= (PADCTL_PKE | PADCTL_PUE);
+
+          value   = (ioset & _IOMUX_PULLDESC_MASK) >> _IOMUX_PULLDESC_SHIFT;
+          regval |= PADCTL_PUS(value);
+        }
+        break;
+    }
+
+  /* Select slow/fast slew rate */
+
+  if ((ioset & IOMUX_SLEW_FAST) != 0)
+    {
+      regval |= PADCTL_HYS;
+    }
+
+  /* Write the result to the specified Pad Control register */
+
+  putreg32(regval, padctl);
+  return OK;
+}

arch/arm/src/imxrt/imxrt_iomuxc.h

@@ -0,0 +1,170 @@
+/****************************************************************************
+ * arch/arm/src/imxrt/imxrt_iomuxc.h
+ *
+ *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_IMXRT_IMX_IOMUXC_H
+#define __ARCH_ARM_SRC_IMXRT_IMX_IOMUXC_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+
+#include "chip/imxrt_iomuxc.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* 16-bit Encoding:
+ *
+ *   .... RRRR ODDD LSST
+ */
+
+/* Output Pull Up/Down:
+ *
+ *   .... RRRR .... ....
+ */
+
+#define _IOMUX_PULLTYPE_SHIFT   (8)        /* Bits 8-9: Pull up/down type */
+#define _IOMUX_PULLTYPE_MASK    (3 << _IOMUX_PULLTYPE_SHIFT)
+#  define _IOMUX_PULL_NONE      (0 << _IOMUX_PULLTYPE_SHIFT) /* Pull/keeper disabled */
+#  define _IOMUX_PULL_KEEP      (1 << _IOMUX_PULLTYPE_SHIFT) /* Output determined by keeper */
+#  define _IOMUX_PULL_ENABLE    (2 << _IOMUX_PULLTYPE_SHIFT) /* Output pulled up or down */
+
+#define _IOMUX_PULLDESC_SHIFT   (10)       /* Bits 10-11: Pull up/down description */
+#define _IOMUX_PULLDESC_MASK    (3 << _IOMUX_PULLDESC_SHIFT)
+#  define _IOMUX_PULL_UP_22K    (PULL_UP_22K    << _IOMUX_PULLDESC_SHIFT) /* Pull up with 22 KOhm resister */
+#  define _IOMUX_PULL_UP_47K    (PULL_UP_47K    << _IOMUX_PULLDESC_SHIFT) /* Pull up with 47 KOhm resister */
+#  define _IOMUX_PULL_UP_100K   (PULL_UP_100K   << _IOMUX_PULLDESC_SHIFT) /* Pull up with 100 KOhm resister */
+#  define _IOMUX_PULL_DOWN_100K (PULL_DOWN_100K << _IOMUX_PULLDESC_SHIFT) /* Pull down with 100 KOhm resister */
+
+#define IOMUX_PULL_SHIFT        (8)        /* Bits 8-11: Pull up/down selection */
+#define IOMUX_PULL_MASK         (15 << IOMUX_PULL_SHIFT)
+#  define IOMUX_PULL_NONE       _IOMUX_PULL_NONE
+#  define IOMUX_PULL_KEEP       _IOMUX_PULL_KEEP
+#  define IOMUX_PULL_UP_22K     (_IOMUX_PULL_ENABLE | _IOMUX_PULL_UP_22K)
+#  define IOMUX_PULL_UP_47K     (_IOMUX_PULL_ENABLE | _IOMUX_PULL_UP_47K)
+#  define IOMUX_PULL_UP_100K    (_IOMUX_PULL_ENABLE | _IOMUX_PULL_UP_100K)
+#  define IOMUX_PULL_DOWN_100K  (_IOMUX_PULL_ENABLE | _IOMUX_PULL_DOWN_100K)
+
+/* Open Drain Output:
+ *
+ *   .... .... O... ....
+ */
+
+#define IOMUX_CMOS_OUTPUT       (0)       /* Bit 7: 0=CMOS output */
+#define IOMUX_OPENDRAIN         (1 << 7)  /* Bit 7: 1=Enable open-drain output */
+
+/* Output Drive Strength:
+ *
+ *   .... .... .DDD ....
+ */
+
+#define IOMUX_DRIVE_SHIFT       (4)       /* Bits 4-6: Output Drive Strength */
+#define IOMUX_DRIVE_MASK        (7 << IOMUX_DRIVE_SHIFT)
+#  define IOMUX_DRIVE_HIZ       (DRIVE_HIZ    << IOMUX_DRIVE_SHIFT) /* HI-Z */
+#  define IOMUX_DRIVE_260OHM    (DRIVE_260OHM << IOMUX_DRIVE_SHIFT) /* 150 Ohm @3.3V, 260 Ohm @1.8V */
+#  define IOMUX_DRIVE_130OHM    (DRIVE_130OHM << IOMUX_DRIVE_SHIFT) /* 75 Ohm @3.3V, 130 Ohm @1.8V */
+#  define IOMUX_DRIVE_90OHM     (DRIVE_90OHM  << IOMUX_DRIVE_SHIFT) /* 50 Ohm @3.3V, 90 Ohm @1.8V */
+#  define IOMUX_DRIVE_60OHM     (DRIVE_60OHM  << IOMUX_DRIVE_SHIFT) /* 37 Ohm @3.3V, 60 Ohm @1.8V */
+#  define IOMUX_DRIVE_50OHM     (DRIVE_50OHM  << IOMUX_DRIVE_SHIFT) /* 30 Ohm @3.3V, 50 Ohm @1.8V */
+#  define IOMUX_DRIVE_40OHM     (DRIVE_40OHM  << IOMUX_DRIVE_SHIFT) /* 25 Ohm @3.3V, 40 Ohm @1.8V */
+#  define IOMUX_DRIVE_33OHM     (DRIVE_33OHM  << IOMUX_DRIVE_SHIFT) /* 20 Ohm @3.3V, 33 Ohm @1.8V */
+
+/* Output Slew Rate:
+ *
+ *   .... .... .... L...
+ */
+
+#define IOMUX_SLEW_SLOW         (0)       /* Bit 3: 0=Slow Slew Rate */
+#define IOMUX_SLEW_FAST         (1 << 3)  /* Bit 3: 1=Fast Slew Rate */
+
+/* Output Speed:
+ *
+ *   .... .... .... .SS.
+ */
+
+#define IOMUX_SPEED_SHIFT       (2)       /* Bits 2-3: Speed */
+#define IOMUX_SPEED_MASK        (3 << IOMUX_SPEED_SHIFT)
+#  define IOMUX_SPEED_LOW       (SPEED_LOW    << IOMUX_SPEED_SHIFT) /* Low frequency (50 MHz) */
+#  define IOMUX_SPEED_MEDIUM    (SPEED_MEDIUM << IOMUX_SPEED_SHIFT) /* Medium frequency (100, 150 MHz) */
+#  define IOMUX_SPEED_MAX       (SPEED_MAX    << IOMUX_SPEED_SHIFT) /* Maximum frequency (100, 150, 200 MHz) */
+
+/* Input Schmitt Trigger:
+ *
+ *   .... .... .... ...T
+ */
+
+#define IOMUX_CMOS_INPUT        (0)       /* Bit 0: 0=CMOS input */
+#define IOMUX_SCHMITT_TRIGGER   (1 << 0)  /* Bit 0: 1=Enable Schmitt trigger if input */
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+ /* The smallest integer type that can hold the IOMUX encoding */
+
+typedef uint16_t iomux_pinset_t;
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: imxrt_padmux_map
+ *
+ * Description:
+ *   This function map a Pad Mux register index to the corresponding Pad
+ *   Control register index.
+ *
+ ****************************************************************************/
+
+unsigned int imxrt_padmux_map(unsigned int padmux);
+
+/****************************************************************************
+ * Name: imxrt_iomux_configure
+ *
+ * Description:
+ *   This function writes the encoded pad configuration to the Pad Control
+ *   register.
+ *
+ ****************************************************************************/
+
+int imxrt_iomux_configure(uintptr_t padctl, iomux_pinset_t ioset);
+
+#endif /* __ARCH_ARM_SRC_IMXRT_IMX_IOMUXC_H */

arch/arm/src/imxrt/imxrt_irq.h

@@ -0,0 +1,60 @@
+/****************************************************************************
+ * arch/arm/src/imxrt/imxrt_irq.h
+ *
+ *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_IMXRT_IMXRT_IRQ_H
+#define __ARCH_ARM_SRC_IMXRT_IMXRT_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: imxrt_clrpend
+ *
+ * Description:
+ *   Clear a pending interrupt at the NVIC.  This does not seem to be
+ *   required for most interrupts.
+ *
+ ****************************************************************************/
+
+void imxrt_clrpend(int irq);
+
+#endif /* __ARCH_ARM_SRC_IMXRT_IMXRT_IRQ_H */

arch/arm/src/imxrt/imxrt_lowputc.h

@@ -0,0 +1,115 @@
+/****************************************************************************
+ * arch/arm/src/imxrt/imxrt_lowputc.h
+ *
+ *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ *   Author: Ivan Ucherdzhiev <ivanucherdjiev@gmail.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_IMXRT_LOWPUTC_H
+#define __ARCH_ARM_SRC_IMXRT_LOWPUTC_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/compiler.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "up_internal.h"
+#include "chip.h"
+#include "imxrt_config.h"
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+#ifdef HAVE_LPUART_DEVICE
+/* This structure describes the configuration of an UART */
+
+struct uart_config_s
+{
+  uint32_t baud;          /* Configured baud */
+  uint8_t  parity;        /* 0=none, 1=odd, 2=even */
+  uint8_t  bits;          /* Number of bits (5-9) */
+  bool     stopbits2;     /* true: Configure with 2 stop bits instead of 1 */
+};
+#endif
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: imxrt_lowsetup
+ *
+ * Description:
+ *   Called at the very beginning of _start.  Performs low level
+ *   initialization including setup of the console UART.  This UART done
+ *   early so that the serial console is available for debugging very early
+ *   in the boot sequence.
+ *
+ ****************************************************************************/
+
+void imxrt_lowsetup(void);
+
+/************************************************************************************
+ * Name: imxrt_lpuart_configure
+ *
+ * Description:
+ *   Configure a UART for non-interrupt driven operation
+ *
+ ************************************************************************************/
+
+#ifdef HAVE_LPUART_DEVICE
+int imxrt_lpuart_configure(uint32_t base, FAR const struct uart_config_s *config);
+#endif
+
+/************************************************************************************
+ * Name: imxrt_lowputc
+ *
+ * Description:
+ *   Output a byte with as few system dependencies as possible.  This will even work
+ *   BEFORE the console is initialized if we are booting from U-Boot (and the same
+ *   UART is used for the console, of course.)
+ *
+ ************************************************************************************/
+
+#if defined(HAVE_LPUART_DEVICE) && defined(CONFIG_DEBUG_FEATURES)
+void imxrt_lowputc(int ch);
+#else
+#  define imxrt_lowputc(ch)
+#endif
+
+#endif /* __ARCH_ARM_SRC_IMXRT_LOWPUTC_H */

arch/arm/src/imxrt/imxrt_mpuinit.c

@@ -0,0 +1,141 @@
+/****************************************************************************
+ * arch/arm/src/imxrt/imxrt_mpuinit.c
+ *
+ *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <assert.h>
+
+#include <nuttx/userspace.h>
+
+#include "mpu.h"
+#include "cache.h"
+#include "chip/imxrt_memorymap.h"
+
+#include "imxrt_mpuinit.h"
+
+#ifdef CONFIG_ARM_MPU
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#ifndef MAX
+#  define MAX(a,b) a > b ? a : b
+#endif
+
+#ifndef MIN
+#  define MIN(a,b) a < b ? a : b
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: imxrt_mpu_initialize
+ *
+ * Description:
+ *   Configure the MPU to permit user-space access to only restricted SAM3/4
+ *   resources.
+ *
+ ****************************************************************************/
+
+void imxrt_mpu_initialize(void)
+{
+#ifdef CONFIG_BUILD_PROTECTED
+  uintptr_t datastart;
+  uintptr_t dataend;
+#endif
+
+  /* Show MPU information */
+
+  mpu_showtype();
+
+#ifdef CONFIG_ARMV7M_DCACHE
+  /* Memory barrier */
+
+  ARM_DMB();
+
+#ifdef CONFIG_SAMV7_QSPI
+  /* Make QSPI memory region strongly ordered */
+
+  mpu_priv_stronglyordered(SAM_QSPIMEM_BASE, SAM_QSPIMEM_SIZE);
+
+#endif
+#endif
+
+#ifdef CONFIG_BUILD_PROTECTED
+  /* Configure user flash and SRAM space */
+
+  DEBUGASSERT(USERSPACE->us_textend >= USERSPACE->us_textstart);
+
+  mpu_user_flash(USERSPACE->us_textstart,
+                 USERSPACE->us_textend - USERSPACE->us_textstart);
+
+  datastart = MIN(USERSPACE->us_datastart, USERSPACE->us_bssstart);
+  dataend   = MAX(USERSPACE->us_dataend,   USERSPACE->us_bssend);
+
+  DEBUGASSERT(dataend >= datastart);
+
+  mpu_user_intsram(datastart, dataend - datastart);
+#endif
+
+  /* Then enable the MPU */
+
+  mpu_control(true, false, true);
+}
+
+/****************************************************************************
+ * Name: imxrt_mpu_uheap
+ *
+ * Description:
+ *  Map the user-heap region.
+ *
+ *  This logic may need an extension to handle external SDRAM).
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_BUILD_PROTECTED
+void imxrt_mpu_uheap(uintptr_t start, size_t size)
+{
+  mpu_user_intsram(start, size);
+}
+#endif
+
+#endif /* CONFIG_ARM_MPU */

arch/arm/src/imxrt/imxrt_mpuinit.h

@@ -0,0 +1,106 @@
+/****************************************************************************
+ * arch/arm/src/imxrt/imxrt_mpuinit.h
+ *
+ *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_IMXRT_IMXRT_MPUINIT_H
+#define __ARCH_ARM_SRC_IMXRT_IMXRT_MPUINIT_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+
+/****************************************************************************
+ * Inline Functions
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: imxrt_mpu_initialize
+ *
+ * Description:
+ *   Configure the MPU to permit user-space access to only unrestricted SAMV7
+ *   resources.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_ARM_MPU
+void imxrt_mpu_initialize(void);
+#else
+#  define imxrt_mpu_initialize()
+#endif
+
+/****************************************************************************
+ * Name: imxrt_mpu_uheap
+ *
+ * Description:
+ *  Map the user heap region.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_BUILD_PROTECTED
+void imxrt_mpu_uheap(uintptr_t start, size_t size);
+#else
+#  define imxrt_mpu_uheap(start,size)
+#endif
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_ARM_SRC_IMXRT_IMXRT_MPUINIT_H */

arch/arm/src/imxrt/imxrt_serial.h

@@ -0,0 +1,126 @@
+/****************************************************************************
+ * arch/arm/src/imxrt/imxrt_serial.h
+ *
+ *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ *   Author: Ivan Ucherdzhiev <ivanucherdjiev@gmail.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_IMXRT_IMX_SERIAL_H
+#define __ARCH_ARM_SRC_IMXRT_IMX_SERIAL_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "up_internal.h"
+#include "imxrt_config.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Inline Functions
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: imxrt_earlyserialinit
+ *
+ * Description:
+ *   Performs the low level UART initialization early in debug so that the
+ *   serial console will be available during bootup.  This must be called
+ *   before up_serialinit.
+ *
+ ****************************************************************************/
+
+#ifdef USE_EARLYSERIALINIT
+void imxrt_earlyserialinit(void);
+#endif
+
+/****************************************************************************
+ * Name: uart_earlyserialinit
+ *
+ * Description:
+ *   Performs the low level UART initialization early in debug so that the
+ *   serial console will be available during bootup.  This must be called
+ *   before up_serialinit.
+ *
+ ****************************************************************************/
+
+#if defined(USE_EARLYSERIALINIT) && defined(IMXRT_HAVE_LPUART)
+void uart_earlyserialinit(void);
+#endif
+
+/****************************************************************************
+ * Name: uart_serialinit
+ *
+ * Description:
+ *   Register the UART serial console and serial ports.  This assumes that
+ *   uart_earlyserialinit was called previously.
+ *
+ ****************************************************************************/
+
+#ifdef IMXRT_HAVE_LPUART
+void uart_serialinit(void);
+#endif
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_ARM_SRC_IMXRT_IMX_SERIAL_H */

arch/arm/src/imxrt/imxrt_start.c

@@ -0,0 +1,404 @@
+/****************************************************************************
+ * arch/arm/src/imxrt/imxrt_start.c
+ *
+ *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <assert.h>
+#include <debug.h>
+
+#include <nuttx/init.h>
+#include <arch/board/board.h>
+
+#include "up_arch.h"
+#include "up_internal.h"
+
+#include "cache.h"
+#ifdef CONFIG_ARCH_FPU
+#  include "nvic.h"
+#endif
+
+#include "imxrt_clockconfig.h"
+#include "imxrt_mpuinit.h"
+#include "imxrt_userspace.h"
+#include "imxrt_start.h"
+#include "imxrt_gpio.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Memory Map ***************************************************************/
+/* 0x2020:0000 - Start of on-chip RAM (OCRAM) and start of .data (_sdata)
+ *             - End of .data (_edata) and start of .bss (_sbss)
+ *             - End of .bss (_ebss) and bottom of idle stack
+ *             - _ebss + CONFIG_IDLETHREAD_STACKSIZE = end of idle stack,
+ *               start of heap. NOTE that the ARM uses a decrement before
+ *               store stack so that the correct initial value is the end of
+ *               the stack + 4;
+ * 0x2027:ffff - End of OCRAM and end of heap (assuming 512Kb OCRAM)
+ *
+ * NOTE:  This assumes that all internal RAM is configured for OCRAM (vs.
+ * ITCM or DTCM).  The RAM that holds .data and .bss is called the "Primary
+ * RAM".  Many other configurations are possible, including configurations
+ * where the primary ram is in external memory.  Those are not considered
+ * here.
+ */
+
+#define IDLE_STACK ((uintptr_t)&_ebss + CONFIG_IDLETHREAD_STACKSIZE - 4)
+#define HEAP_BASE  ((uintptr_t)&_ebss + CONFIG_IDLETHREAD_STACKSIZE)
+
+/****************************************************************************
+ * Private Function prototypes
+ ****************************************************************************/
+
+#ifdef CONFIG_ARCH_FPU
+static inline void imxrt_fpuconfig(void);
+#endif
+#ifdef CONFIG_STACK_COLORATION
+static void go_os_start(void *pv, unsigned int nbytes)
+  __attribute__ ((naked, no_instrument_function, noreturn));
+#endif
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+#ifdef CONFIG_ARMV7M_STACKCHECK
+/* we need to get r10 set before we can allow instrumentation calls */
+
+void __start(void) __attribute__ ((no_instrument_function));
+#endif
+
+/****************************************************************************
+ * Name: imxrt_fpuconfig
+ *
+ * Description:
+ *   Configure the FPU.  Relative bit settings:
+ *
+ *     CPACR:  Enables access to CP10 and CP11
+ *     CONTROL.FPCA: Determines whether the FP extension is active in the
+ *       current context:
+ *     FPCCR.ASPEN:  Enables automatic FP state preservation, then the
+ *       processor sets this bit to 1 on successful completion of any FP
+ *       instruction.
+ *     FPCCR.LSPEN:  Enables lazy context save of FP state. When this is
+ *       done, the processor reserves space on the stack for the FP state,
+ *       but does not save that state information to the stack.
+ *
+ *  Software must not change the value of the ASPEN bit or LSPEN bit while
+ *  either:
+ *
+ *   - the CPACR permits access to CP10 and CP11, that give access to the FP
+ *     extension, or
+ *   - the CONTROL.FPCA bit is set to 1
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_ARCH_FPU
+#if defined(CONFIG_ARMV7M_CMNVECTOR) && !defined(CONFIG_ARMV7M_LAZYFPU)
+
+static inline void imxrt_fpuconfig(void)
+{
+  uint32_t regval;
+
+  /* Set CONTROL.FPCA so that we always get the extended context frame
+   * with the volatile FP registers stacked above the basic context.
+   */
+
+  regval = getcontrol();
+  regval |= (1 << 2);
+  setcontrol(regval);
+
+  /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
+   * with the lazy FP context save behavior.  Clear FPCCR.ASPEN since we
+   * are going to turn on CONTROL.FPCA for all contexts.
+   */
+
+  regval = getreg32(NVIC_FPCCR);
+  regval &= ~((1 << 31) | (1 << 30));
+  putreg32(regval, NVIC_FPCCR);
+
+  /* Enable full access to CP10 and CP11 */
+
+  regval = getreg32(NVIC_CPACR);
+  regval |= ((3 << (2*10)) | (3 << (2*11)));
+  putreg32(regval, NVIC_CPACR);
+}
+
+#else
+
+static inline void imxrt_fpuconfig(void)
+{
+  uint32_t regval;
+
+  /* Clear CONTROL.FPCA so that we do not get the extended context frame
+   * with the volatile FP registers stacked in the saved context.
+   */
+
+  regval = getcontrol();
+  regval &= ~(1 << 2);
+  setcontrol(regval);
+
+  /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
+   * with the lazy FP context save behavior.  Clear FPCCR.ASPEN since we
+   * are going to keep CONTROL.FPCA off for all contexts.
+   */
+
+  regval = getreg32(NVIC_FPCCR);
+  regval &= ~((1 << 31) | (1 << 30));
+  putreg32(regval, NVIC_FPCCR);
+
+  /* Enable full access to CP10 and CP11 */
+
+  regval = getreg32(NVIC_CPACR);
+  regval |= ((3 << (2*10)) | (3 << (2*11)));
+  putreg32(regval, NVIC_CPACR);
+}
+
+#endif
+
+#else
+#  define imxrt_fpuconfig()
+#endif
+
+/****************************************************************************
+ * Name: imxrt_tcmenable
+ *
+ * Description:
+ *   Enable/disable tightly coupled memories.  Size of tightly coupled
+ *   memory regions is controlled by GPNVM Bits 7-8.
+ *
+ ****************************************************************************/
+
+static inline void imxrt_tcmenable(void)
+{
+  uint32_t regval;
+
+  ARM_DSB();
+  ARM_ISB();
+
+  /* Enabled/disabled ITCM */
+
+#ifdef CONFIG_ARMV7M_ITCM
+  regval  = NVIC_TCMCR_EN | NVIC_TCMCR_RMW | NVIC_TCMCR_RETEN;
+#else
+  regval  = getreg32(NVIC_ITCMCR);
+  regval &= ~NVIC_TCMCR_EN;
+#endif
+  putreg32(regval, NVIC_ITCMCR);
+
+  /* Enabled/disabled DTCM */
+
+#ifdef CONFIG_ARMV7M_DTCM
+  regval  = NVIC_TCMCR_EN | NVIC_TCMCR_RMW | NVIC_TCMCR_RETEN;
+#else
+  regval  = getreg32(NVIC_DTCMCR);
+  regval &= ~NVIC_TCMCR_EN;
+#endif
+  putreg32(regval, NVIC_DTCMCR);
+
+  ARM_DSB();
+  ARM_ISB();
+
+#ifdef CONFIG_ARMV7M_ITCM
+  /* Copy TCM code from flash to ITCM */
+
+#warning Missing logic
+#endif
+}
+
+/****************************************************************************
+ * Name: go_os_start
+ *
+ * Description:
+ *   Set the IDLE stack to the
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_STACK_COLORATION
+static void go_os_start(void *pv, unsigned int nbytes)
+{
+  /* Set the IDLE stack to the stack coloration value then jump to
+   * os_start().  We take extreme care here because were currently
+   * executing on this stack.
+   *
+   * We want to avoid sneak stack access generated by the compiler.
+   */
+
+  __asm__ __volatile__
+  (
+    "\tmovs r1, r1, lsr #2\n"   /* R1 = nwords = nbytes >> 2 */
+    "\tbeq  2f\n"               /* (should not happen) */
+
+    "\tbic  r0, r0, #3\n"       /* R0 = Aligned stackptr */
+    "\tmovw r2, #0xbeef\n"      /* R2 = STACK_COLOR = 0xdeadbeef */
+    "\tmovt r2, #0xdead\n"
+
+    "1:\n"                      /* Top of the loop */
+    "\tsub  r1, r1, #1\n"       /* R1 nwords-- */
+    "\tcmp  r1, #0\n"           /* Check (nwords == 0) */
+    "\tstr  r2, [r0], #4\n"     /* Save stack color word, increment stackptr */
+    "\tbne  1b\n"               /* Bottom of the loop */
+
+    "2:\n"
+    "\tmov  r14, #0\n"          /* LR = return address (none) */
+    "\tb    os_start\n"         /* Branch to os_start */
+  );
+}
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: _start
+ *
+ * Description:
+ *   This is the reset entry point.
+ *
+ ****************************************************************************/
+
+void __start(void)
+{
+  const uint32_t *src;
+  uint32_t *dest;
+
+#ifdef CONFIG_ARMV7M_STACKCHECK
+  /* Set the stack limit before we attempt to call any functions */
+
+  __asm__ volatile ("sub r10, sp, %0" : : "r" (CONFIG_IDLETHREAD_STACKSIZE - 64) : );
+#endif
+
+  /* Clear .bss.  We'll do this inline (vs. calling memset) just to be
+   * certain that there are no issues with the state of global variables.
+   */
+
+  for (dest = &_sbss; dest < &_ebss; )
+    {
+      *dest++ = 0;
+    }
+
+  /* Move the initialized data section from his temporary holding spot in
+   * FLASH into the correct place in OCRAM.  The correct place in OCRAM is
+   * give by _sdata and _edata.  The temporary location is in FLASH at the
+   * end of all of the other read-only data (.text, .rodata) at _eronly.
+   */
+
+  for (src = &_eronly, dest = &_sdata; dest < &_edata; )
+    {
+      *dest++ = *src++;
+    }
+
+  /* Copy any necessary code sections from FLASH to RAM.  The correct
+   * destination in OCRAM is given by _sramfuncs and _eramfuncs.  The
+   * temporary location is in flash after the data initialization code
+   * at _framfuncs.  This should be done before imxrt_clockconfig() is
+   * called (in case it has some dependency on initialized C variables).
+   */
+
+#ifdef CONFIG_ARCH_RAMFUNCS
+  for (src = &_framfuncs, dest = &_sramfuncs; dest < &_eramfuncs; )
+    {
+      *dest++ = *src++;
+    }
+#endif
+
+  /* Configure the UART so that we can get debug output as soon as possible */
+
+  imxrt_clockconfig();
+  imxrt_fpuconfig();
+  imxrt_lowsetup();
+
+  /* Enable/disable tightly coupled memories */
+
+  imxrt_tcmenable();
+
+  /* Initialize onboard resources */
+
+  imxrt_boardinitialize();
+
+#ifdef CONFIG_ARM_MPU
+  /* For the case of the separate user-/kernel-space build, perform whatever
+   * platform specific initialization of the user memory is required.
+   * Normally this just means initializing the user space .data and .bss
+   * segments.
+   */
+
+#ifdef CONFIG_BUILD_PROTECTED
+  imxrt_userspace();
+#endif
+
+  /* Configure the MPU to permit user-space access to its FLASH and RAM (for
+   * CONFIG_BUILD_PROTECTED) or to manage cache properties in external
+   * memory regions.
+   */
+
+  imxrt_mpu_initialize();
+#endif
+
+  /* Enable I- and D-Caches */
+
+  arch_dcache_writethrough();
+  arch_enable_icache();
+  arch_enable_dcache();
+
+  /* Perform early serial initialization */
+
+#ifdef USE_EARLYSERIALINIT
+  up_earlyserialinit();
+#endif
+
+  /* Then start NuttX */
+
+#ifdef CONFIG_STACK_COLORATION
+  /* Set the IDLE stack to the coloration value and jump into os_start() */
+
+  go_os_start((FAR void *)&_ebss, CONFIG_IDLETHREAD_STACKSIZE);
+#else
+  /* Call os_start() */
+
+  os_start();
+
+  /* Shouldn't get here */
+
+  for (; ; );
+#endif
+}

arch/arm/src/imxrt/imxrt_start.h

@@ -0,0 +1,126 @@
+/************************************************************************************
+ * arch/arm/src/imxrt/imxrt_start.h
+ *
+ *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_IMXRT_IMXRT_START_H
+#define __ARCH_ARM_SRC_IMXRT_IMXRT_START_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/compiler.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "up_internal.h"
+#include "chip.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Inline Functions
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/* g_idle_topstack: _sbss is the start of the BSS region as defined by the linker
+ * script. _ebss lies at the end of the BSS region. The idle task stack starts at
+ * the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE.  The IDLE thread is
+ * the thread that the system boots on and, eventually, becomes the IDLE, do
+ * nothing task that runs only when there is nothing else to run.  The heap
+ * continues from there until the end of memory.  g_idle_topstack is a read-only
+ * variable the provides this computed address.
+ */
+
+EXTERN const uintptr_t g_idle_topstack;
+
+/************************************************************************************
+ * Public Function Prototypes
+ ************************************************************************************/
+
+/************************************************************************************
+ * Name: imxrt_lowsetup
+ *
+ * Description:
+ *   Called at the very beginning of _start.  Performs low level initialization
+ *   including setup of the console UART.  This UART done early so that the serial
+ *   console is available for debugging very early in the boot sequence.
+ *
+ ************************************************************************************/
+
+void imxrt_lowsetup(void);
+
+/************************************************************************************
+ * Name: imxrt_boardinitialize
+ *
+ * Description:
+ *   All SAMV7 architectures must provide the following entry point.  This entry
+ *   point is called early in the initialization -- after clocking and memory have
+ *   been configured but before caches have been enabled and before any devices have
+ *   been initialized.
+ *
+ ************************************************************************************/
+
+void imxrt_boardinitialize(void);
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_ARM_SRC_IMXRT_IMXRT_START_H */

arch/arm/src/imxrt/imxrt_timerisr.c

@@ -0,0 +1,139 @@
+/****************************************************************************
+ * arch/arm/src/imxrt/imxrt_timerisr.c
+ *
+ *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <time.h>
+#include <debug.h>
+#include <nuttx/arch.h>
+#include <arch/board/board.h>
+
+#include "nvic.h"
+#include "clock/clock.h"
+#include "up_internal.h"
+#include "up_arch.h"
+
+#include "chip.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#warning REVISIT these clock settings
+
+/* Select MCU-specific settings
+ *
+ * The SysTick timer is driven by the output of the Main Clock (main_clk). */
+
+#define IMXRT_SYSTICK_CLOCK  BOARD_CPU_FREQUENCY
+
+/* The desired timer interrupt frequency is provided by the definition
+ * CLK_TCK (see include/time.h).  CLK_TCK defines the desired number of
+ * system clock ticks per second.  That value is a user configurable setting
+ * that defaults to 100 (100 ticks per second = 10 MS interval).
+ */
+
+#define SYSTICK_RELOAD ((IMXRT_SYSTICK_CLOCK / CLK_TCK) - 1)
+
+/* The size of the reload field is 24 bits.  Verify that the reload value
+ * will fit in the reload register.
+ */
+
+#if SYSTICK_RELOAD > 0x00ffffff
+#  error SYSTICK_RELOAD exceeds the range of the RELOAD register
+#endif
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Function:  imxrt_timerisr
+ *
+ * Description:
+ *   The timer ISR will perform a variety of services for various portions
+ *   of the systems.
+ *
+ ****************************************************************************/
+
+static int imxrt_timerisr(int irq, uint32_t *regs, void *arg)
+{
+  /* Process timer interrupt */
+
+  sched_process_timer();
+  return 0;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Function:  arm_timer_initialize
+ *
+ * Description:
+ *   This function is called during start-up to initialize the timer
+ *   interrupt.
+ *
+ ****************************************************************************/
+
+void arm_timer_initialize(void)
+{
+  uint32_t regval;
+
+  /* Configure SysTick to interrupt at the requested rate */
+
+  putreg32(SYSTICK_RELOAD, NVIC_SYSTICK_RELOAD);
+  putreg32(0, NVIC_SYSTICK_CURRENT);
+
+  /* Attach the timer interrupt vector */
+
+  (void)irq_attach(IMXRT_IRQ_SYSTICK, (xcpt_t)imxrt_timerisr, NULL);
+
+  /* Enable SysTick interrupts */
+
+  regval = (NVIC_SYSTICK_CTRL_CLKSOURCE | NVIC_SYSTICK_CTRL_TICKINT |
+            NVIC_SYSTICK_CTRL_ENABLE);
+  putreg32(regval, NVIC_SYSTICK_CTRL);
+
+  /* And enable the timer interrupt */
+
+  up_enable_irq(IMXRT_IRQ_SYSTICK);
+}

arch/arm/src/imxrt/imxrt_userspace.c

@@ -0,0 +1,105 @@
+/****************************************************************************
+ * arch/arm/src/imxrt/imxrt_userspace.c
+ *
+ *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <assert.h>
+
+#include <nuttx/userspace.h>
+
+#include "imxrt_mpuinit.h"
+#include "imxrt_userspace.h"
+
+#ifdef CONFIG_BUILD_PROTECTED
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: imxrt_userspace
+ *
+ * Description:
+ *   For the case of the separate user-/kernel-space build, perform whatever
+ *   platform specific initialization of the user memory is required.
+ *   Normally this just means initializing the user space .data and .bss
+ *   segments.
+ *
+ * Assumptions:
+ *   The D-Cache has not yet been enabled.
+ *
+ ****************************************************************************/
+
+void imxrt_userspace(void)
+{
+  uint8_t *src;
+  uint8_t *dest;
+  uint8_t *end;
+
+  /* Clear all of user-space .bss */
+
+  DEBUGASSERT(USERSPACE->us_bssstart != 0 && USERSPACE->us_bssend != 0 &&
+              USERSPACE->us_bssstart <= USERSPACE->us_bssend);
+
+  dest = (uint8_t *)USERSPACE->us_bssstart;
+  end  = (uint8_t *)USERSPACE->us_bssend;
+
+  while (dest != end)
+    {
+      *dest++ = 0;
+    }
+
+  /* Initialize all of user-space .data */
+
+  DEBUGASSERT(USERSPACE->us_datasource != 0 &&
+              USERSPACE->us_datastart != 0 && USERSPACE->us_dataend != 0 &&
+              USERSPACE->us_datastart <= USERSPACE->us_dataend);
+
+  src  = (uint8_t *)USERSPACE->us_datasource;
+  dest = (uint8_t *)USERSPACE->us_datastart;
+  end  = (uint8_t *)USERSPACE->us_dataend;
+
+  while (dest != end)
+    {
+      *dest++ = *src++;
+    }
+}
+
+#endif /* CONFIG_BUILD_PROTECTED */

arch/arm/src/imxrt/imxrt_userspace.h

@@ -0,0 +1,93 @@
+/************************************************************************************
+ * arch/arm/src/imxrt/imxrt_userspace.h
+ *
+ *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_IMXRT_IMXRT_USERSPACE_H
+#define __ARCH_ARM_SRC_IMXRT_IMXRT_USERSPACE_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/compiler.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "up_internal.h"
+#include "chip.h"
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/************************************************************************************
+ * Public Function Prototypes
+ ************************************************************************************/
+
+/****************************************************************************
+ * Name: imxrt_userspace
+ *
+ * Description:
+ *   For the case of the separate user-/kernel-space build, perform whatever
+ *   platform specific initialization of the user memory is required.
+ *   Normally this just means initializing the user space .data and .bss
+ *   segments.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_BUILD_PROTECTED
+void imxrt_userspace(void);
+#endif
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_ARM_SRC_IMXRT_IMXRT_USERSPACE_H */

arch/arm/src/imxrt/imxrt_wdog.c

@@ -0,0 +1,95 @@
+/****************************************************************************
+ * arch/arm/src/imxrt/imxrt_wdog.c
+ *
+ *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ *   Author:  Janne Rosberg <janne@offcode.fi>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <fixedmath.h>
+#include <assert.h>
+
+#include "up_arch.h"
+
+#include "chip/imxrt_wdog.h"
+#include "imxrt_config.h"
+#include <arch/board/board.h> /* Include last:  has dependencies */
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+/* Configuration ************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: imxrt_wdog_disable
+ *
+ * Description:
+ *   Disables all watchdogs
+ *
+ ****************************************************************************/
+
+void imxrt_wdog_disable_all(void)
+{
+  uint32_t reg;
+
+  reg = getreg32(IMXRT_WDOG1_WCR);
+  if (reg & WDOG_WCR_WDE)
+    {
+      reg &= ~WDOG_WCR_WDE;
+      putreg32(reg, IMXRT_WDOG1_WCR);
+    }
+
+  reg = getreg32(IMXRT_WDOG2_WCR);
+  if (reg & WDOG_WCR_WDE)
+  {
+    reg &= ~WDOG_WCR_WDE;
+    putreg32(reg, IMXRT_WDOG2_WCR);
+  }
+
+  putreg32(RTWDOG_UPDATE_KEY, IMXRT_RTWDOG_CNT);
+  putreg32(0xFFFF, IMXRT_RTWDOG_TOVAL);
+  modifyreg32(IMXRT_RTWDOG_CS, RTWDOG_CS_EN, RTWDOG_CS_UPDATE);
+
+}

arch/arm/src/imxrt/imxrt_wdog.h

@@ -0,0 +1,72 @@
+/****************************************************************************
+ * arch/arm/src/imxrt/imxrt_wdog.h
+ *
+ *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ *   Author:  Janne Rosberg <janne@offcode.fi>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_IMRT_IMXRT_WDOG_H
+#define __ARCH_ARM_SRC_IMRT_IMXRT_WDOG_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/compiler.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "up_internal.h"
+#include "chip.h"
+#include "chip/imxrt_wdog.h"
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: imxrt_wdog_disable
+ *
+ * Description:
+ *   Called at the very beginning of _start.  Disables all watchdogs
+ *
+ ****************************************************************************/
+
+void imxrt_wdog_disable_all(void);
+
+#endif /* __ARCH_ARM_SRC_IMRT_IMXRT_WDOG_H */

configs/Kconfig

@@ -258,15 +258,15 @@ config ARCH_BOARD_FREEDOM_KL26Z
 		This is the configuration for the NXP/FreeScale Freedom KL26Z board.  This
 		board has the K26Z128VLH4 chip with a built-in SDA debugger.
 
-config ARCH_BOARD_HYMINI_STM32V
+config ARCH_BOARD_IMXRT1050_EVK
-	bool "HY-Mini STM32v board"
+	bool "NXP i.MX RT 1050 EVK"
-	depends on ARCH_CHIP_STM32F103VC
+	depends on ARCH_CHIP_MIMXRT1052DVL6A
 	select ARCH_HAVE_LEDS
 	select ARCH_HAVE_BUTTONS
 	select ARCH_HAVE_IRQBUTTONS
 	---help---
-		A configuration for the HY-Mini STM32v board.  This board is based on the
+		This is the board configuratino for the port of NuttX to the NXP i.MXRT
-		STM32F103VCT6 chip.
+		evaluation kit, MIMXRT1050-EVKB.  This board features the MIMXRT1052DVL6A MCU.
 
 config ARCH_BOARD_INDIUM_F7
 	bool "Indium-F7"
@@ -1627,6 +1627,7 @@ config ARCH_BOARD
 	default "freedom-kl25z"            if ARCH_BOARD_FREEDOM_KL25Z
 	default "freedom-kl26z"            if ARCH_BOARD_FREEDOM_KL26Z
 	default "hymini-stm32v"            if ARCH_BOARD_HYMINI_STM32V
+	default "imxrt1050-evk"            if ARCH_BOARD_IMXRT1050_EVK
 	default "indium-f7"                if ARCH_BOARD_INDIUM_F7
 	default "kwikstik-k40"             if ARCH_BOARD_KWIKSTIK_K40
 	default "launchxl-tms57004"        if ARCH_BOARD_LAUNCHXL_TMS57004
@@ -1866,6 +1867,9 @@ endif
 if ARCH_BOARD_HYMINI_STM32V
 source "configs/hymini-stm32v/Kconfig"
 endif
+if ARCH_BOARD_IMXRT1050_EVK
+source "configs/imxrt1050-evk/Kconfig"
+endif
 if ARCH_BOARD_INDIUM_F7
 source "configs/indium-f7/Kconfig"
 endif

configs/imxrt1050-evk/Kconfig

@@ -0,0 +1,7 @@
+#
+# For a description of the syntax of this configuration file,
+# see the file kconfig-language.txt in the NuttX tools repository.
+#
+
+if ARCH_BOARD_IMXRT1050_EVK
+endif

configs/imxrt1050-evk/README.txt

@@ -0,0 +1,168 @@
+README
+======
+
+  This README file provides information about the port of NuttX to the NXP
+  i.MXRT evaluation kit, MIMXRT1050-EVKB.  This board features the
+  MIMXRT1052DVL6A MCU.  Some of the features of this board include:
+
+    o Processor
+
+      - MIMXRT1052DVL6A processor
+
+    o Memory
+
+      - 256 Mb SDRAM memory
+      - 512 Mb Hyper Flash
+      - Footprint for QSPI Flash
+      - TF socket for SD card
+
+    o Display and Audio
+
+      - Parallel LCD connector
+      - Camera connector
+      - Audio CODEC
+      - 4-pole audio headphone jack
+      - External speaker connection
+      - Microphone
+      - SPDIF connector
+
+    o Connectivity
+
+      - Micro USB host and OTG connectors
+      - Ethernet (10/100T) connector
+      - CAN transceivers
+      - Arduino® interface
+
+Contents
+========
+
+  o Serial Console
+  o LEDs and buttons
+  o Configurations
+    - Configuration sub-directories
+
+Serial Console
+==============
+
+  To be provided.
+
+  GPIO_AD_B0_12 LPUART1_TX UART Console
+  GPIO_AD_B0_13 LPUART1_RX UART Console
+
+LEDs and buttons
+================
+
+  LEDs
+  ----
+
+  There are four LED status indicators located on the EVK Board.  The
+  functions of these LEDs include:
+
+    - Main Power Supply(D3)
+      Green: DC 5V main supply is normal.
+      Red:   J2 input voltage is over 5.6V.
+      Off:   The board is not powered.
+    - Reset RED LED(D15)
+    - OpenSDA LED(D16)
+    - USER LED(D18)
+
+  Only a single LED, D18, is under software control.  It connects to
+  GPIO_AD_B0_09 which is shared with JTAG_TDI and ENET_RST
+
+  This LED is not used by the board port unless CONFIG_ARCH_LEDS is
+  defined.  In that case, the usage by the board port is defined in
+  include/board.h and src/sam_autoleds.c. The LED is used to encode
+  OS-related events as follows:
+
+    ------------------- ----------------------- ------
+    SYMBOL              Meaning                 LED
+    ------------------- ----------------------- ------
+    LED_STARTED         NuttX has been started  OFF
+    LED_HEAPALLOCATE    Heap has been allocated OFF
+    LED_IRQSENABLED     Interrupts enabled      OFF
+    LED_STACKCREATED    Idle stack created      ON
+    LED_INIRQ           In an interrupt         N/C
+    LED_SIGNAL          In a signal handler     N/C
+    LED_ASSERTION       An assertion failed     N/C
+    LED_PANIC           The system has crashed  FLASH
+
+  Thus if the LED is statically on, NuttX has successfully  booted and is,
+  apparently, running normally.  If the LED is flashing at approximately
+  2Hz, then a fatal error has been detected and the system has halted.
+
+  Buttons
+  -------
+
+  There are four user interface switches on the MIMXRT1050 EVK Board:
+
+    - SW1: Power Switch (slide switch)
+    - SW2: ON/OFF Button
+    - SW3: Reset button
+    - SW8: User button
+
+  Only the user button is available to the software.  It is sensed on the
+  WAKEUP pin which will be pulled low when the button is pressed.
+
+Configurations
+==============
+
+  Information Common to All Configurations
+  ----------------------------------------
+  Each i.MX RT 10050 configuration is maintained in a sub-directory and
+  can be selected as follow:
+
+    tools/configure.sh [OPTIONS] imxrt1050-evk/<subdir>
+
+  Where typical options are -l to configure to build on Linux or -c to
+  configure for Cygwin under Linux.  'tools/configure.sh -h' will show
+  you all of the options.
+
+  Before building, make sure the PATH environment variable include the
+  correct path to the directory than holds your toolchain binaries.
+
+  And then build NuttX by simply typing the following.  At the conclusion of
+  the make, the nuttx binary will reside in an ELF file called, simply, nuttx.
+
+    make
+
+  The <subdir> that is provided above as an argument to the tools/configure.sh
+  must be is one of the following.
+
+  NOTES:
+
+  1. These configurations use the mconf-based configuration tool.  To
+    change any of these configurations using that tool, you should:
+
+    a. Build and install the kconfig-mconf tool.  See nuttx/README.txt
+       see additional README.txt files in the NuttX tools repository.
+
+    b. Execute 'make menuconfig' in nuttx/ in order to start the
+       reconfiguration process.
+
+  2. Unless stated otherwise, all configurations generate console
+     output on UART3 (i.e., for the Arduino serial shield).
+
+  3. All of these configurations are set up to build under Windows using the
+     "GNU Tools for ARM Embedded Processors" that is maintained by ARM
+     (unless stated otherwise in the description of the configuration).
+
+       https://developer.arm.com/open-source/gnu-toolchain/gnu-rm
+
+     That toolchain selection can easily be reconfigured using
+     'make menuconfig'.  Here are the relevant current settings:
+
+     Build Setup:
+       CONFIG_HOST_WINDOWS=y               : Window environment
+       CONFIG_WINDOWS_CYGWIN=y             : Cywin under Windows
+
+     System Type -> Toolchain:
+       CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIW=y : GNU ARM EABI toolchain
+
+Configuration sub-directories
+-----------------------------
+
+  nsh:
+
+    Configures the NuttShell (nsh) located at examples/nsh.  This NSH
+    configuration is focused on low level, command-line driver testing.
+    It has no network.

configs/imxrt1050-evk/include/board.h

@@ -0,0 +1,173 @@
+/************************************************************************************
+ * configs/imxrt1050/include/board.h
+ *
+ *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __CONFIGS_IMXRT1050_EVK_INCLUDE_BOARD_H
+#define __CONFIGS_IMXRT1050_EVK_INCLUDE_BOARD_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+/* Clocking *************************************************************************/
+
+/* Set VDD_SOC to 1.5V */
+
+#define IMXRT_VDD_SOC (0x12)
+
+/*
+ * Set Arm PLL (PLL1) to 1200Mhz = (24Mhz * 100) / 2
+ * Set Sys PLL (PLL2) to 528Mhz = 1
+ *   (0 = 20 * 24Mhz = 480Mhz
+ *    1 = 22 * 24Mhz = 528Mhz)
+ *
+ * Arm clock divider = 2 -> Arm Clock = 600Mhz
+ * AHB clock divider = 1
+ * IPG clock divider = 4
+ *
+ */
+
+#define BOARD_XTAL_FREQUENCY    24000000
+
+#define IMXRT_ARM_PLL_SELECT    (100)
+#define IMXRT_SYS_PLL_SELECT    (1)
+#define IMXRT_ARM_CLOCK_DIVIDER (1)
+#define IMXRT_AHB_CLOCK_DIVIDER (0)
+#define IMXRT_IPG_CLOCK_DIVIDER (3)
+
+#define BOARD_CPU_FREQUENCY \
+  (BOARD_XTAL_FREQUENCY * IMXRT_ARM_PLL_SELECT) / (IMXRT_ARM_CLOCK_DIVIDER + 1)
+
+/* Define lpuart RF and TX pins
+ *
+ * WARNING: imxrt_pinmux.h should be added and used later.
+ */
+
+#define IOMUX_UART              (IOMUX_PULL_UP_100K | IOMUX_CMOS_OUTPUT | \
+                                 IOMUX_DRIVE_40OHM | IOMUX_SLEW_FAST | \
+                                 IOMUX_SPEED_MEDIUM | IOMUX_SCHMITT_TRIGGER)
+#define GPIO_LPUART1_RX_DATA    (GPIO_PERIPH | GPIO_ALT2 | \
+                                 GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_13_INDEX) | \
+                                 IOMUX_UART)
+#define GPIO_LPUART1_TX_DATA    (GPIO_PERIPH | GPIO_ALT2 | \
+                                 GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_12_INDEX) | \
+                                 IOMUX_UART)
+
+/* LED definitions ******************************************************************/
+/* There are four LED status indicators located on the EVK Board.  The functions of
+ * these LEDs include:
+ *
+ *   - Main Power Supply(D3)
+ *     Green: DC 5V main supply is normal.
+ *     Red:   J2 input voltage is over 5.6V.
+ *     Off:   The board is not powered.
+ *   - Reset RED LED(D15)
+ *   - OpenSDA LED(D16)
+ *   - USER LED(D18)
+ *
+ * Only a single LED, D18, is under software control.
+ */
+
+/* LED index values for use with board_userled() */
+
+#define BOARD_USERLED     0
+#define BOARD_NLEDS       1
+
+/* LED bits for use with board_userled_all() */
+
+#define BOARD_USERLED_BIT (1 << BOARD_USERLED)
+
+/* This LED is not used by the board port unless CONFIG_ARCH_LEDS is
+ * defined.  In that case, the usage by the board port is defined in
+ * include/board.h and src/sam_autoleds.c. The LED is used to encode
+ * OS-related events as follows:
+ *
+ *   -------------------- ----------------------------- ------
+ *   SYMBOL                   Meaning                   LED
+ *   -------------------- ----------------------------- ------ */
+
+#define LED_STARTED       0  /* NuttX has been started  OFF    */
+#define LED_HEAPALLOCATE  0  /* Heap has been allocated OFF    */
+#define LED_IRQSENABLED   0  /* Interrupts enabled      OFF    */
+#define LED_STACKCREATED  1  /* Idle stack created      ON     */
+#define LED_INIRQ         2  /* In an interrupt         N/C    */
+#define LED_SIGNAL        2  /* In a signal handler     N/C    */
+#define LED_ASSERTION     2  /* An assertion failed     N/C    */
+#define LED_PANIC         3  /* The system has crashed  FLASH  */
+#undef  LED_IDLE             /* Not used                       */
+
+/* Thus if the LED is statically on, NuttX has successfully  booted and is,
+ * apparently, running normally.  If the LED is flashing at approximately
+ * 2Hz, then a fatal error has been detected and the system has halted.
+ */
+
+/* Button definitions ***************************************************************/
+
+/* PIO Disambiguation ***************************************************************/
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __CONFIGS_IMXRT1050_EVK_INCLUDE_BOARD_H */

configs/imxrt1050-evk/nsh/defconfig

@@ -0,0 +1,28 @@
+# CONFIG_NSH_DISABLE_IFCONFIG is not set
+# CONFIG_NSH_DISABLE_PS is not set
+CONFIG_ARCH_BOARD_IMXRT1050_EVK=y
+CONFIG_ARCH_BOARD="imxrt1050-evk"
+CONFIG_ARCH_CHIP_IMXRT=y
+CONFIG_ARCH_CHIP_MIMXRT1052DVL6A=y
+CONFIG_ARCH_STACKDUMP=y
+CONFIG_ARCH="arm"
+CONFIG_BOARD_LOOPSPERMSEC=20000
+CONFIG_EXAMPLES_NSH=y
+CONFIG_IDLETHREAD_STACKSIZE=2048
+CONFIG_IMXRT_LPUART1=y
+CONFIG_INTELHEX_BINARY=y
+CONFIG_LPUART1_SERIAL_CONSOLE=y
+CONFIG_MAX_TASKS=16
+CONFIG_MAX_WDOGPARMS=2
+CONFIG_NFILE_DESCRIPTORS=8
+CONFIG_NFILE_STREAMS=8
+CONFIG_NSH_FILEIOSIZE=512
+CONFIG_NSH_LINELEN=64
+CONFIG_NSH_READLINE=y
+CONFIG_PREALLOC_MQ_MSGS=4
+CONFIG_PREALLOC_WDOGS=16
+CONFIG_RAM_SIZE=536870912
+CONFIG_RAM_START=0x20200000
+CONFIG_START_DAY=14
+CONFIG_START_MONTH=3
+CONFIG_USER_ENTRYPOINT="nsh_main"