From cf8c25df643bf54b2700281108316139eea5b26f Mon Sep 17 00:00:00 2001 From: Ivan Ucherdzhiev Date: Thu, 12 Apr 2018 09:31:09 -0600 Subject: [PATCH] This commit brings in basic support fo the i.MX RT 1050 'crossover' SoC. The basic support is complete and compiles without error, but is still untested. This port was the joing effort of Janne Rosberg, Ivan Ucherdzhiev, and myself. I give credit to Ivan for the kill because he is the one to held on to the end. Squashed commit of the following: Author: Gregory Nutt configs/imxrt1050-evk/scripts: Add section to linker script to handle the case where RAMFUNCs are enabled. RAMFUNCs appear to be enabled in the default configuration ... they probably should not be enabled. Author: Ivan Ucherdzhiev arch/arm/src/imxrt: imxrt_lowputc.c is finished. Now everything needed for the initial port is done and ready for testing. arch/arm/src/imxrt: Add logic to imxrt_lowputc.c. Still incomplete. Author: Ivan Ucherdzhiev arch/arm/src/imxrt: Add serial support. configs/imxrt1050-evk: Add linker script. Author: Gregory Nutt arch/arm/src/imxrt: Add initial cut at imxrt_allocateheap.c Author: Ivan Ucherdzhiev arm/arm/src/imxrt: Completes all definitions for PADMUX, CTLMUX, and IOMUX_INPUT and mapping tables on imxrt_gpio.c and imxr_iomuxc.c. arch/arm/src/imxrt/chip: Add definitions for IMXRT_PADCTL and IMXRT_PADMUX registers. Only the IMXRT_INPUT definitions in this commit. arch/arm/src/imxrt/chip: Add more IOMUXC register definitions. Author: Gregory Nutt configs/imxrt1050-evk: Add STRIP definition to Make.defs. arch/arm/src/imxrt: Bring in i.MX6 memory configuration settings. arch/arm/src/imxrt: Remove call to non-existent imxrt_gpioinit() from imxrt_start.c. arch/arm/src/imxrt: Bring in incomplete imxrt_iomuxc.c file from i.mx6. arch/arm/src/imxrt: Add first cut at GPIO interrupt logic. arch/arm/include: Add definitions to support a second level of GPIO pin interrupts. Author: Janne Rosberg arch/arm/src/imxrt: Add imxrt_wdog.c/.h Author: Gregory Nutt arch/arm/src/imxrt: Port SAMv7 interrupt logic to imxrt_irq.c. arch/arm/src/imxrt: More clarification of the start-up memory map. arch/arm/src/imxrt: Some mostly cosmetic clean-up to the imxrt_start.c file that was so rudely taken from the SAMv7. arch/arm/src/imxrt: Add imxrt_start.c. Initial commit is the the SAMv7 startup logic with name changes. Author: Ivan Ucherdzhiev arch/arm/src/imxrt: Adds a few IOMUXC register definitions. Author: Janne Rosberg arch/arm/src/imxrt: Add imxrt_clockconfig.c/.h configs/imxrt1050-evk: Add clock configuration definitions to board.h arch/arm/src/imxrt: Fix CCM register name; Fix doubly defined in LPUART bit field. arch/arm/src/imxrt: Add analog defines to CCM register definition header file. Author: Gregory Nutt arch/arm/src/imxrt: Bring in GPIO C files from i.MX6. Things are in disarray now because that GPIO logic depends on IOMUXC logic which is not yet in place. arch/arm/src/imxrt: Add a few more GPIO definitions to make the header file compatible with i.MX6 arch/arm/src/imxrt/chip: Add GPIO register definition file. Author: Janne Rosberg arch/arm/src/imxrt: Add DCDC register definitions. arch/arm/srch/imxrt: Add CCM register bit definitions Author: Gregory Nutt Purely cosmetic arch/arm/src/imxrt: Add system reset controller register definition header file. Embarassingly trivial change left in compiler. arch/arm/src/imxrt: Finishes i.MX RT1050 LPUART register definition header file. arch/arm/src/imxrt: Beginning of an i.MX RT1050 LPUART register definition header file. Some trivial things Author: Janne Rosberg arch/arm/src/imxrt: Add imxrt_wdog.h arch/arm/src/imxrt: Add initial imxrt_ccm.h Author: Gregory Nutt Trivial update to README. arch/arm/src/imxrt: The i.MX Rt implements 4 bits of interrupt priority, not two. Thanks, Janne. arch/arm/src/imxrt: Fix some initial compile issues. Still a long way from complete, but there is a buildable environment now for the imxrt1050-evk. configs/imxrt1050-evk: Add an initial NSH configuration for testing. configs/Kconfig: Hook the i.MX RT 1050 board configuration into the NuttX configuration system. configs/imxrt_evk: Add the framework for i.MX RT 1050 board support. arch/arm/src/imxrt: Bring in a few more files from LPC54xxx. arch/arm/src/imxrt: Bring in imxrt_clrpend() from the LPC54xxx. arch/arm/src/imxrt: Bring in Cortex-M7 SysTick setup from the SAMv7. arch/arm/src/imxrt: Add a few easy files. arch/arm/src/imxrt/chip: Add memory map header files. arch/arm/src/imxrt: A few basic files to start the port to the i.MX RT 1050. --- Documentation/README.html | 2 + README.txt | 2 + arch/arm/Kconfig | 20 + arch/arm/include/imxrt/chip.h | 139 ++ arch/arm/include/imxrt/imxrt105x_irq.h | 467 ++++++ arch/arm/include/imxrt/irq.h | 114 ++ arch/arm/src/Makefile | 3 +- arch/arm/src/imxrt/Kconfig | 316 ++++ arch/arm/src/imxrt/Make.defs | 108 ++ arch/arm/src/imxrt/chip.h | 81 + arch/arm/src/imxrt/chip/imxrt105x_memorymap.h | 259 +++ arch/arm/src/imxrt/chip/imxrt_ccm.h | 1010 ++++++++++++ arch/arm/src/imxrt/chip/imxrt_dcdc.h | 152 ++ arch/arm/src/imxrt/chip/imxrt_gpio.h | 136 ++ arch/arm/src/imxrt/chip/imxrt_iomuxc.h | 1400 +++++++++++++++++ arch/arm/src/imxrt/chip/imxrt_lpuart.h | 416 +++++ arch/arm/src/imxrt/chip/imxrt_memorymap.h | 51 + arch/arm/src/imxrt/chip/imxrt_src.h | 157 ++ arch/arm/src/imxrt/chip/imxrt_wdog.h | 142 ++ arch/arm/src/imxrt/imxrt_allocateheap.c | 357 +++++ arch/arm/src/imxrt/imxrt_clockconfig.c | 159 ++ arch/arm/src/imxrt/imxrt_clockconfig.h | 61 + arch/arm/src/imxrt/imxrt_clrpend.c | 106 ++ arch/arm/src/imxrt/imxrt_config.h | 206 +++ arch/arm/src/imxrt/imxrt_gpio.c | 510 ++++++ arch/arm/src/imxrt/imxrt_gpio.h | 311 ++++ arch/arm/src/imxrt/imxrt_gpioirq.c | 630 ++++++++ arch/arm/src/imxrt/imxrt_idle.c | 188 +++ arch/arm/src/imxrt/imxrt_iomuxc.c | 298 ++++ arch/arm/src/imxrt/imxrt_iomuxc.h | 170 ++ arch/arm/src/imxrt/imxrt_irq.c | 676 ++++++++ arch/arm/src/imxrt/imxrt_irq.h | 60 + arch/arm/src/imxrt/imxrt_lowputc.c | 572 +++++++ arch/arm/src/imxrt/imxrt_lowputc.h | 115 ++ arch/arm/src/imxrt/imxrt_mpuinit.c | 141 ++ arch/arm/src/imxrt/imxrt_mpuinit.h | 106 ++ arch/arm/src/imxrt/imxrt_serial.c | 1194 ++++++++++++++ arch/arm/src/imxrt/imxrt_serial.h | 126 ++ arch/arm/src/imxrt/imxrt_start.c | 404 +++++ arch/arm/src/imxrt/imxrt_start.h | 126 ++ arch/arm/src/imxrt/imxrt_timerisr.c | 139 ++ arch/arm/src/imxrt/imxrt_userspace.c | 105 ++ arch/arm/src/imxrt/imxrt_userspace.h | 93 ++ arch/arm/src/imxrt/imxrt_wdog.c | 95 ++ arch/arm/src/imxrt/imxrt_wdog.h | 72 + configs/Kconfig | 14 +- configs/imxrt1050-evk/Kconfig | 7 + configs/imxrt1050-evk/README.txt | 168 ++ configs/imxrt1050-evk/include/board.h | 173 ++ configs/imxrt1050-evk/nsh/defconfig | 28 + configs/imxrt1050-evk/scripts/Make.defs | 128 ++ configs/imxrt1050-evk/scripts/flash-ocram.ld | 132 ++ configs/imxrt1050-evk/src/Makefile | 61 + configs/imxrt1050-evk/src/imxrt1050-evk.h | 115 ++ configs/imxrt1050-evk/src/imxrt_appinit.c | 90 ++ configs/imxrt1050-evk/src/imxrt_autoleds.c | 113 ++ configs/imxrt1050-evk/src/imxrt_boot.c | 92 ++ configs/imxrt1050-evk/src/imxrt_bringup.c | 75 + configs/imxrt1050-evk/src/imxrt_userleds.c | 84 + 59 files changed, 13269 insertions(+), 6 deletions(-) create mode 100644 arch/arm/include/imxrt/chip.h create mode 100644 arch/arm/include/imxrt/imxrt105x_irq.h create mode 100644 arch/arm/include/imxrt/irq.h create mode 100644 arch/arm/src/imxrt/Kconfig create mode 100644 arch/arm/src/imxrt/Make.defs create mode 100644 arch/arm/src/imxrt/chip.h create mode 100644 arch/arm/src/imxrt/chip/imxrt105x_memorymap.h create mode 100644 arch/arm/src/imxrt/chip/imxrt_ccm.h create mode 100644 arch/arm/src/imxrt/chip/imxrt_dcdc.h create mode 100644 arch/arm/src/imxrt/chip/imxrt_gpio.h create mode 100644 arch/arm/src/imxrt/chip/imxrt_iomuxc.h create mode 100644 arch/arm/src/imxrt/chip/imxrt_lpuart.h create mode 100644 arch/arm/src/imxrt/chip/imxrt_memorymap.h create mode 100644 arch/arm/src/imxrt/chip/imxrt_src.h create mode 100644 arch/arm/src/imxrt/chip/imxrt_wdog.h create mode 100644 arch/arm/src/imxrt/imxrt_allocateheap.c create mode 100644 arch/arm/src/imxrt/imxrt_clockconfig.c create mode 100644 arch/arm/src/imxrt/imxrt_clockconfig.h create mode 100644 arch/arm/src/imxrt/imxrt_clrpend.c create mode 100644 arch/arm/src/imxrt/imxrt_config.h create mode 100644 arch/arm/src/imxrt/imxrt_gpio.c create mode 100644 arch/arm/src/imxrt/imxrt_gpio.h create mode 100644 arch/arm/src/imxrt/imxrt_gpioirq.c create mode 100644 arch/arm/src/imxrt/imxrt_idle.c create mode 100644 arch/arm/src/imxrt/imxrt_iomuxc.c create mode 100644 arch/arm/src/imxrt/imxrt_iomuxc.h create mode 100644 arch/arm/src/imxrt/imxrt_irq.c create mode 100644 arch/arm/src/imxrt/imxrt_irq.h create mode 100644 arch/arm/src/imxrt/imxrt_lowputc.c create mode 100644 arch/arm/src/imxrt/imxrt_lowputc.h create mode 100644 arch/arm/src/imxrt/imxrt_mpuinit.c create mode 100644 arch/arm/src/imxrt/imxrt_mpuinit.h create mode 100644 arch/arm/src/imxrt/imxrt_serial.c create mode 100644 arch/arm/src/imxrt/imxrt_serial.h create mode 100644 arch/arm/src/imxrt/imxrt_start.c create mode 100644 arch/arm/src/imxrt/imxrt_start.h create mode 100644 arch/arm/src/imxrt/imxrt_timerisr.c create mode 100644 arch/arm/src/imxrt/imxrt_userspace.c create mode 100644 arch/arm/src/imxrt/imxrt_userspace.h create mode 100644 arch/arm/src/imxrt/imxrt_wdog.c create mode 100644 arch/arm/src/imxrt/imxrt_wdog.h create mode 100644 configs/imxrt1050-evk/Kconfig create mode 100644 configs/imxrt1050-evk/README.txt create mode 100644 configs/imxrt1050-evk/include/board.h create mode 100644 configs/imxrt1050-evk/nsh/defconfig create mode 100644 configs/imxrt1050-evk/scripts/Make.defs create mode 100644 configs/imxrt1050-evk/scripts/flash-ocram.ld create mode 100644 configs/imxrt1050-evk/src/Makefile create mode 100644 configs/imxrt1050-evk/src/imxrt1050-evk.h create mode 100644 configs/imxrt1050-evk/src/imxrt_appinit.c create mode 100644 configs/imxrt1050-evk/src/imxrt_autoleds.c create mode 100644 configs/imxrt1050-evk/src/imxrt_boot.c create mode 100644 configs/imxrt1050-evk/src/imxrt_bringup.c create mode 100644 configs/imxrt1050-evk/src/imxrt_userleds.c diff --git a/Documentation/README.html b/Documentation/README.html index e3ca40a8191..1cc5c91d63a 100644 --- a/Documentation/README.html +++ b/Documentation/README.html @@ -116,6 +116,8 @@ nuttx/ | |- hymini-stm32v/ | | |- RIDE/README.txt | | `- README.txt + | |- imxrt1050-evk/ + | | `- README.txt | |- indium-f7/ | | `- README.txt | |- kwikstik-k40/ diff --git a/README.txt b/README.txt index dc7bc4e6ff2..1a1d762c774 100644 --- a/README.txt +++ b/README.txt @@ -1685,6 +1685,8 @@ nuttx/ | | `- README.txt | |- hymini-stm32v/ | | `- README.txt + | |- imxrt1050-evk + | | `- README.txt | |- indium-f7 | | `- README.txt | |- kwikstik-k40/ diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index e3224d046f2..b03af7fd8ca 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -79,6 +79,22 @@ config ARCH_CHIP_IMX6 ---help--- Freescale iMX.6 architectures (Cortex-A9) +config ARCH_CHIP_IMXRT + bool "NXP/Freescale iMX.RT" + select ARCH_HAVE_CMNVECTOR + select ARCH_CORTEXM7 + select ARCH_HAVE_MPU + select ARCH_HAVE_FETCHADD + select ARCH_HAVE_RAMFUNCS + select ARCH_HAVE_TICKLESS + select ARCH_HAVE_I2CRESET + select ARCH_HAVE_SPI_CS_CONTROL + select ARM_HAVE_MPU_UNIFIED + select ARMV7M_CMNVECTOR + select ARMV7M_HAVE_STACKCHECK + ---help--- + NXP i.MX RT (ARM Cortex-M7) architectures + config ARCH_CHIP_KINETIS bool "NXP/Freescale Kinetis" select ARCH_CORTEXM4 @@ -550,6 +566,7 @@ config ARCH_CHIP default "efm32" if ARCH_CHIP_EFM32 default "imx1" if ARCH_CHIP_IMX1 default "imx6" if ARCH_CHIP_IMX6 + default "imxrt" if ARCH_CHIP_IMXRT default "kinetis" if ARCH_CHIP_KINETIS default "kl" if ARCH_CHIP_KL default "lc823450" if ARCH_CHIP_LC823450 @@ -773,6 +790,9 @@ endif if ARCH_CHIP_IMX6 source arch/arm/src/imx6/Kconfig endif +if ARCH_CHIP_IMXRT +source arch/arm/src/imxrt/Kconfig +endif if ARCH_CHIP_KINETIS source arch/arm/src/kinetis/Kconfig endif diff --git a/arch/arm/include/imxrt/chip.h b/arch/arm/include/imxrt/chip.h new file mode 100644 index 00000000000..9720dc65870 --- /dev/null +++ b/arch/arm/include/imxrt/chip.h @@ -0,0 +1,139 @@ +/************************************************************************************ + * arch/arm/include/imxrt/chip.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_IMXRT_CHIP_H +#define __ARCH_ARM_INCLUDE_IMXRT_CHIP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Get customizations for each supported chip */ + +/* MIMXRT1051CVL5A - Industrial, Reduced Features, 528MHz + * MIMXRT1051CVL5A - Consumer, Reduced Features, 600MHz + * MIMXRT1052CVL5A - Industrial, Full Feature, 528MHz + * MIMXRT1052CVL5A - Consumer, Full Feature, 600MHz + */ + +#if defined(CONFIG_ARCH_CHIP_MIMXRT1051DVL6A) || \ + defined(CONFIG_ARCH_CHIP_MIMXRT1051CVL5A) || \ + defined(CONFIG_ARCH_CHIP_MIMXRT1052DVL6A) || \ + defined(CONFIG_ARCH_CHIP_MIMXRT1052CVL5A) + +#define IMXRT_OCRAM_SIZE (512 * 1024) /* 512Kb OCRAM */ +#else +# error "Unknown i.MX RT chip type" +#endif + +/* NVIC priority levels *************************************************************/ +/* Each priority field holds an 8-bit priority value, 0-15. The lower the value, the + * greater the priority of the corresponding interrupt. The i.MX RT processor + * implements only bits[7:4] of each field, bits[3:0] read as zero and ignore writes. + */ + +#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits[7:4] set is minimum priority */ +#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ +#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ +#define NVIC_SYSH_PRIORITY_STEP 0x40 /* Two bits of interrupt priority used */ + +/* If CONFIG_ARMV7M_USEBASEPRI is selected, then interrupts will be disabled + * by setting the BASEPRI register to NVIC_SYSH_DISABLE_PRIORITY so that most + * interrupts will not have execution priority. SVCall must have execution + * priority in all cases. + * + * In the normal cases, interrupts are not nest-able and all interrupts run + * at an execution priority between NVIC_SYSH_PRIORITY_MIN and + * NVIC_SYSH_PRIORITY_MAX (with NVIC_SYSH_PRIORITY_MAX reserved for SVCall). + * + * If, in addition, CONFIG_ARCH_HIPRI_INTERRUPT is defined, then special + * high priority interrupts are supported. These are not "nested" in the + * normal sense of the word. These high priority interrupts can interrupt + * normal processing but execute outside of OS (although they can "get back + * into the game" via a PendSV interrupt). + * + * In the normal course of things, interrupts must occasionally be disabled + * using the up_irq_save() inline function to prevent contention in use of + * resources that may be shared between interrupt level and non-interrupt + * level logic. Now the question arises, if CONFIG_ARCH_HIPRI_INTERRUPT, + * do we disable all interrupts (except SVCall), or do we only disable the + * "normal" interrupts. Since the high priority interrupts cannot interact + * with the OS, you may want to permit the high priority interrupts even if + * interrupts are disabled. The setting CONFIG_ARCH_INT_DISABLEALL can be + * used to select either behavior: + * + * ----------------------------+--------------+---------------------------- + * CONFIG_ARCH_HIPRI_INTERRUPT | NO | YES + * ----------------------------+--------------+--------------+------------- + * CONFIG_ARCH_INT_DISABLEALL | N/A | YES | NO + * ----------------------------+--------------+--------------+------------- + * | | | SVCall + * | SVCall | SVCall | HIGH + * Disable here and below --------> MAXNORMAL ---> HIGH --------> MAXNORMAL + * | | MAXNORMAL | + * ----------------------------+--------------+--------------+------------- + */ + +#if defined(CONFIG_ARCH_HIPRI_INTERRUPT) && defined(CONFIG_ARCH_INT_DISABLEALL) +# define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + 2*NVIC_SYSH_PRIORITY_STEP) +# define NVIC_SYSH_HIGH_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP) +# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_HIGH_PRIORITY +# define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX +#else +# define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP) +# define NVIC_SYSH_HIGH_PRIORITY NVIC_SYSH_PRIORITY_MAX +# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_MAXNORMAL_PRIORITY +# define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX +#endif + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_INCLUDE_IMXRT_CHIP_H */ diff --git a/arch/arm/include/imxrt/imxrt105x_irq.h b/arch/arm/include/imxrt/imxrt105x_irq.h new file mode 100644 index 00000000000..9784ae7964a --- /dev/null +++ b/arch/arm/include/imxrt/imxrt105x_irq.h @@ -0,0 +1,467 @@ +/**************************************************************************************** + * arch/arm/include/imxrt/imxrt105x_irq.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +/* This file should never be included directed but, rather, only indirectly through + * nuttx/irq.h + */ + +#ifndef __ARCH_ARM_INCLUDE_IMXRT_IMXRT105X_IRQ_H +#define __ARCH_ARM_INCLUDE_IMXRT_IMXRT105X_IRQ_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* External interrupts (priority levels >= 256) *****************************************/ + +#define IMXRT_IRQ_EDMA0_16 (IMXRT_IRQ_EXTINT + 0) /* eDMA Channel 0/16 Transfer Complete */ +#define IMXRT_IRQ_EDMA1_17 (IMXRT_IRQ_EXTINT + 1) /* eDMA Channel 1/17 Transfer Complete */ +#define IMXRT_IRQ_EDMA2_18 (IMXRT_IRQ_EXTINT + 2) /* eDMA Channel 2/18 Transfer Complete */ +#define IMXRT_IRQ_EDMA3_19 (IMXRT_IRQ_EXTINT + 3) /* eDMA Channel 3/19 Transfer Complete */ +#define IMXRT_IRQ_EDMA4_20 (IMXRT_IRQ_EXTINT + 4) /* eDMA Channel 4/20 Transfer Complete */ +#define IMXRT_IRQ_EDMA5_21 (IMXRT_IRQ_EXTINT + 5) /* eDMA Channel 5/21 Transfer Complete */ +#define IMXRT_IRQ_EDMA6_22 (IMXRT_IRQ_EXTINT + 6) /* eDMA Channel 6/22 Transfer Complete */ +#define IMXRT_IRQ_EDMA7_23 (IMXRT_IRQ_EXTINT + 7) /* eDMA Channel 7/23 Transfer Complete */ +#define IMXRT_IRQ_EDMA8_24 (IMXRT_IRQ_EXTINT + 8) /* eDMA Channel 8/24 Transfer Complete */ +#define IMXRT_IRQ_EDMA9_25 (IMXRT_IRQ_EXTINT + 9) /* eDMA Channel 9/25 Transfer Complete */ +#define IMXRT_IRQ_EDMA0_26 (IMXRT_IRQ_EXTINT + 10) /* eDMA Channel 10/26 Transfer Complete */ +#define IMXRT_IRQ_EDMA1_27 (IMXRT_IRQ_EXTINT + 11) /* eDMA Channel 11/27 Transfer Complete */ +#define IMXRT_IRQ_EDMA2_28 (IMXRT_IRQ_EXTINT + 12) /* eDMA Channel 12/28 Transfer Complete */ +#define IMXRT_IRQ_EDMA3_29 (IMXRT_IRQ_EXTINT + 13) /* eDMA Channel 13/29 Transfer Complete */ +#define IMXRT_IRQ_EDMA4_30 (IMXRT_IRQ_EXTINT + 14) /* eDMA Channel 14/30 Transfer Complete */ +#define IMXRT_IRQ_EDMA5_31 (IMXRT_IRQ_EXTINT + 15) /* eDMA Channel 15/31 Transfer Complete */ +#define IMXRT_IRQ_EDMA_ERROR (IMXRT_IRQ_EXTINT + 16) /* Error Interrupt, Channels 0-15 / 16-31 */ +#define IMXRT_IRQ_CM70 (IMXRT_IRQ_EXTINT + 17) /* CTI trigger outputs (internal: CTIIRQ[0]) */ +#define IMXRT_IRQ_CM71 (IMXRT_IRQ_EXTINT + 18) /* CTI trigger outputs (internal: CTIIRQ[1]) */ +#define IMXRT_IRQ_CM7CP (IMXRT_IRQ_EXTINT + 19) /* CorePlatform exception IRQ */ +#define IMXRT_IRQ_LPUART1 (IMXRT_IRQ_EXTINT + 20) /* UART1 TX/RX interrupt */ +#define IMXRT_IRQ_LPUART2 (IMXRT_IRQ_EXTINT + 21) /* UART2 TX/RX interrupt */ +#define IMXRT_IRQ_LPUART3 (IMXRT_IRQ_EXTINT + 22) /* UART3 TX/RX interrupt */ +#define IMXRT_IRQ_LPUART4 (IMXRT_IRQ_EXTINT + 23) /* UART4 TX/RX interrupt */ +#define IMXRT_IRQ_LPUART5 (IMXRT_IRQ_EXTINT + 24) /* UART5 TX/RX interrupt */ +#define IMXRT_IRQ_LPUART6 (IMXRT_IRQ_EXTINT + 25) /* UART6 TX/RX interrupt */ +#define IMXRT_IRQ_LPUART7 (IMXRT_IRQ_EXTINT + 26) /* UART7 TX/RX interrupt */ +#define IMXRT_IRQ_LPUART8 (IMXRT_IRQ_EXTINT + 27) /* UART8 TX/RX interrupt */ +#define IMXRT_IRQ_LPI2C1 (IMXRT_IRQ_EXTINT + 28) /* I2C1 Interrupt */ +#define IMXRT_IRQ_LPI2C2 (IMXRT_IRQ_EXTINT + 29) /* I2C2 Interrupt */ +#define IMXRT_IRQ_LPI2C3 (IMXRT_IRQ_EXTINT + 30) /* I2C3 Interrupt */ +#define IMXRT_IRQ_LPI2C4 (IMXRT_IRQ_EXTINT + 31) /* I2C- Interrupt */ +#define IMXRT_IRQ_LPSPI1 (IMXRT_IRQ_EXTINT + 32) /* LPSPI1 interrupt */ +#define IMXRT_IRQ_LPSPI2 (IMXRT_IRQ_EXTINT + 33) /* LPSPI2 interrupt */ +#define IMXRT_IRQ_LPSPI3 (IMXRT_IRQ_EXTINT + 34) /* LPSPI3 interrupt */ +#define IMXRT_IRQ_LPSPI4 (IMXRT_IRQ_EXTINT + 35) /* LPSPI4 interrupt */ +#define IMXRT_IRQ_CAN1 (IMXRT_IRQ_EXTINT + 36) /* CAN1 interrupt */ +#define IMXRT_IRQ_CAN2 (IMXRT_IRQ_EXTINT + 37) /* CAN2 interrupt */ +#define IMXRT_IRQ_CM7FR (IMXRT_IRQ_EXTINT + 38) /* FlexRAM address fault */ +#define IMXRT_IRQ_KPP (IMXRT_IRQ_EXTINT + 39) /* Keypad Interrupt */ +#define IMXRT_IRQ_TSCDIG (IMXRT_IRQ_EXTINT + 40) /* TSC interrupt */ +#define IMXRT_IRQ_GPRIRQ (IMXRT_IRQ_EXTINT + 41) /* Notify cores on exception while boot */ +#define IMXRT_IRQ_LCDIF (IMXRT_IRQ_EXTINT + 42) /* LCDIF Sync Interrupt */ +#define IMXRT_IRQ_CSI (IMXRT_IRQ_EXTINT + 43) /* CSI interrupt */ +#define IMXRT_IRQ_PXP (IMXRT_IRQ_EXTINT + 44) /* PXP interrupt */ +#define IMXRT_IRQ_WDOG2 (IMXRT_IRQ_EXTINT + 45) /* Watchdog Timer reset */ +#define IMXRT_IRQ_SNVS (IMXRT_IRQ_EXTINT + 46) /* SNVS Functional Interrupt */ +#define IMXRT_IRQ_SNVSSEC (IMXRT_IRQ_EXTINT + 47) /* SNVS Security Interrupt */ +#define IMXRT_IRQ_SNVSSB (IMXRT_IRQ_EXTINT + 48) /* ON-OFF short button press */ +#define IMXRT_IRQ_CSU (IMXRT_IRQ_EXTINT + 49) /* CSU Interrupt Request 1 */ +#define IMXRT_IRQ_DCP (IMXRT_IRQ_EXTINT + 50) /* DCP channel/CRC interrupts (channel != 0) */ +#define IMXRT_IRQ_DCP0 (IMXRT_IRQ_EXTINT + 51) /* DCP channel 0 interrupt */ +#define IMXRT_IRQ_RESERVED52 (IMXRT_IRQ_EXTINT + 52) /* Reserved */ +#define IMXRT_IRQ_TRNG (IMXRT_IRQ_EXTINT + 53) /* TRNG Interrupt */ +#define IMXRT_IRQ_SJC (IMXRT_IRQ_EXTINT + 54) /* SJC Interrupt from General Purpose register */ +#define IMXRT_IRQ_BEE (IMXRT_IRQ_EXTINT + 55) /* BEE IRQ */ +#define IMXRT_IRQ_SAI1 (IMXRT_IRQ_EXTINT + 56) /* SAI1 interrupt */ +#define IMXRT_IRQ_SAI2 (IMXRT_IRQ_EXTINT + 57) /* SAI2 interrupt */ +#define IMXRT_IRQ_SAI3RX (IMXRT_IRQ_EXTINT + 58) /* SAI3 RX interrupt */ +#define IMXRT_IRQ_SAI3TX (IMXRT_IRQ_EXTINT + 59) /* SAI3 TX interrupt */ +#define IMXRT_IRQ_SPDIF (IMXRT_IRQ_EXTINT + 60) /* SPDIF interrupt */ +#define IMXRT_IRQ_PMU (IMXRT_IRQ_EXTINT + 61) /* Brown-out event 1.1, 2.5 or 3.0 regulators */ +#define IMXRT_IRQ_RESERVED62 (IMXRT_IRQ_EXTINT + 62) /* Reserved */ +#define IMXRT_IRQ_TEMP (IMXRT_IRQ_EXTINT + 63) /* Temperature Monitor */ +#define IMXRT_IRQ_TEMPPANIC (IMXRT_IRQ_EXTINT + 64) /* TempSensor panic */ +#define IMXRT_IRQ_USBPHY0 (IMXRT_IRQ_EXTINT + 65) /* USBPHY (UTMI0) interrupt */ +#define IMXRT_IRQ_USBPHY1 (IMXRT_IRQ_EXTINT + 66) /* USBPHY (UTMI1) interrupt */ +#define IMXRT_IRQ_ADC1 (IMXRT_IRQ_EXTINT + 67) /* ADC1 interrupt */ +#define IMXRT_IRQ_ADC2 (IMXRT_IRQ_EXTINT + 68) /* ADC2 interrupt */ +#define IMXRT_IRQ_DCDC (IMXRT_IRQ_EXTINT + 69) /* DCDC interrupt */ +#define IMXRT_IRQ_RESERVED70 (IMXRT_IRQ_EXTINT + 70) /* Reserved */ +#define IMXRT_IRQ_RESERVED71 (IMXRT_IRQ_EXTINT + 71) /* Reserved */ +#define IMXRT_IRQ_GPIO1_0 (IMXRT_IRQ_EXTINT + 72) /* GPIO1 INT0 interrupt */ +#define IMXRT_IRQ_GPIO1_1 (IMXRT_IRQ_EXTINT + 73) /* GPIO1 INT1 interrupt */ +#define IMXRT_IRQ_GPIO1_2 (IMXRT_IRQ_EXTINT + 74) /* GPIO1 INT2 interrupt */ +#define IMXRT_IRQ_GPIO1_3 (IMXRT_IRQ_EXTINT + 75) /* GPIO1 INT3 interrupt */ +#define IMXRT_IRQ_GPIO1_4 (IMXRT_IRQ_EXTINT + 76) /* GPIO1 INT4 interrupt */ +#define IMXRT_IRQ_GPIO1_5 (IMXRT_IRQ_EXTINT + 77) /* GPIO1 INT5 interrupt */ +#define IMXRT_IRQ_GPIO1_6 (IMXRT_IRQ_EXTINT + 78) /* GPIO1 INT6 interrupt */ +#define IMXRT_IRQ_GPIO1_7 (IMXRT_IRQ_EXTINT + 79) /* GPIO1 INT7 interrupt */ +#define IMXRT_IRQ_GPIO1_0_15 (IMXRT_IRQ_EXTINT + 80) /* GPIO1 INT0-15 interrupt */ +#define IMXRT_IRQ_GPIO1_16_31 (IMXRT_IRQ_EXTINT + 81) /* GPIO1 INT16-31 interrupt */ +#define IMXRT_IRQ_GPIO2_0_15 (IMXRT_IRQ_EXTINT + 82) /* GPIO2 INT0-15 interrupt */ +#define IMXRT_IRQ_GPIO2_16_31 (IMXRT_IRQ_EXTINT + 83) /* GPIO2 INT16-31 interrupt */ +#define IMXRT_IRQ_GPIO3_0_15 (IMXRT_IRQ_EXTINT + 84) /* GPIO3 INT0-15 interrupt */ +#define IMXRT_IRQ_GPIO3_16_31 (IMXRT_IRQ_EXTINT + 85) /* GPIO3 INT16-31 interrupt */ +#define IMXRT_IRQ_GPIO4_0_15 (IMXRT_IRQ_EXTINT + 86) /* GPIO4 INT0-15 interrupt */ +#define IMXRT_IRQ_GPIO4_16_31 (IMXRT_IRQ_EXTINT + 87) /* GPIO4 INT16-31 interrupt */ +#define IMXRT_IRQ_GPIO5_0_15 (IMXRT_IRQ_EXTINT + 88) /* GPIO5 INT0-15 interrupt */ +#define IMXRT_IRQ_GPIO5_16_31 (IMXRT_IRQ_EXTINT + 89) /* GPIO5 INT16-31 interrupt */ +#define IMXRT_IRQ_FLEXIO1 (IMXRT_IRQ_EXTINT + 90) /* IPI compare interrupt */ +#define IMXRT_IRQ_FLEXIO2 (IMXRT_IRQ_EXTINT + 91) /* IPI compare interrupt */ +#define IMXRT_IRQ_WDOG1 (IMXRT_IRQ_EXTINT + 92) /* Watchdog Timer reset */ +#define IMXRT_IRQ_RTWDOG (IMXRT_IRQ_EXTINT + 93) /* Watchdog Timer reset */ +#define IMXRT_IRQ_EWM (IMXRT_IRQ_EXTINT + 94) /* EWM interrupt */ +#define IMXRT_IRQ_CCM_1 (IMXRT_IRQ_EXTINT + 95) /* CCM interrupt 1 */ +#define IMXRT_IRQ_CCM_2 (IMXRT_IRQ_EXTINT + 96) /* CCM interrupt 2 */ +#define IMXRT_IRQ_GPC (IMXRT_IRQ_EXTINT + 97) /* GPC interrupt 1 */ +#define IMXRT_IRQ_SRC (IMXRT_IRQ_EXTINT + 98) /* SRC interrupt */ +#define IMXRT_IRQ_RESERVED99 (IMXRT_IRQ_EXTINT + 99) /* Reserved */ +#define IMXRT_IRQ_GPT1 (IMXRT_IRQ_EXTINT + 100) /* GPT1 interrupt */ +#define IMXRT_IRQ_GPT2 (IMXRT_IRQ_EXTINT + 101) /* GPT2 interrupt */ +#define IMXRT_IRQ_FLEXPWM1_0 (IMXRT_IRQ_EXTINT + 102) /* FLEXPWM1 capture/compare/reload 0 interrupt */ +#define IMXRT_IRQ_FLEXPWM1_1 (IMXRT_IRQ_EXTINT + 103) /* FLEXPWM1 capture/compare/reload 1 interrupt */ +#define IMXRT_IRQ_FLEXPWM1_2 (IMXRT_IRQ_EXTINT + 104) /* FLEXPWM1 capture/compare/reload 2 interrupt */ +#define IMXRT_IRQ_FLEXPWM1_3 (IMXRT_IRQ_EXTINT + 105) /* FLEXPWM1 capture/compare/reload 3 interrupt */ +#define IMXRT_IRQ_FLEXPWM1_F (IMXRT_IRQ_EXTINT + 106) /* FLEXPWM1 fault interrupt */ +#define IMXRT_IRQ_RESERVED107 (IMXRT_IRQ_EXTINT + 107) /* Reserved */ +#define IMXRT_IRQ_FLEXSPI (IMXRT_IRQ_EXTINT + 108) /* FlexSPI interrupt */ +#define IMXRT_IRQ_SEMC (IMXRT_IRQ_EXTINT + 109) /* SEMC interrupt */ +#define IMXRT_IRQ_USDHC1 (IMXRT_IRQ_EXTINT + 110) /* USDHC1 interrupt */ +#define IMXRT_IRQ_USDHC2 (IMXRT_IRQ_EXTINT + 111) /* USDHC2 interrupt */ +#define IMXRT_IRQ_USBOTG2 (IMXRT_IRQ_EXTINT + 112) /* USBO2 USB OTG2 interrupt */ +#define IMXRT_IRQ_USBOTG1 (IMXRT_IRQ_EXTINT + 113) /* USBO2 USB OTG1 interrupt */ +#define IMXRT_IRQ_ENET (IMXRT_IRQ_EXTINT + 114) /* ENET MAC 0 interrupt */ +#define IMXRT_IRQ_ENET1588 (IMXRT_IRQ_EXTINT + 115) /* ENET MAC 0 1588 Timer Interrupt */ +#define IMXRT_IRQ_XBAR1_0_1 (IMXRT_IRQ_EXTINT + 116) /* XBAR1 interrupt 0/1 */ +#define IMXRT_IRQ_XBAR1_2_3 (IMXRT_IRQ_EXTINT + 117) /* XBAR1 interrupt 2/3 */ +#define IMXRT_IRQ_ADCETC_0 (IMXRT_IRQ_EXTINT + 118) /* ADC_ETC interrupt 0 */ +#define IMXRT_IRQ_ADCETC_1 (IMXRT_IRQ_EXTINT + 119) /* ADC_ETC interrupt 1 */ +#define IMXRT_IRQ_ADCETC_2 (IMXRT_IRQ_EXTINT + 120) /* ADC_ETC interrupt 2 */ +#define IMXRT_IRQ_ADCETC_ERR (IMXRT_IRQ_EXTINT + 121) /* ADC_ETC error interrupt */ +#define IMXRT_IRQ_PIT (IMXRT_IRQ_EXTINT + 122) /* PIT interrupt */ +#define IMXRT_IRQ_ACMP1 (IMXRT_IRQ_EXTINT + 123) /* ACMP1 interrupt */ +#define IMXRT_IRQ_ACMP2 (IMXRT_IRQ_EXTINT + 124) /* ACMP2 interrupt */ +#define IMXRT_IRQ_ACMP3 (IMXRT_IRQ_EXTINT + 125) /* ACMP3 interrupt */ +#define IMXRT_IRQ_ACMP4 (IMXRT_IRQ_EXTINT + 126) /* ACMP4 interrupt */ +#define IMXRT_IRQ_RESERVED127 (IMXRT_IRQ_EXTINT + 127) /* Reserved */ +#define IMXRT_IRQ_RESERVED128 (IMXRT_IRQ_EXTINT + 128) /* Reserved */ +#define IMXRT_IRQ_ENC1 (IMXRT_IRQ_EXTINT + 129) /* ENC1 interrupt */ +#define IMXRT_IRQ_ENC2 (IMXRT_IRQ_EXTINT + 130) /* ENC2 interrupt */ +#define IMXRT_IRQ_ENC3 (IMXRT_IRQ_EXTINT + 131) /* ENC3 interrupt */ +#define IMXRT_IRQ_ENC4 (IMXRT_IRQ_EXTINT + 132) /* ENC4 interrupt */ +#define IMXRT_IRQ_QTIMER1 (IMXRT_IRQ_EXTINT + 133) /* QTIMER1 timer 0-3 interrupt */ +#define IMXRT_IRQ_QTIMER2 (IMXRT_IRQ_EXTINT + 134) /* QTIMER2 timer 0-3 interrupt */ +#define IMXRT_IRQ_QTIMER3 (IMXRT_IRQ_EXTINT + 135) /* QTIMER3 timer 0-3 interrupt */ +#define IMXRT_IRQ_QTIMER4 (IMXRT_IRQ_EXTINT + 136) /* QTIMER4 timer 0-3 interrupt */ +#define IMXRT_IRQ_FLEXPWM2_0 (IMXRT_IRQ_EXTINT + 137) /* LEXPWM2 capture/compare/reload 0 interrupt */ +#define IMXRT_IRQ_FLEXPWM2_1 (IMXRT_IRQ_EXTINT + 138) /* LEXPWM2 capture/compare/reload 1 interrupt */ +#define IMXRT_IRQ_FLEXPWM2_2 (IMXRT_IRQ_EXTINT + 139) /* LEXPWM2 capture/compare/reload 1 interrupt */ +#define IMXRT_IRQ_FLEXPWM2_3 (IMXRT_IRQ_EXTINT + 140) /* LEXPWM2 capture/compare/reload 3 interrupt */ +#define IMXRT_IRQ_FLEXPWM2_F (IMXRT_IRQ_EXTINT + 141) /* LEXPWM2 fault interrupt */ +#define IMXRT_IRQ_FLEXPWM3_0 (IMXRT_IRQ_EXTINT + 142) /* LEXPWM3 capture/compare/reload 0 interrupt */ +#define IMXRT_IRQ_FLEXPWM3_1 (IMXRT_IRQ_EXTINT + 143) /* LEXPWM3 capture/compare/reload 1 interrupt */ +#define IMXRT_IRQ_FLEXPWM3_2 (IMXRT_IRQ_EXTINT + 144) /* LEXPWM3 capture/compare/reload 2 interrupt */ +#define IMXRT_IRQ_FLEXPWM3_F (IMXRT_IRQ_EXTINT + 146) /* LEXPWM3 fault interrupt */ +#define IMXRT_IRQ_FLEXPWM4_0 (IMXRT_IRQ_EXTINT + 147) /* LEXPWM4 capture/compare/reload 0 interrupt */ +#define IMXRT_IRQ_FLEXPWM4_1 (IMXRT_IRQ_EXTINT + 148) /* LEXPWM4 capture/compare/reload 1 interrupt */ +#define IMXRT_IRQ_FLEXPWM4_2 (IMXRT_IRQ_EXTINT + 149) /* LEXPWM4 capture/compare/reload 2 interrupt */ +#define IMXRT_IRQ_FLEXPWM4_3 (IMXRT_IRQ_EXTINT + 150) /* LEXPWM4 capture/compare/reload 3 interrupt */ +#define IMXRT_IRQ_FLEXPWM4_F (IMXRT_IRQ_EXTINT + 151) /* LEXPWM4 fault interrupt */ +#define IMXRT_IRQ_RESERVED152 (IMXRT_IRQ_EXTINT + 152) /* Reserved */ +#define IMXRT_IRQ_RESERVED153 (IMXRT_IRQ_EXTINT + 153) /* Reserved */ +#define IMXRT_IRQ_RESERVED154 (IMXRT_IRQ_EXTINT + 154) /* Reserved */ +#define IMXRT_IRQ_RESERVED155 (IMXRT_IRQ_EXTINT + 155) /* Reserved */ +#define IMXRT_IRQ_RESERVED156 (IMXRT_IRQ_EXTINT + 156) /* Reserved */ +#define IMXRT_IRQ_RESERVED157 (IMXRT_IRQ_EXTINT + 157) /* Reserved */ +#define IMXRT_IRQ_RESERVED158 (IMXRT_IRQ_EXTINT + 158) /* Reserved */ +#define IMXRT_IRQ_RESERVED159 (IMXRT_IRQ_EXTINT + 159) /* Reserved */ + +#define IMXRT_IRQ_NEXTINT 160 + +/* GPIO second level interrupt **********************************************************/ + +#define IMXRT_GPIO_IRQ_FIRST (IMXRT_IRQ_EXTINT + IMXRT_IRQ_NEXTINT) +#define _IMXRT_GPIO1_0_15_BASE IMXRT_GPIO_IRQ_FIRST + +#ifdef CONFIG_IMXRT_GPIO1_0_15_IRQ + /* GPIO1 has dedicated interrupts for pins 0-7 + * REVISIT: I am assuming that you really cannot use the dedicated and the multiplex + * interrupts concurrently. + */ + +# define IMXRT_IRQ_GPIO1_0 (_IMXRT_GPIO1_0_15_BASE + 0) /* GPIO1 pin 8 interrupt */ +# define IMXRT_IRQ_GPIO1_1 (_IMXRT_GPIO1_0_15_BASE + 1) /* GPIO1 pin 8 interrupt */ +# define IMXRT_IRQ_GPIO1_2 (_IMXRT_GPIO1_0_15_BASE + 2) /* GPIO1 pin 8 interrupt */ +# define IMXRT_IRQ_GPIO1_3 (_IMXRT_GPIO1_0_15_BASE + 3) /* GPIO1 pin 8 interrupt */ +# define IMXRT_IRQ_GPIO1_4 (_IMXRT_GPIO1_0_15_BASE + 4) /* GPIO1 pin 8 interrupt */ +# define IMXRT_IRQ_GPIO1_5 (_IMXRT_GPIO1_0_15_BASE + 5) /* GPIO1 pin 8 interrupt */ +# define IMXRT_IRQ_GPIO1_6 (_IMXRT_GPIO1_0_15_BASE + 6) /* GPIO1 pin 8 interrupt */ +# define IMXRT_IRQ_GPIO1_7 (_IMXRT_GPIO1_0_15_BASE + 7) /* GPIO1 pin 8 interrupt */ +# define IMXRT_IRQ_GPIO1_8 (_IMXRT_GPIO1_0_15_BASE + 8) /* GPIO1 pin 8 interrupt */ +# define IMXRT_IRQ_GPIO1_9 (_IMXRT_GPIO1_0_15_BASE + 9) /* GPIO1 pin 9 interrupt */ +# define IMXRT_IRQ_GPIO1_10 (_IMXRT_GPIO1_0_15_BASE + 10) /* GPIO1 pin 10 interrupt */ +# define IMXRT_IRQ_GPIO1_11 (_IMXRT_GPIO1_0_15_BASE + 11) /* GPIO1 pin 11 interrupt */ +# define IMXRT_IRQ_GPIO1_12 (_IMXRT_GPIO1_0_15_BASE + 12) /* GPIO1 pin 12 interrupt */ +# define IMXRT_IRQ_GPIO1_13 (_IMXRT_GPIO1_0_15_BASE + 13) /* GPIO1 pin 13 interrupt */ +# define IMXRT_IRQ_GPIO1_14 (_IMXRT_GPIO1_0_15_BASE + 14) /* GPIO1 pin 14 interrupt */ +# define IMXRT_IRQ_GPIO1_15 (_IMXRT_GPIO1_0_15_BASE + 15) /* GPIO1 pin 15 interrupt */ + +# define _IMXRT_GPIO1_8_15_NIRQS 16 +# define _IMXRT_GPIO1_16_31_BASE (_IMXRT_GPIO1_0_15_BASE + _IMXRT_GPIO1_8_15_NIRQS) +#else +# define _IMXRT_GPIO1_8_15_NIRQS 0 +# define _IMXRT_GPIO1_16_31_BASE _IMXRT_GPIO1_0_15_BASE +#endif + +#ifdef CONFIG_IMXRT_GPIO1_16_31_IRQ +# define IMXRT_IRQ_GPIO1_16 (_IMXRT_GPIO1_16_31_BASE + 0) /* GPIO1 pin 16 interrupt */ +# define IMXRT_IRQ_GPIO1_17 (_IMXRT_GPIO1_16_31_BASE + 1) /* GPIO1 pin 17 interrupt */ +# define IMXRT_IRQ_GPIO1_18 (_IMXRT_GPIO1_16_31_BASE + 2) /* GPIO1 pin 18 interrupt */ +# define IMXRT_IRQ_GPIO1_19 (_IMXRT_GPIO1_16_31_BASE + 3) /* GPIO1 pin 19 interrupt */ +# define IMXRT_IRQ_GPIO1_20 (_IMXRT_GPIO1_16_31_BASE + 4) /* GPIO1 pin 10 interrupt */ +# define IMXRT_IRQ_GPIO1_21 (_IMXRT_GPIO1_16_31_BASE + 5) /* GPIO1 pin 21 interrupt */ +# define IMXRT_IRQ_GPIO1_22 (_IMXRT_GPIO1_16_31_BASE + 6) /* GPIO1 pin 22 interrupt */ +# define IMXRT_IRQ_GPIO1_23 (_IMXRT_GPIO1_16_31_BASE + 7) /* GPIO1 pin 23 interrupt */ +# define IMXRT_IRQ_GPIO1_24 (_IMXRT_GPIO1_16_31_BASE + 8) /* GPIO1 pin 24 interrupt */ +# define IMXRT_IRQ_GPIO1_25 (_IMXRT_GPIO1_16_31_BASE + 9) /* GPIO1 pin 25 interrupt */ +# define IMXRT_IRQ_GPIO1_26 (_IMXRT_GPIO1_16_31_BASE + 10) /* GPIO1 pin 26 interrupt */ +# define IMXRT_IRQ_GPIO1_27 (_IMXRT_GPIO1_16_31_BASE + 11) /* GPIO1 pin 27 interrupt */ +# define IMXRT_IRQ_GPIO1_28 (_IMXRT_GPIO1_16_31_BASE + 12) /* GPIO1 pin 28 interrupt */ +# define IMXRT_IRQ_GPIO1_29 (_IMXRT_GPIO1_16_31_BASE + 13) /* GPIO1 pin 29 interrupt */ +# define IMXRT_IRQ_GPIO1_30 (_IMXRT_GPIO1_16_31_BASE + 14) /* GPIO1 pin 30 interrupt */ +# define IMXRT_IRQ_GPIO1_31 (_IMXRT_GPIO1_16_31_BASE + 15) /* GPIO1 pin 31 interrupt */ + +# define _IMXRT_GPIO1_16_31_NIRQS 16 +# define _IMXRT_GPIO2_0_15_BASE (_IMXRT_GPIO1_16_31_BASE + _IMXRT_GPIO1_16_31_NIRQS) +# define IMXRT_GPIO1_NIRQS (_IMXRT_GPIO1_8_15_NIRQS + _IMXRT_GPIO1_16_31_NIRQS) +#else +# define _IMXRT_GPIO2_0_15_BASE _IMXRT_GPIO1_16_31_BASE +# define IMXRT_GPIO1_NIRQS _IMXRT_GPIO1_8_15_NIRQS +#endif + +#ifdef CONFIG_IMXRT_GPIO2_0_15_IRQ +# define IMXRT_IRQ_GPIO2_16 (_IMXRT_GPIO2_0_15_BASE + 0) /* GPIO2 pin 0 interrupt */ +# define IMXRT_IRQ_GPIO2_17 (_IMXRT_GPIO2_0_15_BASE + 1) /* GPIO2 pin 1 interrupt */ +# define IMXRT_IRQ_GPIO2_18 (_IMXRT_GPIO2_0_15_BASE + 2) /* GPIO2 pin 2 interrupt */ +# define IMXRT_IRQ_GPIO2_19 (_IMXRT_GPIO2_0_15_BASE + 3) /* GPIO2 pin 3 interrupt */ +# define IMXRT_IRQ_GPIO2_20 (_IMXRT_GPIO2_0_15_BASE + 4) /* GPIO2 pin 4 interrupt */ +# define IMXRT_IRQ_GPIO2_21 (_IMXRT_GPIO2_0_15_BASE + 5) /* GPIO2 pin 5 interrupt */ +# define IMXRT_IRQ_GPIO2_22 (_IMXRT_GPIO2_0_15_BASE + 6) /* GPIO2 pin 6 interrupt */ +# define IMXRT_IRQ_GPIO2_23 (_IMXRT_GPIO2_0_15_BASE + 7) /* GPIO2 pin 7 interrupt */ +# define IMXRT_IRQ_GPIO2_24 (_IMXRT_GPIO2_0_15_BASE + 8) /* GPIO2 pin 8 interrupt */ +# define IMXRT_IRQ_GPIO2_25 (_IMXRT_GPIO2_0_15_BASE + 9) /* GPIO2 pin 9 interrupt */ +# define IMXRT_IRQ_GPIO2_26 (_IMXRT_GPIO2_0_15_BASE + 10) /* GPIO2 pin 10 interrupt */ +# define IMXRT_IRQ_GPIO2_27 (_IMXRT_GPIO2_0_15_BASE + 11) /* GPIO2 pin 11 interrupt */ +# define IMXRT_IRQ_GPIO2_28 (_IMXRT_GPIO2_0_15_BASE + 12) /* GPIO2 pin 12 interrupt */ +# define IMXRT_IRQ_GPIO2_29 (_IMXRT_GPIO2_0_15_BASE + 13) /* GPIO2 pin 13 interrupt */ +# define IMXRT_IRQ_GPIO2_30 (_IMXRT_GPIO2_0_15_BASE + 14) /* GPIO2 pin 14 interrupt */ +# define IMXRT_IRQ_GPIO2_31 (_IMXRT_GPIO2_0_15_BASE + 15) /* GPIO2 pin 15 interrupt */ + +# define _IMXRT_GPIO2_0_15_NIRQS 16 +# define _IMXRT_GPIO2_16_31_BASE (_IMXRT_GPIO2_0_15_BASE + _IMXRT_GPIO2_0_15_NIRQS) +#else +# define _IMXRT_GPIO2_0_15_NIRQS 0 +# define _IMXRT_GPIO2_16_31_BASE _IMXRT_GPIO2_0_15_BASE +#endif + +#ifdef CONFIG_IMXRT_GPIO2_16_31_IRQ +# define IMXRT_IRQ_GPIO2_16 (_IMXRT_GPIO2_16_31_BASE + 0) /* GPIO2 pin 16 interrupt */ +# define IMXRT_IRQ_GPIO2_17 (_IMXRT_GPIO2_16_31_BASE + 1) /* GPIO2 pin 17 interrupt */ +# define IMXRT_IRQ_GPIO2_18 (_IMXRT_GPIO2_16_31_BASE + 2) /* GPIO2 pin 18 interrupt */ +# define IMXRT_IRQ_GPIO2_19 (_IMXRT_GPIO2_16_31_BASE + 3) /* GPIO2 pin 19 interrupt */ +# define IMXRT_IRQ_GPIO2_20 (_IMXRT_GPIO2_16_31_BASE + 4) /* GPIO2 pin 20 interrupt */ +# define IMXRT_IRQ_GPIO2_21 (_IMXRT_GPIO2_16_31_BASE + 5) /* GPIO2 pin 21 interrupt */ +# define IMXRT_IRQ_GPIO2_22 (_IMXRT_GPIO2_16_31_BASE + 6) /* GPIO2 pin 22 interrupt */ +# define IMXRT_IRQ_GPIO2_23 (_IMXRT_GPIO2_16_31_BASE + 7) /* GPIO2 pin 23 interrupt */ +# define IMXRT_IRQ_GPIO2_24 (_IMXRT_GPIO2_16_31_BASE + 8) /* GPIO2 pin 24 interrupt */ +# define IMXRT_IRQ_GPIO2_25 (_IMXRT_GPIO2_16_31_BASE + 9) /* GPIO2 pin 25 interrupt */ +# define IMXRT_IRQ_GPIO2_26 (_IMXRT_GPIO2_16_31_BASE + 10) /* GPIO2 pin 26 interrupt */ +# define IMXRT_IRQ_GPIO2_27 (_IMXRT_GPIO2_16_31_BASE + 11) /* GPIO2 pin 27 interrupt */ +# define IMXRT_IRQ_GPIO2_28 (_IMXRT_GPIO2_16_31_BASE + 12) /* GPIO2 pin 28 interrupt */ +# define IMXRT_IRQ_GPIO2_29 (_IMXRT_GPIO2_16_31_BASE + 13) /* GPIO2 pin 29 interrupt */ +# define IMXRT_IRQ_GPIO2_30 (_IMXRT_GPIO2_16_31_BASE + 14) /* GPIO2 pin 30 interrupt */ +# define IMXRT_IRQ_GPIO2_31 (_IMXRT_GPIO2_16_31_BASE + 15) /* GPIO2 pin 31 interrupt */ + +# define _IMXRT_GPIO2_16_31_NIRQS 16 +# define _IMXRT_GPIO3_0_15_BASE (_IMXRT_GPIO2_16_31_BASE + _IMXRT_GPIO2_16_31_NIRQS) +# define IMXRT_GPIO2_NIRQS (_IMXRT_GPIO2_0_15_NIRQS + _IMXRT_GPIO2_16_31_NIRQS) +#else +# define _IMXRT_GPIO3_0_15_BASE _IMXRT_GPIO2_16_31_BASE +# define IMXRT_GPIO2_NIRQS _IMXRT_GPIO2_0_15_NIRQS +#endif + +#ifdef CONFIG_IMXRT_GPIO3_0_15_IRQ +# define IMXRT_IRQ_GPIO3_16 (_IMXRT_GPIO3_0_15_BASE + 0) /* GPIO3 pin 0 interrupt */ +# define IMXRT_IRQ_GPIO3_17 (_IMXRT_GPIO3_0_15_BASE + 1) /* GPIO3 pin 1 interrupt */ +# define IMXRT_IRQ_GPIO3_18 (_IMXRT_GPIO3_0_15_BASE + 2) /* GPIO3 pin 2 interrupt */ +# define IMXRT_IRQ_GPIO3_19 (_IMXRT_GPIO3_0_15_BASE + 3) /* GPIO3 pin 3 interrupt */ +# define IMXRT_IRQ_GPIO3_20 (_IMXRT_GPIO3_0_15_BASE + 4) /* GPIO3 pin 4 interrupt */ +# define IMXRT_IRQ_GPIO3_21 (_IMXRT_GPIO3_0_15_BASE + 5) /* GPIO3 pin 5 interrupt */ +# define IMXRT_IRQ_GPIO3_22 (_IMXRT_GPIO3_0_15_BASE + 6) /* GPIO3 pin 6 interrupt */ +# define IMXRT_IRQ_GPIO3_23 (_IMXRT_GPIO3_0_15_BASE + 7) /* GPIO3 pin 7 interrupt */ +# define IMXRT_IRQ_GPIO3_24 (_IMXRT_GPIO3_0_15_BASE + 8) /* GPIO3 pin 8 interrupt */ +# define IMXRT_IRQ_GPIO3_25 (_IMXRT_GPIO3_0_15_BASE + 9) /* GPIO3 pin 9 interrupt */ +# define IMXRT_IRQ_GPIO3_26 (_IMXRT_GPIO3_0_15_BASE + 10) /* GPIO3 pin 10 interrupt */ +# define IMXRT_IRQ_GPIO3_27 (_IMXRT_GPIO3_0_15_BASE + 11) /* GPIO3 pin 11 interrupt */ +# define IMXRT_IRQ_GPIO3_28 (_IMXRT_GPIO3_0_15_BASE + 12) /* GPIO3 pin 12 interrupt */ +# define IMXRT_IRQ_GPIO3_29 (_IMXRT_GPIO3_0_15_BASE + 13) /* GPIO3 pin 13 interrupt */ +# define IMXRT_IRQ_GPIO3_30 (_IMXRT_GPIO3_0_15_BASE + 14) /* GPIO3 pin 14 interrupt */ +# define IMXRT_IRQ_GPIO3_31 (_IMXRT_GPIO3_0_15_BASE + 15) /* GPIO3 pin 15 interrupt */ + +# define _IMXRT_GPIO3_0_15_NIRQS 16 +# define _IMXRT_GPIO3_16_31_BASE (_IMXRT_GPIO3_0_15_BASE + _IMXRT_GPIO3_0_15_NIRQS) +#else +# define _IMXRT_GPIO3_0_15_NIRQS 0 +# define _IMXRT_GPIO3_16_31_BASE _IMXRT_GPIO3_0_15_BASE +#endif + +#ifdef CONFIG_IMXRT_GPIO3_16_31_IRQ +# define IMXRT_IRQ_GPIO3_16 (_IMXRT_GPIO3_16_31_BASE + 0) /* GPIO3 pin 16 interrupt */ +# define IMXRT_IRQ_GPIO3_17 (_IMXRT_GPIO3_16_31_BASE + 1) /* GPIO3 pin 17 interrupt */ +# define IMXRT_IRQ_GPIO3_18 (_IMXRT_GPIO3_16_31_BASE + 2) /* GPIO3 pin 18 interrupt */ +# define IMXRT_IRQ_GPIO3_19 (_IMXRT_GPIO3_16_31_BASE + 3) /* GPIO3 pin 19 interrupt */ +# define IMXRT_IRQ_GPIO3_20 (_IMXRT_GPIO3_16_31_BASE + 4) /* GPIO3 pin 20 interrupt */ +# define IMXRT_IRQ_GPIO3_21 (_IMXRT_GPIO3_16_31_BASE + 5) /* GPIO3 pin 21 interrupt */ +# define IMXRT_IRQ_GPIO3_22 (_IMXRT_GPIO3_16_31_BASE + 6) /* GPIO3 pin 22 interrupt */ +# define IMXRT_IRQ_GPIO3_23 (_IMXRT_GPIO3_16_31_BASE + 7) /* GPIO3 pin 23 interrupt */ +# define IMXRT_IRQ_GPIO3_24 (_IMXRT_GPIO3_16_31_BASE + 8) /* GPIO3 pin 24 interrupt */ +# define IMXRT_IRQ_GPIO3_25 (_IMXRT_GPIO3_16_31_BASE + 9) /* GPIO3 pin 25 interrupt */ +# define IMXRT_IRQ_GPIO3_26 (_IMXRT_GPIO3_16_31_BASE + 10) /* GPIO3 pin 26 interrupt */ +# define IMXRT_IRQ_GPIO3_27 (_IMXRT_GPIO3_16_31_BASE + 11) /* GPIO3 pin 27 interrupt */ +# define IMXRT_IRQ_GPIO3_28 (_IMXRT_GPIO3_16_31_BASE + 12) /* GPIO3 pin 28 interrupt */ +# define IMXRT_IRQ_GPIO3_29 (_IMXRT_GPIO3_16_31_BASE + 13) /* GPIO3 pin 29 interrupt */ +# define IMXRT_IRQ_GPIO3_30 (_IMXRT_GPIO3_16_31_BASE + 14) /* GPIO3 pin 30 interrupt */ +# define IMXRT_IRQ_GPIO3_31 (_IMXRT_GPIO3_16_31_BASE + 15) /* GPIO3 pin 31 interrupt */ + +# define _IMXRT_GPIO3_16_31_NIRQS 16 +# define _IMXRT_GPIO4_0_15_BASE (_IMXRT_GPIO3_16_31_BASE + _IMXRT_GPIO3_16_31_NIRQS) +# define IMXRT_GPIO3_NIRQS (_IMXRT_GPIO3_0_15_NIRQS + _IMXRT_GPIO3_16_31_NIRQS) +#else +# define _IMXRT_GPIO4_0_15_BASE _IMXRT_GPIO3_16_31_BASE +# define IMXRT_GPIO3_NIRQS _IMXRT_GPIO3_0_15_NIRQS +#endif + +#ifdef CONFIG_IMXRT_GPIO4_0_15_IRQ +# define IMXRT_IRQ_GPIO4_16 (_IMXRT_GPIO4_0_15_BASE + 0) /* GPIO4 pin 0 interrupt */ +# define IMXRT_IRQ_GPIO4_17 (_IMXRT_GPIO4_0_15_BASE + 1) /* GPIO4 pin 1 interrupt */ +# define IMXRT_IRQ_GPIO4_18 (_IMXRT_GPIO4_0_15_BASE + 2) /* GPIO4 pin 2 interrupt */ +# define IMXRT_IRQ_GPIO4_19 (_IMXRT_GPIO4_0_15_BASE + 3) /* GPIO4 pin 3 interrupt */ +# define IMXRT_IRQ_GPIO4_20 (_IMXRT_GPIO4_0_15_BASE + 4) /* GPIO4 pin 4 interrupt */ +# define IMXRT_IRQ_GPIO4_21 (_IMXRT_GPIO4_0_15_BASE + 5) /* GPIO4 pin 5 interrupt */ +# define IMXRT_IRQ_GPIO4_22 (_IMXRT_GPIO4_0_15_BASE + 6) /* GPIO4 pin 6 interrupt */ +# define IMXRT_IRQ_GPIO4_23 (_IMXRT_GPIO4_0_15_BASE + 7) /* GPIO4 pin 7 interrupt */ +# define IMXRT_IRQ_GPIO4_24 (_IMXRT_GPIO4_0_15_BASE + 8) /* GPIO4 pin 8 interrupt */ +# define IMXRT_IRQ_GPIO4_25 (_IMXRT_GPIO4_0_15_BASE + 9) /* GPIO4 pin 9 interrupt */ +# define IMXRT_IRQ_GPIO4_26 (_IMXRT_GPIO4_0_15_BASE + 10) /* GPIO4 pin 10 interrupt */ +# define IMXRT_IRQ_GPIO4_27 (_IMXRT_GPIO4_0_15_BASE + 11) /* GPIO4 pin 11 interrupt */ +# define IMXRT_IRQ_GPIO4_28 (_IMXRT_GPIO4_0_15_BASE + 12) /* GPIO4 pin 12 interrupt */ +# define IMXRT_IRQ_GPIO4_29 (_IMXRT_GPIO4_0_15_BASE + 13) /* GPIO4 pin 13 interrupt */ +# define IMXRT_IRQ_GPIO4_30 (_IMXRT_GPIO4_0_15_BASE + 14) /* GPIO4 pin 14 interrupt */ +# define IMXRT_IRQ_GPIO4_31 (_IMXRT_GPIO4_0_15_BASE + 15) /* GPIO4 pin 15 interrupt */ + +# define _IMXRT_GPIO4_0_15_NIRQS 16 +# define _IMXRT_GPIO4_16_31_BASE (_IMXRT_GPIO4_0_15_BASE + _IMXRT_GPIO4_0_15_NIRQS) +#else +# define _IMXRT_GPIO4_0_15_NIRQS 0 +# define _IMXRT_GPIO4_16_31_BASE _IMXRT_GPIO4_0_15_BASE +#endif + +#ifdef CONFIG_IMXRT_GPIO4_16_31_IRQ +# define IMXRT_IRQ_GPIO4_16 (_IMXRT_GPIO4_16_31_BASE + 0) /* GPIO4 pin 16 interrupt */ +# define IMXRT_IRQ_GPIO4_17 (_IMXRT_GPIO4_16_31_BASE + 1) /* GPIO4 pin 17 interrupt */ +# define IMXRT_IRQ_GPIO4_18 (_IMXRT_GPIO4_16_31_BASE + 2) /* GPIO4 pin 18 interrupt */ +# define IMXRT_IRQ_GPIO4_19 (_IMXRT_GPIO4_16_31_BASE + 3) /* GPIO4 pin 19 interrupt */ +# define IMXRT_IRQ_GPIO4_20 (_IMXRT_GPIO4_16_31_BASE + 4) /* GPIO4 pin 20 interrupt */ +# define IMXRT_IRQ_GPIO4_21 (_IMXRT_GPIO4_16_31_BASE + 5) /* GPIO4 pin 21 interrupt */ +# define IMXRT_IRQ_GPIO4_22 (_IMXRT_GPIO4_16_31_BASE + 6) /* GPIO4 pin 22 interrupt */ +# define IMXRT_IRQ_GPIO4_23 (_IMXRT_GPIO4_16_31_BASE + 7) /* GPIO4 pin 23 interrupt */ +# define IMXRT_IRQ_GPIO4_24 (_IMXRT_GPIO4_16_31_BASE + 8) /* GPIO4 pin 24 interrupt */ +# define IMXRT_IRQ_GPIO4_25 (_IMXRT_GPIO4_16_31_BASE + 9) /* GPIO4 pin 25 interrupt */ +# define IMXRT_IRQ_GPIO4_26 (_IMXRT_GPIO4_16_31_BASE + 10) /* GPIO4 pin 26 interrupt */ +# define IMXRT_IRQ_GPIO4_27 (_IMXRT_GPIO4_16_31_BASE + 11) /* GPIO4 pin 27 interrupt */ +# define IMXRT_IRQ_GPIO4_28 (_IMXRT_GPIO4_16_31_BASE + 12) /* GPIO4 pin 28 interrupt */ +# define IMXRT_IRQ_GPIO4_29 (_IMXRT_GPIO4_16_31_BASE + 13) /* GPIO4 pin 29 interrupt */ +# define IMXRT_IRQ_GPIO4_30 (_IMXRT_GPIO4_16_31_BASE + 14) /* GPIO4 pin 30 interrupt */ +# define IMXRT_IRQ_GPIO4_31 (_IMXRT_GPIO4_16_31_BASE + 15) /* GPIO4 pin 31 interrupt */ + +# define _IMXRT_GPIO4_16_31_NIRQS 16 +# define IMXRT_GPIO4_NIRQS (_IMXRT_GPIO4_0_15_NIRQS + _IMXRT_GPIO4_16_31_NIRQS) +#else +# define IMXRT_GPIO4_NIRQS _IMXRT_GPIO4_0_15_NIRQS +#endif + +#define IMXRT_GPIO_NIRQS (IMXRT_GPIO1_NIRQS + IMXRT_GPIO2_NIRQS + \ + IMXRT_GPIO3_NIRQS + IMXRT_GPIO4_NIRQS) +#define IMXRT_GPIO_IRQ_LAST (_IMXRT_GPIO1_0_15_BASE + IMXRT_GPIO_NIRQS) + +/* Total number of IRQ numbers **********************************************************/ + +#define NR_VECTORS IMXRT_IRQ_NIRQS +#define NR_IRQS (IMXRT_IRQ_EXTINT + IMXRT_IRQ_NEXTINT + IMXRT_GPIO_NIRQS) + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Inline functions + ****************************************************************************************/ + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +/**************************************************************************************** + * Public Function Prototypes + ****************************************************************************************/ + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif +#endif + +#endif /* __ARCH_ARM_INCLUDE_IMXRT_IMXRT105X_IRQ_H */ diff --git a/arch/arm/include/imxrt/irq.h b/arch/arm/include/imxrt/irq.h new file mode 100644 index 00000000000..aa0521bdade --- /dev/null +++ b/arch/arm/include/imxrt/irq.h @@ -0,0 +1,114 @@ +/**************************************************************************************** + * arch/arm/include/imxrt/irq.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +/* This file should never be included directed but, rather, only indirectly through + * nuttx/irq.h + */ + +#ifndef __ARCH_ARM_INCLUDE_IMXRT_IRQ_H +#define __ARCH_ARM_INCLUDE_IMXRT_IRQ_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +#include +#include + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* IRQ numbers. The IRQ number corresponds vector number and hence map directly to + * bits in the NVIC. This does, however, waste several words of memory in the IRQ + * to handle mapping tables. + */ + +/* Common Processor Exceptions (vectors 0-15) */ + +#define IMXRT_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ + /* Vector 0: Reset stack pointer value */ + /* Vector 1: Reset (not handler as an IRQ) */ +#define IMXRT_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ +#define IMXRT_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ +#define IMXRT_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ +#define IMXRT_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ +#define IMXRT_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ + /* Vectors 7-10: Reserved */ +#define IMXRT_IRQ_SVCALL (11) /* Vector 11: SVC call */ +#define IMXRT_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ + /* Vector 13: Reserved */ +#define IMXRT_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ +#define IMXRT_IRQ_SYSTICK (15) /* Vector 15: System tick */ + +/* Chip-Specific External interrupts */ + +#define IMXRT_IRQ_EXTINT (16) /* Vector number of the first external interrupt */ + +#if defined(CONFIG_ARCH_FAMILY_IMXRT105x) +# include +#else +# error Unrecognized i.MX RT architecture +#endif + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************************** + * Public Function Prototypes + ****************************************************************************************/ + +#undef EXTERN +#ifdef __cplusplus +} +#endif +#endif + +#endif /* __ARCH_ARM_INCLUDE_IMXRT_IRQ_H */ diff --git a/arch/arm/src/Makefile b/arch/arm/src/Makefile index 9cdf5898fe0..e6694a6e1c1 100644 --- a/arch/arm/src/Makefile +++ b/arch/arm/src/Makefile @@ -1,7 +1,8 @@ ############################################################################ # arch/arm/src/Makefile # -# Copyright (C) 2007-2009, 2011-2012, 2014-2016 Gregory Nutt. All rights reserved. +# Copyright (C) 2007-2009, 2011-2012, 2014-2016 Gregory Nutt. All rights +# reserved. # Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without diff --git a/arch/arm/src/imxrt/Kconfig b/arch/arm/src/imxrt/Kconfig new file mode 100644 index 00000000000..815902b3b13 --- /dev/null +++ b/arch/arm/src/imxrt/Kconfig @@ -0,0 +1,316 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_CHIP_IMXRT + +comment "i.MX RT Configuration Options" + +choice + prompt "i.MX RT Chip Selection" + default ARCH_CHIP_MIMXRT1052DVL6A + depends on ARCH_CHIP_IMXRT + +config ARCH_CHIP_MIMXRT1051DVL6A + bool "MIMXRT1051DVL6A" + select ARCH_FAMILY_MXRT105xDVL6A + +config ARCH_CHIP_MIMXRT1051CVL5A + bool "MIMXRT1051CVL5A" + select ARCH_FAMILY_IMIMXRT105xCVL5A + +config ARCH_CHIP_MIMXRT1052DVL6A + bool "MIMXRT1052DVL6A" + select ARCH_FAMILY_MXRT105xDVL6A + +config ARCH_CHIP_MIMXRT1052CVL5A + bool "MIMXRT1052DVL6A" + select ARCH_FAMILY_MIMXRT1052CVL5A + +endchoice # i.MX RT Chip Selection + +# i.MX RT Families + +config ARCH_FAMILY_MXRT105xDVL6A + bool + default n + select ARCH_FAMILY_IMXRT105x + ---help--- + i.MX RT1050 Crossover Processors for Consumer Products + +config ARCH_FAMILY_MIMXRT1052CVL5A + bool + default n + select ARCH_FAMILY_IMXRT105x + ---help--- + i.MX RT1050 Crossover Processors for Industrial Products + +config ARCH_FAMILY_IMXRT105x + bool + default n + +# Peripheral support + +config IMXRT_HAVE_LPUART + bool + default n + +menu "i.MX RT Peripheral Selection" + +menu "FlexIO Peripherals" + +endmenu # FlexIO Peripherals + +menu "LPUART Peripherals" + +config IMXRT_LPUART1 + bool "LPUART1" + default n + select LPUART1_SERIALDRIVER + select IMXRT_HAVE_LPUART + +config IMXRT_LPUART2 + bool "LPUART2" + default n + select LPUART2_SERIALDRIVER + select IMXRT_HAVE_LPUART + +config IMXRT_LPUART3 + bool "LPUART3" + default n + select LPUART3_SERIALDRIVER + select IMXRT_HAVE_LPUART + +config IMXRT_LPUART4 + bool "LPUART4" + default n + select LPUART4_SERIALDRIVER + select IMXRT_HAVE_LPUART + +config IMXRT_LPUART5 + bool "LPUART5" + default n + select LPUART5_SERIALDRIVER + select IMXRT_HAVE_LPUART + +config IMXRT_LPUART6 + bool "LPUART6" + default n + select LPUART6_SERIALDRIVER + select IMXRT_HAVE_LPUART + +config IMXRT_LPUART7 + bool "LPUART7" + default n + select LPUART7_SERIALDRIVER + select IMXRT_HAVE_LPUART + +config IMXRT_LPUART8 + bool "LPUART8" + default n + select LPUART8_SERIALDRIVER + select IMXRT_HAVE_LPUART + +endmenu # LPUART Peripherals + +config IMXRT_SEMC + bool "Smart External Memory Controller (SEMC)" + default n + +endmenu # i.MX RT Peripheral Selection + +menuconfig IMXRT_GPIO_IRQ + bool "GPIO Interrupt Support" + default n + +if IMXRT_GPIO_IRQ + +config IMXRT_GPIO1_0_15_IRQ + bool "GPIO1 Pins 8-15 interrupts" + default n + +config IMXRT_GPIO1_16_31_IRQ + bool "GPIO1 Pins 16-31 interrupts" + default n + +config IMXRT_GPIO2_0_15_IRQ + bool "GPIO2 Pins 0-15 interrupts" + default n + +config IMXRT_GPIO2_16_31_IRQ + bool "GPIO2 Pins 16-31 interrupts" + default n + +config IMXRT_GPIO3_0_15_IRQ + bool "GPIO3 Pins 0-15 interrupts" + default n + +config IMXRT_GPIO3_16_31_IRQ + bool "GPIO3 Pins 16-31 interrupts" + default n + +config IMXRT_GPIO4_0_15_IRQ + bool "GPIO4 Pins 0-15 interrupts" + default n + +config IMXRT_GPIO4_16_31_IRQ + bool "GPIO4 Pins 16-31 interrupts" + default n + +endif # IMXRT_GPIO_IRQ + +menu "Memory Configuration" + +config IMXRT_DTCM + bool "Enable DTCM" + default n + depends on !IMXRT_OCRAM_PRIMARY && EXPERIMENTAL + +config IMXRT_ITCM + bool "Enable ITCM" + default n + depends on !IMXRT_OCRAM_PRIMARY && EXPERIMENTAL + +config IMXRT_SEMC_SDRAM + bool "External SDRAM installed" + default n + depends on IMXRT_SEMC + +if IMXRT_SEMC_SDRAM + +config IMXRT_SDRAM_START + hex "SDRAM start address" + default 0x10000000 + +config IMXRT_SDRAM_SIZE + int "SDRAM size (bytes)" + default 268435456 + +endif # IMXRT_SEMC_SDRAM + +config IMXRT_SEMC_SRAM + bool "External SRAM installed" + default n + depends on IMXRT_SEMC + +if IMXRT_SEMC_SRAM + +config IMXRT_SRAM_START + hex "SRAM start address" + default 0x10000000 + +config IMXRT_SRAM_SIZE + int "SRAM size (bytes)" + default 268435456 + +endif # IMXRT_SRAM_SIZE + +config IMXRT_SEMC_NOR + bool "External NOR FLASH installed" + default n + depends on IMXRT_SEMC + +choice + prompt "i.MX RT Boot Configuration" + default IMXRT_BOOT_NOR if IMXRT_SEMC_NOR + default IMXRT_BOOT_SDRAM if IMXRT_SEMC_SDRAM && !IMXRT_SEMC_NOR + default IMXRT_BOOT_SRAM if IMXRT_SEMC_SRAM && !IMXRT_SEMC_SDRAM && !IMXRT_SEMC_NOR + default IMXRT_BOOT_OCRAM if !IMXRT_SEMC_SRAM && !IMXRT_SEMC_SDRAM && !IMXRT_SEMC_NOR + ---help--- + The startup code needs to know if the code is running from internal + OCRAM, external SDRAM, external NOR, or external SDRAM in order to + initialize properly. Note that the boot device is not known for + cases where the code is copied into RAM by a bootloader. + +config IMXRT_BOOT_OCRAM + bool "Running from internal OCRAM" + select BOOT_RUNFROMISRAM + +config IMXRT_BOOT_SDRAM + bool "Running from external SDRAM" + select BOOT_RUNFROMSDRAM + depends on IMXRT_SEMC_SDRAM + +config IMXRT_BOOT_NOR + bool "Running from external NOR FLASH" + select BOOT_RUNFROMFLASH + depends on IMXRT_SEMC_NOR + +config IMXRT_BOOT_SRAM + bool "Running from external SRAM" + select BOOT_RUNFROMEXTSRAM + depends on IMXRT_SEMC_SRAM + +endchoice # i.MX RT Boot Configuration + +choice + prompt "i.MX6 Primary RAM" + default IMXRT_OCRAM_PRIMARY + ---help--- + The primary RAM is the RAM that contains the system BLOB's .data and + .bss. The unused portion of the primary RAM will automatically be + added to the system heap. + +config IMXRT_OCRAM_PRIMARY + bool "Internal OCRAM primary" + +config IMXRT_SDRAM_PRIMARY + bool "External SDRAM primary" + depends on IMXRT_SEMC_SDRAM + +config IMXRT_SRAM_PRIMARY + bool "External SRAM primary" + depends on IMXRT_SEMC_SRAM + +endchoice # i.MX6 Primary RAM + +menu "i.MX RT Heap Configuration" + +config IMXRT_OCRAM_HEAP + bool "Add OCRAM to heap" + depends on !IMXRT_OCRAM_PRIMARY + ---help--- + Select to add the entire OCRAM to the heap + +config IMXRT_SDRAM_HEAP + bool "Add SDRAM to heap" + depends on IMXRT_SEMC_SDRAM && !IMXRT_SDRAM_PRIMARY + ---help--- + Add a region of SDRAM to the heap. A region of SDRAM will be added + to the heap that starts at (CONFIG_IMXRT_SDRAM_START + + CONFIG_IMXRT_SDRAM_HEAPOFFSET) and extends up to + (CONFIG_IMXRT_SDRAM_START + CONFIG_IMXRT_SDRAM_SIZE). Note that the + START is the actual start of SDRAM but SIZE is not necessarily the + actual SIZE. + +config IMXRT_SDRAM_HEAPOFFSET + hex "SDRAM heap offset" + default 0x0 + depends on IMXRT_SDRAM_HEAP + ---help--- + Used to reserve memory at the beginning of SDRAM for, as an example, + a framebuffer. + +config IMXRT_SRAM_HEAP + bool "Add SRAM to heap" + depends on IMXRT_SEMC_SRAM && !IMXRT_SRAM_PRIMARY + ---help--- + Add a region of SRAM to the heap. A region of SDRAM will be added + to the heap that starts at (CONFIG_IMXRT_SRAM_START + + CONFIG_IMXRT_SRAM_HEAPOFFSET) and extends up to + (CONFIG_IMXRT_SRAM_START + CONFIG_IMXRT_SRAM_SIZE). Note that the + START is the actual start of SRAM but SIZE is not necessarily the + actual SIZE. + +config IMXRT_SRAM_HEAPOFFSET + hex "SRAM heap offset" + default 0x0 + depends on IMXRT_SRAM_HEAP + ---help--- + Used to reserve memory at the beginning of SRAM for, as an example, + a framebuffer. + +endmenu # i.MX6 Primary RAM +endmenu # Memory Configuration +endif # ARCH_CHIP_IMXRT diff --git a/arch/arm/src/imxrt/Make.defs b/arch/arm/src/imxrt/Make.defs new file mode 100644 index 00000000000..72d3e0a9bd0 --- /dev/null +++ b/arch/arm/src/imxrt/Make.defs @@ -0,0 +1,108 @@ +############################################################################ +# arch/arm/src/imxrt/Make.defs +# +# Copyright (C) 2018 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +HEAD_ASRC = + +# Common ARM and Cortex-M7 files + +CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S +CMN_ASRCS += up_testset.S up_fetchadd.S vfork.S + +CMN_CSRCS = up_assert.c up_blocktask.c up_copyfullstate.c +CMN_CSRCS += up_createstack.c up_mdelay.c up_udelay.c up_exit.c +CMN_CSRCS += up_initialize.c up_initialstate.c up_interruptcontext.c +CMN_CSRCS += up_memfault.c up_modifyreg8.c up_modifyreg16.c up_modifyreg32.c +CMN_CSRCS += up_releasepending.c up_releasestack.c up_reprioritizertr.c +CMN_CSRCS += up_schedulesigaction.c up_sigdeliver.c up_stackframe.c +CMN_CSRCS += up_unblocktask.c up_usestack.c up_doirq.c up_hardfault.c +CMN_CSRCS += up_svcall.c up_vfork.c + +# Configuration-dependent common files + +ifeq ($(CONFIG_ARMV7M_LAZYFPU),y) +CMN_ASRCS += up_lazyexception.S +else +CMN_ASRCS += up_exception.S +endif +CMN_CSRCS += up_vectors.c + +ifeq ($(CONFIG_ARCH_RAMVECTORS),y) +CMN_CSRCS += up_ramvec_initialize.c up_ramvec_attach.c +endif + +ifeq ($(CONFIG_BUILD_PROTECTED),y) +CMN_CSRCS += up_mpu.c up_task_start.c up_pthread_start.c +ifneq ($(CONFIG_DISABLE_SIGNALS),y) +CMN_CSRCS += up_signal_dispatch.c +CMN_UASRCS += up_signal_handler.S +endif +endif + +ifeq ($(CONFIG_STACK_COLORATION),y) +CMN_CSRCS += up_checkstack.c +endif + +ifeq ($(CONFIG_ARCH_FPU),y) +CMN_ASRCS += up_fpu.S +ifneq ($(CONFIG_ARMV7M_CMNVECTOR),y) +CMN_CSRCS += up_copyarmstate.c +else ifeq ($(CONFIG_ARMV7M_LAZYFPU),y) +CMN_CSRCS += up_copyarmstate.c +endif +endif + +# Required i.MX RT files + +CHIP_ASRCS = +CHIP_CSRCS = imxrt_allocateheap.c imxrt_start.c imxrt_clockconfig.c imxrt_idle.c +CHIP_CSRCS += imxrt_irq.c imxrt_clrpend.c imxrt_gpio.c imxrt_wdog.c imxrt_iomuxc.c +CHIP_CSRCS += imxrt_serial.c imxrt_lowputc.c + +# Configuration-dependent i.MX RT files + +ifneq ($(CONFIG_SCHED_TICKLESS),y) +CHIP_CSRCS += imxrt_timerisr.c +endif + +ifeq ($(CONFIG_IMXRT_GPIO_IRQ),y) +CHIP_CSRCS += imxrt_gpioirq.c +endif + +ifeq ($(CONFIG_ARM_MPU),y) +CHIP_CSRCS += imxrt_mpuinit.c +ifeq ($(CONFIG_BUILD_PROTECTED),y) +CHIP_CSRCS += imxrt_userspace.c +endif +endif diff --git a/arch/arm/src/imxrt/chip.h b/arch/arm/src/imxrt/chip.h new file mode 100644 index 00000000000..71f444f4645 --- /dev/null +++ b/arch/arm/src/imxrt/chip.h @@ -0,0 +1,81 @@ +/************************************************************************************ + * arch/arm/src/imxrt/chip.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_H +#define __ARCH_ARM_SRC_IMXRT_CHIP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/* Include the memory map and the chip definitions file. Other chip hardware files + * should then include this file for the proper setup. + */ + +#include +#include +#include "chip/imxrt_memorymap.h" + +/* If the common ARMv7-M vector handling logic is used, then it expects the following + * definition in this file that provides the number of supported vectors external + * interrupts. + */ + +#define ARMV7M_PERIPHERAL_INTERRUPTS IMXRT_IRQ_NEXTINT + +/* Cache line sizes (in bytes)for the SAMV71 */ + +#define ARMV7M_DCACHE_LINESIZE 32 /* 32 bytes (8 words) */ +#define ARMV7M_ICACHE_LINESIZE 32 /* 32 bytes (8 words) */ + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_H */ diff --git a/arch/arm/src/imxrt/chip/imxrt105x_memorymap.h b/arch/arm/src/imxrt/chip/imxrt105x_memorymap.h new file mode 100644 index 00000000000..2b6278a3c23 --- /dev/null +++ b/arch/arm/src/imxrt/chip/imxrt105x_memorymap.h @@ -0,0 +1,259 @@ +/************************************************************************************ + * arch/arm/src/imxrt/chip/imxrt105x_memorymap.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT105X_MEMORYMAP_H +#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT105X_MEMORYMAP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* System memory map */ + +#define IMXRT_ITCM_BASE 0x00000000 /* 512KB ITCM */ + /* 0x00080000 512KB ITCM Reserved */ + /* 0x00100000 1MB ITCM Reserved */ +#define IMXRT_ROMCP_BASE 0x00200000 /* 96KB ROMCP */ + /* 0x00218000 416KB ROMCP Reserved */ + /* 0x00280000 1536KB Reserved */ + /* 0x00400000 128MB Reserved */ +#define IMXRT_FLEXSPI_BASE 0x08000000 /* 128MB FlexSPI (Aliased) */ +#define IMXRT_SEMCA_BASE 0x10000000 /* 256MB SEMC (Aliased) */ +#define IMXRT_DTCM_BASE 0x20000000 /* 512KB DTCM */ + /* 0x20080000 512KB DTCM Reserved */ + /* 0x20100000 1MB Reserved */ +#define IMXRT_OCRAM_BASE 0x20200000 /* 512KB OCRAM */ + /* 0x20280000 1536KB OCRAM Reserved */ + /* 0x20400000 252MB Reserved */ + /* 0x30000000 256MB Reserved */ +#define IMXRT_AIPS1_BASE 0x40000000 /* 1MB AIPS-1 */ +#define IMXRT_AIPS2_BASE 0x40100000 /* 1MB AIPS-2 */ +#define IMXRT_AIPS3_BASE 0x40200000 /* 1MB AIPS-3 */ +#define IMXRT_AIPS4_BASE 0x40300000 /* 1MB AIPS-4 */ + /* 40400000 12MB Reserved */ +#define IMXRT_MAINCNF_BASE 0x41000000 /* 1MB "main" configuration port */ +#define IMXRT_MCNF_BASE 0x41100000 /* 1MB "m" configuration port */ + /* 41200000 1MB Reserved for "per" GPV */ + /* 41300000 1MB Reserved for "ems" GPV */ +#define IMXRT_CPUCNF_BASE 0x41400000 /* 1MB "cpu" configuration port */ + /* 0x41500000 1MB GPV Reserved */ + /* 0x41600000 1MB GPV Reserved */ + /* 0x41700000 1MB GPV Reserved */ + /* 0x41800000 8MB Reserved */ + /* 0x42000000 32MB Reserved */ + /* 0x44000000 64MB Reserved */ + /* 0x48000000 384MB Reserved */ +#define IMXRT_FLEXCIPHER_BASE 0x60000000 /* 504MB FlexSPI/ FlexSPI ciphertext */ +#define IMXRT_FLEXSPITX_BASE 0x7f800000 /* 4MB FlexSPI TX FIFO */ +#define IMXRT_FLEXSPIRX_BASE 0x7fc00000 /* 4MB FlexSPI RX FIFO */ +#define IMXRT_EXTMEM_BASE 0x80000000 /* 1.5GB SEMC external memories shared memory space */ +#define IMXRT_CM7_BASE 0xe0000000 /* 1MB CM7 PPB */ + /* 0xe0100000 511MB Reserved */ + +/* AIPS-1 memory map */ + + /* 0x40000000 256KB Reserved */ + /* 0x40040000 240KB Reserved */ +#define IMXRT_AIPS1CNF_BASE 0x4007c000 /* 6KB AIPS-1 Configuration */ +#define IMXRT_DCDC_BASE 0x40080000 /* 16KB DCDC */ +#define IMXRT_PIT_BASE 0x40084000 /* 16KB PIT */ + /* 0x40088000 16KB Reserved */ + /* 0x4008c000 16KB Reserved */ +#define IMXRT_MTR_BASE 0x40090000 /* 16KB MTR */ +#define IMXRT_ACMP_BASE 0x40094000 /* 16KB ACMP */ + /* 0x40098000 16KB Reserved */ + /* 0x4009c000 16KB Reserved */ + /* 0x400a0000 16KB Reserved */ +#define IMXRT_IOMUXCSNVSGPR_BASE 0x400a4000 /* 16KB IOMUXC_SNVS_GPR */ +#define IMXRT_IOMUXCSNVS_BASE 0x400a8000 /* 16KB IOMUXC_SNVS */ +#define IMXRT_IOMUXCGPR_BASE 0x400ac000 /* 16KB IOMUXC_GPR */ +#define IMXRT_FLEXRAM_BASE 0x400b0000 /* 16KB CM7_MX6RT(FLEXRAM) */ +#define IMXRT_EWM_BASE 0x400b4000 /* 16KB EWM */ +#define IMXRT_WDOG1_BASE 0x400b8000 /* 16KB WDOG1 */ +#define IMXRT_WDOG3_BASE 0x400bc000 /* 16KB WDOG3 */ +#define IMXRT_GPIO5_BASE 0x400c0000 /* 16KB GPIO5 */ +#define IMXRT_ADC1_BASE 0x400c4000 /* 16KB ADC1 */ +#define IMXRT_ADC2_BASE 0x400c8000 /* 16KB ADC2 */ +#define IMXRT_TRNG_BASE 0x400cc000 /* 16KB TRNG */ +#define IMXRT_WDOG2_BASE 0x400d0000 /* 16KB WDOG2 */ +#define IMXRT_SNVSHP_BASE 0x400d4000 /* 16KB SNVS_HP */ +#define IMXRT_ANATOP_BASE 0x400d8000 /* 16KB ANATOP */ +#define IMXRT_CSU_BASE 0x400dc000 /* 16KB CSU */ + /* 0x400e0000 16KB Reserved */ + /* 0x400e4000 16KB Reserved */ +#define IMXRT_EDMA_BASE 0x400e8000 /* 16KB EDMA */ +#define IMXRT_DMACHMUX_BASE 0x400ec000 /* 16KB DMA_CH_MUX */ + /* 400f0000 16KB Reserved */ +#define IMXRT_GPC_BASE 0x400f4000 /* 16KB GPC */ +#define IMXRT_SRC_BASE 0x400f8000 /* 16KB SRC */ +#define IMXRT_CCM_BASE 0x400fc000 /* 16KB CCM */ + +/* AIPS-2 memory map */ + + /* 0x40100000 256KB Reserved */ + /* 0x40140000 240KB Reserved */ +#define IMXRT_AIPS2CNF_BASE 0x4017c000 /* 16KB AIPS-2 Configuration */ +#define IMXRT_ROMCPC_BASE 0x40180000 /* 16KB ROMCP controller*/ +#define IMXRT_LPUART1_BASE 0x40184000 /* 16KB LPUART1 */ +#define IMXRT_LPUART2_BASE 0x40188000 /* 16KB LPUART2 */ +#define IMXRT_LPUART3_BASE 0x4018c000 /* 16KB LPUART3 */ +#define IMXRT_LPUART4_BASE 0x40190000 /* 16KB LPUART4 */ +#define IMXRT_LPUART5_BASE 0x40194000 /* 16KB LPUART5 */ +#define IMXRT_LPUART6_BASE 0x40198000 /* 16KB LPUART6 */ +#define IMXRT_LPUART7_BASE 0x4019c000 /* 16KB LPUART7 */ +#define IMXRT_LPUART8_BASE 0x401a0000 /* 16KB LPUART8 */ + /* 0x401a4000 16KB Reserved */ + /* 0x401a8000 16KB Reserved */ +#define IMXRT_FLEXIO1_BASE 0x401ac000 /* 16KB FlexIO1 */ +#define IMXRT_FLEXIO2_BASE 0x401b0000 /* 16KB FlexIO2 */ + /* 0x401b4000 16KB Reserved */ +#define IMXRT_GPIO_BASE(n) (0x401b8000 + ((n) << 14)) +#define IMXRT_GPIO1_BASE 0x401b8000 /* 16KB GPIO1 */ +#define IMXRT_GPIO2_BASE 0x401bc000 /* 16KB GPIO2 */ +#define IMXRT_GPIO3_BASE 0x401c0000 /* 16KB GPIO3 */ +#define IMXRT_GPIO4_BASE 0x401c4000 /* 16KB GPIO4 */ + /* 0x401c8000 16KB Reserved */ + /* 0x401cc000 16KB Reserved */ +#define IMXRT_CAN1_BASE 0x401d0000 /* 16KB CAN1 */ +#define IMXRT_CAN2_BASE 0x401d4000 /* 16KB CAN2 */ + /* 0x401d8000 16KB Reserved */ +#define IMXRT_QTIMER1_BASE 0x401dc000 /* 16KB QTimer1 */ +#define IMXRT_QTIMER2_BASE 0x401e0000 /* 16KB QTimer2 */ +#define IMXRT_QTIMER3_BASE 0x401e4000 /* 16KB QTimer3 */ +#define IMXRT_QTIMER4_BASE 0x401e8000 /* 16KB QTimer4 */ +#define IMXRT_GPT1_BASE 0x401ec000 /* 16KB GPT1 */ +#define IMXRT_GPT2_BASE 0x401f0000 /* 16KB GPT2 */ +#define IMXRT_OCOTP_BASE 0x401f4000 /* 16KB OCOTP */ +#define IMXRT_IOMUXC_BASE 0x401f8000 /* 16KB IOMUXC */ +#define IMXRT_KPP_BASE 0x401fc000 /* 16KB KPP */ + +/* AIPS-3 memory map */ + + /* 0x40200000 256KB Reserved */ + /* 0x40240000 240KB Reserved */ +#define IMXRT_AIOS3CNF_BASE 0x4027c000 /* 16KB AIPS-3 Configuration */ + /* 0x40280000 16KB Reserved */ + /* 0x40284000 16KB Reserved */ + /* 0x40288000 16KB Reserved */ + /* 0x4028c000 16KB Reserved */ + /* 0x40290000 16KB Reserved */ + /* 0x40294000 16KB Reserved */ + /* 0x40298000 16KB Reserved */ + /* 0x4029c000 16KB Reserved */ + /* 0x402a0000 16KB Reserved */ + /* 0x402a4000 16KB Reserved */ +#define IMXRT_FLEXSPIC_BASE 0x402a8000 /* 16KB FlexSPI controller */ + /* 0x402ac000 16KB Reserved */ + /* 0x402b0000 16KB Reserved */ +#define IMXRT_PXP_BASE 0x402b4000 /* 16KB PXP */ +#define IMXRT_LCDIF_BASE 0x402b8000 /* 16KB LCDIF */ +#define IMXRT_CSI_BASE 0x402bc000 /* 16KB CSI */ +#define IMXRT_USDHC1_BASE 0x402c0000 /* 16KB USDHC1 */ +#define IMXRT_USDHC2_BASE 0x402c4000 /* 16KB USDHC2 */ + /* 0x402c8000 16KB Reserved */ + /* 0x402cc000 16KB Reserved */ + /* 0x402d0000 16KB Reserved */ + /* 0x402d4000 16KB Reserved */ +#define IMXRT_ENET_BASE 0x402d8000 /* 16KB ENET */ +#define IMXRT_USBPL301_BASE 0x402dc000 /* 16KB USB(PL301) */ +#define IMXRT_USB_BASE 0x402e0000 /* 16KB USB(USB) */ + /* 0x402e4000 16KB Reserved */ + /* 0x402e8000 16KB Reserved */ + /* 0x402ec000 16KB Reserved */ +#define IMXRT_SEMC_BASE 0x402f0000 /* 16KB SEMC */ + /* 0x402f4000 16KB Reserved */ + /* 0x402f8000 16KB Reserved */ +#define IMXRT_DCP_BASE 0x402fc000 /* 16KB DCP */ + +/* AIPS-4 memory map */ + + /* 0x40300000 256KB Reserved */ + /* 0x40340000 240KB Reserved */ +#define IMXRT_AIPS4CNF_BASE 0x4037c000 /* 16KB AIPS-4 Configuration */ +#define IMXRT_SPDIF_BASE 0x40380000 /* 16KB SPDIF */ +#define IMXRT_SAI1_BASE 0x40384000 /* 16KB SAI1 */ +#define IMXRT_SAI2_BASE 0x40388000 /* 16KB SAI2 */ +#define IMXRT_SAI3_BASE 0x4038c000 /* 16KB SAI3 */ + /* 0x40390000 16KB Reserved */ +#define IMXRT_LPSPI1_BASE 0x40394000 /* 16KB LPSPI1 */ +#define IMXRT_LPSPI2_BASE 0x40398000 /* 16KB LPSPI2 */ +#define IMXRT_LPSPI3_BASE 0x4039c000 /* 16KB LPSPI3 */ +#define IMXRT_LPSPI4_BASE 0x403a0000 /* 16KB LPSPI4 */ + /* 0x403a4000 16KB Reserved */ + /* 0x403a8000 16KB Reserved */ + /* 0x403ac000 16KB Reserved */ +#define IMXRT_ADCETC_BASE 0x403b0000 /* 16KB ADC_ETC */ +#define IMXRT_AOI1_BASE 0x403b4000 /* 16KB AOI1 */ +#define IMXRT_AOI2_BASE 0x403b8000 /* 16KB AOI2 */ +#define IMXRT_XBAR1_BASE 0x403bc000 /* 16KB XBAR1 */ +#define IMXRT_XBAR2_BASE 0x403c0000 /* 16KB XBAR2 */ +#define IMXRT_XBAR3_BASE 0x403c4000 /* 16KB XBAR3 */ +#define IMXRT_ENC1_BASE 0x403c8000 /* 16KB ENC1 */ +#define IMXRT_ENC2_BASE 0x403cc000 /* 16KB ENC2 */ +#define IMXRT_ENC3_BASE 0x403d0000 /* 16KB ENC3 */ +#define IMXRT_ENC4_BASE 0x403d4000 /* 16KB ENC4 */ + /* 0x403d8000 16KB Reserved */ +#define IMXRT_FLEXPWM1_BASE 0x403dc000 /* 16KB FLEXPWM1 */ +#define IMXRT_FLEXPWM2_BASE 0x403e0000 /* 16KB FLEXPWM2 */ +#define IMXRT_FLEXPWM3_BASE 0x403e4000 /* 16KB FLEXPWM3 */ +#define IMXRT_FLEXPWM4_BASE 0x403e8000 /* 16KB FLEXPWM4 */ +#define IMXRT_BEE_BASE 0x403ec000 /* 16KB BEE */ +#define IMXRT_LPI2C1_BASE 0x403f0000 /* 16KB */ +#define IMXRT_LPI2C2_BASE 0x403f4000 /* 16KB LPI2C2 */ +#define IMXRT_LPI2C3_BASE 0x403f8000 /* 16KB LPI2C3 */ +#define IMXRT_LPI2C4_BASE 0x403fc000 /* 16KB LPI2C4 */ + +/* PPB memory map */ + +#define IMXRT_TPIU_BASE 0xe0040000 /* 4KB TPIU */ +#define IMXRT_ETM_BASE 0xe0041000 /* 4KB ETM */ +#define IMXRT_CTI_BASE 0xe0042000 /* 4KB CTI */ +#define IMXRT_TSGEN_BASE 0xe0043000 /* 4KB TSGEN */ +#define IMXRT_PPBRES_BASE 0xe0044000 /* 4KB PPB RES */ + /* 0xe0045000 236KB PPB Reserved */ +#define IMXRT_MCM_BASE 0xe0080000 /* 4KB MCM */ + /* 0xe0081000 444KB PPB Reserved */ + /* 0xe00f0000 52KB PPB Reserved */ +#define IMXRT_SYSROM_BASE 0xe00fd000 /* 4KB SYS ROM */ +#define IMXRT_PROCROM_BASE 0xe00fe000 /* 4KB Processor ROM */ +#define IMXRT_PPBROM_BASE 0xe00ff000 /* 4KB PPB ROM */ + +#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT105X_MEMORYMAP_H */ diff --git a/arch/arm/src/imxrt/chip/imxrt_ccm.h b/arch/arm/src/imxrt/chip/imxrt_ccm.h new file mode 100644 index 00000000000..17210052f29 --- /dev/null +++ b/arch/arm/src/imxrt/chip/imxrt_ccm.h @@ -0,0 +1,1010 @@ +/************************************************************************************************************ + * arch/arm/src/imxrt/imxrt_ccm.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Janne Rosberg + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_CCM_H +#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_CCM_H + +/************************************************************************************************************ + * Included Files + ************************************************************************************************************/ + +#include +#include "chip/imxrt_memorymap.h" + +/************************************************************************************************************ + * Pre-processor Definitions + ************************************************************************************************************/ + +/* Register offsets *****************************************************************************************/ + +#define IMXRT_CCM_CCR_OFFSET 0x0000 /* CCM Control Register */ + /* 0x0004 Reserved */ +#define IMXRT_CCM_CSR_OFFSET 0x0008 /* CCM Status Register */ +#define IMXRT_CCM_CCSR_OFFSET 0x000c /* CCM Clock Switcher Register */ +#define IMXRT_CCM_CACRR_OFFSET 0x0010 /* CCM Arm Clock Root Register */ +#define IMXRT_CCM_CBCDR_OFFSET 0x0014 /* CCM Bus Clock Divider Register */ +#define IMXRT_CCM_CBCMR_OFFSET 0x0018 /* CCM Bus Clock Multiplexer Register */ +#define IMXRT_CCM_CSCMR1_OFFSET 0x001c /* CCM Serial Clock Multiplexer Register 1 */ +#define IMXRT_CCM_CSCMR2_OFFSET 0x0020 /* CCM Serial Clock Multiplexer Register 2 */ +#define IMXRT_CCM_CSCDR1_OFFSET 0x0024 /* CCM Serial Clock Divider Register 1 */ +#define IMXRT_CCM_CS1CDR_OFFSET 0x0028 /* CCM Clock Divider Register */ +#define IMXRT_CCM_CS2CDR_OFFSET 0x002c /* CCM Clock Divider Register */ +#define IMXRT_CCM_CDCDR_OFFSET 0x0030 /* CCM D1 Clock Divider Register */ + /* 0x0034 Reserved */ +#define IMXRT_CCM_CSCDR2_OFFSET 0x0038 /* CCM Serial Clock Divider Register 2 */ +#define IMXRT_CCM_CSCDR3_OFFSET 0x003c /* CCM Serial Clock Divider Register 3 */ + /* 0x0040 Reserved */ + /* 0x0044 Reserved */ +#define IMXRT_CCM_CDHIPR_OFFSET 0x0048 /* CCM Divider Handshake In-Process Register */ + /* 0x004c Reserved */ + /* 0x0050 Reserved */ +#define IMXRT_CCM_CLPCR_OFFSET 0x0054 /* CCM Low Power Control Register */ + +#define IMXRT_CCM_CISR_OFFSET 0x0058 /* CCM Interrupt Status Register */ +#define IMXRT_CCM_CIMR_OFFSET 0x005c /* CCM Interrupt Mask Register */ +#define IMXRT_CCM_CCOSR_OFFSET 0x0060 /* CCM Clock Output Source Register */ +#define IMXRT_CCM_CGPR_OFFSET 0x0064 /* CCM General Purpose Register */ +#define IMXRT_CCM_CCGR0_OFFSET 0x0068 /* CCM Clock Gating Register 0 */ +#define IMXRT_CCM_CCGR1_OFFSET 0x006c /* CCM Clock Gating Register 1 */ +#define IMXRT_CCM_CCGR2_OFFSET 0x0070 /* CCM Clock Gating Register 2 */ +#define IMXRT_CCM_CCGR3_OFFSET 0x0074 /* CCM Clock Gating Register 3 */ +#define IMXRT_CCM_CCGR4_OFFSET 0x0078 /* CCM Clock Gating Register 4 */ +#define IMXRT_CCM_CCGR5_OFFSET 0x007c /* CCM Clock Gating Register 5 */ +#define IMXRT_CCM_CCGR6_OFFSET 0x0080 /* CCM Clock Gating Register 6 */ + /* 0x0084 Reserved */ +#define IMXRT_CCM_CMEOR_OFFSET 0x0088 /* CCM Module Enable Overide Register */ + +/* Analog */ + +#define IMXRT_CCM_ANALOG_PLL_ARM_OFFSET 0x0000 /* Analog ARM PLL control Register */ +#define IMXRT_CCM_ANALOG_PLL_USB1_OFFSET 0x0010 /* Analog USB1 480MHz PLL Control Register */ +#define IMXRT_CCM_ANALOG_PLL_USB2_OFFSET 0x0020 /* Analog USB2 480MHz PLL Control Register */ +#define IMXRT_CCM_ANALOG_PLL_SYS_OFFSET 0x0030 /* Analog System PLL Control Register */ +#define IMXRT_CCM_ANALOG_PLL_SYS_SS_OFFSET 0x0040 /* 528MHz System PLL Spread Spectrum Register */ +#define IMXRT_CCM_ANALOG_PLL_SYS_NUM_OFFSET 0x0050 /* Numerator of 528MHz System PLL Fractional Loop Divider */ +#define IMXRT_CCM_ANALOG_PLL_SYS_DENOM_OFFSET 0x0060 /* Denominator of 528MHz System PLL Fractional Loop Divider */ +#define IMXRT_CCM_ANALOG_PLL_AUDIO_OFFSET 0x0070 /* Analog Audio PLL control Register */ +#define IMXRT_CCM_ANALOG_PLL_AUDIO_NUM_OFFSET 0x0080 /* Numerator of Audio PLL Fractional Loop Divider */ +#define IMXRT_CCM_ANALOG_PLL_AUDIO_DENOM_OFFSET 0x0090 /* Denominator of Audio PLL Fractional Loop Divider */ +#define IMXRT_CCM_ANALOG_PLL_VIDEO_OFFSET 0x00a0 /* Analog Video PLL control Register */ +#define IMXRT_CCM_ANALOG_PLL_VIDEO_NUM_OFFSET 0x00b0 /* Numerator of Video PLL Fractional Loop Divider */ +#define IMXRT_CCM_ANALOG_PLL_VIDEO_DENOM_OFFSET 0x00c0 /* Denominator of Video PLL Fractional Loop Divider */ +#define IMXRT_CCM_ANALOG_PLL_ENET_OFFSET 0x00e0 /* Analog ENET PLL Control Register */ +#define IMXRT_CCM_ANALOG_PFD_480_OFFSET 0x00f0 /* 480MHz Clock (PLL3) Phase Fractional Divider Control */ +#define IMXRT_CCM_ANALOG_PFD_528_OFFSET 0x0100 /* 528MHz Clock (PLL2) Phase Fractional Divider Control */ +#define IMXRT_CCM_ANALOG_MISC0_OFFSET 0x0150 /* Miscellaneous Register 0 */ +#define IMXRT_CCM_ANALOG_MISC1_OFFSET 0x0160 /* Miscellaneous Register 1 */ +#define IMXRT_CCM_ANALOG_MISC2_OFFSET 0x0170 /* Miscellaneous Register 2 */ + +/* Register addresses ***************************************************************************************/ + +#define IMXRT_CCM_CCR (IMXRT_CCM_BASE + IMXRT_CCM_CCR_OFFSET) +#define IMXRT_CCM_CSR (IMXRT_CCM_BASE + IMXRT_CCM_CSR_OFFSET) +#define IMXRT_CCM_CCSR (IMXRT_CCM_BASE + IMXRT_CCM_CCSR_OFFSET) +#define IMXRT_CCM_CACRR (IMXRT_CCM_BASE + IMXRT_CCM_CACRR_OFFSET) +#define IMXRT_CCM_CBCDR (IMXRT_CCM_BASE + IMXRT_CCM_CBCDR_OFFSET) +#define IMXRT_CCM_CBCMR (IMXRT_CCM_BASE + IMXRT_CCM_CBCMR_OFFSET) +#define IMXRT_CCM_CSCMR1 (IMXRT_CCM_BASE + IMXRT_CCM_CSCMR1_OFFSET) +#define IMXRT_CCM_CSCMR2 (IMXRT_CCM_BASE + IMXRT_CCM_CSCMR2_OFFSET) +#define IMXRT_CCM_CSCDR1 (IMXRT_CCM_BASE + IMXRT_CCM_CSCDR1_OFFSET) +#define IMXRT_CCM_CS1CDR (IMXRT_CCM_BASE + IMXRT_CCM_CS1CDR_OFFSET) +#define IMXRT_CCM_CS2CDR (IMXRT_CCM_BASE + IMXRT_CCM_CS2CDR_OFFSET) +#define IMXRT_CCM_CDCDR (IMXRT_CCM_BASE + IMXRT_CCM_CDCDR_OFFSET) +#define IMXRT_CCM_CSCDR2 (IMXRT_CCM_BASE + IMXRT_CCM_CSCDR2_OFFSET) +#define IMXRT_CCM_CSCDR3 (IMXRT_CCM_BASE + IMXRT_CCM_CSCDR3_OFFSET) +#define IMXRT_CCM_CDHIPR (IMXRT_CCM_BASE + IMXRT_CCM_CDHIPR_OFFSET) +#define IMXRT_CCM_CLPCR (IMXRT_CCM_BASE + IMXRT_CCM_CLPCR_OFFSET) +#define IMXRT_CCM_CISR (IMXRT_CCM_BASE + IMXRT_CCM_CISR_OFFSET) +#define IMXRT_CCM_CIMR (IMXRT_CCM_BASE + IMXRT_CCM_CIMR_OFFSET) +#define IMXRT_CCM_CCOSR (IMXRT_CCM_BASE + IMXRT_CCM_CCOSR_OFFSET) +#define IMXRT_CCM_CGPR (IMXRT_CCM_BASE + IMXRT_CCM_CGPR_OFFSET) +#define IMXRT_CCM_CCGR0 (IMXRT_CCM_BASE + IMXRT_CCM_CCGR0_OFFSET) +#define IMXRT_CCM_CCGR1 (IMXRT_CCM_BASE + IMXRT_CCM_CCGR1_OFFSET) +#define IMXRT_CCM_CCGR2 (IMXRT_CCM_BASE + IMXRT_CCM_CCGR2_OFFSET) +#define IMXRT_CCM_CCGR3 (IMXRT_CCM_BASE + IMXRT_CCM_CCGR3_OFFSET) +#define IMXRT_CCM_CCGR4 (IMXRT_CCM_BASE + IMXRT_CCM_CCGR4_OFFSET) +#define IMXRT_CCM_CCGR5 (IMXRT_CCM_BASE + IMXRT_CCM_CCGR5_OFFSET) +#define IMXRT_CCM_CCGR6 (IMXRT_CCM_BASE + IMXRT_CCM_CCGR6_OFFSET) +#define IMXRT_CCM_CMEOR (IMXRT_CCM_BASE + IMXRT_CCM_CMEOR_OFFSET) + +#define IMXRT_CCM_ANALOG_PLL_ARM (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_ARM_OFFSET) +#define IMXRT_CCM_ANALOG_PLL_USB1 (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_USB1_OFFSET) +#define IMXRT_CCM_ANALOG_PLL_USB2 (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_USB2_OFFSET) +#define IMXRT_CCM_ANALOG_PLL_SYS (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_SYS_OFFSET) +#define IMXRT_CCM_ANALOG_PLL_SYS_SS (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_SYS_SS_OFFSET) +#define IMXRT_CCM_ANALOG_PLL_SYS_NUM (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_SYS_NUM_OFFSET) +#define IMXRT_CCM_ANALOG_PLL_SYS_DENOM (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_SYS_DENOM_OFFSET) +#define IMXRT_CCM_ANALOG_PLL_AUDIO (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_AUDIO_OFFSET) +#define IMXRT_CCM_ANALOG_PLL_AUDIO_NUM (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_AUDIO_NUM_OFFSET) +#define IMXRT_CCM_ANALOG_PLL_AUDIO_DENOM (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_AUDIO_DENOM_OFFSET) +#define IMXRT_CCM_ANALOG_PLL_VIDEO (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_VIDEO_OFFSET) +#define IMXRT_CCM_ANALOG_PLL_VIDEO_NUM (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_VIDEO_NUM_OFFSET) +#define IMXRT_CCM_ANALOG_PLL_VIDEO_DENOM (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_VIDEO_DENOM_OFFSET) +#define IMXRT_CCM_ANALOG_PLL_ENET (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_ENET_OFFSET) +#define IMXRT_CCM_ANALOG_PFD_480 (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PFD_480_OFFSET) +#define IMXRT_CCM_ANALOG_PFD_528 (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PFD_528_OFFSET) +#define IMXRT_CCM_ANALOG_MISC0 (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_MISC0_OFFSET) +#define IMXRT_CCM_ANALOG_MISC1 (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_MISC1_OFFSET) +#define IMXRT_CCM_ANALOG_MISC2 (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_MISC2_OFFSET) + +/* Register bit definitions *********************************************************************************/ + +/* Control Register */ + +#define CCM_CCR_OSCNT_SHIFT (0) /* Bits 0-7: Oscillator ready counter value */ +#define CCM_CCR_OSCNT_MASK (0xff << CCM_CCR_OSCNT_SHIFT) +# define CCM_CCR_OSCNT(n) ((uint32_t)(n) << CCM_CCR_OSCNT_SHIFT) + /* Bits 8-11: Reserved */ +#define CCM_CCR_COSC_EN (1 << 12) /* Bit 12: On chip oscillator enable */ + /* Bits 13-20: Reserved */ +#define CCM_CCR_REG_BYPASS_COUNT_SHIFT (21) /* Bits 21-26: Counter for analog_reg_bypass */ +#define CCM_CCR_REG_BYPASS_COUNT_MASK (0x3f << CCM_CCR_REG_BYPASS_COUNT_SHIFT) +# define CCM_CCR_REG_BYPASS_COUNT(n) ((uint32_t)(n) << CCM_CCR_REG_BYPASS_COUNT_SHIFT) +#define CCM_CCR_RBC_EN (1 << 27) /* Bit 27: Enable for REG_BYPASS_COUNTER */ + /* Bits 28-31: Reserved */ +/* Status Register */ + +#define CCM_CSR_REF_EN_B (1 << 0) /* Bit 0: Status of the value of CCM_REF_EN_B */ + /* Bits 1-2: Reserved */ +#define CCM_CSR_CAMP2_READY (3 << 0) /* Bit 3: Status indication of CAMP2 */ + /* Bit 4: Reserved */ +#define CCM_CSR_COSC_READY (5 << 0) /* Bit 5: Status indication of on board oscillator */ + /* Bits 6-31: Reserved */ +/* Clock Switcher Register */ + +#define CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0) /* Bit 0: Selects source to generate pll3_sw_clk */ + +/* Arm Clock Root Register */ + +#define CCM_CACRR_ARM_PODF_SHIFT (0) /* Bits 0-2: Divider for ARM clock root */ +#define CCM_CACRR_ARM_PODF_MASK (0x3 << CCM_CACRR_ARM_PODF_SHIFT) +# define CCM_CACRR_ARM_PODF(n) ((uint32_t)(n) << CCM_CACRR_ARM_PODF_SHIFT) + +/* Bus Clock Divider Register */ + + /* Bits 0-5: Reserved */ +#define CCM_CBCDR_SEMC_CLK_SEL (1 << 6) /* Bit 6: SEMC clock source select */ +#define CCM_CBCDR_SEMC_ALT_CLK_SEL (1 << 7) /* Bit 7: SEMC alternative clock select */ +#define CCM_CBCDR_SEMC_ALT_CLK_SEL_PLL2 (0 << 7) /* Bit 7: PLL2 PFD2 will be selected */ +#define CCM_CBCDR_SEMC_ALT_CLK_SEL_PLL3 (1 << 7) /* Bit 7: PLL3 PFD1 will be selected */ +#define CCM_CBCDR_IPG_PODF_SHIFT (8) /* Bits 8-9: Divider for ipg podf */ +#define CCM_CBCDR_IPG_PODF_MASK (0x3 << CCM_CBCDR_IPG_PODF_SHIFT) +# define CCM_CBCDR_IPG_PODF(n) ((uint32_t)(n) << CCM_CBCDR_IPG_PODF_SHIFT) +#define CCM_CBCDR_AHB_PODF_SHIFT (10) /* Bits 10-12: Divider for AHB PODF */ +#define CCM_CBCDR_AHB_PODF_MASK (0x3 << CCM_CBCDR_AHB_PODF_SHIFT) +# define CCM_CBCDR_AHB_PODF(n) ((uint32_t)(n) << CCM_CBCDR_AHB_PODF_SHIFT) + /* Bits 13-15: Reserved */ +#define CCM_CBCDR_SEMC_PODF_SHIFT (16) /* Bits 16-18: Post divider for SEMC clock */ +#define CCM_CBCDR_SEMC_PODF_MASK (0x3 << CCM_CBCDR_SEMC_PODF_SHIFT) +# define CCM_CBCDR_SEMC_PODF(n) ((uint32_t)(n) << CCM_CBCDR_SEMC_PODF_SHIFT) + /* Bits 19-24: Reserved */ +#define CCM_CBCDR_SEMC_PERIPH_CLK_SEL (1 << 25) /* Bit 25: Selector for peripheral main clock */ + /* Bit 26: Reserved */ +#define CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT (27) /* Bits 27-29: Divider for periph_clk2_podf */ +#define CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x7 << CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT) +# define CCM_CBCDR_PERIPH_CLK2_PODF(n) ((uint32_t)(n) << CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT) + /* Bits 30-31: Reserved */ + +/* Bus Clock Multiplexer Register */ + + /* Bits 0-3: Reserved */ +#define CCM_CBCMR_LPSPI_CLK_SEL_SHIFT (4) /* Bits 4-5: Selector for lpspi clock multiplexer */ +#define CCM_CBCMR_LPSPI_CLK_SEL_MASK (0x3 << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT) +# define CCM_CBCMR_LPSPI_CLK_SEL(n) ((uint32_t)(n) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT) +# define CCM_CBCMR_LPSPI_CLK_SEL_PLL3_PFD1 ((uint32_t)(0) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT) +# define CCM_CBCMR_LPSPI_CLK_SEL_PLL3_PFD0 ((uint32_t)(1) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT) +# define CCM_CBCMR_LPSPI_CLK_SEL_PLL2 ((uint32_t)(2) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT) +# define CCM_CBCMR_LPSPI_CLK_SEL_PLL2_PFD2 ((uint32_t)(3) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT) + /* Bits 6-11: Reserved */ +#define CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT (12) /* Bits 13-13: Selector for peripheral clk2 clock multiplexer */ +#define CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3 << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT) +# define CCM_CBCMR_PERIPH_CLK2_SEL(n) ((uint32_t)(n) << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT) +# define CCM_CBCMR_PERIPH_CLK2_SEL_PLL3_SW ((uint32_t)(0) << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT) +# define CCM_CBCMR_PERIPH_CLK2_SEL_OSC_CLK ((uint32_t)(1) << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT) +# define CCM_CBCMR_PERIPH_CLK2_SEL_PLL2_BP ((uint32_t)(2) << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT) +#define CCM_CBCMR_TRACE_CLK_SEL_SHIFT (14) /* Bits 14-15: Selector for Trace clock multiplexer */ +#define CCM_CBCMR_TRACE_CLK_SEL_MASK (0x3 << CCM_CBCMR_TRACE_CLK_SEL_SHIFT) +# define CCM_CBCMR_TRACE_CLK_SEL(n) ((uint32_t)(n) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT) +# define CCM_CBCMR_TRACE_CLK_SEL_PLL2 ((uint32_t)(0) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT) +# define CCM_CBCMR_TRACE_CLK_SEL_PLL2_PFD2 ((uint32_t)(1) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT) +# define CCM_CBCMR_TRACE_CLK_SEL_PLL2_PFD0 ((uint32_t)(2) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT) +# define CCM_CBCMR_TRACE_CLK_SEL_PLL2_PFD1 ((uint32_t)(3) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT) + /* Bits 16-17: Reserved */ +#define CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT (18) /* Bits 18-19: Selector for pre_periph clock multiplexer */ +#define CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0x3 << CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT) +# define CCM_CBCMR_PRE_PERIPH_CLK_SEL(n) ((uint32_t)(n) << CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT) +# define CCM_CBCMR_PRE_PERIPH_CLK_SEL_PLL2 ((uint32_t)(0) << CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT) +# define CCM_CBCMR_PRE_PERIPH_CLK_SEL_PLL2_PFD2 ((uint32_t)(1) << CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT) +# define CCM_CBCMR_PRE_PERIPH_CLK_SEL_PLL2_PFD0 ((uint32_t)(2) << CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT) +# define CCM_CBCMR_PRE_PERIPH_CLK_SEL_PLL1 ((uint32_t)(3) << CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT) + /* Bits 20-22: Reserved */ +#define CCM_CBCMR_LCDIF_PODF_SHIFT (23) /* Bits 23-25: Post-divider for LCDIF clock */ +#define CCM_CBCMR_LCDIF_PODF_MASK (0x7 << CCM_CBCMR_LCDIF_PODF_SHIFT) +# define CCM_CBCMR_LCDIF_PODF(n) ((uint32_t)(n) << CCM_CBCMR_LCDIF_PODF_SHIFT) +#define CCM_CBCMR_LPSPI_PODF_SHIFT (26) /* Bits 26-28: Divider for LPSPI */ +#define CCM_CBCMR_LPSPI_PODF_MASK (0x7 << CCM_CBCMR_LPSPI_PODF_SHIFT) +# define CCM_CBCMR_LPSPI_PODF(n) ((uint32_t)(n) << CCM_CBCMR_LPSPI_PODF_SHIFT) + +/* Serial Clock Multiplexer Register 1 */ + +#define CCM_CSCMR1_PERCLK_PODF_SHIFT (0) /* Bits 0-5: Divider for perclk podf */ +#define CCM_CSCMR1_PERCLK_PODF_MASK (0x3f << CCM_CSCMR1_PERCLK_PODF_SHIFT) +# define CCM_CSCMR1_PERCLK_PODF(n) ((uint32_t)(n) << CCM_CSCMR1_PERCLK_PODF_SHIFT) +#define CCM_CSCMR1_PERCLK_CLK_SEL (1 << 6) /* Bit 6: Selector for the perclk clock multiplexer */ + /* Bits 7-9: Reserved */ +#define CCM_CSCMR1_SAI1_CLK_SEL_SHIFT (10) /* Bits 10-11: Selector for sai1 clock multiplexer */ +#define CCM_CSCMR1_SAI1_CLK_SEL_MASK (0x3 << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT) +# define CCM_CSCMR1_SAI1_CLK_SEL(n) ((uint32_t)(n) << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT) +# define CCM_CSCMR1_SAI1_CLK_SEL_PLL3_PFD2 ((uint32_t)(0) << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT) +# define CCM_CSCMR1_SAI1_CLK_SEL_PLL5 ((uint32_t)(1) << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT) +# define CCM_CSCMR1_SAI1_CLK_SEL_PLL4 ((uint32_t)(2) << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT) +#define CCM_CSCMR1_SAI2_CLK_SEL_SHIFT (12) /* Bits 12-13: Selector for sai2 clock multiplexer */ +#define CCM_CSCMR1_SAI2_CLK_SEL_MASK (0x3 << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT) +# define CCM_CSCMR1_SAI2_CLK_SEL(n) ((uint32_t)(n) << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT) +# define CCM_CSCMR1_SAI2_CLK_SEL_PLL3_PFD2 ((uint32_t)(0) << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT) +# define CCM_CSCMR1_SAI2_CLK_SEL_PLL5 ((uint32_t)(1) << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT) +# define CCM_CSCMR1_SAI2_CLK_SEL_PLL4 ((uint32_t)(2) << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT) +#define CCM_CSCMR1_SAI3_CLK_SEL_SHIFT (14) /* Bits 14-15: Selector for sai3 clock multiplexer */ +#define CCM_CSCMR1_SAI3_CLK_SEL_MASK (0x3 << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT) +# define CCM_CSCMR1_SAI3_CLK_SEL(n) ((uint32_t)(n) << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT) +# define CCM_CSCMR1_SAI3_CLK_SEL_PLL3_PFD2 ((uint32_t)(0) << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT) +# define CCM_CSCMR1_SAI3_CLK_SEL_PLL5 ((uint32_t)(1) << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT) +# define CCM_CSCMR1_SAI3_CLK_SEL_PLL4 ((uint32_t)(2) << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT) +#define CCM_CSCMR1_USDHC1_CLK_SEL (1 << 16) /* Bit 16: Selector for usdhc1 clock multiplexer */ +# define CCM_CSCMR1_USDHC1_CLK_SEL_PLL2_PFD2 (0 << 16) /* derive clock from PLL2 PFD2 */ +# define CCM_CSCMR1_USDHC1_CLK_SEL_PLL2_PFD0 (1 << 16) /* derive clock from PLL2 PFD0 */ +#define CCM_CSCMR1_USDHC2_CLK_SEL (1 << 17) /* Bit 17: Selector for usdhc2 clock multiplexer */ +# define CCM_CSCMR1_USDHC2_CLK_SEL_PLL2_PFD2 (0 << 17) /* derive clock from PLL2 PFD2 */ +# define CCM_CSCMR1_USDHC2_CLK_SEL_PLL2_PFD0 (1 << 17) /* derive clock from PLL2 PFD0 */ + /* Bits 18-22: Reserved */ +#define CCM_CSCMR1_FLEXSPI_PODF_SHIFT (23) /* Bits 23-25: Divider for flexspi clock root */ +#define CCM_CSCMR1_FLEXSPI_PODF_MASK (0x7 << CCM_CSCMR1_FLEXSPI_PODF_SHIFT) +# define CCM_CSCMR1_FLEXSPI_PODF(n) ((uint32_t)(n) << CCM_CSCMR1_FLEXSPI_PODF_SHIFT) + /* Bits 26-28: Reserved */ +#define CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT (29) /* Bits 29-30: Selector for flexspi clock multiplexer */ +#define CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK (0x3 << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT) +# define CCM_CSCMR1_FLEXSPI_CLK_SEL(n) ((uint32_t)(n) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT) +# define CCM_CSCMR1_FLEXSPI_CLK_SEL_SEMC_CLK ((uint32_t)(0) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT) +# define CCM_CSCMR1_FLEXSPI_CLK_SEL_PLL3_SW ((uint32_t)(1) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT) +# define CCM_CSCMR1_FLEXSPI_CLK_SEL_PLL2_PFD2 ((uint32_t)(2) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT) +# define CCM_CSCMR1_FLEXSPI_CLK_SEL_PLL3_PFD0 ((uint32_t)(3) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT) + /* Bit 31: Reserved */ + +/* Serial Clock Multiplexer Register 2 */ + +#define CCM_CSCMR2_CAN_CLK_PODF_SHIFT (2) /* Bits 2-7: Divider for can clock podf */ +#define CCM_CSCMR2_CAN_CLK_PODF_MASK (0x3f << CCM_CSCMR2_CAN_CLK_PODF_SHIFT) +# define CCM_CSCMR2_CAN_CLK_PODF(n) ((uint32_t)(n) << CCM_CSCMR2_CAN_CLK_PODF_SHIFT) +#define CCM_CSCMR2_CAN_CLK_SEL_SHIFT (8) /* Bits 8-9: Selector for FlexCAN clock multiplexer */ +#define CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3 << CCM_CSCMR2_CAN_CLK_SEL_SHIFT) +# define CCM_CSCMR2_CAN_CLK_SEL(n) ((uint32_t)(n) << CCM_CSCMR2_CAN_CLK_SEL_SHIFT) +# define CCM_CSCMR2_CAN_CLK_SEL_PLL3_SW_60 ((uint32_t)(0) << CCM_CSCMR2_CAN_CLK_SEL_SHIFT) +# define CCM_CSCMR2_CAN_CLK_SEL_OSC_CLK ((uint32_t)(1) << CCM_CSCMR2_CAN_CLK_SEL_SHIFT) +# define CCM_CSCMR2_CAN_CLK_SEL_PLL3_SW_80 ((uint32_t)(2) << CCM_CSCMR2_CAN_CLK_SEL_SHIFT) + /* Bits 10-18: Reserved */ +#define CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT (19) /* Bits 19-20: Selector for flexio2 clock multiplexer */ +#define CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK (0x3 << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT) +# define CCM_CSCMR2_FLEXIO2_CLK_SEL(n) ((uint32_t)(n) << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT) +# define CCM_CSCMR2_FLEXIO2_CLK_SEL_PLL4 ((uint32_t)(0) << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT) +# define CCM_CSCMR2_FLEXIO2_CLK_SEL_PLL3_PFD2 ((uint32_t)(1) << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT) +# define CCM_CSCMR2_FLEXIO2_CLK_SEL_PLL5 ((uint32_t)(2) << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT) +# define CCM_CSCMR2_FLEXIO2_CLK_SEL_PLL3_SW ((uint32_t)(3) << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT) + /* Bits 21-31: Reserved */ + +/* Serial Clock Divider Register 1 */ + +#define CCM_CSCDR1_UART_CLK_PODF_SHIFT (0) /* Bits 0-5: Divider for uart clock podf */ +#define CCM_CSCDR1_UART_CLK_PODF_MASK (0x3f << CCM_CSCDR1_UART_CLK_PODF_SHIFT) +# define CCM_CSCDR1_UART_CLK_PODF(n) ((uint32_t)(n) << CCM_CSCDR1_UART_CLK_PODF_SHIFT) +#define CCM_CSCDR1_UART_CLK_SEL (1 << 6) /* Bit 6: Selector for the UART clock multiplexer */ +# define CCM_CSCDR1_UART_CLK_SEL_PLL3_80 (0 << 6) /* derive clock from pll3_80m */ +# define CCM_CSCDR1_UART_CLK_SEL_OSC_CLK (1 << 6) /* derive clock from osc_clk */ + /* Bits 7-10: Reserved */ +#define CCM_CSCDR1_USDHC1_PODF_SHIFT (11) /* Bits 11-13: Divider for usdhc1 clock podf */ +#define CCM_CSCDR1_USDHC1_PODF_MASK (0x7 << CCM_CSCDR1_USDHC1_PODF_SHIFT) +# define CCM_CSCDR1_USDHC1_PODF(n) ((uint32_t)(n) << CCM_CSCDR1_USDHC1_PODF_SHIFT) + /* Bits 14-15: Reserved */ +#define CCM_CSCDR1_USDHC2_PODF_SHIFT (16) /* Bits 16-18: Divider for usdhc2 clock */ +#define CCM_CSCDR1_USDHC2_PODF_MASK (0x7 << CCM_CSCDR1_USDHC2_PODF_SHIFT) +# define CCM_CSCDR1_USDHC2_PODF(n) ((uint32_t)(n) << CCM_CSCDR1_USDHC2_PODF_SHIFT) + /* Bits 19-24: Reserved */ +#define CCM_CSCDR1_TRACE_PODF_SHIFT (25) /* Bits 25-27: Divider for trace clock */ +#define CCM_CSCDR1_TRACE_PODF_MASK (0x7 << CCM_CSCDR1_TRACE_PODF_SHIFT) +# define CCM_CSCDR1_TRACE_PODF(n) ((uint32_t)(n) << CCM_CSCDR1_TRACE_PODF_SHIFT) + /* Bits 28-31: Reserved */ + +/* Clock Divider Register 1 */ + +#define CCM_CS1CDR_SAI1_CLK_PODF_SHIFT (0) /* Bits 0-5: Divider for sai1 clock podf */ +#define CCM_CS1CDR_SAI1_CLK_PODF_MASK (0x3f << CCM_CS1CDR_SAI1_CLK_PODF_SHIFT) +# define CCM_CS1CDR_SAI1_CLK_PODF(n) ((uint32_t)(n) << CCM_CS1CDR_SAI1_CLK_PODF_SHIFT) +#define CCM_CS1CDR_SAI1_CLK_PRED_SHIFT (6) /* Bits 6-8: Divider for sai1 clock pred */ +#define CCM_CS1CDR_SAI1_CLK_PRED_MASK (0x7 << CCM_CS1CDR_SAI1_CLK_PRED_SHIFT) +# define CCM_CS1CDR_SAI1_CLK_PRED(n) ((uint32_t)(n) << CCM_CS1CDR_SAI1_CLK_PRED_SHIFT) +#define CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT (9) /* Bits 9-11: Divider for flexio2 clock */ +#define CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK (0x7 << CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT) +# define CCM_CS1CDR_FLEXIO2_CLK_PRED(n) ((uint32_t)(n) << CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT) + /* Bits 12-15: Reserved */ +#define CCM_CS1CDR_SAI3_CLK_PODF_SHIFT (16) /* Bits 16-21: Divider for sai3 clock podf */ +#define CCM_CS1CDR_SAI3_CLK_PODF_MASK (0x3f << CCM_CS1CDR_SAI3_CLK_PODF_SHIFT) +# define CCM_CS1CDR_SAI3_CLK_PODF(n) ((uint32_t)(n) << CCM_CS1CDR_SAI3_CLK_PODF_SHIFT) +#define CCM_CS1CDR_SAI3_CLK_PRED_SHIFT (22) /* Bits 22-24: Divider for sai3 clock pred */ +#define CCM_CS1CDR_SAI3_CLK_PRED_MASK (0x7 << CCM_CS1CDR_SAI3_CLK_PRED_SHIFT) +# define CCM_CS1CDR_SAI3_CLK_PRED(n) ((uint32_t)(n) << CCM_CS1CDR_SAI3_CLK_PRED_SHIFT) +#define CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT (25) /* Bits 25-27: Divider for flexio2 clock */ +#define CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK (0x7 << CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT) +# define CCM_CS1CDR_FLEXIO2_CLK_PODF(n) ((uint32_t)(n) << CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT) + /* Bits 28-31: Reserved */ + +/* Clock Divider Register 2 */ + +#define CCM_CS2CDR_SAI2_CLK_PODF_SHIFT (0) /* Bits 0-5: Divider for sai2 clock podf */ +#define CCM_CS2CDR_SAI2_CLK_PODF_MASK (0x3f << CCM_CS2CDR_SAI2_CLK_PODF_SHIFT) +# define CCM_CS2CDR_SAI2_CLK_PODF(n) ((uint32_t)(n) << CCM_CS2CDR_SAI2_CLK_PODF_SHIFT) +#define CCM_CS2CDR_SAI2_CLK_PRED_SHIFT (6) /* Bits 6-8: Divider for sai2 clock pred */ +#define CCM_CS2CDR_SAI2_CLK_PRED_MASK (0x7 << CCM_CS2CDR_SAI2_CLK_PRED_SHIFT) +# define CCM_CS2CDR_SAI2_CLK_PRED(n) ((uint32_t)(n) << CCM_CS2CDR_SAI2_CLK_PRED_SHIFT) + +/* D1 Clock Divider Register */ + +#define CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT (7) /* Bits 7-8: Selector for flexio1 clock multiplexer */ +#define CCM_CDCDR_FLEXIO1_CLK_SEL_MASK (0x3 << CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT) +# define CCM_CDCDR_FLEXIO1_CLK_SEL(n) ((uint32_t)(n) << CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT) +# define CCM_CDCDR_FLEXIO1_CLK_SEL_PLL4 ((uint32_t)(0) << CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT) +# define CCM_CDCDR_FLEXIO1_CLK_SEL_PLL3_PFD2 ((uint32_t)(1) << CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT) +# define CCM_CDCDR_FLEXIO1_CLK_SEL_PLL3_PLL5 ((uint32_t)(2) << CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT) +# define CCM_CDCDR_FLEXIO1_CLK_SEL_PLL3_PLL3_SW ((uint32_t)(3) << CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT) +#define CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT (9) /* Bits 9-11: Divider for flexio1 clock podf */ +#define CCM_CDCDR_FLEXIO1_CLK_PODF_MASK (0x7 << CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT) +# define CCM_CDCDR_FLEXIO1_CLK_PODF(n) ((uint32_t)(n) << CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT) +#define CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT (12) /* Bits 12-14: Divider for flexio1 clock pred */ +#define CCM_CDCDR_FLEXIO1_CLK_PRED_MASK (0x7 << CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT) +# define CCM_CDCDR_FLEXIO1_CLK_PRED(n) ((uint32_t)(n) << CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT) + /* Bits 15-19: Reserved */ +#define CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT (20) /* Bits 20-21: Selector for spdif0 clock multiplexer */ +#define CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x3 << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT) +# define CCM_CDCDR_SPDIF0_CLK_SEL(n) ((uint32_t)(n) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT) +# define CCM_CDCDR_SPDIF0_CLK_SEL_PLL4 ((uint32_t)(0) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT) +# define CCM_CDCDR_SPDIF0_CLK_SEL_PLL3_PFD2 ((uint32_t)(1) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT) +# define CCM_CDCDR_SPDIF0_CLK_SEL_PLL3_PLL5 ((uint32_t)(2) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT) +# define CCM_CDCDR_SPDIF0_CLK_SEL_PLL3_PLL3_SW ((uint32_t)(3) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT) +#define CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT (22) /* Bits 22-24: Divider for spdif0 clock podf */ +#define CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x7 << CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT) +# define CCM_CDCDR_SPDIF0_CLK_PODF(n) ((uint32_t)(n) << CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT) +#define CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT (25) /* Bits 25-27: Divider for spdif0 clock pred */ +#define CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT) +# define CCM_CDCDR_SPDIF0_CLK_PRED(n) ((uint32_t)(n) << CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT) + +/* Serial Clock Divider Register 2 */ + + /* Bits 0-8: Reserved */ +#define CCM_CSCDR2_LCDIF_CLK_SEL_SHIFT (9) /* Bits 9-11: Selector for LCDIF root clock multiplexer */ +#define CCM_CSCDR2_LCDIF_CLK_SEL_MASK (0x7 << CCM_CSCDR2_LCDIF_CLK_SEL_SHIFT) +# define CCM_CSCDR2_LCDIF_CLK_SEL(n) ((uint32_t)(n) << CCM_CSCDR2_LCDIF_CLK_SEL_SHIFT) +# define CCM_CSCDR2_LCDIF_CLK_SEL_LCDIF ((uint32_t)(0) << CCM_CSCDR2_LCDIF_CLK_SEL_SHIFT) +# define CCM_CSCDR2_LCDIF_CLK_SEL_IPP_DI0_CLK ((uint32_t)(1) << CCM_CSCDR2_LCDIF_CLK_SEL_SHIFT) +# define CCM_CSCDR2_LCDIF_CLK_SEL_IPP_DI1_CLK ((uint32_t)(2) << CCM_CSCDR2_LCDIF_CLK_SEL_SHIFT) +# define CCM_CSCDR2_LCDIF_CLK_SEL_IDB_DI0_CLK ((uint32_t)(3) << CCM_CSCDR2_LCDIF_CLK_SEL_SHIFT) +# define CCM_CSCDR2_LCDIF_CLK_SEL_IDB_DI1_CLK ((uint32_t)(4) << CCM_CSCDR2_LCDIF_CLK_SEL_SHIFT) +#define CCM_CSCDR2_LCDIF_PRED_SHIFT (12) /* Bits 12-14: Pre-divider for lcdif clock */ +#define CCM_CSCDR2_LCDIF_PRED_MASK (0x7 << CCM_CSCDR2_LCDIF_PRED_SHIFT) +# define CCM_CSCDR2_LCDIF_PRED(n) ((uint32_t)(n) << CCM_CSCDR2_LCDIF_PRED_SHIFT) +#define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT (15) /* Bits 15-17: Selector for lcdif root clock pre-multiplexer */ +#define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK (0x7 << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT) +# define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_(n) ((uint32_t)(n) << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT) +# define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_PLL2 ((uint32_t)(0) << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT) +# define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_PLL3_PFD3 ((uint32_t)(1) << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT) +# define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_PLL5 ((uint32_t)(2) << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT) +# define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_PLL2_PFD0 ((uint32_t)(3) << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT) +# define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_PLL2_PFD1 ((uint32_t)(4) << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT) +# define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_PLL3_PFD1 ((uint32_t)(5) << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT) +#define CCM_CSCDR2_LPI2C_CLK_SEL (1 << 18) /* Bit 18: Selector for the LPI2C clock multiplexer */ +# define CCM_CSCDR2_LPI2C_CLK_SEL_PLL3_60M (0 << 18) /* derive clock from pll3_60m */ +# define CCM_CSCDR2_LPI2C_CLK_SEL_OSC_CLK (1 << 18) /* derive clock from ock_clk */ +#define CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT (19) /* Bits 19-24: Divider for lpi2c clock podf */ +#define CCM_CSCDR2_LPI2C_CLK_PODF_MASK (0x3f << CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT) +# define CCM_CSCDR2_LPI2C_CLK_PODF(n) ((uint32_t)(n) << CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT) + /* Bits 25-31: Reserved */ + +/* Serial Clock Divider Register 3 */ + + /* Bits 0-8: Reserved */ +#define CCM_CSCDR3_CSI_CLK_SEL_SHIFT (9) /* Bits 9-10: Selector for csi_mclk multiplexer */ +#define CCM_CSCDR3_CSI_CLK_SEL_MASK (0x3 << CCM_CSCDR3_CSI_CLK_SEL_SHIFT) +# define CCM_CSCDR3_CSI_CLK_SEL(n) ((uint32_t)(n) << CCM_CSCDR3_CSI_CLK_SEL_SHIFT) +# define CCM_CSCDR3_CSI_CLK_SEL_OSC_CLK ((uint32_t)(0) << CCM_CSCDR3_CSI_CLK_SEL_SHIFT) +# define CCM_CSCDR3_CSI_CLK_SEL_OSC_PLL2_PFD2 ((uint32_t)(1) << CCM_CSCDR3_CSI_CLK_SEL_SHIFT) +# define CCM_CSCDR3_CSI_CLK_SEL_OSC_PLL3_120M ((uint32_t)(2) << CCM_CSCDR3_CSI_CLK_SEL_SHIFT) +# define CCM_CSCDR3_CSI_CLK_SEL_OSC_PLL3_PFD1 ((uint32_t)(3) << CCM_CSCDR3_CSI_CLK_SEL_SHIFT) +#define CCM_CSCDR3_CSI_PODF_SHIFT (11) /* Bits 11-13: Post divider for csi_mclk */ +#define CCM_CSCDR3_CSI_PODF_MASK (0x3 << CCM_CSCDR3_CSI_PODF_SHIFT) +# define CCM_CSCDR3_CSI_PODF(n) ((uint32_t)(n) << CCM_CSCDR3_CSI_PODF_SHIFT) + +/* Divider Handshake In-Process Register */ + +#define CCM_CDHIPR_SEMC_PODF_BUSY (1 << 0) /* Bit 0: Busy indicator for semc_podf */ +#define CCM_CDHIPR_AHB_PODF_BUSY (1 << 1) /* Bit 1: Busy indicator for ahb_podf */ + /* Bit 2: Reserved */ +#define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY (1 << 3) /* Bit 3: Busy indicator for periph2_clk_sel mux control */ + /* Bit 4: Reserved */ +#define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5) /* Bit 5: Busy indicator for periph_clk_sel mux control */ + /* Bits 6-15: Reserved */ +#define CCM_CDHIPR_ARM_PODF_BUSY (1 << 16) /* Bit 16: Busy indicator for arm_podf */ + /* Bits 17-31: Reserved */ + +/* Low Power Control Register */ + +#define CCM_CLPCR_LPM_SHIFT (0) /* Bits 0-1: Setting the low power mode */ +#define CCM_CLPCR_LPM_MASK (0x3 << CCM_CLPCR_LPM_SHIFT) +# define CCM_CLPCR_LPM(n) ((uint32_t)(n) << CCM_CLPCR_LPM_SHIFT) +# define CCM_CLPCR_LPM_RUN ((uint32_t)(0) << CCM_CLPCR_LPM_SHIFT) /* Remain in run mode */ +# define CCM_CLPCR_LPM_WAIT ((uint32_t)(1) << CCM_CLPCR_LPM_SHIFT) /* Transfer to wait mode */ +# define CCM_CLPCR_LPM_STOP ((uint32_t)(2) << CCM_CLPCR_LPM_SHIFT) /* Transfer to stop mode */ + /* Bits 2-4: Reserved */ +#define CCM_CLPCR_ARM_CLK_DIS_ON_LPM (1 << 5) /* Bit 5: ARM clocks disabled on wait mode */ +#define CCM_CLPCR_SBYOS (1 << 6) /* Bit 6: Standby clock oscillator bit */ +#define CCM_CLPCR_DIS_REF_OSC (1 << 7) /* Bit 7: external high frequency oscillator disable */ +#define CCM_CLPCR_VSTBY (1 << 8) /* Bit 8: Voltage standby request bit */ +#define CCM_CLPCR_STBY_COUNT_SHIFT (9) /* Bits 9-10: Standby counter definition */ +#define CCM_CLPCR_STBY_COUNT_MASK (0x3 << CCM_CLPCR_STBY_COUNT_SHIFT) +# define CCM_CLPCR_STBY_COUNT(n) ((uint32_t)(n) << CCM_CLPCR_STBY_COUNT_SHIFT) +#define CCM_CLPCR_COSC_PWRDOWN (1 << 11) /* Bit 11: On chip oscillator power down */ + /* Bits 12-18: Reserved */ +#define CCM_CLPCR_BYPASS_LPM_HS1 (1 << 19) /* Bit 19: Bypass low power mode handshake */ + /* Bit 20: Reserved */ +#define CCM_CLPCR_BYPASS_LPM_HS0 (1 << 21) /* Bit 21: Bypass low power mode handshake */ +#define CCM_CLPCR_MASK_CORE0_WFI (1 << 22) /* Bit 22: Mask WFI of core0 for entering low power mode */ + /* Bits 23-25: Reserved */ +#define CCM_CLPCR_MASK_SCU_IDLE (1 << 26) /* Bit 26: Mask SCU IDLE for entering low power mode */ +#define CCM_CLPCR_MASK_L2CC_IDLE (1 << 27) /* Bit 27: Mask L2CC IDLE for entering low power mode */ + /* Bits 28-31: Reserved */ + +/* Interrupt Status Register */ + +#define CCM_CISR_LRF_PLL (1 << 0) /* Bit 0: CCM irq2, lock of all enabled and not bypassed PLLs */ + /* Bits 1-5: Reserved */ +#define CCM_CISR_COSC_READY (1 << 6) /* Bit 6: CCM irq2, on board oscillator ready */ + /* Bits 7-16: Reserved */ +#define CCM_CISR_SEMC_PODF_LOADED (1 << 17) /* Bit 17: CCM irq1, frequency change of semc_podf */ + /* Bit 18: Reserved */ +#define CCM_CISR_PERIPH2_CLK_SEL_LOADED (1 << 19) /* Bit 19: CCM irq1, frequency change of periph2_clk_sel */ +#define CCM_CISR_AHB_PODF_LOADED (1 << 20) /* Bit 20: CCM irq1, frequency change of ahb_podf */ + /* Bit 21: Reserved */ +#define CCM_CISR_PERIPH_CLK_SEL_LOADED (1 << 22) /* Bit 22: CCM irq1, update of periph_clk_sel */ + /* Bits 23-25: Reserved */ +#define CCM_CISR_ARM_PODF_LOADED (1 << 26) /* Bit 26: CCM irq1, frequency change of arm_podf */ + /* Bits 27-31: Reserved */ + +/* Interrupt Mask Register */ + +#define CCM_CIMR_MASK_LRF_PLL (1 << 0) /* Bit 0: mask interrupt generation due to lrf of PLLs */ + /* Bits 1-5: Reserved */ +#define CCM_CIMR_MASK_COSC_READY (1 << 6) /* Bit 6: mask interrupt generation due to on board oscillator ready */ + /* Bits 7-16: Reserved */ +#define CCM_CIMR_MASK_SEMC_PODF_LOADED (1 << 17) /* Bit 17: mask interrupt generation due to frequency change of semc_podf */ + /* Bit 18: Reserved */ +#define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED (1 << 19) /* Bit 19: mask interrupt generation due to update of periph2_clk_sel */ +#define CCM_CIMR_MASK_AHB_PODF_LOADED (1 << 20) /* Bit 20: mask interrupt generation due to frequency change of ahb_podf */ + /* Bit 21: Reserved */ +#define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED (1 << 22) /* Bit 22: mask interrupt generation due to update of periph_clk_sel */ + /* Bits 23-25: Reserved */ +#define CCM_CIMR_MASK_ARM_PODF_LOADED (1 << 26) /* Bit 26: mask interrupt generation due to frequency change of arm_podf */ + /* Bits 27-31: Reserved */ + +/* Clock Output Source Register */ + +#define CCM_CCOSR_CLKO1_SEL_SHIFT (0) /* Bits 0-3: Selection of the clock to be generated on CCM_CLKO1 */ +#define CCM_CCOSR_CLKO1_SEL_MASK (0xF << CCM_CCOSR_CLKO1_SEL_SHIFT) +# define CCM_CCOSR_CLKO1_SEL_SEMC_CLK ((uint32_t)(5) << CCM_CCOSR_CLKO1_SEL_SHIFT) +# define CCM_CCOSR_CLKO1_SEL_ENC_CLK ((uint32_t)(6) << CCM_CCOSR_CLKO1_SEL_SHIFT) +# define CCM_CCOSR_CLKO1_SEL_LCDIF_PIX_CLK ((uint32_t)(10) << CCM_CCOSR_CLKO1_SEL_SHIFT) +# define CCM_CCOSR_CLKO1_SEL_AHB_CLK ((uint32_t)(11) << CCM_CCOSR_CLKO1_SEL_SHIFT) +# define CCM_CCOSR_CLKO1_SEL_IPG_CLK ((uint32_t)(12) << CCM_CCOSR_CLKO1_SEL_SHIFT) +# define CCM_CCOSR_CLKO1_SEL_PER_CLK ((uint32_t)(13) << CCM_CCOSR_CLKO1_SEL_SHIFT) +# define CCM_CCOSR_CLKO1_SEL_CKIL_SYNC_CLK ((uint32_t)(14) << CCM_CCOSR_CLKO1_SEL_SHIFT) +# define CCM_CCOSR_CLKO1_SEL_PLL4_MAIN_CLK ((uint32_t)(15) << CCM_CCOSR_CLKO1_SEL_SHIFT) +#define CCM_CCOSR_CLKO1_DIV_SHIFT (4) /* Bits 4-6: Setting the divider of CCM_CLKO1 */ +#define CCM_CCOSR_CLKO1_DIV_MASK (0x7 << CCM_CCOSR_CLKO1_DIV_SHIFT) +# define CCM_CCOSR_CLKO1_DIV(n) ((uint32_t)(n) << CCM_CCOSR_CLKO1_DIV_SHIFT) +#define CCM_CCOSR_CLKO1_EN (1 << 7) /* Bit 7: Enable of CCM_CLKO1 clock */ +#define CCM_CCOSR_CLK_OUT_SEL (1 << 8) /* Bit 8: CCM_CLKO1 output to reflect CCM_CLKO1 or CCM_CLKO2 clocks */ + /* Bits 9-15: Reserved */ +#define CCM_CCOSR_CLKO2_SEL_SHIFT (16) /* Bits 16-20: Selection of the clock to be generated on CCM_CLKO2 */ +#define CCM_CCOSR_CLKO2_SEL_MASK (0x1F << CCM_CCOSR_CLKO2_SEL_SHIFT) +# define CCM_CCOSR_CLKO2_SEL_USDHC1_CLK ((uint32_t)(3) << CCM_CCOSR_CLKO2_SEL_SHIFT) +# define CCM_CCOSR_CLKO2_SEL_WRCK_CLK ((uint32_t)(5) << CCM_CCOSR_CLKO2_SEL_SHIFT) +# define CCM_CCOSR_CLKO2_SEL_LPI2C_CLK ((uint32_t)(6) << CCM_CCOSR_CLKO2_SEL_SHIFT) +# define CCM_CCOSR_CLKO2_SEL_CSI_CORE ((uint32_t)(11) << CCM_CCOSR_CLKO2_SEL_SHIFT) +# define CCM_CCOSR_CLKO2_SEL_OSC_CLK ((uint32_t)(14) << CCM_CCOSR_CLKO2_SEL_SHIFT) +# define CCM_CCOSR_CLKO2_SEL_USDHC2_CLK ((uint32_t)(17) << CCM_CCOSR_CLKO2_SEL_SHIFT) +# define CCM_CCOSR_CLKO2_SEL_SAI1_CLK ((uint32_t)(18) << CCM_CCOSR_CLKO2_SEL_SHIFT) +# define CCM_CCOSR_CLKO2_SEL_SAI2_CLK ((uint32_t)(19) << CCM_CCOSR_CLKO2_SEL_SHIFT) +# define CCM_CCOSR_CLKO2_SEL_SAI3_CLK ((uint32_t)(20) << CCM_CCOSR_CLKO2_SEL_SHIFT) +# define CCM_CCOSR_CLKO2_SEL_CAN_CLK ((uint32_t)(23) << CCM_CCOSR_CLKO2_SEL_SHIFT) +# define CCM_CCOSR_CLKO2_SEL_FLEXSPI_CLK ((uint32_t)(27) << CCM_CCOSR_CLKO2_SEL_SHIFT) +# define CCM_CCOSR_CLKO2_SEL_UART_CLK ((uint32_t)(28) << CCM_CCOSR_CLKO2_SEL_SHIFT) +# define CCM_CCOSR_CLKO2_SEL_SPDIF0_CLK ((uint32_t)(29) << CCM_CCOSR_CLKO2_SEL_SHIFT) +#define CCM_CCOSR_CLKO2_DIV_SHIFT (21) /* Bits 21-23: Setting the divider of CCM_CLKO2 */ +#define CCM_CCOSR_CLKO2_DIV_MASK (0x7 << CCM_CCOSR_CLKO2_DIV_SHIFT) +# define CCM_CCOSR_CLKO2_DIV(n) ((uint32_t)(n) << CCM_CCOSR_CLKO2_DIV_SHIFT) +#define CCM_CCOSR_CLKO2_EN (1 << 24) /* Bit 24: Enable of CCM_CLKO2 clock */ + /* Bits 25-31: Reserved */ + +/* General Purpose Register */ + +#define CCM_CGPR_PMIC_DELAY_SCALER (1 << 0) /* Bit 0: Defines clock division of clock for stby_count */ + /* Bits 1-3: Reserved */ +#define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (1 << 4) /* Bit 4: allow fuse programing */ + /* Bits 5-13: Reserved */ +#define CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT (14) /* Bits 14-15: System memory DS control */ +#define CCM_CGPR_SYS_MEM_DS_CTRL_MASK (0x7 << CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT) +# define CCM_CGPR_SYS_MEM_DS_CTRL(n) ((uint32_t)(n) << CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT) +#define CCM_CGPR_FPL (1 << 16) /* Bit 16: Fast PLL enable */ +#define CCM_CGPR_INT_MEM_CLK_LPM (1 << 17) /* Bit 17: Control for the Deep Sleep signal to the ARM Platform memories */ + /* Bits 18-31: Reserved */ + +/* Clock Gating Register 0-6 */ + +#define CCM_CG_OFF (0) /* Clock is off during all modes */ +#define CCM_CG_RUN (1) /* Clock is on in run mode, but off in WAIT and STOP modes */ +#define CCM_CG_ALL (3) /* Clock is on during all modes, except STOP mode. */ + +#define CCM_CCGRX_CG0_SHIFT (0) +#define CCM_CCGRX_CG0_MASK (0x3) +# define CCM_CCGRX_CG0(n) ((uint32_t)(n) << CCM_CCGRX_CG0_SHIFT) +#define CCM_CCGRX_CG1_SHIFT (2) +#define CCM_CCGRX_CG1_MASK (0x3) +# define CCM_CCGRX_CG1(n) ((uint32_t)(n) << CCM_CCGRX_CG1_SHIFT) +#define CCM_CCGRX_CG2_SHIFT (4) +#define CCM_CCGRX_CG2_MASK (0x3) +# define CCM_CCGRX_CG2(n) ((uint32_t)(n) << CCM_CCGRX_CG2_SHIFT) +#define CCM_CCGRX_CG3_SHIFT (6) +#define CCM_CCGRX_CG3_MASK (0x3) +# define CCM_CCGRX_CG3(n) ((uint32_t)(n) << CCM_CCGRX_CG3_SHIFT) +#define CCM_CCGRX_CG4_SHIFT (8) +#define CCM_CCGRX_CG4_MASK (0x3) +# define CCM_CCGRX_CG4(n) ((uint32_t)(n) << CCM_CCGRX_CG4_SHIFT) +#define CCM_CCGRX_CG5_SHIFT (10) +#define CCM_CCGRX_CG5_MASK (0x3) +# define CCM_CCGRX_CG5(n) ((uint32_t)(n) << CCM_CCGRX_CG5_SHIFT) +#define CCM_CCGRX_CG6_SHIFT (12) +#define CCM_CCGRX_CG6_MASK (0x3) +# define CCM_CCGRX_CG6(n) ((uint32_t)(n) << CCM_CCGRX_CG6_SHIFT) +#define CCM_CCGRX_CG7_SHIFT (14) +#define CCM_CCGRX_CG7_MASK (0x3) +# define CCM_CCGRX_CG7(n) ((uint32_t)(n) << CCM_CCGRX_CG7_SHIFT) +#define CCM_CCGRX_CG8_SHIFT (16) +#define CCM_CCGRX_CG8_MASK (0x3) +# define CCM_CCGRX_CG8(n) ((uint32_t)(n) << CCM_CCGRX_CG8_SHIFT) +#define CCM_CCGRX_CG9_SHIFT (18) +#define CCM_CCGRX_CG9_MASK (0x3) +# define CCM_CCGRX_CG9(n) ((uint32_t)(n) << CCM_CCGRX_CG9_SHIFT) +#define CCM_CCGRX_CG10_SHIFT (20) +#define CCM_CCGRX_CG10_MASK (0x3) +# define CCM_CCGRX_CG10(n) ((uint32_t)(n) << CCM_CCGRX_CG10_SHIFT) +#define CCM_CCGRX_CG11_SHIFT (22) +#define CCM_CCGRX_CG11_MASK (0x3) +# define CCM_CCGRX_CG11(n) ((uint32_t)(n) << CCM_CCGRX_CG11_SHIFT) +#define CCM_CCGRX_CG12_SHIFT (24) +#define CCM_CCGRX_CG12_MASK (0x3) +# define CCM_CCGRX_CG12(n) ((uint32_t)(n) << CCM_CCGRX_CG12_SHIFT) +#define CCM_CCGRX_CG13_SHIFT (26) +#define CCM_CCGRX_CG13_MASK (0x3) +# define CCM_CCGRX_CG13(n) ((uint32_t)(n) << CCM_CCGRX_CG13_SHIFT) +#define CCM_CCGRX_CG14_SHIFT (28) +#define CCM_CCGRX_CG14_MASK (0x3) +# define CCM_CCGRX_CG14(n) ((uint32_t)(n) << CCM_CCGRX_CG14_SHIFT) +#define CCM_CCGRX_CG15_SHIFT (30) +#define CCM_CCGRX_CG15_MASK (0x3) +# define CCM_CCGRX_CG15(n) ((uint32_t)(n) << CCM_CCGRX_CG15_SHIFT) + +/* Module Enable Overide Register */ + + /* Bits 0-4: Reserved */ +#define CCM_CMEOR_MOD_EN_OV_GPT (1 << 5) /* Bit 5: Overide clock enable signal from GPT */ +#define CCM_CMEOR_MOD_EN_OV_PIT (1 << 6) /* Bit 6: Overide clock enable signal from PIT */ +#define CCM_CMEOR_MOD_EN_OV_USDHC (1 << 7) /* Bit 7: Overide clock enable signal from USDHC */ +#define CCM_CMEOR_MOD_EN_OV_TRNG (1 << 9) /* Bit 9: Overide clock enable signal from TRNG */ + /* Bits 10-27: Reserved */ +#define CCM_CMEOR_MOD_EN_OV_CAN2_CPI (1 << 28) /* Bit 28: Overide clock enable signal from CAN2 */ +#define CCM_CMEOR_MOD_EN_OV_CAN1_CPI (1 << 30) /* Bit 30: Overide clock enable signal from CAN1 */ + /* Bit 31: Reserved */ + +/* Analog ARM PLL control Register */ + +#define CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT (0) /* Bits 0-6: This field controls the PLL loop divider 54-108 */ +#define CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK (0x7f << CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT) +# define CCM_ANALOG_PLL_ARM_DIV_SELECT(n) ((uint32_t)(n) << CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT) + /* Bits 7-11 Reserved */ +#define CCM_ANALOG_PLL_ARM_POWERDOWN (1 << 12) /* Bit 12: Powers down the PLL */ +#define CCM_ANALOG_PLL_ARM_ENABLE (1 << 13) /* Bit 13: Enable the clock output */ +#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT (14) /* Bits 14-15: Determines the bypass source */ +#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK (0x3 << CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT) +# define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_REF_24M ((uint32_t)(0) << CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT) /* Select 24Mhz Osc as source */ +# define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_CLK1 ((uint32_t)(1) << CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT) /* Select the CLK1_N / CLK1_P as source */ +#define CCM_ANALOG_PLL_ARM_BYPASS (1 << 16) /* Bit 16: Bypass the PLL */ + /* Bits 17-18 Reserved */ +#define CCM_ANALOG_PLL_ARM_PLL_SEL (1 << 39) /* Bit 19: ? */ +#define CCM_ANALOG_PLL_ARM_LOCK (1 << 31) /* Bit 31: PLL is currently locked */ + +/* Analog USB1 480MHz PLL Control Register */ + +#define CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT (0) /* Bits 0-1: This field controls the PLL loop divider 20 or 22 */ +#define CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK (0x3 << CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT) +# define CCM_ANALOG_PLL_USB1_DIV_SELECT_20 ((uint32_t)(0) << CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT) +# define CCM_ANALOG_PLL_USB1_DIV_SELECT_22 ((uint32_t)(1) << CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT) + /* Bits 2-5 Reserved */ +#define CCM_ANALOG_PLL_USB1_EN_USB_CLKS (1 << 6) /* Bit 6: Enable PLL outputs for USBPHYn */ +#define CCM_ANALOG_PLL_USB1_POWER (1 << 12) /* Bit 12: Powers up the PLL */ +#define CCM_ANALOG_PLL_USB1_ENABLE (1 << 13) /* Bit 13: Enable the PLL clock output */ +#define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT (14) /* Bits 14-15: Determines the bypass source */ +#define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK (0x3 << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT) +# define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_REF_24M ((uint32_t)(0) << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT) /* Select 24Mhz Osc as source */ +# define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_CLK1 ((uint32_t)(1) << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT) /* Select the CLK1_N / CLK1_P as source */ +# define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_GPANAIO ((uint32_t)(2) << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT) /* */ +# define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_CHRG_DET_B ((uint32_t)(3) << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT) /* */ +#define CCM_ANALOG_PLL_USB1_BYPASS (1 << 16) /* Bit 16: Bypass the PLL */ + /* Bits 17-30 Reserved */ +#define CCM_ANALOG_PLL_USB1_LOCK (1 << 31) /* Bit 31: PLL is currently locked */ + +/* Analog USB2 480MHz PLL Control Register */ + +#define CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT (0) /* Bits 0-1: This field controls the PLL loop divider 20 or 22 */ +#define CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK (0x3 << CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT) +# define CCM_ANALOG_PLL_USB2_DIV_SELECT_20 ((uint32_t)(0) << CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT) +# define CCM_ANALOG_PLL_USB2_DIV_SELECT_22 ((uint32_t)(1) << CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT) + /* Bits 2-5 Reserved */ +#define CCM_ANALOG_PLL_USB2_EN_USB_CLKS (1 << 6) /* Bit 6: Enable PLL outputs for USBPHYn */ +#define CCM_ANALOG_PLL_USB2_POWER (1 << 12) /* Bit 12: Powers up the PLL */ +#define CCM_ANALOG_PLL_USB2_ENABLE (1 << 13) /* Bit 13: Enable the PLL clock output */ +#define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT (14) /* Bits 14-15: Determines the bypass source */ +#define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_MASK (0x3 << CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT) +# define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_REF_24M ((uint32_t)(0) << CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT) /* Select 24Mhz Osc as source */ +# define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_CLK1 ((uint32_t)(1) << CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT) /* Select the CLK1_N / CLK1_P as source */ +#define CCM_ANALOG_PLL_USB2_BYPASS (1 << 16) /* Bit 16: Bypass the PLL */ + /* Bits 17-30 Reserved */ +#define CCM_ANALOG_PLL_USB2_LOCK (1 << 31) /* Bit 31: PLL is currently locked */ + +/* Analog System PLL Control Register */ + +#define CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT (0) /* Bits 0-1: This field controls the PLL loop divider 20 or 22 */ +#define CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK (0x3 << CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT) +# define CCM_ANALOG_PLL_SYS_DIV_SELECT(n) ((uint32_t)(n) << CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT) +# define CCM_ANALOG_PLL_SYS_DIV_SELECT_20 ((uint32_t)(0) << CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT) +# define CCM_ANALOG_PLL_SYS_DIV_SELECT_22 ((uint32_t)(1) << CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT) +#define CCM_ANALOG_PLL_SYS_POWERDOWN (1 << 12) /* Bit 12: Powers down the PLL */ +#define CCM_ANALOG_PLL_SYS_ENABLE (1 << 13) /* Bit 13: Enable the PLL clock output */ +#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT (14) /* Bits 14-15: Determines the bypass source */ +#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK (0x3 << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) +# define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_REF_24M ((uint32_t)(0) << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) /* Select 24Mhz Osc as source */ +# define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_CLK1 ((uint32_t)(1) << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) /* Select the CLK1_N / CLK1_P as source */ +# define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_GPANAIO ((uint32_t)(2) << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) /* */ +# define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_CHRG_DET_B ((uint32_t)(3) << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) /* */ +#define CCM_ANALOG_PLL_SYS_BYPASS (1 << 16) /* Bit 16: Bypass the PLL */ + /* Bit 17: Reserved */ +#define CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN (1 << 18) /* Bit 18: Enables an offset in the phase frequency detector */ + /* Bits 19-30 Reserved */ +#define CCM_ANALOG_PLL_SYS_LOCK (1 << 31) /* Bit 31: PLL is currently locked */ + +/* 528MHz System PLL Spread Spectrum Register */ + +#define CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT (0) /* Bits 0-14: Frequency change step */ +#define CCM_ANALOG_PLL_SYS_SS_STEP_MASK (0x3FFF << CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT) +# define CCM_ANALOG_PLL_SYS_SS_STEP(n) ((uint32_t)(n) << CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT) +#define CCM_ANALOG_PLL_SYS_SS_ENABLE (1 << 15) /* Bit 15: Enable bit */ +#define CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT (0) /* Bits 16-31: Frequency change */ +#define CCM_ANALOG_PLL_SYS_SS_STOP_MASK (0xFFFF << CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT) +# define CCM_ANALOG_PLL_SYS_SS_STOP(n) ((uint32_t)(n) << CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT) + +/* Numerator of 528MHz System PLL Fractional Loop Divider Register */ + +#define CCM_ANALOG_PLL_SYS_NUM_A_SHIFT (0) /* Bits 0-29: 30 bit numerator (A) */ +#define CCM_ANALOG_PLL_SYS_NUM_A_MASK (0x3FFFFFFF << CCM_ANALOG_PLL_SYS_NUM_A_SHIFT) +#define CCM_ANALOG_PLL_SYS_NUM_A(n) ((uint32_t)(n) << CCM_ANALOG_PLL_SYS_NUM_A_SHIFT) + /* Bits 30-31: Reserved */ + +/* Denominator of 528MHz System PLL Fractional Loop Divider Register */ + +#define CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT (0) /* Bits 0-29: 30 bit numerator (A) */ +#define CCM_ANALOG_PLL_SYS_DENOM_B_MASK (0x3FFFFFFF << CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT) +#define CCM_ANALOG_PLL_SYS_DENOM_B(n) ((uint32_t)(n) << CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT) + /* Bits 30-31: Reserved */ + +/* Analog Audio PLL control Register */ + +#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT (0) /* Bits 0-6: This field controls the PLL loop divider: 27-54 */ +#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK (0x7f << CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT) +# define CCM_ANALOG_PLL_AUDIO_DIV_SELECT(n) ((uint32_t)(n) << CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT) + /* Bits 7-11: Reserved */ +#define CCM_ANALOG_PLL_AUDIO_POWERDOWN (1 << 12) /* Bit 12: Powers down the PLL */ +#define CCM_ANALOG_PLL_AUDIO_ENABLE (1 << 13) /* Bit 13: Enable PLL output */ +#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT (14) /* Bits 14-15: Determines the bypass source */ +#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK (0x3 << CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT) +# define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_REF_24M ((uint32_t)(0) << CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT) /* Select 24Mhz Osc as source */ +# define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_CLK1 ((uint32_t)(1) << CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT) /* Select the CLK1_N / CLK1_P as source */ +#define CCM_ANALOG_PLL_AUDIO_BYPASS (1 << 16) /* Bit 16: Bypass the PLL */ + /* Bit 17: Reserved */ +#define CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN (1 << 18) /* Bit 18: Enables an offset in the phase frequency detector */ +#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT (19) /* Bits 19-20: These bits implement a divider after the PLL */ +#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK (0x7f << CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT) +# define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_DIV4 ((uint32_t)(0) << CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT) +# define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_DIV2 ((uint32_t)(1) << CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT) +# define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_DIV1 ((uint32_t)(2) << CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT) + /* Bits 21-30: Reserved */ +#define CCM_ANALOG_PLL_AUDIO_LOCK (1 << 31) /* Bit 31: PLL is currently locked */ + +/* Numerator of Audio PLL Fractional Loop Divider Register */ + +#define CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT (0) /* Bits 0-29: 30 bit numerator (A) */ +#define CCM_ANALOG_PLL_AUDIO_NUM_A_MASK (0x3FFFFFFF << CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT) +#define CCM_ANALOG_PLL_AUDIO_NUM_A(n) ((uint32_t)(n) << CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT) +/* Bits 30-31: Reserved */ + +/* Denominator of Audio PLL Fractional Loop Divider Register */ + +#define CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT (0) /* Bits 0-29: 30 bit numerator (A) */ +#define CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK (0x3FFFFFFF << CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT) +#define CCM_ANALOG_PLL_AUDIO_DENOM_B(n) ((uint32_t)(n) << CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT) + /* Bits 30-31: Reserved */ +/* Analog Video PLL control Register */ + +#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT (0) /* Bits 0-6: This field controls the PLL loop divider: 27-54 */ +#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK (0x7f << CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT) +# define CCM_ANALOG_PLL_VIDEO_DIV_SELECT(n) ((uint32_t)(n) << CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT) + /* Bits 7-11: Reserved */ +#define CCM_ANALOG_PLL_VIDEO_POWERDOWN (1 << 12) /* Bit 12: Powers down the PLL */ +#define CCM_ANALOG_PLL_VIDEO_ENABLE (1 << 13) /* Bit 13: Enable PLL output */ +#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT (14) /* Bits 14-15: Determines the bypass source */ +#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK (0x3 << CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT) +# define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_REF_24M ((uint32_t)(0) << CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT) /* Select 24Mhz Osc as source */ +# define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_CLK1 ((uint32_t)(1) << CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT) /* Select the CLK1_N / CLK1_P as source */ +#define CCM_ANALOG_PLL_VIDEO_BYPASS (1 << 16) /* Bit 16: Bypass the PLL */ + /* Bit 17: Reserved */ +#define CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN (1 << 18) /* Bit 18: Enables an offset in the phase frequency detector */ +#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT (19) /* Bits 19-20: These bits implement a divider after the PLL */ +#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_MASK (0x7f << CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT) +# define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_DIV4 ((uint32_t)(0) << CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT) +# define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_DIV2 ((uint32_t)(1) << CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT) +# define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_DIV1 ((uint32_t)(2) << CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT) + /* Bits 21-30: Reserved */ +#define CCM_ANALOG_PLL_VIDEO_LOCK (1 << 31) /* Bit 31: PLL is currently locked */ + +/* Numerator of Video PLL Fractional Loop Divider Register */ + +#define CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT (0) /* Bits 0-29: 30 bit numerator (A) */ +#define CCM_ANALOG_PLL_VIDEO_NUM_A_MASK (0x3FFFFFFF << CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT) +#define CCM_ANALOG_PLL_VIDEO_NUM_A(n) ((uint32_t)(n) << CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT) + /* Bits 30-31: Reserved */ + +/* Denominator of Video PLL Fractional Loop Divider Register */ + +#define CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT (0) /* Bits 0-29: 30 bit numerator (A) */ +#define CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK (0x3FFFFFFF << CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT) +#define CCM_ANALOG_PLL_VIDEO_DENOM_B(n) ((uint32_t)(n) << CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT) + /* Bits 30-31: Reserved */ + +/* Analog ENET PLL Control Register */ + +#define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT (0) /* Bits 0-1: Controls the frequency of the ethernet0 reference clock */ +#define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_MASK (0x3 << CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT) +# define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_25MHZ ((uint32_t)(0) << CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT) +# define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_50MHZ ((uint32_t)(1) << CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT) +# define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_100MHZ ((uint32_t)(2) << CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT) +# define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_125MHZ ((uint32_t)(3) << CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT) +#define CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT (2) /* Bits 0-1: Controls the frequency of the ethernet1 reference clock */ +#define CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_MASK (0x3 << CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT) +# define CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_25MHZ ((uint32_t)(0) << CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT) +# define CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_50MHZ ((uint32_t)(1) << CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT) +# define CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_100MHZ ((uint32_t)(2) << CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT) +# define CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_125MHZ ((uint32_t)(3) << CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT) + /* Bits 4-11: Reserved */ +#define CCM_ANALOG_PLL_ENET_POWERDOWN (1 << 12) /* Bit 12: Powers down the PLL */ +#define CCM_ANALOG_PLL_ENET_ENET1_125M_EN (1 << 13) /* Bit 13: Enable the PLL providing the ENET1 125 MHz reference clock */ +#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT (14) /* Bits 14-15: Determines the bypass source */ +#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK (0x3 << CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT) +# define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_REF_24M ((uint32_t)(0) << CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT) /* Select 24Mhz Osc as source */ +# define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_CLK1 ((uint32_t)(1) << CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT) /* Select the CLK1_N / CLK1_P as source */ +#define CCM_ANALOG_PLL_ENET_BYPASS (1 << 16) /* Bit 16: Bypass the PLL */ + /* Bit 17: Reserved */ +#define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN (1 << 18) /* Bit 18: Enables an offset in the phase frequency detector */ +#define CCM_ANALOG_PLL_ENET_ENABLE_125M (1 << 19) /* Bit 19: */ +#define CCM_ANALOG_PLL_ENET_ENET2_125M_EN (1 << 20) /* Bit 20: Enable the PLL providing the ENET2 125 MHz reference clock */ +#define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN (1 << 21) /* Bit 21: Enable the PLL providing ENET 25 MHz reference clock */ +#define CCM_ANALOG_PLL_ENET_LOCK (1 << 31) /* Bit 31: PLL is currently locked */ + +/* 480MHz Clock (PLL3) Phase Fractional Divider Control Register */ + +#define CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT (0) /* Bits 0-5: This field controls the fractional divide value */ +#define CCM_ANALOG_PFD_480_PFD0_FRAC_MASK (0x3f << CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT) +# define CCM_ANALOG_PFD_480_PFD0_FRAC(n) ((uint32_t)(n) << CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT) +#define CCM_ANALOG_PFD_480_PFD0_STABLE (6) /* Bit 6: */ +#define CCM_ANALOG_PFD_480_PFD0_CLKGATE (7) /* Bit 7: If set to 1, the IO fractional divider clock is off */ +#define CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT (8) /* Bits 8-13: This field controls the fractional divide value */ +#define CCM_ANALOG_PFD_480_PFD1_FRAC_MASK (0x3f << CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT) +# define CCM_ANALOG_PFD_480_PFD1_FRAC(n) ((uint32_t)(n) << CCM_ANALOG_PFD_481_PFD1_FRAC_SHIFT) +#define CCM_ANALOG_PFD_480_PFD1_STABLE (14) /* Bit 14: */ +#define CCM_ANALOG_PFD_480_PFD1_CLKGATE (15) /* Bit 15: If set to 1, the IO fractional divider clock is off */ +#define CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT (16) /* Bits 8-21: This field controls the fractional divide value */ +#define CCM_ANALOG_PFD_480_PFD2_FRAC_MASK (0x3f << CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT) +# define CCM_ANALOG_PFD_480_PFD2_FRAC(n) ((uint32_t)(n) << CCM_ANALOG_PFD_482_PFD2_FRAC_SHIFT) +#define CCM_ANALOG_PFD_480_PFD2_STABLE (22) /* Bit 22: */ +#define CCM_ANALOG_PFD_480_PFD2_CLKGATE (23) /* Bit 23: If set to 1, the IO fractional divider clock is off */ +#define CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT (24) /* Bits 24-29: This field controls the fractional divide value */ +#define CCM_ANALOG_PFD_480_PFD3_FRAC_MASK (0x3f << CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT) +# define CCM_ANALOG_PFD_480_PFD3_FRAC(n) ((uint32_t)(n) << CCM_ANALOG_PFD_482_PFD3_FRAC_SHIFT) +#define CCM_ANALOG_PFD_480_PFD3_STABLE (30) /* Bit 30: */ +#define CCM_ANALOG_PFD_480_PFD3_CLKGATE (31) /* Bit 31: If set to 1, the IO fractional divider clock is off */ + +/* 528MHz Clock (PLL2) Phase Fractional Divider Control */ + +#define CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT (0) /* Bits 0-5: This field controls the fractional divide value */ +#define CCM_ANALOG_PFD_528_PFD0_FRAC_MASK (0x3f << CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT) +# define CCM_ANALOG_PFD_528_PFD0_FRAC(n) ((uint32_t)(n) << CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT) +#define CCM_ANALOG_PFD_528_PFD0_STABLE (6) /* Bit 6: */ +#define CCM_ANALOG_PFD_528_PFD0_CLKGATE (7) /* Bit 7: If set to 1, the IO fractional divider clock is off */ +#define CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT (8) /* Bits 8-13: This field controls the fractional divide value */ +#define CCM_ANALOG_PFD_528_PFD1_FRAC_MASK (0x3f << CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT) +# define CCM_ANALOG_PFD_528_PFD1_FRAC(n) ((uint32_t)(n) << CCM_ANALOG_PFD_481_PFD1_FRAC_SHIFT) +#define CCM_ANALOG_PFD_528_PFD1_STABLE (14) /* Bit 14: */ +#define CCM_ANALOG_PFD_528_PFD1_CLKGATE (15) /* Bit 15: If set to 1, the IO fractional divider clock is off */ +#define CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT (16) /* Bits 8-21: This field controls the fractional divide value */ +#define CCM_ANALOG_PFD_528_PFD2_FRAC_MASK (0x3f << CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT) +# define CCM_ANALOG_PFD_528_PFD2_FRAC(n) ((uint32_t)(n) << CCM_ANALOG_PFD_482_PFD2_FRAC_SHIFT) +#define CCM_ANALOG_PFD_528_PFD2_STABLE (22) /* Bit 22: */ +#define CCM_ANALOG_PFD_528_PFD2_CLKGATE (23) /* Bit 23: If set to 1, the IO fractional divider clock is off */ +#define CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT (24) /* Bits 24-29: This field controls the fractional divide value */ +#define CCM_ANALOG_PFD_528_PFD3_FRAC_MASK (0x3f << CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT) +# define CCM_ANALOG_PFD_528_PFD3_FRAC(n) ((uint32_t)(n) << CCM_ANALOG_PFD_482_PFD3_FRAC_SHIFT) +#define CCM_ANALOG_PFD_528_PFD3_STABLE (30) /* Bit 30: */ +#define CCM_ANALOG_PFD_528_PFD3_CLKGATE (31) /* Bit 31: If set to 1, the IO fractional divider clock is off */ + +/* Miscellaneous Register 0 */ + +#define CCM_ANALOG_MISC0_REFTOP_PWD (1 << 0) /* Bit 0: Control bit to power-down the analog bandgap reference circuitry */ + /* Bits 1-2: Reserved */ +#define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF (1 << 2) /* Bit 3: Control bit to disable the self-bias circuit in the analog bandgap */ +#define CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT (4) /* Bits 4-6: VBG (PMU) */ +#define CCM_ANALOG_MISC0_REFTOP_VBGADJ_MASK (0x3 << CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT) +# define CCM_ANALOG_MISC0_REFTOP_VBGADJ(n) ((uint32_t)(n) << CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT) +#define CCM_ANALOG_MISC0_REFTOP_VBGUP (1 << 7) /* Bit 7: Status bit that signals the analog bandgap voltage is up and stable */ + /* Bits 8-9: Reserved */ +#define CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT (10) /* Bits 10-11: Configure the analog behavior in stop mode */ +#define CCM_ANALOG_MISC0_STOP_MODE_CONFIG_MASK (0x3 << CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT) +# define CCM_ANALOG_MISC0_STOP_MODE_CONFIG(n) ((uint32_t)(n) << CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT) +#define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS (1 << 12) /* Bit 12: This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN */ +#define CCM_ANALOG_MISC0_OSC_I_SHIFT (13) /* Bits 13-14: This field determines the bias current in the 24MHz oscillator */ +#define CCM_ANALOG_MISC0_OSC_I_MASK (0x3 << CCM_ANALOG_MISC0_OSC_I_SHIFT) +# define CCM_ANALOG_MISC0_OSC_I(n) ((uint32_t)(n) << CCM_ANALOG_MISC0_OSC_I_SHIFT) +#define CCM_ANALOG_MISC0_OSC_XTALOK (1 << 15) /* Bit 15: bit that signals 24-MHz crystal oscillator is stable */ +#define CCM_ANALOG_MISC0_OSC_XTALOK_EN (1 << 16) /* Bit 16: enables the detector that signals 24MHz crystal oscillator is stable */ + /* Bits 17-24: Reserved */ +#define CCM_ANALOG_MISC0_CLKGATE_CTRL (1 << 25) /* Bit 25: This bit allows disabling the clock gate */ +#define CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT (26) /* Bits 26-28: delay powering up the XTAL 24MHz */ +#define CCM_ANALOG_MISC0_CLKGATE_DELAY_MASK (0x7 << CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT) +# define CCM_ANALOG_MISC0_CLKGATE_DELAY(n) ((uint32_t)(n) << CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT) +#define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE (1 << 29) /* Bit 29: which chip source is being used for the rtc clock */ +#define CCM_ANALOG_MISC0_XTAL_24M_PWD (1 << 30) /* Bit 30: power down the 24M crystal oscillator if set true */ +#define CCM_ANALOG_MISC0_VID_PLL_PREDIV (1 << 31) /* Bit 31: Predivider for the source clock of the PLL's */ +#define CCM_ANALOG_MISC0_VID_PLL_PREDIV_1 (0 << 31) /* Bit 31: Predivider for the source clock of the PLL's */ +#define CCM_ANALOG_MISC0_VID_PLL_PREDIV_2 (1 << 31) /* Bit 31: Predivider for the source clock of the PLL's */ + +/* Miscellaneous Register 1 */ + +#define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT (0) /* Bits 0-4: This field selects the clk to be routed to anaclk1/1b */ +#define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK (0x1f << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) +# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_ARM_PLL ((uint32_t)(0) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) +# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SYS_PLL ((uint32_t)(1) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) +# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_PFD4 ((uint32_t)(2) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) +# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_PFD5 ((uint32_t)(3) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) +# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_PFD6 ((uint32_t)(4) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) +# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_PFD7 ((uint32_t)(5) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) +# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_AUDIO_PLL ((uint32_t)(6) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) +# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_VIDEO_PLL ((uint32_t)(7) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) +# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_ETHERNET_REF ((uint32_t)(9) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) +# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_USB1_PLL ((uint32_t)(12) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) +# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_USB2_PLL ((uint32_t)(13) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) +# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_PFD0 ((uint32_t)(14) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) +# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_PFD1 ((uint32_t)(15) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) +# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_PFD2 ((uint32_t)(16) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) +# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_PFD3 ((uint32_t)(17) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) +# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_XTAL ((uint32_t)(18) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) + /* Bits 5-9: Reserved */ +#define CCM_ANALOG_MISC1_LVDSCLK1_OBEN (1 << 10) /* Bit 10: This enables the LVDS output buffer for anaclk1/1b */ + /* Bit 11: Reserved */ +#define CCM_ANALOG_MISC1_LVDSCLK1_IBEN (1 << 12) /* Bit 12: This enables the LVDS input buffer for anaclk1/1b */ + /* Bits 13-15: Reserved */ +#define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN (1 << 16) /* Bit 16: */ +#define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN (1 << 17) /* Bit 17: */ + /* Bits 18-26: Reserved */ +#define CCM_ANALOG_MISC1_IRQ_TEMPPANIC (1 << 27) /* Bit 27: temperature sensor panic interrupt */ +#define CCM_ANALOG_MISC1_IRQ_TEMPLOW (1 << 28) /* Bit 28: temperature sensor low interrupt */ +#define CCM_ANALOG_MISC1_IRQ_TEMPHIGH (1 << 29) /* Bit 29: temperature sensor high interrupt */ +#define CCM_ANALOG_MISC1_IRQ_ANA_BO (1 << 30) /* Bit 30: analog regulator brownout interrupt */ +#define CCM_ANALOG_MISC1_IRQ_DIG_BO (1 << 31) /* Bit 31: digital regulator brownout interrupt */ + +/* Miscellaneous Register 2 */ + +#define CCM_ANALOG_MISC1_REG0_BO_OFFSET_SHIFT (0) /* Bits 0-2: This field defines the brown out voltage offset */ +#define CCM_ANALOG_MISC1_REG0_BO_OFFSET_MASK (0x7 << CCM_ANALOG_MISC1_REG0_BO_OFFSET_SHIFT) +# define CCM_ANALOG_MISC1_REG0_BO_OFFSET_0_100 ((uint32_t)(0) << CCM_ANALOG_MISC1_REG0_BO_OFFSET_SHIFT) +# define CCM_ANALOG_MISC1_REG0_BO_OFFSET_0_175 ((uint32_t)(1) << CCM_ANALOG_MISC1_REG0_BO_OFFSET_SHIFT) +#define CCM_ANALOG_MISC1_REG0_BO_STATUS (1 << 3) /* Bit 3: Reg0 brownout status bit */ + /* Bit 4: Reserved */ +#define CCM_ANALOG_MISC1_REG0_ENABLE_BO (1 << 5) /* Bit 5: Enables the brownout detection */ +#define CCM_ANALOG_MISC1_REG0_OK (1 << 6) /* Bit 6: ARM supply */ +#define CCM_ANALOG_MISC1_PLL3_DISABLE (1 << 7) /* Bit 7: PLL3 can be disabled when the SoC is not in any low power mode */ +#define CCM_ANALOG_MISC1_REG1_BO_OFFSET_SHIFT (8) /* Bits 8-10: This field defines the brown out voltage offset */ +#define CCM_ANALOG_MISC1_REG1_BO_OFFSET_MASK (0x7 << CCM_ANALOG_MISC1_REG1_BO_OFFSET_SHIFT) +# define CCM_ANALOG_MISC1_REG1_BO_OFFSET_0_100 ((uint32_t)(0) << CCM_ANALOG_MISC1_REG1_BO_OFFSET_SHIFT) +# define CCM_ANALOG_MISC1_REG1_BO_OFFSET_0_175 ((uint32_t)(1) << CCM_ANALOG_MISC1_REG1_BO_OFFSET_SHIFT) +#define CCM_ANALOG_MISC1_REG1_BO_STATUS (1 << 11) /* Bit 11: Reg1 brownout status bit */ + /* Bit 12: Reserved */ +#define CCM_ANALOG_MISC1_REG1_ENABLE_BO (1 << 13) /* Bit 13: Enables the brownout detection */ +#define CCM_ANALOG_MISC1_REG1_OK (1 << 14) /* Bit 14: GPU/VPU supply */ +#define CCM_ANALOG_MISC1_AUDIO_DIV_LSB (1 << 15) /* Bit 15: LSB of Post-divider for Audio PLL */ + +#define CCM_ANALOG_MISC1_REG2_BO_OFFSET_SHIFT (16) /* Bits 16-18: This field defines the brown out voltage offset */ +#define CCM_ANALOG_MISC1_REG2_BO_OFFSET_MASK (0x7 << CCM_ANALOG_MISC1_REG2_BO_OFFSET_SHIFT) +# define CCM_ANALOG_MISC1_REG2_BO_OFFSET_0_100 ((uint32_t)(0) << CCM_ANALOG_MISC1_REG2_BO_OFFSET_SHIFT) +# define CCM_ANALOG_MISC1_REG2_BO_OFFSET_0_175 ((uint32_t)(1) << CCM_ANALOG_MISC1_REG2_BO_OFFSET_SHIFT) +#define CCM_ANALOG_MISC1_REG2_BO_STATUS (1 << 19) /* Bit 19: Reg2 brownout status bit */ + /* Bit 20: Reserved */ +#define CCM_ANALOG_MISC1_REG2_ENABLE_BO (1 << 21) /* Bit 21: Enables the brownout detection */ +#define CCM_ANALOG_MISC1_REG2_OK (1 << 22) /* Bit 22: voltage is above the brownout level for the SOC supply */ +#define CCM_ANALOG_MISC1_AUDIO_DIV_MSB (1 << 23) /* Bit 23: MSB of Post-divider for Audio PLL */ +#define CCM_ANALOG_MISC1_REG0_STEP_TIME_SHIFT (24) /* Bits 24-25: Number of clock periods (24MHz clock) */ +#define CCM_ANALOG_MISC1_REG0_STEP_TIME_MASK (0x3 << CCM_ANALOG_MISC1_REG0_STEP_TIME_SHIFT) +# define CCM_ANALOG_MISC1_REG0_STEP_TIME_64 ((uint32_t)(0) << CCM_ANALOG_MISC1_REG0_STEP_TIME_SHIFT) +# define CCM_ANALOG_MISC1_REG0_STEP_TIME_128 ((uint32_t)(1) << CCM_ANALOG_MISC1_REG0_STEP_TIME_SHIFT) +# define CCM_ANALOG_MISC1_REG0_STEP_TIME_256 ((uint32_t)(2) << CCM_ANALOG_MISC1_REG0_STEP_TIME_SHIFT) +# define CCM_ANALOG_MISC1_REG0_STEP_TIME_512 ((uint32_t)(3) << CCM_ANALOG_MISC1_REG0_STEP_TIME_SHIFT) +#define CCM_ANALOG_MISC1_REG1_STEP_TIME_SHIFT (26) /* Bits 26-27: Number of clock periods (24MHz clock) */ +#define CCM_ANALOG_MISC1_REG1_STEP_TIME_MASK (0x3 << CCM_ANALOG_MISC1_REG1_STEP_TIME_SHIFT) +# define CCM_ANALOG_MISC1_REG1_STEP_TIME_64 ((uint32_t)(0) << CCM_ANALOG_MISC1_REG1_STEP_TIME_SHIFT) +# define CCM_ANALOG_MISC1_REG1_STEP_TIME_128 ((uint32_t)(1) << CCM_ANALOG_MISC1_REG1_STEP_TIME_SHIFT) +# define CCM_ANALOG_MISC1_REG1_STEP_TIME_256 ((uint32_t)(2) << CCM_ANALOG_MISC1_REG1_STEP_TIME_SHIFT) +# define CCM_ANALOG_MISC1_REG1_STEP_TIME_512 ((uint32_t)(3) << CCM_ANALOG_MISC1_REG1_STEP_TIME_SHIFT) +#define CCM_ANALOG_MISC1_REG2_STEP_TIME_SHIFT (28) /* Bits 28-29: Number of clock periods (24MHz clock) */ +#define CCM_ANALOG_MISC1_REG2_STEP_TIME_MASK (0x3 << CCM_ANALOG_MISC1_REG2_STEP_TIME_SHIFT) +# define CCM_ANALOG_MISC1_REG2_STEP_TIME_64 ((uint32_t)(0) << CCM_ANALOG_MISC1_REG2_STEP_TIME_SHIFT) +# define CCM_ANALOG_MISC1_REG2_STEP_TIME_128 ((uint32_t)(1) << CCM_ANALOG_MISC1_REG2_STEP_TIME_SHIFT) +# define CCM_ANALOG_MISC1_REG2_STEP_TIME_256 ((uint32_t)(2) << CCM_ANALOG_MISC1_REG2_STEP_TIME_SHIFT) +# define CCM_ANALOG_MISC1_REG2_STEP_TIME_512 ((uint32_t)(3) << CCM_ANALOG_MISC1_REG2_STEP_TIME_SHIFT) + +#define CCM_ANALOG_MISC1_VIDEO_DIV_SHIFT (30) /* Bits 30-31: Post-divider for video */ +#define CCM_ANALOG_MISC1_VIDEO_DIV_MASK (0x3 << CCM_ANALOG_MISC1_VIDEO_DIV_SHIFT) +# define CCM_ANALOG_MISC1_VIDEO_DIV(n) ((uint32_t)(0) << CCM_ANALOG_MISC1_VIDEO_DIV_SHIFT) + +#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_CCM_H */ diff --git a/arch/arm/src/imxrt/chip/imxrt_dcdc.h b/arch/arm/src/imxrt/chip/imxrt_dcdc.h new file mode 100644 index 00000000000..28d3c758adb --- /dev/null +++ b/arch/arm/src/imxrt/chip/imxrt_dcdc.h @@ -0,0 +1,152 @@ +/**************************************************************************************************** + * arch/arm/src/imxrt/imxrt_dcdc.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Janne Rosberg + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_DCDC_H +#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_DCDC_H + +/**************************************************************************************************** + * Included Files + ****************************************************************************************************/ + +#include +#include "chip/imxrt_memorymap.h" + +/**************************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************************/ + +/* Register offsets *********************************************************************************/ + +#define IMXRT_DCDC_REG0_OFFSET 0x0000 /* DCDC Register 0 */ +#define IMXRT_DCDC_REG1_OFFSET 0x0004 /* DCDC Register 1 */ +#define IMXRT_DCDC_REG2_OFFSET 0x0008 /* DCDC Register 2 */ +#define IMXRT_DCDC_REG3_OFFSET 0x000c /* DCDC Register 3 */ + +/* Register addresses *******************************************************************************/ + +#define IMXRT_DCDC_REG0 (IMXRT_DCDC_BASE + IMXRT_DCDC_REG0_OFFSET) +#define IMXRT_DCDC_REG1 (IMXRT_DCDC_BASE + IMXRT_DCDC_REG1_OFFSET) +#define IMXRT_DCDC_REG2 (IMXRT_DCDC_BASE + IMXRT_DCDC_REG2_OFFSET) +#define IMXRT_DCDC_REG3 (IMXRT_DCDC_BASE + IMXRT_DCDC_REG3_OFFSET) + +/* Register bit definitions *************************************************************************/ + +/* Register 0 */ + +#define DCDC_REG0_PWD_ZCD (1 << 0) /* Bit 0: Power down the zero cross detection */ +#define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH (1 << 1) /* Bit 1: Disable automatic clock switch */ +#define DCDC_REG0_SEL_CLK (1 << 2) /* Bit 2: Select 24 MHz Crystal clock */ +#define DCDC_REG0_PWD_OSC_INT (1 << 3) /* Bit 3: Power down internal osc */ +#define DCDC_REG0_PWD_CUR_SNS_CMP (1 << 4) /* Bit 4: The power down signal of the current detector */ +#define DCDC_REG0_CUR_SNS_THRSH_SHIFT (5) /* Bits 5-7: threshold of current detector */ +#define DCDC_REG0_CUR_SNS_THRSH_MASK (0x7 << DCDC_REG0_CUR_SNS_THRSH_SHIFT) +# define DCDC_REG0_CUR_SNS_THRSH_150MA ((uint32_t)(0) << DCDC_REG0_CUR_SNS_THRSH_SHIFT) +# define DCDC_REG0_CUR_SNS_THRSH_250MA ((uint32_t)(1) << DCDC_REG0_CUR_SNS_THRSH_SHIFT) +# define DCDC_REG0_CUR_SNS_THRSH_350MA ((uint32_t)(2) << DCDC_REG0_CUR_SNS_THRSH_SHIFT) +# define DCDC_REG0_CUR_SNS_THRSH_450MA ((uint32_t)(3) << DCDC_REG0_CUR_SNS_THRSH_SHIFT) +# define DCDC_REG0_CUR_SNS_THRSH_550MA ((uint32_t)(4) << DCDC_REG0_CUR_SNS_THRSH_SHIFT) +# define DCDC_REG0_CUR_SNS_THRSH_650MA ((uint32_t)(5) << DCDC_REG0_CUR_SNS_THRSH_SHIFT) +#define DCDC_REG0_PWD_OVERCUR_DET (1 << 8) /* Bit 8: Power down overcurrent detection comparator */ +#define DCDC_REG0_OVERCUR_TIRG_ADJ_SHIFT (9) /* Bits 9-10: The threshold of over current detection */ +#define DCDC_REG0_OVERCUR_TIRG_ADJ_MASK (0x3 << DCDC_REG0_OVERCUR_TIRG_ADJ_SHIFT) +# define DCDC_REG0_OVERCUR_TIRG_ADJ_1A_025 ((uint32_t)(0) << DCDC_REG0_OVERCUR_TIRG_ADJ_SHIFT) +# define DCDC_REG0_OVERCUR_TIRG_ADJ_2A_025 ((uint32_t)(1) << DCDC_REG0_OVERCUR_TIRG_ADJ_SHIFT) +# define DCDC_REG0_OVERCUR_TIRG_ADJ_1A_02 ((uint32_t)(2) << DCDC_REG0_OVERCUR_TIRG_ADJ_SHIFT) +# define DCDC_REG0_OVERCUR_TIRG_ADJ_2A_02 ((uint32_t)(3) << DCDC_REG0_OVERCUR_TIRG_ADJ_SHIFT) +#define DCDC_REG0_PWD_CMP_BATT_DET (1 << 11) /* Bit 11: Power down the low voltage detection comparator */ +#define DCDC_REG0_ADJ_POSLIMIT_BUCK_SHIFT (12) /* Bits 12-15: Adjust value to poslimit_buck register */ +#define DCDC_REG0_ADJ_POSLIMIT_BUCK_MASK (0xf << DCDC_REG0_ADJ_POSLIMIT_BUCK_SHIFT) +# define DCDC_REG0_ADJ_POSLIMIT_BUCK(n) ((uint32_t)(n) << DCDC_REG0_ADJ_POSLIMIT_BUCK_SHIFT) +#define DCDC_REG0_EN_LP_OVERLOAD_SNS (1 << 16) /* Bit 16: Enable the overload detection in power save mode */ +#define DCDC_REG0_PWD_HIGH_VOLT_DET (1 << 17) /* Bit 17: Power down overvoltage detection comparator */ +#define DCDC_REG0_LP_OVERLOAD_THRSH_SHIFT (18) /* Bits 18-19: the threshold of the counting number */ +#define DCDC_REG0_LP_OVERLOAD_THRSH_MASK (0x3 << DCDC_REG0_LP_OVERLOAD_THRSH_SHIFT) +# define DCDC_REG0_LP_OVERLOAD_THRSH_32 ((uint32_t)(0) << DCDC_REG0_LP_OVERLOAD_THRSH_SHIFT) +# define DCDC_REG0_LP_OVERLOAD_THRSH_64 ((uint32_t)(1) << DCDC_REG0_LP_OVERLOAD_THRSH_SHIFT) +# define DCDC_REG0_LP_OVERLOAD_THRSH_16 ((uint32_t)(2) << DCDC_REG0_LP_OVERLOAD_THRSH_SHIFT) +# define DCDC_REG0_LP_OVERLOAD_THRSH_8 ((uint32_t)(3) << DCDC_REG0_LP_OVERLOAD_THRSH_SHIFT) +#define DCDC_REG0_LP_OVERLOAD_FREQ_SEL (1 << 20) /* Bit 20: The period of counting the charging times in power save mode */ +#define DCDC_REG0_LP_OVERLOAD_FREQ_SEL_8 (0 << 20) /* Bit 20: The period of counting the charging times in power save mode */ +#define DCDC_REG0_LP_OVERLOAD_FREQ_SEL_16 (1 << 20) /* Bit 20: Fhe period of counting the charging times in power save mode */ +#define DCDC_REG0_LP_HIGH_HYS (1 << 21) /* Bit 21: Adjust hysteretic value in low power from 12.5mV to 25mV */ + /* Bits 22-26 Reserved */ +#define DCDC_REG0_XTALOK_DISABLE (1 << 27) /* Bit 27: Disable xtalok detection circuit */ +#define DCDC_REG0_CURRENT_ALERT_RESET (1 << 28) /* Bit 28: Reset current alert signal */ +#define DCDC_REG0_XTAL_24M_OK (1 << 29) /* Bit 29: Set to 1 to switch internal ring osc to xtal 24M */ + /* Bit 30: Reserved */ +#define DCDC_REG0_STS_DC_OK (1 << 31) /* Bit 31: Status register to indicate DCDC status */ + +/* Register 1 */ + +#define DCDC_REG1_POSLIMIT_BUCK_IN_SHIFT (0) /* Bits 0-6: Upper limit duty cycle limit in DC-DC converter */ +#define DCDC_REG1_POSLIMIT_BUCK_IN_MASK (0x7f << DCDC_REG1_POSLIMIT_BUCK_IN_SHIFT) +# define DCDC_REG1_POSLIMIT_BUCK_IN(n) ((uint32_t)(n) << DCDC_REG1_POSLIMIT_BUCK_IN_SHIFT) +#define DCDC_REG1_REG_FBK_SEL_SHIFT (7) /* Bits 7-8: Select the feedback point of the internal regulator */ +#define DCDC_REG1_REG_FBK_SEL_MASK (0x3 << DCDC_REG1_REG_FBK_SEL_SHIFT) +# define DCDC_REG1_REG_FBK_SEL(n) ((uint32_t)(n) << DCDC_REG1_REG_FBK_SEL_SHIFT) + /* Bits 9-11: Reserved */ +#define DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT (12) /* Bits 12-13: Set the current bias of low power comparator */ +#define DCDC_REG1_LP_CMP_ISRC_SEL_MASK (0x3 << DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT) +# define DCDC_REG1_LP_CMP_ISRC_SEL(n) ((uint32_t)(n) << DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT) +#define DCDC_REG1_NEGLIMIT_IN_SHIFT (14) /* Bits 14-20: Set the current bias of low power comparator */ +#define DCDC_REG1_NEGLIMIT_IN_MASK (0x3f << DCDC_REG1_NEGLIMIT_IN_SHIFT) +# define DCDC_REG1_NEGLIMIT_IN(n) ((uint32_t)(n) << DCDC_REG1_NEGLIMIT_IN_SHIFT) +#define DCDC_REG1_LOOPCTRL_HST_THRESH (1 << 21) /* Bit 21: Increase the threshold detection for common mode analog comparator */ + /* Bit 22: Reserved */ +#define DCDC_REG1_LOOPCTRL_EN_HYST (1 << 23) /* Bit 23: Enable hysteresis in switching converter */ +#define DCDC_REG1_VBG_TRIM_SHIFT (24) /* Bits 24-28: Trim bandgap voltage */ +#define DCDC_REG1_VBG_TRIM_MASK (0x1f << DCDC_REG1_VBG_TRIM_SHIFT) +# define DCDC_REG1_VBG_TRIM(n) ((uint32_t)(n) << DCDC_REG1_VBG_TRIM_SHIFT) + /* Bit 29-31: Reserved */ + +/* Register 3 */ + +#define DCDC_REG3_TRG_SHIFT (0) /* Bits 0-4: Target value of VDD_SOC, 25 mV each step */ +#define DCDC_REG3_TRG_MASK (0x1f << DCDC_REG3_TRG_SHIFT) +# define DCDC_REG3_TRG(n) ((uint32_t)(n) << DCDC_REG3_TRG_SHIFT) + /* Bit 5-7: Reserved */ +#define DCDC_REG3_TARGET_LP_SHIFT (8) /* Bits 8-10: Target value of standby (low power) mode */ +#define DCDC_REG3_TARGET_LP_MASK (0x7 << DCDC_REG3_TARGET_LP_SHIFT) +# define DCDC_REG3_TARGET_LP_(n) ((uint32_t)(n) << DCDC_REG3_TARGET_LP_SHIFT) + /* Bit 11-23: Reserved */ +#define DCDC_REG3_MINPWR_DC_HALFCLK (1 << 24) /* Bit 24: Set DCDC clock to half freqeuncy for continuous mode */ + /* Bit 25-26: Reserved */ +#define DCDC_REG3_MISC_DELAY_TIMING (1 << 27) /* Bit 27: Adjust delay to reduce ground noise */ +#define DCDC_REG3_MISC_DISABLE_FET_LOGIC (1 << 28) /* Bit 28: Datasheet: reserved? */ + /* Bit 29: Reserved */ +#define DCDC_REG3_DISABLE_STEP (1 << 30) /* Bit 30: Disable stepping */ + /* Bit 31: Reserved */ + +#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_DCDC_H */ diff --git a/arch/arm/src/imxrt/chip/imxrt_gpio.h b/arch/arm/src/imxrt/chip/imxrt_gpio.h new file mode 100644 index 00000000000..3dd363c20a3 --- /dev/null +++ b/arch/arm/src/imxrt/chip/imxrt_gpio.h @@ -0,0 +1,136 @@ +/******************************************************************************************** + * arch/arm/src/imxrt/imxrt_gpio.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ********************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_GPIO_H +#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_GPIO_H + +/******************************************************************************************** + * Included Files + ********************************************************************************************/ + +#include +#include "chip/imxrt_memorymap.h" + +/******************************************************************************************** + * Pre-processor Definitions + ********************************************************************************************/ + +#define GPIO1 0 /* Port 1 index */ +#define GPIO2 1 /* Port 2 index */ +#define GPIO3 2 /* Port 3 index */ +#define GPIO4 3 /* Port 4 index */ + +#define IMXRT_GPIO_NPORTS 4 /* Four total ports */ +#define IMXRT_GPIO_NPINS 32 /* Up to 32 pins per port */ + +/* Register offsets *************************************************************************/ + +#define IMXRT_GPIO_DR_OFFSET 0x0000 /* GPIO data register */ +#define IMXRT_GPIO_GDIR_OFFSET 0x0004 /* GPIO direction register */ +#define IMXRT_GPIO_PSR_OFFSET 0x0008 /* GPIO pad status register */ +#define IMXRT_GPIO_ICR1_OFFSET 0x000c /* GPIO interrupt configuration register1 */ +#define IMXRT_GPIO_ICR2_OFFSET 0x0010 /* GPIO interrupt configuration register2 */ +#define IMXRT_GPIO_IMR_OFFSET 0x0014 /* GPIO interrupt mask register */ +#define IMXRT_GPIO_ISR_OFFSET 0x0018 /* GPIO interrupt status register */ +#define IMXRT_GPIO_EDGE_OFFSET 0x001c /* GPIO edge select register */ + +/* Register addresses ***********************************************************************/ + +#define IMXRT_GPIO_DR(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_DR_OFFSET) +#define IMXRT_GPIO_GDIR(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_GDIR_OFFSET) +#define IMXRT_GPIO_PSR(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_PSR_OFFSET) +#define IMXRT_GPIO_ICR1(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_ICR1_OFFSET) +#define IMXRT_GPIO_ICR2(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_ICR2_OFFSET) +#define IMXRT_GPIO_IMR(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_IMR_OFFSET) +#define IMXRT_GPIO_ISR(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_ISR_OFFSET) +#define IMXRT_GPIO_EDGE(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_EDGE_OFFSET) + +#define IMXRT_GPIO1_DR (IMXRT_GPIO1_BASE + IMXRT_GPIO_DR_OFFSET) +#define IMXRT_GPIO1_GDIR (IMXRT_GPIO1_BASE + IMXRT_GPIO_GDIR_OFFSET) +#define IMXRT_GPIO1_PSR (IMXRT_GPIO1_BASE + IMXRT_GPIO_PSR_OFFSET) +#define IMXRT_GPIO1_ICR1 (IMXRT_GPIO1_BASE + IMXRT_GPIO_ICR1_OFFSET) +#define IMXRT_GPIO1_ICR2 (IMXRT_GPIO1_BASE + IMXRT_GPIO_ICR2_OFFSET) +#define IMXRT_GPIO1_IMR (IMXRT_GPIO1_BASE + IMXRT_GPIO_IMR_OFFSET) +#define IMXRT_GPIO1_ISR (IMXRT_GPIO1_BASE + IMXRT_GPIO_ISR_OFFSET) +#define IMXRT_GPIO1_EDGE (IMXRT_GPIO1_BASE + IMXRT_GPIO_EDGE_OFFSET) + +#define IMXRT_GPIO2_DR (IMXRT_GPIO2_BASE + IMXRT_GPIO_DR_OFFSET) +#define IMXRT_GPIO2_GDIR (IMXRT_GPIO2_BASE + IMXRT_GPIO_GDIR_OFFSET) +#define IMXRT_GPIO2_PSR (IMXRT_GPIO2_BASE + IMXRT_GPIO_PSR_OFFSET) +#define IMXRT_GPIO2_ICR1 (IMXRT_GPIO2_BASE + IMXRT_GPIO_ICR1_OFFSET) +#define IMXRT_GPIO2_ICR2 (IMXRT_GPIO2_BASE + IMXRT_GPIO_ICR2_OFFSET) +#define IMXRT_GPIO2_IMR (IMXRT_GPIO2_BASE + IMXRT_GPIO_IMR_OFFSET) +#define IMXRT_GPIO2_ISR (IMXRT_GPIO2_BASE + IMXRT_GPIO_ISR_OFFSET) +#define IMXRT_GPIO2_EDGE (IMXRT_GPIO2_BASE + IMXRT_GPIO_EDGE_OFFSET) + +#define IMXRT_GPIO3_DR (IMXRT_GPIO3_BASE + IMXRT_GPIO_DR_OFFSET) +#define IMXRT_GPIO3_GDIR (IMXRT_GPIO3_BASE + IMXRT_GPIO_GDIR_OFFSET) +#define IMXRT_GPIO3_PSR (IMXRT_GPIO3_BASE + IMXRT_GPIO_PSR_OFFSET) +#define IMXRT_GPIO3_ICR1 (IMXRT_GPIO3_BASE + IMXRT_GPIO_ICR1_OFFSET) +#define IMXRT_GPIO3_ICR2 (IMXRT_GPIO3_BASE + IMXRT_GPIO_ICR2_OFFSET) +#define IMXRT_GPIO3_IMR (IMXRT_GPIO3_BASE + IMXRT_GPIO_IMR_OFFSET) +#define IMXRT_GPIO3_ISR (IMXRT_GPIO3_BASE + IMXRT_GPIO_ISR_OFFSET) +#define IMXRT_GPIO3_EDGE (IMXRT_GPIO3_BASE + IMXRT_GPIO_EDGE_OFFSET) + +#define IMXRT_GPIO4_DR (IMXRT_GPIO4_BASE + IMXRT_GPIO_DR_OFFSET) +#define IMXRT_GPIO4_GDIR (IMXRT_GPIO4_BASE + IMXRT_GPIO_GDIR_OFFSET) +#define IMXRT_GPIO4_PSR (IMXRT_GPIO4_BASE + IMXRT_GPIO_PSR_OFFSET) +#define IMXRT_GPIO4_ICR1 (IMXRT_GPIO4_BASE + IMXRT_GPIO_ICR1_OFFSET) +#define IMXRT_GPIO4_ICR2 (IMXRT_GPIO4_BASE + IMXRT_GPIO_ICR2_OFFSET) +#define IMXRT_GPIO4_IMR (IMXRT_GPIO4_BASE + IMXRT_GPIO_IMR_OFFSET) +#define IMXRT_GPIO4_ISR (IMXRT_GPIO4_BASE + IMXRT_GPIO_ISR_OFFSET) +#define IMXRT_GPIO4_EDGE (IMXRT_GPIO4_BASE + IMXRT_GPIO_EDGE_OFFSET) + +/* Register bit definitions *****************************************************************/ + +/* Most registers are laid out simply with one bit per pin */ + +#define GPIO_PIN(n) (1 << (n)) /* Bit n: Pin n, n=0-31 */ + +/* GPIO interrupt configuration register 1/2 */ + +#define GPIO_ICR_INDEX(n) (((n) >> 4) & 1) +#define GPIO_ICR_OFFSET(n) (GPIO_ICR1_OFFSET + (GPIO_ICR_INDEX(n) << 2)) + +#define GPIO_ICR_LOWLEVEL 0 /* Interrupt is low-level sensitive */ +#define GPIO_ICR_HIGHLEVEL 1 /* Interrupt is high-level sensitive */ +#define GPIO_ICR_RISINGEDGE 2 /* Interrupt is rising-edge sensitive */ +#define GPIO_ICR_FALLINGEDGE 3 /* Interrupt is falling-edge sensitive */ + +#define GPIO_ICR_SHIFT(n) (((n) & 15) << 1) +#define GPIO_ICR_MASK(n) (3 << GPIO_ICR_SHIFT(n)) +#define GPIO_ICR(i,n) ((uint32_t)(i) << GPIO_ICR_SHIFT(n)) + +#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_GPIO_H */ diff --git a/arch/arm/src/imxrt/chip/imxrt_iomuxc.h b/arch/arm/src/imxrt/chip/imxrt_iomuxc.h new file mode 100644 index 00000000000..4e4f00904ac --- /dev/null +++ b/arch/arm/src/imxrt/chip/imxrt_iomuxc.h @@ -0,0 +1,1400 @@ +/************************************************************************************ + * arch/arm/src/imxrt/imxrt_iomuxc.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_IOMUXC_H +#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_IOMUXC_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include "chip/imxrt_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ + +#define IMXRT_IOMUXC_GPR_GPR0_OFFSET 0x0000 /* GPR0 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR1_OFFSET 0x0004 /* GPR1 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR2_OFFSET 0x0008 /* GPR2 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR3_OFFSET 0x000c /* GPR3 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR4_OFFSET 0x0010 /* GPR4 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR5_OFFSET 0x0014 /* GPR5 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR6_OFFSET 0x0018 /* GPR6 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR7_OFFSET 0x001c /* GPR7 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR8_OFFSET 0x0020 /* GPR8 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR9_OFFSET 0x0024 /* GPR9 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR10_OFFSET 0x0028 /* GPR10 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR11_OFFSET 0x002c /* GPR11 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR12_OFFSET 0x0030 /* GPR12 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR13_OFFSET 0x0034 /* GPR13 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR14_OFFSET 0x0038 /* GPR14 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR15_OFFSET 0x003c /* GPR15 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR16_OFFSET 0x0040 /* GPR16 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR17_OFFSET 0x0044 /* GPR17 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR18_OFFSET 0x0048 /* GPR18 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR19_OFFSET 0x004c /* GPR19 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR20_OFFSET 0x0050 /* GPR20 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR21_OFFSET 0x0054 /* GPR21 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR22_OFFSET 0x0058 /* GPR22 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR23_OFFSET 0x005c /* GPR23 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR24_OFFSET 0x0060 /* GPR24 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR25_OFFSET 0x0064 /* GPR25 General Purpose Register*/ + +#define IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEU_OFFSET 0x0000 /* SW_MUX_CTL_PAD_WAKEUP SW MUX Control Register */ +#define IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_OFFSET 0x0004 /* SW_MUX_CTL_PAD_PMIC_ON_REQ SW MUX Control Register */ +#define IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_OFFSET 0x0008 /* SW_MUX_CTL_PAD_PMIC_STBY_REQ SW MUX Control Register */ +#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_OFFSET 0x000c /* SW_PAD_CTL_PAD_TEST_MODE SW PAD Control Register */ +#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_OFFSET 0x0010 /* SW_PAD_CTL_PAD_POR_B SW PAD Control Register */ +#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_OFFSET 0x0014 /* SW_PAD_CTL_PAD_ONOFF SW PAD Control Register */ +#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_OFFSET 0x0018 /* SW_PAD_CTL_PAD_WAKEUP SW PAD Control Register */ +#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_OFFSET 0x001c /* SW_PAD_CTL_PAD_PMIC_ON_REQ SW PAD Control Register */ +#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_OFFSET 0x0020 /* SW_PAD_CTL_PAD_PMIC_STBY_REQ SW PAD Control Register */ + +#define IMXRT_IOMUXC_SNVS_GPR_GPR0_OFFSET 0x0000 /* SNVC GPR0 General Purpose Register */ +#define IMXRT_IOMUXC_SNVS_GPR_GPR1_OFFSET 0x0004 /* SNVC GPR1 General Purpose Register */ +#define IMXRT_IOMUXC_SNVS_GPR_GPR2_OFFSET 0x0008 /* SNVC GPR2 General Purpose Register */ +#define IMXRT_IOMUXC_SNVS_GPR_GPR3_OFFSET 0x000c /* SNVC GPR3 General Purpose Register */ + +/* Pad Mux Registers */ +/* Pad Mux Register Indices (used by software for table lookups) */ + +#define IMXRT_PADMUX_GPIO_EMC_00_INDEX 0 +#define IMXRT_PADMUX_GPIO_EMC_01_INDEX 1 +#define IMXRT_PADMUX_GPIO_EMC_02_INDEX 2 +#define IMXRT_PADMUX_GPIO_EMC_03_INDEX 3 +#define IMXRT_PADMUX_GPIO_EMC_04_INDEX 4 +#define IMXRT_PADMUX_GPIO_EMC_05_INDEX 5 +#define IMXRT_PADMUX_GPIO_EMC_06_INDEX 6 +#define IMXRT_PADMUX_GPIO_EMC_07_INDEX 7 +#define IMXRT_PADMUX_GPIO_EMC_08_INDEX 8 +#define IMXRT_PADMUX_GPIO_EMC_09_INDEX 9 +#define IMXRT_PADMUX_GPIO_EMC_10_INDEX 10 +#define IMXRT_PADMUX_GPIO_EMC_11_INDEX 11 +#define IMXRT_PADMUX_GPIO_EMC_12_INDEX 12 +#define IMXRT_PADMUX_GPIO_EMC_13_INDEX 13 +#define IMXRT_PADMUX_GPIO_EMC_14_INDEX 14 +#define IMXRT_PADMUX_GPIO_EMC_15_INDEX 15 +#define IMXRT_PADMUX_GPIO_EMC_16_INDEX 16 +#define IMXRT_PADMUX_GPIO_EMC_17_INDEX 17 +#define IMXRT_PADMUX_GPIO_EMC_18_INDEX 18 +#define IMXRT_PADMUX_GPIO_EMC_19_INDEX 19 +#define IMXRT_PADMUX_GPIO_EMC_20_INDEX 20 +#define IMXRT_PADMUX_GPIO_EMC_21_INDEX 21 +#define IMXRT_PADMUX_GPIO_EMC_22_INDEX 22 +#define IMXRT_PADMUX_GPIO_EMC_23_INDEX 23 +#define IMXRT_PADMUX_GPIO_EMC_24_INDEX 24 +#define IMXRT_PADMUX_GPIO_EMC_25_INDEX 25 +#define IMXRT_PADMUX_GPIO_EMC_26_INDEX 26 +#define IMXRT_PADMUX_GPIO_EMC_27_INDEX 27 +#define IMXRT_PADMUX_GPIO_EMC_28_INDEX 28 +#define IMXRT_PADMUX_GPIO_EMC_29_INDEX 29 +#define IMXRT_PADMUX_GPIO_EMC_30_INDEX 30 +#define IMXRT_PADMUX_GPIO_EMC_31_INDEX 31 +#define IMXRT_PADMUX_GPIO_EMC_32_INDEX 32 +#define IMXRT_PADMUX_GPIO_EMC_33_INDEX 33 +#define IMXRT_PADMUX_GPIO_EMC_34_INDEX 34 +#define IMXRT_PADMUX_GPIO_EMC_35_INDEX 35 +#define IMXRT_PADMUX_GPIO_EMC_36_INDEX 36 +#define IMXRT_PADMUX_GPIO_EMC_37_INDEX 37 +#define IMXRT_PADMUX_GPIO_EMC_38_INDEX 38 +#define IMXRT_PADMUX_GPIO_EMC_39_INDEX 39 +#define IMXRT_PADMUX_GPIO_EMC_40_INDEX 40 +#define IMXRT_PADMUX_GPIO_EMC_41_INDEX 41 +#define IMXRT_PADMUX_GPIO_AD_B0_00_INDEX 42 +#define IMXRT_PADMUX_GPIO_AD_B0_01_INDEX 43 +#define IMXRT_PADMUX_GPIO_AD_B0_02_INDEX 44 +#define IMXRT_PADMUX_GPIO_AD_B0_03_INDEX 45 +#define IMXRT_PADMUX_GPIO_AD_B0_04_INDEX 46 +#define IMXRT_PADMUX_GPIO_AD_B0_05_INDEX 47 +#define IMXRT_PADMUX_GPIO_AD_B0_06_INDEX 48 +#define IMXRT_PADMUX_GPIO_AD_B0_07_INDEX 49 +#define IMXRT_PADMUX_GPIO_AD_B0_08_INDEX 50 +#define IMXRT_PADMUX_GPIO_AD_B0_09_INDEX 51 +#define IMXRT_PADMUX_GPIO_AD_B0_10_INDEX 52 +#define IMXRT_PADMUX_GPIO_AD_B0_11_INDEX 53 +#define IMXRT_PADMUX_GPIO_AD_B0_12_INDEX 54 +#define IMXRT_PADMUX_GPIO_AD_B0_13_INDEX 55 +#define IMXRT_PADMUX_GPIO_AD_B0_14_INDEX 56 +#define IMXRT_PADMUX_GPIO_AD_B0_15_INDEX 57 +#define IMXRT_PADMUX_GPIO_AD_B1_00_INDEX 58 +#define IMXRT_PADMUX_GPIO_AD_B1_01_INDEX 59 +#define IMXRT_PADMUX_GPIO_AD_B1_02_INDEX 60 +#define IMXRT_PADMUX_GPIO_AD_B1_03_INDEX 61 +#define IMXRT_PADMUX_GPIO_AD_B1_04_INDEX 62 +#define IMXRT_PADMUX_GPIO_AD_B1_05_INDEX 63 +#define IMXRT_PADMUX_GPIO_AD_B1_06_INDEX 64 +#define IMXRT_PADMUX_GPIO_AD_B1_07_INDEX 65 +#define IMXRT_PADMUX_GPIO_AD_B1_08_INDEX 66 +#define IMXRT_PADMUX_GPIO_AD_B1_09_INDEX 67 +#define IMXRT_PADMUX_GPIO_AD_B1_10_INDEX 68 +#define IMXRT_PADMUX_GPIO_AD_B1_11_INDEX 69 +#define IMXRT_PADMUX_GPIO_AD_B1_12_INDEX 70 +#define IMXRT_PADMUX_GPIO_AD_B1_13_INDEX 71 +#define IMXRT_PADMUX_GPIO_AD_B1_14_INDEX 72 +#define IMXRT_PADMUX_GPIO_AD_B1_15_INDEX 73 +#define IMXRT_PADMUX_GPIO_B0_00_INDEX 74 +#define IMXRT_PADMUX_GPIO_B0_01_INDEX 75 +#define IMXRT_PADMUX_GPIO_B0_02_INDEX 76 +#define IMXRT_PADMUX_GPIO_B0_03_INDEX 77 +#define IMXRT_PADMUX_GPIO_B0_04_INDEX 78 +#define IMXRT_PADMUX_GPIO_B0_05_INDEX 79 +#define IMXRT_PADMUX_GPIO_B0_06_INDEX 80 +#define IMXRT_PADMUX_GPIO_B0_07_INDEX 81 +#define IMXRT_PADMUX_GPIO_B0_08_INDEX 82 +#define IMXRT_PADMUX_GPIO_B0_09_INDEX 83 +#define IMXRT_PADMUX_GPIO_B0_10_INDEX 84 +#define IMXRT_PADMUX_GPIO_B0_11_INDEX 85 +#define IMXRT_PADMUX_GPIO_B0_12_INDEX 86 +#define IMXRT_PADMUX_GPIO_B0_13_INDEX 87 +#define IMXRT_PADMUX_GPIO_B0_14_INDEX 88 +#define IMXRT_PADMUX_GPIO_B0_15_INDEX 89 +#define IMXRT_PADMUX_GPIO_B1_00_INDEX 90 +#define IMXRT_PADMUX_GPIO_B1_01_INDEX 91 +#define IMXRT_PADMUX_GPIO_B1_02_INDEX 92 +#define IMXRT_PADMUX_GPIO_B1_03_INDEX 93 +#define IMXRT_PADMUX_GPIO_B1_04_INDEX 94 +#define IMXRT_PADMUX_GPIO_B1_05_INDEX 95 +#define IMXRT_PADMUX_GPIO_B1_06_INDEX 96 +#define IMXRT_PADMUX_GPIO_B1_07_INDEX 97 +#define IMXRT_PADMUX_GPIO_B1_08_INDEX 98 +#define IMXRT_PADMUX_GPIO_B1_09_INDEX 99 +#define IMXRT_PADMUX_GPIO_B1_10_INDEX 100 +#define IMXRT_PADMUX_GPIO_B1_11_INDEX 101 +#define IMXRT_PADMUX_GPIO_B1_12_INDEX 102 +#define IMXRT_PADMUX_GPIO_B1_13_INDEX 103 +#define IMXRT_PADMUX_GPIO_B1_14_INDEX 104 +#define IMXRT_PADMUX_GPIO_B1_15_INDEX 105 +#define IMXRT_PADMUX_GPIO_SD_B0_00_INDEX 106 +#define IMXRT_PADMUX_GPIO_SD_B0_01_INDEX 107 +#define IMXRT_PADMUX_GPIO_SD_B0_02_INDEX 108 +#define IMXRT_PADMUX_GPIO_SD_B0_03_INDEX 109 +#define IMXRT_PADMUX_GPIO_SD_B0_04_INDEX 110 +#define IMXRT_PADMUX_GPIO_SD_B0_05_INDEX 111 +#define IMXRT_PADMUX_GPIO_SD_B1_00_INDEX 112 +#define IMXRT_PADMUX_GPIO_SD_B1_01_INDEX 113 +#define IMXRT_PADMUX_GPIO_SD_B1_02_INDEX 114 +#define IMXRT_PADMUX_GPIO_SD_B1_03_INDEX 115 +#define IMXRT_PADMUX_GPIO_SD_B1_04_INDEX 116 +#define IMXRT_PADMUX_GPIO_SD_B1_05_INDEX 117 +#define IMXRT_PADMUX_GPIO_SD_B1_06_INDEX 118 +#define IMXRT_PADMUX_GPIO_SD_B1_07_INDEX 119 +#define IMXRT_PADMUX_GPIO_SD_B1_08_INDEX 120 +#define IMXRT_PADMUX_GPIO_SD_B1_09_INDEX 121 +#define IMXRT_PADMUX_GPIO_SD_B1_10_INDEX 122 +#define IMXRT_PADMUX_GPIO_SD_B1_11_INDEX 123 + +#define IMXRT_PADMUX_NREGISTERS 124 + +/* Pad Mux Register Offsets */ + +#define IMXRT_PADMUX_OFFSET(n) (0x0014 + ((unsigned int)(n) << 2)) + +#define IMXRT_PADMUX_GPIO_EMC_00_OFFSET 0x0014 +#define IMXRT_PADMUX_GPIO_EMC_01_OFFSET 0x0018 +#define IMXRT_PADMUX_GPIO_EMC_02_OFFSET 0x001c +#define IMXRT_PADMUX_GPIO_EMC_03_OFFSET 0x0020 +#define IMXRT_PADMUX_GPIO_EMC_04_OFFSET 0x0024 +#define IMXRT_PADMUX_GPIO_EMC_05_OFFSET 0x0028 +#define IMXRT_PADMUX_GPIO_EMC_06_OFFSET 0x002c +#define IMXRT_PADMUX_GPIO_EMC_07_OFFSET 0x0030 +#define IMXRT_PADMUX_GPIO_EMC_08_OFFSET 0x0034 +#define IMXRT_PADMUX_GPIO_EMC_09_OFFSET 0x0038 +#define IMXRT_PADMUX_GPIO_EMC_10_OFFSET 0x003c +#define IMXRT_PADMUX_GPIO_EMC_11_OFFSET 0x0040 +#define IMXRT_PADMUX_GPIO_EMC_12_OFFSET 0x0044 +#define IMXRT_PADMUX_GPIO_EMC_13_OFFSET 0x0048 +#define IMXRT_PADMUX_GPIO_EMC_14_OFFSET 0x004c +#define IMXRT_PADMUX_GPIO_EMC_15_OFFSET 0x0050 +#define IMXRT_PADMUX_GPIO_EMC_16_OFFSET 0x0054 +#define IMXRT_PADMUX_GPIO_EMC_17_OFFSET 0x0058 +#define IMXRT_PADMUX_GPIO_EMC_18_OFFSET 0x005c +#define IMXRT_PADMUX_GPIO_EMC_19_OFFSET 0x0060 +#define IMXRT_PADMUX_GPIO_EMC_20_OFFSET 0x0064 +#define IMXRT_PADMUX_GPIO_EMC_21_OFFSET 0x0068 +#define IMXRT_PADMUX_GPIO_EMC_22_OFFSET 0x006c +#define IMXRT_PADMUX_GPIO_EMC_23_OFFSET 0x0070 +#define IMXRT_PADMUX_GPIO_EMC_24_OFFSET 0x0074 +#define IMXRT_PADMUX_GPIO_EMC_25_OFFSET 0x0078 +#define IMXRT_PADMUX_GPIO_EMC_26_OFFSET 0x007c +#define IMXRT_PADMUX_GPIO_EMC_27_OFFSET 0x0080 +#define IMXRT_PADMUX_GPIO_EMC_28_OFFSET 0x0084 +#define IMXRT_PADMUX_GPIO_EMC_29_OFFSET 0x0088 +#define IMXRT_PADMUX_GPIO_EMC_30_OFFSET 0x008c +#define IMXRT_PADMUX_GPIO_EMC_31_OFFSET 0x0090 +#define IMXRT_PADMUX_GPIO_EMC_32_OFFSET 0x0094 +#define IMXRT_PADMUX_GPIO_EMC_33_OFFSET 0x0098 +#define IMXRT_PADMUX_GPIO_EMC_34_OFFSET 0x009c +#define IMXRT_PADMUX_GPIO_EMC_35_OFFSET 0x00a0 +#define IMXRT_PADMUX_GPIO_EMC_36_OFFSET 0x00a4 +#define IMXRT_PADMUX_GPIO_EMC_37_OFFSET 0x00a8 +#define IMXRT_PADMUX_GPIO_EMC_38_OFFSET 0x00ac +#define IMXRT_PADMUX_GPIO_EMC_39_OFFSET 0x00b0 +#define IMXRT_PADMUX_GPIO_EMC_40_OFFSET 0x00b4 +#define IMXRT_PADMUX_GPIO_EMC_41_OFFSET 0x00b8 +#define IMXRT_PADMUX_GPIO_AD_B0_00_OFFSET 0x00bc +#define IMXRT_PADMUX_GPIO_AD_B0_01_OFFSET 0x00c0 +#define IMXRT_PADMUX_GPIO_AD_B0_02_OFFSET 0x00c4 +#define IMXRT_PADMUX_GPIO_AD_B0_03_OFFSET 0x00c8 +#define IMXRT_PADMUX_GPIO_AD_B0_04_OFFSET 0x00cc +#define IMXRT_PADMUX_GPIO_AD_B0_05_OFFSET 0x00d0 +#define IMXRT_PADMUX_GPIO_AD_B0_06_OFFSET 0x00d4 +#define IMXRT_PADMUX_GPIO_AD_B0_07_OFFSET 0x00d8 +#define IMXRT_PADMUX_GPIO_AD_B0_08_OFFSET 0x00dc +#define IMXRT_PADMUX_GPIO_AD_B0_09_OFFSET 0x00e0 +#define IMXRT_PADMUX_GPIO_AD_B0_10_OFFSET 0x00e4 +#define IMXRT_PADMUX_GPIO_AD_B0_11_OFFSET 0x00e8 +#define IMXRT_PADMUX_GPIO_AD_B0_12_OFFSET 0x00ec +#define IMXRT_PADMUX_GPIO_AD_B0_13_OFFSET 0x00f0 +#define IMXRT_PADMUX_GPIO_AD_B0_14_OFFSET 0x00f4 +#define IMXRT_PADMUX_GPIO_AD_B0_15_OFFSET 0x00f8 +#define IMXRT_PADMUX_GPIO_AD_B1_00_OFFSET 0x00fc +#define IMXRT_PADMUX_GPIO_AD_B1_01_OFFSET 0x0100 +#define IMXRT_PADMUX_GPIO_AD_B1_02_OFFSET 0x0104 +#define IMXRT_PADMUX_GPIO_AD_B1_03_OFFSET 0x0108 +#define IMXRT_PADMUX_GPIO_AD_B1_04_OFFSET 0x010c +#define IMXRT_PADMUX_GPIO_AD_B1_05_OFFSET 0x0110 +#define IMXRT_PADMUX_GPIO_AD_B1_06_OFFSET 0x0114 +#define IMXRT_PADMUX_GPIO_AD_B1_07_OFFSET 0x0118 +#define IMXRT_PADMUX_GPIO_AD_B1_08_OFFSET 0x011c +#define IMXRT_PADMUX_GPIO_AD_B1_09_OFFSET 0x0120 +#define IMXRT_PADMUX_GPIO_AD_B1_10_OFFSET 0x0124 +#define IMXRT_PADMUX_GPIO_AD_B1_11_OFFSET 0x0128 +#define IMXRT_PADMUX_GPIO_AD_B1_12_OFFSET 0x012c +#define IMXRT_PADMUX_GPIO_AD_B1_13_OFFSET 0x0130 +#define IMXRT_PADMUX_GPIO_AD_B1_14_OFFSET 0x0134 +#define IMXRT_PADMUX_GPIO_AD_B1_15_OFFSET 0x0138 +#define IMXRT_PADMUX_GPIO_B0_00_OFFSET 0x013c +#define IMXRT_PADMUX_GPIO_B0_01_OFFSET 0x0140 +#define IMXRT_PADMUX_GPIO_B0_02_OFFSET 0x0144 +#define IMXRT_PADMUX_GPIO_B0_03_OFFSET 0x0148 +#define IMXRT_PADMUX_GPIO_B0_04_OFFSET 0x014c +#define IMXRT_PADMUX_GPIO_B0_05_OFFSET 0x0150 +#define IMXRT_PADMUX_GPIO_B0_06_OFFSET 0x0154 +#define IMXRT_PADMUX_GPIO_B0_07_OFFSET 0x0158 +#define IMXRT_PADMUX_GPIO_B0_08_OFFSET 0x015c +#define IMXRT_PADMUX_GPIO_B0_09_OFFSET 0x0160 +#define IMXRT_PADMUX_GPIO_B0_10_OFFSET 0x0164 +#define IMXRT_PADMUX_GPIO_B0_11_OFFSET 0x0168 +#define IMXRT_PADMUX_GPIO_B0_12_OFFSET 0x016c +#define IMXRT_PADMUX_GPIO_B0_13_OFFSET 0x0170 +#define IMXRT_PADMUX_GPIO_B0_14_OFFSET 0x0174 +#define IMXRT_PADMUX_GPIO_B0_15_OFFSET 0x0178 +#define IMXRT_PADMUX_GPIO_B1_00_OFFSET 0x017c +#define IMXRT_PADMUX_GPIO_B1_01_OFFSET 0x0180 +#define IMXRT_PADMUX_GPIO_B1_02_OFFSET 0x0184 +#define IMXRT_PADMUX_GPIO_B1_03_OFFSET 0x0188 +#define IMXRT_PADMUX_GPIO_B1_04_OFFSET 0x018c +#define IMXRT_PADMUX_GPIO_B1_05_OFFSET 0x0190 +#define IMXRT_PADMUX_GPIO_B1_06_OFFSET 0x0194 +#define IMXRT_PADMUX_GPIO_B1_07_OFFSET 0x0198 +#define IMXRT_PADMUX_GPIO_B1_08_OFFSET 0x019c +#define IMXRT_PADMUX_GPIO_B1_09_OFFSET 0x01a0 +#define IMXRT_PADMUX_GPIO_B1_10_OFFSET 0x01a4 +#define IMXRT_PADMUX_GPIO_B1_11_OFFSET 0x01a8 +#define IMXRT_PADMUX_GPIO_B1_12_OFFSET 0x01ac +#define IMXRT_PADMUX_GPIO_B1_13_OFFSET 0x01b0 +#define IMXRT_PADMUX_GPIO_B1_14_OFFSET 0x01b4 +#define IMXRT_PADMUX_GPIO_B1_15_OFFSET 0x01b8 +#define IMXRT_PADMUX_GPIO_SD_B0_00_OFFSET 0x01bc +#define IMXRT_PADMUX_GPIO_SD_B0_01_OFFSET 0x01c0 +#define IMXRT_PADMUX_GPIO_SD_B0_02_OFFSET 0x01c4 +#define IMXRT_PADMUX_GPIO_SD_B0_03_OFFSET 0x01c8 +#define IMXRT_PADMUX_GPIO_SD_B0_04_OFFSET 0x01cc +#define IMXRT_PADMUX_GPIO_SD_B0_05_OFFSET 0x01d0 +#define IMXRT_PADMUX_GPIO_SD_B1_00_OFFSET 0x01d4 +#define IMXRT_PADMUX_GPIO_SD_B1_01_OFFSET 0x01d8 +#define IMXRT_PADMUX_GPIO_SD_B1_02_OFFSET 0x01dc +#define IMXRT_PADMUX_GPIO_SD_B1_03_OFFSET 0x01e0 +#define IMXRT_PADMUX_GPIO_SD_B1_04_OFFSET 0x01e4 +#define IMXRT_PADMUX_GPIO_SD_B1_05_OFFSET 0x01e8 +#define IMXRT_PADMUX_GPIO_SD_B1_06_OFFSET 0x01ec +#define IMXRT_PADMUX_GPIO_SD_B1_07_OFFSET 0x01f0 +#define IMXRT_PADMUX_GPIO_SD_B1_08_OFFSET 0x01f4 +#define IMXRT_PADMUX_GPIO_SD_B1_09_OFFSET 0x01f8 +#define IMXRT_PADMUX_GPIO_SD_B1_10_OFFSET 0x01fc +#define IMXRT_PADMUX_GPIO_SD_B1_11_OFFSET 0x0200 + + +/* Pad Control Registers */ +/* Pad Mux Register Indices (used by software for table lookups) */ + +#define IMXRT_PADCTL_GPIO_EMC_00_INDEX 0 +#define IMXRT_PADCTL_GPIO_EMC_01_INDEX 1 +#define IMXRT_PADCTL_GPIO_EMC_02_INDEX 2 +#define IMXRT_PADCTL_GPIO_EMC_03_INDEX 3 +#define IMXRT_PADCTL_GPIO_EMC_04_INDEX 4 +#define IMXRT_PADCTL_GPIO_EMC_05_INDEX 5 +#define IMXRT_PADCTL_GPIO_EMC_06_INDEX 6 +#define IMXRT_PADCTL_GPIO_EMC_07_INDEX 7 +#define IMXRT_PADCTL_GPIO_EMC_08_INDEX 8 +#define IMXRT_PADCTL_GPIO_EMC_09_INDEX 9 +#define IMXRT_PADCTL_GPIO_EMC_10_INDEX 10 +#define IMXRT_PADCTL_GPIO_EMC_11_INDEX 11 +#define IMXRT_PADCTL_GPIO_EMC_12_INDEX 12 +#define IMXRT_PADCTL_GPIO_EMC_13_INDEX 13 +#define IMXRT_PADCTL_GPIO_EMC_14_INDEX 14 +#define IMXRT_PADCTL_GPIO_EMC_15_INDEX 15 +#define IMXRT_PADCTL_GPIO_EMC_16_INDEX 16 +#define IMXRT_PADCTL_GPIO_EMC_17_INDEX 17 +#define IMXRT_PADCTL_GPIO_EMC_18_INDEX 18 +#define IMXRT_PADCTL_GPIO_EMC_19_INDEX 19 +#define IMXRT_PADCTL_GPIO_EMC_20_INDEX 20 +#define IMXRT_PADCTL_GPIO_EMC_21_INDEX 21 +#define IMXRT_PADCTL_GPIO_EMC_22_INDEX 22 +#define IMXRT_PADCTL_GPIO_EMC_23_INDEX 23 +#define IMXRT_PADCTL_GPIO_EMC_24_INDEX 24 +#define IMXRT_PADCTL_GPIO_EMC_25_INDEX 25 +#define IMXRT_PADCTL_GPIO_EMC_26_INDEX 26 +#define IMXRT_PADCTL_GPIO_EMC_27_INDEX 27 +#define IMXRT_PADCTL_GPIO_EMC_28_INDEX 28 +#define IMXRT_PADCTL_GPIO_EMC_29_INDEX 29 +#define IMXRT_PADCTL_GPIO_EMC_30_INDEX 30 +#define IMXRT_PADCTL_GPIO_EMC_31_INDEX 31 +#define IMXRT_PADCTL_GPIO_EMC_32_INDEX 32 +#define IMXRT_PADCTL_GPIO_EMC_33_INDEX 33 +#define IMXRT_PADCTL_GPIO_EMC_34_INDEX 34 +#define IMXRT_PADCTL_GPIO_EMC_35_INDEX 35 +#define IMXRT_PADCTL_GPIO_EMC_36_INDEX 36 +#define IMXRT_PADCTL_GPIO_EMC_37_INDEX 37 +#define IMXRT_PADCTL_GPIO_EMC_38_INDEX 38 +#define IMXRT_PADCTL_GPIO_EMC_39_INDEX 39 +#define IMXRT_PADCTL_GPIO_EMC_40_INDEX 40 +#define IMXRT_PADCTL_GPIO_EMC_41_INDEX 41 +#define IMXRT_PADCTL_GPIO_AD_B0_00_INDEX 42 +#define IMXRT_PADCTL_GPIO_AD_B0_01_INDEX 43 +#define IMXRT_PADCTL_GPIO_AD_B0_02_INDEX 44 +#define IMXRT_PADCTL_GPIO_AD_B0_03_INDEX 45 +#define IMXRT_PADCTL_GPIO_AD_B0_04_INDEX 46 +#define IMXRT_PADCTL_GPIO_AD_B0_05_INDEX 47 +#define IMXRT_PADCTL_GPIO_AD_B0_06_INDEX 48 +#define IMXRT_PADCTL_GPIO_AD_B0_07_INDEX 49 +#define IMXRT_PADCTL_GPIO_AD_B0_08_INDEX 50 +#define IMXRT_PADCTL_GPIO_AD_B0_09_INDEX 51 +#define IMXRT_PADCTL_GPIO_AD_B0_10_INDEX 52 +#define IMXRT_PADCTL_GPIO_AD_B0_11_INDEX 53 +#define IMXRT_PADCTL_GPIO_AD_B0_12_INDEX 54 +#define IMXRT_PADCTL_GPIO_AD_B0_13_INDEX 55 +#define IMXRT_PADCTL_GPIO_AD_B0_14_INDEX 56 +#define IMXRT_PADCTL_GPIO_AD_B0_15_INDEX 57 +#define IMXRT_PADCTL_GPIO_AD_B1_00_INDEX 58 +#define IMXRT_PADCTL_GPIO_AD_B1_01_INDEX 59 +#define IMXRT_PADCTL_GPIO_AD_B1_02_INDEX 60 +#define IMXRT_PADCTL_GPIO_AD_B1_03_INDEX 61 +#define IMXRT_PADCTL_GPIO_AD_B1_04_INDEX 62 +#define IMXRT_PADCTL_GPIO_AD_B1_05_INDEX 63 +#define IMXRT_PADCTL_GPIO_AD_B1_06_INDEX 64 +#define IMXRT_PADCTL_GPIO_AD_B1_07_INDEX 65 +#define IMXRT_PADCTL_GPIO_AD_B1_08_INDEX 66 +#define IMXRT_PADCTL_GPIO_AD_B1_09_INDEX 67 +#define IMXRT_PADCTL_GPIO_AD_B1_10_INDEX 68 +#define IMXRT_PADCTL_GPIO_AD_B1_11_INDEX 69 +#define IMXRT_PADCTL_GPIO_AD_B1_12_INDEX 70 +#define IMXRT_PADCTL_GPIO_AD_B1_13_INDEX 71 +#define IMXRT_PADCTL_GPIO_AD_B1_14_INDEX 72 +#define IMXRT_PADCTL_GPIO_AD_B1_15_INDEX 73 +#define IMXRT_PADCTL_GPIO_B0_00_INDEX 74 +#define IMXRT_PADCTL_GPIO_B0_01_INDEX 75 +#define IMXRT_PADCTL_GPIO_B0_02_INDEX 76 +#define IMXRT_PADCTL_GPIO_B0_03_INDEX 77 +#define IMXRT_PADCTL_GPIO_B0_04_INDEX 78 +#define IMXRT_PADCTL_GPIO_B0_05_INDEX 79 +#define IMXRT_PADCTL_GPIO_B0_06_INDEX 80 +#define IMXRT_PADCTL_GPIO_B0_07_INDEX 81 +#define IMXRT_PADCTL_GPIO_B0_08_INDEX 82 +#define IMXRT_PADCTL_GPIO_B0_09_INDEX 83 +#define IMXRT_PADCTL_GPIO_B0_10_INDEX 84 +#define IMXRT_PADCTL_GPIO_B0_11_INDEX 85 +#define IMXRT_PADCTL_GPIO_B0_12_INDEX 86 +#define IMXRT_PADCTL_GPIO_B0_13_INDEX 87 +#define IMXRT_PADCTL_GPIO_B0_14_INDEX 88 +#define IMXRT_PADCTL_GPIO_B0_15_INDEX 89 +#define IMXRT_PADCTL_GPIO_B1_00_INDEX 90 +#define IMXRT_PADCTL_GPIO_B1_01_INDEX 91 +#define IMXRT_PADCTL_GPIO_B1_02_INDEX 92 +#define IMXRT_PADCTL_GPIO_B1_03_INDEX 93 +#define IMXRT_PADCTL_GPIO_B1_04_INDEX 94 +#define IMXRT_PADCTL_GPIO_B1_05_INDEX 95 +#define IMXRT_PADCTL_GPIO_B1_06_INDEX 96 +#define IMXRT_PADCTL_GPIO_B1_07_INDEX 97 +#define IMXRT_PADCTL_GPIO_B1_08_INDEX 98 +#define IMXRT_PADCTL_GPIO_B1_09_INDEX 99 +#define IMXRT_PADCTL_GPIO_B1_10_INDEX 100 +#define IMXRT_PADCTL_GPIO_B1_11_INDEX 101 +#define IMXRT_PADCTL_GPIO_B1_12_INDEX 102 +#define IMXRT_PADCTL_GPIO_B1_13_INDEX 103 +#define IMXRT_PADCTL_GPIO_B1_14_INDEX 104 +#define IMXRT_PADCTL_GPIO_B1_15_INDEX 105 +#define IMXRT_PADCTL_GPIO_SD_B0_00_INDEX 106 +#define IMXRT_PADCTL_GPIO_SD_B0_01_INDEX 107 +#define IMXRT_PADCTL_GPIO_SD_B0_02_INDEX 108 +#define IMXRT_PADCTL_GPIO_SD_B0_03_INDEX 109 +#define IMXRT_PADCTL_GPIO_SD_B0_04_INDEX 110 +#define IMXRT_PADCTL_GPIO_SD_B0_05_INDEX 111 +#define IMXRT_PADCTL_GPIO_SD_B1_00_INDEX 112 +#define IMXRT_PADCTL_GPIO_SD_B1_01_INDEX 113 +#define IMXRT_PADCTL_GPIO_SD_B1_02_INDEX 114 +#define IMXRT_PADCTL_GPIO_SD_B1_03_INDEX 115 +#define IMXRT_PADCTL_GPIO_SD_B1_04_INDEX 116 +#define IMXRT_PADCTL_GPIO_SD_B1_05_INDEX 117 +#define IMXRT_PADCTL_GPIO_SD_B1_06_INDEX 118 +#define IMXRT_PADCTL_GPIO_SD_B1_07_INDEX 119 +#define IMXRT_PADCTL_GPIO_SD_B1_08_INDEX 120 +#define IMXRT_PADCTL_GPIO_SD_B1_09_INDEX 121 +#define IMXRT_PADCTL_GPIO_SD_B1_10_INDEX 122 +#define IMXRT_PADCTL_GPIO_SD_B1_11_INDEX 123 + +#define IMXRT_PADCTL_NREGISTERS 124 + +/* Pad Mux Register Offsets */ + +#define IMXRT_PADCTL_OFFSET(n) (0x0204 + ((unsigned int)(n) << 2)) + +#define IMXRT_PADCTL_GPIO_EMC_00_OFFSET 0x0204 +#define IMXRT_PADCTL_GPIO_EMC_01_OFFSET 0x0208 +#define IMXRT_PADCTL_GPIO_EMC_02_OFFSET 0x020c +#define IMXRT_PADCTL_GPIO_EMC_03_OFFSET 0x0210 +#define IMXRT_PADCTL_GPIO_EMC_04_OFFSET 0x0214 +#define IMXRT_PADCTL_GPIO_EMC_05_OFFSET 0x0218 +#define IMXRT_PADCTL_GPIO_EMC_06_OFFSET 0x021c +#define IMXRT_PADCTL_GPIO_EMC_07_OFFSET 0x0220 +#define IMXRT_PADCTL_GPIO_EMC_08_OFFSET 0x0224 +#define IMXRT_PADCTL_GPIO_EMC_09_OFFSET 0x0228 +#define IMXRT_PADCTL_GPIO_EMC_10_OFFSET 0x022c +#define IMXRT_PADCTL_GPIO_EMC_11_OFFSET 0x0230 +#define IMXRT_PADCTL_GPIO_EMC_12_OFFSET 0x0234 +#define IMXRT_PADCTL_GPIO_EMC_13_OFFSET 0x0238 +#define IMXRT_PADCTL_GPIO_EMC_14_OFFSET 0x023c +#define IMXRT_PADCTL_GPIO_EMC_15_OFFSET 0x0240 +#define IMXRT_PADCTL_GPIO_EMC_16_OFFSET 0x0244 +#define IMXRT_PADCTL_GPIO_EMC_17_OFFSET 0x0248 +#define IMXRT_PADCTL_GPIO_EMC_18_OFFSET 0x024c +#define IMXRT_PADCTL_GPIO_EMC_19_OFFSET 0x0250 +#define IMXRT_PADCTL_GPIO_EMC_20_OFFSET 0x0254 +#define IMXRT_PADCTL_GPIO_EMC_21_OFFSET 0x0258 +#define IMXRT_PADCTL_GPIO_EMC_22_OFFSET 0x025c +#define IMXRT_PADCTL_GPIO_EMC_23_OFFSET 0x0260 +#define IMXRT_PADCTL_GPIO_EMC_24_OFFSET 0x0264 +#define IMXRT_PADCTL_GPIO_EMC_25_OFFSET 0x0268 +#define IMXRT_PADCTL_GPIO_EMC_26_OFFSET 0x026c +#define IMXRT_PADCTL_GPIO_EMC_27_OFFSET 0x0270 +#define IMXRT_PADCTL_GPIO_EMC_28_OFFSET 0x0274 +#define IMXRT_PADCTL_GPIO_EMC_29_OFFSET 0x0278 +#define IMXRT_PADCTL_GPIO_EMC_30_OFFSET 0x027c +#define IMXRT_PADCTL_GPIO_EMC_31_OFFSET 0x0280 +#define IMXRT_PADCTL_GPIO_EMC_32_OFFSET 0x0284 +#define IMXRT_PADCTL_GPIO_EMC_33_OFFSET 0x0288 +#define IMXRT_PADCTL_GPIO_EMC_34_OFFSET 0x028c +#define IMXRT_PADCTL_GPIO_EMC_35_OFFSET 0x0290 +#define IMXRT_PADCTL_GPIO_EMC_36_OFFSET 0x0294 +#define IMXRT_PADCTL_GPIO_EMC_37_OFFSET 0x0298 +#define IMXRT_PADCTL_GPIO_EMC_38_OFFSET 0x029c +#define IMXRT_PADCTL_GPIO_EMC_39_OFFSET 0x02a0 +#define IMXRT_PADCTL_GPIO_EMC_40_OFFSET 0x02a4 +#define IMXRT_PADCTL_GPIO_EMC_41_OFFSET 0x02a8 +#define IMXRT_PADCTL_GPIO_AD_B0_00_OFFSET 0x02ac +#define IMXRT_PADCTL_GPIO_AD_B0_01_OFFSET 0x02b0 +#define IMXRT_PADCTL_GPIO_AD_B0_02_OFFSET 0x02b4 +#define IMXRT_PADCTL_GPIO_AD_B0_03_OFFSET 0x02b8 +#define IMXRT_PADCTL_GPIO_AD_B0_04_OFFSET 0x02bc +#define IMXRT_PADCTL_GPIO_AD_B0_05_OFFSET 0x02c0 +#define IMXRT_PADCTL_GPIO_AD_B0_06_OFFSET 0x02c4 +#define IMXRT_PADCTL_GPIO_AD_B0_07_OFFSET 0x02c8 +#define IMXRT_PADCTL_GPIO_AD_B0_08_OFFSET 0x02cc +#define IMXRT_PADCTL_GPIO_AD_B0_09_OFFSET 0x02d0 +#define IMXRT_PADCTL_GPIO_AD_B0_10_OFFSET 0x02d4 +#define IMXRT_PADCTL_GPIO_AD_B0_11_OFFSET 0x02d8 +#define IMXRT_PADCTL_GPIO_AD_B0_12_OFFSET 0x02dc +#define IMXRT_PADCTL_GPIO_AD_B0_13_OFFSET 0x02e0 +#define IMXRT_PADCTL_GPIO_AD_B0_14_OFFSET 0x02e4 +#define IMXRT_PADCTL_GPIO_AD_B0_15_OFFSET 0x02e8 +#define IMXRT_PADCTL_GPIO_AD_B1_00_OFFSET 0x02ec +#define IMXRT_PADCTL_GPIO_AD_B1_01_OFFSET 0x02f0 +#define IMXRT_PADCTL_GPIO_AD_B1_02_OFFSET 0x02f4 +#define IMXRT_PADCTL_GPIO_AD_B1_03_OFFSET 0x02f8 +#define IMXRT_PADCTL_GPIO_AD_B1_04_OFFSET 0x02fc +#define IMXRT_PADCTL_GPIO_AD_B1_05_OFFSET 0x0300 +#define IMXRT_PADCTL_GPIO_AD_B1_06_OFFSET 0x0304 +#define IMXRT_PADCTL_GPIO_AD_B1_07_OFFSET 0x0308 +#define IMXRT_PADCTL_GPIO_AD_B1_08_OFFSET 0x030c +#define IMXRT_PADCTL_GPIO_AD_B1_09_OFFSET 0x0310 +#define IMXRT_PADCTL_GPIO_AD_B1_10_OFFSET 0x0314 +#define IMXRT_PADCTL_GPIO_AD_B1_11_OFFSET 0x0318 +#define IMXRT_PADCTL_GPIO_AD_B1_12_OFFSET 0x031c +#define IMXRT_PADCTL_GPIO_AD_B1_13_OFFSET 0x0320 +#define IMXRT_PADCTL_GPIO_AD_B1_14_OFFSET 0x0324 +#define IMXRT_PADCTL_GPIO_AD_B1_15_OFFSET 0x0328 +#define IMXRT_PADCTL_GPIO_B0_00_OFFSET 0x032c +#define IMXRT_PADCTL_GPIO_B0_01_OFFSET 0x0330 +#define IMXRT_PADCTL_GPIO_B0_02_OFFSET 0x0334 +#define IMXRT_PADCTL_GPIO_B0_03_OFFSET 0x0338 +#define IMXRT_PADCTL_GPIO_B0_04_OFFSET 0x033c +#define IMXRT_PADCTL_GPIO_B0_05_OFFSET 0x0340 +#define IMXRT_PADCTL_GPIO_B0_06_OFFSET 0x0344 +#define IMXRT_PADCTL_GPIO_B0_07_OFFSET 0x0348 +#define IMXRT_PADCTL_GPIO_B0_08_OFFSET 0x034c +#define IMXRT_PADCTL_GPIO_B0_09_OFFSET 0x0350 +#define IMXRT_PADCTL_GPIO_B0_10_OFFSET 0x0354 +#define IMXRT_PADCTL_GPIO_B0_11_OFFSET 0x0358 +#define IMXRT_PADCTL_GPIO_B0_12_OFFSET 0x035c +#define IMXRT_PADCTL_GPIO_B0_13_OFFSET 0x0360 +#define IMXRT_PADCTL_GPIO_B0_14_OFFSET 0x0364 +#define IMXRT_PADCTL_GPIO_B0_15_OFFSET 0x0368 +#define IMXRT_PADCTL_GPIO_B1_00_OFFSET 0x036c +#define IMXRT_PADCTL_GPIO_B1_01_OFFSET 0x0370 +#define IMXRT_PADCTL_GPIO_B1_02_OFFSET 0x0374 +#define IMXRT_PADCTL_GPIO_B1_03_OFFSET 0x0378 +#define IMXRT_PADCTL_GPIO_B1_04_OFFSET 0x037c +#define IMXRT_PADCTL_GPIO_B1_05_OFFSET 0x0380 +#define IMXRT_PADCTL_GPIO_B1_06_OFFSET 0x0384 +#define IMXRT_PADCTL_GPIO_B1_07_OFFSET 0x0388 +#define IMXRT_PADCTL_GPIO_B1_08_OFFSET 0x038c +#define IMXRT_PADCTL_GPIO_B1_09_OFFSET 0x0390 +#define IMXRT_PADCTL_GPIO_B1_10_OFFSET 0x0394 +#define IMXRT_PADCTL_GPIO_B1_11_OFFSET 0x0398 +#define IMXRT_PADCTL_GPIO_B1_12_OFFSET 0x039c +#define IMXRT_PADCTL_GPIO_B1_13_OFFSET 0x03a0 +#define IMXRT_PADCTL_GPIO_B1_14_OFFSET 0x03a4 +#define IMXRT_PADCTL_GPIO_B1_15_OFFSET 0x03a8 +#define IMXRT_PADCTL_GPIO_SD_B0_00_OFFSET 0x03ac +#define IMXRT_PADCTL_GPIO_SD_B0_01_OFFSET 0x03b0 +#define IMXRT_PADCTL_GPIO_SD_B0_02_OFFSET 0x03b4 +#define IMXRT_PADCTL_GPIO_SD_B0_03_OFFSET 0x03b8 +#define IMXRT_PADCTL_GPIO_SD_B0_04_OFFSET 0x03bc +#define IMXRT_PADCTL_GPIO_SD_B0_05_OFFSET 0x03c0 +#define IMXRT_PADCTL_GPIO_SD_B1_00_OFFSET 0x03c4 +#define IMXRT_PADCTL_GPIO_SD_B1_01_OFFSET 0x03c8 +#define IMXRT_PADCTL_GPIO_SD_B1_02_OFFSET 0x03cc +#define IMXRT_PADCTL_GPIO_SD_B1_03_OFFSET 0x03d0 +#define IMXRT_PADCTL_GPIO_SD_B1_04_OFFSET 0x03d4 +#define IMXRT_PADCTL_GPIO_SD_B1_05_OFFSET 0x03d8 +#define IMXRT_PADCTL_GPIO_SD_B1_06_OFFSET 0x03dc +#define IMXRT_PADCTL_GPIO_SD_B1_07_OFFSET 0x03e0 +#define IMXRT_PADCTL_GPIO_SD_B1_08_OFFSET 0x03e4 +#define IMXRT_PADCTL_GPIO_SD_B1_09_OFFSET 0x03e8 +#define IMXRT_PADCTL_GPIO_SD_B1_10_OFFSET 0x03ec +#define IMXRT_PADCTL_GPIO_SD_B1_11_OFFSET 0x03f0 + +/* Select Input Register Offsets */ + +#define IMXRT_INPUT_ANATOP_USB_OTG1_ID_OFFSET 0x03f4 +#define IMXRT_INPUT_ANATOP_USB_OTG2_ID_OFFSET 0x03f8 +#define IMXRT_INPUT_CCM_PMIC_READY_OFFSET 0x03fc +#define IMXRT_INPUT_CSI_DATA02_OFFSET 0x0400 +#define IMXRT_INPUT_CSI_DATA03_OFFSET 0x0404 +#define IMXRT_INPUT_CSI_DATA04_OFFSET 0x0408 +#define IMXRT_INPUT_CSI_DATA05_OFFSET 0x040c +#define IMXRT_INPUT_CSI_DATA06_OFFSET 0x0410 +#define IMXRT_INPUT_CSI_DATA07_OFFSET 0x0414 +#define IMXRT_INPUT_CSI_DATA08_OFFSET 0x0418 +#define IMXRT_INPUT_CSI_DATA09_OFFSET 0x041c +#define IMXRT_INPUT_CSI_HSYNC_OFFSET 0x0420 +#define IMXRT_INPUT_CSI_PIXCLK_OFFSET 0x0424 +#define IMXRT_INPUT_CSI_VSYNC_OFFSET 0x0428 +#define IMXRT_INPUT_ENET_IPG_CLK_RMII_OFFSET 0x042c +#define IMXRT_INPUT_ENET_MDIO_OFFSET 0x0430 +#define IMXRT_INPUT_ENET0_RXDATA_OFFSET 0x0434 +#define IMXRT_INPUT_ENET1_RXDATA_OFFSET 0x0438 +#define IMXRT_INPUT_ENET_RXEN_OFFSET 0x043c +#define IMXRT_INPUT_ENET_RXERR_OFFSET 0x0440 +#define IMXRT_INPUT_ENET0_TIMER_OFFSET 0x0444 +#define IMXRT_INPUT_ENET_TXCLK_OFFSET 0x0448 +#define IMXRT_INPUT_FLEXCAN1_RX_OFFSET 0x044c +#define IMXRT_INPUT_FLEXCAN2_RX_OFFSET 0x0450 +#define IMXRT_INPUT_FLEXPWM1_PWMA3_OFFSET 0x0454 +#define IMXRT_INPUT_FLEXPWM1_PWMA0_OFFSET 0x0458 +#define IMXRT_INPUT_FLEXPWM1_PWMA1_OFFSET 0x045c +#define IMXRT_INPUT_FLEXPWM1_PWMA2_OFFSET 0x0460 +#define IMXRT_INPUT_FLEXPWM1_PWMB3_OFFSET 0x0464 +#define IMXRT_INPUT_FLEXPWM1_PWMB0_OFFSET 0x0468 +#define IMXRT_INPUT_FLEXPWM1_PWMB1_OFFSET 0x046c +#define IMXRT_INPUT_FLEXPWM1_PWMB2_OFFSET 0x0470 +#define IMXRT_INPUT_FLEXPWM2_PWMA3_OFFSET 0x0474 +#define IMXRT_INPUT_FLEXPWM2_PWMA0_OFFSET 0x0478 +#define IMXRT_INPUT_FLEXPWM2_PWMA1_OFFSET 0x047c +#define IMXRT_INPUT_FLEXPWM2_PWMA2_OFFSET 0x0480 +#define IMXRT_INPUT_FLEXPWM2_PWMB3_OFFSET 0x0484 +#define IMXRT_INPUT_FLEXPWM2_PWMB0_OFFSET 0x0488 +#define IMXRT_INPUT_FLEXPWM2_PWMB1_OFFSET 0x048c +#define IMXRT_INPUT_FLEXPWM2_PWMB2_OFFSET 0x0490 +#define IMXRT_INPUT_FLEXPWM4_PWMA0_OFFSET 0x0494 +#define IMXRT_INPUT_FLEXPWM4_PWMA1_OFFSET 0x0498 +#define IMXRT_INPUT_FLEXPWM4_PWMA2_OFFSET 0x049c +#define IMXRT_INPUT_FLEXPWM4_PWMA3_OFFSET 0x04a0 +#define IMXRT_INPUT_FLEXSPIA_DQS_OFFSET 0x04a4 +#define IMXRT_INPUT_FLEXSPIA_DATA0_OFFSET 0x04a8 +#define IMXRT_INPUT_FLEXSPIA_DATA1_OFFSET 0x04ac +#define IMXRT_INPUT_FLEXSPIA_DATA2_OFFSET 0x04b0 +#define IMXRT_INPUT_FLEXSPIA_DATA3_OFFSET 0x04b4 +#define IMXRT_INPUT_FLEXSPIB_DATA0_OFFSET 0x04b8 +#define IMXRT_INPUT_FLEXSPIB_DATA1_OFFSET 0x04bc +#define IMXRT_INPUT_FLEXSPIB_DATA2_OFFSET 0x04c0 +#define IMXRT_INPUT_FLEXSPIB_DATA3_OFFSET 0x04c4 +#define IMXRT_INPUT_FLEXSPIA_SCK_OFFSET 0x04c8 +#define IMXRT_INPUT_LPI2C1_SCL_OFFSET 0x04cc +#define IMXRT_INPUT_LPI2C1_SDA_OFFSET 0x04d0 +#define IMXRT_INPUT_LPI2C2_SCL_OFFSET 0x04d4 +#define IMXRT_INPUT_LPI2C2_SDA_OFFSET 0x04d8 +#define IMXRT_INPUT_LPI2C3_SCL_OFFSET 0x04dc +#define IMXRT_INPUT_LPI2C3_SDA_OFFSET 0x04e0 +#define IMXRT_INPUT_LPI2C4_SCL_OFFSET 0x04e4 +#define IMXRT_INPUT_LPI2C4_SDA_OFFSET 0x04e8 +#define IMXRT_INPUT_LPSPI1_PCS0_OFFSET 0x04ec +#define IMXRT_INPUT_LPSPI1_SCK_OFFSET 0x04f0 +#define IMXRT_INPUT_LPSPI1_SDI_OFFSET 0x04f4 +#define IMXRT_INPUT_LPSPI1_SDO_OFFSET 0x04f8 +#define IMXRT_INPUT_LPSPI2_PCS0_OFFSET 0x04fc +#define IMXRT_INPUT_LPSPI2_SCK_OFFSET 0x0500 +#define IMXRT_INPUT_LPSPI2_SDI_OFFSET 0x0504 +#define IMXRT_INPUT_LPSPI2_SDO_OFFSET 0x0508 +#define IMXRT_INPUT_LPSPI3_PCS0_OFFSET 0x050c +#define IMXRT_INPUT_LPSPI3_SCK_OFFSET 0x0510 +#define IMXRT_INPUT_LPSPI3_SDI_OFFSET 0x0514 +#define IMXRT_INPUT_LPSPI3_SDO_OFFSET 0x0518 +#define IMXRT_INPUT_LPSPI4_PCS0_OFFSET 0x051c +#define IMXRT_INPUT_LPSPI4_SCK_OFFSET 0x0520 +#define IMXRT_INPUT_LPSPI4_SDI_OFFSET 0x0524 +#define IMXRT_INPUT_LPSPI4_SDO_OFFSET 0x0528 +#define IMXRT_INPUT_LPUART2_RX_OFFSET 0x052c +#define IMXRT_INPUT_LPUART2_TX_OFFSET 0x0530 +#define IMXRT_INPUT_LPUART3_CTS_B_OFFSET 0x0534 +#define IMXRT_INPUT_LPUART3_RX_OFFSET 0x0538 +#define IMXRT_INPUT_LPUART3_TX_OFFSET 0x053c +#define IMXRT_INPUT_LPUART4_RX_OFFSET 0x0540 +#define IMXRT_INPUT_LPUART4_TX_OFFSET 0x0544 +#define IMXRT_INPUT_LPUART5_RX_OFFSET 0x0548 +#define IMXRT_INPUT_LPUART5_TX_OFFSET 0x054c +#define IMXRT_INPUT_LPUART6_RX_OFFSET 0x0550 +#define IMXRT_INPUT_LPUART6_TX_OFFSET 0x0554 +#define IMXRT_INPUT_LPUART7_RX_OFFSET 0x0558 +#define IMXRT_INPUT_LPUART7_TX_OFFSET 0x055c +#define IMXRT_INPUT_LPUART8_RX_OFFSET 0x0560 +#define IMXRT_INPUT_LPUART8_TX_OFFSET 0x0564 +#define IMXRT_INPUT_NMI_GLUE_NMI_OFFSET 0x0568 +#define IMXRT_INPUT_QTIMER2_TIMER0_OFFSET 0x056c +#define IMXRT_INPUT_QTIMER2_TIMER1_OFFSET 0x0570 +#define IMXRT_INPUT_QTIMER2_TIMER2_OFFSET 0x0574 +#define IMXRT_INPUT_QTIMER2_TIMER3_OFFSET 0x0578 +#define IMXRT_INPUT_QTIMER3_TIMER0_OFFSET 0x057c +#define IMXRT_INPUT_QTIMER3_TIMER1_OFFSET 0x0580 +#define IMXRT_INPUT_QTIMER3_TIMER2_OFFSET 0x0584 +#define IMXRT_INPUT_QTIMER3_TIMER3_OFFSET 0x0588 +#define IMXRT_INPUT_SAI1_MCLK2_OFFSET 0x058c +#define IMXRT_INPUT_SAI1_RX_BCLK_OFFSET 0x0590 +#define IMXRT_INPUT_SAI1_RX_DATA0_OFFSET 0x0594 +#define IMXRT_INPUT_SAI1_RX_DATA1_OFFSET 0x0598 +#define IMXRT_INPUT_SAI1_RX_DATA2_OFFSET 0x059c +#define IMXRT_INPUT_SAI1_RX_DATA3_OFFSET 0x05a0 +#define IMXRT_INPUT_SAI1_RX_SYNC_OFFSET 0x05a4 +#define IMXRT_INPUT_SAI1_TX_BCLK_OFFSET 0x05a8 +#define IMXRT_INPUT_SAI1_TX_SYNC_OFFSET 0x05ac +#define IMXRT_INPUT_SAI2_MCLK2_OFFSET 0x05b0 +#define IMXRT_INPUT_SAI2_RX_BCLK_OFFSET 0x05b4 +#define IMXRT_INPUT_SAI2_RX_DATA0_OFFSET 0x05b8 +#define IMXRT_INPUT_SAI2_RX_SYNC_OFFSET 0x05bc +#define IMXRT_INPUT_SAI2_TX_BCLK_OFFSET 0x05c0 +#define IMXRT_INPUT_SAI2_TX_SYNC_OFFSET 0x05c4 +#define IMXRT_INPUT_SPDIF_IN_OFFSET 0x05c8 +#define IMXRT_INPUT_USB_OTG2_OC_OFFSET 0x05cc +#define IMXRT_INPUT_USB_OTG1_OC_OFFSET 0x05d0 +#define IMXRT_INPUT_USDHC1_CD_B_OFFSET 0x05d4 +#define IMXRT_INPUT_USDHC1_WP_OFFSET 0x05d8 +#define IMXRT_INPUT_USDHC2_CLK_OFFSET 0x05dc +#define IMXRT_INPUT_USDHC2_CD_B_OFFSET 0x05e0 +#define IMXRT_INPUT_USDHC2_CMD_OFFSET 0x05e4 +#define IMXRT_INPUT_USDHC2_DATA0_OFFSET 0x05e8 +#define IMXRT_INPUT_USDHC2_DATA1_OFFSET 0x05ec +#define IMXRT_INPUT_USDHC2_DATA2_OFFSET 0x05f0 +#define IMXRT_INPUT_USDHC2_DATA3_OFFSET 0x05f4 +#define IMXRT_INPUT_USDHC2_DATA4_OFFSET 0x05f8 +#define IMXRT_INPUT_USDHC2_DATA5_OFFSET 0x05fc +#define IMXRT_INPUT_USDHC2_DATA6_OFFSET 0x0600 +#define IMXRT_INPUT_USDHC2_DATA7_OFFSET 0x0604 +#define IMXRT_INPUT_USDHC2_WP_OFFSET 0x0608 +#define IMXRT_INPUT_XBAR1_IN02_OFFSET 0x060c +#define IMXRT_INPUT_XBAR1_IN03_OFFSET 0x0610 +#define IMXRT_INPUT_XBAR1_IN04_OFFSET 0x0614 +#define IMXRT_INPUT_XBAR1_IN05_OFFSET 0x0618 +#define IMXRT_INPUT_XBAR1_IN06_OFFSET 0x061c +#define IMXRT_INPUT_XBAR1_IN07_OFFSET 0x0620 +#define IMXRT_INPUT_XBAR1_IN08_OFFSET 0x0624 +#define IMXRT_INPUT_XBAR1_IN09_OFFSET 0x0628 +#define IMXRT_INPUT_XBAR1_IN17_OFFSET 0x062c +#define IMXRT_INPUT_XBAR1_IN18_OFFSET 0x0630 +#define IMXRT_INPUT_XBAR1_IN20_OFFSET 0x0634 +#define IMXRT_INPUT_XBAR1_IN22_OFFSET 0x0638 +#define IMXRT_INPUT_XBAR1_IN23_OFFSET 0x063c +#define IMXRT_INPUT_XBAR1_IN24_OFFSET 0x0640 +#define IMXRT_INPUT_XBAR1_IN14_OFFSET 0x0644 +#define IMXRT_INPUT_XBAR1_IN15_OFFSET 0x0648 +#define IMXRT_INPUT_XBAR1_IN16_OFFSET 0x064c +#define IMXRT_INPUT_XBAR1_IN25_OFFSET 0x0650 +#define IMXRT_INPUT_XBAR1_IN19_OFFSET 0x0654 +#define IMXRT_INPUT_XBAR1_IN21_OFFSET 0x0658 + +/* Register addresses ***************************************************************/ + +#define IMXRT_IOMUXC_GPR_GPR0 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR0_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR1 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR1_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR2 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR2_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR3 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR3_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR4 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR4_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR5 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR5_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR6 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR6_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR7 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR7_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR8 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR8_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR9 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR9_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR10 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR10_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR11 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR11_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR12 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR12_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR13 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR13_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR14 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR14_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR15 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR15_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR16 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR16_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR17 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR17_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR18 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR18_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR19 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR19_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR20 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR20_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR21 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR21_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR22 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR22_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR23 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR23_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR24 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR24_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR25 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR25_OFFSET) + +#define IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEU (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEU_OFFSET) +#define IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_OFFSET) +#define IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_OFFSET) +#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_OFFSET) +#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_OFFSET) +#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_OFFSET) +#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_OFFSET) +#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_OFFSET) +#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_OFFSET) + +#define IMXRT_IOMUXC_SNVS_GPR_GPR0 (IMXRT_IOMUXCSNVSGPR_BASE + IMXRT_IOMUXC_SNVS_GPR_GPR0_OFFSET) +#define IMXRT_IOMUXC_SNVS_GPR_GPR1 (IMXRT_IOMUXCSNVSGPR_BASE + IMXRT_IOMUXC_SNVS_GPR_GPR1_OFFSET) +#define IMXRT_IOMUXC_SNVS_GPR_GPR2 (IMXRT_IOMUXCSNVSGPR_BASE + IMXRT_IOMUXC_SNVS_GPR_GPR2_OFFSET) +#define IMXRT_IOMUXC_SNVS_GPR_GPR3 (IMXRT_IOMUXCSNVSGPR_BASE + IMXRT_IOMUXC_SNVS_GPR_GPR3_OFFSET) + +/* Pad Mux Registers */ + +#define IMXRT_PADMUX_ADDRESS(n) (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_OFFSET(n)) + +#define IMXRT_PADMUX_GPIO_EMC_00 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_00_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_01 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_01_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_02 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_02_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_03 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_03_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_04 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_04_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_05 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_05_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_06 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_06_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_07 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_07_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_08 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_08_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_09 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_09_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_10 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_10_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_11 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_11_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_12 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_12_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_13 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_13_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_14 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_14_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_15 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_15_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_16 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_16_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_17 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_17_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_18 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_18_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_19 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_19_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_20 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_20_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_21 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_21_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_22 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_22_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_23 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_23_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_24 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_24_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_25 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_25_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_26 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_26_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_27 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_27_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_28 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_28_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_29 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_29_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_30 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_30_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_31 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_31_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_32 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_32_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_33 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_33_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_34 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_34_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_35 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_35_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_36 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_36_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_37 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_37_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_38 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_38_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_39 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_39_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_40 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_40_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_41 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_41_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B0_00 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_00_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B0_01 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_01_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B0_02 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_02_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B0_03 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_03_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B0_04 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_04_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B0_05 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_05_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B0_06 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_06_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B0_07 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_07_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B0_08 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_08_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B0_09 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_09_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B0_10 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_10_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B0_11 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_11_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B0_12 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_12_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B0_13 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_13_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B0_14 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_14_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B0_15 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_15_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B1_00 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_00_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B1_01 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_01_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B1_02 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_02_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B1_03 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_03_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B1_04 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_04_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B1_05 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_05_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B1_06 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_06_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B1_07 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_07_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B1_08 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_08_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B1_09 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_09_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B1_10 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_10_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B1_11 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_11_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B1_12 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_12_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B1_13 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_13_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B1_14 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_14_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B1_15 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_15_OFFSET) +#define IMXRT_PADMUX_GPIO_B0_00 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_00_OFFSET) +#define IMXRT_PADMUX_GPIO_B0_01 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_01_OFFSET) +#define IMXRT_PADMUX_GPIO_B0_02 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_02_OFFSET) +#define IMXRT_PADMUX_GPIO_B0_03 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_03_OFFSET) +#define IMXRT_PADMUX_GPIO_B0_04 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_04_OFFSET) +#define IMXRT_PADMUX_GPIO_B0_05 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_05_OFFSET) +#define IMXRT_PADMUX_GPIO_B0_06 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_06_OFFSET) +#define IMXRT_PADMUX_GPIO_B0_07 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_07_OFFSET) +#define IMXRT_PADMUX_GPIO_B0_08 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_08_OFFSET) +#define IMXRT_PADMUX_GPIO_B0_09 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_09_OFFSET) +#define IMXRT_PADMUX_GPIO_B0_10 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_10_OFFSET) +#define IMXRT_PADMUX_GPIO_B0_11 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_11_OFFSET) +#define IMXRT_PADMUX_GPIO_B0_12 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_12_OFFSET) +#define IMXRT_PADMUX_GPIO_B0_13 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_13_OFFSET) +#define IMXRT_PADMUX_GPIO_B0_14 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_14_OFFSET) +#define IMXRT_PADMUX_GPIO_B0_15 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_15_OFFSET) +#define IMXRT_PADMUX_GPIO_B1_00 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_00_OFFSET) +#define IMXRT_PADMUX_GPIO_B1_01 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_01_OFFSET) +#define IMXRT_PADMUX_GPIO_B1_02 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_02_OFFSET) +#define IMXRT_PADMUX_GPIO_B1_03 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_03_OFFSET) +#define IMXRT_PADMUX_GPIO_B1_04 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_04_OFFSET) +#define IMXRT_PADMUX_GPIO_B1_05 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_05_OFFSET) +#define IMXRT_PADMUX_GPIO_B1_06 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_06_OFFSET) +#define IMXRT_PADMUX_GPIO_B1_07 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_07_OFFSET) +#define IMXRT_PADMUX_GPIO_B1_08 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_08_OFFSET) +#define IMXRT_PADMUX_GPIO_B1_09 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_09_OFFSET) +#define IMXRT_PADMUX_GPIO_B1_10 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_10_OFFSET) +#define IMXRT_PADMUX_GPIO_B1_11 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_11_OFFSET) +#define IMXRT_PADMUX_GPIO_B1_12 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_12_OFFSET) +#define IMXRT_PADMUX_GPIO_B1_13 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_13_OFFSET) +#define IMXRT_PADMUX_GPIO_B1_14 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_14_OFFSET) +#define IMXRT_PADMUX_GPIO_B1_15 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_15_OFFSET) +#define IMXRT_PADMUX_GPIO_SD_B0_00 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B0_00_OFFSET) +#define IMXRT_PADMUX_GPIO_SD_B0_01 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B0_01_OFFSET) +#define IMXRT_PADMUX_GPIO_SD_B0_02 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B0_02_OFFSET) +#define IMXRT_PADMUX_GPIO_SD_B0_03 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B0_03_OFFSET) +#define IMXRT_PADMUX_GPIO_SD_B0_04 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B0_04_OFFSET) +#define IMXRT_PADMUX_GPIO_SD_B0_05 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B0_05_OFFSET) +#define IMXRT_PADMUX_GPIO_SD_B1_00 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_00_OFFSET) +#define IMXRT_PADMUX_GPIO_SD_B1_01 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_01_OFFSET) +#define IMXRT_PADMUX_GPIO_SD_B1_02 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_02_OFFSET) +#define IMXRT_PADMUX_GPIO_SD_B1_03 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_03_OFFSET) +#define IMXRT_PADMUX_GPIO_SD_B1_04 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_04_OFFSET) +#define IMXRT_PADMUX_GPIO_SD_B1_05 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_05_OFFSET) +#define IMXRT_PADMUX_GPIO_SD_B1_06 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_06_OFFSET) +#define IMXRT_PADMUX_GPIO_SD_B1_07 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_07_OFFSET) +#define IMXRT_PADMUX_GPIO_SD_B1_08 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_08_OFFSET) +#define IMXRT_PADMUX_GPIO_SD_B1_09 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_09_OFFSET) +#define IMXRT_PADMUX_GPIO_SD_B1_10 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_10_OFFSET) +#define IMXRT_PADMUX_GPIO_SD_B1_11 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_11_OFFSET) + +/* Pad Control Registers */ + +#define IMXRT_PADCTL_ADDRESS(n) (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_OFFSET(n)) + +#define IMXRT_PADCTL_GPIO_EMC_00 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_00_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_01 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_01_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_02 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_02_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_03 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_03_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_04 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_04_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_05 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_05_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_06 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_06_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_07 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_07_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_08 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_08_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_09 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_09_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_10 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_10_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_11 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_11_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_12 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_12_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_13 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_13_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_14 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_14_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_15 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_15_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_16 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_16_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_17 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_17_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_18 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_18_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_19 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_19_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_20 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_20_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_21 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_21_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_22 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_22_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_23 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_23_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_24 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_24_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_25 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_25_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_26 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_26_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_27 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_27_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_28 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_28_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_29 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_29_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_30 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_30_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_31 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_31_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_32 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_32_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_33 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_33_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_34 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_34_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_35 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_35_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_36 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_36_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_37 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_37_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_38 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_38_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_39 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_39_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_40 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_40_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_41 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_41_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B0_00 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_00_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B0_01 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_01_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B0_02 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_02_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B0_03 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_03_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B0_04 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_04_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B0_05 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_05_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B0_06 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_06_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B0_07 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_07_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B0_08 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_08_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B0_09 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_09_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B0_10 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_10_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B0_11 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_11_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B0_12 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_12_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B0_13 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_13_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B0_14 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_14_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B0_15 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_15_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B1_00 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_00_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B1_01 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_01_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B1_02 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_02_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B1_03 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_03_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B1_04 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_04_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B1_05 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_05_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B1_06 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_06_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B1_07 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_07_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B1_08 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_08_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B1_09 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_09_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B1_10 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_10_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B1_11 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_11_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B1_12 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_12_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B1_13 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_13_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B1_14 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_14_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B1_15 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_15_OFFSET) +#define IMXRT_PADCTL_GPIO_B0_00 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_00_OFFSET) +#define IMXRT_PADCTL_GPIO_B0_01 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_01_OFFSET) +#define IMXRT_PADCTL_GPIO_B0_02 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_02_OFFSET) +#define IMXRT_PADCTL_GPIO_B0_03 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_03_OFFSET) +#define IMXRT_PADCTL_GPIO_B0_04 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_04_OFFSET) +#define IMXRT_PADCTL_GPIO_B0_05 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_05_OFFSET) +#define IMXRT_PADCTL_GPIO_B0_06 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_06_OFFSET) +#define IMXRT_PADCTL_GPIO_B0_07 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_07_OFFSET) +#define IMXRT_PADCTL_GPIO_B0_08 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_08_OFFSET) +#define IMXRT_PADCTL_GPIO_B0_09 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_09_OFFSET) +#define IMXRT_PADCTL_GPIO_B0_10 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_10_OFFSET) +#define IMXRT_PADCTL_GPIO_B0_11 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_11_OFFSET) +#define IMXRT_PADCTL_GPIO_B0_12 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_12_OFFSET) +#define IMXRT_PADCTL_GPIO_B0_13 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_13_OFFSET) +#define IMXRT_PADCTL_GPIO_B0_14 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_14_OFFSET) +#define IMXRT_PADCTL_GPIO_B0_15 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_15_OFFSET) +#define IMXRT_PADCTL_GPIO_B1_00 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_00_OFFSET) +#define IMXRT_PADCTL_GPIO_B1_01 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_01_OFFSET) +#define IMXRT_PADCTL_GPIO_B1_02 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_02_OFFSET) +#define IMXRT_PADCTL_GPIO_B1_03 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_03_OFFSET) +#define IMXRT_PADCTL_GPIO_B1_04 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_04_OFFSET) +#define IMXRT_PADCTL_GPIO_B1_05 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_05_OFFSET) +#define IMXRT_PADCTL_GPIO_B1_06 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_06_OFFSET) +#define IMXRT_PADCTL_GPIO_B1_07 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_07_OFFSET) +#define IMXRT_PADCTL_GPIO_B1_08 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_08_OFFSET) +#define IMXRT_PADCTL_GPIO_B1_09 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_09_OFFSET) +#define IMXRT_PADCTL_GPIO_B1_10 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_10_OFFSET) +#define IMXRT_PADCTL_GPIO_B1_11 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_11_OFFSET) +#define IMXRT_PADCTL_GPIO_B1_12 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_12_OFFSET) +#define IMXRT_PADCTL_GPIO_B1_13 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_13_OFFSET) +#define IMXRT_PADCTL_GPIO_B1_14 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_14_OFFSET) +#define IMXRT_PADCTL_GPIO_B1_15 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_15_OFFSET) +#define IMXRT_PADCTL_GPIO_SD_B0_00 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B0_00_OFFSET) +#define IMXRT_PADCTL_GPIO_SD_B0_01 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B0_01_OFFSET) +#define IMXRT_PADCTL_GPIO_SD_B0_02 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B0_02_OFFSET) +#define IMXRT_PADCTL_GPIO_SD_B0_03 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B0_03_OFFSET) +#define IMXRT_PADCTL_GPIO_SD_B0_04 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B0_04_OFFSET) +#define IMXRT_PADCTL_GPIO_SD_B0_05 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B0_05_OFFSET) +#define IMXRT_PADCTL_GPIO_SD_B1_00 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_00_OFFSET) +#define IMXRT_PADCTL_GPIO_SD_B1_01 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_01_OFFSET) +#define IMXRT_PADCTL_GPIO_SD_B1_02 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_02_OFFSET) +#define IMXRT_PADCTL_GPIO_SD_B1_03 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_03_OFFSET) +#define IMXRT_PADCTL_GPIO_SD_B1_04 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_04_OFFSET) +#define IMXRT_PADCTL_GPIO_SD_B1_05 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_05_OFFSET) +#define IMXRT_PADCTL_GPIO_SD_B1_06 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_06_OFFSET) +#define IMXRT_PADCTL_GPIO_SD_B1_07 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_07_OFFSET) +#define IMXRT_PADCTL_GPIO_SD_B1_08 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_08_OFFSET) +#define IMXRT_PADCTL_GPIO_SD_B1_09 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_09_OFFSET) +#define IMXRT_PADCTL_GPIO_SD_B1_10 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_10_OFFSET) +#define IMXRT_PADCTL_GPIO_SD_B1_11 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_11_OFFSET) + +/* Select Input Registers */ + +#define IMXRT_INPUT_ANATOP_USB_OTG1_ID (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ANATOP_USB_OTG1_ID_OFFSET) +#define IMXRT_INPUT_ANATOP_USB_OTG2_ID (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ANATOP_USB_OTG2_ID_OFFSET) +#define IMXRT_INPUT_CCM_PMIC_READY (IMXRT_IOMUXC_BASE + IMXRT_INPUT_CCM_PMIC_READY_OFFSET) +#define IMXRT_INPUT_CSI_DATA02 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_CSI_DATA02_OFFSET) +#define IMXRT_INPUT_CSI_DATA03 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_CSI_DATA03_OFFSET) +#define IMXRT_INPUT_CSI_DATA04 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_CSI_DATA04_OFFSET) +#define IMXRT_INPUT_CSI_DATA05 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_CSI_DATA05_OFFSET) +#define IMXRT_INPUT_CSI_DATA06 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_CSI_DATA06_OFFSET) +#define IMXRT_INPUT_CSI_DATA07 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_CSI_DATA07_OFFSET) +#define IMXRT_INPUT_CSI_DATA08 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_CSI_DATA08_OFFSET) +#define IMXRT_INPUT_CSI_DATA09 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_CSI_DATA09_OFFSET) +#define IMXRT_INPUT_CSI_HSYNC (IMXRT_IOMUXC_BASE + IMXRT_INPUT_CSI_HSYNC_OFFSET) +#define IMXRT_INPUT_CSI_PIXCLK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_CSI_PIXCLK_OFFSET) +#define IMXRT_INPUT_CSI_VSYNC (IMXRT_IOMUXC_BASE + IMXRT_INPUT_CSI_VSYNC_OFFSET) +#define IMXRT_INPUT_ENET_IPG_CLK_RMII (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET_IPG_CLK_RMII_OFFSET) +#define IMXRT_INPUT_ENET_MDIO (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET_MDIO_OFFSET) +#define IMXRT_INPUT_ENET0_RXDATA (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET0_RXDATA_OFFSET) +#define IMXRT_INPUT_ENET1_RXDATA (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET1_RXDATA_OFFSET) +#define IMXRT_INPUT_ENET_RXEN (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET_RXEN_OFFSET) +#define IMXRT_INPUT_ENET_RXERR (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET_RXERR_OFFSET) +#define IMXRT_INPUT_ENET0_TIMER (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET0_TIMER_OFFSET) +#define IMXRT_INPUT_ENET_TXCLK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET_TXCLK_OFFSET) +#define IMXRT_INPUT_FLEXCAN1_RX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXCAN1_RX_OFFSET) +#define IMXRT_INPUT_FLEXCAN2_RX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXCAN2_RX_OFFSET) +#define IMXRT_INPUT_FLEXPWM1_PWMA3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM1_PWMA3_OFFSET) +#define IMXRT_INPUT_FLEXPWM1_PWMA0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM1_PWMA0_OFFSET) +#define IMXRT_INPUT_FLEXPWM1_PWMA1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM1_PWMA1_OFFSET) +#define IMXRT_INPUT_FLEXPWM1_PWMA2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM1_PWMA2_OFFSET) +#define IMXRT_INPUT_FLEXPWM1_PWMB3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM1_PWMB3_OFFSET) +#define IMXRT_INPUT_FLEXPWM1_PWMB0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM1_PWMB0_OFFSET) +#define IMXRT_INPUT_FLEXPWM1_PWMB1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM1_PWMB1_OFFSET) +#define IMXRT_INPUT_FLEXPWM1_PWMB2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM1_PWMB2_OFFSET) +#define IMXRT_INPUT_FLEXPWM2_PWMA3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM2_PWMA3_OFFSET) +#define IMXRT_INPUT_FLEXPWM2_PWMA0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM2_PWMA0_OFFSET) +#define IMXRT_INPUT_FLEXPWM2_PWMA1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM2_PWMA1_OFFSET) +#define IMXRT_INPUT_FLEXPWM2_PWMA2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM2_PWMA2_OFFSET) +#define IMXRT_INPUT_FLEXPWM2_PWMB3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM2_PWMB3_OFFSET) +#define IMXRT_INPUT_FLEXPWM2_PWMB0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM2_PWMB0_OFFSET) +#define IMXRT_INPUT_FLEXPWM2_PWMB1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM2_PWMB1_OFFSET) +#define IMXRT_INPUT_FLEXPWM2_PWMB2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM2_PWMB2_OFFSET) +#define IMXRT_INPUT_FLEXPWM4_PWMA0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM4_PWMA0_OFFSET) +#define IMXRT_INPUT_FLEXPWM4_PWMA1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM4_PWMA1_OFFSET) +#define IMXRT_INPUT_FLEXPWM4_PWMA2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM4_PWMA2_OFFSET) +#define IMXRT_INPUT_FLEXPWM4_PWMA3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM4_PWMA3_OFFSET) +#define IMXRT_INPUT_FLEXSPIA_DQS (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPIA_DQS_OFFSET) +#define IMXRT_INPUT_FLEXSPIA_DATA0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPIA_DATA0_OFFSET) +#define IMXRT_INPUT_FLEXSPIA_DATA1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPIA_DATA1_OFFSET) +#define IMXRT_INPUT_FLEXSPIA_DATA2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPIA_DATA2_OFFSET) +#define IMXRT_INPUT_FLEXSPIA_DATA3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPIA_DATA3_OFFSET) +#define IMXRT_INPUT_FLEXSPIB_DATA0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPIB_DATA0_OFFSET) +#define IMXRT_INPUT_FLEXSPIB_DATA1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPIB_DATA1_OFFSET) +#define IMXRT_INPUT_FLEXSPIB_DATA2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPIB_DATA2_OFFSET) +#define IMXRT_INPUT_FLEXSPIB_DATA3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPIB_DATA3_OFFSET) +#define IMXRT_INPUT_FLEXSPIA_SCK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPIA_SCK_OFFSET) +#define IMXRT_INPUT_LPI2C1_SCL (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPI2C1_SCL_OFFSET) +#define IMXRT_INPUT_LPI2C1_SDA (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPI2C1_SDA_OFFSET) +#define IMXRT_INPUT_LPI2C2_SCL (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPI2C2_SCL_OFFSET) +#define IMXRT_INPUT_LPI2C2_SDA (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPI2C2_SDA_OFFSET) +#define IMXRT_INPUT_LPI2C3_SCL (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPI2C3_SCL_OFFSET) +#define IMXRT_INPUT_LPI2C3_SDA (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPI2C3_SDA_OFFSET) +#define IMXRT_INPUT_LPI2C4_SCL (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPI2C4_SCL_OFFSET) +#define IMXRT_INPUT_LPI2C4_SDA (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPI2C4_SDA_OFFSET) +#define IMXRT_INPUT_LPSPI1_PCS0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI1_PCS0_OFFSET) +#define IMXRT_INPUT_LPSPI1_SCK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI1_SCK_OFFSET) +#define IMXRT_INPUT_LPSPI1_SDI (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI1_SDI_OFFSET) +#define IMXRT_INPUT_LPSPI1_SDO (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI1_SDO_OFFSET) +#define IMXRT_INPUT_LPSPI2_PCS0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI2_PCS0_OFFSET) +#define IMXRT_INPUT_LPSPI2_SCK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI2_SCK_OFFSET) +#define IMXRT_INPUT_LPSPI2_SDI (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI2_SDI_OFFSET) +#define IMXRT_INPUT_LPSPI2_SDO (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI2_SDO_OFFSET) +#define IMXRT_INPUT_LPSPI3_PCS0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI3_PCS0_OFFSET) +#define IMXRT_INPUT_LPSPI3_SCK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI3_SCK_OFFSET) +#define IMXRT_INPUT_LPSPI3_SDI (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI3_SDI_OFFSET) +#define IMXRT_INPUT_LPSPI3_SDO (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI3_SDO_OFFSET) +#define IMXRT_INPUT_LPSPI4_PCS0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI4_PCS0_OFFSET) +#define IMXRT_INPUT_LPSPI4_SCK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI4_SCK_OFFSET) +#define IMXRT_INPUT_LPSPI4_SDI (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI4_SDI_OFFSET) +#define IMXRT_INPUT_LPSPI4_SDO (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI4_SDO_OFFSET) +#define IMXRT_INPUT_LPUART2_RX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART2_RX_OFFSET) +#define IMXRT_INPUT_LPUART2_TX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART2_TX_OFFSET) +#define IMXRT_INPUT_LPUART3_CTS_B (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART3_CTS_B_OFFSET) +#define IMXRT_INPUT_LPUART3_RX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART3_RX_OFFSET) +#define IMXRT_INPUT_LPUART3_TX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART3_TX_OFFSET) +#define IMXRT_INPUT_LPUART4_RX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART4_RX_OFFSET) +#define IMXRT_INPUT_LPUART4_TX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART4_TX_OFFSET) +#define IMXRT_INPUT_LPUART5_RX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART5_RX_OFFSET) +#define IMXRT_INPUT_LPUART5_TX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART5_TX_OFFSET) +#define IMXRT_INPUT_LPUART6_RX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART6_RX_OFFSET) +#define IMXRT_INPUT_LPUART6_TX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART6_TX_OFFSET) +#define IMXRT_INPUT_LPUART7_RX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART7_RX_OFFSET) +#define IMXRT_INPUT_LPUART7_TX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART7_TX_OFFSET) +#define IMXRT_INPUT_LPUART8_RX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART8_RX_OFFSET) +#define IMXRT_INPUT_LPUART8_TX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART8_TX_OFFSET) +#define IMXRT_INPUT_NMI_GLUE_NMI (IMXRT_IOMUXC_BASE + IMXRT_INPUT_NMI_GLUE_NMI_OFFSET) +#define IMXRT_INPUT_QTIMER2_TIMER0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_QTIMER2_TIMER0_OFFSET) +#define IMXRT_INPUT_QTIMER2_TIMER1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_QTIMER2_TIMER1_OFFSET) +#define IMXRT_INPUT_QTIMER2_TIMER2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_QTIMER2_TIMER2_OFFSET) +#define IMXRT_INPUT_QTIMER2_TIMER3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_QTIMER2_TIMER3_OFFSET) +#define IMXRT_INPUT_QTIMER3_TIMER0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_QTIMER3_TIMER0_OFFSET) +#define IMXRT_INPUT_QTIMER3_TIMER1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_QTIMER3_TIMER1_OFFSET) +#define IMXRT_INPUT_QTIMER3_TIMER2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_QTIMER3_TIMER2_OFFSET) +#define IMXRT_INPUT_QTIMER3_TIMER3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_QTIMER3_TIMER3_OFFSET) +#define IMXRT_INPUT_SAI1_MCLK2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI1_MCLK2_OFFSET) +#define IMXRT_INPUT_SAI1_RX_BCLK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI1_RX_BCLK_OFFSET) +#define IMXRT_INPUT_SAI1_RX_DATA0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI1_RX_DATA0_OFFSET) +#define IMXRT_INPUT_SAI1_RX_DATA1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI1_RX_DATA1_OFFSET) +#define IMXRT_INPUT_SAI1_RX_DATA2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI1_RX_DATA2_OFFSET) +#define IMXRT_INPUT_SAI1_RX_DATA3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI1_RX_DATA3_OFFSET) +#define IMXRT_INPUT_SAI1_RX_SYNC (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI1_RX_SYNC_OFFSET) +#define IMXRT_INPUT_SAI1_TX_BCLK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI1_TX_BCLK_OFFSET) +#define IMXRT_INPUT_SAI1_TX_SYNC (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI1_TX_SYNC_OFFSET) +#define IMXRT_INPUT_SAI2_MCLK2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI2_MCLK2_OFFSET) +#define IMXRT_INPUT_SAI2_RX_BCLK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI2_RX_BCLK_OFFSET) +#define IMXRT_INPUT_SAI2_RX_DATA0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI2_RX_DATA0_OFFSET) +#define IMXRT_INPUT_SAI2_RX_SYNC (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI2_RX_SYNC_OFFSET) +#define IMXRT_INPUT_SAI2_TX_BCLK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI2_TX_BCLK_OFFSET) +#define IMXRT_INPUT_SAI2_TX_SYNC (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI2_TX_SYNC_OFFSET) +#define IMXRT_INPUT_SPDIF_IN (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SPDIF_IN_OFFSET) +#define IMXRT_INPUT_USB_OTG2_OC (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USB_OTG2_OC_OFFSET) +#define IMXRT_INPUT_USB_OTG1_OC (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USB_OTG1_OC_OFFSET) +#define IMXRT_INPUT_USDHC1_CD_B (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC1_CD_B_OFFSET) +#define IMXRT_INPUT_USDHC1_WP (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC1_WP_OFFSET) +#define IMXRT_INPUT_USDHC2_CLK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC2_CLK_OFFSET) +#define IMXRT_INPUT_USDHC2_CD_B (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC2_CD_B_OFFSET) +#define IMXRT_INPUT_USDHC2_CMD (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC2_CMD_OFFSET) +#define IMXRT_INPUT_USDHC2_DATA0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC2_DATA0_OFFSET) +#define IMXRT_INPUT_USDHC2_DATA1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC2_DATA1_OFFSET) +#define IMXRT_INPUT_USDHC2_DATA2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC2_DATA2_OFFSET) +#define IMXRT_INPUT_USDHC2_DATA3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC2_DATA3_OFFSET) +#define IMXRT_INPUT_USDHC2_DATA4 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC2_DATA4_OFFSET) +#define IMXRT_INPUT_USDHC2_DATA5 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC2_DATA5_OFFSET) +#define IMXRT_INPUT_USDHC2_DATA6 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC2_DATA6_OFFSET) +#define IMXRT_INPUT_USDHC2_DATA7 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC2_DATA7_OFFSET) +#define IMXRT_INPUT_USDHC2_WP (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC2_WP_OFFSET) +#define IMXRT_INPUT_XBAR1_IN02 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN02_OFFSET) +#define IMXRT_INPUT_XBAR1_IN03 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN03_OFFSET) +#define IMXRT_INPUT_XBAR1_IN04 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN04_OFFSET) +#define IMXRT_INPUT_XBAR1_IN05 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN05_OFFSET) +#define IMXRT_INPUT_XBAR1_IN06 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN05_OFFSET) +#define IMXRT_INPUT_XBAR1_IN07 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN07_OFFSET) +#define IMXRT_INPUT_XBAR1_IN08 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN08_OFFSET) +#define IMXRT_INPUT_XBAR1_IN09 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN09_OFFSET) +#define IMXRT_INPUT_XBAR1_IN17 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN17_OFFSET) +#define IMXRT_INPUT_XBAR1_IN18 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN18_OFFSET) +#define IMXRT_INPUT_XBAR1_IN20 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN20_OFFSET) +#define IMXRT_INPUT_XBAR1_IN22 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN22_OFFSET) +#define IMXRT_INPUT_XBAR1_IN23 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN23_OFFSET) +#define IMXRT_INPUT_XBAR1_IN24 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN24_OFFSET) +#define IMXRT_INPUT_XBAR1_IN14 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN14_OFFSET) +#define IMXRT_INPUT_XBAR1_IN15 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN15_OFFSET) +#define IMXRT_INPUT_XBAR1_IN16 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN16_OFFSET) +#define IMXRT_INPUT_XBAR1_IN25 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN25_OFFSET) +#define IMXRT_INPUT_XBAR1_IN19 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN19_OFFSET) +#define IMXRT_INPUT_XBAR1_IN21 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN21_OFFSET) + +/* Register bit definitions *********************************************************/ + +/* General Purpose Register 1 (GPR1) */ + +#define GPR_GPR1_SAI1_MCLK1_SEL_SHIFT (0) +#define GPR_GPR1_SAI1_MCLK1_SEL_MASK (7 << GPR_GPR1_SAI1_MCLK1_SEL_SHIFT) +# define GPR_GPR1_SAI1_MCLK1_SEL_CCM_SSI1_CLK_ROOT (0 << GPR_GPR1_SAI1_MCLK1_SEL_SHIFT) +# define GPR_GPR1_SAI1_MCLK1_SEL_CCM_SSI2_CLK_ROOT (1 << GPR_GPR1_SAI1_MCLK1_SEL_SHIFT) +# define GPR_GPR1_SAI1_MCLK1_SEL_CCM_SSI3_CLK_ROOT (2 << GPR_GPR1_SAI1_MCLK1_SEL_SHIFT) +# define GPR_GPR1_SAI1_MCLK1_SEL_IOMUX_SAI1_IPG_CLK_SAI_MCLK2 (3 << GPR_GPR1_SAI1_MCLK1_SEL_SHIFT) +# define GPR_GPR1_SAI1_MCLK1_SEL_IOMUX_SAI2_IPG_CLK_SAI_MCLK2 (4 << GPR_GPR1_SAI1_MCLK1_SEL_SHIFT) +# define GPR_GPR1_SAI1_MCLK1_SEL_IOMUX_SAI3_IPG_CLK_SAI_MCLK2 (5 << GPR_GPR1_SAI1_MCLK1_SEL_SHIFT) +#define GPR_GPR1_SAI1_MCLK2_SEL_SHIFT (3) +#define GPR_GPR1_SAI1_MCLK2_SEL_MASK (7 << GPR_GPR1_SAI1_MCLK2_SEL_SHIFT) +# define GPR_GPR1_SAI1_MCLK2_SEL_CCM_SSI1_CLK_ROOT (0 << GPR_GPR1_SAI1_MCLK2_SEL_SHIFT) +# define GPR_GPR1_SAI1_MCLK2_SEL_CCM_SSI2_CLK_ROOT (1 << GPR_GPR1_SAI1_MCLK2_SEL_SHIFT) +# define GPR_GPR1_SAI1_MCLK2_SEL_CCM_SSI3_CLK_ROOT (2 << GPR_GPR1_SAI1_MCLK2_SEL_SHIFT) +# define GPR_GPR1_SAI1_MCLK2_SEL_IOMUX_SAI1_IPG_CLK_SAI_MCLK2 (3 << GPR_GPR1_SAI1_MCLK2_SEL_SHIFT) +# define GPR_GPR1_SAI1_MCLK2_SEL_IOMUX_SAI2_IPG_CLK_SAI_MCLK2 (4 << GPR_GPR1_SAI1_MCLK2_SEL_SHIFT) +# define GPR_GPR1_SAI1_MCLK2_SEL_IOMUX_SAI3_IPG_CLK_SAI_MCLK2 (5 << GPR_GPR1_SAI1_MCLK2_SEL_SHIFT) +#define GPR_GPR1_SAI1_MCLK3_SEL_SHIFT (6) +#define GPR_GPR1_SAI1_MCLK3_SEL_MASK (3 << GPR_GPR1_SAI1_MCLK3_SEL_SHIFT) +# define GPR_GPR1_SAI1_MCLK3_SEL_CCM_SPDIF0_CLK_ROOT (0 << GPR_GPR1_SAI1_MCLK3_SEL_SHIFT) +# define GPR_GPR1_SAI1_MCLK3_SEL_IOMUX_SPDIF_TX_CLK2 (1 << GPR_GPR1_SAI1_MCLK3_SEL_SHIFT) +# define GPR_GPR1_SAI1_MCLK3_SEL_SPDIF_SPDIF_SRCLK (2 << GPR_GPR1_SAI1_MCLK3_SEL_SHIFT) +# define GPR_GPR1_SAI1_MCLK3_SEL_SPDIF_SPDIF_OUTCLOCK (3 << GPR_GPR1_SAI1_MCLK3_SEL_SHIFT) +#define GPR_GPR1_SAI2_MCLK3_SEL_SHIFT (8) +#define GPR_GPR1_SAI2_MCLK3_SEL_MASK (3 << GPR_GPR1_SAI2_MCLK3_SEL_SHIFT) +# define GPR_GPR1_SAI2_MCLK3_SEL_CCM_SPDIF0_CLK_ROOT (0 << GPR_GPR1_SAI2_MCLK3_SEL_SHIFT) +# define GPR_GPR1_SAI2_MCLK3_SEL_IOMUX_SPDIF_TX_CLK2 (1 << GPR_GPR1_SAI2_MCLK3_SEL_SHIFT) +# define GPR_GPR1_SAI2_MCLK3_SEL_SPDIF_SPDIF_SRCLK (2 << GPR_GPR1_SAI2_MCLK3_SEL_SHIFT) +# define GPR_GPR1_SAI2_MCLK3_SEL_SPDIF_SPDIF_OUTCLOCK (3 << GPR_GPR1_SAI2_MCLK3_SEL_SHIFT) +#define GPR_GPR1_SAI3_MCLK3_SEL_SHIFT (10) +#define GPR_GPR1_SAI3_MCLK3_SEL_MASK (3 << GPR_GPR1_SAI3_MCLK3_SEL_SHIFT) +# define GPR_GPR1_SAI3_MCLK3_SEL_CCM_SPDIF0_CLK_ROOT (0 << GPR_GPR1_SAI3_MCLK3_SEL_SHIFT) +# define GPR_GPR1_SAI3_MCLK3_SEL_IOMUX_SPDIF_TX_CLK2 (1 << GPR_GPR1_SAI3_MCLK3_SEL_SHIFT) +# define GPR_GPR1_SAI3_MCLK3_SEL_SPDIF_SPDIF_SRCLK (2 << GPR_GPR1_SAI3_MCLK3_SEL_SHIFT) +# define GPR_GPR1_SAI3_MCLK3_SEL_SPDIF_SPDIF_OUTCLOCK (3 << GPR_GPR1_SAI3_MCLK3_SEL_SHIFT) +#define GPR_GPR1_GINT (1 << 12) +#define GPR_GPR1_ENET1_CLK_SEL (1 << 13) +#define GPR_GPR1_USB_EXP_MODE_EN (1 << 15) +#define GPR_GPR1_ENET1_TX_CLK_OUT_EN (1 << 17) +#define GPR_GPR1_SAI1_MCLK_DIR_IN (0 << 19) +#define GPR_GPR1_SAI1_MCLK_DIR_OUT (1 << 19) +#define GPR_GPR1_SAI2_MCLK_DIR_IN (0 << 20) +#define GPR_GPR1_SAI2_MCLK_DIR_OUT (1 << 20) +#define GPR_GPR1_SAI3_MCLK_DIR_IN (0 << 21) +#define GPR_GPR1_SAI3_MCLK_DIR_OUT (1 << 21) +#define GPR_GPR1_EXC_MON_OKAY (0 << 22) +#define GPR_GPR1_EXC_MON_SLVERR (1 << 22) +#define GPR_GPR1_ENET_IMG_CLS_S_EN (1 << 23) +#define GPR_GPR1_CM7_FORCE_HCLK_EN (1 << 31) + +/* General Purpose Register 2 (GPR2) */ + +#define GPR_GPR2_L2_MEM_POWERSAVE_EN (1 << 12) +#define GPR_GPR2_L2_MEM_FORCE_DEEPSLEEP (1 << 14) +#define GPR_GPR2_MQS_CLK_DIV_SHIFT (16) +#define GPR_GPR2_MQS_CLK_DIV_MASK (255 << GPR_GPR2_MQS_CLK_DIV_SHIFT) +# define GPR_GPR2_MQS_CLK_DIV(n) ((n - 1) << GPR_GPR2_MQS_CLK_DIV_SHIFT) +#define GPR_GPR2_MQS_SW_RST_EN (1 << 24) +#define GPR_GPR2_MQS_EN (1 << 25) +#define GPR_GPR2_MQS_OVERSAMPLE32 (0 << 26) +#define GPR_GPR2_MQS_OVERSAMPLE64 (1 << 26) +#define GPR_GPR2_QTIM1_TMR_RESET (1 << 28) +#define GPR_GPR2_QTIM2_TMR_RESET (1 << 29) +#define GPR_GPR2_QTIM3_TMR_RESET (1 << 30) +#define GPR_GPR2_QTIM4_TMR_RESET (1 << 31) + +/* General Purpose Register 3 (GPR3) */ +#define GPR_GPR3_OCRAM_CTL_SHIFT (0) +#define GPR_GPR3_OCRAM_CTL_MASK (15 << GPR_GPR3_OCRAM_CTL_SHIFT) +# define GPR_GPR3_OCRAM_CTL_READ_DATA_PIPELINE_EN (1 << GPR_GPR3_OCRAM_CTL_SHIFT) +# define GPR_GPR3_OCRAM_CTL_READ_ADDR_PIPELINE_EN (2 << GPR_GPR3_OCRAM_CTL_SHIFT) +# define GPR_GPR3_OCRAM_CTL_WRITE_DATA_PIPELINE_EN (4 << GPR_GPR3_OCRAM_CTL_SHIFT) +# define GPR_GPR3_OCRAM_CTL_WRITE_ADDR_PIPELINE_EN (8 << GPR_GPR3_OCRAM_CTL_SHIFT) +#define GPR_GPR3_DCP_KEY_SEL_128 (0 << 4) +#define GPR_GPR3_DCP_KEY_SEL_256 (1 << 4) + +/* General Purpose Register 4 (GPR4) */ +#define GPR_GRP4_EDMA_STOP_REQ (1 << 0) +#define GPR_GPR4_CAN1_STOP_REQ (1 << 1) +#define GPR_GPR4_CAN2_STOP_REQ (1 << 2) +#define GPR_GPR4_TRNG_STOP_REQ (1 << 3) +#define GPR_GPR4_ENET_STOP_REQ (1 << 4) +#define GPR_GPR4_SAI1_STOP_REQ (1 << 5) +#define GPR_GPR4_SAI2_STOP_REQ (1 << 6) +#define GPR_GPR4_SAI3_STOP_REQ (1 << 7) +#define GPR_GPR4_SEMC_STOP_REQ (1 << 9) +#define GPR_GPR4_PIT_STOP_REQ (1 << 10) +#define GPR_GPR4_FLEXSPI_STOP_REQ (1 << 11) +#define GPR_GPR4_FLEXIO1_STOP_REQ (1 << 12) +#define GPR_GPR4_FLEXIO2_STOP_REQ (1 << 13) + +/* General Purpose Register 5 (GPR5) */ +#define GPR_GPR5_WDOG1_MASK (1 << 6) +#define GPR_GPR5_WDOG2_MASK (1 << 7) +#define GPR_GPR5_GPT2_CAPIN1_SEL_PAD (0 << 23) +#define GPR_GPR5_GPT2_CAPIN1_SEL_ENET1 (1 << 23) +#define GPR_GPR5_GPT2_CAPIN2_SEL_PAD (0 << 24) +#define GPR_GPR5_GPT2_CAPIN2_SEL_ENET2 (1 << 24) +#define GPR_GPR5_ENET_EVENT3IN_SEL_PAD (0 << 25) +#define GPR_GPR5_ENET_EVENT3IN_SEL_ENET2 (1 << 25) +#define GPR_GPR5_VREF_1M_CLK_GPT1_IPG_PERCLK (0 << 28) +#define GPR_GPR5_VREF_1M_CLK_GPT1_ANATOP (1 << 28) +#define GPR_GPR5_VREF_1M_CLK_GPT2_IPG_PERCLK (0 << 29) +#define GPR_GPR5_VREF_1M_CLK_GPT2_ANATOP (1 << 29) + +/* Pad Mux Registers */ + +#define PADMUX_MUXMODE_SHIFT (0) /* Bit 0-2: Software Input On Field */ +#define PADMUX_MUXMODE_MASK (7 << PADMUX_MUXMODE_SHIFT) +# define PADMUX_MUXMODE_ALT0 (0 << PADMUX_MUXMODE_SHIFT) +# define PADMUX_MUXMODE_ALT1 (1 << PADMUX_MUXMODE_SHIFT) +# define PADMUX_MUXMODE_ALT2 (2 << PADMUX_MUXMODE_SHIFT) +# define PADMUX_MUXMODE_ALT3 (3 << PADMUX_MUXMODE_SHIFT) +# define PADMUX_MUXMODE_ALT4 (4 << PADMUX_MUXMODE_SHIFT) +# define PADMUX_MUXMODE_ALT5 (5 << PADMUX_MUXMODE_SHIFT) +# define PADMUX_MUXMODE_ALT7 (7 << PADMUX_MUXMODE_SHIFT) +#define PADMUX_SION (1 << 4) /* Bit 4: Software Input On Field */ + +/* Pad Control Registers */ + +#define DRIVE_HIZ (0) /* HI-Z */ +#define DRIVE_260OHM (1) /* 150 Ohm @3.3V, 260 Ohm @1.8V */ +#define DRIVE_130OHM (2) /* 75 Ohm @3.3V, 130 Ohm @1.8V */ +#define DRIVE_90OHM (3) /* 50 Ohm @3.3V, 90 Ohm @1.8V */ +#define DRIVE_60OHM (4) /* 37 Ohm @3.3V, 60 Ohm @1.8V */ +#define DRIVE_50OHM (5) /* 30 Ohm @3.3V, 50 Ohm @1.8V */ +#define DRIVE_40OHM (6) /* 25 Ohm @3.3V, 40 Ohm @1.8V */ +#define DRIVE_33OHM (7) /* 20 Ohm @3.3V, 33 Ohm @1.8V */ + +#define SPEED_LOW (0) /* Low frequency (50 MHz) */ +#define SPEED_MEDIUM (2) /* Medium frequency (100, MHz) */ +#define SPEED_MAX (3) /* Maximum frequency (200 MHz) */ + +#define PULL_DOWN_100K (0) /* 100K Ohm Pull Down */ +#define PULL_UP_47K (1) /* 47K Ohm Pull Up */ +#define PULL_UP_100K (2) /* 100K Ohm Pull Up */ +#define PULL_UP_22K (3) /* 22K Ohm Pull Up */ + +#define PADCTL_SRE (1 << 0) /* Bit 0: Slew Rate Field */ +#define PADCTL_DSE_SHIFT (3) /* Bits 3-5: Drive Strength Field */ +#define PADCTL_DSE_MASK (7 << PADCTL_DSE_SHIFT) +# define PADCTL_DSE(n) ((uint32_t)(n) << PADCTL_DSE_SHIFT) /* n=DRIVE_* */ +# define PADCTL_DSE_HIZ (0 << PADCTL_DSE_SHIFT) /* HI-Z */ +# define PADCTL_DSE_260OHM (1 << PADCTL_DSE_SHIFT) /* 150 Ohm @3.3V, 260 Ohm @1.8V */ +# define PADCTL_DSE_130OHM (2 << PADCTL_DSE_SHIFT) /* 75 Ohm @3.3V, 130 Ohm @1.8V */ +# define PADCTL_DSE_90OHM (3 << PADCTL_DSE_SHIFT) /* 50 Ohm @3.3V, 90 Ohm @1.8V */ +# define PADCTL_DSE_60OHM (4 << PADCTL_DSE_SHIFT) /* 37 Ohm @3.3V, 60 Ohm @1.8V */ +# define PADCTL_DSE_50OHM (5 << PADCTL_DSE_SHIFT) /* 30 Ohm @3.3V, 50 Ohm @1.8V */ +# define PADCTL_DSE_40OHM (6 << PADCTL_DSE_SHIFT) /* 25 Ohm @3.3V, 40 Ohm @1.8V */ +# define PADCTL_DSE_33OHM (7 << PADCTL_DSE_SHIFT) /* 20 Ohm @3.3V, 33 Ohm @1.8V */ +#define PADCTL_SPEED_SHIFT (6) /* Bits 6-7: Speed Field */ +#define PADCTL_SPEED_MASK (3 << PADCTL_SPEED_SHIFT) +# define PADCTL_SPEED(n) ((uint32_t)(n) << PADCTL_SPEED_SHIFT) /* n=SPEED_* */ +# define PADCTL_SPEED_LOW (0 << PADCTL_SPEED_SHIFT) /* Low frequency (50 MHz) */ +# define PADCTL_SPEED_MEDIUM (1 << PADCTL_SPEED_SHIFT) /* Medium frequency (100, 150 MHz) */ +# define PADCTL_SPEED_MAX (3 << PADCTL_SPEED_SHIFT) /* Maximum frequency (100, 150, 200 MHz) */ +#define PADCTL_ODE (1 << 11) /* Bit 11: Open Drain Enable Field */ +#define PADCTL_PKE (1 << 12) /* Bit 12: Pull / Keep Enable Field */ +#define PADCTL_PUE (1 << 13) /* Bit 13: Pull / Keep Select Field */ +#define PADCTL_PUS_SHIFT (14) /* Bits 14-15: Pull Up / Down Config. Field */ +#define PADCTL_PUS_MASK (3 << PADCTL_PUS_SHIFT) +# define PADCTL_PUS(n) ((uint32_t)(n) << PADCTL_PUS_SHIFT) /* n=PULL_* */ +# define PADCTL_PUS_DOWN_100K (0 << PADCTL_PUS_SHIFT) /* 100K Ohm Pull Down */ +# define PADCTL_PUS_UP_47K (1 << PADCTL_PUS_SHIFT) /* 47K Ohm Pull Up */ +# define PADCTL_PUS_UP_100K (2 << PADCTL_PUS_SHIFT) /* 100K Ohm Pull Up */ +# define PADCTL_PUS_UP_22K (3 << PADCTL_PUS_SHIFT) /* 22K Ohm Pull Up */ +#define PADCTL_HYS (1 << 16) /* Bit 16: Hysteresis Enable Field */ + +#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_IOMUXC_H */ diff --git a/arch/arm/src/imxrt/chip/imxrt_lpuart.h b/arch/arm/src/imxrt/chip/imxrt_lpuart.h new file mode 100644 index 00000000000..a578de82ad7 --- /dev/null +++ b/arch/arm/src/imxrt/chip/imxrt_lpuart.h @@ -0,0 +1,416 @@ +/******************************************************************************************** + * arch/arm/src/imxrt/imxrt_lpuart.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ********************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_LPUART_H +#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_LPUART_H + +/******************************************************************************************** + * Included Files + ********************************************************************************************/ + +#include +#include "chip/imxrt_memorymap.h" + +/******************************************************************************************** + * Pre-processor Definitions + ********************************************************************************************/ + +/* Register offsets *************************************************************************/ + +#define IMXRT_LPUART_VERID_OFFSET 0x0000 /* Version ID Register */ +#define IMXRT_LPUART_PARAM_OFFSET 0x0004 /* Parameter Register */ +#define IMXRT_LPUART_GLOBAL_OFFSET 0x0008 /* LPUART Global Register */ +#define IMXRT_LPUART_PINCFG_OFFSET 0x000c /* LPUART Pin Configuration Register */ +#define IMXRT_LPUART_BAUD_OFFSET 0x0010 /* LPUART Baud Rate Register */ +#define IMXRT_LPUART_STAT_OFFSET 0x0014 /* LPUART Status Register */ +#define IMXRT_LPUART_CTRL_OFFSET 0x0018 /* LPUART Control Register */ +#define IMXRT_LPUART_DATA_OFFSET 0x001c /* LPUART Data Register */ +#define IMXRT_LPUART_MATCH_OFFSET 0x0020 /* LPUART Match Address Register */ +#define IMXRT_LPUART_MODIR_OFFSET 0x0024 /* LPUART Modem IrDA Register */ +#define IMXRT_LPUART_FIFO_OFFSET 0x0028 /* LPUART FIFO Register */ +#define IMXRT_LPUART_WATER_OFFSET 0x002c /* LPUART Watermark Register */ + +/* Register addresses ***********************************************************************/ + +#define IMXRT_LPUART1_VERID (IMXRT_LPUART1_BASE + IMXRT_LPUART_VERID_OFFSET) +#define IMXRT_LPUART1_PARAM (IMXRT_LPUART1_BASE + IMXRT_LPUART_PARAM_OFFSET) +#define IMXRT_LPUART1_GLOBAL (IMXRT_LPUART1_BASE + IMXRT_LPUART_GLOBAL_OFFSET) +#define IMXRT_LPUART1_PINCFG (IMXRT_LPUART1_BASE + IMXRT_LPUART_PINCFG_OFFSET) +#define IMXRT_LPUART1_BAUD (IMXRT_LPUART1_BASE + IMXRT_LPUART_BAUD_OFFSET) +#define IMXRT_LPUART1_STAT (IMXRT_LPUART1_BASE + IMXRT_LPUART_STAT_OFFSET) +#define IMXRT_LPUART1_CTRL (IMXRT_LPUART1_BASE + IMXRT_LPUART_CTRL_OFFSET) +#define IMXRT_LPUART1_DATA (IMXRT_LPUART1_BASE + IMXRT_LPUART_DATA_OFFSET) +#define IMXRT_LPUART1_MATCH (IMXRT_LPUART1_BASE + IMXRT_LPUART_MATCH_OFFSET) +#define IMXRT_LPUART1_MODIR (IMXRT_LPUART1_BASE + IMXRT_LPUART_MODIR_OFFSET) +#define IMXRT_LPUART1_FIFO (IMXRT_LPUART1_BASE + IMXRT_LPUART_FIFO_OFFSET) +#define IMXRT_LPUART1_WATER (IMXRT_LPUART1_BASE + IMXRT_LPUART_WATER_OFFSET) + +#define IMXRT_LPUART2_VERID (IMXRT_LPUART2_BASE + IMXRT_LPUART_VERID_OFFSET) +#define IMXRT_LPUART2_PARAM (IMXRT_LPUART2_BASE + IMXRT_LPUART_PARAM_OFFSET) +#define IMXRT_LPUART2_GLOBAL (IMXRT_LPUART2_BASE + IMXRT_LPUART_GLOBAL_OFFSET) +#define IMXRT_LPUART2_PINCFG (IMXRT_LPUART2_BASE + IMXRT_LPUART_PINCFG_OFFSET) +#define IMXRT_LPUART2_BAUD (IMXRT_LPUART2_BASE + IMXRT_LPUART_BAUD_OFFSET) +#define IMXRT_LPUART2_STAT (IMXRT_LPUART2_BASE + IMXRT_LPUART_STAT_OFFSET) +#define IMXRT_LPUART2_CTRL (IMXRT_LPUART2_BASE + IMXRT_LPUART_CTRL_OFFSET) +#define IMXRT_LPUART2_DATA (IMXRT_LPUART2_BASE + IMXRT_LPUART_DATA_OFFSET) +#define IMXRT_LPUART2_MATCH (IMXRT_LPUART2_BASE + IMXRT_LPUART_MATCH_OFFSET) +#define IMXRT_LPUART2_MODIR (IMXRT_LPUART2_BASE + IMXRT_LPUART_MODIR_OFFSET) +#define IMXRT_LPUART2_FIFO (IMXRT_LPUART2_BASE + IMXRT_LPUART_FIFO_OFFSET) +#define IMXRT_LPUART2_WATER (IMXRT_LPUART2_BASE + IMXRT_LPUART_WATER_OFFSET) + +#define IMXRT_LPUART3_VERID (IMXRT_LPUART3_BASE + IMXRT_LPUART_VERID_OFFSET) +#define IMXRT_LPUART3_PARAM (IMXRT_LPUART3_BASE + IMXRT_LPUART_PARAM_OFFSET) +#define IMXRT_LPUART3_GLOBAL (IMXRT_LPUART3_BASE + IMXRT_LPUART_GLOBAL_OFFSET) +#define IMXRT_LPUART3_PINCFG (IMXRT_LPUART3_BASE + IMXRT_LPUART_PINCFG_OFFSET) +#define IMXRT_LPUART3_BAUD (IMXRT_LPUART3_BASE + IMXRT_LPUART_BAUD_OFFSET) +#define IMXRT_LPUART3_STAT (IMXRT_LPUART3_BASE + IMXRT_LPUART_STAT_OFFSET) +#define IMXRT_LPUART3_CTRL (IMXRT_LPUART3_BASE + IMXRT_LPUART_CTRL_OFFSET) +#define IMXRT_LPUART3_DATA (IMXRT_LPUART3_BASE + IMXRT_LPUART_DATA_OFFSET) +#define IMXRT_LPUART3_MATCH (IMXRT_LPUART3_BASE + IMXRT_LPUART_MATCH_OFFSET) +#define IMXRT_LPUART3_MODIR (IMXRT_LPUART3_BASE + IMXRT_LPUART_MODIR_OFFSET) +#define IMXRT_LPUART3_FIFO (IMXRT_LPUART3_BASE + IMXRT_LPUART_FIFO_OFFSET) +#define IMXRT_LPUART3_WATER (IMXRT_LPUART3_BASE + IMXRT_LPUART_WATER_OFFSET) + +#define IMXRT_LPUART4_VERID (IMXRT_LPUART4_BASE + IMXRT_LPUART_VERID_OFFSET) +#define IMXRT_LPUART4_PARAM (IMXRT_LPUART4_BASE + IMXRT_LPUART_PARAM_OFFSET) +#define IMXRT_LPUART4_GLOBAL (IMXRT_LPUART4_BASE + IMXRT_LPUART_GLOBAL_OFFSET) +#define IMXRT_LPUART4_PINCFG (IMXRT_LPUART4_BASE + IMXRT_LPUART_PINCFG_OFFSET) +#define IMXRT_LPUART4_BAUD (IMXRT_LPUART4_BASE + IMXRT_LPUART_BAUD_OFFSET) +#define IMXRT_LPUART4_STAT (IMXRT_LPUART4_BASE + IMXRT_LPUART_STAT_OFFSET) +#define IMXRT_LPUART4_CTRL (IMXRT_LPUART4_BASE + IMXRT_LPUART_CTRL_OFFSET) +#define IMXRT_LPUART4_DATA (IMXRT_LPUART4_BASE + IMXRT_LPUART_DATA_OFFSET) +#define IMXRT_LPUART4_MATCH (IMXRT_LPUART4_BASE + IMXRT_LPUART_MATCH_OFFSET) +#define IMXRT_LPUART4_MODIR (IMXRT_LPUART4_BASE + IMXRT_LPUART_MODIR_OFFSET) +#define IMXRT_LPUART4_FIFO (IMXRT_LPUART4_BASE + IMXRT_LPUART_FIFO_OFFSET) +#define IMXRT_LPUART4_WATER (IMXRT_LPUART4_BASE + IMXRT_LPUART_WATER_OFFSET) + +#define IMXRT_LPUART5_VERID (IMXRT_LPUART5_BASE + IMXRT_LPUART_VERID_OFFSET) +#define IMXRT_LPUART5_PARAM (IMXRT_LPUART5_BASE + IMXRT_LPUART_PARAM_OFFSET) +#define IMXRT_LPUART5_GLOBAL (IMXRT_LPUART5_BASE + IMXRT_LPUART_GLOBAL_OFFSET) +#define IMXRT_LPUART5_PINCFG (IMXRT_LPUART5_BASE + IMXRT_LPUART_PINCFG_OFFSET) +#define IMXRT_LPUART5_BAUD (IMXRT_LPUART5_BASE + IMXRT_LPUART_BAUD_OFFSET) +#define IMXRT_LPUART5_STAT (IMXRT_LPUART5_BASE + IMXRT_LPUART_STAT_OFFSET) +#define IMXRT_LPUART5_CTRL (IMXRT_LPUART5_BASE + IMXRT_LPUART_CTRL_OFFSET) +#define IMXRT_LPUART5_DATA (IMXRT_LPUART5_BASE + IMXRT_LPUART_DATA_OFFSET) +#define IMXRT_LPUART5_MATCH (IMXRT_LPUART5_BASE + IMXRT_LPUART_MATCH_OFFSET) +#define IMXRT_LPUART5_MODIR (IMXRT_LPUART5_BASE + IMXRT_LPUART_MODIR_OFFSET) +#define IMXRT_LPUART5_FIFO (IMXRT_LPUART5_BASE + IMXRT_LPUART_FIFO_OFFSET) +#define IMXRT_LPUART5_WATER (IMXRT_LPUART5_BASE + IMXRT_LPUART_WATER_OFFSET) + +#define IMXRT_LPUART6_VERID (IMXRT_LPUART6_BASE + IMXRT_LPUART_VERID_OFFSET) +#define IMXRT_LPUART6_PARAM (IMXRT_LPUART6_BASE + IMXRT_LPUART_PARAM_OFFSET) +#define IMXRT_LPUART6_GLOBAL (IMXRT_LPUART6_BASE + IMXRT_LPUART_GLOBAL_OFFSET) +#define IMXRT_LPUART6_PINCFG (IMXRT_LPUART6_BASE + IMXRT_LPUART_PINCFG_OFFSET) +#define IMXRT_LPUART6_BAUD (IMXRT_LPUART6_BASE + IMXRT_LPUART_BAUD_OFFSET) +#define IMXRT_LPUART6_STAT (IMXRT_LPUART6_BASE + IMXRT_LPUART_STAT_OFFSET) +#define IMXRT_LPUART6_CTRL (IMXRT_LPUART6_BASE + IMXRT_LPUART_CTRL_OFFSET) +#define IMXRT_LPUART6_DATA (IMXRT_LPUART6_BASE + IMXRT_LPUART_DATA_OFFSET) +#define IMXRT_LPUART6_MATCH (IMXRT_LPUART6_BASE + IMXRT_LPUART_MATCH_OFFSET) +#define IMXRT_LPUART6_MODIR (IMXRT_LPUART6_BASE + IMXRT_LPUART_MODIR_OFFSET) +#define IMXRT_LPUART6_FIFO (IMXRT_LPUART6_BASE + IMXRT_LPUART_FIFO_OFFSET) +#define IMXRT_LPUART6_WATER (IMXRT_LPUART6_BASE + IMXRT_LPUART_WATER_OFFSET) + +#define IMXRT_LPUART7_VERID (IMXRT_LPUART7_BASE + IMXRT_LPUART_VERID_OFFSET) +#define IMXRT_LPUART7_PARAM (IMXRT_LPUART7_BASE + IMXRT_LPUART_PARAM_OFFSET) +#define IMXRT_LPUART7_GLOBAL (IMXRT_LPUART7_BASE + IMXRT_LPUART_GLOBAL_OFFSET) +#define IMXRT_LPUART7_PINCFG (IMXRT_LPUART7_BASE + IMXRT_LPUART_PINCFG_OFFSET) +#define IMXRT_LPUART7_BAUD (IMXRT_LPUART7_BASE + IMXRT_LPUART_BAUD_OFFSET) +#define IMXRT_LPUART7_STAT (IMXRT_LPUART7_BASE + IMXRT_LPUART_STAT_OFFSET) +#define IMXRT_LPUART7_CTRL (IMXRT_LPUART7_BASE + IMXRT_LPUART_CTRL_OFFSET) +#define IMXRT_LPUART7_DATA (IMXRT_LPUART7_BASE + IMXRT_LPUART_DATA_OFFSET) +#define IMXRT_LPUART7_MATCH (IMXRT_LPUART7_BASE + IMXRT_LPUART_MATCH_OFFSET) +#define IMXRT_LPUART7_MODIR (IMXRT_LPUART7_BASE + IMXRT_LPUART_MODIR_OFFSET) +#define IMXRT_LPUART7_FIFO (IMXRT_LPUART7_BASE + IMXRT_LPUART_FIFO_OFFSET) +#define IMXRT_LPUART7_WATER (IMXRT_LPUART7_BASE + IMXRT_LPUART_WATER_OFFSET) + +#define IMXRT_LPUART8_VERID (IMXRT_LPUART8_BASE + IMXRT_LPUART_VERID_OFFSET) +#define IMXRT_LPUART8_PARAM (IMXRT_LPUART8_BASE + IMXRT_LPUART_PARAM_OFFSET) +#define IMXRT_LPUART8_GLOBAL (IMXRT_LPUART8_BASE + IMXRT_LPUART_GLOBAL_OFFSET) +#define IMXRT_LPUART8_PINCFG (IMXRT_LPUART8_BASE + IMXRT_LPUART_PINCFG_OFFSET) +#define IMXRT_LPUART8_BAUD (IMXRT_LPUART8_BASE + IMXRT_LPUART_BAUD_OFFSET) +#define IMXRT_LPUART8_STAT (IMXRT_LPUART8_BASE + IMXRT_LPUART_STAT_OFFSET) +#define IMXRT_LPUART8_CTRL (IMXRT_LPUART8_BASE + IMXRT_LPUART_CTRL_OFFSET) +#define IMXRT_LPUART8_DATA (IMXRT_LPUART8_BASE + IMXRT_LPUART_DATA_OFFSET) +#define IMXRT_LPUART8_MATCH (IMXRT_LPUART8_BASE + IMXRT_LPUART_MATCH_OFFSET) +#define IMXRT_LPUART8_MODIR (IMXRT_LPUART8_BASE + IMXRT_LPUART_MODIR_OFFSET) +#define IMXRT_LPUART8_FIFO (IMXRT_LPUART8_BASE + IMXRT_LPUART_FIFO_OFFSET) +#define IMXRT_LPUART8_WATER (IMXRT_LPUART8_BASE + IMXRT_LPUART_WATER_OFFSET) + +/* Register bit definitions *****************************************************************/ + +/* Version ID Register */ + +#define LPUART_VERID_FEATURE_SHIFT (0) /* Bits 0-15: Feature Identification Number */ +#define LPUART_VERID_FEATURE_MASK (0xffff << LPUART_VERID_FEATURE_SHIFT) +# define LPUART_VERID_FEATURE_STD (1 << LPUART_VERID_FEATURE_SHIFT) /* Standard feature set */ +# define LPUART_VERID_FEATURE_MODEM (3 << LPUART_VERID_FEATURE_SHIFT) /* MODEM/IrDA support */ +#define LPUART_VERID_MINOR_SHIFT (16) /* Bits 16-23: Minor Version Number */ +#define LPUART_VERID_MINOR_MASK (0xff << LPUART_VERID_MINOR_SHIFT) +#define LPUART_VERID_MAJOR_SHIFT (24) /* Bits 24-31: Major Version Number */ +#define LPUART_VERID_MAJOR_MASK (0xff << LPUART_VERID_MAJOR_SHIFT) + +/* Parameter Register */ + +#define LPUART_PARAM_TXFIFO_SHIFT (0) /* Bits 0-7: Transmit FIFO Size */ +#define LPUART_PARAM_TXFIFO_MASK (0xff << LPUART_PARAM_TXFIFO_SHIFT) +#define LPUART_PARAM_RXFIFO_SHIFT (8) /* Bits 8-15: Transmit FIFO Size */ +#define LPUART_PARAM_RXFIFO_MASK (0xff << LPUART_PARAM_RXFIFO_SHIFT) + /* Bits 16-31: Reserved */ + +/* LPUART Global Register */ + + /* Bit 0: Reserved */ +#define LPUART_GLOBAL_RST (1 << 1) /* Bit 1: Software Reset */ + /* Bits 2-31: Reserved */ + +/* LPUART Pin Configuration Register */ + +#define LPUART_PINCFG_TRGSEL_SHIFT (0) /* Bits 0-1: Trigger Select */ +#define LPUART_PINCFG_TRGSEL_MASK (3 << LPUART_PINCFG_TRGSEL_SHIFT) +# define LPUART_PINCFG_TRGSEL_DISABLE (0 << LPUART_PINCFG_TRGSEL_SHIFT) /* Trigger disabled */ +# define LPUART_PINCFG_TRGSEL_RXD (1 << LPUART_PINCFG_TRGSEL_SHIFT) /* Trigger used instead of RXD pin */ +# define LPUART_PINCFG_TRGSEL_CTSB (2 << LPUART_PINCFG_TRGSEL_SHIFT) /* Trigger used instead of CTS_B pin */ +# define LPUART_PINCFG_TRGSEL_TXDMOD (3 << LPUART_PINCFG_TRGSEL_SHIFT) /* Trigger used to modulate the TXD output */ + /* Bits 2-31: Reserved */ + +/* LPUART Baud Rate Register */ + +#define LPUART_BAUD_SBR_SHIFT (0) /* Bits 0-12: Baud Rate Modulo Divisor. */ +#define LPUART_BAUD_SBR_MASK (0x1fff << LPUART_BAUD_SBR_SHIFT) +# define LPUART_BAUD_SBR(n) ((uint32_t)(n) << LPUART_BAUD_SBR_SHIFT) +#define LPUART_BAUD_SBNS (1 << 13) /* Bit 13: Stop Bit Number Select */ +#define LPUART_BAUD_RXEDGIE (1 << 14) /* Bit 14: RX Input Active Edge Interrupt Enable */ +#define LPUART_BAUD_LBKDIE (1 << 15) /* Bit 15: LIN Break Detect Interrupt Enable */ +#define LPUART_BAUD_RESYNCDIS (1 << 16) /* Bit 16: Resynchronization Disable */ +#define LPUART_BAUD_BOTHEDGE (1 << 17) /* Bit 17: Both Edge Sampling */ +#define LPUART_BAUD_MATCFG_SHIFT (18) /* Bits 18-19: Match Configuration */ +#define LPUART_BAUD_MATCFG_MASK (3 << LPUART_BAUD_MATCFG_SHIFT) +# define LPUART_BAUD_MATCFG_ADDR (0 << LPUART_BAUD_MATCFG_SHIFT) /* Address Match Wakeup */ +# define LPUART_BAUD_MATCFG_IDLE (1 << LPUART_BAUD_MATCFG_SHIFT) /* Idle Match Wakeup */ +# define LPUART_BAUD_MATCFG_ONOFF (2 << LPUART_BAUD_MATCFG_SHIFT) /* Match On and Match Off */ +# define LPUART_BAUD_MATCFG_RWUENAB (3 << LPUART_BAUD_MATCFG_SHIFT) /* Enables RWU on Data Match and Match + * On/Off for transmitter CTS input */ + /* Bit 20: Reserved */ +#define LPUART_BAUD_RDMAE (1 << 21) /* Bit 21: Receiver Full DMA Enable */ + /* Bit 22: Reserved */ +#define LPUART_BAUD_TDMAE (1 << 23) /* Bit 23: Transmitter DMA Enable */ +#define LPUART_BAUD_OSR_SHIFT (28) /* Bits 24-28: Oversampling Ratio */ +#define LPUART_BAUD_OSR_MASK (31 << LPUART_BAUD_OSR_SHIFT) + #define LPUART_BAUD_OSR(n) ((uint32_t)((n) - 1) << LPUART_BAUD_OSR_SHIFT) +#define LPUART_BAUD_M10 (1 << 29) /* Bit 20: 10-bit Mode select */ +#define LPUART_BAUD_MAEN2 (1 << 30) /* Bit 30: Match Address Mode Enable 2 */ +#define LPUART_BAUD_MAEN1 (1 << 31) /* Bit 31: Match Address Mode Enable 1 */ + +/* LPUART Status Register */ + + /* Bits 0-13: Reserved */ +#define LPUART_STAT_MA2F (1 << 14) /* Bit 14: Match 2 Flag */ +#define LPUART_STAT_MA1F (1 << 15) /* Bit 15: Match 1 Flag */ +#define LPUART_STAT_PF (1 << 16) /* Bit 16: Parity Error Flag */ +#define LPUART_STAT_FE (1 << 17) /* Bit 17: Framing Error Flag */ +#define LPUART_STAT_NF (1 << 18) /* Bit 18: Noise Flag */ +#define LPUART_STAT_OR (1 << 19) /* Bit 19: Receiver Overrun Flag */ +#define LPUART_STAT_IDLE (1 << 20) /* Bit 20: Idle Line Flag */ +#define LPUART_STAT_RDRF (1 << 21) /* Bit 21: Receive Data Register Full Flag */ +#define LPUART_STAT_TC (1 << 22) /* Bit 22: Transmission Complete Flag */ +#define LPUART_STAT_TDRE (1 << 23) /* Bit 23: Transmit Data Register Empty Flag */ +#define LPUART_STAT_RAF (1 << 24) /* Bit 24: Receiver Active Flag */ +#define LPUART_STAT_LBKDE (1 << 25) /* Bit 25: LIN Break Detection Enable */ +#define LPUART_STAT_BRK13 (1 << 26) /* Bit 26: Break Character Generation Length */ +#define LPUART_STAT_RWUID (1 << 27) /* Bit 27: Receive Wake Up Idle Detect */ +#define LPUART_STAT_RXINV (1 << 28) /* Bit 28: Receive Data Inversion */ +#define LPUART_STAT_MSBF (1 << 29) /* Bit 29: MSB First */ +#define LPUART_STAT_RXEDGIF (1 << 30) /* Bit 30: RXD Pin Active Edge Interrupt Flag */ +#define LPUART_STAT_LBKDIF (1 << 31) /* Bit 31: LIN Break Detect Interrupt Flag */ + +/* LPUART Control Register */ + +#define LPUART_CTRL_PT (1 << 0) /* Bit 0: Parity Type */ +# define LPUART_CTRL_PT_EVEN (0 << 0) /* Even parity */ +# define LPUART_CTRL_PT_ODD (1 << 0) /* Odd parity */ +#define LPUART_CTRL_PE (1 << 1) /* Bit 1: Parity Enable */ +#define LPUART_CTRL_ILT (1 << 2) /* Bit 2: Idle Line Type Select */ +#define LPUART_CTRL_WAKE (1 << 3) /* Bit 3: Receiver Wakeup Method Select */ +#define LPUART_CTRL_M (1 << 4) /* Bit 4: 9-Bit or 8-Bit Mode Select */ +#define LPUART_CTRL_RSRC (1 << 5) /* Bit 5: Receiver Source Select */ +#define LPUART_CTRL_DOZEEN (1 << 6) /* Bit 6: Doze Enable */ +#define LPUART_CTRL_LOOPS (1 << 7) /* Bit 7: Loop Mode Select */ +#define LPUART_CTRL_IDLECFG_SHIFT (8) /* Bits 8-10: Idle Configuration */ +#define LPUART_CTRL_IDLECFG_MASK (7 << LPUART_CTRL_IDLECFG_SHIFT) +# define LPUART_CTRL_IDLECFG_1 (0 << LPUART_CTRL_IDLECFG_SHIFT) /* 1 idle character */ +# define LPUART_CTRL_IDLECFG_2 (1 << LPUART_CTRL_IDLECFG_SHIFT) /* 2 idle characters */ +# define LPUART_CTRL_IDLECFG_4 (2 << LPUART_CTRL_IDLECFG_SHIFT) /* 4 idle characters */ +# define LPUART_CTRL_IDLECFG_8 (3 << LPUART_CTRL_IDLECFG_SHIFT) /* 8 idle characters */ +# define LPUART_CTRL_IDLECFG_16 (4 << LPUART_CTRL_IDLECFG_SHIFT) /* 6 idle characters */ +# define LPUART_CTRL_IDLECFG_32 (5 << LPUART_CTRL_IDLECFG_SHIFT) /* 32 idle characters */ +# define LPUART_CTRL_IDLECFG_64 (6 << LPUART_CTRL_IDLECFG_SHIFT) /* 64 idle characters */ +# define LPUART_CTRL_IDLECFG_128 (7 << LPUART_CTRL_IDLECFG_SHIFT) /* 128 idle characters */ +#define LPUART_CTRL_M7 (1 << 11) /* Bit 11: 7-Bit Mode Select */ + /* Bits 12-13: Reserved */ +#define LPUART_CTRL_MA2IE (1 << 14) /* Bit 14: Match 2 Interrupt Enable */ +#define LPUART_CTRL_MA1IE (1 << 15) /* Bit 15: Match 1 Interrupt Enable */ +#define LPUART_CTRL_SBK (1 << 16) /* Bit 16: Send Break */ +#define LPUART_CTRL_RWU (1 << 17) /* Bit 17: Receiver Wakeup Control */ +#define LPUART_CTRL_RE (1 << 18) /* Bit 18: Receiver Enable */ +#define LPUART_CTRL_TE (1 << 19) /* Bit 19: Transmitter Enable */ +#define LPUART_CTRL_ILIE (1 << 20) /* Bit 20: Idle Line Interrupt Enable */ +#define LPUART_CTRL_RIE (1 << 21) /* Bit 21: Receiver Interrupt Enable */ +#define LPUART_CTRL_TCIE (1 << 22) /* Bit 22: Transmission Complete Interrupt Enable */ +#define LPUART_CTRL_TIE (1 << 23) /* Bit 23: Transmit Interrupt Enable */ +#define LPUART_CTRL_PEIE (1 << 24) /* Bit 24: Parity Error Interrupt Enable */ +#define LPUART_CTRL_FEIE (1 << 25) /* Bit 25: Framing Error Interrupt Enable */ +#define LPUART_CTRL_NEIE (1 << 26) /* Bit 26: Noise Error Interrupt Enable */ +#define LPUART_CTRL_ORIE (1 << 27) /* Bit 27: Overrun Interrupt Enable */ +#define LPUART_CTRL_TXINV (1 << 28) /* Bit 28: Transmit Data Inversion */ +#define LPUART_CTRL_TXDIR (1 << 29) /* Bit 29: TXD Pin Direction in Single-Wire Mode */ +#define LPUART_CTRL_R9T8 (1 << 30) /* Bit 30: Receive Bit 9 / Transmit Bit 8 */ +#define LPUART_CTRL_R8T9 (1 << 31) /* Bit 31: Receive Bit 8 / Transmit Bit 9 */ + +#define LPUART_ALL_INTS (LPUART_CTRL_ORIE | LPUART_CTRL_NEIE | LPUART_CTRL_FEIE | \ + LPUART_CTRL_PEIE | LPUART_CTRL_TIE | LPUART_CTRL_TCIE | \ + LPUART_CTRL_RIE | LPUART_CTRL_ILIE | LPUART_CTRL_MA1IE | \ + LPUART_CTRL_MA2IE) + +/* LPUART Data Register */ + +#define LPUART_DATA_SHIFT (0) /* Bits 0-9: Data bits 0-9 */ +#define LPUART_DATA_MASK (0x3ff << LPUART_DATA_SHIFT) + /* Bit 10: Reserved */ +#define LPUART_DATA_STATUS_SHIFT (11) /* Bit 11: Idle Line status */ +#define LPUART_DATA_IDLINE (1 << 11) /* Bit 11: Idle Line */ +#define LPUART_DATA_RXEMPT (1 << 12) /* Bit 12: Receive Buffer Empty */ +#define LPUART_DATA_FRETSC (1 << 13) /* Bit 13: Frame Error / Transmit Special Character */ +#define LPUART_DATA_PARITYE (1 << 14) /* Bit 14: Parity Error */ +#define LPUART_DATA_NOISY (1 << 15) /* Bit 15: Noisy */ + /* Bits 16-31: Reserved */ + +/* LPUART Match Address Register */ + +#define LPUART_MATCH_MA1_SHIFT (0) /* Bits 0-9: Match Address 1 */ +#define LPUART_MATCH_MA1_MASK (0x3ff << LPUART_MATCH_MA1_SHIFT) +# define LPUART_MATCH_MA1(n) ((uint32_t)(n) << LPUART_MATCH_MA1_SHIFT) + /* Bits 10-15: Reserved */ +#define LPUART_MATCH_MA2_SHIFT (16) /* Bits 16-25: Match Address 2 */ +#define LPUART_MATCH_MA2_MASK (0x3ff << LPUART_MATCH_MA2_SHIFT) +# define LPUART_MATCH_MA2(n) ((uint32_t)(n) << LPUART_MATCH_MA2_SHIFT) + /* Bits 26-31: Reserved */ + +/* LPUART Modem IrDA Register */ + +#define LPUART_MODIR_TXCTSE (1 << 0) /* Bit nn: Transmitter clear-to-send enable */ +#define LPUART_MODIR_TXRTSE (1 << 1) /* Bit nn: Transmitter request-to-send enable */ +#define LPUART_MODIR_TXRTSPOL (1 << 2) /* Bit nn: Transmitter request-to-send polarity */ +#define LPUART_MODIR_RXRTSE (1 << 3) /* Bit nn: Receiver request-to-send enable */ +#define LPUART_MODIR_TXCTSC (1 << 4) /* Bit nn: Transmit CTS Configuration */ +# define LPUART_MODIR_TXCTSC_START (0 << 4) /* CTS sampled at start of character */ +# define LPUART_MODIR_TXCTSC_IDLE (1 << 4) /* CTS sampled when transmitter idle */ +#define LPUART_MODIR_TXCTSSRC (1 << 5) /* Bit nn: Transmit CTS Source */ +# define LPUART_MODIR_TXCTSSRC_CTSB (0 << 5) /* Bit nn: CTS input is CTS_B pin */ +# define LPUART_MODIR_TXCTSSRC_RXMAT (1 << 5) /* Bit nn: Transmit CTS Source */ + /* Bits 6-7: Reserved */ +#define LPUART_MODIR_RTSWATER (8) /* Bits 8-9: Receive RTS Configuration */ + /* Bits 10-15: Reserved */ +#define LPUART_MODIR_TNP_SHIFT (16) /* Bits 16-17: Transmitter narrow pulse */ +#define LPUART_MODIR_TNP_MASK (3 << LPUART_MODIR_TNP_SHIFT) +# define LPUART_MODIR_TNP(n) ((uint32_t)((n) - 1) << LPUART_MODIR_TNP_SHIFT) /* n/OSR */ +#define LPUART_MODIR_IREN (1 << 18) /* Bit nn: Infrared enable */ + /* Bits 19-31: Reserved */ + +/* LPUART FIFO Register */ + +#define LPUART_FIFO_RXFIFOSIZE_SHIFT (0) /* Bits 0-2: Receive FIFO. Buffer Depth */ +#define LPUART_FIFO_RXFIFOSIZE_MASK (7 << LPUART_FIFO_RXFIFOSIZE_SHIFT) +# define LPUART_FIFO_RXFIFOSIZE_1 (0 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 1 datawords */ +# define LPUART_FIFO_RXFIFOSIZE_4 (1 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 4 datawords */ +# define LPUART_FIFO_RXFIFOSIZE_8 (2 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 8 datawords */ +# define LPUART_FIFO_RXFIFOSIZE_16 (3 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 16 datawords */ +# define LPUART_FIFO_RXFIFOSIZE_32 (4 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 32 datawords */ +# define LPUART_FIFO_RXFIFOSIZE_64 (5 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 64 datawords */ +# define LPUART_FIFO_RXFIFOSIZE_128 (6 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 128 datawords */ +# define LPUART_FIFO_RXFIFOSIZE_256 (7 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 256 datawords */ +#define LPUART_FIFO_TXFIFOSIZE_SHIFT (4) /* Bits 4-6: Transmit FIFO. Buffer Depth */ +#define LPUART_FIFO_TXFIFOSIZE_MASK (7 << LPUART_FIFO_TXFIFOSIZE_SHIFT) +# define LPUART_FIFO_TXFIFOSIZE_1 (0 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* 1 datawords */ +# define LPUART_FIFO_TXFIFOSIZE_4 (1 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* 4 datawords */ +# define LPUART_FIFO_TXFIFOSIZE_8 (2 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* 8 datawords */ +# define LPUART_FIFO_TXFIFOSIZE_16 (3 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* 16 datawords */ +# define LPUART_FIFO_TXFIFOSIZE_32 (4 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* 32 datawords */ +# define LPUART_FIFO_TXFIFOSIZE_64 (5 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* 64 datawords */ +# define LPUART_FIFO_TXFIFOSIZE_128 (6 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* 128 datawords */ +# define LPUART_FIFO_TXFIFOSIZE_256 (7 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* 256 datawords */ + +#define LPUART_FIFO_TXFE (1 << 7) /* Bit 7: Transmit FIFO Enable */ +#define LPUART_FIFO_RXUFE (1 << 8) /* Bit 8: Receive FIFO Underflow Interrupt Enable */ +#define LPUART_FIFO_TXOFE (1 << 9) /* Bit 9: Transmit FIFO Overflow Interrupt Enable */ +#define LPUART_FIFO_RXIDEN_SHIFT (10) /* Bits 10-12: Receiver Idle Empty Enable */ +#define LPUART_FIFO_RXIDEN_MASK (7 << LPUART_FIFO_RXIDEN_SHIFT) +# define LPUART_FIFO_RXIDEN_DISABLE (0 << LPUART_FIFO_RXIDEN_SHIFT) /* Disable RDRF assertion when receiver is idle */ +# define LPUART_FIFO_RXIDEN_1 (1 << LPUART_FIFO_RXIDEN_SHIFT) /* Enable RDRF assertion when receiver idle for 1 word */ +# define LPUART_FIFO_RXIDEN_2 (2 << LPUART_FIFO_RXIDEN_SHIFT) /* Enable RDRF assertion when receiver idle for 2 words */ +# define LPUART_FIFO_RXIDEN_4 (3 << LPUART_FIFO_RXIDEN_SHIFT) /* Enable RDRF assertion when receiver idle for 4 words */ +# define LPUART_FIFO_RXIDEN_8 (4 << LPUART_FIFO_RXIDEN_SHIFT) /* Enable RDRF assertion when receiver idle for 8 words */ +# define LPUART_FIFO_RXIDEN_16 (5 << LPUART_FIFO_RXIDEN_SHIFT) /* Enable RDRF assertion when receiver idle for 16 words */ +# define LPUART_FIFO_RXIDEN_32 (6 << LPUART_FIFO_RXIDEN_SHIFT) /* Enable RDRF assertion when receiver idle for 32 words */ +# define LPUART_FIFO_RXIDEN_64 (7 << LPUART_FIFO_RXIDEN_SHIFT) /* Enable RDRF assertion when receiver idle for 64 words */ + +#define LPUART_FIFO_RXFLUSH (1 << 14) /* Bit 14: Receive FIFO/Buffer Flush */ +#define LPUART_FIFO_TXFLUSH (1 << 15) /* Bit 15: Transmit FIFO/Buffer Flush */ +#define LPUART_FIFO_RXUF (1 << 16) /* Bit 16: Receiver Buffer Underflow Flag */ +#define LPUART_FIFO_TXOF (1 << 17) /* Bit 17: Transmitter Buffer Overflow Flag */ + /* Bits 18-21: Reserved */ +#define LPUART_FIFO_RXEMPT (1 << 22) /* Bit 22: Receive Buffer/FIFO Empty */ +#define LPUART_FIFO_TXEMPT (1 << 23) /* Bit 23: Transmit Buffer/FIFO Empty */ + /* Bits 24-31: Reserved */ + +/* LPUART Watermark Register */ + +#define LPUART_WATER_TXWATER_SHIFT (0) /* Bits 0-1: Transmit Watermark */ +#define LPUART_WATER_TXWATER_MASK (3 << LPUART_WATER_TXWATER_SHIFT) +# define LPUART_WATER_TXWATER(n) ((uint32_t)(n) << LPUART_WATER_TXWATER_SHIFT) + /* Bits 2-7: Reserved */ +#define LPUART_WATER_TXCOUNT_SHIFT (8) /* Bits 8-10:Transmit Counter */ +#define LPUART_WATER_TXCOUNT_MASK (7 << LPUART_WATER_TXCOUNT_SHIFT) +# define LPUART_WATER_TXCOUNT(n) ((uint32_t)(n) << LPUART_WATER_TXCOUNT_SHIFT) + /* Bits 11-15: Reserved */ +#define LPUART_WATER_RXWATER_SHIFT (16) /* Bits 16-17: Receive Watermark */ +#define LPUART_WATER_RXWATER_MASK (3 << LPUART_WATER_RXWATER_SHIFT) +# define LPUART_WATER_RXWATER(n) ((uint32_t)(n) << LPUART_WATER_RXWATER_SHIFT) + /* Bits 18-23: Reserved */ +#define LPUART_WATER_RXCOUNT_SHIFT (24) /* Bits 24-26: Receive Counter */ +#define LPUART_WATER_RXCOUNT_MASK (7 << LPUART_WATER_RXCOUNT_SHIFT) +# define LPUART_WATER_RXCOUNT(n) ((uint32_t)(n) << LPUART_WATER_RXCOUNT_SHIFT) + /* Bits 27-31: Reserved */ + +#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_LPUART_H */ diff --git a/arch/arm/src/imxrt/chip/imxrt_memorymap.h b/arch/arm/src/imxrt/chip/imxrt_memorymap.h new file mode 100644 index 00000000000..b528d9beb92 --- /dev/null +++ b/arch/arm/src/imxrt/chip/imxrt_memorymap.h @@ -0,0 +1,51 @@ +/************************************************************************************ + * arch/arm/src/imxrt/chip/imxrt_memorymap.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_MEMORYMAP_H +#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_MEMORYMAP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#if defined(CONFIG_ARCH_FAMILY_IMXRT105x) +# include "chip/imxrt105x_memorymap.h" +#else +# error Unrecognized i.MX RT architecture +#endif + +#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_MEMORYMAP_H */ diff --git a/arch/arm/src/imxrt/chip/imxrt_src.h b/arch/arm/src/imxrt/chip/imxrt_src.h new file mode 100644 index 00000000000..60beeedbe96 --- /dev/null +++ b/arch/arm/src/imxrt/chip/imxrt_src.h @@ -0,0 +1,157 @@ +/******************************************************************************************** + * arch/arm/src/imxrt/imxrt_src.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ********************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_SRC_H +#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_SRC_H + +/******************************************************************************************** + * Included Files + ********************************************************************************************/ + +#include +#include "chip/imxrt_memorymap.h" + +/******************************************************************************************** + * Pre-processor Definitions + ********************************************************************************************/ + +/* Register offsets *************************************************************************/ + +#define IMXRT_SRC_SCR_OFFSET 0x0000 /* SRC Control Register */ +#define IMXRT_SRC_SBMR1_OFFSET 0x0004 /* SRC Boot Mode Register 1 */ +#define IMXRT_SRC_SRSR_OFFSET 0x0008 /* SRC Reset Status Register */ +#define IMXRT_SRC_SBMR2_OFFSET 0x001c /* SRC Boot Mode Register 2 */ +#define IMXRT_SRC_GPR1_OFFSET 0x0020 /* SRC General Purpose Register 1 */ +#define IMXRT_SRC_GPR2_OFFSET 0x0024 /* SRC General Purpose Register 2 */ +#define IMXRT_SRC_GPR3_OFFSET 0x0028 /* SRC General Purpose Register 3 */ +#define IMXRT_SRC_GPR4_OFFSET 0x002c /* SRC General Purpose Register 4 */ +#define IMXRT_SRC_GPR5_OFFSET 0x0030 /* SRC General Purpose Register 5 */ +#define IMXRT_SRC_GPR6_OFFSET 0x0034 /* SRC General Purpose Register 6 */ +#define IMXRT_SRC_GPR7_OFFSET 0x0038 /* SRC General Purpose Register 7 */ +#define IMXRT_SRC_GPR8_OFFSET 0x003c /* SRC General Purpose Register 8 */ +#define IMXRT_SRC_GPR9_OFFSET 0x0040 /* SRC General Purpose Register 9 */ +#define IMXRT_SRC_GPR10_OFFSET 0x0044 /* SRC General Purpose Register 10 */ + +/* Register addresses ***********************************************************************/ + +#define IMXRT_SRC_SCR (IMXRT_SRC_BASE + IMXRT_SRC_SCR_OFFSET) +#define IMXRT_SRC_SBMR1 (IMXRT_SRC_BASE + IMXRT_SRC_SBMR1_OFFSET) +#define IMXRT_SRC_SRSR (IMXRT_SRC_BASE + IMXRT_SRC_SRSR_OFFSET) +#define IMXRT_SRC_SBMR2 (IMXRT_SRC_BASE + IMXRT_SRC_SBMR2_OFFSET) +#define IMXRT_SRC_GPR1 (IMXRT_SRC_BASE + IMXRT_SRC_GPR1_OFFSET) +#define IMXRT_SRC_GPR2 (IMXRT_SRC_BASE + IMXRT_SRC_GPR2_OFFSET) +#define IMXRT_SRC_GPR3 (IMXRT_SRC_BASE + IMXRT_SRC_GPR3_OFFSET) +#define IMXRT_SRC_GPR4 (IMXRT_SRC_BASE + IMXRT_SRC_GPR4_OFFSET) +#define IMXRT_SRC_GPR5 (IMXRT_SRC_BASE + IMXRT_SRC_GPR5_OFFSET) +#define IMXRT_SRC_GPR6 (IMXRT_SRC_BASE + IMXRT_SRC_GPR6_OFFSET) +#define IMXRT_SRC_GPR7 (IMXRT_SRC_BASE + IMXRT_SRC_GPR7_OFFSET) +#define IMXRT_SRC_GPR8 (IMXRT_SRC_BASE + IMXRT_SRC_GPR8_OFFSET) +#define IMXRT_SRC_GPR9 (IMXRT_SRC_BASE + IMXRT_SRC_GPR9_OFFSET) +#define IMXRT_SRC_GPR10 (IMXRT_SRC_BASE + IMXRT_SRC_GPR10_OFFSET) + +/* Register bit definitions *****************************************************************/ + +/* SRC Control Register */ + + /* Bits 0-3: Reserved */ +#define SRC_SCR_LOCKUP_RST (1 << 4) /* Bit 4: Lockup reset enable bit */ + /* Bits 5-6: Reserved */ +#define SRC_SCR_MASK_WDOG_RST_SHIFT (7) /* Bits 7-10: Mask wdog_rst_b source */ +#define SRC_SCR_MASK_WDOG_RST_MASK (15 << SRC_SCR_MASK_WDOG_RST_SHIFT) +# define SRC_SCR_MASK_WDOG_RST_MASKED (5 << SRC_SCR_MASK_WDOG_RST_SHIFT) +# define SRC_SCR_MASK_WDOG_RST_UNMASKED (10 << SRC_SCR_MASK_WDOG_RST_SHIFT) + /* Bits 11-12: Reserved */ +#define SRC_SCR_CORE0_RST (1 << 13) /* Bit 13: Software reset for core0 only. */ + /* Bits 14-16: Reserved */ +#define SRC_SCR_CORE0_DBG_RST (1 << 17) /* Bit 17: Software reset for core0 debug only */ + /* Bits 18-24: Reserved */ +#define SRC_SCR_DBG_RST_MSK_PG (1 << 25) /* Bit 25: Do not assert debug resets + * after power gating event of core */ + /* Bits 26-27: Reserved */ +#define SRC_SCR_MASK_WDOG3_RST_SHIFT (28) /* Bits 38-31: Mask wdog3_rst_b source */ +#define SRC_SCR_MASK_WDOG3_RST_MASK (15 << SRC_SCR_MASK_WDOG3_RST_SHIFT) +# define SRC_SCR_MASK_WDOG3_RST_MASKED (5 << SRC_SCR_MASK_WDOG3_RST_SHIFT) +# define SRC_SCR_MASK_WDOG3_RST_UNMASKED (10 << SRC_SCR_MASK_WDOG3_RST_SHIFT) + +/* SRC Boot Mode Register 1 */ + +#define SRC_SBMR1_BOOT_CFG_SHIFT (24) /* Bits 24-31: Refer to fusemap */ +#define SRC_SBMR1_BOOT_CFG_MASK (0xff << SRC_SBMR1_BOOT_CFG_SHIFT) +#define SRC_SBMR1_BOOT_CFG2_SHIFT (16) /* Bits 16-23: Refer to fusemap */ +#define SRC_SBMR1_BOOT_CFG2_MASK (0xff << SRC_SBMR1_BOOT_CFG2_SHIFT) +#define SRC_SBMR1_BOOT_CFG3_SHIFT (8) /* Bits 8-15: Refer to fusemap */ +#define SRC_SBMR1_BOOT_CFG3_MASK (0xff << SRC_SBMR1_BOOT_CFG3_SHIFT) +#define SRC_SBMR1_BOOT_CFG4_SHIFT (0) /* Bits 0-7: Refer to fusemap */ +#define SRC_SBMR1_BOOT_CFG4_MASK (0xff << SRC_SBMR1_BOOT_CFG4_SHIFT) + +/* SRC Reset Status Register */ + +#define SRC_SRSR_IPP_RESET_B (1 << 0) /* Bit 0: Indicates whether reset was the + * result of ipp_reset_b pin (Power-up + * sequence) */ +#define SRC_SRSR_LOCKUP_SYSRESETREQ (1 << 1) /* Bit 1: Indicates a reset has been + * caused by CPU lockup or software setting + * of SYSRESETREQ bit */ +#define SRC_SRSR_CSU_RESET_B (1 << 2) /* Bit 2: Indicates whether the reset was + * the result of the csu_reset_b input */ +#define SRC_SRSR_IPP_USER_RESET_B (1 << 3) /* Bit 3: Indicates whether the reset was + * the result of the ipp_user_reset_b qualified + * reset */ +#define SRC_SRSR_WDOG_RST_B (1 << 4) /* Bit 4: IC Watchdog Time-out reset */ +#define SRC_SRSR_JTAG_RST_B (1 << 5) /* Bit 5: HIGH - Z JTAG reset */ +#define SRC_SRSR_JTAG_SW_RST (1 << 6) /* Bit 6: JTAG software reset */ +#define SRC_SRSR_WDOG3_RST_B (1 << 7) /* Bit 7: IC Watchdog3 Time-out reset */ +#define SRC_SRSR_TEMPSENSE_RST_B (1 << 8) /* Bit 8: Temper Sensor software reset */ + /* Bits 9-31: Reserved */ + +/* SRC Boot Mode Register 2 */ + +#define SRC_SBMR2_SEC_CONFIG_SHIFT (0) /* Bits 0-1: State of the corresponding + * SECONFIG fuse */ + /* Bit 2: Reserved */ +#define SRC_SBMR2_DIR_BT_DIS (1 << 3) /* Bit 3: State of the DIR_BT_DIS fuse */ +#define SRC_SBMR2_BT_FUSE_SEL (1 << 4) /* Bit 4: State of the BT_FUSE_SEL fuse */ + /* Bits 5-23: Reserved */ +#define SRC_SBMR2_BMOD_SHIFT (24) /* Bits 24-25: Latched state of the BOOT_MODE + * and BOOT_MODE0 signals on POR. + /* Bits 26-31: Reserved */ + +/* SRC General Purpose Register 1 (32-bit values, some have reserved bits) + * NOTE: Ald GPR registers are used by the ROM code and should not be used by application + * software. + */ + +#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_SRC_H */ + diff --git a/arch/arm/src/imxrt/chip/imxrt_wdog.h b/arch/arm/src/imxrt/chip/imxrt_wdog.h new file mode 100644 index 00000000000..1f1bfba62f7 --- /dev/null +++ b/arch/arm/src/imxrt/chip/imxrt_wdog.h @@ -0,0 +1,142 @@ +/************************************************************************************ + * arch/arm/src/imxrt/imxrt_wdog.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Janne Rosberg + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_WDOG_H +#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_WDOG_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include "chip/imxrt_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ + +#define IMXRT_WDOG_WCR_OFFSET 0x0000 /* Watchdog control register */ +#define IMXRT_WDOG_WSR_OFFSET 0x0002 /* Watchdog service register */ +#define IMXRT_WDOG_WRSR_OFFSET 0x0004 /* Watchdog reset status */ +#define IMXRT_WDOG_WICR_OFFSET 0x0006 /* Watchdog interrupt control */ +#define IMXRT_WDOG_WMCR_OFFSET 0x0008 /* Watchdog misc control */ + +#define IMXRT_RTWDOG_CS_OFFSET 0x0000 /* Watchdog control and status register */ +#define IMXRT_RTWDOG_CNT_OFFSET 0x0004 /* Watchdog counter register */ +#define IMXRT_RTWDOG_TOVAL_OFFSET 0x0008 /* Watchdog timeout value register */ +#define IMXRT_RTWDOG_WIN_OFFSET 0x000c /* Watchdog window register */ + +/* Register addresses ***************************************************************/ + +#define IMXRT_WDOG1_WCR (IMXRT_WDOG1_BASE + IMXRT_WDOG_WCR_OFFSET) +#define IMXRT_WDOG1_WSR (IMXRT_WDOG1_BASE + IMXRT_WDOG_WSR_OFFSET) +#define IMXRT_WDOG1_WRSR (IMXRT_WDOG1_BASE + IMXRT_WDOG_WRSR_OFFSET) +#define IMXRT_WDOG1_WICR (IMXRT_WDOG1_BASE + IMXRT_WDOG_WICR_OFFSET) +#define IMXRT_WDOG1_WMCR (IMXRT_WDOG1_BASE + IMXRT_WDOG_WMCR_OFFSET) + +#define IMXRT_WDOG2_WCR (IMXRT_WDOG2_BASE + IMXRT_WDOG_WCR_OFFSET) +#define IMXRT_WDOG2_WSR (IMXRT_WDOG2_BASE + IMXRT_WDOG_WSR_OFFSET) +#define IMXRT_WDOG2_WRSR (IMXRT_WDOG2_BASE + IMXRT_WDOG_WRSR_OFFSET) +#define IMXRT_WDOG2_WMCR (IMXRT_WDOG2_BASE + IMXRT_WDOG_WMCR_OFFSET) + +#define IMXRT_RTWDOG_CS (IMXRT_WDOG3_BASE + IMXRT_RTWDOG_CS_OFFSET) +#define IMXRT_RTWDOG_CNT (IMXRT_WDOG3_BASE + IMXRT_RTWDOG_CNT_OFFSET) +#define IMXRT_RTWDOG_TOVAL (IMXRT_WDOG3_BASE + IMXRT_RTWDOG_TOVAL_OFFSET) +#define IMXRT_RTWDOG_WIN (IMXRT_WDOG3_BASE + IMXRT_RTWDOG_WIN_OFFSET) + +/* Register bit definitions *********************************************************/ + +/* Watchdog control and status register */ + +#define WDOG_WCR_WDZST (1 << 0) /* Bit 0: Watchdog Low Power */ +#define WDOG_WCR_WDBG (1 << 1) /* Bit 1: Watchdog DEBUG Enable */ +#define WDOG_WCR_WDE (1 << 2) /* Bit 2: Watchdog Enable */ +#define WDOG_WCR_WDT (1 << 3) /* Bit 3: WDOG_B Time-out assertion */ +#define WDOG_WCR_SRS (1 << 4) /* Bit 4: Software Reset Signal */ +#define WDOG_WCR_WDA (1 << 5) /* Bit 5: WDOG_B assertion */ +#define WDOG_WCR_SRE (1 << 6) /* Bit 6: Software reset extension */ +#define WDOG_WCR_WDW (1 << 7) /* Bit 7: Watchdog Disable for Wait */ + +#define WDOG_WCR_WT_SHIFT (8) /* Bits 8-15: Watchdog time-out value */ +#define WDOG_WCR_WT_MASK (0xff << WDOG_WCR_WT_SHIFT) +# define WDOG_WCR_WT(n) ((uint16_t)((n)) << WDOG_WCR_WT_SHIFT) + +/* Watchdog reset status */ + +#define WDOG_WRSR_SFTW (1 << 0) /* Bit 0: Software Reset */ +#define WDOG_WRSR_TOUT (1 << 1) /* Bit 1: Timeout */ + /* Bits 2-3: reserved */ +#define WDOG_WRSR_POR (1 << 4) /* Bit 4: Power on reset */ + /* Bits 5-15: Reserved */ +/* Watchdog interrupt control */ + +#define WDOG_WICR_WICT_SHIFT (0) /* Bits 0-7: Watchdog Interrupt Count Time-out */ +#define WDOG_WICR_WICT_MASK (0xff << WDOG_WCR_WT_SHIFT) +# define WDOG_WICR_WICT(n) ((uint16_t)((n)) << WDOG_WICR_WICT_SHIFT) + /* Bits 8-13: Reserved */ +#define WDOG_WICR_WTIS (1 << 14) /* Bit 14: Watchdog Timer Interrupt Status */ +#define WDOG_WICR_WIE (1 << 15) /* Bit 15: Watchdog Timer Interrupt enable */ + +/* Watchdog misc control */ + +#define WDOG_WMCR_PDE (1 << 0) /* Bit 0: Power Down Enable */ + /* Bits 1-15: Reserved */ +/* RT Watchdog Control and Status Register */ + +#define RTWDOG_CS_STOP (1 << 0) /* Bit 0: Stop enable */ +#define RTWDOG_CS_WAIT (1 << 1) /* Bit 1: Wait enable */ +#define RTWDOG_CS_DBG (1 << 2) /* Bit 2: Debug Enable */ +#define RTWDOG_CS_TST_SHIFT (3) /* Bits 3-4: Enables the fast test mode */ +#define RTWDOG_CS_TST_MASK (0x03 << RTWDOG_CS_TST_SHIFT) +# define RTWDOG_CS_TST(n) ((uint32_t)((n)) << RTWDOG_CS_TST_SHIFT) +#define RTWDOG_CS_UPDATE (1 << 5) /* Bit 5: Update */ +#define RTWDOG_CS_INT (1 << 6) /* Bit 6: Interrupt */ +#define RTWDOG_CS_EN (1 << 7) /* Bit 7: Enable */ +#define RTWDOG_CS_CLK_SHIFT (8) /* Bits 8-9: Clock */ +#define RTWDOG_CS_CLK_MASK (0x03 << RTWDOG_CS_CLK_SHIFT) +# define RTWDOG_CS_CLK(n) ((uint32_t)((n)) << RTWDOG_CS_CLK_SHIFT) +#define RTWDOG_CS_RCS (1 << 10) /* Bit 10: Reconfiguration Success */ +#define RTWDOG_CS_ULK (1 << 11) /* Bit 11: Unlock status */ +#define RTWDOG_CS_PRES (1 << 12) /* Bit 12: Watchdog prescaler */ +#define RTWDOG_CS_CMD32EN (1 << 13) /* Bit 13: WDOG support for 32-bit */ +#define RTWDOG_CS_FLG (1 << 14) /* Bit 14: Interrupt Flag */ +#define RTWDOG_CS_WIN (1 << 15) /* Bit 15: Watchdog Window */ + +#define RTWDOG_UPDATE_KEY (0xd928c520) +#define RTWDOG_REFRESH_KEY (0xb480a602) + +#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_WDOG_H */ diff --git a/arch/arm/src/imxrt/imxrt_allocateheap.c b/arch/arm/src/imxrt/imxrt_allocateheap.c new file mode 100644 index 00000000000..a320c514655 --- /dev/null +++ b/arch/arm/src/imxrt/imxrt_allocateheap.c @@ -0,0 +1,357 @@ +/**************************************************************************** + * arch/arm/src/imxrt/imxrt_allocateheap.c + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +#include "up_arch.h" +#include "up_internal.h" + +#include "chip/imxrt_memorymap.h" +#include "imxrt_mpuinit.h" + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +/* Configuration ************************************************************/ +/* Terminology. In the flat build (CONFIG_BUILD_FLAT=y), there is only a + * single heap access with the standard allocations (malloc/free). This + * heap is referred to as the user heap. In the protected build + * (CONFIG_BUILD_PROTECTED=y) where an MPU is used to protect a region of + * otherwise flat memory, there will be two allocators: One that allocates + * protected (kernel) memory and one that allocates unprotected (user) + * memory. These are referred to as the kernel and user heaps, + * respectively. + * + * The ARMv7 has no MPU but does have an MMU. Without an MMU, it cannot + * support the kernel build (CONFIG_BUILD_KERNEL=y). In that configuration, + * there would is one kernel heap but multiple user heaps: One per task + * group. However, in this case, we need only be concerned about + * initializing the single kernel heap here. + * + * Primary RAM: The Linker script positions the system BLOB's .data and + * .bss in some RAM. We refer to that RAM as the primary RAM. It also + * holds the IDLE threads stack and any remaining portion of the primary + * RAM is automatically added to the heap. The start and size of the + * primary RAM are provided by CONFIG_RAM_START and CONFIG_RAM_SIZE. The + * linker provided address, ... .sbss, .ebss, .sdat, etc. ... are expected + * to lie in the the region defined by those configuration settings. + * + * Other RAM regions must be selected use configuration options and the + * start and end of those RAM regions must also be provided in the + * configuration. CONFIG_MM_REGIONS must also be set to determined the + * number of regions to be added to the heap. + * + * REVISIT: The i.MX RT SEMC will support up to 8 512Mbit memory regions. + * So it is possible that there could be multiple external SDRAM or SRAM + * banks. This logic assumes that there is at most one of each (or at least + * only one contiguous block of addresses for each). This would need to + * be exceed considerably to support multiple SDRAM or SRAM memory regions. + */ + +#define IMXRT_DTCM_BASE 0x20000000 /* 512KB DTCM */ + /* 0x20080000 512KB DTCM Reserved */ + /* 0x20100000 1MB Reserved */ +#define IMXRT_OCRAM_BASE 0x20200000 /* 512KB OCRAM */ + +/* There there then several memory configurations with a one primary memory + * region and up to two additional memory regions which may be OCRAM, + * external SDRAM, or external SRAM. + */ + +#undef IMXRT_OCRAM_ASSIGNED +#undef IMXRT_SDRAM_ASSIGNED +#undef IMXRT_SRAM_ASSIGNED + +/* REVISIT: Assume that if OCRAM is the primary RAM, then DTCM and ITCM are + * not being used. + */ + +#if defined(CONFIG_IMXRT_OCRAM_PRIMARY) +# define PRIMARY_RAM_START IMXRT_OCRAM_BASE /* CONFIG_RAM_START */ +# define PRIMARY_RAM_SIZE IMXRT_OCRAM_SIZE /* CONFIG_RAM_SIZE */ +# define IMXRT_OCRAM_ASSIGNED 1 +#elif defined(CONFIG_IMXRT_SDRAM_PRIMARY) +# define PRIMARY_RAM_START CONFIG_IMXRT_SDRAM_START /* CONFIG_RAM_START */ +# define PRIMARY_RAM_SIZE CONFIG_IMXRT_SDRAM_SIZE /* CONFIG_RAM_SIZE */ +# define IMXRT_SDRAM_ASSIGNED 1 +#elif defined(CONFIG_IMXRT_SRAM_PRIMARY) +# define PRIMARY_RAM_START CONFIG_IMXRT_SRAM_START /* CONFIG_RAM_START */ +# define PRIMARY_RAM_SIZE CONFIG_IMXRT_SRAM_SIZE /* CONFIG_RAM_SIZE */ +# define IMXRT_SRAM_ASSIGNED 1 +#else +# error No primary RAM defined +#endif + +#define PRIMARY_RAM_END (PRIMARY_RAM_START + PRIMARY_RAM_SIZE) + +/* REVISIT: I am not sure how this works. But I am assuming that if DTCM + * is enabled, then ITCM is not and we can just use the DTCM base address to + * access OCRAM. + */ + +#ifdef CONFIG_IMXRT_DTCM +# define IMXRT_OCRAM_START IMXRT_DTCM_BASE +#else +# define IMXRT_OCRAM_START IMXRT_OCRAM_BASE +#endif + +#if CONFIG_MM_REGIONS > 1 +/* Pick the first region to add to the heap could be any one of OCRAM, + * SDRAM, or SRAM depending upon which are enabled and which has not + * already been assigned as the primary RAM. + */ + +#if defined(CONFIG_IMXRT_OCRAM_HEAP) && !defined(IMXRT_OCRAM_ASSIGNED) +# define REGION1_RAM_START IMXRT_OCRAM_START +# define REGION1_RAM_SIZE IMXRT_OCRAM_SIZE +# define IMXRT_OCRAM_ASSIGNED 1 +#elif defined(CONFIG_IMXRT_SDRAM_HEAP) && !defined(IMXRT_SDRAM_ASSIGNED) +# define REGION1_RAM_START (CONFIG_IMXRT_SDRAM_START + CONFIG_IMXRT_SDRAM_HEAPOFFSET) +# define REGION1_RAM_SIZE (CONFIG_IMXRT_SDRAM_SIZE - CONFIG_IMXRT_SDRAM_HEAPOFFSET) +# define IMXRT_SDRAM_ASSIGNED 1 +#elif defined(CONFIG_IMXRT_SDRAM_HEAP) && !defined(IMXRT_SDRAM_ASSIGNED) +# define REGION1_RAM_START (CONFIG_IMXRT_SRAM_START + CONFIG_IMXRT_SRAM_HEAPOFFSET) +# define REGION1_RAM_SIZE (CONFIG_IMXRT_SRAM_SIZE - CONFIG_IMXRT_SRAM_HEAPOFFSET) +# define IMXRT_SDRAM_ASSIGNED 1 +#else +# warning CONFIG_MM_REGIONS > 1 but no available memory region +#endif + +#define REGION1_RAM_END (REGION1_RAM_START + REGION1_RAM_SIZE) +#endif + +#if CONFIG_MM_REGIONS > 2 +/* Pick the first region to add to the heap could be any one of OCRAM, + * SDRAM, or SRAM depending upon which are enabled and which has not + * already been assigned as the primary RAM. + */ + +#if defined(CONFIG_IMXRT_OCRAM_HEAP) && !defined(IMXRT_OCRAM_ASSIGNED) +# define REGION2_RAM_START IMXRT_OCRAM_START +# define REGION2_RAM_SIZE IMXRT_OCRAM_SIZE +# define IMXRT_OCRAM_ASSIGNED 1 +#elif defined(CONFIG_IMXRT_SDRAM_HEAP) && !defined(IMXRT_SDRAM_ASSIGNED) +# define REGION2_RAM_START (CONFIG_IMXRT_SDRAM_START + CONFIG_IMXRT_SDRAM_HEAPOFFSET) +# define REGION2_RAM_SIZE (CONFIG_IMXRT_SDRAM_SIZE - CONFIG_IMXRT_SDRAM_HEAPOFFSET) +# define IMXRT_SDRAM_ASSIGNED 1 +#elif defined(CONFIG_IMXRT_SDRAM_HEAP) && !defined(IMXRT_SDRAM_ASSIGNED) +# define REGION2_RAM_START (CONFIG_IMXRT_SRAM_START + CONFIG_IMXRT_SRAM_HEAPOFFSET) +# define REGION2_RAM_SIZE (CONFIG_IMXRT_SRAM_SIZE - CONFIG_IMXRT_SRAM_HEAPOFFSET) +# define IMXRT_SDRAM_ASSIGNED 1 +#else +# warning CONFIG_MM_REGIONS > 2 but no available memory region +#endif + +#define REGION2_RAM_END (REGION2_RAM_START + REGION2_RAM_SIZE) +#endif + +#if CONFIG_MM_REGIONS > 3 +# warning CONFIG_MM_REGIONS > 3 but no available memory region +#endif + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* _sbss is the start of the BSS region (see the linker script) _ebss is the + * end of the BSS regions (see the linker script). The idle task stack starts + * at the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE. The IDLE + * thread is the thread that the system boots on and, eventually, becomes the + * idle, do nothing task that runs only when there is nothing else to run. + * The heap continues from there until the configured end of memory. + * g_idle_topstack is the beginning of this heap region (not necessarily + * aligned). + */ + +const uintptr_t g_idle_topstack = (uintptr_t)&_ebss + CONFIG_IDLETHREAD_STACKSIZE; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_allocate_heap/up_allocate_kheap + * + * Description: + * This function will be called to dynamically set aside the heap region. + * + * - For the normal "flat" build, this function returns the size of the + * single heap. + * - For the protected build (CONFIG_BUILD_PROTECTED=y) with both kernel- + * and user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function + * provides the size of the unprotected, user-space heap. + * - For the kernel build (CONFIG_BUILD_KERNEL=y), this function provides + * the size of the protected, kernel-space heap. + * + * If a protected kernel-space heap is provided, the kernel heap must be + * allocated by an analogous up_allocate_kheap(). A custom version of this + * file is needed if memory protection of the kernel heap is required. + * + * The following memory map is assumed for the flat build: + * + * .data region. Size determined at link time. + * .bss region Size determined at link time. + * IDLE thread stack. Size determined by CONFIG_IDLETHREAD_STACKSIZE. + * Heap. Extends to the end of SRAM. + * + * The following memory map is assumed for the kernel build: + * + * Kernel .data region. Size determined at link time. + * Kernel .bss region Size determined at link time. + * Kernel IDLE thread stack. Size determined by CONFIG_IDLETHREAD_STACKSIZE. + * Padding for alignment + * User .data region. Size determined at link time. + * User .bss region Size determined at link time. + * Kernel heap. Size determined by CONFIG_MM_KERNEL_HEAPSIZE. + * User heap. Extends to the end of SRAM. + * + ****************************************************************************/ + +#ifdef CONFIG_BUILD_KERNEL +void up_allocate_kheap(FAR void **heap_start, size_t *heap_size) +#else +void up_allocate_heap(FAR void **heap_start, size_t *heap_size) +#endif +{ +#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) + /* Get the unaligned size and position of the user-space heap. + * This heap begins after the user-space .bss section at an offset + * of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment). + */ + + uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + CONFIG_MM_KERNEL_HEAPSIZE; + size_t usize = PRIMARY_RAM_END - ubase; + + DEBUGASSERT(ubase < (uintptr_t)PRIMARY_RAM_END); + + /* Return the user-space heap settings */ + + board_autoled_on(LED_HEAPALLOCATE); + *heap_start = (FAR void *)ubase; + *heap_size = usize; +#else + + /* Return the heap settings */ + + board_autoled_on(LED_HEAPALLOCATE); + *heap_start = (FAR void *)g_idle_topstack; + *heap_size = PRIMARY_RAM_END - g_idle_topstack; +#endif +} + +/**************************************************************************** + * Name: up_allocate_kheap + * + * Description: + * For the kernel build (CONFIG_BUILD_PROTECTED/KERNEL=y) with both kernel- + * and user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function allocates + * the kernel-space heap. A custom version of this function is needed if + * memory protection of the kernel heap is required. + * + ****************************************************************************/ + +#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) +void up_allocate_kheap(FAR void **heap_start, size_t *heap_size) +{ + /* Get the unaligned size and position of the user-space heap. + * This heap begins after the user-space .bss section at an offset + * of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment). + */ + + uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + CONFIG_MM_KERNEL_HEAPSIZE; + DEBUGASSERT(ubase < (uintptr_t)PRIMARY_RAM_END); + + /* Return the kernel heap settings (i.e., the part of the heap region + * that was not dedicated to the user heap). + */ + + *heap_start = (FAR void *)USERSPACE->us_bssend; + *heap_size = ubase - (uintptr_t)USERSPACE->us_bssend; +} +#endif + +/**************************************************************************** + * Name: up_addregion + * + * Description: + * Memory may be added in non-contiguous chunks. Additional chunks are + * added by calling this function. + * + ****************************************************************************/ + +#if CONFIG_MM_REGIONS > 1 +void up_addregion(void) +{ + /* Add region 1 to the user heap */ + + kumm_addregion((FAR void *)REGION1_RAM_START, REGION1_RAM_SIZE); + +#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) + /* Allow user-mode access to region 1 */ + + imxrt_mpu_uheap((uintptr_t)REGION1_RAM_START, REGION1_RAM_SIZE); +#endif + +#if CONFIG_MM_REGIONS > 2 + /* Add region 2 to the user heap */ + + kumm_addregion((FAR void *)REGION2_RAM_START, REGION2_RAM_SIZE); + +#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) + /* Allow user-mode access to region 2 */ + + imxrt_mpu_uheap((uintptr_t)REGION2_RAM_START, REGION2_RAM_SIZE); +#endif +#endif /* CONFIG_MM_REGIONS > 2 */ +} +#endif /* CONFIG_MM_REGIONS > 1 */ diff --git a/arch/arm/src/imxrt/imxrt_clockconfig.c b/arch/arm/src/imxrt/imxrt_clockconfig.c new file mode 100644 index 00000000000..6f4d7cad08a --- /dev/null +++ b/arch/arm/src/imxrt/imxrt_clockconfig.c @@ -0,0 +1,159 @@ +/**************************************************************************** + * arch/arm/src/imxrt/imxrt_clockconfig.c + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Janne Rosberg + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "up_arch.h" +#include +#include "chip/imxrt_ccm.h" +#include "chip/imxrt_dcdc.h" +#include "imxrt_clockconfig.h" +#include "chip/imxrt105x_memorymap.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imxrt_clockconfig + * + * Description: + * Called to initialize the i.MXRT. This does whatever setup is needed to + * put the SoC in a usable state. This includes the initialization of + * clocking using the settings in board.h. + * + ****************************************************************************/ + +void imxrt_clockconfig(void) +{ + /* Don't change the current basic clock configuration if we are running + * from SDRAM. In this case, some bootloader logic has already configured + * clocking and SDRAM. We are pretty much committed to using things the + * way that the bootloader has left them. + */ + +#ifndef CONFIG_IMXRT_BOOT_SDRAM + uint32_t reg; + + /* Set clock mux and dividers */ + + /* Set PERIPH_CLK2 MUX to OSC */ + + reg = getreg32(IMXRT_CCM_CBCMR); + reg &= ~CCM_CBCMR_PERIPH_CLK2_SEL_MASK; + reg |= CCM_CBCMR_PERIPH_CLK2_SEL_OSC_CLK; + putreg32(reg, IMXRT_CCM_CBCMR); + + /* Set PERIPH_CLK MUX to PERIPH_CLK2 */ + + reg = getreg32(IMXRT_CCM_CBCDR); + reg |= CCM_CBCDR_SEMC_PERIPH_CLK_SEL; + putreg32(reg, IMXRT_CCM_CBCDR); + + /* Wait handshake */ + + while ((getreg32(IMXRT_CCM_CDHIPR) & CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY) == 1) + { + } + + /* Set Soc VDD */ + + reg = getreg32(IMXRT_DCDC_REG3); + reg &= ~(DCDC_REG3_TRG_MASK); + reg |= DCDC_REG3_TRG(IMXRT_VDD_SOC); + putreg32(reg, IMXRT_DCDC_REG3); + + /* Init Arm PLL1 */ + + reg = CCM_ANALOG_PLL_ARM_DIV_SELECT(IMXRT_ARM_PLL_SELECT) | CCM_ANALOG_PLL_ARM_ENABLE; + putreg32(reg, IMXRT_CCM_ANALOG_PLL_ARM); + while ((getreg32(IMXRT_CCM_ANALOG_PLL_ARM) & CCM_ANALOG_PLL_ARM_LOCK) == 0) + { + } + + /* Init Sys PLL2 */ + + reg = CCM_ANALOG_PLL_SYS_DIV_SELECT(IMXRT_SYS_PLL_SELECT) | CCM_ANALOG_PLL_SYS_ENABLE; + putreg32(reg, IMXRT_CCM_ANALOG_PLL_SYS); + while ((getreg32(IMXRT_CCM_ANALOG_PLL_SYS) & CCM_ANALOG_PLL_SYS_LOCK) == 0) + { + } + + /* TODO: other pll configs */ + + /* Set Dividers */ + + putreg32(CCM_CACRR_ARM_PODF(IMXRT_ARM_CLOCK_DIVIDER), IMXRT_CCM_CACRR); + putreg32(CCM_CBCDR_AHB_PODF(IMXRT_AHB_CLOCK_DIVIDER), IMXRT_CCM_CBCDR); + putreg32(CCM_CBCDR_IPG_PODF(IMXRT_IPG_CLOCK_DIVIDER), IMXRT_CCM_CBCDR); + + /* Set PRE_PERIPH_CLK to PLL1 */ + + reg = getreg32(IMXRT_CCM_CBCMR); + reg &= ~CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK; + reg |= CCM_CBCMR_PRE_PERIPH_CLK_SEL_PLL1; + putreg32(reg, IMXRT_CCM_CBCMR); + + /* Set PERIPH_CLK MUX to PRE_PERIPH_CLK2 */ + + reg = getreg32(IMXRT_CCM_CBCDR); + reg &= ~CCM_CBCDR_SEMC_PERIPH_CLK_SEL; + putreg32(reg, IMXRT_CCM_CBCDR); + + /* Wait handshake */ + + while ((getreg32(IMXRT_CCM_CDHIPR) & CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY) == 1) + { + } + + /* Set UART source to PLL3 80M */ + + reg = getreg32(IMXRT_CCM_CSCDR1); + reg &= CCM_CSCDR1_UART_CLK_SEL; + reg |= CCM_CSCDR1_UART_CLK_SEL_PLL3_80; + putreg32(reg, IMXRT_CCM_CBCDR); + + /* Set UART divider to 1 */ + + reg = getreg32(IMXRT_CCM_CSCDR1); + reg &= CCM_CSCDR1_UART_CLK_PODF_MASK; + reg |= CCM_CSCDR1_UART_CLK_PODF(0); + putreg32(reg, IMXRT_CCM_CBCDR); +#endif +} diff --git a/arch/arm/src/imxrt/imxrt_clockconfig.h b/arch/arm/src/imxrt/imxrt_clockconfig.h new file mode 100644 index 00000000000..d6aed607e5e --- /dev/null +++ b/arch/arm/src/imxrt/imxrt_clockconfig.h @@ -0,0 +1,61 @@ +/**************************************************************************** + * arch/arm/src/imrt/imxrt_clockconfig.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMRT_IMX_CLOCKCONFIG_H +#define __ARCH_ARM_SRC_IMRT_IMX_CLOCKCONFIG_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: imxrt_clockconfig + * + * Description: + * Called to initialize the i.MXRT. This does whatever setup is needed to + * put the SoC in a usable state. This includes the initialization of + * clocking using the settings in board.h. + * + ****************************************************************************/ + +void imxrt_clockconfig(void); + +#endif /* __ARCH_ARM_SRC_IMRT_IMX_CLOCKCONFIG_H */ diff --git a/arch/arm/src/imxrt/imxrt_clrpend.c b/arch/arm/src/imxrt/imxrt_clrpend.c new file mode 100644 index 00000000000..3b500267646 --- /dev/null +++ b/arch/arm/src/imxrt/imxrt_clrpend.c @@ -0,0 +1,106 @@ +/**************************************************************************** + * arch/arm/src/imxrt/imxrt_clrpend.c + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "nvic.h" +#include "up_arch.h" + +#include "imxrt_irq.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imxrt_clrpend + * + * Description: + * Clear a pending interrupt at the NVIC. This does not seem to be required + * for most interrupts. Don't know why... but the LPC54xx Ethernet EMAC + * interrupt definitely needs it! + * + * This function is logically a part of imxrt_irq.c, but I will keep it in + * a separate file so that it will not increase the footprint on LPC54xx + * platforms that do not need this function. + * + ****************************************************************************/ + +void imxrt_clrpend(int irq) +{ + /* Check for external interrupt */ + + if (irq >= IMXRT_IRQ_EXTINT) + { + if (irq < (IMXRT_IRQ_EXTINT + 32)) + { + putreg32(1 << (irq - IMXRT_IRQ_EXTINT), NVIC_IRQ0_31_CLRPEND); + } +#if IMXRT_IRQ_NEXTINT >= 64 + else if (irq < (IMXRT_IRQ_EXTINT + 64)) + { + putreg32(1 << (irq - IMXRT_IRQ_EXTINT - 32), NVIC_IRQ32_63_CLRPEND); + } +#endif +#if IMXRT_IRQ_NEXTINT >= 96 + else if (irq < (IMXRT_IRQ_EXTINT + 96)) + { + putreg32(1 << (irq - IMXRT_IRQ_EXTINT - 64), NVIC_IRQ64_95_CLRPEND); + } +#endif +#if IMXRT_IRQ_NEXTINT >= 128 + else if (irq < (IMXRT_IRQ_EXTINT + 128)) + { + putreg32(1 << (irq - IMXRT_IRQ_EXTINT - 96), NVIC_IRQ96_127_CLRPEND); + } +#endif +#if IMXRT_IRQ_NEXTINT >= 160 + else if (irq < (IMXRT_IRQ_EXTINT + 160)) + { + putreg32(1 << (irq - IMXRT_IRQ_EXTINT - 128), NVIC_IRQ128_159_CLRPEND); + } +#endif + else + { + DEBUGPANIC(); + } + } +} diff --git a/arch/arm/src/imxrt/imxrt_config.h b/arch/arm/src/imxrt/imxrt_config.h new file mode 100644 index 00000000000..57e20cab118 --- /dev/null +++ b/arch/arm/src/imxrt/imxrt_config.h @@ -0,0 +1,206 @@ +/************************************************************************************ + * arch/arm/src/imxrt/imxrt_config.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMXRT_IMXRT_CONFIG_H +#define __ARCH_ARM_SRC_IMXRT_IMXRT_CONFIG_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include + +#include "chip.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Configuration *********************************************************************/ + +#undef HAVE_LPUART1 +#undef HAVE_LPUART2 +#undef HAVE_LPUART3 +#undef HAVE_LPUART4 +#undef HAVE_LPUART5 +#undef HAVE_LPUART6 +#undef HAVE_LPUART7 +#undef HAVE_LPUART8 + +#ifdef CONFIG_IMXRT_LPUART1 +# define HAVE_LPUART1 1 +#endif +#ifdef CONFIG_IMXRT_LPUART2 +# define HAVE_LPUART2 1 +#endif +#ifdef CONFIG_IMXRT_LPUART3 +# define HAVE_LPUART3 1 +#endif +#ifdef CONFIG_IMXRT_LPUART4 +# define HAVE_LPUART4 1 +#endif +#ifdef CONFIG_IMXRT_LPUART5 +# define HAVE_LPUART5 1 +#endif +#ifdef CONFIG_IMXRT_LPUART6 +# define HAVE_LPUART6 1 +#endif +#ifdef CONFIG_IMXRT_LPUART7 +# define HAVE_LPUART7 1 +#endif +#ifdef CONFIG_IMXRT_LPUART8 +# define HAVE_LPUART8 1 +#endif + +/* Check if we have a LPUART device */ + +#undef CONFIG_IMXRT_HAVE_LPUART +#undef HAVE_LPUART_DEVICE + +#if defined(HAVE_LPUART1) || defined(HAVE_LPUART2) || defined(HAVE_LPUART3) || \ + defined(HAVE_LPUART4) || defined(HAVE_LPUART5) || defined(HAVE_LPUART6) || \ + defined(HAVE_LPUART7) || defined(HAVE_LPUART8) +# define HAVE_LPUART_DEVICE 1 +#endif + +/* Is there a serial console? There should be at most one defined. It could be on + * any LPUARTn, n=1,2,3,4,5,6,7,8 + */ + +#undef HAVE_LPUART_CONSOLE + +#if defined(CONFIG_LPUART1_SERIAL_CONSOLE) && defined(HAVE_LPUART1) +# undef CONFIG_LPUART2_SERIAL_CONSOLE +# undef CONFIG_LPUART3_SERIAL_CONSOLE +# undef CONFIG_LPUART4_SERIAL_CONSOLE +# undef CONFIG_LPUART5_SERIAL_CONSOLE +# undef CONFIG_LPUART6_SERIAL_CONSOLE +# undef CONFIG_LPUART7_SERIAL_CONSOLE +# undef CONFIG_LPUART8_SERIAL_CONSOLE +# define HAVE_LPUART_CONSOLE 1 +#elif defined(CONFIG_LPUART2_SERIAL_CONSOLE) && defined(HAVE_LPUART2) +# undef CONFIG_LPUART1_SERIAL_CONSOLE +# undef CONFIG_LPUART3_SERIAL_CONSOLE +# undef CONFIG_LPUART4_SERIAL_CONSOLE +# undef CONFIG_LPUART5_SERIAL_CONSOLE +# undef CONFIG_LPUART6_SERIAL_CONSOLE +# undef CONFIG_LPUART7_SERIAL_CONSOLE +# undef CONFIG_LPUART8_SERIAL_CONSOLE +# define HAVE_LPUART_CONSOLE 1 +#elif defined(CONFIG_LPUART3_SERIAL_CONSOLE) && defined(HAVE_LPUART3) +# undef CONFIG_LPUART1_SERIAL_CONSOLE +# undef CONFIG_LPUART2_SERIAL_CONSOLE +# undef CONFIG_LPUART4_SERIAL_CONSOLE +# undef CONFIG_LPUART5_SERIAL_CONSOLE +# undef CONFIG_LPUART6_SERIAL_CONSOLE +# undef CONFIG_LPUART7_SERIAL_CONSOLE +# undef CONFIG_LPUART8_SERIAL_CONSOLE +# define HAVE_LPUART_CONSOLE 1 +#elif defined(CONFIG_LPUART4_SERIAL_CONSOLE) && defined(HAVE_LPUART4) +# undef CONFIG_LPUART1_SERIAL_CONSOLE +# undef CONFIG_LPUART2_SERIAL_CONSOLE +# undef CONFIG_LPUART3_SERIAL_CONSOLE +# undef CONFIG_LPUART5_SERIAL_CONSOLE +# undef CONFIG_LPUART6_SERIAL_CONSOLE +# undef CONFIG_LPUART7_SERIAL_CONSOLE +# undef CONFIG_LPUART8_SERIAL_CONSOLE +# define HAVE_LPUART_CONSOLE 1 +#elif defined(CONFIG_LPUART5_SERIAL_CONSOLE) && defined(HAVE_LPUART5) +# undef CONFIG_LPUART1_SERIAL_CONSOLE +# undef CONFIG_LPUART2_SERIAL_CONSOLE +# undef CONFIG_LPUART3_SERIAL_CONSOLE +# undef CONFIG_LPUART4_SERIAL_CONSOLE +# undef CONFIG_LPUART6_SERIAL_CONSOLE +# undef CONFIG_LPUART7_SERIAL_CONSOLE +# undef CONFIG_LPUART8_SERIAL_CONSOLE +# define HAVE_LPUART_CONSOLE 1 +#elif defined(CONFIG_LPUART6_SERIAL_CONSOLE) && defined(HAVE_LPUART6) +# undef CONFIG_LPUART1_SERIAL_CONSOLE +# undef CONFIG_LPUART2_SERIAL_CONSOLE +# undef CONFIG_LPUART3_SERIAL_CONSOLE +# undef CONFIG_LPUART4_SERIAL_CONSOLE +# undef CONFIG_LPUART5_SERIAL_CONSOLE +# undef CONFIG_LPUART7_SERIAL_CONSOLE +# undef CONFIG_LPUART8_SERIAL_CONSOLE +# define HAVE_LPUART_CONSOLE 1 +#elif defined(CONFIG_LPUART7_SERIAL_CONSOLE) && defined(HAVE_LPUART7) +# undef CONFIG_LPUART1_SERIAL_CONSOLE +# undef CONFIG_LPUART2_SERIAL_CONSOLE +# undef CONFIG_LPUART3_SERIAL_CONSOLE +# undef CONFIG_LPUART4_SERIAL_CONSOLE +# undef CONFIG_LPUART5_SERIAL_CONSOLE +# undef CONFIG_LPUART6_SERIAL_CONSOLE +# undef CONFIG_LPUART8_SERIAL_CONSOLE +# define HAVE_LPUART_CONSOLE 1 +#elif defined(CONFIG_LPUART8_SERIAL_CONSOLE) && defined(HAVE_LPUART8) +# undef CONFIG_LPUART1_SERIAL_CONSOLE +# undef CONFIG_LPUART2_SERIAL_CONSOLE +# undef CONFIG_LPUART3_SERIAL_CONSOLE +# undef CONFIG_LPUART4_SERIAL_CONSOLE +# undef CONFIG_LPUART5_SERIAL_CONSOLE +# undef CONFIG_LPUART6_SERIAL_CONSOLE +# undef CONFIG_LPUART7_SERIAL_CONSOLE +# define HAVE_LPUART_CONSOLE 1 +#else +# ifdef CONFIG_DEV_CONSOLE +# warning "No valid CONFIG_[LP]LPUART[n]_SERIAL_CONSOLE Setting" +# endif +# undef CONFIG_LPUART1_SERIAL_CONSOLE +# undef CONFIG_LPUART2_SERIAL_CONSOLE +# undef CONFIG_LPUART3_SERIAL_CONSOLE +# undef CONFIG_LPUART4_SERIAL_CONSOLE +# undef CONFIG_LPUART5_SERIAL_CONSOLE +# undef CONFIG_LPUART6_SERIAL_CONSOLE +# undef CONFIG_LPUART7_SERIAL_CONSOLE +# undef CONFIG_LPUART8_SERIAL_CONSOLE +#endif + +/* Check LPUART flow control (Not yet supported) */ + +# undef CONFIG_LPUART1_FLOWCONTROL +# undef CONFIG_LPUART2_FLOWCONTROL +# undef CONFIG_LPUART3_FLOWCONTROL +# undef CONFIG_LPUART4_FLOWCONTROL +# undef CONFIG_LPUART5_FLOWCONTROL +# undef CONFIG_LPUART6_FLOWCONTROL +# undef CONFIG_LPUART7_FLOWCONTROL +# undef CONFIG_LPUART8_FLOWCONTROL + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_IMXRT_IMXRT_CONFIG_H */ diff --git a/arch/arm/src/imxrt/imxrt_gpio.c b/arch/arm/src/imxrt/imxrt_gpio.c new file mode 100644 index 00000000000..fe9b78b4bab --- /dev/null +++ b/arch/arm/src/imxrt/imxrt_gpio.c @@ -0,0 +1,510 @@ +/**************************************************************************** + * arch/arm/src/imxrt/imxrt_gpio.c + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#include "chip.h" +#include "up_arch.h" +#include "imxrt_iomuxc.h" +#include "imxrt_gpio.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define IMXRT_PADMUX_INVALID 255 + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const uint8_t g_gpio1_padmux[IMXRT_GPIO_NPINS] = +{ + IMXRT_PADMUX_GPIO_AD_B0_00_INDEX, /* GPIO1 Pin 0 */ + IMXRT_PADMUX_GPIO_AD_B0_01_INDEX, /* GPIO1 Pin 1 */ + IMXRT_PADMUX_GPIO_AD_B0_02_INDEX, /* GPIO1 Pin 2 */ + IMXRT_PADMUX_GPIO_AD_B0_03_INDEX, /* GPIO1 Pin 3 */ + IMXRT_PADMUX_GPIO_AD_B0_04_INDEX, /* GPIO1 Pin 4 */ + IMXRT_PADMUX_GPIO_AD_B0_05_INDEX, /* GPIO1 Pin 5 */ + IMXRT_PADMUX_GPIO_AD_B0_06_INDEX, /* GPIO1 Pin 6 */ + IMXRT_PADMUX_GPIO_AD_B0_07_INDEX, /* GPIO1 Pin 7 */ + + IMXRT_PADMUX_GPIO_AD_B0_08_INDEX, /* GPIO1 Pin 8 */ + IMXRT_PADMUX_GPIO_AD_B0_09_INDEX, /* GPIO1 Pin 9 */ + IMXRT_PADMUX_GPIO_AD_B0_10_INDEX, /* GPIO1 Pin 10 */ + IMXRT_PADMUX_GPIO_AD_B0_11_INDEX, /* GPIO1 Pin 11 */ + IMXRT_PADMUX_GPIO_AD_B0_12_INDEX, /* GPIO1 Pin 12 */ + IMXRT_PADMUX_GPIO_AD_B0_13_INDEX, /* GPIO1 Pin 13 */ + IMXRT_PADMUX_GPIO_AD_B0_14_INDEX, /* GPIO1 Pin 14 */ + IMXRT_PADMUX_GPIO_AD_B0_15_INDEX, /* GPIO1 Pin 15 */ + + IMXRT_PADMUX_GPIO_AD_B1_00_INDEX, /* GPIO1 Pin 16 */ + IMXRT_PADMUX_GPIO_AD_B1_01_INDEX, /* GPIO1 Pin 17 */ + IMXRT_PADMUX_GPIO_AD_B1_02_INDEX, /* GPIO1 Pin 18 */ + IMXRT_PADMUX_GPIO_AD_B1_03_INDEX, /* GPIO1 Pin 19 */ + IMXRT_PADMUX_GPIO_AD_B1_04_INDEX, /* GPIO1 Pin 20 */ + IMXRT_PADMUX_GPIO_AD_B1_05_INDEX, /* GPIO1 Pin 21 */ + IMXRT_PADMUX_GPIO_AD_B1_06_INDEX, /* GPIO1 Pin 22 */ + IMXRT_PADMUX_GPIO_AD_B1_07_INDEX, /* GPIO1 Pin 23 */ + + IMXRT_PADMUX_GPIO_AD_B1_08_INDEX, /* GPIO1 Pin 24 */ + IMXRT_PADMUX_GPIO_AD_B1_09_INDEX, /* GPIO1 Pin 25 */ + IMXRT_PADMUX_GPIO_AD_B1_10_INDEX, /* GPIO1 Pin 26 */ + IMXRT_PADMUX_GPIO_AD_B1_11_INDEX, /* GPIO1 Pin 27 */ + IMXRT_PADMUX_GPIO_AD_B1_12_INDEX, /* GPIO1 Pin 28 */ + IMXRT_PADMUX_GPIO_AD_B1_13_INDEX, /* GPIO1 Pin 29 */ + IMXRT_PADMUX_GPIO_AD_B1_14_INDEX, /* GPIO1 Pin 30 */ + IMXRT_PADMUX_GPIO_AD_B1_15_INDEX /* GPIO1 Pin 31 */ +}; + +static const uint8_t g_gpio2_padmux[IMXRT_GPIO_NPINS] = +{ + IMXRT_PADMUX_GPIO_B0_00_INDEX, /* GPIO2 Pin 0 */ + IMXRT_PADMUX_GPIO_B0_01_INDEX, /* GPIO2 Pin 1 */ + IMXRT_PADMUX_GPIO_B0_02_INDEX, /* GPIO2 Pin 2 */ + IMXRT_PADMUX_GPIO_B0_03_INDEX, /* GPIO2 Pin 3 */ + IMXRT_PADMUX_GPIO_B0_04_INDEX, /* GPIO2 Pin 4 */ + IMXRT_PADMUX_GPIO_B0_05_INDEX, /* GPIO2 Pin 5 */ + IMXRT_PADMUX_GPIO_B0_06_INDEX, /* GPIO2 Pin 6 */ + IMXRT_PADMUX_GPIO_B0_07_INDEX, /* GPIO2 Pin 7 */ + + IMXRT_PADMUX_GPIO_B0_08_INDEX, /* GPIO2 Pin 8 */ + IMXRT_PADMUX_GPIO_B0_09_INDEX, /* GPIO2 Pin 9 */ + IMXRT_PADMUX_GPIO_B0_10_INDEX, /* GPIO2 Pin 10 */ + IMXRT_PADMUX_GPIO_B0_11_INDEX, /* GPIO2 Pin 11 */ + IMXRT_PADMUX_GPIO_B0_12_INDEX, /* GPIO2 Pin 12 */ + IMXRT_PADMUX_GPIO_B0_13_INDEX, /* GPIO2 Pin 13 */ + IMXRT_PADMUX_GPIO_B0_14_INDEX, /* GPIO2 Pin 14 */ + IMXRT_PADMUX_GPIO_B0_15_INDEX, /* GPIO2 Pin 15 */ + + IMXRT_PADMUX_GPIO_B1_00_INDEX, /* GPIO2 Pin 16 */ + IMXRT_PADMUX_GPIO_B1_01_INDEX, /* GPIO2 Pin 17 */ + IMXRT_PADMUX_GPIO_B1_02_INDEX, /* GPIO2 Pin 18 */ + IMXRT_PADMUX_GPIO_B1_03_INDEX, /* GPIO2 Pin 19 */ + IMXRT_PADMUX_GPIO_B1_04_INDEX, /* GPIO2 Pin 20 */ + IMXRT_PADMUX_GPIO_B1_05_INDEX, /* GPIO2 Pin 21 */ + IMXRT_PADMUX_GPIO_B1_06_INDEX, /* GPIO2 Pin 22 */ + IMXRT_PADMUX_GPIO_B1_07_INDEX, /* GPIO2 Pin 23 */ + + IMXRT_PADMUX_GPIO_B1_08_INDEX, /* GPIO2 Pin 24 */ + IMXRT_PADMUX_GPIO_B1_09_INDEX, /* GPIO2 Pin 25 */ + IMXRT_PADMUX_GPIO_B1_10_INDEX, /* GPIO2 Pin 26 */ + IMXRT_PADMUX_GPIO_B1_11_INDEX, /* GPIO2 Pin 27 */ + IMXRT_PADMUX_GPIO_B1_12_INDEX, /* GPIO2 Pin 28 */ + IMXRT_PADMUX_GPIO_B1_13_INDEX, /* GPIO2 Pin 29 */ + IMXRT_PADMUX_GPIO_B1_14_INDEX, /* GPIO2 Pin 30 */ + IMXRT_PADMUX_GPIO_B1_15_INDEX /* GPIO2 Pin 31 */ +}; + +static const uint8_t g_gpio3_padmux[IMXRT_GPIO_NPINS] = +{ + IMXRT_PADMUX_GPIO_SD_B1_00_INDEX, /* GPIO3 Pin 0 */ + IMXRT_PADMUX_GPIO_SD_B1_01_INDEX, /* GPIO3 Pin 1 */ + IMXRT_PADMUX_GPIO_SD_B1_02_INDEX, /* GPIO3 Pin 2 */ + IMXRT_PADMUX_GPIO_SD_B1_03_INDEX, /* GPIO3 Pin 3 */ + IMXRT_PADMUX_GPIO_SD_B1_04_INDEX, /* GPIO3 Pin 4 */ + IMXRT_PADMUX_GPIO_SD_B1_05_INDEX, /* GPIO3 Pin 5 */ + IMXRT_PADMUX_GPIO_SD_B1_06_INDEX, /* GPIO3 Pin 6 */ + IMXRT_PADMUX_GPIO_SD_B1_07_INDEX, /* GPIO3 Pin 7 */ + + IMXRT_PADMUX_GPIO_SD_B1_08_INDEX, /* GPIO3 Pin 8 */ + IMXRT_PADMUX_GPIO_SD_B1_09_INDEX, /* GPIO3 Pin 9 */ + IMXRT_PADMUX_GPIO_SD_B1_10_INDEX, /* GPIO3 Pin 10 */ + IMXRT_PADMUX_GPIO_SD_B1_11_INDEX, /* GPIO3 Pin 11 */ + IMXRT_PADMUX_GPIO_SD_B0_00_INDEX, /* GPIO3 Pin 12 */ + IMXRT_PADMUX_GPIO_SD_B0_01_INDEX, /* GPIO3 Pin 13 */ + IMXRT_PADMUX_GPIO_SD_B0_02_INDEX, /* GPIO3 Pin 14 */ + IMXRT_PADMUX_GPIO_SD_B0_03_INDEX, /* GPIO3 Pin 15 */ + + IMXRT_PADMUX_GPIO_SD_B0_04_INDEX, /* GPIO3 Pin 16 */ + IMXRT_PADMUX_GPIO_SD_B0_05_INDEX, /* GPIO3 Pin 17 */ + IMXRT_PADMUX_GPIO_EMC_32_INDEX, /* GPIO3 Pin 18 */ + IMXRT_PADMUX_GPIO_EMC_33_INDEX, /* GPIO3 Pin 19 */ + IMXRT_PADMUX_GPIO_EMC_34_INDEX, /* GPIO3 Pin 20 */ + IMXRT_PADMUX_GPIO_EMC_35_INDEX, /* GPIO3 Pin 21 */ + IMXRT_PADMUX_GPIO_EMC_36_INDEX, /* GPIO3 Pin 22 */ + IMXRT_PADMUX_GPIO_EMC_37_INDEX, /* GPIO3 Pin 23 */ + + IMXRT_PADMUX_GPIO_EMC_38_INDEX, /* GPIO3 Pin 24 */ + IMXRT_PADMUX_GPIO_EMC_39_INDEX, /* GPIO3 Pin 25 */ + IMXRT_PADMUX_GPIO_EMC_40_INDEX, /* GPIO3 Pin 26 */ + IMXRT_PADMUX_GPIO_EMC_41_INDEX, /* GPIO3 Pin 27 */ + IMXRT_PADMUX_INVALID, /* GPIO3 Pin 28 */ + IMXRT_PADMUX_INVALID, /* GPIO3 Pin 29 */ + IMXRT_PADMUX_INVALID, /* GPIO3 Pin 30 */ + IMXRT_PADMUX_INVALID /* GPIO3 Pin 31 */ +}; + +static const uint8_t g_gpio4_padmux[IMXRT_GPIO_NPINS] = +{ + IMXRT_PADMUX_GPIO_EMC_00_INDEX, /* GPIO4 Pin 0 */ + IMXRT_PADMUX_GPIO_EMC_01_INDEX, /* GPIO4 Pin 1 */ + IMXRT_PADMUX_GPIO_EMC_02_INDEX, /* GPIO4 Pin 2 */ + IMXRT_PADMUX_GPIO_EMC_03_INDEX, /* GPIO4 Pin 3 */ + IMXRT_PADMUX_GPIO_EMC_04_INDEX, /* GPIO4 Pin 4 */ + IMXRT_PADMUX_GPIO_EMC_05_INDEX, /* GPIO4 Pin 5 */ + IMXRT_PADMUX_GPIO_EMC_06_INDEX, /* GPIO4 Pin 6 */ + IMXRT_PADMUX_GPIO_EMC_07_INDEX, /* GPIO4 Pin 7 */ + + IMXRT_PADMUX_GPIO_EMC_08_INDEX, /* GPIO4 Pin 8 */ + IMXRT_PADMUX_GPIO_EMC_09_INDEX, /* GPIO4 Pin 9 */ + IMXRT_PADMUX_GPIO_EMC_10_INDEX, /* GPIO4 Pin 10 */ + IMXRT_PADMUX_GPIO_EMC_11_INDEX, /* GPIO4 Pin 11 */ + IMXRT_PADMUX_GPIO_EMC_12_INDEX, /* GPIO4 Pin 12 */ + IMXRT_PADMUX_GPIO_EMC_13_INDEX, /* GPIO4 Pin 13 */ + IMXRT_PADMUX_GPIO_EMC_14_INDEX, /* GPIO4 Pin 14 */ + IMXRT_PADMUX_GPIO_EMC_15_INDEX, /* GPIO4 Pin 15 */ + + IMXRT_PADMUX_GPIO_EMC_16_INDEX, /* GPIO4 Pin 16 */ + IMXRT_PADMUX_GPIO_EMC_17_INDEX, /* GPIO4 Pin 17 */ + IMXRT_PADMUX_GPIO_EMC_18_INDEX, /* GPIO4 Pin 18 */ + IMXRT_PADMUX_GPIO_EMC_19_INDEX, /* GPIO4 Pin 19 */ + IMXRT_PADMUX_GPIO_EMC_20_INDEX, /* GPIO4 Pin 20 */ + IMXRT_PADMUX_GPIO_EMC_21_INDEX, /* GPIO4 Pin 21 */ + IMXRT_PADMUX_GPIO_EMC_22_INDEX, /* GPIO4 Pin 22 */ + IMXRT_PADMUX_GPIO_EMC_23_INDEX, /* GPIO4 Pin 23 */ + + IMXRT_PADMUX_GPIO_EMC_24_INDEX, /* GPIO4 Pin 24 */ + IMXRT_PADMUX_GPIO_EMC_25_INDEX, /* GPIO4 Pin 25 */ + IMXRT_PADMUX_GPIO_EMC_26_INDEX, /* GPIO4 Pin 26 */ + IMXRT_PADMUX_GPIO_EMC_27_INDEX, /* GPIO4 Pin 27 */ + IMXRT_PADMUX_GPIO_EMC_28_INDEX, /* GPIO4 Pin 28 */ + IMXRT_PADMUX_GPIO_EMC_29_INDEX, /* GPIO4 Pin 29 */ + IMXRT_PADMUX_GPIO_EMC_30_INDEX, /* GPIO4 Pin 30 */ + IMXRT_PADMUX_GPIO_EMC_31_INDEX /* GPIO4 Pin 31 */ +}; + +static FAR const uint8_t *g_gpio_padmux[IMXRT_GPIO_NPORTS + 1] = +{ + g_gpio1_padmux, /* GPIO1 */ + g_gpio2_padmux, /* GPIO2 */ + g_gpio3_padmux, /* GPIO3 */ + g_gpio4_padmux, /* GPIO4 */ + NULL /* End of list */ +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imxrt_gpio_dirout + ****************************************************************************/ + +static inline void imxrt_gpio_dirout(int port, int pin) +{ + uint32_t regval = getreg32(IMXRT_GPIO_GDIR(port)); + regval |= GPIO_PIN(pin); + putreg32(regval, IMXRT_GPIO_GDIR(port)); +} + +/**************************************************************************** + * Name: imxrt_gpio_dirin + ****************************************************************************/ + +static inline void imxrt_gpio_dirin(int port, int pin) +{ + uint32_t regval = getreg32(IMXRT_GPIO_GDIR(port)); + regval &= ~GPIO_PIN(pin); + putreg32(regval, IMXRT_GPIO_GDIR(port)); +} + +/**************************************************************************** + * Name: imxrt_gpio_setoutput + ****************************************************************************/ + +static void imxrt_gpio_setoutput(int port, int pin, bool value) +{ + uintptr_t regaddr = IMXRT_GPIO_DR(port); + uint32_t regval; + + regval = getreg32(regaddr); + if (value) + { + regval |= GPIO_PIN(pin); + } + else + { + regval &= ~GPIO_PIN(pin); + } + + putreg32(regval, regaddr); +} + +/**************************************************************************** + * Name: imxrt_gpio_getinput + ****************************************************************************/ + +static inline bool imxrt_gpio_getinput(int port, int pin) +{ + uintptr_t regaddr = IMXRT_GPIO_DR(port); + uint32_t regval; + + regval = getreg32(regaddr); + return ((regval & GPIO_PIN(pin)) != 0); +} + +/**************************************************************************** + * Name: imxrt_gpio_configinput + ****************************************************************************/ + +static int imxrt_gpio_configinput(gpio_pinset_t pinset) +{ + int port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + int pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + FAR const uint8_t *table; + iomux_pinset_t ioset; + uintptr_t regaddr; + unsigned int index; + + /* Configure pin as in input */ + + imxrt_gpio_dirin(port, pin); + + /* Configure pin as a GPIO */ + + table = g_gpio_padmux[port]; + if (table == NULL) + { + return -EINVAL; + } + + index = (unsigned int)table[pin]; + if (index >= IMXRT_PADMUX_NREGISTERS) + { + return -EINVAL; + } + + regaddr = IMXRT_PADMUX_ADDRESS(index); + putreg32(PADMUX_MUXMODE_ALT5, regaddr); + + /* Configure pin pad settings */ + + index = imxrt_padmux_map(index); + if (index >= IMXRT_PADCTL_NREGISTERS) + { + return -EINVAL; + } + + regaddr = IMXRT_PADCTL_ADDRESS(index); + ioset = (iomux_pinset_t)((pinset & GPIO_IOMUX_MASK) >> GPIO_IOMUX_SHIFT); + return imxrt_iomux_configure(regaddr, ioset); +} + +/**************************************************************************** + * Name: imxrt_gpio_configoutput + ****************************************************************************/ + +static inline int imxrt_gpio_configoutput(gpio_pinset_t pinset) +{ + int port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + int pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + bool value = ((pinset & GPIO_OUTPUT_ONE) != 0); + + /* Set the output value */ + + imxrt_gpio_setoutput(port, pin, value); + + /* Convert the configured input GPIO to an output */ + + imxrt_gpio_dirout(port, pin); + return OK; +} + +/**************************************************************************** + * Name: imxrt_gpio_configperiph + ****************************************************************************/ + +static inline int imxrt_gpio_configperiph(gpio_pinset_t pinset) +{ + iomux_pinset_t ioset; + uintptr_t regaddr; + uint32_t regval; + uint32_t value; + unsigned int index; + + /* Configure pin as a peripheral */ + + index = ((pinset & GPIO_PADMUX_MASK) >> GPIO_PADMUX_SHIFT); + regaddr = IMXRT_PADMUX_ADDRESS(index); + + value = ((pinset & GPIO_ALT_MASK) >> GPIO_ALT_SHIFT); + regval = (value << PADMUX_MUXMODE_SHIFT); + + putreg32(regval, regaddr); + + /* Configure pin pad settings */ + + index = imxrt_padmux_map(index); + if (index >= IMXRT_PADCTL_NREGISTERS) + { + return -EINVAL; + } + + regaddr = IMXRT_PADCTL_ADDRESS(index); + ioset = (iomux_pinset_t)((pinset & GPIO_IOMUX_MASK) >> GPIO_IOMUX_SHIFT); + return imxrt_iomux_configure(regaddr, ioset); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imxrt_config_gpio + * + * Description: + * Configure a GPIO pin based on pin-encoded description of the pin. + * + ****************************************************************************/ + +int imxrt_config_gpio(gpio_pinset_t pinset) +{ + irqstate_t flags; + int ret; + + /* Configure the pin as an input initially to avoid any spurious outputs */ + + flags = enter_critical_section(); + + /* Configure based upon the pin mode */ + + switch (pinset & GPIO_MODE_MASK) + { + case GPIO_INPUT: + { + /* Configure the pin as a GPIO input */ + + ret = imxrt_gpio_configinput(pinset); + } + break; + + case GPIO_OUTPUT: + { + /* First configure the pin as a GPIO input to avoid output + * glitches. + */ + + ret = imxrt_gpio_configinput(pinset); + if (ret >= 0) + { + /* Convert the input to an output */ + + ret = imxrt_gpio_configoutput(pinset); + } + } + break; + + case GPIO_PERIPH: + { + /* Configure the pin as a peripheral */ + + ret = imxrt_gpio_configperiph(pinset); + } + break; + +#ifdef CONFIG_IMXRT_GPIO_IRQ + case GPIO_INTERRUPT: + { + /* Configure the pin as a GPIO input */ + + ret = imxrt_gpio_configinput(pinset); + if (ret == OK) + { + ret = imxrt_gpioirq_configure(pinset); + } + } + break; +#endif + + default: + ret = -EINVAL; + break; + } + + leave_critical_section(flags); + return ret; +} + +/************************************************************************************ + * Name: imxrt_gpio_write + * + * Description: + * Write one or zero to the selected GPIO pin + * + ************************************************************************************/ + +void imxrt_gpio_write(gpio_pinset_t pinset, bool value) +{ + irqstate_t flags; + int port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + int pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + + flags = enter_critical_section(); + imxrt_gpio_setoutput(port, pin, value); + leave_critical_section(flags); +} + +/************************************************************************************ + * Name: imxrt_gpio_read + * + * Description: + * Read one or zero from the selected GPIO pin + * + ************************************************************************************/ + +bool imxrt_gpio_read(gpio_pinset_t pinset) +{ + irqstate_t flags; + int port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + int pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + bool value; + + flags = enter_critical_section(); + value = imxrt_gpio_getinput(port, pin); + leave_critical_section(flags); + return value; +} diff --git a/arch/arm/src/imxrt/imxrt_gpio.h b/arch/arm/src/imxrt/imxrt_gpio.h new file mode 100644 index 00000000000..e6a736f32b5 --- /dev/null +++ b/arch/arm/src/imxrt/imxrt_gpio.h @@ -0,0 +1,311 @@ +/************************************************************************************ + * arch/arm/src/imxrt/imxrt_gpio.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMXRT_IMXRT_GPIO_H +#define __ARCH_ARM_SRC_IMXRT_IMXRT_GPIO_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include +#include + +#include "chip/imxrt_gpio.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ +/* 32-bit Encoding: + * + * ENCODING IIXX XXXX XXXX XXXX MMMM MMMM MMMM MMMM + * GPIO INPUT 00.. ..EE .GGP PPPP MMMM MMMM MMMM MMMM + * GPIO OUTPUT 01V. .... .GGP PPPP MMMM MMMM MMMM MMMM + * PERIPHERAL 10AA A... IIII IIII MMMM MMMM MMMM MMMM + */ + +/* Input/Output Selection: + * + * ENCODING II.. .... .... .... .... .... .... .... + */ + +#define GPIO_MODE_SHIFT (30) /* Bits 30-31: Pin mode */ +#define GPIO_MODE_MASK (3 << GPIO_MODE_SHIFT) +# define GPIO_INPUT (0 << GPIO_MODE_SHIFT) /* GPIO input */ +# define GPIO_OUTPUT (1 << GPIO_MODE_SHIFT) /* GPIO output */ +# define GPIO_PERIPH (2 << GPIO_MODE_SHIFT) /* Peripheral */ +# define GPIO_INTERRUPT (3 << GPIO_MODE_SHIFT) /* Interrupt input */ + +/* Initial Ouptut Value: + * + * GPIO OUTPUT 01V. .... .... .... .... .... .... .... + */ + +#define GPIO_OUTPUT_ZERO (0) /* Bit 29: 0=Initial output is low */ +#define GPIO_OUTPUT_ONE (1 << 29) /* Bit 29: 1=Initial output is high */ + +/* GPIO Port Number + * + * GPIO INPUT 00.. .... .GG. .... .... .... .... .... + * GPIO OUTPUT 01.. .... .GG. .... .... .... .... .... + */ + +#define GPIO_PORT_SHIFT (21) /* Bits 21-23: GPIO port index */ +#define GPIO_PORT_MASK (3 << GPIO_PORT_SHIFT) +# define GPIO_PORT1 (0 << GPIO_PORT_SHIFT) /* GPIO1 */ +# define GPIO_PORT2 (1 << GPIO_PORT_SHIFT) /* GPIO2 */ +# define GPIO_PORT3 (2 << GPIO_PORT_SHIFT) /* GPIO3 */ +# define GPIO_PORT4 (3 << GPIO_PORT_SHIFT) /* GPIO4 */ + +/* GPIO Pin Number: + * + * GPIO INPUT 00.. .... ...P PPPP .... .... .... .... + * GPIO OUTPUT 01.. .... ...P PPPP .... .... .... .... + */ + +#define GPIO_PIN_SHIFT (16) /* Bits 16-20: GPIO pin number */ +#define GPIO_PIN_MASK (15 << GPIO_PIN_SHIFT) +# define GPIO_PIN0 (0 << GPIO_PIN_SHIFT) /* Pin 0 */ +# define GPIO_PIN1 (1 << GPIO_PIN_SHIFT) /* Pin 1 */ +# define GPIO_PIN2 (2 << GPIO_PIN_SHIFT) /* Pin 2 */ +# define GPIO_PIN3 (3 << GPIO_PIN_SHIFT) /* Pin 3 */ +# define GPIO_PIN4 (4 << GPIO_PIN_SHIFT) /* Pin 4 */ +# define GPIO_PIN5 (5 << GPIO_PIN_SHIFT) /* Pin 5 */ +# define GPIO_PIN6 (6 << GPIO_PIN_SHIFT) /* Pin 6 */ +# define GPIO_PIN7 (7 << GPIO_PIN_SHIFT) /* Pin 7 */ +# define GPIO_PIN8 (8 << GPIO_PIN_SHIFT) /* Pin 8 */ +# define GPIO_PIN9 (9 << GPIO_PIN_SHIFT) /* Pin 9 */ +# define GPIO_PIN10 (10 << GPIO_PIN_SHIFT) /* Pin 10 */ +# define GPIO_PIN11 (11 << GPIO_PIN_SHIFT) /* Pin 11 */ +# define GPIO_PIN12 (12 << GPIO_PIN_SHIFT) /* Pin 12 */ +# define GPIO_PIN13 (13 << GPIO_PIN_SHIFT) /* Pin 13 */ +# define GPIO_PIN14 (14 << GPIO_PIN_SHIFT) /* Pin 14 */ +# define GPIO_PIN15 (15 << GPIO_PIN_SHIFT) /* Pin 15 */ +# define GPIO_PIN16 (16 << GPIO_PIN_SHIFT) /* Pin 16 */ +# define GPIO_PIN17 (17 << GPIO_PIN_SHIFT) /* Pin 17 */ +# define GPIO_PIN18 (18 << GPIO_PIN_SHIFT) /* Pin 18 */ +# define GPIO_PIN19 (19 << GPIO_PIN_SHIFT) /* Pin 19 */ +# define GPIO_PIN20 (20 << GPIO_PIN_SHIFT) /* Pin 20 */ +# define GPIO_PIN21 (21 << GPIO_PIN_SHIFT) /* Pin 21 */ +# define GPIO_PIN22 (22 << GPIO_PIN_SHIFT) /* Pin 22 */ +# define GPIO_PIN23 (23 << GPIO_PIN_SHIFT) /* Pin 23 */ +# define GPIO_PIN24 (24 << GPIO_PIN_SHIFT) /* Pin 24 */ +# define GPIO_PIN25 (25 << GPIO_PIN_SHIFT) /* Pin 25 */ +# define GPIO_PIN26 (26 << GPIO_PIN_SHIFT) /* Pin 26 */ +# define GPIO_PIN27 (27 << GPIO_PIN_SHIFT) /* Pin 27 */ +# define GPIO_PIN28 (28 << GPIO_PIN_SHIFT) /* Pin 28 */ +# define GPIO_PIN29 (29 << GPIO_PIN_SHIFT) /* Pin 29 */ +# define GPIO_PIN30 (30 << GPIO_PIN_SHIFT) /* Pin 30 */ +# define GPIO_PIN31 (31 << GPIO_PIN_SHIFT) /* Pin 31 */ + +/* Peripheral Alternate Function: + * + * PERIPHERAL 10AA A... .... .... MMMM MMMM MMMM MMMM + */ + +#define GPIO_ALT_SHIFT (27) /* Bits 27-29: Peripheral alternate function */ +#define GPIO_ALT_MASK (15 << GPIO_ALT_SHIFT) +# define GPIO_ALT0 (0 << GPIO_ALT_SHIFT) /* Alternate function 1 */ +# define GPIO_ALT1 (1 << GPIO_ALT_SHIFT) /* Alternate function 2 */ +# define GPIO_ALT2 (2 << GPIO_ALT_SHIFT) /* Alternate function 3 */ +# define GPIO_ALT3 (3 << GPIO_ALT_SHIFT) /* Alternate function 4 */ +# define GPIO_ALT4 (4 << GPIO_ALT_SHIFT) /* Alternate function 5 */ + /* Alternate function 5 is GPIO */ +# define GPIO_ALT6 (6 << GPIO_ALT_SHIFT) /* Alternate function 1 */ +# define GPIO_ALT7 (7 << GPIO_ALT_SHIFT) /* Alternate function 1 */ + +/* Interrupt edge/level configuration + * + * GPIO INPUT ... ..EE .... .... .... .... .... .... + */ + +#define GPIO_INTCFG_SHIFT (24) /* Bits 24-25: Interrupt edge/level configuration */ +#define GPIO_INTCFG_MASK (3 << GPIO_INTCFG_SHIFT) +# define GPIO_INT_LOWLEVEL (GPIO_ICR_LOWLEVEL << GPIO_INTCFG_SHIFT) +# define GPIO_INT_HIGHLEVEL (GPIO_ICR_HIGHLEVEL << GPIO_INTCFG_SHIFT) +# define GPIO_INT_RISINGEDGE (GPIO_ICR_RISINGEDGE << GPIO_INTCFG_SHIFT) +# define GPIO_INT_FALLINGEDGE (GPIO_ICR_FALLINGEDGE << GPIO_INTCFG_SHIFT) + +/* Pad Mux Register Index: + * + * PERIPHERAL .... .... IIII IIII .... .... .... .... + */ + +#define GPIO_PADMUX_SHIFT (16) /* Bits 16-23: Peripheral alternate function */ +#define GPIO_PADMUX_MASK (0xff << GPIO_PADMUX_SHIFT) +# define GPIO_PADMUX(n) ((uint32_t)(n) << GPIO_PADMUX_SHIFT) + +/* IOMUX Pin Configuration: + * + * ENCODING .... .... .... .... MMMM MMMM MMMM MMMM + * + * See imxrt_iomuxc.h for detailed content. + */ + +#define GPIO_IOMUX_SHIFT (0) /* Bits 9-15: IOMUX pin configuration */ +#define GPIO_IOMUX_MASK (0xffff << GPIO_IOMUX_SHIFT) + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/* The smallest integer type that can hold the GPIO encoding */ + +typedef uint32_t gpio_pinset_t; + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +/************************************************************************************ + * Name: imxrt_gpioirq_initialize + * + * Description: + * Initialize logic to support a second level of interrupt decoding for GPIO pins. + * + ************************************************************************************/ + +#ifdef CONFIG_IMXRT_GPIO_IRQ +void imxrt_gpioirq_initialize(void); +#else +# define imxrt_gpioirq_initialize() +#endif + +/************************************************************************************ + * Name: imxrt_config_gpio + * + * Description: + * Configure a GPIO pin based on bit-encoded description of the pin. + * + ************************************************************************************/ + +int imxrt_config_gpio(gpio_pinset_t pinset); + +/************************************************************************************ + * Name: imxrt_gpio_write + * + * Description: + * Write one or zero to the selected GPIO pin + * + ************************************************************************************/ + +void imxrt_gpio_write(gpio_pinset_t pinset, bool value); + +/************************************************************************************ + * Name: imxrt_gpio_read + * + * Description: + * Read one or zero from the selected GPIO pin + * + ************************************************************************************/ + +bool imxrt_gpio_read(gpio_pinset_t pinset); + +/************************************************************************************ + * Name: imxrt_gpioirq_configure + * + * Description: + * Configure an interrupt for the specified GPIO pin. + * + ************************************************************************************/ + +#ifdef CONFIG_IMXRT_GPIO_IRQ +int imxrt_gpioirq_configure(gpio_pinset_t pinset); +#else +# define imxrt_gpioirq_configure(pinset) +#endif + +/************************************************************************************ + * Name: imxrt_gpioirq_enable + * + * Description: + * Enable the interrupt for specified GPIO IRQ + * + ************************************************************************************/ + +#ifdef CONFIG_IMXRT_GPIO_IRQ +int imxrt_gpioirq_enable(int irq); +#else +# define imxrt_gpioirq_enable(irq) +#endif + +/************************************************************************************ + * Name: imxrt_gpioirq_disable + * + * Description: + * Disable the interrupt for specified GPIO IRQ + * + ************************************************************************************/ + +#ifdef CONFIG_IMXRT_GPIO_IRQ +int imxrt_gpioirq_disable(int irq); +#else +# define imxrt_gpioirq_disable(irq) +#endif + +/************************************************************************************ + * Function: imxrt_dump_gpio + * + * Description: + * Dump all GPIO registers associated with the base address of the provided pinset. + * + ************************************************************************************/ + +#ifdef CONFIG_DEBUG_GPIO_INFO +int imxrt_dump_gpio(uint32_t pinset, const char *msg); +#else +# define imxrt_dumpgpio(p,m) +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif +#endif /* __ARCH_ARM_SRC_IMXRT_IMXRT_GPIO_H */ diff --git a/arch/arm/src/imxrt/imxrt_gpioirq.c b/arch/arm/src/imxrt/imxrt_gpioirq.c new file mode 100644 index 00000000000..804076c655d --- /dev/null +++ b/arch/arm/src/imxrt/imxrt_gpioirq.c @@ -0,0 +1,630 @@ +/**************************************************************************** + * arch/arm/src/imxrt/imxrt_gpioirq.c + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "up_arch.h" + +#include "imxrt_config.h" +#include "imxrt_irq.h" +#include "imxrt_gpio.h" + +#ifdef CONFIG_IMXRT_GPIO_IRQ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imxrt_gpio_info + * + * Description: + * Given an IRQ number, provide the register and bit setting to enable or + * disable the irq. + * + ****************************************************************************/ + +static int imxrt_gpio_info(int irq, uintptr_t *regaddr, unsigned int *pin) +{ + DEBUGASSERT(irq >= IMXRT_GPIO_IRQ_FIRST && irq < IMXRT_GPIO_IRQ_LAST); + +#ifdef CONFIG_IMXRT_GPIO1_0_15_IRQ + if (irq < _IMXRT_GPIO1_16_31_BASE) + { + *regaddr = IMXRT_GPIO1_IMR; + *pin = irq - _IMXRT_GPIO1_0_15_BASE; + } + else +#endif +#ifdef CONFIG_IMXRT_GPIO1_16_31_IRQ + if (irq < _IMXRT_GPIO2_0_15_BASE) + { + *regaddr = IMXRT_GPIO1_IMR; + *pin = irq - _IMXRT_GPIO1_16_31_BASE + 16; + } + else +#endif + +#ifdef CONFIG_IMXRT_GPIO2_0_15_IRQ + if (irq < _IMXRT_GPIO2_16_31_BASE) + { + *regaddr = IMXRT_GPIO2_IMR; + *pin = irq - _IMXRT_GPIO2_0_15_BASE; + } + else +#endif +#ifdef CONFIG_IMXRT_GPIO2_16_31_IRQ + if (irq < _IMXRT_GPIO3_0_15_BASE) + { + *regaddr = IMXRT_GPIO2_IMR; + *pin = irq - _IMXRT_GPIO2_16_31_BASE + 16; + } + else +#endif + +#ifdef CONFIG_IMXRT_GPIO3_0_15_IRQ + if (irq < _IMXRT_GPIO3_16_31_BASE) + { + *regaddr = IMXRT_GPIO3_IMR; + *pin = irq - _IMXRT_GPIO3_0_15_BASE; + } + else +#endif +#ifdef CONFIG_IMXRT_GPIO3_16_31_IRQ + if (irq < _IMXRT_GPIO4_0_15_BASE) + { + *regaddr = IMXRT_GPIO3_IMR; + *pin = irq - _IMXRT_GPIO3_16_31_BASE + 16; + } + else +#endif + +#ifdef CONFIG_IMXRT_GPIO4_0_15_IRQ + if (irq < _IMXRT_GPIO4_16_31_BASE) + { + *regaddr = IMXRT_GPIO4_IMR; + *pin = irq - _IMXRT_GPIO4_0_15_BASE; + } + else +#endif +#ifdef CONFIG_IMXRT_GPIO4_0_15_IRQ + if (irq < IMXRT_GPIO_IRQ_LAST) + { + *regaddr = IMXRT_GPIO4_IMR; + *pin = irq - _IMXRT_GPIO4_16_31_BASE + 16; + } + else +#endif + { + return -EINVAL; + } + + return OK; +} + +/**************************************************************************** + * Name: imxrt_gpioN_A_B_interrupt + * + * Description: + * GPIO interrupt handlers. + * + ****************************************************************************/ + +#ifdef CONFIG_IMXRT_GPIO1_0_15_IRQ +static int imxrt_gpio1_0_15_interrupt(int irq, FAR void *context, + FAR void *arg) +{ + uint32_t status; + int irq; + int bit; + + /* Get the pending interrupt indications */ + + status = getreg32(IMXRT_GPIO1_ISR) & 0x0000fffff; + + /* Decode the pending interrupts */ + + for (bit = 0, irq = _IMXRT_GPIO1_0_15_BASE; + bit < 16 && status != 0; + bit++, irq++) + { + /* Is the IRQ associate with this pin pending? */ + + uint32_t mask = (1 << bit); + if ((status & mask) != 0) + { + /* Yes, clear the status bit and dispatch the interrupt */ + + putreg32(mask, IMXRT_GPIO1_ISR) + status &= ~mask; + + irq_dispath(irq, context); + } + } + + return OK; +} +#endif + +#ifdef CONFIG_IMXRT_GPIO1_16_31_IRQ +static int imxrt_gpio1_16_31_interrupt(int irq, FAR void *context, FAR void *arg) +{ + uint32_t status; + int irq; + int bit; + + /* Get the pending interrupt indications */ + + status = getreg32(IMXRT_GPIO1_ISR) & 0xffff0000; + + /* Decode the pending interrupts */ + + for (bit = 16, irq = _IMXRT_GPIO1_16_31_BASE; + bit < 32 && status != 0; + bit++, irq++) + { + /* Is the IRQ associate with this pin pending? */ + + uint32_t mask = (1 << bit); + if ((status & mask) != 0) + { + /* Yes, clear the status bit and dispatch the interrupt */ + + putreg32(mask, IMXRT_GPIO1_ISR) + status &= ~mask; + + irq_dispath(irq, context); + } + } + + return OK; +} +#endif + +#ifdef CONFIG_IMXRT_GPIO2_0_15_IRQ +static int imxrt_gpio2_0_15_interrupt(int irq, FAR void *context, FAR void *arg) +{ + uint32_t status; + int irq; + int bit; + + /* Get the pending interrupt indications */ + + status = getreg32(IMXRT_GPIO2_ISR) & 0x0000fffff; + + /* Decode the pending interrupts */ + + for (bit = 0, irq = _IMXRT_GPIO2_0_15_BASE; + bit < 16 && status != 0; + bit++, irq++) + { + /* Is the IRQ associate with this pin pending? */ + + uint32_t mask = (1 << bit); + if ((status & mask) != 0) + { + /* Yes, clear the status bit and dispatch the interrupt */ + + putreg32(mask, IMXRT_GPIO2_ISR) + status &= ~mask; + + irq_dispath(irq, context); + } + } + + return OK; +} +#endif + +#ifdef CONFIG_IMXRT_GPIO2_16_31_IRQ +static int imxrt_gpio2_16_31_interrupt(int irq, FAR void *context, FAR void *arg) +{ +static int imxrt_gpio1_16_31_interrupt(int irq, FAR void *context, FAR void *arg) +{ + uint32_t status; + int irq; + int bit; + + /* Get the pending interrupt indications */ + + status = getreg32(IMXRT_GPIO2_ISR) & 0xffff0000; + + /* Decode the pending interrupts */ + + for (bit = 16, irq = _IMXRT_GPIO2_16_31_BASE; + bit < 32 && status != 0; + bit++, irq++) + { + /* Is the IRQ associate with this pin pending? */ + + uint32_t mask = (1 << bit); + if ((status & mask) != 0) + { + /* Yes, clear the status bit and dispatch the interrupt */ + + putreg32(mask, IMXRT_GPIO2_ISR) + status &= ~mask; + + irq_dispath(irq, context); + } + } + + return OK; +} +#endif + +#ifdef CONFIG_IMXRT_GPIO3_0_15_IRQ +static int imxrt_gpio3_0_15_interrupt(int irq, FAR void *context, FAR void *arg) +{ + uint32_t status; + int irq; + int bit; + + /* Get the pending interrupt indications */ + + status = getreg32(IMXRT_GPIO3_ISR) & 0x0000fffff; + + /* Decode the pending interrupts */ + + for (bit = 0, irq = _IMXRT_GPIO3_0_15_BASE; + bit < 16 && status != 0; + bit++, irq++) + { + /* Is the IRQ associate with this pin pending? */ + + uint32_t mask = (1 << bit); + if ((status & mask) != 0) + { + /* Yes, clear the status bit and dispatch the interrupt */ + + putreg32(mask, IMXRT_GPIO3_ISR) + status &= ~mask; + + irq_dispath(irq, context); + } + } + + return OK; +} +#endif + +#ifdef CONFIG_IMXRT_GPIO3_16_31_IRQ +static int imxrt_gpio3_16_31_interrupt(int irq, FAR void *context, FAR void *arg) +{ +static int imxrt_gpio1_16_31_interrupt(int irq, FAR void *context, FAR void *arg) +{ + uint32_t status; + int irq; + int bit; + + /* Get the pending interrupt indications */ + + status = getreg32(IMXRT_GPIO3_ISR) & 0xffff0000; + + /* Decode the pending interrupts */ + + for (bit = 16, irq = _IMXRT_GPIO3_16_31_BASE; + bit < 32 && status != 0; + bit++, irq++) + { + /* Is the IRQ associate with this pin pending? */ + + uint32_t mask = (1 << bit); + if ((status & mask) != 0) + { + /* Yes, clear the status bit and dispatch the interrupt */ + + putreg32(mask, IMXRT_GPIO3_ISR) + status &= ~mask; + + irq_dispath(irq, context); + } + } + + return OK; +} +#endif + +#ifdef CONFIG_IMXRT_GPIO4_0_15_IRQ +static int imxrt_gpio4_0_15_interrupt(int irq, FAR void *context, FAR void *arg) +{ + uint32_t status; + int irq; + int bit; + + /* Get the pending interrupt indications */ + + status = getreg32(IMXRT_GPIO4_ISR) & 0x0000fffff; + + /* Decode the pending interrupts */ + + for (bit = 0, irq = _IMXRT_GPIO4_0_15_BASE; + bit < 16 && status != 0; + bit++, irq++) + { + /* Is the IRQ associate with this pin pending? */ + + uint32_t mask = (1 << bit); + if ((status & mask) != 0) + { + /* Yes, clear the status bit and dispatch the interrupt */ + + putreg32(mask, IMXRT_GPIO4_ISR) + status &= ~mask; + + irq_dispath(irq, context); + } + } + + return OK; +} +#endif + +#ifdef CONFIG_IMXRT_GPIO4_16_31_IRQ +static int imxrt_gpio4_16_31_interrupt(int irq, FAR void *context, FAR void *arg) +{ +static int imxrt_gpio1_16_31_interrupt(int irq, FAR void *context, FAR void *arg) +{ + uint32_t status; + int irq; + int bit; + + /* Get the pending interrupt indications */ + + status = getreg32(IMXRT_GPIO4_ISR) & 0xffff0000; + + /* Decode the pending interrupts */ + + for (bit = 16, irq = _IMXRT_GPIO4_16_31_BASE; + bit < 32 && status != 0; + bit++, irq++) + { + /* Is the IRQ associate with this pin pending? */ + + uint32_t mask = (1 << bit); + if ((status & mask) != 0) + { + /* Yes, clear the status bit and dispatch the interrupt */ + + putreg32(mask, IMXRT_GPIO4_ISR) + status &= ~mask; + + irq_dispath(irq, context); + } + } + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/************************************************************************************ + * Name: imxrt_gpioirq_initialize + * + * Description: + * Initialize logic to support a second level of interrupt decoding for GPIO pins. + * + ************************************************************************************/ + +void imxrt_gpioirq_initialize(void) +{ + /* Disable all GPIO interrupts at the source */ + + putreg32(0, IMXRT_GPIO1_IMR); + putreg32(0, IMXRT_GPIO2_IMR); + putreg32(0, IMXRT_GPIO3_IMR); + putreg32(0, IMXRT_GPIO4_IMR); + + /* Disable all unconfigured GPIO interrupts at the NVIC */ + +#ifndef CONFIG_IMXRT_GPIO1_0_15_IRQ + up_disable_irq(IMXRT_IRQ_GPIO1_0_15); +#endif +#ifndef CONFIG_IMXRT_GPIO1_16_31_IRQ + up_disable_irq(IMXRT_IRQ_GPIO1_16_31); +#endif +#ifndef CONFIG_IMXRT_GPIO2_0_15_IRQ + up_disable_irq(IMXRT_IRQ_GPIO2_0_15); +#endif +#ifndef CONFIG_IMXRT_GPIO2_16_31_IRQ + up_disable_irq(IMXRT_IRQ_GPIO2_16_31); +#endif +#ifndef CONFIG_IMXRT_GPIO3_0_15_IRQ + up_disable_irq(IMXRT_IRQ_GPIO3_0_15); +#endif +#ifndef CONFIG_IMXRT_GPIO3_16_31_IRQ + up_disable_irq(IMXRT_IRQ_GPIO3_16_31); +#endif +#ifndef CONFIG_IMXRT_GPIO4_0_15_IRQ + up_disable_irq(IMXRT_IRQ_GPIO4_0_15); +#endif +#ifndef CONFIG_IMXRT_GPIO4_16_31_IRQ + up_disable_irq(IMXRT_IRQ_GPIO4_16_31); +#endif + + /* Attach all configured GPIO interrupts and enable the interrupt at the + * NVIC + */ + +#ifdef CONFIG_IMXRT_GPIO1_0_15_IRQ + DEBUGVERIFY(irq_attach(imxrt_gpio1_0_15_interrupt, + IMXRT_IRQ_GPIO1_0_15, NULL)); + up_enable_irq(IMXRT_IRQ_GPIO1_0_15); +#endif + +#ifdef CONFIG_IMXRT_GPIO1_16_31_IRQ + DEBUGVERIFY(irq_attach(imxrt_gpio1_16_31_interrupt, + IMXRT_IRQ_GPIO1_16_31, NULL)); + up_enable_irq(IMXRT_IRQ_GPIO1_16_31); +#endif + +#ifdef CONFIG_IMXRT_GPIO2_0_15_IRQ + DEBUGVERIFY(irq_attach(imxrt_gpio2_0_15_interrupt, + IMXRT_IRQ_GPIO2_0_15, NULL)); + up_enable_irq(IMXRT_IRQ_GPIO2_0_15); +#endif + +#ifdef CONFIG_IMXRT_GPIO2_16_31_IRQ + DEBUGVERIFY(irq_attach(imxrt_gpio2_16_31_interrupt, + IMXRT_IRQ_GPIO2_16_31, NULL)); + up_enable_irq(IMXRT_IRQ_GPIO2_16_31); +#endif + +#ifdef CONFIG_IMXRT_GPIO3_0_15_IRQ + DEBUGVERIFY(irq_attach(imxrt_gpio3_0_15_interrupt, + IMXRT_IRQ_GPIO3_0_15, NULL)); + up_enable_irq(IMXRT_IRQ_GPIO3_0_15); +#endif + +#ifdef CONFIG_IMXRT_GPIO3_16_31_IRQ + DEBUGVERIFY(irq_attach(imxrt_gpio3_16_31_interrupt, + IMXRT_IRQ_GPIO3_16_31, NULL)); + up_enable_irq(IMXRT_IRQ_GPIO3_16_31); +#endif + +#ifdef CONFIG_IMXRT_GPIO4_0_15_IRQ + DEBUGVERIFY(irq_attach(imxrt_gpio4_0_15_interrupt, + IMXRT_IRQ_GPIO4_0_15, NULL)); + up_enable_irq(IMXRT_IRQ_GPIO4_0_15); +#endif + +#ifdef CONFIG_IMXRT_GPIO4_0_15_IRQ + DEBUGVERIFY(irq_attach(imxrt_gpio4_16_31_interrupt, + IMXRT_IRQ_GPIO4_16_31, NULL)); + up_enable_irq(IMXRT_IRQ_GPIO4_16_31); +#endif +} + +/************************************************************************************ + * Name: imxrt_gpioirq_configure + * + * Description: + * Configure an interrupt for the specified GPIO pin. + * + ************************************************************************************/ + +int imxrt_gpioirq_configure(gpio_pinset_t pinset) +{ + unsigned int port; + unsigned int pin; + uintptr_t regaddr; + uint32_t regval; + uint32_t icr; + + /* Decode information in the pin configuration */ + + port = ((unsigned int)pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + pin = ((unsigned int)pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + icr = ((uint32_t)pinset & GPIO_INTCFG_MASK) >> GPIO_INTCFG_SHIFT; + + /* Set the right field in the right ICR register */ + + regaddr = pin < 16 ? IMXRT_GPIO_ICR1(port) : IMXRT_GPIO_ICR2(port); + regval = getreg32(regaddr); + regval &= ~GPIO_ICR_MASK(pin); + regval |= GPIO_ICR(icr, pin); + putreg32(regval, regaddr); + + return OK; +} + +/************************************************************************************ + * Name: imxrt_gpioirq_enable + * + * Description: + * Enable the interrupt for specified GPIO IRQ + * + ************************************************************************************/ + +int imxrt_gpioirq_enable(int irq) +{ + uintptr_t regaddr; + unsigned int pin; + uint32_t regval; + int ret; + + ret = imxrt_gpio_info(irq, ®addr, &pin); + if (ret >= 0) + { + regval = getreg32(regaddr); + regval |= (1 << pin); + putreg32(regval, regaddr); + } + + return ret; +} + +/************************************************************************************ + * Name: imxrt_gpioirq_disable + * + * Description: + * Disable the interrupt for specified GPIO IRQ + * + ************************************************************************************/ + +int imxrt_gpioirq_disable(int irq) +{ + uintptr_t regaddr; + unsigned int pin; + uint32_t regval; + int ret; + + ret = imxrt_gpio_info(irq, ®addr, &pin); + if (ret >= 0) + { + regval = getreg32(regaddr); + regval &= ~(1 << pin); + putreg32(regval, regaddr); + } + + return ret; +} + +#endif /* CONFIG_IMXRT_GPIO_IRQ */ diff --git a/arch/arm/src/imxrt/imxrt_idle.c b/arch/arm/src/imxrt/imxrt_idle.c new file mode 100644 index 00000000000..445dd202f8c --- /dev/null +++ b/arch/arm/src/imxrt/imxrt_idle.c @@ -0,0 +1,188 @@ +/**************************************************************************** + * arch/arm/src/imxrt/imxrt_idle.c + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Ivan Ucherdzhiev + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include +#include +#include + +#include + +#include "chip.h" +#include "up_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Does the board support an IDLE LED to indicate that the board is in the + * IDLE state? + */ + +#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE) +# define BEGIN_IDLE() board_autoled_on(LED_IDLE) +# define END_IDLE() board_autoled_off(LED_IDLE) +#else +# define BEGIN_IDLE() +# define END_IDLE() +#endif + +#define PM_IDLE_DOMAIN 0 /* Revisit */ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_idlepm + * + * Description: + * Perform IDLE state power management. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static void up_idlepm(void) +{ + static enum pm_state_e oldstate = PM_NORMAL; + enum pm_state_e newstate; + irqstate_t flags; + int ret; + + /* Decide, which power saving level can be obtained */ + + newstate = pm_checkstate(PM_IDLE_DOMAIN); + + /* Check for state changes */ + + if (newstate != oldstate) + { + flags = enter_critical_section(); + + /* Perform board-specific, state-dependent logic here */ + + pwrinfo("newstate= %d oldstate=%d\n", newstate, oldstate); + + /* Then force the global state change */ + + ret = pm_changestate(PM_IDLE_DOMAIN, newstate); + if (ret < 0) + { + /* The new state change failed, revert to the preceding state */ + + (void)pm_changestate(PM_IDLE_DOMAIN, oldstate); + } + else + { + /* Save the new state */ + + oldstate = newstate; + } + + /* MCU-specific power management logic */ + + switch (newstate) + { + case PM_NORMAL: + break; + + case PM_IDLE: + break; + + case PM_STANDBY: + imxrt_pmstop(true); + break; + + case PM_SLEEP: + (void)imxrt_pmstandby(); + break; + + default: + break; + } + + leave_critical_section(flags); + } +} +#else +# define up_idlepm() +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_idle + * + * Description: + * up_idle() is the logic that will be executed when their is no other + * ready-to-run task. This is processor idle time and will continue until + * some interrupt occurs to cause a context switch from the idle task. + * + * Processing in this state may be processor-specific. e.g., this is where + * power management operations might be performed. + * + ****************************************************************************/ + +void up_idle(void) +{ +#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS) + /* If the system is idle and there are no timer interrupts, then process + * "fake" timer interrupts. Hopefully, something will wake up. + */ + + sched_process_timer(); +#else + + /* Perform IDLE mode power management */ + + up_idlepm(); + +#if 0 /* REVISIT */ + /* Sleep until an interrupt occurs to save power. */ + + BEGIN_IDLE(); + asm("WFI"); + END_IDLE(); +#endif +#endif +} diff --git a/arch/arm/src/imxrt/imxrt_iomuxc.c b/arch/arm/src/imxrt/imxrt_iomuxc.c new file mode 100644 index 00000000000..2b4ec4cdf8e --- /dev/null +++ b/arch/arm/src/imxrt/imxrt_iomuxc.c @@ -0,0 +1,298 @@ +/**************************************************************************** + * arch/arm/src/imxrt/imxrt_irq.c + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include + +#include +#include +#include + +#include "up_arch.h" +#include "chip/imxrt_ccm.h" +#include "imxrt_iomuxc.h" + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This table is indexed by the Pad Mux register index and provides the index + * to the corresponding Pad Control register. + * + * REVISIT: This could be greatly simplified: The Pad Control registers + * map 1-to-1 with the Pad Mux registers except for two regions where + * there are no corresponding Pad Mux registers. The entire table could be + * replaced to two range checks and the appropriate offset added to the Pad + * Mux Register index. + */ + +static const uint8_t g_mux2ctl_map[IMXRT_PADMUX_NREGISTERS] = +{ + /* The first mappings are simple 1-to-1 mappings. This may be a little wasteful */ + + IMXRT_PADCTL_GPIO_EMC_00_INDEX, + IMXRT_PADCTL_GPIO_EMC_01_INDEX, + IMXRT_PADCTL_GPIO_EMC_02_INDEX, + IMXRT_PADCTL_GPIO_EMC_03_INDEX, + IMXRT_PADCTL_GPIO_EMC_04_INDEX, + IMXRT_PADCTL_GPIO_EMC_05_INDEX, + IMXRT_PADCTL_GPIO_EMC_06_INDEX, + IMXRT_PADCTL_GPIO_EMC_07_INDEX, + IMXRT_PADCTL_GPIO_EMC_08_INDEX, + IMXRT_PADCTL_GPIO_EMC_09_INDEX, + IMXRT_PADCTL_GPIO_EMC_10_INDEX, + IMXRT_PADCTL_GPIO_EMC_11_INDEX, + IMXRT_PADCTL_GPIO_EMC_12_INDEX, + IMXRT_PADCTL_GPIO_EMC_13_INDEX, + IMXRT_PADCTL_GPIO_EMC_14_INDEX, + IMXRT_PADCTL_GPIO_EMC_15_INDEX, + IMXRT_PADCTL_GPIO_EMC_16_INDEX, + IMXRT_PADCTL_GPIO_EMC_17_INDEX, + IMXRT_PADCTL_GPIO_EMC_18_INDEX, + IMXRT_PADCTL_GPIO_EMC_19_INDEX, + IMXRT_PADCTL_GPIO_EMC_20_INDEX, + IMXRT_PADCTL_GPIO_EMC_21_INDEX, + IMXRT_PADCTL_GPIO_EMC_22_INDEX, + IMXRT_PADCTL_GPIO_EMC_23_INDEX, + IMXRT_PADCTL_GPIO_EMC_24_INDEX, + IMXRT_PADCTL_GPIO_EMC_25_INDEX, + IMXRT_PADCTL_GPIO_EMC_26_INDEX, + IMXRT_PADCTL_GPIO_EMC_27_INDEX, + IMXRT_PADCTL_GPIO_EMC_28_INDEX, + IMXRT_PADCTL_GPIO_EMC_29_INDEX, + IMXRT_PADCTL_GPIO_EMC_30_INDEX, + IMXRT_PADCTL_GPIO_EMC_31_INDEX, + IMXRT_PADCTL_GPIO_EMC_32_INDEX, + IMXRT_PADCTL_GPIO_EMC_33_INDEX, + IMXRT_PADCTL_GPIO_EMC_34_INDEX, + IMXRT_PADCTL_GPIO_EMC_35_INDEX, + IMXRT_PADCTL_GPIO_EMC_36_INDEX, + IMXRT_PADCTL_GPIO_EMC_37_INDEX, + IMXRT_PADCTL_GPIO_EMC_38_INDEX, + IMXRT_PADCTL_GPIO_EMC_39_INDEX, + IMXRT_PADCTL_GPIO_EMC_40_INDEX, + IMXRT_PADCTL_GPIO_EMC_41_INDEX, + IMXRT_PADCTL_GPIO_AD_B0_00_INDEX, + IMXRT_PADCTL_GPIO_AD_B0_01_INDEX, + IMXRT_PADCTL_GPIO_AD_B0_02_INDEX, + IMXRT_PADCTL_GPIO_AD_B0_03_INDEX, + IMXRT_PADCTL_GPIO_AD_B0_04_INDEX, + IMXRT_PADCTL_GPIO_AD_B0_05_INDEX, + IMXRT_PADCTL_GPIO_AD_B0_06_INDEX, + IMXRT_PADCTL_GPIO_AD_B0_07_INDEX, + IMXRT_PADCTL_GPIO_AD_B0_08_INDEX, + IMXRT_PADCTL_GPIO_AD_B0_09_INDEX, + IMXRT_PADCTL_GPIO_AD_B0_10_INDEX, + IMXRT_PADCTL_GPIO_AD_B0_11_INDEX, + IMXRT_PADCTL_GPIO_AD_B0_12_INDEX, + IMXRT_PADCTL_GPIO_AD_B0_13_INDEX, + IMXRT_PADCTL_GPIO_AD_B0_14_INDEX, + IMXRT_PADCTL_GPIO_AD_B0_15_INDEX, + IMXRT_PADCTL_GPIO_AD_B1_00_INDEX, + IMXRT_PADCTL_GPIO_AD_B1_01_INDEX, + IMXRT_PADCTL_GPIO_AD_B1_02_INDEX, + IMXRT_PADCTL_GPIO_AD_B1_03_INDEX, + IMXRT_PADCTL_GPIO_AD_B1_04_INDEX, + IMXRT_PADCTL_GPIO_AD_B1_05_INDEX, + IMXRT_PADCTL_GPIO_AD_B1_06_INDEX, + IMXRT_PADCTL_GPIO_AD_B1_07_INDEX, + IMXRT_PADCTL_GPIO_AD_B1_08_INDEX, + IMXRT_PADCTL_GPIO_AD_B1_09_INDEX, + IMXRT_PADCTL_GPIO_AD_B1_10_INDEX, + IMXRT_PADCTL_GPIO_AD_B1_11_INDEX, + IMXRT_PADCTL_GPIO_AD_B1_12_INDEX, + IMXRT_PADCTL_GPIO_AD_B1_13_INDEX, + IMXRT_PADCTL_GPIO_AD_B1_14_INDEX, + IMXRT_PADCTL_GPIO_AD_B1_15_INDEX, + IMXRT_PADCTL_GPIO_B0_00_INDEX, + IMXRT_PADCTL_GPIO_B0_01_INDEX, + IMXRT_PADCTL_GPIO_B0_02_INDEX, + IMXRT_PADCTL_GPIO_B0_03_INDEX, + IMXRT_PADCTL_GPIO_B0_04_INDEX, + IMXRT_PADCTL_GPIO_B0_05_INDEX, + IMXRT_PADCTL_GPIO_B0_06_INDEX, + IMXRT_PADCTL_GPIO_B0_07_INDEX, + IMXRT_PADCTL_GPIO_B0_08_INDEX, + IMXRT_PADCTL_GPIO_B0_09_INDEX, + IMXRT_PADCTL_GPIO_B0_10_INDEX, + IMXRT_PADCTL_GPIO_B0_11_INDEX, + IMXRT_PADCTL_GPIO_B0_12_INDEX, + IMXRT_PADCTL_GPIO_B0_13_INDEX, + IMXRT_PADCTL_GPIO_B0_14_INDEX, + IMXRT_PADCTL_GPIO_B0_15_INDEX, + IMXRT_PADCTL_GPIO_B1_00_INDEX, + IMXRT_PADCTL_GPIO_B1_01_INDEX, + IMXRT_PADCTL_GPIO_B1_02_INDEX, + IMXRT_PADCTL_GPIO_B1_03_INDEX, + IMXRT_PADCTL_GPIO_B1_04_INDEX, + IMXRT_PADCTL_GPIO_B1_05_INDEX, + IMXRT_PADCTL_GPIO_B1_06_INDEX, + IMXRT_PADCTL_GPIO_B1_07_INDEX, + IMXRT_PADCTL_GPIO_B1_08_INDEX, + IMXRT_PADCTL_GPIO_B1_09_INDEX, + IMXRT_PADCTL_GPIO_B1_10_INDEX, + IMXRT_PADCTL_GPIO_B1_11_INDEX, + IMXRT_PADCTL_GPIO_B1_12_INDEX, + IMXRT_PADCTL_GPIO_B1_13_INDEX, + IMXRT_PADCTL_GPIO_B1_14_INDEX, + IMXRT_PADCTL_GPIO_B1_15_INDEX, + IMXRT_PADCTL_GPIO_SD_B0_00_INDEX, + IMXRT_PADCTL_GPIO_SD_B0_01_INDEX, + IMXRT_PADCTL_GPIO_SD_B0_02_INDEX, + IMXRT_PADCTL_GPIO_SD_B0_03_INDEX, + IMXRT_PADCTL_GPIO_SD_B0_04_INDEX, + IMXRT_PADCTL_GPIO_SD_B0_05_INDEX, + IMXRT_PADCTL_GPIO_SD_B1_00_INDEX, + IMXRT_PADCTL_GPIO_SD_B1_01_INDEX, + IMXRT_PADCTL_GPIO_SD_B1_02_INDEX, + IMXRT_PADCTL_GPIO_SD_B1_03_INDEX, + IMXRT_PADCTL_GPIO_SD_B1_04_INDEX, + IMXRT_PADCTL_GPIO_SD_B1_05_INDEX, + IMXRT_PADCTL_GPIO_SD_B1_06_INDEX, + IMXRT_PADCTL_GPIO_SD_B1_07_INDEX, + IMXRT_PADCTL_GPIO_SD_B1_08_INDEX, + IMXRT_PADCTL_GPIO_SD_B1_09_INDEX, + IMXRT_PADCTL_GPIO_SD_B1_10_INDEX, + IMXRT_PADCTL_GPIO_SD_B1_11_INDEX +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imxrt_padmux_map + * + * Description: + * This function map a Pad Mux register index to the corresponding Pad + * Control register index. + * + ****************************************************************************/ + +unsigned int imxrt_padmux_map(unsigned int padmux) +{ + DEBUGASSERT(padmux < IMX_PADMUX_NREGISTERS); + return (unsigned int)g_mux2ctl_map[padmux]; +} + +/**************************************************************************** + * Name: imxrt_iomux_configure + * + * Description: + * This function writes the encoded pad configuration to the Pad Control + * register. + * + ****************************************************************************/ + +int imxrt_iomux_configure(uintptr_t padctl, iomux_pinset_t ioset) +{ + uint32_t regval = 0; + uint32_t value; + + /* Enable IOMUXC clock if it is not enabled*/ + + regval = getreg32(IMXRT_CCM_CCGR2); + if ((regval & CCM_CCGRX_CG2_MASK) == 0) + { + putreg32(CCM_CG_ALL << CCM_CCGRX_CG2_SHIFT, IMXRT_CCM_CCGR2); + } + + /* Select CMOS input or Schmitt Trigger input */ + + if ((ioset & IOMUX_SCHMITT_TRIGGER) != 0) + { + regval |= PADCTL_SRE; + } + + /* Select drive strength */ + + value = (ioset & IOMUX_DRIVE_MASK) >> IOMUX_DRIVE_SHIFT; + regval |= PADCTL_DSE(value); + + /* Select spped */ + + value = (ioset & IOMUX_SPEED_MASK) >> IOMUX_SPEED_SHIFT; + regval |= PADCTL_SPEED(value); + + /* Select CMOS output or Open Drain outpout */ + + if ((ioset & IOMUX_OPENDRAIN) != 0) + { + regval |= PADCTL_ODE; + } + + /* Handle pull/keep selection */ + + switch (ioset & _IOMUX_PULLTYPE_MASK) + { + default: + case _IOMUX_PULL_NONE: + break; + + case _IOMUX_PULL_KEEP: + { + regval |= PADCTL_PKE; + } + break; + + case _IOMUX_PULL_ENABLE: + { + regval |= (PADCTL_PKE | PADCTL_PUE); + + value = (ioset & _IOMUX_PULLDESC_MASK) >> _IOMUX_PULLDESC_SHIFT; + regval |= PADCTL_PUS(value); + } + break; + } + + /* Select slow/fast slew rate */ + + if ((ioset & IOMUX_SLEW_FAST) != 0) + { + regval |= PADCTL_HYS; + } + + /* Write the result to the specified Pad Control register */ + + putreg32(regval, padctl); + return OK; +} diff --git a/arch/arm/src/imxrt/imxrt_iomuxc.h b/arch/arm/src/imxrt/imxrt_iomuxc.h new file mode 100644 index 00000000000..2bb9df9bf80 --- /dev/null +++ b/arch/arm/src/imxrt/imxrt_iomuxc.h @@ -0,0 +1,170 @@ +/**************************************************************************** + * arch/arm/src/imxrt/imxrt_iomuxc.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMXRT_IMX_IOMUXC_H +#define __ARCH_ARM_SRC_IMXRT_IMX_IOMUXC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "chip/imxrt_iomuxc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* 16-bit Encoding: + * + * .... RRRR ODDD LSST + */ + +/* Output Pull Up/Down: + * + * .... RRRR .... .... + */ + +#define _IOMUX_PULLTYPE_SHIFT (8) /* Bits 8-9: Pull up/down type */ +#define _IOMUX_PULLTYPE_MASK (3 << _IOMUX_PULLTYPE_SHIFT) +# define _IOMUX_PULL_NONE (0 << _IOMUX_PULLTYPE_SHIFT) /* Pull/keeper disabled */ +# define _IOMUX_PULL_KEEP (1 << _IOMUX_PULLTYPE_SHIFT) /* Output determined by keeper */ +# define _IOMUX_PULL_ENABLE (2 << _IOMUX_PULLTYPE_SHIFT) /* Output pulled up or down */ + +#define _IOMUX_PULLDESC_SHIFT (10) /* Bits 10-11: Pull up/down description */ +#define _IOMUX_PULLDESC_MASK (3 << _IOMUX_PULLDESC_SHIFT) +# define _IOMUX_PULL_UP_22K (PULL_UP_22K << _IOMUX_PULLDESC_SHIFT) /* Pull up with 22 KOhm resister */ +# define _IOMUX_PULL_UP_47K (PULL_UP_47K << _IOMUX_PULLDESC_SHIFT) /* Pull up with 47 KOhm resister */ +# define _IOMUX_PULL_UP_100K (PULL_UP_100K << _IOMUX_PULLDESC_SHIFT) /* Pull up with 100 KOhm resister */ +# define _IOMUX_PULL_DOWN_100K (PULL_DOWN_100K << _IOMUX_PULLDESC_SHIFT) /* Pull down with 100 KOhm resister */ + +#define IOMUX_PULL_SHIFT (8) /* Bits 8-11: Pull up/down selection */ +#define IOMUX_PULL_MASK (15 << IOMUX_PULL_SHIFT) +# define IOMUX_PULL_NONE _IOMUX_PULL_NONE +# define IOMUX_PULL_KEEP _IOMUX_PULL_KEEP +# define IOMUX_PULL_UP_22K (_IOMUX_PULL_ENABLE | _IOMUX_PULL_UP_22K) +# define IOMUX_PULL_UP_47K (_IOMUX_PULL_ENABLE | _IOMUX_PULL_UP_47K) +# define IOMUX_PULL_UP_100K (_IOMUX_PULL_ENABLE | _IOMUX_PULL_UP_100K) +# define IOMUX_PULL_DOWN_100K (_IOMUX_PULL_ENABLE | _IOMUX_PULL_DOWN_100K) + +/* Open Drain Output: + * + * .... .... O... .... + */ + +#define IOMUX_CMOS_OUTPUT (0) /* Bit 7: 0=CMOS output */ +#define IOMUX_OPENDRAIN (1 << 7) /* Bit 7: 1=Enable open-drain output */ + +/* Output Drive Strength: + * + * .... .... .DDD .... + */ + +#define IOMUX_DRIVE_SHIFT (4) /* Bits 4-6: Output Drive Strength */ +#define IOMUX_DRIVE_MASK (7 << IOMUX_DRIVE_SHIFT) +# define IOMUX_DRIVE_HIZ (DRIVE_HIZ << IOMUX_DRIVE_SHIFT) /* HI-Z */ +# define IOMUX_DRIVE_260OHM (DRIVE_260OHM << IOMUX_DRIVE_SHIFT) /* 150 Ohm @3.3V, 260 Ohm @1.8V */ +# define IOMUX_DRIVE_130OHM (DRIVE_130OHM << IOMUX_DRIVE_SHIFT) /* 75 Ohm @3.3V, 130 Ohm @1.8V */ +# define IOMUX_DRIVE_90OHM (DRIVE_90OHM << IOMUX_DRIVE_SHIFT) /* 50 Ohm @3.3V, 90 Ohm @1.8V */ +# define IOMUX_DRIVE_60OHM (DRIVE_60OHM << IOMUX_DRIVE_SHIFT) /* 37 Ohm @3.3V, 60 Ohm @1.8V */ +# define IOMUX_DRIVE_50OHM (DRIVE_50OHM << IOMUX_DRIVE_SHIFT) /* 30 Ohm @3.3V, 50 Ohm @1.8V */ +# define IOMUX_DRIVE_40OHM (DRIVE_40OHM << IOMUX_DRIVE_SHIFT) /* 25 Ohm @3.3V, 40 Ohm @1.8V */ +# define IOMUX_DRIVE_33OHM (DRIVE_33OHM << IOMUX_DRIVE_SHIFT) /* 20 Ohm @3.3V, 33 Ohm @1.8V */ + +/* Output Slew Rate: + * + * .... .... .... L... + */ + +#define IOMUX_SLEW_SLOW (0) /* Bit 3: 0=Slow Slew Rate */ +#define IOMUX_SLEW_FAST (1 << 3) /* Bit 3: 1=Fast Slew Rate */ + +/* Output Speed: + * + * .... .... .... .SS. + */ + +#define IOMUX_SPEED_SHIFT (2) /* Bits 2-3: Speed */ +#define IOMUX_SPEED_MASK (3 << IOMUX_SPEED_SHIFT) +# define IOMUX_SPEED_LOW (SPEED_LOW << IOMUX_SPEED_SHIFT) /* Low frequency (50 MHz) */ +# define IOMUX_SPEED_MEDIUM (SPEED_MEDIUM << IOMUX_SPEED_SHIFT) /* Medium frequency (100, 150 MHz) */ +# define IOMUX_SPEED_MAX (SPEED_MAX << IOMUX_SPEED_SHIFT) /* Maximum frequency (100, 150, 200 MHz) */ + +/* Input Schmitt Trigger: + * + * .... .... .... ...T + */ + +#define IOMUX_CMOS_INPUT (0) /* Bit 0: 0=CMOS input */ +#define IOMUX_SCHMITT_TRIGGER (1 << 0) /* Bit 0: 1=Enable Schmitt trigger if input */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + + /* The smallest integer type that can hold the IOMUX encoding */ + +typedef uint16_t iomux_pinset_t; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: imxrt_padmux_map + * + * Description: + * This function map a Pad Mux register index to the corresponding Pad + * Control register index. + * + ****************************************************************************/ + +unsigned int imxrt_padmux_map(unsigned int padmux); + +/**************************************************************************** + * Name: imxrt_iomux_configure + * + * Description: + * This function writes the encoded pad configuration to the Pad Control + * register. + * + ****************************************************************************/ + +int imxrt_iomux_configure(uintptr_t padctl, iomux_pinset_t ioset); + +#endif /* __ARCH_ARM_SRC_IMXRT_IMX_IOMUXC_H */ diff --git a/arch/arm/src/imxrt/imxrt_irq.c b/arch/arm/src/imxrt/imxrt_irq.c new file mode 100644 index 00000000000..ffb146a0882 --- /dev/null +++ b/arch/arm/src/imxrt/imxrt_irq.c @@ -0,0 +1,676 @@ +/**************************************************************************** + * arch/arm/src/imxrt/imxrt_irq.c + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "nvic.h" +#include "ram_vectors.h" +#include "up_arch.h" +#include "up_internal.h" + +#ifdef CONFIG_IMXRT_GPIO_IRQ +# include "imxrt_gpio.h" +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Get a 32-bit version of the default priority */ + +#define DEFPRIORITY32 \ + (NVIC_SYSH_PRIORITY_DEFAULT << 24 | \ + NVIC_SYSH_PRIORITY_DEFAULT << 16 | \ + NVIC_SYSH_PRIORITY_DEFAULT << 8 | \ + NVIC_SYSH_PRIORITY_DEFAULT) + +/* Given the address of a NVIC ENABLE register, this is the offset to + * the corresponding CLEAR ENABLE register. + */ + +#define NVIC_ENA_OFFSET (0) +#define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE) + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* g_current_regs[] holds a references to the current interrupt level + * register storage structure. If is non-NULL only during interrupt + * processing. Access to g_current_regs[] must be through the macro + * CURRENT_REGS for portability. + */ + +volatile uint32_t *g_current_regs[1]; + +/* This is the address of the exception vector table (determined by the + * linker script). + */ + +extern uint32_t _vectors[]; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imxrt_dumpnvic + * + * Description: + * Dump some interesting NVIC registers + * + ****************************************************************************/ + +#if defined(CONFIG_DEBUG_IRQ_INFO) +static void imxrt_dumpnvic(const char *msg, int irq) +{ + irqstate_t flags; + + flags = enter_critical_section(); + + irqinfo("NVIC (%s, irq=%d):\n", msg, irq); + irqinfo(" INTCTRL: %08x VECTAB: %08x\n", + getreg32(NVIC_INTCTRL), getreg32(NVIC_VECTAB)); +#if 0 + irqinfo(" SYSH ENABLE MEMFAULT: %08x BUSFAULT: %08x USGFAULT: %08x SYSTICK: %08x\n", + getreg32(NVIC_SYSHCON_MEMFAULTENA), getreg32(NVIC_SYSHCON_BUSFAULTENA), + getreg32(NVIC_SYSHCON_USGFAULTENA), getreg32(NVIC_SYSTICK_CTRL_ENABLE)); +#endif + irqinfo(" IRQ ENABLE: %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ0_31_ENABLE), getreg32(NVIC_IRQ32_63_ENABLE), + getreg32(NVIC_IRQ64_95_ENABLE), getreg32(NVIC_IRQ96_127_ENABLE)); +#if IMXRT_IRQ_NEXTINT > 128 + irqinfo(" %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ128_159_ENABLE), getreg32(NVIC_IRQ160_191_ENABLE), + getreg32(NVIC_IRQ192_223_ENABLE), getreg32(NVIC_IRQ224_239_ENABLE)); +#endif + irqinfo(" SYSH_PRIO: %08x %08x %08x\n", + getreg32(NVIC_SYSH4_7_PRIORITY), getreg32(NVIC_SYSH8_11_PRIORITY), + getreg32(NVIC_SYSH12_15_PRIORITY)); + irqinfo(" IRQ PRIO: %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ0_3_PRIORITY), getreg32(NVIC_IRQ4_7_PRIORITY), + getreg32(NVIC_IRQ8_11_PRIORITY), getreg32(NVIC_IRQ12_15_PRIORITY)); +#if IMXRT_IRQ_NEXTINT > 16 + irqinfo(" %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ16_19_PRIORITY), getreg32(NVIC_IRQ20_23_PRIORITY), + getreg32(NVIC_IRQ24_27_PRIORITY), getreg32(NVIC_IRQ28_31_PRIORITY)); +#endif +#if IMXRT_IRQ_NEXTINT > 32 + irqinfo(" %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ32_35_PRIORITY), getreg32(NVIC_IRQ36_39_PRIORITY), + getreg32(NVIC_IRQ40_43_PRIORITY), getreg32(NVIC_IRQ44_47_PRIORITY)); +#endif +#if IMXRT_IRQ_NEXTINT > 48 + irqinfo(" %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ48_51_PRIORITY), getreg32(NVIC_IRQ52_55_PRIORITY), + getreg32(NVIC_IRQ56_59_PRIORITY), getreg32(NVIC_IRQ60_63_PRIORITY)); +#endif +#if IMXRT_IRQ_NEXTINT > 64 + irqinfo(" %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ64_67_PRIORITY), getreg32(NVIC_IRQ68_71_PRIORITY), + getreg32(NVIC_IRQ72_75_PRIORITY), getreg32(NVIC_IRQ76_79_PRIORITY)); +#endif +#if IMXRT_IRQ_NEXTINT > 80 + irqinfo(" %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ80_83_PRIORITY), getreg32(NVIC_IRQ84_87_PRIORITY), + getreg32(NVIC_IRQ88_91_PRIORITY), getreg32(NVIC_IRQ92_95_PRIORITY)); +#endif +#if IMXRT_IRQ_NEXTINT > 96 + irqinfo(" %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ96_99_PRIORITY), getreg32(NVIC_IRQ100_103_PRIORITY), + getreg32(NVIC_IRQ104_107_PRIORITY), getreg32(NVIC_IRQ108_111_PRIORITY)); +#endif +#if IMXRT_IRQ_NEXTINT > 112 + irqinfo(" %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ112_115_PRIORITY), getreg32(NVIC_IRQ116_119_PRIORITY), + getreg32(NVIC_IRQ120_123_PRIORITY), getreg32(NVIC_IRQ124_127_PRIORITY)); +#endif +#if IMXRT_IRQ_NEXTINT > 128 + irqinfo(" %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ128_131_PRIORITY), getreg32(NVIC_IRQ132_135_PRIORITY), + getreg32(NVIC_IRQ136_139_PRIORITY), getreg32(NVIC_IRQ140_143_PRIORITY)); +#endif +#if IMXRT_IRQ_NEXTINT > 144 + irqinfo(" %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ144_147_PRIORITY), getreg32(NVIC_IRQ148_151_PRIORITY), + getreg32(NVIC_IRQ152_155_PRIORITY), getreg32(NVIC_IRQ156_159_PRIORITY)); +#endif +#if IMXRT_IRQ_NEXTINT > 160 +# warning Missing logic +#endif + + leave_critical_section(flags); +} +#else +# define imxrt_dumpnvic(msg, irq) +#endif + +/**************************************************************************** + * Name: imxrt_nmi, imxrt_busfault, imxrt_usagefault, imxrt_pendsv, + * imxrt_dbgmonitor, imxrt_pendsv, imxrt_reserved + * + * Description: + * Handlers for various exceptions. None are handled and all are fatal + * error conditions. The only advantage these provided over the default + * unexpected interrupt handler is that they provide a diagnostic output. + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_FEATURES +static int imxrt_nmi(int irq, FAR void *context, FAR void *arg) +{ + (void)up_irq_save(); + _err("PANIC!!! NMI received\n"); + PANIC(); + return 0; +} + +static int imxrt_busfault(int irq, FAR void *context, FAR void *arg) +{ + (void)up_irq_save(); + _err("PANIC!!! Bus fault received: %08x\n", getreg32(NVIC_CFAULTS)); + PANIC(); + return 0; +} + +static int imxrt_usagefault(int irq, FAR void *context, FAR void *arg) +{ + (void)up_irq_save(); + _err("PANIC!!! Usage fault received: %08x\n", getreg32(NVIC_CFAULTS)); + PANIC(); + return 0; +} + +static int imxrt_pendsv(int irq, FAR void *context, FAR void *arg) +{ + (void)up_irq_save(); + _err("PANIC!!! PendSV received\n"); + PANIC(); + return 0; +} + +static int imxrt_dbgmonitor(int irq, FAR void *context, FAR void *arg) +{ + (void)up_irq_save(); + _err("PANIC!!! Debug Monitor received\n"); + PANIC(); + return 0; +} + +static int imxrt_reserved(int irq, FAR void *context, FAR void *arg) +{ + (void)up_irq_save(); + _err("PANIC!!! Reserved interrupt\n"); + PANIC(); + return 0; +} +#endif + +/**************************************************************************** + * Name: imxrt_prioritize_syscall + * + * Description: + * Set the priority of an exception. This function may be needed + * internally even if support for prioritized interrupts is not enabled. + * + ****************************************************************************/ + +#ifdef CONFIG_ARMV7M_USEBASEPRI +static inline void imxrt_prioritize_syscall(int priority) +{ + uint32_t regval; + + /* SVCALL is system handler 11 */ + + regval = getreg32(NVIC_SYSH8_11_PRIORITY); + regval &= ~NVIC_SYSH_PRIORITY_PR11_MASK; + regval |= (priority << NVIC_SYSH_PRIORITY_PR11_SHIFT); + putreg32(regval, NVIC_SYSH8_11_PRIORITY); +} +#endif + +/**************************************************************************** + * Name: imxrt_irqinfo + * + * Description: + * Given an IRQ number, provide the register and bit setting to enable or + * disable the irq. + * + ****************************************************************************/ + +static int imxrt_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, + uintptr_t offset) +{ + unsigned int extint = irq - IMXRT_IRQ_EXTINT; + + DEBUGASSERT(irq >= IMXRT_IRQ_NMI && irq < NR_IRQS); + + /* Check for external interrupt */ + + if (irq >= IMXRT_IRQ_EXTINT) + { + if (extint < IMXRT_IRQ_NEXTINT) + { + *regaddr = (NVIC_IRQ0_31_ENABLE + offset); + *bit = 1 << extint; + } + else +#if IMXRT_IRQ_NEXTINT > 32 + if (extint < 32) + { + *regaddr = (NVIC_IRQ32_63_ENABLE + offset); + *bit = 1 << (extint - 32); + } + else +#endif +#if IMXRT_IRQ_NEXTINT > 64 + if (extint < 96) + { + *regaddr = (NVIC_IRQ64_95_ENABLE + offset); + *bit = 1 << (extint - 64); + } + else +#endif +#if IMXRT_IRQ_NEXTINT > 96 + if (extint < 96) + { + *regaddr = (NVIC_IRQ96_127_ENABLE + offset); + *bit = 1 << (extint - 96); + } + else +#endif +#if IMXRT_IRQ_NEXTINT > 128 + if (extint < 160) + { + *regaddr = (NVIC_IRQ128_159_ENABLE + offset); + *bit = 1 << (extint - 128); + } + else +#endif +#if IMXRT_IRQ_NEXTINT > 160 +# error Missing logic +#endif + { + return ERROR; /* Invalid interrupt */ + } + } + + /* Handle processor exceptions. Only a few can be disabled */ + + else + { + *regaddr = NVIC_SYSHCON; + if (irq == IMXRT_IRQ_MEMFAULT) + { + *bit = NVIC_SYSHCON_MEMFAULTENA; + } + else if (irq == IMXRT_IRQ_BUSFAULT) + { + *bit = NVIC_SYSHCON_BUSFAULTENA; + } + else if (irq == IMXRT_IRQ_USAGEFAULT) + { + *bit = NVIC_SYSHCON_USGFAULTENA; + } + else if (irq == IMXRT_IRQ_SYSTICK) + { + *regaddr = NVIC_SYSTICK_CTRL; + *bit = NVIC_SYSTICK_CTRL_ENABLE; + } + else + { + return ERROR; /* Invalid or unsupported exception */ + } + } + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_irqinitialize + ****************************************************************************/ + +void up_irqinitialize(void) +{ + uintptr_t regaddr; +#if defined(CONFIG_DEBUG_SYMBOLS) && !defined(CONFIG_ARMV7M_USEBASEPRI) + uint32_t regval; +#endif + int nintlines; + int i; + + /* The NVIC ICTR register (bits 0-4) holds the number of of interrupt + * lines that the NVIC supports, defined in groups of 32. That is, + * the total number of interrupt lines is up to (32*(INTLINESNUM+1)). + * + * 0 -> 32 interrupt lines, 1 enable register, 8 priority registers + * 1 -> 64 " " " ", 2 enable registers, 16 priority registers + * 2 -> 96 " " " ", 3 enable registers, 24 priority registers + * ... + */ + + nintlines = (getreg32(NVIC_ICTR) & NVIC_ICTR_INTLINESNUM_MASK) + 1; + + /* Disable all interrupts. There are nintlines interrupt enable + * registers. + */ + + for (i = nintlines, regaddr = NVIC_IRQ0_31_ENABLE; + i > 0; + i--, regaddr += 4) + { + putreg32(0, regaddr); + } + + /* Make sure that we are using the correct vector table. The default + * vector address is 0x0000:0000 but if we are executing code that is + * positioned in SRAM or in external FLASH, then we may need to reset + * the interrupt vector so that it refers to the table in SRAM or in + * external FLASH. + */ + + putreg32((uint32_t)_vectors, NVIC_VECTAB); + +#ifdef CONFIG_ARCH_RAMVECTORS + /* If CONFIG_ARCH_RAMVECTORS is defined, then we are using a RAM-based + * vector table that requires special initialization. + */ + + up_ramvec_initialize(); +#endif + + /* Set all interrupts (and exceptions) to the default priority */ + + putreg32(DEFPRIORITY32, NVIC_SYSH4_7_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_SYSH8_11_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_SYSH12_15_PRIORITY); + + /* Now set all of the interrupt lines to the default priority. There are + * nintlines * 8 priority registers. + */ + + for (i = (nintlines << 3), regaddr = NVIC_IRQ0_3_PRIORITY; + i > 0; + i--, regaddr += 4) + { + putreg32(DEFPRIORITY32, regaddr); + } + + /* currents_regs is non-NULL only while processing an interrupt */ + + CURRENT_REGS = NULL; + + /* Attach the SVCall and Hard Fault exception handlers. The SVCall + * exception is used for performing context switches; The Hard Fault + * must also be caught because a SVCall may show up as a Hard Fault + * under certain conditions. + */ + + irq_attach(IMXRT_IRQ_SVCALL, up_svcall, NULL); + irq_attach(IMXRT_IRQ_HARDFAULT, up_hardfault, NULL); + + /* Set the priority of the SVCall interrupt */ + +#ifdef CONFIG_ARCH_IRQPRIO + /* up_prioritize_irq(IMXRT_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ +#endif +#ifdef CONFIG_ARMV7M_USEBASEPRI + imxrt_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY); +#endif + + /* If the MPU is enabled, then attach and enable the Memory Management + * Fault handler. + */ + +#ifdef CONFIG_ARM_MPU + irq_attach(IMXRT_IRQ_MEMFAULT, up_memfault, NULL); + up_enable_irq(IMXRT_IRQ_MEMFAULT); +#endif + + /* Attach all other processor exceptions (except reset and sys tick) */ + +#ifdef CONFIG_DEBUG_FEATURES + irq_attach(IMXRT_IRQ_NMI, imxrt_nmi, NULL); +#ifndef CONFIG_ARM_MPU + irq_attach(IMXRT_IRQ_MEMFAULT, up_memfault, NULL); +#endif + irq_attach(IMXRT_IRQ_BUSFAULT, imxrt_busfault, NULL); + irq_attach(IMXRT_IRQ_USAGEFAULT, imxrt_usagefault, NULL); + irq_attach(IMXRT_IRQ_PENDSV, imxrt_pendsv, NULL); + irq_attach(IMXRT_IRQ_DBGMONITOR, imxrt_dbgmonitor, NULL); + irq_attach(IMXRT_IRQ_RESERVED, imxrt_reserved, NULL); +#endif + + imxrt_dumpnvic("initial", IMXRT_IRQ_NIRQS); + + /* If a debugger is connected, try to prevent it from catching hardfaults. + * If CONFIG_ARMV7M_USEBASEPRI, no hardfaults are expected in normal + * operation. + */ + +#if defined(CONFIG_DEBUG_SYMBOLS) && !defined(CONFIG_ARMV7M_USEBASEPRI) + regval = getreg32(NVIC_DEMCR); + regval &= ~NVIC_DEMCR_VCHARDERR; + putreg32(regval, NVIC_DEMCR); +#endif + +#ifndef CONFIG_SUPPRESS_INTERRUPTS + /* Initialize logic to support a second level of interrupt decoding for + * GPIO pins. + */ + +#ifdef CONFIG_IMXRT_GPIO_IRQ + imxrt_gpioirq_initialize(); +#endif + + /* And finally, enable interrupts */ + + up_irq_enable(); +#endif +} + +/**************************************************************************** + * Name: up_disable_irq + * + * Description: + * Disable the IRQ specified by 'irq' + * + ****************************************************************************/ + +void up_disable_irq(int irq) +{ + uintptr_t regaddr; + uint32_t regval; + uint32_t bit; + + if (imxrt_irqinfo(irq, ®addr, &bit, NVIC_CLRENA_OFFSET) == 0) + { + /* Modify the appropriate bit in the register to disable the interrupt. + * For normal interrupts, we need to set the bit in the associated + * Interrupt Clear Enable register. For other exceptions, we need to + * clear the bit in the System Handler Control and State Register. + */ + + if (irq >= IMXRT_IRQ_EXTINT) + { + putreg32(bit, regaddr); + } + else + { + regval = getreg32(regaddr); + regval &= ~bit; + putreg32(regval, regaddr); + } + } +#ifdef CONFIG_IMXRT_GPIO_IRQ + else + { + /* Maybe it is a (derived) GPIO IRQ */ + + imxrt_gpioirq_disable(irq); + } +#endif + +#if 0 /* Might be useful in early bring-up */ + imxrt_dumpnvic("disable", irq); +#endif +} + +/**************************************************************************** + * Name: up_enable_irq + * + * Description: + * Enable the IRQ specified by 'irq' + * + ****************************************************************************/ + +void up_enable_irq(int irq) +{ + uintptr_t regaddr; + uint32_t regval; + uint32_t bit; + + if (imxrt_irqinfo(irq, ®addr, &bit, NVIC_ENA_OFFSET) == 0) + { + /* Modify the appropriate bit in the register to enable the interrupt. + * For normal interrupts, we need to set the bit in the associated + * Interrupt Set Enable register. For other exceptions, we need to + * set the bit in the System Handler Control and State Register. + */ + + if (irq >= IMXRT_IRQ_EXTINT) + { + putreg32(bit, regaddr); + } + else + { + regval = getreg32(regaddr); + regval |= bit; + putreg32(regval, regaddr); + } + } +#ifdef CONFIG_IMXRT_GPIO_IRQ + else + { + /* Maybe it is a (derived) GPIO IRQ */ + + imxrt_gpioirq_enable(irq); + } +#endif + +#if 0 /* Might be useful in early bring-up */ + imxrt_dumpnvic("enable", irq); +#endif +} + +/**************************************************************************** + * Name: up_ack_irq + * + * Description: + * Acknowledge the IRQ + * + ****************************************************************************/ + +void up_ack_irq(int irq) +{ +} + +/**************************************************************************** + * Name: up_prioritize_irq + * + * Description: + * Set the priority of an IRQ. + * + * Since this API is not supported on all architectures, it should be + * avoided in common implementations where possible. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQPRIO +int up_prioritize_irq(int irq, int priority) +{ + uint32_t regaddr; + uint32_t regval; + int shift; + + DEBUGASSERT(irq >= IMXRT_IRQ_MEMFAULT && irq < IMXRT_IRQ_NIRQS && + (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN); + + if (irq < IMXRT_IRQ_EXTINT) + { + /* NVIC_SYSH_PRIORITY() maps {0..15} to one of three priority + * registers (0-3 are invalid) + */ + + regaddr = NVIC_SYSH_PRIORITY(irq); + irq -= 4; + } + else + { + /* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */ + + irq -= IMXRT_IRQ_EXTINT; + regaddr = NVIC_IRQ_PRIORITY(irq); + } + + regval = getreg32(regaddr); + shift = ((irq & 3) << 3); + regval &= ~(0xff << shift); + regval |= (priority << shift); + putreg32(regval, regaddr); + + imxrt_dumpnvic("prioritize", irq); + return OK; +} +#endif diff --git a/arch/arm/src/imxrt/imxrt_irq.h b/arch/arm/src/imxrt/imxrt_irq.h new file mode 100644 index 00000000000..60ef594d100 --- /dev/null +++ b/arch/arm/src/imxrt/imxrt_irq.h @@ -0,0 +1,60 @@ +/**************************************************************************** + * arch/arm/src/imxrt/imxrt_irq.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMXRT_IMXRT_IRQ_H +#define __ARCH_ARM_SRC_IMXRT_IMXRT_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imxrt_clrpend + * + * Description: + * Clear a pending interrupt at the NVIC. This does not seem to be + * required for most interrupts. + * + ****************************************************************************/ + +void imxrt_clrpend(int irq); + +#endif /* __ARCH_ARM_SRC_IMXRT_IMXRT_IRQ_H */ diff --git a/arch/arm/src/imxrt/imxrt_lowputc.c b/arch/arm/src/imxrt/imxrt_lowputc.c new file mode 100644 index 00000000000..5c784c4d96c --- /dev/null +++ b/arch/arm/src/imxrt/imxrt_lowputc.c @@ -0,0 +1,572 @@ +/**************************************************************************** + * arch/arm/src/imxrt/imxrt_lowputc.c + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Ivan Ucherdzhiev + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include "up_arch.h" + +#include "chip/imxrt_iomuxc.h" +#include "chip/imxrt_ccm.h" +#include "chip/imxrt_lpuart.h" +#include "imxrt_config.h" +#include "imxrt_iomuxc.h" +#include "imxrt_gpio.h" +#include "imxrt_lowputc.h" + +#include "up_internal.h" + +#include /* Include last: has dependencies */ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifdef HAVE_LPUART_CONSOLE +# if defined(CONFIG_LPUART1_SERIAL_CONSOLE) +# define IMXRT_CONSOLE_BASE IMXRT_LPUART1_BASE +# define IMXRT_CONSOLE_BAUD CONFIG_LPUART1_BAUD +# define IMXRT_CONSOLE_BITS CONFIG_LPUART1_BITS +# define IMXRT_CONSOLE_PARITY CONFIG_LPUART1_PARITY +# define IMXRT_CONSOLE_2STOP CONFIG_LPUART1_2STOP +# elif defined(CONFIG_LPUART2_SERIAL_CONSOLE) +# define IMXRT_CONSOLE_BASE IMXRT_LPUART2_BASE +# define IMXRT_CONSOLE_BAUD CONFIG_LPUART2_BAUD +# define IMXRT_CONSOLE_BITS CONFIG_LPUART2_BITS +# define IMXRT_CONSOLE_PARITY CONFIG_LPUART2_PARITY +# define IMXRT_CONSOLE_2STOP CONFIG_LPUART2_2STOP +# elif defined(CONFIG_LPUART3_SERIAL_CONSOLE) +# define IMXRT_CONSOLE_BASE IMXRT_LPUART3_BASE +# define IMXRT_CONSOLE_BAUD CONFIG_LPUART3_BAUD +# define IMXRT_CONSOLE_BITS CONFIG_LPUART3_BITS +# define IMXRT_CONSOLE_PARITY CONFIG_LPUART3_PARITY +# define IMXRT_CONSOLE_2STOP CONFIG_LPUART3_2STOP +# elif defined(CONFIG_LPUART4_SERIAL_CONSOLE) +# define IMXRT_CONSOLE_BASE IMXRT_LPUART4_BASE +# define IMXRT_CONSOLE_BAUD CONFIG_LPUART4_BAUD +# define IMXRT_CONSOLE_BITS CONFIG_LPUART4_BITS +# define IMXRT_CONSOLE_PARITY CONFIG_LPUART4_PARITY +# define IMXRT_CONSOLE_2STOP CONFIG_LPUART4_2STOP +# elif defined(CONFIG_LPUART5_SERIAL_CONSOLE) +# define IMXRT_CONSOLE_BASE IMXRT_LPUART5_BASE +# define IMXRT_CONSOLE_BAUD CONFIG_LPUART5_BAUD +# define IMXRT_CONSOLE_BITS CONFIG_LPUART5_BITS +# define IMXRT_CONSOLE_PARITY CONFIG_LPUART5_PARITY +# define IMXRT_CONSOLE_2STOP CONFIG_LPUART5_2STOP +# elif defined(CONFIG_LPUART6_SERIAL_CONSOLE) +# define IMXRT_CONSOLE_BASE IMXRT_LPUART6_BASE +# define IMXRT_CONSOLE_BAUD CONFIG_LPUART6_BAUD +# define IMXRT_CONSOLE_BITS CONFIG_LPUART6_BITS +# define IMXRT_CONSOLE_PARITY CONFIG_LPUART6_PARITY +# define IMXRT_CONSOLE_2STOP CONFIG_LPUART6_2STOP +# elif defined(CONFIG_LPUART7_SERIAL_CONSOLE) +# define IMXRT_CONSOLE_BASE IMXRT_LPUART7_BASE +# define IMXRT_CONSOLE_BAUD CONFIG_LPUART7_BAUD +# define IMXRT_CONSOLE_BITS CONFIG_LPUART7_BITS +# define IMXRT_CONSOLE_PARITY CONFIG_LPUART7_PARITY +# define IMXRT_CONSOLE_2STOP CONFIG_LPUART7_2STOP +# elif defined(CONFIG_LPUART8_SERIAL_CONSOLE) +# define IMXRT_CONSOLE_BASE IMXRT_LPUART8_BASE +# define IMXRT_CONSOLE_BAUD CONFIG_LPUART8_BAUD +# define IMXRT_CONSOLE_BITS CONFIG_LPUART8_BITS +# define IMXRT_CONSOLE_PARITY CONFIG_LPUART8_PARITY +# define IMXRT_CONSOLE_2STOP CONFIG_LPUART8_2STOP +# endif +#endif + +/* Clocking *****************************************************************/ +/* the UART module receives two clocks, a peripheral_clock (ipg_clk) and the + * module_clock (ipg_perclk). The peripheral_clock is used as write clock + * of the TxFIFO, read clock of the RxFIFO and synchronization of the modem + * control input pins. It must always be running when UART is enabled. + * + * The default ipg_clk is 66MHz (max 66.5MHz). ipg_clk is gated by + * CCGR5[CG12], uart_clk_enable. ipg_clk is shared among many modules and + * should not be controlled by the UART logic. + * + * The module_clock is for all the state machines, writing RxFIFO, reading + * TxFIFO, etc. It must always be running when UART is sending or receiving + * characters. This clock is used in order to allow frequency scaling on + * peripheral_clock without changing configuration of baud rate. + * + * The default ipg_perclk is 80MHz (max 80MHz). ipg_perclk is gated by + * CCGR5[CG13], uart_serial_clk_enable. The clock generation sequence is: + * + * pll3_sw_clk (480M) -> CCGR5[CG13] -> 3 bit divider cg podf=6 -> + * PLL3_80M (80Mhz) -> CDCDR1: uart_clk_podf -> + * 6 bit divider default=1 -> UART_CLK_ROOT + * + * REVISIT: This logic assumes that all dividers are at the default value + * and that the value of the ipg_perclk is 80MHz. + */ + +#define IPG_PERCLK_FREQUENCY 80000000 + +/* The BRM sub-block receives ref_clk (module_clock clock after divider). + * From this clock, and with integer and non-integer division, BRM generates + * a 16x baud rate clock. + */ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef HAVE_LPUART_CONSOLE +static const struct uart_config_s g_console_config = +{ + .baud = IMXRT_CONSOLE_BAUD, /* Configured baud */ + .parity = IMXRT_CONSOLE_PARITY, /* 0=none, 1=odd, 2=even */ + .bits = IMXRT_CONSOLE_BITS, /* Number of bits (5-9) */ + .stopbits2 = IMXRT_CONSOLE_2STOP, /* true: Configure with 2 stop bits instead of 1 */ +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +void imxrt_lpuart_clock_enable (uint32_t base) +{ + if (base == IMXRT_LPUART1_BASE) + { + putreg32(CCM_CG_ALL << CCM_CCGRX_CG12_SHIFT, IMXRT_CCM_CCGR5); + } + else if (base == IMXRT_LPUART2_BASE) + { + putreg32(CCM_CG_ALL << CCM_CCGRX_CG14_SHIFT, IMXRT_CCM_CCGR0); + } + else if (base == IMXRT_LPUART3_BASE) + { + putreg32(CCM_CG_ALL << CCM_CCGRX_CG6_SHIFT, IMXRT_CCM_CCGR0); + } + else if (base == IMXRT_LPUART4_BASE) + { + putreg32(CCM_CG_ALL << CCM_CCGRX_CG12_SHIFT, IMXRT_CCM_CCGR1); + } + else if (base == IMXRT_LPUART5_BASE) + { + putreg32(CCM_CG_ALL << CCM_CCGRX_CG1_SHIFT, IMXRT_CCM_CCGR3); + } + else if (base == IMXRT_LPUART6_BASE) + { + putreg32(CCM_CG_ALL << CCM_CCGRX_CG4_SHIFT, IMXRT_CCM_CCGR3); + } + else if (base == IMXRT_LPUART7_BASE) + { + putreg32(CCM_CG_ALL << CCM_CCGRX_CG13_SHIFT, IMXRT_CCM_CCGR5); + } + else if (base == IMXRT_LPUART8_BASE) + { + putreg32(CCM_CG_ALL << CCM_CCGRX_CG7_SHIFT, IMXRT_CCM_CCGR6); + } +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imxrt_lowsetup + * + * Description: + * Called at the very beginning of _start. Performs low level + * initialization including setup of the console UART. This UART done + * early so that the serial console is available for debugging very early + * in the boot sequence. + * + ****************************************************************************/ + +void imxrt_lowsetup(void) +{ +#ifndef CONFIG_SUPPRESS_LPUART_CONFIG +#ifdef HAVE_LPUART_DEVICE + +#ifdef CONFIG_IMXRT_LPUART1 + + /* Configure LPUART1 pins: RXD and TXD. Also configure RTS and CTS if flow + * control is enabled. + */ + + (void)imxrt_config_gpio(GPIO_LPUART1_RX_DATA); + (void)imxrt_config_gpio(GPIO_LPUART1_TX_DATA); +#ifdef CONFIG_LPUART1_OFLOWCONTROL + (void)imxrt_config_gpio(GPIO_LPUART1_CTS); +#endif +#ifdef CONFIG_LPUART1_IFLOWCONTROL + (void)imxrt_config_gpio(GPIO_LPUART1_RTS); +#endif +#endif + +#ifdef CONFIG_IMXRT_LPUART2 + + /* Configure LPUART2 pins: RXD and TXD. Also configure RTS and CTS if flow + * control is enabled. + */ + + (void)imxrt_config_gpio(GPIO_LPUART2_RX_DATA); + (void)imxrt_config_gpio(GPIO_LPUART2_TX_DATA); +#ifdef CONFIG_LPUART2_OFLOWCONTROL + (void)imxrt_config_gpio(GPIO_LPUART2_CTS); +#endif +#ifdef CONFIG_LPUART2_IFLOWCONTROL + (void)imxrt_config_gpio(GPIO_LPUART2_RTS); +#endif +#endif + +#ifdef CONFIG_IMXRT_LPUART3 + + /* Configure LPUART3 pins: RXD and TXD. Also configure RTS and CTS if flow + * control is enabled. + */ + + (void)imxrt_config_gpio(GPIO_LPUART3_RX_DATA); + (void)imxrt_config_gpio(GPIO_LPUART3_TX_DATA); +#ifdef CONFIG_LPUART3_OFLOWCONTROL + (void)imxrt_config_gpio(GPIO_LPUART3_CTS); +#endif +#ifdef CONFIG_LPUART3_IFLOWCONTROL + (void)imxrt_config_gpio(GPIO_LPUART3_RTS); +#endif +#endif + +#ifdef CONFIG_IMXRT_LPUART4 + + /* Configure LPUART4 pins: RXD and TXD. Also configure RTS and CTS if flow + * control is enabled. + */ + + (void)imxrt_config_gpio(GPIO_LPUART4_RX_DATA); + (void)imxrt_config_gpio(GPIO_LPUART4_TX_DATA); +#ifdef CONFIG_LPUART4_OFLOWCONTROL + (void)imxrt_config_gpio(GPIO_LPUART4_CTS); +#endif +#ifdef CONFIG_LPUART4_IFLOWCONTROL + (void)imxrt_config_gpio(GPIO_LPUART4_RTS); +#endif +#endif + +#ifdef CONFIG_IMXRT_LPUART5 + + /* Configure LPUART5 pins: RXD and TXD. Also configure RTS and CTS if flow + * control is enabled. + */ + + (void)imxrt_config_gpio(GPIO_LPUART5_RX_DATA); + (void)imxrt_config_gpio(GPIO_LPUART5_TX_DATA); +#ifdef CONFIG_LPUART5_OFLOWCONTROL + (void)imxrt_config_gpio(GPIO_LPUART5_CTS); +#endif +#ifdef CONFIG_LPUART5_IFLOWCONTROL + (void)imxrt_config_gpio(GPIO_LPUART5_RTS); +#endif +#endif + +#ifdef CONFIG_IMXRT_LPUART6 + + /* Configure LPUART6 pins: RXD and TXD. Also configure RTS and CTS if flow + * control is enabled. + */ + + (void)imxrt_config_gpio(GPIO_LPUART6_RX_DATA); + (void)imxrt_config_gpio(GPIO_LPUART6_TX_DATA); +#ifdef CONFIG_LPUART6_OFLOWCONTROL + (void)imxrt_config_gpio(GPIO_LPUART6_CTS); +#endif +#ifdef CONFIG_LPUART6_IFLOWCONTROL + (void)imxrt_config_gpio(GPIO_LPUART6_RTS); +#endif +#endif + +#ifdef CONFIG_IMXRT_LPUART7 + + /* Configure LPUART7 pins: RXD and TXD. Also configure RTS and CTS if flow + * control is enabled. + */ + + (void)imxrt_config_gpio(GPIO_LPUART7_RX_DATA); + (void)imxrt_config_gpio(GPIO_LPUART7_TX_DATA); +#ifdef CONFIG_LPUART7_OFLOWCONTROL + (void)imxrt_config_gpio(GPIO_LPUART7_CTS); +#endif +#ifdef CONFIG_LPUART7_IFLOWCONTROL + (void)imxrt_config_gpio(GPIO_LPUART7_RTS); +#endif +#endif + +#ifdef CONFIG_IMXRT_LPUART8 + + /* Configure LPUART8 pins: RXD and TXD. Also configure RTS and CTS if flow + * control is enabled. + */ + + (void)imxrt_config_gpio(GPIO_LPUART8_RX_DATA); + (void)imxrt_config_gpio(GPIO_LPUART8_TX_DATA); +#ifdef CONFIG_LPUART8_OFLOWCONTROL + (void)imxrt_config_gpio(GPIO_LPUART8_CTS); +#endif +#ifdef CONFIG_LPUART8_IFLOWCONTROL + (void)imxrt_config_gpio(GPIO_LPUART8_RTS); +#endif +#endif + +#ifdef HAVE_LPUART_CONSOLE + /* Configure the serial console for initial, non-interrupt driver mode */ + + (void)imxrt_lpuart_configure(IMXRT_CONSOLE_BASE, &g_console_config); +#endif +#endif /* HAVE_LPUART_DEVICE */ +#endif /* CONFIG_SUPPRESS_LPUART_CONFIG */ +} + +/**************************************************************************** + * Name: imxrt_lpuart_configure + * + * Description: + * Configure a UART for non-interrupt driven operation + * + ****************************************************************************/ + +#ifdef HAVE_LPUART_DEVICE +int imxrt_lpuart_configure(uint32_t base, + FAR const struct uart_config_s *config) +{ + uint32_t src_freq = 0; + uint32_t pll3_div = 0; + uint32_t uart_div = 0; + uint32_t lpuart_freq = 0; + uint16_t sbr; + uint16_t temp_sbr; + uint32_t osr; + uint32_t temp_osr; + uint32_t temp_diff; + uint32_t calculated_baud; + uint32_t baud_diff; + uint32_t regval; + + if ((getreg32(IMXRT_CCM_CSCDR1) & CCM_CSCDR1_UART_CLK_SEL) != 0) + { + src_freq = BOARD_XTAL_FREQUENCY; + } + else + { + if ((getreg32(IMXRT_CCM_ANALOG_PLL_USB1) & + CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK) != 0) + { + pll3_div = 22; + } + else + { + pll3_div = 20; + } + + src_freq = (BOARD_XTAL_FREQUENCY * pll3_div) / 6; + } + + uart_div = (getreg32(IMXRT_CCM_CSCDR1) & CCM_CSCDR1_UART_CLK_PODF_MASK) + 1; + lpuart_freq = src_freq / uart_div; + + /* This LPUART instantiation uses a slightly different baud rate + * calculation. The idea is to use the best OSR (over-sampling rate) + * possible. + * + * NOTE: OSR is typically hard-set to 16 in other LPUART instantiations + * loop to find the best OSR value possible, one that generates minimum + * baud_diff iterate through the rest of the supported values of OSR + */ + + baud_diff = config->baud; + osr = 0; + sbr = 0; + + for (temp_osr = 4; temp_osr <= 32; temp_osr++) + { + /* Calculate the temporary sbr value */ + + temp_sbr = (lpuart_freq / (config->baud * temp_osr)); + + /* Set temp_sbr to 1 if the sourceClockInHz can not satisfy the + * desired baud rate. + */ + + if (temp_sbr == 0) + { + temp_sbr = 1; + } + + /* Calculate the baud rate based on the temporary OSR and SBR values */ + + calculated_baud = (lpuart_freq / (temp_osr * temp_sbr)); + temp_diff = calculated_baud - config->baud; + + /* Select the better value between srb and (sbr + 1) */ + + if (temp_diff > (config->baud - (lpuart_freq / (temp_osr * (temp_sbr + 1))))) + { + temp_diff = config->baud - (lpuart_freq / (temp_osr * (temp_sbr + 1))); + temp_sbr++; + } + + if (temp_diff <= baud_diff) + { + baud_diff = temp_diff; + osr = temp_osr; + sbr = temp_sbr; + } + } + + if (baud_diff > ((config->baud / 100) * 3)) + { + /* Unacceptable baud rate difference of more than 3%*/ + + return ERROR; + } + + /* Enable lpuart clock*/ + + imxrt_lpuart_clock_enable(base); + + /* Reset all internal logic and registers, except the Global Register */ + + regval = getreg32(base + IMXRT_LPUART_GLOBAL_OFFSET); + regval |= LPUART_GLOBAL_RST; + putreg32(regval,base + IMXRT_LPUART_GLOBAL_OFFSET); + + regval &= ~LPUART_GLOBAL_RST; + putreg32(regval,base + IMXRT_LPUART_GLOBAL_OFFSET); + + regval = 0; + + if ((osr > 3) && (osr < 8)) + { + regval |= LPUART_BAUD_BOTHEDGE; + } + + if (config->stopbits2) + { + regval |= LPUART_BAUD_SBNS; + } + + regval |= LPUART_BAUD_OSR(osr) | LPUART_BAUD_SBR(sbr); + putreg32(regval, base + IMXRT_LPUART_BAUD_OFFSET); + + regval = 0; + if (config->parity == 1) + { + regval |= LPUART_CTRL_PE | LPUART_CTRL_PT_ODD; + } + else if (config->parity == 2) + { + regval |= LPUART_CTRL_PE | LPUART_CTRL_PT_EVEN; + } + + if (config->bits == 8) + { + regval &= ~LPUART_CTRL_M; + } + else if (config->bits == 9) + { + regval |= LPUART_CTRL_M; + } + else + { + /* Here should be added support of other bit modes. */ + +#warning missing logic + return ERROR; + } + + regval |= LPUART_CTRL_RE | LPUART_CTRL_TE; + putreg32(regval, base + IMXRT_LPUART_CTRL_OFFSET); + + return OK; +} +#endif /* HAVE_LPUART_DEVICE */ + +/************************************************************************************ + * Name: imxrt_lowputc + * + * Description: + * Output a byte with as few system dependencies as possible. This will even work + * BEFORE the console is initialized if we are booting from U-Boot (and the same + * UART is used for the console, of course.) + * + ************************************************************************************/ + +#if defined(HAVE_LPUART_DEVICE) && defined(CONFIG_DEBUG_FEATURES) +void imxrt_lowputc(int ch) +{ + while ((getreg32(IMXRT_CONSOLE_BASE + IMXRT_LPUART_STAT_OFFSET) & LPUART_STAT_TDRE) == 0) + { + } + + /* If the character to output is a newline, then pre-pend a carriage return */ + + if (ch == '\n') + { + /* Send the carriage return by writing it into the UART_TXD register. */ + + putreg32((uint32_t)'\r', IMXRT_CONSOLE_BASE + IMXRT_LPUART_DATA_OFFSET); + + /* Wait for the transmit register to be emptied. When the TXFE bit is non-zero, + * the TX Buffer FIFO is empty. + */ + + while ((getreg32(IMXRT_CONSOLE_BASE + IMXRT_LPUART_STAT_OFFSET) & LPUART_STAT_TDRE) == 0) + { + } + } + + /* Send the character by writing it into the UART_TXD register. */ + + putreg32((uint32_t)ch, IMXRT_CONSOLE_BASE + IMXRT_LPUART_DATA_OFFSET); + + /* Wait for the transmit register to be emptied. When the TXFE bit is non-zero, + * the TX Buffer FIFO is empty. + */ + + while ((getreg32(IMXRT_CONSOLE_BASE + IMXRT_LPUART_STAT_OFFSET) & LPUART_STAT_TDRE) == 0) + { + } +} +#endif diff --git a/arch/arm/src/imxrt/imxrt_lowputc.h b/arch/arm/src/imxrt/imxrt_lowputc.h new file mode 100644 index 00000000000..710fb92d4cb --- /dev/null +++ b/arch/arm/src/imxrt/imxrt_lowputc.h @@ -0,0 +1,115 @@ +/**************************************************************************** + * arch/arm/src/imxrt/imxrt_lowputc.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Ivan Ucherdzhiev + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMXRT_LOWPUTC_H +#define __ARCH_ARM_SRC_IMXRT_LOWPUTC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include +#include +#include + +#include "up_internal.h" +#include "chip.h" +#include "imxrt_config.h" + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifdef HAVE_LPUART_DEVICE +/* This structure describes the configuration of an UART */ + +struct uart_config_s +{ + uint32_t baud; /* Configured baud */ + uint8_t parity; /* 0=none, 1=odd, 2=even */ + uint8_t bits; /* Number of bits (5-9) */ + bool stopbits2; /* true: Configure with 2 stop bits instead of 1 */ +}; +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: imxrt_lowsetup + * + * Description: + * Called at the very beginning of _start. Performs low level + * initialization including setup of the console UART. This UART done + * early so that the serial console is available for debugging very early + * in the boot sequence. + * + ****************************************************************************/ + +void imxrt_lowsetup(void); + +/************************************************************************************ + * Name: imxrt_lpuart_configure + * + * Description: + * Configure a UART for non-interrupt driven operation + * + ************************************************************************************/ + +#ifdef HAVE_LPUART_DEVICE +int imxrt_lpuart_configure(uint32_t base, FAR const struct uart_config_s *config); +#endif + +/************************************************************************************ + * Name: imxrt_lowputc + * + * Description: + * Output a byte with as few system dependencies as possible. This will even work + * BEFORE the console is initialized if we are booting from U-Boot (and the same + * UART is used for the console, of course.) + * + ************************************************************************************/ + +#if defined(HAVE_LPUART_DEVICE) && defined(CONFIG_DEBUG_FEATURES) +void imxrt_lowputc(int ch); +#else +# define imxrt_lowputc(ch) +#endif + +#endif /* __ARCH_ARM_SRC_IMXRT_LOWPUTC_H */ diff --git a/arch/arm/src/imxrt/imxrt_mpuinit.c b/arch/arm/src/imxrt/imxrt_mpuinit.c new file mode 100644 index 00000000000..e75224c0786 --- /dev/null +++ b/arch/arm/src/imxrt/imxrt_mpuinit.c @@ -0,0 +1,141 @@ +/**************************************************************************** + * arch/arm/src/imxrt/imxrt_mpuinit.c + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#include "mpu.h" +#include "cache.h" +#include "chip/imxrt_memorymap.h" + +#include "imxrt_mpuinit.h" + +#ifdef CONFIG_ARM_MPU + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef MAX +# define MAX(a,b) a > b ? a : b +#endif + +#ifndef MIN +# define MIN(a,b) a < b ? a : b +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imxrt_mpu_initialize + * + * Description: + * Configure the MPU to permit user-space access to only restricted SAM3/4 + * resources. + * + ****************************************************************************/ + +void imxrt_mpu_initialize(void) +{ +#ifdef CONFIG_BUILD_PROTECTED + uintptr_t datastart; + uintptr_t dataend; +#endif + + /* Show MPU information */ + + mpu_showtype(); + +#ifdef CONFIG_ARMV7M_DCACHE + /* Memory barrier */ + + ARM_DMB(); + +#ifdef CONFIG_SAMV7_QSPI + /* Make QSPI memory region strongly ordered */ + + mpu_priv_stronglyordered(SAM_QSPIMEM_BASE, SAM_QSPIMEM_SIZE); + +#endif +#endif + +#ifdef CONFIG_BUILD_PROTECTED + /* Configure user flash and SRAM space */ + + DEBUGASSERT(USERSPACE->us_textend >= USERSPACE->us_textstart); + + mpu_user_flash(USERSPACE->us_textstart, + USERSPACE->us_textend - USERSPACE->us_textstart); + + datastart = MIN(USERSPACE->us_datastart, USERSPACE->us_bssstart); + dataend = MAX(USERSPACE->us_dataend, USERSPACE->us_bssend); + + DEBUGASSERT(dataend >= datastart); + + mpu_user_intsram(datastart, dataend - datastart); +#endif + + /* Then enable the MPU */ + + mpu_control(true, false, true); +} + +/**************************************************************************** + * Name: imxrt_mpu_uheap + * + * Description: + * Map the user-heap region. + * + * This logic may need an extension to handle external SDRAM). + * + ****************************************************************************/ + +#ifdef CONFIG_BUILD_PROTECTED +void imxrt_mpu_uheap(uintptr_t start, size_t size) +{ + mpu_user_intsram(start, size); +} +#endif + +#endif /* CONFIG_ARM_MPU */ diff --git a/arch/arm/src/imxrt/imxrt_mpuinit.h b/arch/arm/src/imxrt/imxrt_mpuinit.h new file mode 100644 index 00000000000..d6a52435674 --- /dev/null +++ b/arch/arm/src/imxrt/imxrt_mpuinit.h @@ -0,0 +1,106 @@ +/**************************************************************************** + * arch/arm/src/imxrt/imxrt_mpuinit.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMXRT_IMXRT_MPUINIT_H +#define __ARCH_ARM_SRC_IMXRT_IMXRT_MPUINIT_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: imxrt_mpu_initialize + * + * Description: + * Configure the MPU to permit user-space access to only unrestricted SAMV7 + * resources. + * + ****************************************************************************/ + +#ifdef CONFIG_ARM_MPU +void imxrt_mpu_initialize(void); +#else +# define imxrt_mpu_initialize() +#endif + +/**************************************************************************** + * Name: imxrt_mpu_uheap + * + * Description: + * Map the user heap region. + * + ****************************************************************************/ + +#ifdef CONFIG_BUILD_PROTECTED +void imxrt_mpu_uheap(uintptr_t start, size_t size); +#else +# define imxrt_mpu_uheap(start,size) +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_IMXRT_IMXRT_MPUINIT_H */ diff --git a/arch/arm/src/imxrt/imxrt_serial.c b/arch/arm/src/imxrt/imxrt_serial.c new file mode 100644 index 00000000000..d84a36f1b06 --- /dev/null +++ b/arch/arm/src/imxrt/imxrt_serial.c @@ -0,0 +1,1194 @@ +/**************************************************************************** + * arch/arm/src/imxrt/imxrt_serial.c + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Ivan Ucherdzhiev + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include "chip.h" +#include "up_arch.h" +#include "up_internal.h" + +#include "chip/imxrt_lpuart.h" +#include "imxrt_config.h" +#include "imxrt_lowputc.h" + +#ifdef USE_SERIALDRIVER + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Which LPUART with be tty0/console and which tty1-7? The console will always + * be ttyS0. If there is no console then will use the lowest numbered UART. + */ + +/* First pick the console and ttys0. This could be any of LPUART1-8 */ + +#if defined(CONFIG_LPUART1_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart1port /* LPUART1 is console */ +# define TTYS0_DEV g_uart1port /* LPUART1 is ttyS0 */ +# define UART1_ASSIGNED 1 +#elif defined(CONFIG_LPUART2_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart2port /* LPUART2 is console */ +# define TTYS0_DEV g_uart2port /* LPUART2 is ttyS0 */ +# define UART2_ASSIGNED 1 +#elif defined(CONFIG_LPUART3_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart3port /* LPUART3 is console */ +# define TTYS0_DEV g_uart3port /* LPUART3 is ttyS0 */ +# define UART3_ASSIGNED 1 +#elif defined(CONFIG_LPUART4_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart4port /* LPUART4 is console */ +# define TTYS0_DEV g_uart4port /* LPUART4 is ttyS0 */ +# define UART4_ASSIGNED 1 +#elif defined(CONFIG_LPUART5_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart5port /* LPUART5 is console */ +# define TTYS5_DEV g_uart5port /* LPUART5 is ttyS0 */ +# define UART5_ASSIGNED 1 +#elif defined(CONFIG_LPUART6_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart6port /* LPUART6 is console */ +# define TTYS6_DEV g_uart6port /* LPUART6 is ttyS0 */ +# define UART6_ASSIGNED 1 +#elif defined(CONFIG_LPUART7_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart7port /* LPUART7 is console */ +# define TTYS7_DEV g_uart7port /* LPUART7 is ttyS0 */ +# define UART7_ASSIGNED 1 +#elif defined(CONFIG_LPUART8_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart8port /* LPUART8 is console */ +# define TTYS8_DEV g_uart8port /* LPUART8 is ttyS0 */ +# define UART8_ASSIGNED 1 +#else +# undef CONSOLE_DEV /* No console */ +# if defined(CONFIG_IMXRT_LPUART1) +# define TTYS0_DEV g_uart1port /* LPUART1 is ttyS0 */ +# define UART1_ASSIGNED 1 +# elif defined(CONFIG_IMXRT_LPUART2) +# define TTYS0_DEV g_uart2port /* LPUART2 is ttyS0 */ +# define UART2_ASSIGNED 1 +# elif defined(CONFIG_IMXRT_LPUART3) +# define TTYS0_DEV g_uart3port /* LPUART3 is ttyS0 */ +# define UART3_ASSIGNED 1 +# elif defined(CONFIG_IMXRT_LPUART4) +# define TTYS0_DEV g_uart4port /* LPUART4 is ttyS0 */ +# define UART4_ASSIGNED 1 +# elif defined(CONFIG_IMXRT_LPUART5) +# define TTYS0_DEV g_uart5port /* LPUART5 is ttyS0 */ +# define UART5_ASSIGNED 1 +# elif defined(CONFIG_IMXRT_LPUART6) +# define TTYS0_DEV g_uart6port /* LPUART6 is ttyS0 */ +# define UART6_ASSIGNED 1 +# elif defined(CONFIG_IMXRT_LPUART7) +# define TTYS0_DEV g_uart7port /* LPUART7 is ttyS0 */ +# define UART7_ASSIGNED 1 +# elif defined(CONFIG_IMXRT_LPUART8) +# define TTYS0_DEV g_uart8port /* LPUART8 is ttyS0 */ +# define UART8_ASSIGNED 1 +# endif +#endif + +/* Pick ttys1. This could be any of UART1-8 excluding the console UART. + * One of UART1-8 could be the console; one of UART1-8 has already been + * assigned to ttys0. + */ + +#if defined(CONFIG_IMXRT_LPUART1) && !defined(UART1_ASSIGNED) +# define TTYS1_DEV g_uart1port /* LPUART1 is ttyS1 */ +# define UART1_ASSIGNED 1 +#elif defined(CONFIG_IMXRT_LPUART2) && !defined(UART2_ASSIGNED) +# define TTYS1_DEV g_uart2port /* LPUART2 is ttyS1 */ +# define UART2_ASSIGNED 1 +#elif defined(CONFIG_IMXRT_LPUART3) && !defined(UART3_ASSIGNED) +# define TTYS1_DEV g_uart3port /* LPUART3 is ttyS1 */ +# define UART3_ASSIGNED 1 +#elif defined(CONFIG_IMXRT_LPUART4) && !defined(UART4_ASSIGNED) +# define TTYS1_DEV g_uart4port /* LPUART4 is ttyS1 */ +# define UART4_ASSIGNED 1 +#elif defined(CONFIG_IMXRT_LPUART5) && !defined(UART5_ASSIGNED) +# define TTYS1_DEV g_uart5port /* LPUART5 is ttyS1 */ +# define UART5_ASSIGNED 1 +#elif defined(CONFIG_IMXRT_LPUART6) && !defined(UART6_ASSIGNED) +# define TTYS1_DEV g_uart6port /* LPUART6 is ttyS1 */ +# define UART6_ASSIGNED 1 +#elif defined(CONFIG_IMXRT_LPUART7) && !defined(UART7_ASSIGNED) +# define TTYS1_DEV g_uart7port /* LPUART7 is ttyS1 */ +# define UART7_ASSIGNED 1 +#elif defined(CONFIG_IMXRT_LPUART8) && !defined(UART8_ASSIGNED) +# define TTYS1_DEV g_uart8port /* LPUART8 is ttyS1 */ +# define UART8_ASSIGNED 1 +#endif + +/* Pick ttys2. This could be one of UART2-8. It can't be UART1 because that + * was either assigned as ttyS0 or ttys1. One of UART 1-8 could be the + * console. One of UART2-8 has already been assigned to ttys0 or ttyS1. + */ + +#if defined(CONFIG_IMXRT_LPUART2) && !defined(UART2_ASSIGNED) +# define TTYS2_DEV g_uart2port /* LPUART2 is ttyS2 */ +# define UART2_ASSIGNED 1 +#elif defined(CONFIG_IMXRT_LPUART3) && !defined(UART3_ASSIGNED) +# define TTYS2_DEV g_uart3port /* LPUART3 is ttyS2 */ +# define UART3_ASSIGNED 1 +#elif defined(CONFIG_IMXRT_LPUART4) && !defined(UART4_ASSIGNED) +# define TTYS2_DEV g_uart4port /* LPUART4 is ttyS2 */ +# define UART4_ASSIGNED 1 +#elif defined(CONFIG_IMXRT_LPUART5) && !defined(UART5_ASSIGNED) +# define TTYS2_DEV g_uart5port /* LPUART5 is ttyS2 */ +# define UART5_ASSIGNED 1 +#elif defined(CONFIG_IMXRT_LPUART6) && !defined(UART6_ASSIGNED) +# define TTYS2_DEV g_uart6port /* LPUART6 is ttyS2 */ +# define UART6_ASSIGNED 1 +#elif defined(CONFIG_IMXRT_LPUART7) && !defined(UART7_ASSIGNED) +# define TTYS2_DEV g_uart7port /* LPUART7 is ttyS2 */ +# define UART7_ASSIGNED 1 +#elif defined(CONFIG_IMXRT_LPUART8) && !defined(UART8_ASSIGNED) +# define TTYS2_DEV g_uart8port /* LPUART8 is ttyS2 */ +# define UART8_ASSIGNED 1 +#endif + +/* Pick ttys3. This could be one of UART3-8. It can't be UART1-2 because + * those have already been assigned to ttsyS0, 1, or 2. One of + * UART3-8 could also be the console. One of UART3-8 has already + * been assigned to ttys0, 1, or 3. + */ + +#if defined(CONFIG_IMXRT_LPUART3) && !defined(UART3_ASSIGNED) +# define TTYS3_DEV g_uart3port /* LPUART3 is ttyS3 */ +# define UART3_ASSIGNED 1 +#elif defined(CONFIG_IMXRT_LPUART4) && !defined(UART4_ASSIGNED) +# define TTYS3_DEV g_uart4port /* LPUART4 is ttyS3 */ +# define UART4_ASSIGNED 1 +#elif defined(CONFIG_IMXRT_LPUART5) && !defined(UART5_ASSIGNED) +# define TTYS3_DEV g_uart5port /* LPUART5 is ttyS3 */ +# define UART5_ASSIGNED 1 +#elif defined(CONFIG_IMXRT_LPUART6) && !defined(UART6_ASSIGNED) +# define TTYS3_DEV g_uart6port /* LPUART6 is ttyS3 */ +# define UART6_ASSIGNED 1 +#elif defined(CONFIG_IMXRT_LPUART7) && !defined(UART7_ASSIGNED) +# define TTYS3_DEV g_uart7port /* LPUART7 is ttyS3 */ +# define UART7_ASSIGNED 1 +#elif defined(CONFIG_IMXRT_LPUART8) && !defined(UART8_ASSIGNED) +# define TTYS3_DEV g_uart8port /* LPUART8 is ttyS3 */ +# define UART8_ASSIGNED 1 +#endif + +/* Pick ttys4. This could be one of UART4-8. It can't be UART1-3 because + * those have already been assigned to ttsyS0, 1, 2 or 3. One of + * UART 4-8 could be the console. One of UART4-8 has already been + * assigned to ttys0, 1, 3, or 4. + */ + +#if defined(CONFIG_IMXRT_LPUART4) && !defined(UART4_ASSIGNED) +# define TTYS4_DEV g_uart4port /* LPUART4 is ttyS4 */ +# define UART4_ASSIGNED 1 +#elif defined(CONFIG_IMXRT_LPUART5) && !defined(UART5_ASSIGNED) +# define TTYS4_DEV g_uart5port /* LPUART5 is ttyS4 */ +# define UART5_ASSIGNED 1 +#elif defined(CONFIG_IMXRT_LPUART6) && !defined(UART6_ASSIGNED) +# define TTYS4_DEV g_uart6port /* LPUART6 is ttyS4 */ +# define UART6_ASSIGNED 1 +#elif defined(CONFIG_IMXRT_LPUART7) && !defined(UART7_ASSIGNED) +# define TTYS4_DEV g_uart7port /* LPUART7 is ttyS4 */ +# define UART7_ASSIGNED 1 +#elif defined(CONFIG_IMXRT_LPUART8) && !defined(UART8_ASSIGNED) +# define TTYS4_DEV g_uart8port /* LPUART8 is ttyS4 */ +# define UART8_ASSIGNED 1 +#endif + +/* Pick ttys5. This could be one of UART5-8. It can't be UART1-4 because + * those have already been assigned to ttsyS0, 1, 2, 3 or 4. One of + * UART 5-8 could be the console. One of UART5-8 has already been + * assigned to ttys0, 1, 2, 3, or 4. + */ +#if defined(CONFIG_IMXRT_LPUART5) && !defined(UART5_ASSIGNED) +# define TTYS5_DEV g_uart5port /* LPUART5 is ttyS5 */ +# define UART5_ASSIGNED 1 +#elif defined(CONFIG_IMXRT_LPUART6) && !defined(UART6_ASSIGNED) +# define TTYS5_DEV g_uart6port /* LPUART6 is ttyS5 */ +# define UART6_ASSIGNED 1 +#elif defined(CONFIG_IMXRT_LPUART7) && !defined(UART7_ASSIGNED) +# define TTYS5_DEV g_uart7port /* LPUART7 is ttyS5 */ +# define UART7_ASSIGNED 1 +#elif defined(CONFIG_IMXRT_LPUART8) && !defined(UART8_ASSIGNED) +# define TTYS5_DEV g_uart8port /* LPUART8 is ttyS5 */ +# define UART8_ASSIGNED 1 +#endif + +/* Pick ttys6. This could be one of UART6-8. It can't be UART1-5 because + * those have already been assigned to ttsyS0, 1, 2, 3, 4 or 5. One of + * UART 6-8 could be the console. One of UART6-8 has already been + * assigned to ttys0, 1, 2, 3, 4 or 5. + */ + +#if defined(CONFIG_IMXRT_LPUART6) && !defined(UART6_ASSIGNED) +# define TTYS6_DEV g_uart6port /* LPUART6 is ttyS5 */ +# define UART6_ASSIGNED 1 +#elif defined(CONFIG_IMXRT_LPUART7) && !defined(UART7_ASSIGNED) +# define TTYS6_DEV g_uart7port /* LPUART7 is ttyS5 */ +# define UART7_ASSIGNED 1 +#elif defined(CONFIG_IMXRT_LPUART8) && !defined(UART8_ASSIGNED) +# define TTYS6_DEV g_uart8port /* LPUART8 is ttyS5 */ +# define UART8_ASSIGNED 1 +#endif + +/* Pick ttys7. This could be one of UART7-8. It can't be UART1-6 because + * those have already been assigned to ttsyS0, 1, 2, 3, 4, 5 or 6. One of + * UART 7-8 could be the console. One of UART7-8 has already been + * assigned to ttys0, 1, 2, 3, 4, 5 or 6. + */ + +#if defined(CONFIG_IMXRT_LPUART7) && !defined(UART7_ASSIGNED) +# define TTYS7_DEV g_uart7port /* LPUART7 is ttyS5 */ +# define UART7_ASSIGNED 1 +#elif defined(CONFIG_IMXRT_LPUART8) && !defined(UART8_ASSIGNED) +# define TTYS7_DEV g_uart8port /* LPUART8 is ttyS5 */ +# define UART8_ASSIGNED 1 +#endif + +/* UART, if available, should have been assigned to ttyS0-7. */ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct imxrt_uart_s +{ + uint32_t uartbase; /* Base address of UART registers */ + uint32_t baud; /* Configured baud */ + uint32_t ie; /* Saved enabled interrupts */ + uint8_t irq; /* IRQ associated with this UART */ + uint8_t parity; /* 0=none, 1=odd, 2=even */ + uint8_t bits; /* Number of bits (7 or 8) */ + uint8_t stopbits2:1; /* 1: Configure with 2 stop bits vs 1 */ + uint8_t hwfc:1; /* 1: Hardware flow control */ + uint8_t reserved:6; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static inline uint32_t imxrt_serialin(struct imxrt_uart_s *priv, + uint32_t offset); +static inline void imxrt_serialout(struct imxrt_uart_s *priv, uint32_t offset, + uint32_t value); +static inline void imxrt_disableuartint(struct imxrt_uart_s *priv, + uint32_t *ie); +static inline void imxrt_restoreuartint(struct imxrt_uart_s *priv, + uint32_t ie); + +static int imxrt_setup(struct uart_dev_s *dev); +static void imxrt_shutdown(struct uart_dev_s *dev); +static int imxrt_attach(struct uart_dev_s *dev); +static void imxrt_detach(struct uart_dev_s *dev); +static int imxrt_interrupt(int irq, void *context, FAR void *arg); +static int imxrt_ioctl(struct file *filep, int cmd, unsigned long arg); +static int imxrt_receive(struct uart_dev_s *dev, uint32_t *status); +static void imxrt_rxint(struct uart_dev_s *dev, bool enable); +static bool imxrt_rxavailable(struct uart_dev_s *dev); +static void imxrt_send(struct uart_dev_s *dev, int ch); +static void imxrt_txint(struct uart_dev_s *dev, bool enable); +static bool imxrt_txready(struct uart_dev_s *dev); +static bool imxrt_txempty(struct uart_dev_s *dev); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Used to assure mutually exclusive access up_putc() */ +/* REVISIT: This is referenced anywhere and generates a warning. */ + +static sem_t g_putc_lock = SEM_INITIALIZER(1); + +/* Serial driver UART operations */ + +static const struct uart_ops_s g_uart_ops = +{ + .setup = imxrt_setup, + .shutdown = imxrt_shutdown, + .attach = imxrt_attach, + .detach = imxrt_detach, + .ioctl = imxrt_ioctl, + .receive = imxrt_receive, + .rxint = imxrt_rxint, + .rxavailable = imxrt_rxavailable, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = NULL, +#endif + .send = imxrt_send, + .txint = imxrt_txint, + .txready = imxrt_txready, + .txempty = imxrt_txempty, +}; + +/* I/O buffers */ + +#ifdef CONFIG_IMXRT_LPUART1 +static char g_uart1rxbuffer[CONFIG_LPUART1_RXBUFSIZE]; +static char g_uart1txbuffer[CONFIG_LPUART1_TXBUFSIZE]; +#endif + +#ifdef CONFIG_IMXRT_LPUART2 +static char g_uart2rxbuffer[CONFIG_LPUART2_RXBUFSIZE]; +static char g_uart2txbuffer[CONFIG_LPUART2_TXBUFSIZE]; +#endif + +#ifdef CONFIG_IMXRT_LPUART3 +static char g_uart3rxbuffer[CONFIG_LPUART3_RXBUFSIZE]; +static char g_uart3txbuffer[CONFIG_LPUART3_TXBUFSIZE]; +#endif + +#ifdef CONFIG_IMXRT_LPUART4 +static char g_uart4rxbuffer[CONFIG_LPUART4_RXBUFSIZE]; +static char g_uart4txbuffer[CONFIG_LPUART4_TXBUFSIZE]; +#endif + +#ifdef CONFIG_IMXRT_LPUART5 +static char g_uart5rxbuffer[CONFIG_LPUART5_RXBUFSIZE]; +static char g_uart5txbuffer[CONFIG_LPUART5_TXBUFSIZE]; +#endif + +#ifdef CONFIG_IMXRT_LPUART6 +static char g_uart6rxbuffer[CONFIG_LPUART6_RXBUFSIZE]; +static char g_uart6txbuffer[CONFIG_LPUART6_TXBUFSIZE]; +#endif + +#ifdef CONFIG_IMXRT_LPUART7 +static char g_uart7rxbuffer[CONFIG_LPUART7_RXBUFSIZE]; +static char g_uart7txbuffer[CONFIG_LPUART7_TXBUFSIZE]; +#endif + +#ifdef CONFIG_IMXRT_LPUART8 +static char g_uart8rxbuffer[CONFIG_LPUART8_RXBUFSIZE]; +static char g_uart8txbuffer[CONFIG_LPUART8_TXBUFSIZE]; +#endif + +/* This describes the state of the IMXRT lpuart1 port. */ + +#ifdef CONFIG_IMXRT_LPUART1 +static struct imxrt_uart_s g_uart1priv = +{ + .uartbase = IMXRT_LPUART1_BASE, + .baud = CONFIG_LPUART1_BAUD, + .irq = IMXRT_IRQ_LPUART1, + .parity = CONFIG_LPUART1_PARITY, + .bits = CONFIG_LPUART1_BITS, + .stopbits2 = CONFIG_LPUART1_2STOP, +}; + +static struct uart_dev_s g_uart1port = +{ + .recv = + { + .size = CONFIG_LPUART1_RXBUFSIZE, + .buffer = g_uart1rxbuffer, + }, + .xmit = + { + .size = CONFIG_LPUART1_TXBUFSIZE, + .buffer = g_uart1txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart1priv, +}; +#endif + +/* This describes the state of the IMXRT lpuart2 port. */ + +#ifdef CONFIG_IMXRT_LPUART2 +static struct imxrt_uart_s g_uart2priv = +{ + .uartbase = IMXRT_LPUART2_BASE, + .baud = CONFIG_LPUART2_BAUD, + .irq = IMXRT_IRQ_LPUART2, + .parity = CONFIG_LPUART2_PARITY, + .bits = CONFIG_LPUART2_BITS, + .stopbits2 = CONFIG_LPUART2_2STOP, +}; + +static struct uart_dev_s g_uart2port = +{ + .recv = + { + .size = CONFIG_LPUART2_RXBUFSIZE, + .buffer = g_uart2rxbuffer, + }, + .xmit = + { + .size = CONFIG_LPUART2_TXBUFSIZE, + .buffer = g_uart2txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart2priv, +}; +#endif + +#ifdef CONFIG_IMXRT_LPUART3 +static struct imxrt_uart_s g_uart3priv = +{ + .uartbase = IMXRT_LPUART3_BASE, + .baud = CONFIG_LPUART3_BAUD, + .irq = IMXRT_IRQ_LPUART3, + .parity = CONFIG_LPUART3_PARITY, + .bits = CONFIG_LPUART3_BITS, + .stopbits2 = CONFIG_LPUART3_2STOP, +}; + +static struct uart_dev_s g_uart3port = +{ + .recv = + { + .size = CONFIG_LPUART3_RXBUFSIZE, + .buffer = g_uart3rxbuffer, + }, + .xmit = + { + .size = CONFIG_LPUART3_TXBUFSIZE, + .buffer = g_uart3txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart3priv, +}; +#endif + +#ifdef CONFIG_IMXRT_LPUART4 +static struct imxrt_uart_s g_uart4priv = +{ + .uartbase = IMXRT_LPUART4_BASE, + .baud = CONFIG_LPUART4_BAUD, + .irq = IMXRT_IRQ_LPUART4, + .parity = CONFIG_LPUART4_PARITY, + .bits = CONFIG_LPUART4_BITS, + .stopbits2 = CONFIG_LPUART4_2STOP, +}; + +static struct uart_dev_s g_uart4port = +{ + .recv = + { + .size = CONFIG_LPUART4_RXBUFSIZE, + .buffer = g_uart4rxbuffer, + }, + .xmit = + { + .size = CONFIG_LPUART4_TXBUFSIZE, + .buffer = g_uart4txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart4priv, +}; +#endif + +#ifdef CONFIG_IMXRT_LPUART5 +static struct imxrt_uart_s g_uart5priv = +{ + .uartbase = IMXRT_LPUART5_BASE, + .baud = CONFIG_LPUART5_BAUD, + .irq = IMXRT_IRQ_LPUART5, + .parity = CONFIG_LPUART5_PARITY, + .bits = CONFIG_LPUART5_BITS, + .stopbits2 = CONFIG_LPUART5_2STOP, +}; + +static struct uart_dev_s g_uart5port = +{ + .recv = + { + .size = CONFIG_LPUART5_RXBUFSIZE, + .buffer = g_uart5rxbuffer, + }, + .xmit = + { + .size = CONFIG_LPUART5_TXBUFSIZE, + .buffer = g_uart5txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart5priv, +}; +#endif + +#ifdef CONFIG_IMXRT_LPUART6 +static struct imxrt_uart_s g_uart6priv = +{ + .uartbase = IMXRT_LPUART6_BASE, + .baud = CONFIG_LPUART6_BAUD, + .irq = IMXRT_IRQ_LPUART6, + .parity = CONFIG_LPUART6_PARITY, + .bits = CONFIG_LPUART6_BITS, + .stopbits2 = CONFIG_LPUART6_2STOP, +}; + +static struct uart_dev_s g_uart6port = +{ + .recv = + { + .size = CONFIG_LPUART6_RXBUFSIZE, + .buffer = g_uart6rxbuffer, + }, + .xmit = + { + .size = CONFIG_LPUART6_TXBUFSIZE, + .buffer = g_uart6txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart6priv, +}; +#endif + +#ifdef CONFIG_IMXRT_LPUART7 +static struct imxrt_uart_s g_uart7priv = +{ + .uartbase = IMXRT_LPUART7_BASE, + .baud = CONFIG_LPUART7_BAUD, + .irq = IMXRT_IRQ_LPUART7, + .parity = CONFIG_LPUART7_PARITY, + .bits = CONFIG_LPUART7_BITS, + .stopbits2 = CONFIG_LPUART7_2STOP, +}; + +static struct uart_dev_s g_uart7port = +{ + .recv = + { + .size = CONFIG_LPUART7_RXBUFSIZE, + .buffer = g_uart7rxbuffer, + }, + .xmit = + { + .size = CONFIG_LPUART7_TXBUFSIZE, + .buffer = g_uart7txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart7priv, +}; +#endif + +#ifdef CONFIG_IMXRT_LPUART8 +static struct imxrt_uart_s g_uart8priv = +{ + .uartbase = IMXRT_LPUART8_BASE, + .baud = CONFIG_LPUART8_BAUD, + .irq = IMXRT_IRQ_LPUART8, + .parity = CONFIG_LPUART8_PARITY, + .bits = CONFIG_LPUART8_BITS, + .stopbits2 = CONFIG_LPUART8_2STOP, +}; + +static struct uart_dev_s g_uart8port = +{ + .recv = + { + .size = CONFIG_LPUART8_RXBUFSIZE, + .buffer = g_uart8rxbuffer, + }, + .xmit = + { + .size = CONFIG_LPUART8_TXBUFSIZE, + .buffer = g_uart8txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart8priv, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imxrt_serialin + ****************************************************************************/ + +static inline uint32_t imxrt_serialin(struct imxrt_uart_s *priv, + uint32_t offset) +{ + return getreg32(priv->uartbase + offset); +} + +/**************************************************************************** + * Name: imxrt_serialout + ****************************************************************************/ + +static inline void imxrt_serialout(struct imxrt_uart_s *priv, uint32_t offset, + uint32_t value) +{ + putreg32(value, priv->uartbase + offset); +} + +/**************************************************************************** + * Name: imxrt_disableuartint + ****************************************************************************/ + +static inline void imxrt_disableuartint(struct imxrt_uart_s *priv, + uint32_t *ie) +{ + irqstate_t flags; + uint32_t regval = 0; + + flags = enter_critical_section(); + regval = imxrt_serialin(priv, IMXRT_LPUART_CTRL_OFFSET); + + /* Return the current Rx and Tx interrupt state */ + + if (ie != NULL) + { + *ie = regval & LPUART_ALL_INTS; + } + + regval &= ~ LPUART_ALL_INTS; + imxrt_serialout(priv, IMXRT_LPUART_CTRL_OFFSET, regval); + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: imxrt_restoreuartint + ****************************************************************************/ + +static inline void imxrt_restoreuartint(struct imxrt_uart_s *priv, + uint32_t ie) +{ + /* Enable/disable any interrupts that are currently disabled but should be + * enabled/disabled. + */ + + uint32_t regval = 0; + + regval = imxrt_serialin(priv, IMXRT_LPUART_CTRL_OFFSET) | ie; + imxrt_serialout(priv, IMXRT_LPUART_CTRL_OFFSET, regval); +} + +/**************************************************************************** + * Name: imxrt_setup + * + * Description: + * Configure the UART baud, bits, parity, fifos, etc. This + * method is called the first time that the serial port is + * opened. + * + ****************************************************************************/ + +static int imxrt_setup(struct uart_dev_s *dev) +{ + struct imxrt_uart_s *priv = (struct imxrt_uart_s *)dev->priv; +#ifndef CONFIG_SUPPRESS_LPUART_CONFIG + struct uart_config_s config; + int ret; + + /* Configure the UART */ + + config.baud = priv->baud; /* Configured baud */ + config.parity = priv->parity; /* 0=none, 1=odd, 2=even */ + config.bits = priv->bits; /* Number of bits (5-9) */ + config.stopbits2 = priv->stopbits2; /* true: Configure with 2 stop bits instead of 1 */ + + ret = imxrt_lpuart_configure(priv->uartbase, &config); + + priv->ie = imxrt_serialin(priv, IMXRT_LPUART_CTRL_OFFSET) | LPUART_ALL_INTS; + return ret; + +#else + priv->ie = imxrt_serialin(priv, IMXRT_LPUART_CTRL_OFFSET) | LPUART_ALL_INTS; + return OK; +#endif +} + +/**************************************************************************** + * Name: imxrt_shutdown + * + * Description: + * Disable the UART. This method is called when the serial + * port is closed + * + ****************************************************************************/ + +static void imxrt_shutdown(struct uart_dev_s *dev) +{ + struct imxrt_uart_s *priv = (struct imxrt_uart_s *)dev->priv; + + /* Disable the UART */ + + imxrt_serialout(priv, IMXRT_LPUART_GLOBAL_OFFSET, LPUART_GLOBAL_RST); +} + +/**************************************************************************** + * Name: imxrt_attach + * + * Description: + * Configure the UART to operation in interrupt driven mode. This method is + * called when the serial port is opened. Normally, this is just after the + * the setup() method is called, however, the serial console may operate in + * a non-interrupt driven mode during the boot phase. + * + * RX and TX interrupts are not enabled when by the attach method (unless the + * hardware supports multiple levels of interrupt enabling). The RX and TX + * interrupts are not enabled until the txint() and rxint() methods are called. + * + ****************************************************************************/ + +static int imxrt_attach(struct uart_dev_s *dev) +{ + struct imxrt_uart_s *priv = (struct imxrt_uart_s *)dev->priv; + int ret; + + /* Attach and enable the IRQ */ + + ret = irq_attach(priv->irq, imxrt_interrupt, dev); + if (ret == OK) + { + /* Enable the interrupt (RX and TX interrupts are still disabled + * in the UART + */ + + up_enable_irq(priv->irq); + } + + return ret; +} + +/**************************************************************************** + * Name: imxrt_detach + * + * Description: + * Detach UART interrupts. This method is called when the serial port is + * closed normally just before the shutdown method is called. The exception is + * the serial console which is never shutdown. + * + ****************************************************************************/ + +static void imxrt_detach(struct uart_dev_s *dev) +{ + struct imxrt_uart_s *priv = (struct imxrt_uart_s *)dev->priv; + + up_disable_irq(priv->irq); + irq_detach(priv->irq); +} + +/**************************************************************************** + * Name: imxrt_interrupt (and front-ends) + * + * Description: + * This is the common UART interrupt handler. It should cal + * uart_transmitchars or uart_receivechar to perform the appropriate data + * transfers. + * + ****************************************************************************/ + +static int imxrt_interrupt(int irq, void *context, FAR void *arg) +{ + struct uart_dev_s *dev = (struct uart_dev_s *)arg; + struct imxrt_uart_s *priv; + uint32_t usr; + int passes = 0; + + DEBUGASSERT(dev != NULL && dev->priv != NULL); + priv = (struct imxrt_uart_s *)dev->priv; + + /* Loop until there are no characters to be transferred or, + * until we have been looping for a long time. + */ + + for (; ; ) + { + /* Get the current UART status and check for loop + * termination conditions + */ + + usr = imxrt_serialin(priv, IMXRT_LPUART_STAT_OFFSET); + usr &= (LPUART_STAT_RDRF | LPUART_STAT_TC); + + if (usr == 0 || passes > 256) + { + return OK; + } + + /* Handle incoming, receive bytes */ + + if (usr & LPUART_STAT_RDRF) + { + uart_recvchars(dev); + } + + /* Handle outgoing, transmit bytes */ + + if (usr & LPUART_STAT_TC) + { + uart_xmitchars(dev); + } + + /* Keep track of how many times we do this in case there + * is some hardware failure condition. + */ + + passes++; + } +} + +/**************************************************************************** + * Name: imxrt_ioctl + * + * Description: + * All ioctl calls will be routed through this method + * + ****************************************************************************/ + +static int imxrt_ioctl(struct file *filep, int cmd, unsigned long arg) +{ +#ifdef CONFIG_SERIAL_TIOCSERGSTRUCT + struct inode *inode = filep->f_inode; + struct uart_dev_s *dev = inode->i_private; +#endif + int ret = OK; + + switch (cmd) + { +#ifdef CONFIG_SERIAL_TIOCSERGSTRUCT + case TIOCSERGSTRUCT: + { + struct imxrt_uart_s *user = (struct imxrt_uart_s *)arg; + if (!user) + { + ret = -EINVAL; + } + else + { + memcpy(user, dev, sizeof(struct imxrt_uart_s)); + } + } + break; +#endif + + case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */ + case TIOCCBRK: /* BSD compatibility: Turn break off, unconditionally */ + default: + ret = -ENOTTY; + break; + } + + return ret; +} + +/**************************************************************************** + * Name: imxrt_receive + * + * Description: + * Called (usually) from the interrupt level to receive one + * character from the UART. Error bits associated with the + * receipt are provided in the return 'status'. + * + ****************************************************************************/ + +static int imxrt_receive(struct uart_dev_s *dev, uint32_t *status) +{ + struct imxrt_uart_s *priv = (struct imxrt_uart_s *)dev->priv; + uint32_t rxd; + + rxd = imxrt_serialin(priv, IMXRT_LPUART_DATA_OFFSET); + *status = rxd >> LPUART_DATA_STATUS_SHIFT; + return (rxd & LPUART_DATA_MASK) >> LPUART_DATA_SHIFT; +} + +/**************************************************************************** + * Name: imxrt_rxint + * + * Description: + * Call to enable or disable RX interrupts + * + ****************************************************************************/ + +static void imxrt_rxint(struct uart_dev_s *dev, bool enable) +{ + struct imxrt_uart_s *priv = (struct imxrt_uart_s *)dev->priv; + uint32_t regval = 0; + + /* Enable interrupts for data available at Rx FIFO */ + + if (enable) + { +#ifndef CONFIG_SUPPRESS_SERIAL_INTS + priv->ie |= LPUART_CTRL_RIE; +#endif + } + else + { + priv->ie &= ~LPUART_CTRL_RIE; + } + + regval = imxrt_serialin(priv, IMXRT_LPUART_CTRL_OFFSET) | priv->ie; + imxrt_serialout(priv, IMXRT_LPUART_CTRL_OFFSET, regval); +} + +/**************************************************************************** + * Name: imxrt_rxavailable + * + * Description: + * Return true if the receive fifo is not empty + * + ****************************************************************************/ + +static bool imxrt_rxavailable(struct uart_dev_s *dev) +{ + struct imxrt_uart_s *priv = (struct imxrt_uart_s *)dev->priv; + + /* Return true is data is ready in the Rx FIFO */ + + return ((imxrt_serialin(priv, IMXRT_LPUART_STAT_OFFSET) & LPUART_STAT_RDRF) != 0); +} + +/**************************************************************************** + * Name: imxrt_send + * + * Description: + * This method will send one byte on the UART + * + ****************************************************************************/ + +static void imxrt_send(struct uart_dev_s *dev, int ch) +{ + struct imxrt_uart_s *priv = (struct imxrt_uart_s *)dev->priv; + imxrt_serialout(priv, IMXRT_LPUART_DATA_OFFSET, (uint32_t)ch); +} + +/**************************************************************************** + * Name: imxrt_txint + * + * Description: + * Call to enable or disable TX interrupts + * + ****************************************************************************/ + +static void imxrt_txint(struct uart_dev_s *dev, bool enable) +{ + struct imxrt_uart_s *priv = (struct imxrt_uart_s *)dev->priv; + uint32_t regval = 0; + + /* We won't take an interrupt until the FIFO is completely empty (although + * there may still be a transmission in progress). + */ + + if (enable) + { +#ifndef CONFIG_SUPPRESS_SERIAL_INTS + priv->ie |= LPUART_CTRL_TCIE; +#endif + } + else + { + priv->ie &= ~LPUART_CTRL_TCIE; + } + + regval = imxrt_serialin(priv, IMXRT_LPUART_CTRL_OFFSET) | priv->ie; + imxrt_serialout(priv, IMXRT_LPUART_CTRL_OFFSET, regval); +} + +/**************************************************************************** + * Name: imxrt_txready + * + * Description: + * Return true if the transmit is completed + * + ****************************************************************************/ + +static bool imxrt_txready(struct uart_dev_s *dev) +{ + struct imxrt_uart_s *priv = (struct imxrt_uart_s *)dev->priv; + + return ((imxrt_serialin(priv, IMXRT_LPUART_STAT_OFFSET) & LPUART_STAT_TC) != 0); +} + +/**************************************************************************** + * Name: imxrt_txempty + * + * Description: + * Return true if the transmit reg is empty + * + ****************************************************************************/ + +static bool imxrt_txempty(struct uart_dev_s *dev) +{ + struct imxrt_uart_s *priv = (struct imxrt_uart_s *)dev->priv; + + return ((imxrt_serialin(priv, IMXRT_LPUART_STAT_OFFSET) & LPUART_STAT_TDRE) != 0); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imxrt_earlyserialinit + * + * Description: + * Performs the low level UART initialization early in debug so that the + * serial console will be available during bootup. This must be called + * before up_serialinit. + * + ****************************************************************************/ + +void up_earlyserialinit(void) +{ + /* NOTE: This function assumes that low level hardware configuration + * -- including all clocking and pin configuration -- was performed by the + * function imxrt_lowsetup() earlier in the boot sequence. + */ + + /* Enable the console UART. The other UARTs will be initialized if and + * when they are first opened. + */ + +#ifdef CONSOLE_DEV + CONSOLE_DEV.isconsole = true; + imxrt_setup(&CONSOLE_DEV); +#endif +} + +/**************************************************************************** + * Name: up_serialinit + * + * Description: + * Register serial console and serial ports. This assumes + * that imxrt_earlyserialinit was called previously. + * + ****************************************************************************/ + +void up_serialinit(void) +{ +#ifdef CONSOLE_DEV + (void)uart_register("/dev/console", &CONSOLE_DEV); +#endif + + /* Register all UARTs */ + + (void)uart_register("/dev/ttyS0", &TTYS0_DEV); +#ifdef TTYS1_DEV + (void)uart_register("/dev/ttyS1", &TTYS1_DEV); +#endif +#ifdef TTYS2_DEV + (void)uart_register("/dev/ttyS2", &TTYS2_DEV); +#endif +#ifdef TTYS3_DEV + (void)uart_register("/dev/ttyS3", &TTYS3_DEV); +#endif +#ifdef TTYS4_DEV + (void)uart_register("/dev/ttyS4", &TTYS4_DEV); +#endif +#ifdef TTYS5_DEV + (void)uart_register("/dev/ttyS5", &TTYS5_DEV); +#endif +#ifdef TTYS6_DEV + (void)uart_register("/dev/ttyS6", &TTYS6_DEV); +#endif +#ifdef TTYS7_DEV + (void)uart_register("/dev/ttyS7", &TTYS7_DEV); +#endif +} + +/**************************************************************************** + * Name: up_putc + * + * Description: + * Provide priority, low-level access to support OS debug writes + * + ****************************************************************************/ + +int up_putc(int ch) +{ +#ifdef HAVE_USART_CONSOLE + struct lpc54_dev_s *priv = (struct lpc54_dev_s *)CONSOLE_DEV.priv; + uint32_t ie; + + imxrt_disableuartint(priv, &ie); + + /* Check for LF */ + + if (ch == '\n') + { + /* Add CR */ + + up_lowputc('\r'); + } + + up_lowputc(ch); + imxrt_restoreuartint(priv, intset); +#endif + + return ch; +} + +#else /* USE_SERIALDRIVER */ + +/**************************************************************************** + * Name: up_putc + * + * Description: + * Provide priority, low-level access to support OS debug writes + * + ****************************************************************************/ + +int up_putc(int ch) +{ +#if CONSOLE_LPUART > 0 + /* Check for LF */ + + if (ch == '\n') + { + /* Add CR */ + + up_lowputc('\r'); + } + + up_lowputc(ch); +#endif + + return ch; +} + +#endif /* USE_SERIALDRIVER */ diff --git a/arch/arm/src/imxrt/imxrt_serial.h b/arch/arm/src/imxrt/imxrt_serial.h new file mode 100644 index 00000000000..b9bf4b8288a --- /dev/null +++ b/arch/arm/src/imxrt/imxrt_serial.h @@ -0,0 +1,126 @@ +/**************************************************************************** + * arch/arm/src/imxrt/imxrt_serial.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Ivan Ucherdzhiev + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMXRT_IMX_SERIAL_H +#define __ARCH_ARM_SRC_IMXRT_IMX_SERIAL_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "up_internal.h" +#include "imxrt_config.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: imxrt_earlyserialinit + * + * Description: + * Performs the low level UART initialization early in debug so that the + * serial console will be available during bootup. This must be called + * before up_serialinit. + * + ****************************************************************************/ + +#ifdef USE_EARLYSERIALINIT +void imxrt_earlyserialinit(void); +#endif + +/**************************************************************************** + * Name: uart_earlyserialinit + * + * Description: + * Performs the low level UART initialization early in debug so that the + * serial console will be available during bootup. This must be called + * before up_serialinit. + * + ****************************************************************************/ + +#if defined(USE_EARLYSERIALINIT) && defined(IMXRT_HAVE_LPUART) +void uart_earlyserialinit(void); +#endif + +/**************************************************************************** + * Name: uart_serialinit + * + * Description: + * Register the UART serial console and serial ports. This assumes that + * uart_earlyserialinit was called previously. + * + ****************************************************************************/ + +#ifdef IMXRT_HAVE_LPUART +void uart_serialinit(void); +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_IMXRT_IMX_SERIAL_H */ diff --git a/arch/arm/src/imxrt/imxrt_start.c b/arch/arm/src/imxrt/imxrt_start.c new file mode 100644 index 00000000000..62b20befd0a --- /dev/null +++ b/arch/arm/src/imxrt/imxrt_start.c @@ -0,0 +1,404 @@ +/**************************************************************************** + * arch/arm/src/imxrt/imxrt_start.c + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "up_arch.h" +#include "up_internal.h" + +#include "cache.h" +#ifdef CONFIG_ARCH_FPU +# include "nvic.h" +#endif + +#include "imxrt_clockconfig.h" +#include "imxrt_mpuinit.h" +#include "imxrt_userspace.h" +#include "imxrt_start.h" +#include "imxrt_gpio.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Memory Map ***************************************************************/ +/* 0x2020:0000 - Start of on-chip RAM (OCRAM) and start of .data (_sdata) + * - End of .data (_edata) and start of .bss (_sbss) + * - End of .bss (_ebss) and bottom of idle stack + * - _ebss + CONFIG_IDLETHREAD_STACKSIZE = end of idle stack, + * start of heap. NOTE that the ARM uses a decrement before + * store stack so that the correct initial value is the end of + * the stack + 4; + * 0x2027:ffff - End of OCRAM and end of heap (assuming 512Kb OCRAM) + * + * NOTE: This assumes that all internal RAM is configured for OCRAM (vs. + * ITCM or DTCM). The RAM that holds .data and .bss is called the "Primary + * RAM". Many other configurations are possible, including configurations + * where the primary ram is in external memory. Those are not considered + * here. + */ + +#define IDLE_STACK ((uintptr_t)&_ebss + CONFIG_IDLETHREAD_STACKSIZE - 4) +#define HEAP_BASE ((uintptr_t)&_ebss + CONFIG_IDLETHREAD_STACKSIZE) + +/**************************************************************************** + * Private Function prototypes + ****************************************************************************/ + +#ifdef CONFIG_ARCH_FPU +static inline void imxrt_fpuconfig(void); +#endif +#ifdef CONFIG_STACK_COLORATION +static void go_os_start(void *pv, unsigned int nbytes) + __attribute__ ((naked, no_instrument_function, noreturn)); +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +#ifdef CONFIG_ARMV7M_STACKCHECK +/* we need to get r10 set before we can allow instrumentation calls */ + +void __start(void) __attribute__ ((no_instrument_function)); +#endif + +/**************************************************************************** + * Name: imxrt_fpuconfig + * + * Description: + * Configure the FPU. Relative bit settings: + * + * CPACR: Enables access to CP10 and CP11 + * CONTROL.FPCA: Determines whether the FP extension is active in the + * current context: + * FPCCR.ASPEN: Enables automatic FP state preservation, then the + * processor sets this bit to 1 on successful completion of any FP + * instruction. + * FPCCR.LSPEN: Enables lazy context save of FP state. When this is + * done, the processor reserves space on the stack for the FP state, + * but does not save that state information to the stack. + * + * Software must not change the value of the ASPEN bit or LSPEN bit while + * either: + * + * - the CPACR permits access to CP10 and CP11, that give access to the FP + * extension, or + * - the CONTROL.FPCA bit is set to 1 + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_FPU +#if defined(CONFIG_ARMV7M_CMNVECTOR) && !defined(CONFIG_ARMV7M_LAZYFPU) + +static inline void imxrt_fpuconfig(void) +{ + uint32_t regval; + + /* Set CONTROL.FPCA so that we always get the extended context frame + * with the volatile FP registers stacked above the basic context. + */ + + regval = getcontrol(); + regval |= (1 << 2); + setcontrol(regval); + + /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend + * with the lazy FP context save behavior. Clear FPCCR.ASPEN since we + * are going to turn on CONTROL.FPCA for all contexts. + */ + + regval = getreg32(NVIC_FPCCR); + regval &= ~((1 << 31) | (1 << 30)); + putreg32(regval, NVIC_FPCCR); + + /* Enable full access to CP10 and CP11 */ + + regval = getreg32(NVIC_CPACR); + regval |= ((3 << (2*10)) | (3 << (2*11))); + putreg32(regval, NVIC_CPACR); +} + +#else + +static inline void imxrt_fpuconfig(void) +{ + uint32_t regval; + + /* Clear CONTROL.FPCA so that we do not get the extended context frame + * with the volatile FP registers stacked in the saved context. + */ + + regval = getcontrol(); + regval &= ~(1 << 2); + setcontrol(regval); + + /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend + * with the lazy FP context save behavior. Clear FPCCR.ASPEN since we + * are going to keep CONTROL.FPCA off for all contexts. + */ + + regval = getreg32(NVIC_FPCCR); + regval &= ~((1 << 31) | (1 << 30)); + putreg32(regval, NVIC_FPCCR); + + /* Enable full access to CP10 and CP11 */ + + regval = getreg32(NVIC_CPACR); + regval |= ((3 << (2*10)) | (3 << (2*11))); + putreg32(regval, NVIC_CPACR); +} + +#endif + +#else +# define imxrt_fpuconfig() +#endif + +/**************************************************************************** + * Name: imxrt_tcmenable + * + * Description: + * Enable/disable tightly coupled memories. Size of tightly coupled + * memory regions is controlled by GPNVM Bits 7-8. + * + ****************************************************************************/ + +static inline void imxrt_tcmenable(void) +{ + uint32_t regval; + + ARM_DSB(); + ARM_ISB(); + + /* Enabled/disabled ITCM */ + +#ifdef CONFIG_ARMV7M_ITCM + regval = NVIC_TCMCR_EN | NVIC_TCMCR_RMW | NVIC_TCMCR_RETEN; +#else + regval = getreg32(NVIC_ITCMCR); + regval &= ~NVIC_TCMCR_EN; +#endif + putreg32(regval, NVIC_ITCMCR); + + /* Enabled/disabled DTCM */ + +#ifdef CONFIG_ARMV7M_DTCM + regval = NVIC_TCMCR_EN | NVIC_TCMCR_RMW | NVIC_TCMCR_RETEN; +#else + regval = getreg32(NVIC_DTCMCR); + regval &= ~NVIC_TCMCR_EN; +#endif + putreg32(regval, NVIC_DTCMCR); + + ARM_DSB(); + ARM_ISB(); + +#ifdef CONFIG_ARMV7M_ITCM + /* Copy TCM code from flash to ITCM */ + +#warning Missing logic +#endif +} + +/**************************************************************************** + * Name: go_os_start + * + * Description: + * Set the IDLE stack to the + * + ****************************************************************************/ + +#ifdef CONFIG_STACK_COLORATION +static void go_os_start(void *pv, unsigned int nbytes) +{ + /* Set the IDLE stack to the stack coloration value then jump to + * os_start(). We take extreme care here because were currently + * executing on this stack. + * + * We want to avoid sneak stack access generated by the compiler. + */ + + __asm__ __volatile__ + ( + "\tmovs r1, r1, lsr #2\n" /* R1 = nwords = nbytes >> 2 */ + "\tbeq 2f\n" /* (should not happen) */ + + "\tbic r0, r0, #3\n" /* R0 = Aligned stackptr */ + "\tmovw r2, #0xbeef\n" /* R2 = STACK_COLOR = 0xdeadbeef */ + "\tmovt r2, #0xdead\n" + + "1:\n" /* Top of the loop */ + "\tsub r1, r1, #1\n" /* R1 nwords-- */ + "\tcmp r1, #0\n" /* Check (nwords == 0) */ + "\tstr r2, [r0], #4\n" /* Save stack color word, increment stackptr */ + "\tbne 1b\n" /* Bottom of the loop */ + + "2:\n" + "\tmov r14, #0\n" /* LR = return address (none) */ + "\tb os_start\n" /* Branch to os_start */ + ); +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: _start + * + * Description: + * This is the reset entry point. + * + ****************************************************************************/ + +void __start(void) +{ + const uint32_t *src; + uint32_t *dest; + +#ifdef CONFIG_ARMV7M_STACKCHECK + /* Set the stack limit before we attempt to call any functions */ + + __asm__ volatile ("sub r10, sp, %0" : : "r" (CONFIG_IDLETHREAD_STACKSIZE - 64) : ); +#endif + + /* Clear .bss. We'll do this inline (vs. calling memset) just to be + * certain that there are no issues with the state of global variables. + */ + + for (dest = &_sbss; dest < &_ebss; ) + { + *dest++ = 0; + } + + /* Move the initialized data section from his temporary holding spot in + * FLASH into the correct place in OCRAM. The correct place in OCRAM is + * give by _sdata and _edata. The temporary location is in FLASH at the + * end of all of the other read-only data (.text, .rodata) at _eronly. + */ + + for (src = &_eronly, dest = &_sdata; dest < &_edata; ) + { + *dest++ = *src++; + } + + /* Copy any necessary code sections from FLASH to RAM. The correct + * destination in OCRAM is given by _sramfuncs and _eramfuncs. The + * temporary location is in flash after the data initialization code + * at _framfuncs. This should be done before imxrt_clockconfig() is + * called (in case it has some dependency on initialized C variables). + */ + +#ifdef CONFIG_ARCH_RAMFUNCS + for (src = &_framfuncs, dest = &_sramfuncs; dest < &_eramfuncs; ) + { + *dest++ = *src++; + } +#endif + + /* Configure the UART so that we can get debug output as soon as possible */ + + imxrt_clockconfig(); + imxrt_fpuconfig(); + imxrt_lowsetup(); + + /* Enable/disable tightly coupled memories */ + + imxrt_tcmenable(); + + /* Initialize onboard resources */ + + imxrt_boardinitialize(); + +#ifdef CONFIG_ARM_MPU + /* For the case of the separate user-/kernel-space build, perform whatever + * platform specific initialization of the user memory is required. + * Normally this just means initializing the user space .data and .bss + * segments. + */ + +#ifdef CONFIG_BUILD_PROTECTED + imxrt_userspace(); +#endif + + /* Configure the MPU to permit user-space access to its FLASH and RAM (for + * CONFIG_BUILD_PROTECTED) or to manage cache properties in external + * memory regions. + */ + + imxrt_mpu_initialize(); +#endif + + /* Enable I- and D-Caches */ + + arch_dcache_writethrough(); + arch_enable_icache(); + arch_enable_dcache(); + + /* Perform early serial initialization */ + +#ifdef USE_EARLYSERIALINIT + up_earlyserialinit(); +#endif + + /* Then start NuttX */ + +#ifdef CONFIG_STACK_COLORATION + /* Set the IDLE stack to the coloration value and jump into os_start() */ + + go_os_start((FAR void *)&_ebss, CONFIG_IDLETHREAD_STACKSIZE); +#else + /* Call os_start() */ + + os_start(); + + /* Shouldn't get here */ + + for (; ; ); +#endif +} diff --git a/arch/arm/src/imxrt/imxrt_start.h b/arch/arm/src/imxrt/imxrt_start.h new file mode 100644 index 00000000000..fffcb0f9fa9 --- /dev/null +++ b/arch/arm/src/imxrt/imxrt_start.h @@ -0,0 +1,126 @@ +/************************************************************************************ + * arch/arm/src/imxrt/imxrt_start.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMXRT_IMXRT_START_H +#define __ARCH_ARM_SRC_IMXRT_IMXRT_START_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include + +#include +#include +#include + +#include "up_internal.h" +#include "chip.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/* g_idle_topstack: _sbss is the start of the BSS region as defined by the linker + * script. _ebss lies at the end of the BSS region. The idle task stack starts at + * the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE. The IDLE thread is + * the thread that the system boots on and, eventually, becomes the IDLE, do + * nothing task that runs only when there is nothing else to run. The heap + * continues from there until the end of memory. g_idle_topstack is a read-only + * variable the provides this computed address. + */ + +EXTERN const uintptr_t g_idle_topstack; + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +/************************************************************************************ + * Name: imxrt_lowsetup + * + * Description: + * Called at the very beginning of _start. Performs low level initialization + * including setup of the console UART. This UART done early so that the serial + * console is available for debugging very early in the boot sequence. + * + ************************************************************************************/ + +void imxrt_lowsetup(void); + +/************************************************************************************ + * Name: imxrt_boardinitialize + * + * Description: + * All SAMV7 architectures must provide the following entry point. This entry + * point is called early in the initialization -- after clocking and memory have + * been configured but before caches have been enabled and before any devices have + * been initialized. + * + ************************************************************************************/ + +void imxrt_boardinitialize(void); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_IMXRT_IMXRT_START_H */ diff --git a/arch/arm/src/imxrt/imxrt_timerisr.c b/arch/arm/src/imxrt/imxrt_timerisr.c new file mode 100644 index 00000000000..5ffe8ebf9bb --- /dev/null +++ b/arch/arm/src/imxrt/imxrt_timerisr.c @@ -0,0 +1,139 @@ +/**************************************************************************** + * arch/arm/src/imxrt/imxrt_timerisr.c + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include "nvic.h" +#include "clock/clock.h" +#include "up_internal.h" +#include "up_arch.h" + +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#warning REVISIT these clock settings + +/* Select MCU-specific settings + * + * The SysTick timer is driven by the output of the Main Clock (main_clk). */ + +#define IMXRT_SYSTICK_CLOCK BOARD_CPU_FREQUENCY + +/* The desired timer interrupt frequency is provided by the definition + * CLK_TCK (see include/time.h). CLK_TCK defines the desired number of + * system clock ticks per second. That value is a user configurable setting + * that defaults to 100 (100 ticks per second = 10 MS interval). + */ + +#define SYSTICK_RELOAD ((IMXRT_SYSTICK_CLOCK / CLK_TCK) - 1) + +/* The size of the reload field is 24 bits. Verify that the reload value + * will fit in the reload register. + */ + +#if SYSTICK_RELOAD > 0x00ffffff +# error SYSTICK_RELOAD exceeds the range of the RELOAD register +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: imxrt_timerisr + * + * Description: + * The timer ISR will perform a variety of services for various portions + * of the systems. + * + ****************************************************************************/ + +static int imxrt_timerisr(int irq, uint32_t *regs, void *arg) +{ + /* Process timer interrupt */ + + sched_process_timer(); + return 0; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: arm_timer_initialize + * + * Description: + * This function is called during start-up to initialize the timer + * interrupt. + * + ****************************************************************************/ + +void arm_timer_initialize(void) +{ + uint32_t regval; + + /* Configure SysTick to interrupt at the requested rate */ + + putreg32(SYSTICK_RELOAD, NVIC_SYSTICK_RELOAD); + putreg32(0, NVIC_SYSTICK_CURRENT); + + /* Attach the timer interrupt vector */ + + (void)irq_attach(IMXRT_IRQ_SYSTICK, (xcpt_t)imxrt_timerisr, NULL); + + /* Enable SysTick interrupts */ + + regval = (NVIC_SYSTICK_CTRL_CLKSOURCE | NVIC_SYSTICK_CTRL_TICKINT | + NVIC_SYSTICK_CTRL_ENABLE); + putreg32(regval, NVIC_SYSTICK_CTRL); + + /* And enable the timer interrupt */ + + up_enable_irq(IMXRT_IRQ_SYSTICK); +} diff --git a/arch/arm/src/imxrt/imxrt_userspace.c b/arch/arm/src/imxrt/imxrt_userspace.c new file mode 100644 index 00000000000..6c814aa0f11 --- /dev/null +++ b/arch/arm/src/imxrt/imxrt_userspace.c @@ -0,0 +1,105 @@ +/**************************************************************************** + * arch/arm/src/imxrt/imxrt_userspace.c + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#include "imxrt_mpuinit.h" +#include "imxrt_userspace.h" + +#ifdef CONFIG_BUILD_PROTECTED + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imxrt_userspace + * + * Description: + * For the case of the separate user-/kernel-space build, perform whatever + * platform specific initialization of the user memory is required. + * Normally this just means initializing the user space .data and .bss + * segments. + * + * Assumptions: + * The D-Cache has not yet been enabled. + * + ****************************************************************************/ + +void imxrt_userspace(void) +{ + uint8_t *src; + uint8_t *dest; + uint8_t *end; + + /* Clear all of user-space .bss */ + + DEBUGASSERT(USERSPACE->us_bssstart != 0 && USERSPACE->us_bssend != 0 && + USERSPACE->us_bssstart <= USERSPACE->us_bssend); + + dest = (uint8_t *)USERSPACE->us_bssstart; + end = (uint8_t *)USERSPACE->us_bssend; + + while (dest != end) + { + *dest++ = 0; + } + + /* Initialize all of user-space .data */ + + DEBUGASSERT(USERSPACE->us_datasource != 0 && + USERSPACE->us_datastart != 0 && USERSPACE->us_dataend != 0 && + USERSPACE->us_datastart <= USERSPACE->us_dataend); + + src = (uint8_t *)USERSPACE->us_datasource; + dest = (uint8_t *)USERSPACE->us_datastart; + end = (uint8_t *)USERSPACE->us_dataend; + + while (dest != end) + { + *dest++ = *src++; + } +} + +#endif /* CONFIG_BUILD_PROTECTED */ diff --git a/arch/arm/src/imxrt/imxrt_userspace.h b/arch/arm/src/imxrt/imxrt_userspace.h new file mode 100644 index 00000000000..9aa4a8ffdcc --- /dev/null +++ b/arch/arm/src/imxrt/imxrt_userspace.h @@ -0,0 +1,93 @@ +/************************************************************************************ + * arch/arm/src/imxrt/imxrt_userspace.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMXRT_IMXRT_USERSPACE_H +#define __ARCH_ARM_SRC_IMXRT_IMXRT_USERSPACE_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include + +#include +#include +#include + +#include "up_internal.h" +#include "chip.h" + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +/**************************************************************************** + * Name: imxrt_userspace + * + * Description: + * For the case of the separate user-/kernel-space build, perform whatever + * platform specific initialization of the user memory is required. + * Normally this just means initializing the user space .data and .bss + * segments. + * + ****************************************************************************/ + +#ifdef CONFIG_BUILD_PROTECTED +void imxrt_userspace(void); +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_IMXRT_IMXRT_USERSPACE_H */ diff --git a/arch/arm/src/imxrt/imxrt_wdog.c b/arch/arm/src/imxrt/imxrt_wdog.c new file mode 100644 index 00000000000..22ef611ff22 --- /dev/null +++ b/arch/arm/src/imxrt/imxrt_wdog.c @@ -0,0 +1,95 @@ +/**************************************************************************** + * arch/arm/src/imxrt/imxrt_wdog.c + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Janne Rosberg + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include "up_arch.h" + +#include "chip/imxrt_wdog.h" +#include "imxrt_config.h" +#include /* Include last: has dependencies */ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +/* Configuration ************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imxrt_wdog_disable + * + * Description: + * Disables all watchdogs + * + ****************************************************************************/ + +void imxrt_wdog_disable_all(void) +{ + uint32_t reg; + + reg = getreg32(IMXRT_WDOG1_WCR); + if (reg & WDOG_WCR_WDE) + { + reg &= ~WDOG_WCR_WDE; + putreg32(reg, IMXRT_WDOG1_WCR); + } + + reg = getreg32(IMXRT_WDOG2_WCR); + if (reg & WDOG_WCR_WDE) + { + reg &= ~WDOG_WCR_WDE; + putreg32(reg, IMXRT_WDOG2_WCR); + } + + putreg32(RTWDOG_UPDATE_KEY, IMXRT_RTWDOG_CNT); + putreg32(0xFFFF, IMXRT_RTWDOG_TOVAL); + modifyreg32(IMXRT_RTWDOG_CS, RTWDOG_CS_EN, RTWDOG_CS_UPDATE); + +} diff --git a/arch/arm/src/imxrt/imxrt_wdog.h b/arch/arm/src/imxrt/imxrt_wdog.h new file mode 100644 index 00000000000..9ac00133877 --- /dev/null +++ b/arch/arm/src/imxrt/imxrt_wdog.h @@ -0,0 +1,72 @@ +/**************************************************************************** + * arch/arm/src/imxrt/imxrt_wdog.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Janne Rosberg + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMRT_IMXRT_WDOG_H +#define __ARCH_ARM_SRC_IMRT_IMXRT_WDOG_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include +#include +#include + +#include "up_internal.h" +#include "chip.h" +#include "chip/imxrt_wdog.h" + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: imxrt_wdog_disable + * + * Description: + * Called at the very beginning of _start. Disables all watchdogs + * + ****************************************************************************/ + +void imxrt_wdog_disable_all(void); + +#endif /* __ARCH_ARM_SRC_IMRT_IMXRT_WDOG_H */ diff --git a/configs/Kconfig b/configs/Kconfig index 50a91b63572..4bc54327549 100644 --- a/configs/Kconfig +++ b/configs/Kconfig @@ -258,15 +258,15 @@ config ARCH_BOARD_FREEDOM_KL26Z This is the configuration for the NXP/FreeScale Freedom KL26Z board. This board has the K26Z128VLH4 chip with a built-in SDA debugger. -config ARCH_BOARD_HYMINI_STM32V - bool "HY-Mini STM32v board" - depends on ARCH_CHIP_STM32F103VC +config ARCH_BOARD_IMXRT1050_EVK + bool "NXP i.MX RT 1050 EVK" + depends on ARCH_CHIP_MIMXRT1052DVL6A select ARCH_HAVE_LEDS select ARCH_HAVE_BUTTONS select ARCH_HAVE_IRQBUTTONS ---help--- - A configuration for the HY-Mini STM32v board. This board is based on the - STM32F103VCT6 chip. + This is the board configuratino for the port of NuttX to the NXP i.MXRT + evaluation kit, MIMXRT1050-EVKB. This board features the MIMXRT1052DVL6A MCU. config ARCH_BOARD_INDIUM_F7 bool "Indium-F7" @@ -1627,6 +1627,7 @@ config ARCH_BOARD default "freedom-kl25z" if ARCH_BOARD_FREEDOM_KL25Z default "freedom-kl26z" if ARCH_BOARD_FREEDOM_KL26Z default "hymini-stm32v" if ARCH_BOARD_HYMINI_STM32V + default "imxrt1050-evk" if ARCH_BOARD_IMXRT1050_EVK default "indium-f7" if ARCH_BOARD_INDIUM_F7 default "kwikstik-k40" if ARCH_BOARD_KWIKSTIK_K40 default "launchxl-tms57004" if ARCH_BOARD_LAUNCHXL_TMS57004 @@ -1866,6 +1867,9 @@ endif if ARCH_BOARD_HYMINI_STM32V source "configs/hymini-stm32v/Kconfig" endif +if ARCH_BOARD_IMXRT1050_EVK +source "configs/imxrt1050-evk/Kconfig" +endif if ARCH_BOARD_INDIUM_F7 source "configs/indium-f7/Kconfig" endif diff --git a/configs/imxrt1050-evk/Kconfig b/configs/imxrt1050-evk/Kconfig new file mode 100644 index 00000000000..b5efe40f1de --- /dev/null +++ b/configs/imxrt1050-evk/Kconfig @@ -0,0 +1,7 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_BOARD_IMXRT1050_EVK +endif diff --git a/configs/imxrt1050-evk/README.txt b/configs/imxrt1050-evk/README.txt new file mode 100644 index 00000000000..610677c920a --- /dev/null +++ b/configs/imxrt1050-evk/README.txt @@ -0,0 +1,168 @@ +README +====== + + This README file provides information about the port of NuttX to the NXP + i.MXRT evaluation kit, MIMXRT1050-EVKB. This board features the + MIMXRT1052DVL6A MCU. Some of the features of this board include: + + o Processor + + - MIMXRT1052DVL6A processor + + o Memory + + - 256 Mb SDRAM memory + - 512 Mb Hyper Flash + - Footprint for QSPI Flash + - TF socket for SD card + + o Display and Audio + + - Parallel LCD connector + - Camera connector + - Audio CODEC + - 4-pole audio headphone jack + - External speaker connection + - Microphone + - SPDIF connector + + o Connectivity + + - Micro USB host and OTG connectors + - Ethernet (10/100T) connector + - CAN transceivers + - Arduino® interface + +Contents +======== + + o Serial Console + o LEDs and buttons + o Configurations + - Configuration sub-directories + +Serial Console +============== + + To be provided. + + GPIO_AD_B0_12 LPUART1_TX UART Console + GPIO_AD_B0_13 LPUART1_RX UART Console + +LEDs and buttons +================ + + LEDs + ---- + + There are four LED status indicators located on the EVK Board. The + functions of these LEDs include: + + - Main Power Supply(D3) + Green: DC 5V main supply is normal. + Red: J2 input voltage is over 5.6V. + Off: The board is not powered. + - Reset RED LED(D15) + - OpenSDA LED(D16) + - USER LED(D18) + + Only a single LED, D18, is under software control. It connects to + GPIO_AD_B0_09 which is shared with JTAG_TDI and ENET_RST + + This LED is not used by the board port unless CONFIG_ARCH_LEDS is + defined. In that case, the usage by the board port is defined in + include/board.h and src/sam_autoleds.c. The LED is used to encode + OS-related events as follows: + + ------------------- ----------------------- ------ + SYMBOL Meaning LED + ------------------- ----------------------- ------ + LED_STARTED NuttX has been started OFF + LED_HEAPALLOCATE Heap has been allocated OFF + LED_IRQSENABLED Interrupts enabled OFF + LED_STACKCREATED Idle stack created ON + LED_INIRQ In an interrupt N/C + LED_SIGNAL In a signal handler N/C + LED_ASSERTION An assertion failed N/C + LED_PANIC The system has crashed FLASH + + Thus if the LED is statically on, NuttX has successfully booted and is, + apparently, running normally. If the LED is flashing at approximately + 2Hz, then a fatal error has been detected and the system has halted. + + Buttons + ------- + + There are four user interface switches on the MIMXRT1050 EVK Board: + + - SW1: Power Switch (slide switch) + - SW2: ON/OFF Button + - SW3: Reset button + - SW8: User button + + Only the user button is available to the software. It is sensed on the + WAKEUP pin which will be pulled low when the button is pressed. + +Configurations +============== + + Information Common to All Configurations + ---------------------------------------- + Each i.MX RT 10050 configuration is maintained in a sub-directory and + can be selected as follow: + + tools/configure.sh [OPTIONS] imxrt1050-evk/ + + Where typical options are -l to configure to build on Linux or -c to + configure for Cygwin under Linux. 'tools/configure.sh -h' will show + you all of the options. + + Before building, make sure the PATH environment variable include the + correct path to the directory than holds your toolchain binaries. + + And then build NuttX by simply typing the following. At the conclusion of + the make, the nuttx binary will reside in an ELF file called, simply, nuttx. + + make + + The that is provided above as an argument to the tools/configure.sh + must be is one of the following. + + NOTES: + + 1. These configurations use the mconf-based configuration tool. To + change any of these configurations using that tool, you should: + + a. Build and install the kconfig-mconf tool. See nuttx/README.txt + see additional README.txt files in the NuttX tools repository. + + b. Execute 'make menuconfig' in nuttx/ in order to start the + reconfiguration process. + + 2. Unless stated otherwise, all configurations generate console + output on UART3 (i.e., for the Arduino serial shield). + + 3. All of these configurations are set up to build under Windows using the + "GNU Tools for ARM Embedded Processors" that is maintained by ARM + (unless stated otherwise in the description of the configuration). + + https://developer.arm.com/open-source/gnu-toolchain/gnu-rm + + That toolchain selection can easily be reconfigured using + 'make menuconfig'. Here are the relevant current settings: + + Build Setup: + CONFIG_HOST_WINDOWS=y : Window environment + CONFIG_WINDOWS_CYGWIN=y : Cywin under Windows + + System Type -> Toolchain: + CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIW=y : GNU ARM EABI toolchain + +Configuration sub-directories +----------------------------- + + nsh: + + Configures the NuttShell (nsh) located at examples/nsh. This NSH + configuration is focused on low level, command-line driver testing. + It has no network. diff --git a/configs/imxrt1050-evk/include/board.h b/configs/imxrt1050-evk/include/board.h new file mode 100644 index 00000000000..286c59143a5 --- /dev/null +++ b/configs/imxrt1050-evk/include/board.h @@ -0,0 +1,173 @@ +/************************************************************************************ + * configs/imxrt1050/include/board.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __CONFIGS_IMXRT1050_EVK_INCLUDE_BOARD_H +#define __CONFIGS_IMXRT1050_EVK_INCLUDE_BOARD_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ +/* Clocking *************************************************************************/ + +/* Set VDD_SOC to 1.5V */ + +#define IMXRT_VDD_SOC (0x12) + +/* + * Set Arm PLL (PLL1) to 1200Mhz = (24Mhz * 100) / 2 + * Set Sys PLL (PLL2) to 528Mhz = 1 + * (0 = 20 * 24Mhz = 480Mhz + * 1 = 22 * 24Mhz = 528Mhz) + * + * Arm clock divider = 2 -> Arm Clock = 600Mhz + * AHB clock divider = 1 + * IPG clock divider = 4 + * + */ + +#define BOARD_XTAL_FREQUENCY 24000000 + +#define IMXRT_ARM_PLL_SELECT (100) +#define IMXRT_SYS_PLL_SELECT (1) +#define IMXRT_ARM_CLOCK_DIVIDER (1) +#define IMXRT_AHB_CLOCK_DIVIDER (0) +#define IMXRT_IPG_CLOCK_DIVIDER (3) + +#define BOARD_CPU_FREQUENCY \ + (BOARD_XTAL_FREQUENCY * IMXRT_ARM_PLL_SELECT) / (IMXRT_ARM_CLOCK_DIVIDER + 1) + +/* Define lpuart RF and TX pins + * + * WARNING: imxrt_pinmux.h should be added and used later. + */ + +#define IOMUX_UART (IOMUX_PULL_UP_100K | IOMUX_CMOS_OUTPUT | \ + IOMUX_DRIVE_40OHM | IOMUX_SLEW_FAST | \ + IOMUX_SPEED_MEDIUM | IOMUX_SCHMITT_TRIGGER) +#define GPIO_LPUART1_RX_DATA (GPIO_PERIPH | GPIO_ALT2 | \ + GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_13_INDEX) | \ + IOMUX_UART) +#define GPIO_LPUART1_TX_DATA (GPIO_PERIPH | GPIO_ALT2 | \ + GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_12_INDEX) | \ + IOMUX_UART) + +/* LED definitions ******************************************************************/ +/* There are four LED status indicators located on the EVK Board. The functions of + * these LEDs include: + * + * - Main Power Supply(D3) + * Green: DC 5V main supply is normal. + * Red: J2 input voltage is over 5.6V. + * Off: The board is not powered. + * - Reset RED LED(D15) + * - OpenSDA LED(D16) + * - USER LED(D18) + * + * Only a single LED, D18, is under software control. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_USERLED 0 +#define BOARD_NLEDS 1 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_USERLED_BIT (1 << BOARD_USERLED) + +/* This LED is not used by the board port unless CONFIG_ARCH_LEDS is + * defined. In that case, the usage by the board port is defined in + * include/board.h and src/sam_autoleds.c. The LED is used to encode + * OS-related events as follows: + * + * -------------------- ----------------------------- ------ + * SYMBOL Meaning LED + * -------------------- ----------------------------- ------ */ + +#define LED_STARTED 0 /* NuttX has been started OFF */ +#define LED_HEAPALLOCATE 0 /* Heap has been allocated OFF */ +#define LED_IRQSENABLED 0 /* Interrupts enabled OFF */ +#define LED_STACKCREATED 1 /* Idle stack created ON */ +#define LED_INIRQ 2 /* In an interrupt N/C */ +#define LED_SIGNAL 2 /* In a signal handler N/C */ +#define LED_ASSERTION 2 /* An assertion failed N/C */ +#define LED_PANIC 3 /* The system has crashed FLASH */ +#undef LED_IDLE /* Not used */ + +/* Thus if the LED is statically on, NuttX has successfully booted and is, + * apparently, running normally. If the LED is flashing at approximately + * 2Hz, then a fatal error has been detected and the system has halted. + */ + +/* Button definitions ***************************************************************/ + +/* PIO Disambiguation ***************************************************************/ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __CONFIGS_IMXRT1050_EVK_INCLUDE_BOARD_H */ diff --git a/configs/imxrt1050-evk/nsh/defconfig b/configs/imxrt1050-evk/nsh/defconfig new file mode 100644 index 00000000000..bdc93a15965 --- /dev/null +++ b/configs/imxrt1050-evk/nsh/defconfig @@ -0,0 +1,28 @@ +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH_BOARD_IMXRT1050_EVK=y +CONFIG_ARCH_BOARD="imxrt1050-evk" +CONFIG_ARCH_CHIP_IMXRT=y +CONFIG_ARCH_CHIP_MIMXRT1052DVL6A=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARCH="arm" +CONFIG_BOARD_LOOPSPERMSEC=20000 +CONFIG_EXAMPLES_NSH=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_IMXRT_LPUART1=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LPUART1_SERIAL_CONSOLE=y +CONFIG_MAX_TASKS=16 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_PREALLOC_WDOGS=16 +CONFIG_RAM_SIZE=536870912 +CONFIG_RAM_START=0x20200000 +CONFIG_START_DAY=14 +CONFIG_START_MONTH=3 +CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/configs/imxrt1050-evk/scripts/Make.defs b/configs/imxrt1050-evk/scripts/Make.defs new file mode 100644 index 00000000000..7e6ec4db668 --- /dev/null +++ b/configs/imxrt1050-evk/scripts/Make.defs @@ -0,0 +1,128 @@ +############################################################################ +# configs/imxrt1050-evk/scripts/Make.defs +# +# Copyright (C) 2018 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +include ${TOPDIR}/.config +include ${TOPDIR}/tools/Config.mk +include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs + +ifeq ($(CONFIG_ARMV7M_DTCM),y) + LDSCRIPT = flash-dtcm.ld +else + LDSCRIPT = flash-ocram.ld +endif + +ifeq ($(WINTOOL),y) + # Windows-native toolchains + DIRLINK = $(TOPDIR)/tools/copydir.sh + DIRUNLINK = $(TOPDIR)/tools/unlink.sh + MKDEP = $(TOPDIR)/tools/mkwindeps.sh + ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" + ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" + ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}" +else + # Linux/Cygwin-native toolchain + MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) + ARCHINCLUDES = -I. -isystem $(TOPDIR)/include + ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx + ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT) +endif + +CC = $(CROSSDEV)gcc +CXX = $(CROSSDEV)g++ +CPP = $(CROSSDEV)gcc -E +LD = $(CROSSDEV)ld +STRIP = $(CROSSDEV)strip --strip-unneeded +AR = $(CROSSDEV)ar rcs +NM = $(CROSSDEV)nm +OBJCOPY = $(CROSSDEV)objcopy +OBJDUMP = $(CROSSDEV)objdump + +ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'} +ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1} + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g +endif + +ifneq ($(CONFIG_DEBUG_NOOPT),y) + ARCHOPTIMIZATION += $(MAXOPTIMIZATION) +endif + +ARCHCFLAGS = -fno-builtin +ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -fno-strict-aliasing +ARCHWARNINGSXX = -Wall -Wshadow -Wundef +ARCHDEFINES = +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) +AFLAGS = $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +# Loadable module definitions + +CMODULEFLAGS = $(CFLAGS) -mlong-calls # --target1-abs + +LDMODULEFLAGS = -r -e module_initialize +ifeq ($(WINTOOL),y) + LDMODULEFLAGS += -T "${shell cygpath -w $(TOPDIR)/libc/modlib/gnu-elf.ld}" +else + LDMODULEFLAGS += -T $(TOPDIR)/libc/modlib/gnu-elf.ld +endif + +ASMEXT = .S +OBJEXT = .o +LIBEXT = .a +EXEEXT = + +ifneq ($(CROSSDEV),arm-nuttx-elf-) + LDFLAGS += -nostartfiles -nodefaultlibs +endif +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + LDFLAGS += -g +endif + + +HOSTCC = gcc +HOSTINCLUDES = -I. +HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe +HOSTLDFLAGS = diff --git a/configs/imxrt1050-evk/scripts/flash-ocram.ld b/configs/imxrt1050-evk/scripts/flash-ocram.ld new file mode 100644 index 00000000000..403f9e3e247 --- /dev/null +++ b/configs/imxrt1050-evk/scripts/flash-ocram.ld @@ -0,0 +1,132 @@ +/**************************************************************************** + * configs/imxrt1050-evk/scripts/flash-ocram.ld + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Ivan Ucherdzhiev + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* Specify the memory areas */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x60000000, LENGTH = 0x04000000 + sram (rwx) : ORIGIN = 0x20200000, LENGTH = 0x00040000 + itcm (rwx) : ORIGIN = 0x00000000, LENGTH = 0x00020000 + dtcm (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00020000 +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) + +SECTIONS +{ + .text : + { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : + { + _sinit = ABSOLUTE(.); + *(.init_array .init_array.*) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : + { + *(.ARM.extab*) + } > flash + + __exidx_start = ABSOLUTE(.); + + .ARM.exidx : + { + *(.ARM.exidx*) + } > flash + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : + { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + _edata = ABSOLUTE(.); + } > sram AT > flash + + .ramfunc ALIGN(4): + { + _sramfuncs = ABSOLUTE(.); + *(.ramfunc .ramfunc.*) + _eramfuncs = ABSOLUTE(.); + } > sram AT > flash + + _framfuncs = LOADADDR(.ramfunc); + + .bss : + { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/configs/imxrt1050-evk/src/Makefile b/configs/imxrt1050-evk/src/Makefile new file mode 100644 index 00000000000..c45601fe37d --- /dev/null +++ b/configs/imxrt1050-evk/src/Makefile @@ -0,0 +1,61 @@ +############################################################################ +# configs/imxrt1050-evk/src/Makefile +# +# Copyright (C) 2018 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +-include $(TOPDIR)/Make.defs + +ASRCS = +CSRCS = imxrt_boot.c + +ifeq ($(CONFIG_SAMV7_SDRAMC),y) +CSRCS += imxrt_sdram.c +endif + +ifeq ($(CONFIG_LIB_BOARDCTL),y) +CSRCS += imxrt_appinit.c imxrt_bringup.c +else ifeq ($(CONFIG_BOARD_INITIALIZE),y) +CSRCS += imxrt_bringup.c +endif + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += imxrt_autoleds.c +else +CSRCS += imxrt_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += imxrt_buttons.c +endif + +include $(TOPDIR)/configs/Board.mk diff --git a/configs/imxrt1050-evk/src/imxrt1050-evk.h b/configs/imxrt1050-evk/src/imxrt1050-evk.h new file mode 100644 index 00000000000..755db2f8b02 --- /dev/null +++ b/configs/imxrt1050-evk/src/imxrt1050-evk.h @@ -0,0 +1,115 @@ +/************************************************************************************ + * configs/imxrt1050-evk/src/imxrt1050-evk.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __CONFIGS_IMXRT1050_EVK_SRC_IMXRT1050_EVK_H +#define __CONFIGS_IMXRT1050_EVK_SRC_IMXRT1050_EVK_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include +#include + +#include +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ +/* Configuration ********************************************************************/ + +/* i.MX RT 1050 GPIO Pin Definitions ************************************************/ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public data + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: imxrt_bringup + * + * Description: + * Bring up board features + * + ************************************************************************************/ + +#if defined(CONFIG_LIB_BOARDCTL) || defined(CONFIG_BOARD_INITIALIZE) +int imxrt_bringup(void); +#endif + +/**************************************************************************** + * Name: imxrt_autoled_initialize + * + * Description: + * Initialize NuttX-controlled LED logic + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_LEDS +void imxrt_autoled_initialize(void); +#endif + +/************************************************************************************ + * Name: imxrt_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the SAMV71-XULT board. + * + ************************************************************************************/ + +#ifdef CONFIG_IMXRT_HAVE_SPI +void imxrt_spidev_initialize(void); +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __CONFIGS_IMXRT1050_EVK_SRC_IMXRT1050_EVK_H */ diff --git a/configs/imxrt1050-evk/src/imxrt_appinit.c b/configs/imxrt1050-evk/src/imxrt_appinit.c new file mode 100644 index 00000000000..e3c22582ea2 --- /dev/null +++ b/configs/imxrt1050-evk/src/imxrt_appinit.c @@ -0,0 +1,90 @@ +/**************************************************************************** + * config/imxrt1050-evk/src/imxrt_appinit.c + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#include "imxrt1050-evk.h" + +#ifdef CONFIG_LIB_BOARDCTL + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_app_initialize + * + * Description: + * Perform application specific initialization. This function is never + * called directly from application code, but only indirectly via the + * (non-standard) boardctl() interface using the command BOARDIOC_INIT. + * + * Input Parameters: + * arg - The boardctl() argument is passed to the board_app_initialize() + * implementation without modification. The argument has no + * meaning to NuttX; the meaning of the argument is a contract + * between the board-specific initalization logic and the + * matching application logic. The value cold be such things as a + * mode enumeration value, a set of DIP switch switch settings, a + * pointer to configuration data read from a file or serial FLASH, + * or whatever you would like to do with it. Every implementation + * should accept zero/NULL as a default configuration. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure to indicate the nature of the failure. + * + ****************************************************************************/ + +int board_app_initialize(uintptr_t arg) +{ +#ifndef CONFIG_BOARD_INITIALIZE + /* Perform board initialization */ + + return imxrt_bringup(); +#else + return OK; +#endif +} + +#endif /* CONFIG_LIB_BOARDCTL */ diff --git a/configs/imxrt1050-evk/src/imxrt_autoleds.c b/configs/imxrt1050-evk/src/imxrt_autoleds.c new file mode 100644 index 00000000000..7bebacaeed8 --- /dev/null +++ b/configs/imxrt1050-evk/src/imxrt_autoleds.c @@ -0,0 +1,113 @@ +/**************************************************************************** + * configs/imxrt1050-evk/include/imxrt_autoleds.c + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "imxrt1050-evk.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imxrt_autoled_initialize + * + * Description: + * Initialize NuttX-controlled LED logic + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void imxrt_autoled_initialize(void) +{ + /* Configure LED GPIOs for output */ +#warning Missing logic +} + +/**************************************************************************** + * Name: board_autoled_on + * + * Description: + * Turn on the "logical" LED state + * + * Input Parameters: + * led - Identifies the "logical" LED state (see definitions in + * include/board.h) + * + * Returned Value: + * None + * + ****************************************************************************/ + +void board_autoled_on(int led) +{ +#warning Missing logic +} + +/**************************************************************************** + * Name: board_autoled_off + * + * Description: + * Turn off the "logical" LED state + * + * Input Parameters: + * led - Identifies the "logical" LED state (see definitions in + * include/board.h) + * + * Returned Value: + * None + * + ****************************************************************************/ + +void board_autoled_off(int led) +{ +#warning Missing logic +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/configs/imxrt1050-evk/src/imxrt_boot.c b/configs/imxrt1050-evk/src/imxrt_boot.c new file mode 100644 index 00000000000..5dedc4a12ca --- /dev/null +++ b/configs/imxrt1050-evk/src/imxrt_boot.c @@ -0,0 +1,92 @@ +/**************************************************************************** + * configs/imxrt1050-evk/src/imxrt_boot.c + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "imxrt_start.h" +#include "imxrt1050-evk.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imxrt_boardinitialize + * + * Description: + * All SAMV7 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after clocking and + * memory have been configured but before caches have been enabled and + * before any devices have been initialized. + * + ****************************************************************************/ + +void imxrt_boardinitialize(void) +{ + /* Configure on-board LEDs if LED support has been selected. */ + +#ifdef CONFIG_ARCH_LEDS + imxrt_autoled_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_initialize + * + * Description: + * If CONFIG_BOARD_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_initialize(). board_initialize() will be + * called immediately after up_intitialize() is called and just before the + * initial application is started. This additional initialization phase + * may be used, for example, to initialize board-specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_INITIALIZE +void board_initialize(void) +{ + /* Perform board initialization */ + + (void)imxrt_bringup(); +} +#endif /* CONFIG_BOARD_INITIALIZE */ diff --git a/configs/imxrt1050-evk/src/imxrt_bringup.c b/configs/imxrt1050-evk/src/imxrt_bringup.c new file mode 100644 index 00000000000..b749dec0023 --- /dev/null +++ b/configs/imxrt1050-evk/src/imxrt_bringup.c @@ -0,0 +1,75 @@ +/**************************************************************************** + * config/imxrt1050-evk/src/imxrt_bringup.c + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "imxrt1050-evk.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imxrt_bringup + * + * Description: + * Bring up board features + * + ****************************************************************************/ + +int imxrt_bringup(void) +{ + int ret; + + /* If we got here then perhaps not all initialization was successful, but + * at least enough succeeded to bring-up NSH with perhaps reduced + * capabilities. + */ + + UNUSED(ret); + return OK; +} diff --git a/configs/imxrt1050-evk/src/imxrt_userleds.c b/configs/imxrt1050-evk/src/imxrt_userleds.c new file mode 100644 index 00000000000..20d76109c87 --- /dev/null +++ b/configs/imxrt1050-evk/src/imxrt_userleds.c @@ -0,0 +1,84 @@ +/**************************************************************************** + * configs/imxrt1050-evk/src/imxrt_userleds.c + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "imxrt1050-evk.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +void board_userled_initialize(void) +{ + /* Configure LED GPIOs for output */ +#warning Missing logic +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ +#warning Missing logic +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint8_t ledset) +{ +#warning Missing logic +}