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SAM4S: GPIO, chip characteristics, peripheral Kconfig

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This commit is contained in:
Gregory Nutt
2013-06-11 12:28:31 -06:00
parent da0526f0bd
commit ce8b9c0d3c
13 changed files with 731 additions and 150 deletions
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ChangeLog
+2
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@@ -4945,4 +4945,6 @@
Add SAM4S memory map and interrupt definitions (2013-6-10)
* configs/sam4s-xplained: Add framework for the SAM4S Xplained board.
There is not much there on initial checkin (2013-6-10).
* arch/arm/src/sam34: SAM3S support: GPIO, chip characteristics,
peripheral Kconfig (2013-6-11).
arch/arm/include/sam34/chip.h
+225 -65
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File diff suppressed because it is too large Load Diff
arch/arm/src/sam34/Kconfig
+101 -45
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File diff suppressed because it is too large Load Diff
arch/arm/src/sam34/chip/sam3u_pio.h
+6 -6
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@@ -300,15 +300,15 @@
/* PIO Write Protect Mode Register */
#define PIO_WPMR_WPEN 1 << 0) /* Bit 0: Write Protect Enable */
#define PIO_WPMR_WPKEY_SHIFT 8) /* Bits 8-31: Write Protect KEY */
#define PIO_WPMR_WPKEY_MASK 0xffffff << PIO_WPMR_WPKEY_SHIFT)
#define PIO_WPMR_WPEN (1 << 0) /* Bit 0: Write Protect Enable */
#define PIO_WPMR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect KEY */
#define PIO_WPMR_WPKEY_MASK (0xffffff << PIO_WPMR_WPKEY_SHIFT)
/* PIO Write Protect Status Register */
#define PIO_WPSR_WPVS 1 << 0) /* Bit 0: Write Protect Violation Status */
#define PIO_WPSR_WPVSRC_SHIFT 8) /* Bits 8-23: Write Protect Violation Source */
#define PIO_WPSR_WPVSRC_MASK 0xffff << PIO_WPSR_WPVSRC_SHIFT)
#define PIO_WPSR_WPVS (1 << 0) /* Bit 0: Write Protect Violation Status */
#define PIO_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protect Violation Source */
#define PIO_WPSR_WPVSRC_MASK (0xffff << PIO_WPSR_WPVSRC_SHIFT)
/****************************************************************************************
* Public Types
arch/arm/src/sam34/chip/sam4s_pio.h
+5 -5
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@@ -58,7 +58,7 @@
/* 0x000c: Reserved */
#define SAM_PIO_OER_OFFSET 0x0010 /* Output Enable Register */
#define SAM_PIO_ODR_OFFSET 0x0014 /* Output Disable Register */
#define SAM_PIO_OSR_OFFSET 0x0018 /* utput Status Register */
#define SAM_PIO_OSR_OFFSET 0x0018 /* Output Status Register */
/* 0x001c: Reserved */
#define SAM_PIO_IFER_OFFSET 0x0020 /* Glitch Input Filter Enable Register */
#define SAM_PIO_IFDR_OFFSET 0x0024 /* Glitch Input Filter Disable Register */
@@ -83,13 +83,13 @@
#define SAM_PIO_ABCDSR1_OFFSET 0x0070 /* Peripheral Select Register 1 */
#define SAM_PIO_ABCDSR2_OFFSET 0x0074 /* Peripheral Select Register 2 */
/* 0x0078-0x007c: Reserved */
#define SAM_PIO_IFSCDR_OFFSET 0x0080 /* SInput Filter Slow Clock Disable Register */
#define SAM_PIO_IFSCDR_OFFSET 0x0080 /* Input Filter Slow Clock Disable Register */
#define SAM_PIO_IFSCER_OFFSET 0x0084 /* Input Filter Slow Clock Enable Register */
#define SAM_PIO_IFSCSR_OFFSET 0x0088 /* Input Filter Slow Clock Status Register */
#define SAM_PIO_SCDR_OFFSET 0x008c /* Slow Clock Divider Debouncing Register */
#define SAM_PIO_PPDDR_OFFSET 0x0090 /* Pad Pull-down Enable Register */
#define SAM_PIO_PPDER_OFFSET 0x0094 /* Pad Pull-down Status Register */
#define SAM_PIO_PPDSR_OFFSET 0x0098 /* Input Filter Slow Clock Disable Register */
#define SAM_PIO_PPDDR_OFFSET 0x0090 /* Pad Pull Down Disable Register */
#define SAM_PIO_PPDER_OFFSET 0x0094 /* PIO Pad Pull Down Enable Register */
#define SAM_PIO_PPDSR_OFFSET 0x0098 /* PIO Pad Pull Down Status Register */
/* 0x009c: Reserved */
#define SAM_PIO_OWER_OFFSET 0x00a0 /* Output Write Enable */
#define SAM_PIO_OWDR_OFFSET 0x00a4 /* Output Write Disable */
arch/arm/src/sam34/sam3u_gpio.c
+119 -8
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@@ -1,5 +1,6 @@
/****************************************************************************
* arch/arm/src/sam34/sam3u_gpio.c
* General Purpose Input/Output (GPIO) logic for the SAM3U and SAM4S
*
* Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@@ -111,6 +112,10 @@ static inline int sam_gpiopin(gpio_pinset_t cfgset)
static inline int sam_configinput(uintptr_t base, uint32_t pin,
gpio_pinset_t cfgset)
{
#ifdef GPIO_HAVE_SCHMITT
uint32_t regval;
#endif
/* Disable interrupts on the pin */
putreg32(pin, base + SAM_PIO_IDR_OFFSET);
@@ -126,6 +131,19 @@ static inline int sam_configinput(uintptr_t base, uint32_t pin,
putreg32(pin, base + SAM_PIO_PUDR_OFFSET);
}
#ifdef GPIO_HAVE_PULLDOWN
/* Enable/disable the pull-down as requested */
if ((cfgset & GPIO_CFG_PULLDOWN) != 0)
{
putreg32(pin, base + SAM_PIO_PPDER_OFFSET);
}
else
{
putreg32(pin, base + SAM_PIO_PPDDR_OFFSET);
}
#endif
/* Check if filtering should be enabled */
if ((cfgset & GPIO_CFG_DEGLITCH) != 0)
@@ -137,14 +155,29 @@ static inline int sam_configinput(uintptr_t base, uint32_t pin,
putreg32(pin, base + SAM_PIO_IFDR_OFFSET);
}
#ifdef GPIO_HAVE_SCHMITT
/* Enable/disable the Schmitt trigger */
regval = getreg32(base + SAM_PIO_SCHMITT_OFFSET);
if ((cfgset & GPIO_CFG_PULLDOWN) != 0)
{
regval |= pin;
}
else
{
regval &= ~pin;
}
putreg32(regval, base + SAM_PIO_SCHMITT_OFFSET);
#endif
/* Configure the pin as an input and enable the GPIO function */
putreg32(pin, base + SAM_PIO_ODR_OFFSET);
putreg32(pin, base + SAM_PIO_PER_OFFSET);
/* To-Do: If DEGLITCH is selected, need to configure DIFSR, SCIFSR, and
* registers. This would probably best be done with another, new
* API... perhaps sam_configfilter()
* IFDGSR registers. This would probably best be done with
* another, new API... perhaps sam_configfilter()
*/
return OK;
@@ -176,6 +209,19 @@ static inline int sam_configoutput(uintptr_t base, uint32_t pin,
putreg32(pin, base + SAM_PIO_PUDR_OFFSET);
}
#ifdef GPIO_HAVE_PULLDOWN
/* Enable/disable the pull-down as requested */
if ((cfgset & GPIO_CFG_PULLDOWN) != 0)
{
putreg32(pin, base + SAM_PIO_PPDER_OFFSET);
}
else
{
putreg32(pin, base + SAM_PIO_PPDDR_OFFSET);
}
#endif
/* Enable the open drain driver if requrested */
if ((cfgset & GPIO_CFG_OPENDRAIN) != 0)
@@ -234,7 +280,58 @@ static inline int sam_configperiph(uintptr_t base, uint32_t pin,
putreg32(pin, base + SAM_PIO_PUDR_OFFSET);
}
/* Configure pin, depending upon the peripheral A or B*/
#ifdef GPIO_HAVE_PULLDOWN
/* Enable/disable the pull-down as requested */
if ((cfgset & GPIO_CFG_PULLDOWN) != 0)
{
putreg32(pin, base + SAM_PIO_PPDER_OFFSET);
}
else
{
putreg32(pin, base + SAM_PIO_PPDDR_OFFSET);
}
#endif
#ifdef GPIO_HAVE_PERIPHCD
/* Configure pin, depending upon the peripheral A, B, C or D
*
* PERIPHA: ABCDSR1[n] = 0 ABCDSR2[n] = 0
* PERIPHB: ABCDSR1[n] = 1 ABCDSR2[n] = 0
* PERIPHC: ABCDSR1[n] = 0 ABCDSR2[n] = 1
* PERIPHD: ABCDSR1[n] = 1 ABCDSR2[n] = 1
*/
regval = getreg32(base + SAM_PIO_ABCDSR1_OFFSET);
if ((cfgset & GPIO_MODE_MASK) == GPIO_PERIPHA ||
(cfgset & GPIO_MODE_MASK) == GPIO_PERIPHC)
{
regval &= ~pin;
}
else
{
regval |= pin;
}
putreg32(regval, base + SAM_PIO_ABCDSR1_OFFSET);
regval = getreg32(base + SAM_PIO_ABCDSR2_OFFSET);
if ((cfgset & GPIO_MODE_MASK) == GPIO_PERIPHA ||
(cfgset & GPIO_MODE_MASK) == GPIO_PERIPHB)
{
regval &= ~pin;
}
else
{
regval |= pin;
}
putreg32(regval, base + SAM_PIO_ABCDSR2_OFFSET);
#else
/* Configure pin, depending upon the peripheral A or B:
*
* PERIPHA: ABSR[n] = 0
* PERIPHB: ABSR[n] = 1
*/
regval = getreg32(base + SAM_PIO_ABSR_OFFSET);
if ((cfgset & GPIO_MODE_MASK) == GPIO_PERIPHA)
@@ -246,6 +343,7 @@ static inline int sam_configperiph(uintptr_t base, uint32_t pin,
regval |= pin;
}
putreg32(regval, base + SAM_PIO_ABSR_OFFSET);
#endif
/* Disable PIO functionality */
@@ -375,11 +473,17 @@ int sam_dumpgpio(uint32_t pinset, const char *msg)
lldbg(" PDSR: %08x IMR: %08x ISR: %08x MDSR: %08x\n",
getreg32(base + SAM_PIO_PDSR_OFFSET), getreg32(base + SAM_PIO_IMR_OFFSET),
getreg32(base + SAM_PIO_ISR_OFFSET), getreg32(base + SAM_PIO_MDSR_OFFSET));
lldbg(" PUSR: %08x ABSR: %08x SCIFSR: %08x DIFSR: %08x\n",
getreg32(base + SAM_PIO_PUSR_OFFSET), getreg32(base + SAM_PIO_ABSR_OFFSET),
getreg32(base + SAM_PIO_SCIFSR_OFFSET), getreg32(base + SAM_PIO_DIFSR_OFFSET));
lldbg(" IFDGSR: %08x SCDR: %08x OWSR: %08x AIMMR: %08x\n",
getreg32(base + SAM_PIO_IFDGSR_OFFSET), getreg32(base + SAM_PIO_SCDR_OFFSET),
#if defined(CONFIG_ARCH_CHIP_ATSAM3U)
lldbg(" ABSR: %08x SCIFSR: %08x DIFSR: %08x IFDGSR: %08x\n",
getreg32(base + SAM_PIO_ABSR_OFFSET), getreg32(base + SAM_PIO_SCIFSR_OFFSET),
getreg32(base + SAM_PIO_DIFSR_OFFSET), getreg32(base + SAM_PIO_IFDGSR_OFFSET));
#elif defined(CONFIG_ARCH_CHIP_ATSAM4S)
lldbg(" ABCDSR: %08x %08x IFSCSR: %08x PPDSR: %08x\n",
getreg32(base + SAM_PIO_ABCDSR1_OFFSET), getreg32(base + SAM_PIO_ABCDSR2_OFFSET),
getreg32(base + SAM_PIO_IFSCSR_OFFSET), getreg32(base + SAM_PIOC_PPDSR));
#endif
lldbg(" PUSR: %08x SCDR: %08x OWSR: %08x AIMMR: %08x\n",
getreg32(base + SAM_PIO_PUSR_OFFSET), getreg32(base + SAM_PIO_SCDR_OFFSET),
getreg32(base + SAM_PIO_OWSR_OFFSET), getreg32(base + SAM_PIO_AIMMR_OFFSET));
lldbg(" ESR: %08x LSR: %08x ELSR: %08x FELLSR: %08x\n",
getreg32(base + SAM_PIO_ESR_OFFSET), getreg32(base + SAM_PIO_LSR_OFFSET),
@@ -387,6 +491,13 @@ int sam_dumpgpio(uint32_t pinset, const char *msg)
lldbg(" FRLHSR: %08x LOCKSR: %08x WPMR: %08x WPSR: %08x\n",
getreg32(base + SAM_PIO_FRLHSR_OFFSET), getreg32(base + SAM_PIO_LOCKSR_OFFSET),
getreg32(base + SAM_PIO_WPMR_OFFSET), getreg32(base + SAM_PIO_WPSR_OFFSET));
#if defined(CONFIG_ARCH_CHIP_ATSAM4S)
lldbg(" PCMR: %08x PCIMR: %08x PCISR: %08x PCRHR: %08x\n",
getreg32(base + SAM_PIO_PCMR_OFFSET), getreg32(base + SAM_PIO_PCIMR_OFFSET),
getreg32(base + SAM_PIO_PCISR_OFFSET), getreg32(base + SAM_PIO_PCRHR_OFFSET));
lldbg("SCHMITT: %08x\n",
getreg32(base + SAM_PIO_SCHMITT_OFFSET));
#endif
irqrestore(flags);
return OK;
}
arch/arm/src/sam34/sam3u_gpio.h
+21 -9
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@@ -1,5 +1,6 @@
/************************************************************************************
* arch/arm/src/sam34/sam3u_gpio.h
* General Purpose Input/Output (GPIO) definitions for the SAM3U
*
* Copyright (C) 2009-2011, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@@ -45,16 +46,22 @@
/************************************************************************************
* Definitions
************************************************************************************/
/* Configuration ********************************************************************/
#undef GPIO_HAVE_PULLDOWN
#undef GPIO_HAVE_PERIPHCD
#undef GPIO_HAVE_SCHMITT
/* Bit-encoded input to sam_configgpio() ********************************************/
/* 16-bit Encoding:
* MMCC CII. VPPB BBBB
*
* MMCC CII. VPPB BBBB
*/
/* Input/Output mode:
*
* MM.. .... .... ....
* MM.. .... .... ....
*/
#define GPIO_MODE_SHIFT (14) /* Bits 14-15: GPIO mode */
@@ -65,7 +72,8 @@
# define GPIO_PERIPHB (3 << GPIO_MODE_SHIFT) /* Controlled by periph B signal */
/* These bits set the configuration of the pin:
* ..CC C... .... ....
*
* ..CC C... .... ....
*/
#define GPIO_CFG_SHIFT (11) /* Bits 11-13: GPIO configuration bits */
@@ -76,10 +84,11 @@
# define GPIO_CFG_OPENDRAIN (4 << GPIO_CFG_SHIFT) /* Bit 13: Open drain */
/* Additional interrupt modes:
* .... .II. .... ....
*
* .... .II. .... ....
*/
#define GPIO_INT_SHIFT (9) /* Bits 9-10: GPIO configuration bits */
#define GPIO_INT_SHIFT (9) /* Bits 9-10: GPIO interrupt bits */
#define GPIO_INT_MASK (3 << GPIO_INT_SHIFT)
# define GPIO_INT_LEVEL (1 << 10) /* Bit 10: Level detection interrupt */
# define GPIO_INT_EDGE (0) /* (vs. Edge detection interrupt) */
@@ -89,14 +98,16 @@
# define GPIO_INT_FALLING (0) /* (vs. Falling edge detection interrupt) */
/* If the pin is an GPIO output, then this identifies the initial output value:
* .... .... V... ....
*
* .... .... V... ....
*/
#define GPIO_OUTPUT_SET (1 << 7) /* Bit 7: Inital value of output */
#define GPIO_OUTPUT_CLEAR (0)
/* This identifies the GPIO port:
* .... .... .PP. ....
*
* .... .... .PP. ....
*/
#define GPIO_PORT_SHIFT (5) /* Bit 5-6: Port number */
@@ -106,10 +117,11 @@
# define GPIO_PORT_PIOC (2 << GPIO_PORT_SHIFT)
/* This identifies the bit in the port:
* .... .... ...B BBBB
*
* .... .... ...B BBBB
*/
#define GPIO_PIN_SHIFT 0 /* Bits 0-4: GPIO number: 0-31 */
#define GPIO_PIN_SHIFT 0 /* Bits 0-4: GPIO number: 0-31 */
#define GPIO_PIN_MASK (31 << GPIO_PIN_SHIFT)
#define GPIO_PIN0 (0 << GPIO_PIN_SHIFT)
#define GPIO_PIN1 (1 << GPIO_PIN_SHIFT)
arch/arm/src/sam34/sam4s_gpio.h
+201
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File diff suppressed because it is too large Load Diff
arch/arm/src/sam34/sam_gpio.h
+2
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@@ -51,6 +51,8 @@
# include "sam3u_gpio.h"
#elif defined(CONFIG_ARCH_CHIP_SAM4L)
# include "sam4l_gpio.h"
#elif defined(CONFIG_ARCH_CHIP_SAMSL)
# include "sam4s_gpio.h"
#else
# error Unrecognized SAM architecture
#endif
configs/mikroe-stm32f4/src/mikroe-stm32f4-internal.h
-1
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@@ -190,7 +190,6 @@
GPIO_OUTPUT_SET|GPIO_PORTC|GPIO_PIN7)
#define GPIO_VS1053_DREQ (GPIO_INPUT|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN6)
/****************************************************************************************************
* Public Types
****************************************************************************************************/
configs/sam3u-ek/README.txt
+23 -9
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@@ -313,15 +313,28 @@ SAM3U-EK-specific Configuration Options
Individual subsystems can be enabled:
CONFIG_SAM34_DMA
CONFIG_SAM34_HSMCI
CONFIG_SAM34_NAND
CONFIG_SAM34_SPI
CONFIG_SAM34_UART0
CONFIG_SAM34_USART0
CONFIG_SAM34_USART1
CONFIG_SAM34_USART2
CONFIG_SAM34_USART3
CONFIG_SAM34_RTC - Real Time Clock
CONFIG_SAM34_RTT - Real Time Timer
CONFIG_SAM34_WDT - Watchdog Timer
CONFIG_SAM34_UART0 - UART 0
CONFIG_SAM34_SMC - Static Memory Controller
CONFIG_SAM34_USART0 - USART 0
CONFIG_SAM34_USART1 - USART 1
CONFIG_SAM34_USART2 - USART 2
CONFIG_SAM34_USART3 - USART 3
CONFIG_SAM34_HSMCI - High Speed Multimedia Card Interface
CONFIG_SAM34_TWI0 - Two-Wire Interface 0
CONFIG_SAM34_TWI1 - Two-Wire Interface 1
CONFIG_SAM34_SPI - Serial Peripheral Interface
CONFIG_SAM34_SSC - Synchronous Serial Controller
CONFIG_SAM34_TC0 - Timer Counter 0
CONFIG_SAM34_TC1 - Timer Counter 1
CONFIG_SAM34_TC2 - Timer Counter 2
CONFIG_SAM34_PWM - Pulse Width Modulation Controller
CONFIG_SAM34_ADC12B - 12-bit ADC Controller
CONFIG_SAM34_ADC - 10-bit ADC Controller
CONFIG_SAM34_DMA - DMA Controller
CONFIG_SAM34_UDPHS - USB Device High Speed
Some subsystems can be configured to operate in different ways. The drivers
need to know how to configure the subsystem.
@@ -333,6 +346,7 @@ SAM3U-EK-specific Configuration Options
CONFIG_USART1_ISUART
CONFIG_USART2_ISUART
CONFIG_USART3_ISUART
CONFIG_SAM34_NAND - NAND memory
AT91SAM3U specific device driver settings
configs/sam4l-xplained/README.txt
+2 -2
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@@ -371,9 +371,9 @@ SAM4L Xplained Pro-specific Configuration Options
CONFIG_SAM34_USART1
CONFIG_SAM34_USART2
CONFIG_SAM34_USART3
CONFIG_SAM34_ADCIFE
CONFIG_SAM34_ADC12B
CONFIG_SAM34_DACC
CONFIG_SAM34_ACIFC
CONFIG_SAM34_ACC
CONFIG_SAM34_GLOC
CONFIG_SAM34_ABDACB
CONFIG_SAM34_TRNG
configs/sam4s-xplained/README.txt
+24
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@@ -401,6 +401,30 @@ SAM4S Xplained-specific Configuration Options
Individual subsystems can be enabled:
CONFIG_SAM34_RTC - Real Time Clock
CONFIG_SAM34_RTT - Real Time Timer
CONFIG_SAM34_WDT - Watchdog Timer
CONFIG_SAM34_UART0 - UART 0
CONFIG_SAM34_UART1 - UART 1
CONFIG_SAM34_SMC - Static Memory Controller
CONFIG_SAM34_USART0 - USART 0
CONFIG_SAM34_USART1 - USART 1
CONFIG_SAM34_HSMCI - High Speed Multimedia Card Interface
CONFIG_SAM34_TWI0 - Two-Wire Interface 0
CONFIG_SAM34_TWI1 - Two-Wire Interface 1
CONFIG_SAM34_SSC - Synchronous Serial Controller
CONFIG_SAM34_TC0 - Timer Counter 0
CONFIG_SAM34_TC1 - Timer Counter 1
CONFIG_SAM34_TC2 - Timer Counter 2
CONFIG_SAM34_TC3 - Timer Counter 3
CONFIG_SAM34_TC4 - Timer Counter 4
CONFIG_SAM34_TC5 - Timer Counter 5
CONFIG_SAM34_ADC12B - 12-bit Analog To Digital Converter
CONFIG_SAM34_DACC - Digital To Analog Converter
CONFIG_SAM34_PWM - Pulse Width Modulation
CONFIG_SAM34_CRCCU - CRC Calculation Unit
CONFIG_SAM34_ACC - Analog Comparator
CONFIG_SAM34_UDP - USB Device Port
Some subsystems can be configured to operate in different ways. The drivers
need to know how to configure the subsystem.