Costmetic fixes to README and some comments

This commit is contained in:
Gregory Nutt
2014-03-30 11:34:18 -06:00
parent b0c302ea06
commit cdcf4f3ad6
4 changed files with 14 additions and 2 deletions
+6
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@@ -327,6 +327,12 @@ Writing to FLASH using SAM-BA
Running NuttX from NAND FLASH Running NuttX from NAND FLASH
============================= =============================
- Boot sequence
- NAND FLASH Memory Map
- Programming the AT91Boostrap Binary
- Programming U-Boot
- Load NuttX with U-Boot on AT91 boards
Boot sequence Boot sequence
------------- -------------
@@ -52,7 +52,7 @@
* booting from SDRAM, NuttX is loaded in SDRAM by an intermediate bootloader. That * booting from SDRAM, NuttX is loaded in SDRAM by an intermediate bootloader. That
* bootloader had to have already configured the PLL and SDRAM for proper operation. * bootloader had to have already configured the PLL and SDRAM for proper operation.
* *
* In this case, we don not reconfigure the clocking. Rather, we need to query * In this case, we do not reconfigure the clocking. Rather, we need to query
* the register settings to determine the clock frequencies. We can only assume that * the register settings to determine the clock frequencies. We can only assume that
* the Main clock source in the on-board 12MHz crystal. * the Main clock source in the on-board 12MHz crystal.
*/ */
+6
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@@ -448,6 +448,12 @@ Creating and Using NORBOOT
Running NuttX from NAND FLASH Running NuttX from NAND FLASH
============================= =============================
- Boot sequence
- NAND FLASH Memory Map
- Programming the AT91Boostrap Binary
- Programming U-Boot
- Load NuttX with U-Boot on AT91 boards
Boot sequence Boot sequence
------------- -------------
+1 -1
View File
@@ -52,7 +52,7 @@
* booting from SDRAM, NuttX is loaded in SDRAM by an intermediate bootloader. That * booting from SDRAM, NuttX is loaded in SDRAM by an intermediate bootloader. That
* bootloader had to have already configured the PLL and SDRAM for proper operation. * bootloader had to have already configured the PLL and SDRAM for proper operation.
* *
* In this case, we don not reconfigure the clocking. Rather, we need to query * In this case, we do not reconfigure the clocking. Rather, we need to query
* the register settings to determine the clock frequencies. We can only assume that * the register settings to determine the clock frequencies. We can only assume that
* the Main clock source in the on-board 12MHz crystal. * the Main clock source in the on-board 12MHz crystal.
*/ */