diff --git a/configs/sama5d3-xplained/README.txt b/configs/sama5d3-xplained/README.txt
index 2ef0426f043..62c4a2ecfb6 100644
--- a/configs/sama5d3-xplained/README.txt
+++ b/configs/sama5d3-xplained/README.txt
@@ -327,6 +327,12 @@ Writing to FLASH using SAM-BA
 Running NuttX from NAND FLASH
 =============================
 
+  - Boot sequence
+  - NAND FLASH Memory Map
+  - Programming the AT91Boostrap Binary
+  - Programming U-Boot
+  - Load NuttX with U-Boot on AT91 boards
+
 Boot sequence
 -------------
 
diff --git a/configs/sama5d3-xplained/include/board_sdram.h b/configs/sama5d3-xplained/include/board_sdram.h
index 28705d72af4..61d25155b5b 100644
--- a/configs/sama5d3-xplained/include/board_sdram.h
+++ b/configs/sama5d3-xplained/include/board_sdram.h
@@ -52,7 +52,7 @@
  * booting from SDRAM, NuttX is loaded in SDRAM by an intermediate bootloader.  That
  * bootloader had to have already configured the PLL and SDRAM for proper operation.
  *
- * In this case, we don not reconfigure the clocking.  Rather, we need to query
+ * In this case, we do not reconfigure the clocking.  Rather, we need to query
  * the register settings to determine the clock frequencies.  We can only assume that
  * the Main clock source in the on-board 12MHz crystal.
  */
diff --git a/configs/sama5d3x-ek/README.txt b/configs/sama5d3x-ek/README.txt
index 1069d4519a4..5e6399fc1e4 100644
--- a/configs/sama5d3x-ek/README.txt
+++ b/configs/sama5d3x-ek/README.txt
@@ -448,6 +448,12 @@ Creating and Using NORBOOT
 Running NuttX from NAND FLASH
 =============================
 
+  - Boot sequence
+  - NAND FLASH Memory Map
+  - Programming the AT91Boostrap Binary
+  - Programming U-Boot
+  - Load NuttX with U-Boot on AT91 boards
+
 Boot sequence
 -------------
 
diff --git a/configs/sama5d3x-ek/include/board_sdram.h b/configs/sama5d3x-ek/include/board_sdram.h
index c870513f2ec..f7e8b8015a8 100644
--- a/configs/sama5d3x-ek/include/board_sdram.h
+++ b/configs/sama5d3x-ek/include/board_sdram.h
@@ -52,7 +52,7 @@
  * booting from SDRAM, NuttX is loaded in SDRAM by an intermediate bootloader.  That
  * bootloader had to have already configured the PLL and SDRAM for proper operation.
  *
- * In this case, we don not reconfigure the clocking.  Rather, we need to query
+ * In this case, we do not reconfigure the clocking.  Rather, we need to query
  * the register settings to determine the clock frequencies.  We can only assume that
  * the Main clock source in the on-board 12MHz crystal.
  */