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arch/arm/src/tiva: Add cc13xx startup logic, rename up_lowsetup->tiva_lowsetup, fixes to cc13xx GPIO header files, break up tiva_timer.h to support future cc13xx timer register definitions, cc13xx has no sysctl block.

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This commit is contained in:
Gregory Nutt
2018-12-05 09:11:55 -06:00
parent 428b625428
commit cdb6e16ad3
17 changed files with 2583 additions and 871 deletions
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arch/arm/src/tiva/Make.defs
+7 -7
View File
@@ -83,19 +83,19 @@ CMN_CSRCS += up_allocateheap.c
endif
CHIP_ASRCS =
CHIP_CSRCS = tiva_allocateheap.c tiva_start.c tiva_irq.c tiva_gpioirq.c
CHIP_CSRCS += tiva_lowputc.c tiva_serial.c tiva_ssi.c
CHIP_CSRCS = tiva_allocateheap.c tiva_irq.c tiva_gpioirq.c tiva_lowputc.c
CHIP_CSRCS += tiva_serial.c tiva_ssi.c
ifeq ($(CONFIG_ARCH_CHIP_LM3S),y)
CHIP_CSRCS += lm3s_gpio.c
CHIP_CSRCS += tiva_start.c lm3s_gpio.c
else ifeq ($(CONFIG_ARCH_CHIP_LM4F),y)
CHIP_CSRCS += lm4f_gpio.c
CHIP_CSRCS += tiva_start.c lm4f_gpio.c
else ifeq ($(CONFIG_ARCH_CHIP_TM4C),y)
CHIP_CSRCS += tm4c_gpio.c
CHIP_CSRCS += tiva_start.c tm4c_gpio.c
else ifeq ($(CONFIG_ARCH_CHIP_CC13X0),y)
CHIP_CSRCS += cc13c0_gpio.c
CHIP_CSRCS += cc13xx_start.c cc13c0_gpio.c
else ifeq ($(CONFIG_ARCH_CHIP_CC13X2),y)
CHIP_CSRCS += cc13x2_cc26x2_gpio.c
CHIP_CSRCS += cc13xx_start.c cc13x2_cc26x2_gpio.c
endif
ifeq ($(CONFIG_DEBUG_GPIO_INFO),y)
arch/arm/src/tiva/cc13xx/cc13xx_start.c
+293
View File
@@ -0,0 +1,293 @@
/****************************************************************************
* arch/arm/src/tiva/cc13xx/cc13x_start.c
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <assert.h>
#include <debug.h>
#include <nuttx/init.h>
#ifdef CONFIG_ARCH_FPU
# include "nvic.h"
#endif
#include "up_arch.h"
#include "up_internal.h"
#include "tiva_lowputc.h"
#include "tiva_userspace.h"
#include "tiva_eeprom.h"
#include "tiva_start.h"
#include <arch/board/board.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* .data is positioned first in the primary RAM followed immediately by .bss.
* The IDLE thread stack lies just after .bss and has size give by
* CONFIG_IDLETHREAD_STACKSIZE; The heap then begins just after the IDLE.
* ARM EABI requires 64 bit stack alignment.
*/
#define IDLE_STACKSIZE (CONFIG_IDLETHREAD_STACKSIZE & ~7)
#define IDLE_STACK ((uintptr_t)&_ebss + IDLE_STACKSIZE)
#define HEAP_BASE ((uintptr_t)&_ebss + IDLE_STACKSIZE)
/****************************************************************************
* Public Data
****************************************************************************/
/* g_idle_topstack: _sbss is the start of the BSS region as defined by the
* linker script. _ebss lies at the end of the BSS region. The idle task
* stack starts at the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE.
* The IDLE thread is the thread that the system boots on and, eventually,
* becomes the IDLE, do nothing task that runs only when there is nothing
* else to run. The heap continues from there until the end of memory.
* g_idle_topstack is a read-only variable the provides this computed
* address.
*/
const uintptr_t g_idle_topstack = HEAP_BASE;
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: showprogress
*
* Description:
* Print a character on the UART to show boot status.
*
****************************************************************************/
#ifdef CONFIG_DEBUG_FEATURES
# define showprogress(c) up_lowputc(c)
#else
# define showprogress(c)
#endif
/****************************************************************************
* Name: tiva_fpuconfig
*
* Description:
* Configure the FPU. Relative bit settings:
*
* CPACR: Enables access to CP10 and CP11
* CONTROL.FPCA: Determines whether the FP extension is active in the
* current context:
* FPCCR.ASPEN: Enables automatic FP state preservation, then the
* processor sets this bit to 1 on successful completion of any FP
* instruction.
* FPCCR.LSPEN: Enables lazy context save of FP state. When this is
* done, the processor reserves space on the stack for the FP state,
* but does not save that state information to the stack.
*
* Software must not change the value of the ASPEN bit or LSPEN bit while either:
* - the CPACR permits access to CP10 and CP11, that give access to the FP
* extension, or
* - the CONTROL.FPCA bit is set to 1
*
****************************************************************************/
#ifdef CONFIG_ARCH_FPU
#ifndef CONFIG_ARMV7M_LAZYFPU
static inline void tiva_fpuconfig(void)
{
uint32_t regval;
/* Set CONTROL.FPCA so that we always get the extended context frame
* with the volatile FP registers stacked above the basic context.
*/
regval = getcontrol();
regval |= (1 << 2);
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
* are going to turn on CONTROL.FPCA for all contexts.
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~((1 << 31) | (1 << 30));
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
putreg32(regval, NVIC_CPACR);
}
#else
static inline void tiva_fpuconfig(void)
{
uint32_t regval;
/* Clear CONTROL.FPCA so that we do not get the extended context frame
* with the volatile FP registers stacked in the saved context.
*/
regval = getcontrol();
regval &= ~(1 << 2);
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
* with the lazy FP context save behavior. Clear FPCCR.ASPEN since we
* are going to keep CONTROL.FPCA off for all contexts.
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~((1 << 31) | (1 << 30));
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
putreg32(regval, NVIC_CPACR);
}
#endif
#else
# define tiva_fpuconfig()
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: _start
*
* Description:
* This is the reset entry point.
*
****************************************************************************/
void __start(void)
{
#ifdef CONFIG_BOOT_RUNFROMFLASH
const uint32_t *src;
#endif
uint32_t *dest;
/* Perform the necessary trim of the device which is not done in boot code. */
cc13x2_cc26x2_trim_device();
/* Configure the UART so that we can get debug output as soon as possible */
tiva_lowsetup();
tiva_fpuconfig();
showprogress('A');
/* Clear .bss. We'll do this inline (vs. calling memset) just to be
* certain that there are no issues with the state of global variables.
*/
for (dest = &_sbss; dest < &_ebss; )
{
*dest++ = 0;
}
showprogress('B');
#ifdef CONFIG_BOOT_RUNFROMFLASH
/* Move the initialized data section from his temporary holding spot in
* FLASH into the correct place in SRAM. The correct place in SRAM is
* give by _sdata and _edata. The temporary location is in FLASH at the
* end of all of the other read-only data (.text, .rodata) at _eronly.
*/
for (src = &_eronly, dest = &_sdata; dest < &_edata; )
{
*dest++ = *src++;
}
showprogress('C');
#endif
#ifdef USE_EARLYSERIALINIT
/* Perform early serial initialization */
up_earlyserialinit();
showprogress('D');
#endif
#ifdef CONFIG_BUILD_PROTECTED
/* For the case of the separate user-/kernel-space build, perform whatever
* platform specific initialization of the user memory is required.
* Normally this just means initializing the user space .data and .bss
* segments.
*/
tiva_userspace();
showprogress('E');
#endif
/* Initialize onboard resources */
tiva_boardinitialize();
showprogress('F');
#ifdef CONFIG_TIVA_EEPROM
/*Initialize the EEPROM */
tiva_eeprom_initialize();
#endif
/* Then start NuttX */
showprogress('\r');
showprogress('\n');
os_start();
/* Shouldn't get here */
for (; ; );
}
arch/arm/src/tiva/common/tiva_lowputc.c
+2 -2
View File
@@ -249,7 +249,7 @@ void up_lowputc(char ch)
}
/****************************************************************************
* Name: up_lowsetup
* Name: tiva_lowsetup
*
* Description:
* This performs basic initialization of the UART used for the serial
@@ -258,7 +258,7 @@ void up_lowputc(char ch)
*
****************************************************************************/
void up_lowsetup(void)
void tiva_lowsetup(void)
{
#if defined(HAVE_SERIAL_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG)
uint32_t ctl;
arch/arm/src/tiva/common/tiva_serial.c
+2 -2
View File
@@ -731,7 +731,7 @@ static void up_set_format(struct uart_dev_s *dev)
bool was_active;
/* Note: The logic here depends on the fact that that the UART module
* was enabled and the GPIOs were configured in up_lowsetup().
* was enabled and the GPIOs were configured in tiva_lowsetup().
*/
/* Disable the UART by clearing the UARTEN bit in the UART CTL register */
@@ -1327,7 +1327,7 @@ static bool up_txempty(struct uart_dev_s *dev)
void up_earlyserialinit(void)
{
/* NOTE: All GPIO configuration for the UARTs was performed in
* up_lowsetup
* tiva_lowsetup
*/
/* Disable all UARTS */
arch/arm/src/tiva/common/tiva_start.c
+6 -5
View File
@@ -44,7 +44,6 @@
#include <debug.h>
#include <nuttx/init.h>
#include <arch/board/board.h>
#ifdef CONFIG_ARCH_FPU
# include "nvic.h"
@@ -59,6 +58,8 @@
#include "tiva_eeprom.h"
#include "tiva_start.h"
#include <arch/board/board.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
@@ -219,7 +220,7 @@ void __start(void)
/* Configure the UART so that we can get debug output as soon as possible */
tiva_clock_configure();
up_lowsetup();
tiva_lowsetup();
tiva_fpuconfig();
showprogress('A');
@@ -249,20 +250,20 @@ void __start(void)
showprogress('C');
#endif
#ifdef USE_EARLYSERIALINIT
/* Perform early serial initialization */
#ifdef USE_EARLYSERIALINIT
up_earlyserialinit();
#endif
showprogress('D');
#endif
#ifdef CONFIG_BUILD_PROTECTED
/* For the case of the separate user-/kernel-space build, perform whatever
* platform specific initialization of the user memory is required.
* Normally this just means initializing the user space .data and .bss
* segments.
*/
#ifdef CONFIG_BUILD_PROTECTED
tiva_userspace();
showprogress('E');
#endif
arch/arm/src/tiva/hardware/cc13x0/cc13x0_gpio.h
+41 -41
View File
@@ -48,76 +48,76 @@
/* GPIO Register Offsets ************************************************************/
#define TIVA_GPIO_DOUT_OFFSET(n) ((n) & ~3)
# define TIVA_GPIO_DOUT3_0_OFFSET 0x0000 /* Data Out 0 to 3 */
# define TIVA_GPIO_DOUT7_4_OFFSET 0x0004 /* Data Out 4 to 7 */
# define TIVA_GPIO_DOUT11_8_OFFSET 0x0008 /* Data Out 8 to 11 */
# define TIVA_GPIO_DOUT15_12_OFFSET 0x000c /* Data Out 12 to 15 */
# define TIVA_GPIO_DOUT19_16_OFFSET 0x0010 /* Data Out 16 to 19 */
# define TIVA_GPIO_DOUT23_20_OFFSET 0x0014 /* Data Out 20 to 23 */
# define TIVA_GPIO_DOUT27_24_OFFSET 0x0018 /* Data Out 24 to 27 */
# define TIVA_GPIO_DOUT31_28_OFFSET 0x001c /* Data Out 28 to 31 */
#define TIVA_GPIO_DOUT_OFFSET 0x0080 /* Data Output for DIO 0 to 31 */
#define TIVA_GPIO_DOUTSET_OFFSET 0x0090 /* Data Out Set */
#define TIVA_GPIO_DOUTCLR_OFFSET 0x00a0 /* Data Out Clear */
#define TIVA_GPIO_DOUTTGL_OFFSET 0x00b0 /* Data Out Toggle */
#define TIVA_GPIO_DIN_OFFSET 0x00c0 /* Data Input from DIO 0 to 31 */
#define TIVA_GPIO_DOE_OFFSET 0x00d0 /* Data Output Enable for DIO 0 to 31 */
#define TIVA_GPIO_EVFLAGS_OFFSET 0x00e0 /* Event Register for DIO 0 to 31 */
#define TIVA_GPIO_DOUT_PIN_OFFSET(n) ((n) & ~3)
# define TIVA_GPIO_DOUT_PIN3_0_OFFSET 0x0000 /* Data Out 0 to 3 */
# define TIVA_GPIO_DOUT_PIN7_4_OFFSET 0x0004 /* Data Out 4 to 7 */
# define TIVA_GPIO_DOUT_PIN11_8_OFFSET 0x0008 /* Data Out 8 to 11 */
# define TIVA_GPIO_DOUT_PIN15_12_OFFSET 0x000c /* Data Out 12 to 15 */
# define TIVA_GPIO_DOUT_PIN19_16_OFFSET 0x0010 /* Data Out 16 to 19 */
# define TIVA_GPIO_DOUT_PIN23_20_OFFSET 0x0014 /* Data Out 20 to 23 */
# define TIVA_GPIO_DOUT_PIN27_24_OFFSET 0x0018 /* Data Out 24 to 27 */
# define TIVA_GPIO_DOUT_PIN31_28_OFFSET 0x001c /* Data Out 28 to 31 */
#define TIVA_GPIO_DOUT_OFFSET 0x0080 /* Data Output for DIO 0 to 31 */
#define TIVA_GPIO_DOUTSET_OFFSET 0x0090 /* Data Out Set */
#define TIVA_GPIO_DOUTCLR_OFFSET 0x00a0 /* Data Out Clear */
#define TIVA_GPIO_DOUTTGL_OFFSET 0x00b0 /* Data Out Toggle */
#define TIVA_GPIO_DIN_OFFSET 0x00c0 /* Data Input from DIO 0 to 31 */
#define TIVA_GPIO_DOE_OFFSET 0x00d0 /* Data Output Enable for DIO 0 to 31 */
#define TIVA_GPIO_EVFLAGS_OFFSET 0x00e0 /* Event Register for DIO 0 to 31 */
/* GPIO Register Addresses **********************************************************/
#define TIVA_GPIO_DOUT_BASE(n) (TIVA_GPIO_BASE + TIVA_GPIO_DOUT_OFFSET(n))
# define TIVA_GPIO_DOUT3_0_OFFSET (TIVA_GPIO_BASE + TIVA_GPIO_DOUT3_0_OFFSET)
# define TIVA_GPIO_DOUT7_4_OFFSET (TIVA_GPIO_BASE + TIVA_GPIO_DOUT7_4_OFFSET)
# define TIVA_GPIO_DOUT11_8_OFFSET (TIVA_GPIO_BASE + TIVA_GPIO_DOUT11_8_OFFSET)
# define TIVA_GPIO_DOUT15_12_OFFSET (TIVA_GPIO_BASE + TIVA_GPIO_DOUT15_12_OFFSET)
# define TIVA_GPIO_DOUT19_16_OFFSET (TIVA_GPIO_BASE + TIVA_GPIO_DOUT19_16_OFFSET)
# define TIVA_GPIO_DOUT23_20_OFFSET (TIVA_GPIO_BASE + TIVA_GPIO_DOUT23_20_OFFSET)
# define TIVA_GPIO_DOUT27_24_OFFSET (TIVA_GPIO_BASE + TIVA_GPIO_DOUT27_24_OFFSET)
# define TIVA_GPIO_DOUT31_28_OFFSET (TIVA_GPIO_BASE + TIVA_GPIO_DOUT31_28_OFFSET)
#define TIVA_GPIO_DOUT_OFFSET (TIVA_GPIO_BASE + TIVA_GPIO_DOUT_OFFSET)
#define TIVA_GPIO_DOUTSET_OFFSET (TIVA_GPIO_BASE + TIVA_GPIO_DOUTSET_OFFSET)
#define TIVA_GPIO_DOUTCLR_OFFSET (TIVA_GPIO_BASE + TIVA_GPIO_DOUTCLR_OFFSET)
#define TIVA_GPIO_DOUTTGL_OFFSET (TIVA_GPIO_BASE + TIVA_GPIO_DOUTTGL_OFFSET)
#define TIVA_GPIO_DIN_OFFSET (TIVA_GPIO_BASE + TIVA_GPIO_DIN_OFFSET)
#define TIVA_GPIO_DOE_OFFSET (TIVA_GPIO_BASE + TIVA_GPIO_DOE_OFFSET)
#define TIVA_GPIO_EVFLAGS_OFFSET (TIVA_GPIO_BASE + TIVA_GPIO_EVFLAGS_OFFSET)
#define TIVA_GPIO_DOUT_PIN_BASE(n) (TIVA_GPIO_BASE + TIVA_GPIO_DOUT_PIN_OFFSET(n))
# define TIVA_GPIO_DOUT_PIN3_0 (TIVA_GPIO_BASE + TIVA_GPIO_DOUT_PIN3_0_OFFSET)
# define TIVA_GPIO_DOUT_PIN7_4 (TIVA_GPIO_BASE + TIVA_GPIO_DOUT_PIN7_4_OFFSET)
# define TIVA_GPIO_DOUT_PIN11_8 (TIVA_GPIO_BASE + TIVA_GPIO_DOUT_PIN11_8_OFFSET)
# define TIVA_GPIO_DOUT_PIN15_12 (TIVA_GPIO_BASE + TIVA_GPIO_DOUT_PIN15_12_OFFSET)
# define TIVA_GPIO_DOUT_PIN19_16 (TIVA_GPIO_BASE + TIVA_GPIO_DOUT_PIN19_16_OFFSET)
# define TIVA_GPIO_DOUT_PIN23_20 (TIVA_GPIO_BASE + TIVA_GPIO_DOUT_PIN23_20_OFFSET)
# define TIVA_GPIO_DOUT_PIN27_24 (TIVA_GPIO_BASE + TIVA_GPIO_DOUT_PIN27_24_OFFSET)
# define TIVA_GPIO_DOUT_PIN31_28 (TIVA_GPIO_BASE + TIVA_GPIO_DOUT_PIN31_28_OFFSET)
#define TIVA_GPIO_DOUT (TIVA_GPIO_BASE + TIVA_GPIO_DOUT_OFFSET)
#define TIVA_GPIO_DOUTSET (TIVA_GPIO_BASE + TIVA_GPIO_DOUTSET_OFFSET)
#define TIVA_GPIO_DOUTCLR (TIVA_GPIO_BASE + TIVA_GPIO_DOUTCLR_OFFSET)
#define TIVA_GPIO_DOUTTGL (TIVA_GPIO_BASE + TIVA_GPIO_DOUTTGL_OFFSET)
#define TIVA_GPIO_DIN (TIVA_GPIO_BASE + TIVA_GPIO_DIN_OFFSET)
#define TIVA_GPIO_DOE (TIVA_GPIO_BASE + TIVA_GPIO_DOE_OFFSET)
#define TIVA_GPIO_EVFLAGS (TIVA_GPIO_BASE + TIVA_GPIO_EVFLAGS_OFFSET)
/* GPIO Register Bitfield Definitions ***********************************************/
/* Data Out n to n + 3 */
#define GPIO_DOUT_SHIFT(n) (((n) & 3) << 8)
#define GPIO_DOUT_VALUE(n) (1 << GPIO_DOUT_SHIFT(n))
#define GPIO_DOUT_SHIFT(n) (((n) & 3) << 8)
#define GPIO_DOUT_VALUE(n) (1 << GPIO_DOUT_SHIFT(n))
/* Data Output for DIO 0 to 31 */
#define GPIO_DOUT(n) (1 << (n))
#define GPIO_DOUT(n) (1 << (n))
/* Data Out Set */
#define GPIO_DOUTSET(n) (1 << (n))
#define GPIO_DOUTSET(n) (1 << (n))
/* Data Out Clear */
#define GPIO_DOUTCLR(n) (1 << (n))
#define GPIO_DOUTCLR(n) (1 << (n))
/* Data Out Toggle */
#define GPIO_DOUTTGL(n) (1 << (n))
#define GPIO_DOUTTGL(n) (1 << (n))
/* Data Input from DIO 0 to 31 */
#define GPIO_DIN(n) (1 << (n))
#define GPIO_DIN(n) (1 << (n))
/* Data Output Enable for DIO 0 to 31 */
#define GPIO_DOE(n) (1 << (n))
#define GPIO_DOE(n) (1 << (n))
/* Event Register for DIO 0 to 31 */
#define GPIO_EVFLAGS(n) (1 << (n))
#define GPIO_EVFLAGS(n) (1 << (n))
/************************************************************************************
* Public Types
arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_gpio.h
+41 -41
View File
@@ -48,76 +48,76 @@
/* GPIO Register Offsets ************************************************************/
#define TIVA_GPIO_DOUT_OFFSET(n) ((n) & ~3)
# define TIVA_GPIO_DOUT3_0_OFFSET 0x0000 /* Data Out 0 to 3 */
# define TIVA_GPIO_DOUT7_4_OFFSET 0x0004 /* Data Out 4 to 7 */
# define TIVA_GPIO_DOUT11_8_OFFSET 0x0008 /* Data Out 8 to 11 */
# define TIVA_GPIO_DOUT15_12_OFFSET 0x000c /* Data Out 12 to 15 */
# define TIVA_GPIO_DOUT19_16_OFFSET 0x0010 /* Data Out 16 to 19 */
# define TIVA_GPIO_DOUT23_20_OFFSET 0x0014 /* Data Out 20 to 23 */
# define TIVA_GPIO_DOUT27_24_OFFSET 0x0018 /* Data Out 24 to 27 */
# define TIVA_GPIO_DOUT31_28_OFFSET 0x001c /* Data Out 28 to 31 */
#define TIVA_GPIO_DOUT_OFFSET 0x0080 /* Data Output for DIO 0 to 31 */
#define TIVA_GPIO_DOUTSET_OFFSET 0x0090 /* Data Out Set */
#define TIVA_GPIO_DOUTCLR_OFFSET 0x00a0 /* Data Out Clear */
#define TIVA_GPIO_DOUTTGL_OFFSET 0x00b0 /* Data Out Toggle */
#define TIVA_GPIO_DIN_OFFSET 0x00c0 /* Data Input from DIO 0 to 31 */
#define TIVA_GPIO_DOE_OFFSET 0x00d0 /* Data Output Enable for DIO 0 to 31 */
#define TIVA_GPIO_EVFLAGS_OFFSET 0x00e0 /* Event Register for DIO 0 to 31 */
#define TIVA_GPIO_DOUT_PIN_OFFSET(n) ((n) & ~3)
# define TIVA_GPIO_DOUT_PIN3_0_OFFSET 0x0000 /* Data Out 0 to 3 */
# define TIVA_GPIO_DOUT_PIN7_4_OFFSET 0x0004 /* Data Out 4 to 7 */
# define TIVA_GPIO_DOUT_PIN11_8_OFFSET 0x0008 /* Data Out 8 to 11 */
# define TIVA_GPIO_DOUT_PIN15_12_OFFSET 0x000c /* Data Out 12 to 15 */
# define TIVA_GPIO_DOUT_PIN19_16_OFFSET 0x0010 /* Data Out 16 to 19 */
# define TIVA_GPIO_DOUT_PIN23_20_OFFSET 0x0014 /* Data Out 20 to 23 */
# define TIVA_GPIO_DOUT_PIN27_24_OFFSET 0x0018 /* Data Out 24 to 27 */
# define TIVA_GPIO_DOUT_PIN31_28_OFFSET 0x001c /* Data Out 28 to 31 */
#define TIVA_GPIO_DOUT_OFFSET 0x0080 /* Data Output for DIO 0 to 31 */
#define TIVA_GPIO_DOUTSET_OFFSET 0x0090 /* Data Out Set */
#define TIVA_GPIO_DOUTCLR_OFFSET 0x00a0 /* Data Out Clear */
#define TIVA_GPIO_DOUTTGL_OFFSET 0x00b0 /* Data Out Toggle */
#define TIVA_GPIO_DIN_OFFSET 0x00c0 /* Data Input from DIO 0 to 31 */
#define TIVA_GPIO_DOE_OFFSET 0x00d0 /* Data Output Enable for DIO 0 to 31 */
#define TIVA_GPIO_EVFLAGS_OFFSET 0x00e0 /* Event Register for DIO 0 to 31 */
/* GPIO Register Addresses **********************************************************/
#define TIVA_GPIO_DOUT_BASE(n) (TIVA_GPIO_BASE + TIVA_GPIO_DOUT_OFFSET(n))
# define TIVA_GPIO_DOUT3_0_OFFSET (TIVA_GPIO_BASE + TIVA_GPIO_DOUT3_0_OFFSET)
# define TIVA_GPIO_DOUT7_4_OFFSET (TIVA_GPIO_BASE + TIVA_GPIO_DOUT7_4_OFFSET)
# define TIVA_GPIO_DOUT11_8_OFFSET (TIVA_GPIO_BASE + TIVA_GPIO_DOUT11_8_OFFSET)
# define TIVA_GPIO_DOUT15_12_OFFSET (TIVA_GPIO_BASE + TIVA_GPIO_DOUT15_12_OFFSET)
# define TIVA_GPIO_DOUT19_16_OFFSET (TIVA_GPIO_BASE + TIVA_GPIO_DOUT19_16_OFFSET)
# define TIVA_GPIO_DOUT23_20_OFFSET (TIVA_GPIO_BASE + TIVA_GPIO_DOUT23_20_OFFSET)
# define TIVA_GPIO_DOUT27_24_OFFSET (TIVA_GPIO_BASE + TIVA_GPIO_DOUT27_24_OFFSET)
# define TIVA_GPIO_DOUT31_28_OFFSET (TIVA_GPIO_BASE + TIVA_GPIO_DOUT31_28_OFFSET)
#define TIVA_GPIO_DOUT_OFFSET (TIVA_GPIO_BASE + TIVA_GPIO_DOUT_OFFSET)
#define TIVA_GPIO_DOUTSET_OFFSET (TIVA_GPIO_BASE + TIVA_GPIO_DOUTSET_OFFSET)
#define TIVA_GPIO_DOUTCLR_OFFSET (TIVA_GPIO_BASE + TIVA_GPIO_DOUTCLR_OFFSET)
#define TIVA_GPIO_DOUTTGL_OFFSET (TIVA_GPIO_BASE + TIVA_GPIO_DOUTTGL_OFFSET)
#define TIVA_GPIO_DIN_OFFSET (TIVA_GPIO_BASE + TIVA_GPIO_DIN_OFFSET)
#define TIVA_GPIO_DOE_OFFSET (TIVA_GPIO_BASE + TIVA_GPIO_DOE_OFFSET)
#define TIVA_GPIO_EVFLAGS_OFFSET (TIVA_GPIO_BASE + TIVA_GPIO_EVFLAGS_OFFSET)
#define TIVA_GPIO_DOUT_PIN_BASE(n) (TIVA_GPIO_BASE + TIVA_GPIO_DOUT_PIN_OFFSET(n))
# define TIVA_GPIO_DOUT_PIN3_0 (TIVA_GPIO_BASE + TIVA_GPIO_DOUT_PIN3_0_OFFSET)
# define TIVA_GPIO_DOUT_PIN7_4 (TIVA_GPIO_BASE + TIVA_GPIO_DOUT_PIN7_4_OFFSET)
# define TIVA_GPIO_DOUT_PIN11_8 (TIVA_GPIO_BASE + TIVA_GPIO_DOUT_PIN11_8_OFFSET)
# define TIVA_GPIO_DOUT_PIN15_12 (TIVA_GPIO_BASE + TIVA_GPIO_DOUT_PIN15_12_OFFSET)
# define TIVA_GPIO_DOUT_PIN19_16 (TIVA_GPIO_BASE + TIVA_GPIO_DOUT_PIN19_16_OFFSET)
# define TIVA_GPIO_DOUT_PIN23_20 (TIVA_GPIO_BASE + TIVA_GPIO_DOUT_PIN23_20_OFFSET)
# define TIVA_GPIO_DOUT_PIN27_24 (TIVA_GPIO_BASE + TIVA_GPIO_DOUT_PIN27_24_OFFSET)
# define TIVA_GPIO_DOUT_PIN31_28 (TIVA_GPIO_BASE + TIVA_GPIO_DOUT_PIN31_28_OFFSET)
#define TIVA_GPIO_DOUT (TIVA_GPIO_BASE + TIVA_GPIO_DOUT_OFFSET)
#define TIVA_GPIO_DOUTSET (TIVA_GPIO_BASE + TIVA_GPIO_DOUTSET_OFFSET)
#define TIVA_GPIO_DOUTCLR (TIVA_GPIO_BASE + TIVA_GPIO_DOUTCLR_OFFSET)
#define TIVA_GPIO_DOUTTGL (TIVA_GPIO_BASE + TIVA_GPIO_DOUTTGL_OFFSET)
#define TIVA_GPIO_DIN (TIVA_GPIO_BASE + TIVA_GPIO_DIN_OFFSET)
#define TIVA_GPIO_DOE (TIVA_GPIO_BASE + TIVA_GPIO_DOE_OFFSET)
#define TIVA_GPIO_EVFLAGS (TIVA_GPIO_BASE + TIVA_GPIO_EVFLAGS_OFFSET)
/* GPIO Register Bitfield Definitions ***********************************************/
/* Data Out n to n + 3 */
#define GPIO_DOUT_SHIFT(n) (((n) & 3) << 8)
#define GPIO_DOUT_VALUE(n) (1 << GPIO_DOUT_SHIFT(n))
#define GPIO_DOUT_SHIFT(n) (((n) & 3) << 8)
#define GPIO_DOUT_VALUE(n) (1 << GPIO_DOUT_SHIFT(n))
/* Data Output for DIO 0 to 31 */
#define GPIO_DOUT(n) (1 << (n))
#define GPIO_DOUT(n) (1 << (n))
/* Data Out Set */
#define GPIO_DOUTSET(n) (1 << (n))
#define GPIO_DOUTSET(n) (1 << (n))
/* Data Out Clear */
#define GPIO_DOUTCLR(n) (1 << (n))
#define GPIO_DOUTCLR(n) (1 << (n))
/* Data Out Toggle */
#define GPIO_DOUTTGL(n) (1 << (n))
#define GPIO_DOUTTGL(n) (1 << (n))
/* Data Input from DIO 0 to 31 */
#define GPIO_DIN(n) (1 << (n))
#define GPIO_DIN(n) (1 << (n))
/* Data Output Enable for DIO 0 to 31 */
#define GPIO_DOE(n) (1 << (n))
#define GPIO_DOE(n) (1 << (n))
/* Event Register for DIO 0 to 31 */
#define GPIO_EVFLAGS(n) (1 << (n))
#define GPIO_EVFLAGS(n) (1 << (n))
/************************************************************************************
* Public Types
arch/arm/src/tiva/hardware/lm/lm3s_timer.h
+333
View File
@@ -0,0 +1,333 @@
/************************************************************************************
* arch/arm/src/tiva/hardware/lm/lm3s_timer.h
*
* Originally:
*
* Copyright (C) 2012, 2014 Max Nekludov. All rights reserved.
* Author: Max Nekludov <macscomp@gmail.com>
*
* Ongoing support and major revision to support the TM4C129 family
* (essentially a full file replacement):
*
* Copyright (C) 2015, 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Some bitfield definitions taken from a header file provided by:
*
* Copyright (C) 2014 TRD2 Inc. All rights reserved.
* Author: Calvin Maguranis <calvin.maguranis@trd2inc.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_LM_LM3S_TIMER_H
#define __ARCH_ARM_SRC_TIVA_HARDWARE_LM_LM3S_TIMER_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include <arch/tiva/tiva_memorymap.h>
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* GPTM register offsets ************************************************************/
#define TIVA_TIMER_CFG_OFFSET 0x0000 /* GPTM Configuration */
#define TIVA_TIMER_TAMR_OFFSET 0x0004 /* GPTM Timer A Mode */
#define TIVA_TIMER_TBMR_OFFSET 0x0008 /* GPTM Timer B Mode */
#define TIVA_TIMER_CTL_OFFSET 0x000c /* GPTM Control */
#define TIVA_TIMER_IMR_OFFSET 0x0018 /* GPTM Interrupt Mask */
#define TIVA_TIMER_RIS_OFFSET 0x001c /* GPTM Raw Interrupt Status */
#define TIVA_TIMER_MIS_OFFSET 0x0020 /* GPTM Masked Interrupt Status */
#define TIVA_TIMER_ICR_OFFSET 0x0024 /* GPTM Interrupt Clear */
#define TIVA_TIMER_TAILR_OFFSET 0x0028 /* GPTM Timer A Interval Load */
#define TIVA_TIMER_TBILR_OFFSET 0x002c /* GPTM Timer B Interval Load */
#define TIVA_TIMER_TAMATCHR_OFFSET 0x0030 /* GPTM Timer A Match */
#define TIVA_TIMER_TBMATCHR_OFFSET 0x0034 /* GPTM Timer B Match */
#define TIVA_TIMER_TAPR_OFFSET 0x0038 /* GPTM Timer A Prescale */
#define TIVA_TIMER_TBPR_OFFSET 0x003c /* GPTM Timer B Prescale */
#define TIVA_TIMER_TAPMR_OFFSET 0x0040 /* GPTM TimerA Prescale Match */
#define TIVA_TIMER_TBPMR_OFFSET 0x0044 /* GPTM TimerB Prescale Match */
#define TIVA_TIMER_TAR_OFFSET 0x0048 /* GPTM Timer A */
#define TIVA_TIMER_TBR_OFFSET 0x004c /* GPTM Timer B */
/* GPTM register addresses **********************************************************/
#if TIVA_NTIMERS > 0
#define TIVA_TIMER0_CFG (TIVA_TIMER0_BASE + TIVA_TIMER_CFG_OFFSET)
#define TIVA_TIMER0_TAMR (TIVA_TIMER0_BASE + TIVA_TIMER_TAMR_OFFSET)
#define TIVA_TIMER0_TBMR (TIVA_TIMER0_BASE + TIVA_TIMER_TBMR_OFFSET)
#define TIVA_TIMER0_CTL (TIVA_TIMER0_BASE + TIVA_TIMER_CTL_OFFSET)
#define TIVA_TIMER0_IMR (TIVA_TIMER0_BASE + TIVA_TIMER_IMR_OFFSET)
#define TIVA_TIMER0_RIS (TIVA_TIMER0_BASE + TIVA_TIMER_RIS_OFFSET)
#define TIVA_TIMER0_MIS (TIVA_TIMER0_BASE + TIVA_TIMER_MIS_OFFSET)
#define TIVA_TIMER0_ICR (TIVA_TIMER0_BASE + TIVA_TIMER_ICR_OFFSET)
#define TIVA_TIMER0_TAILR (TIVA_TIMER0_BASE + TIVA_TIMER_TAILR_OFFSET)
#define TIVA_TIMER0_TBILR (TIVA_TIMER0_BASE + TIVA_TIMER_TBILR_OFFSET)
#define TIVA_TIMER0_TAMATCHR (TIVA_TIMER0_BASE + TIVA_TIMER_TAMATCHR_OFFSET)
#define TIVA_TIMER0_TBMATCHR (TIVA_TIMER0_BASE + TIVA_TIMER_TBMATCHR_OFFSET)
#define TIVA_TIMER0_TAPR (TIVA_TIMER0_BASE + TIVA_TIMER_TAPR_OFFSET)
#define TIVA_TIMER0_TBPR (TIVA_TIMER0_BASE + TIVA_TIMER_TBPR_OFFSET)
#define TIVA_TIMER0_TAPMR (TIVA_TIMER0_BASE + TIVA_TIMER_TAPMR_OFFSET)
#define TIVA_TIMER0_TBPMR (TIVA_TIMER0_BASE + TIVA_TIMER_TBPMR_OFFSET)
#define TIVA_TIMER0_TAR (TIVA_TIMER0_BASE + TIVA_TIMER_TAR_OFFSET)
#define TIVA_TIMER0_TBR (TIVA_TIMER0_BASE + TIVA_TIMER_TBR_OFFSET)
#endif /* TIVA_NTIMERS > 0 */
#if TIVA_NTIMERS > 1
#define TIVA_TIMER1_CFG (TIVA_TIMER1_BASE + TIVA_TIMER_CFG_OFFSET)
#define TIVA_TIMER1_TAMR (TIVA_TIMER1_BASE + TIVA_TIMER_TAMR_OFFSET)
#define TIVA_TIMER1_TBMR (TIVA_TIMER1_BASE + TIVA_TIMER_TBMR_OFFSET)
#define TIVA_TIMER1_CTL (TIVA_TIMER1_BASE + TIVA_TIMER_CTL_OFFSET)
#define TIVA_TIMER1_IMR (TIVA_TIMER1_BASE + TIVA_TIMER_IMR_OFFSET)
#define TIVA_TIMER1_RIS (TIVA_TIMER1_BASE + TIVA_TIMER_RIS_OFFSET)
#define TIVA_TIMER1_MIS (TIVA_TIMER1_BASE + TIVA_TIMER_MIS_OFFSET)
#define TIVA_TIMER1_ICR (TIVA_TIMER1_BASE + TIVA_TIMER_ICR_OFFSET)
#define TIVA_TIMER1_TAILR (TIVA_TIMER1_BASE + TIVA_TIMER_TAILR_OFFSET)
#define TIVA_TIMER1_TBILR (TIVA_TIMER1_BASE + TIVA_TIMER_TBILR_OFFSET)
#define TIVA_TIMER1_TAMATCHR (TIVA_TIMER1_BASE + TIVA_TIMER_TAMATCHR_OFFSET)
#define TIVA_TIMER1_TBMATCHR (TIVA_TIMER1_BASE + TIVA_TIMER_TBMATCHR_OFFSET)
#define TIVA_TIMER1_TAPR (TIVA_TIMER1_BASE + TIVA_TIMER_TAPR_OFFSET)
#define TIVA_TIMER1_TBPR (TIVA_TIMER1_BASE + TIVA_TIMER_TBPR_OFFSET)
#define TIVA_TIMER1_TAPMR (TIVA_TIMER1_BASE + TIVA_TIMER_TAPMR_OFFSET)
#define TIVA_TIMER1_TBPMR (TIVA_TIMER1_BASE + TIVA_TIMER_TBPMR_OFFSET)
#define TIVA_TIMER1_TAR (TIVA_TIMER1_BASE + TIVA_TIMER_TAR_OFFSET)
#define TIVA_TIMER1_TBR (TIVA_TIMER1_BASE + TIVA_TIMER_TBR_OFFSET)
#endif /* TIVA_NTIMERS > 1 */
#if TIVA_NTIMERS > 2
#define TIVA_TIMER2_CFG (TIVA_TIMER2_BASE + TIVA_TIMER_CFG_OFFSET)
#define TIVA_TIMER2_TAMR (TIVA_TIMER2_BASE + TIVA_TIMER_TAMR_OFFSET)
#define TIVA_TIMER2_TBMR (TIVA_TIMER2_BASE + TIVA_TIMER_TBMR_OFFSET)
#define TIVA_TIMER2_CTL (TIVA_TIMER2_BASE + TIVA_TIMER_CTL_OFFSET)
#define TIVA_TIMER2_IMR (TIVA_TIMER2_BASE + TIVA_TIMER_IMR_OFFSET)
#define TIVA_TIMER2_RIS (TIVA_TIMER2_BASE + TIVA_TIMER_RIS_OFFSET)
#define TIVA_TIMER2_MIS (TIVA_TIMER2_BASE + TIVA_TIMER_MIS_OFFSET)
#define TIVA_TIMER2_ICR (TIVA_TIMER2_BASE + TIVA_TIMER_ICR_OFFSET)
#define TIVA_TIMER2_TAILR (TIVA_TIMER2_BASE + TIVA_TIMER_TAILR_OFFSET)
#define TIVA_TIMER2_TBILR (TIVA_TIMER2_BASE + TIVA_TIMER_TBILR_OFFSET)
#define TIVA_TIMER2_TAMATCHR (TIVA_TIMER2_BASE + TIVA_TIMER_TAMATCHR_OFFSET)
#define TIVA_TIMER2_TBMATCHR (TIVA_TIMER2_BASE + TIVA_TIMER_TBMATCHR_OFFSET)
#define TIVA_TIMER2_TAPR (TIVA_TIMER2_BASE + TIVA_TIMER_TAPR_OFFSET)
#define TIVA_TIMER2_TBPR (TIVA_TIMER2_BASE + TIVA_TIMER_TBPR_OFFSET)
#define TIVA_TIMER2_TAPMR (TIVA_TIMER2_BASE + TIVA_TIMER_TAPMR_OFFSET)
#define TIVA_TIMER2_TBPMR (TIVA_TIMER2_BASE + TIVA_TIMER_TBPMR_OFFSET)
#define TIVA_TIMER2_TAR (TIVA_TIMER2_BASE + TIVA_TIMER_TAR_OFFSET)
#define TIVA_TIMER2_TBR (TIVA_TIMER2_BASE + TIVA_TIMER_TBR_OFFSET)
#endif /* TIVA_NTIMERS > 2 */
#if TIVA_NTIMERS > 3
#define TIVA_TIMER3_CFG (TIVA_TIMER3_BASE + TIVA_TIMER_CFG_OFFSET)
#define TIVA_TIMER3_TAMR (TIVA_TIMER3_BASE + TIVA_TIMER_TAMR_OFFSET)
#define TIVA_TIMER3_TBMR (TIVA_TIMER3_BASE + TIVA_TIMER_TBMR_OFFSET)
#define TIVA_TIMER3_CTL (TIVA_TIMER3_BASE + TIVA_TIMER_CTL_OFFSET)
#define TIVA_TIMER3_IMR (TIVA_TIMER3_BASE + TIVA_TIMER_IMR_OFFSET)
#define TIVA_TIMER3_RIS (TIVA_TIMER3_BASE + TIVA_TIMER_RIS_OFFSET)
#define TIVA_TIMER3_MIS (TIVA_TIMER3_BASE + TIVA_TIMER_MIS_OFFSET)
#define TIVA_TIMER3_ICR (TIVA_TIMER3_BASE + TIVA_TIMER_ICR_OFFSET)
#define TIVA_TIMER3_TAILR (TIVA_TIMER3_BASE + TIVA_TIMER_TAILR_OFFSET)
#define TIVA_TIMER3_TBILR (TIVA_TIMER3_BASE + TIVA_TIMER_TBILR_OFFSET)
#define TIVA_TIMER3_TAMATCHR (TIVA_TIMER3_BASE + TIVA_TIMER_TAMATCHR_OFFSET)
#define TIVA_TIMER3_TBMATCHR (TIVA_TIMER3_BASE + TIVA_TIMER_TBMATCHR_OFFSET)
#define TIVA_TIMER3_TAPR (TIVA_TIMER3_BASE + TIVA_TIMER_TAPR_OFFSET)
#define TIVA_TIMER3_TBPR (TIVA_TIMER3_BASE + TIVA_TIMER_TBPR_OFFSET)
#define TIVA_TIMER3_TAPMR (TIVA_TIMER3_BASE + TIVA_TIMER_TAPMR_OFFSET)
#define TIVA_TIMER3_TBPMR (TIVA_TIMER3_BASE + TIVA_TIMER_TBPMR_OFFSET)
#define TIVA_TIMER3_TAR (TIVA_TIMER3_BASE + TIVA_TIMER_TAR_OFFSET)
#define TIVA_TIMER3_TBR (TIVA_TIMER3_BASE + TIVA_TIMER_TBR_OFFSET)
#endif /* TIVA_NTIMERS > 3 */
#if TIVA_NTIMERS > 4
#define TIVA_TIMER4_CFG (TIVA_TIMER4_BASE + TIVA_TIMER_CFG_OFFSET)
#define TIVA_TIMER4_TAMR (TIVA_TIMER4_BASE + TIVA_TIMER_TAMR_OFFSET)
#define TIVA_TIMER4_TBMR (TIVA_TIMER4_BASE + TIVA_TIMER_TBMR_OFFSET)
#define TIVA_TIMER4_CTL (TIVA_TIMER4_BASE + TIVA_TIMER_CTL_OFFSET)
#define TIVA_TIMER4_IMR (TIVA_TIMER4_BASE + TIVA_TIMER_IMR_OFFSET)
#define TIVA_TIMER4_RIS (TIVA_TIMER4_BASE + TIVA_TIMER_RIS_OFFSET)
#define TIVA_TIMER4_MIS (TIVA_TIMER4_BASE + TIVA_TIMER_MIS_OFFSET)
#define TIVA_TIMER4_ICR (TIVA_TIMER4_BASE + TIVA_TIMER_ICR_OFFSET)
#define TIVA_TIMER4_TAILR (TIVA_TIMER4_BASE + TIVA_TIMER_TAILR_OFFSET)
#define TIVA_TIMER4_TBILR (TIVA_TIMER4_BASE + TIVA_TIMER_TBILR_OFFSET)
#define TIVA_TIMER4_TAMATCHR (TIVA_TIMER4_BASE + TIVA_TIMER_TAMATCHR_OFFSET)
#define TIVA_TIMER4_TBMATCHR (TIVA_TIMER4_BASE + TIVA_TIMER_TBMATCHR_OFFSET)
#define TIVA_TIMER4_TAPR (TIVA_TIMER4_BASE + TIVA_TIMER_TAPR_OFFSET)
#define TIVA_TIMER4_TBPR (TIVA_TIMER4_BASE + TIVA_TIMER_TBPR_OFFSET)
#define TIVA_TIMER4_TAPMR (TIVA_TIMER4_BASE + TIVA_TIMER_TAPMR_OFFSET)
#define TIVA_TIMER4_TBPMR (TIVA_TIMER4_BASE + TIVA_TIMER_TBPMR_OFFSET)
#define TIVA_TIMER4_TAR (TIVA_TIMER4_BASE + TIVA_TIMER_TAR_OFFSET)
#define TIVA_TIMER4_TBR (TIVA_TIMER4_BASE + TIVA_TIMER_TBR_OFFSET)
#endif /* TIVA_NTIMERS > 4 */
#if TIVA_NTIMERS > 5
#define TIVA_TIMER5_CFG (TIVA_TIMER5_BASE + TIVA_TIMER_CFG_OFFSET)
#define TIVA_TIMER5_TAMR (TIVA_TIMER5_BASE + TIVA_TIMER_TAMR_OFFSET)
#define TIVA_TIMER5_TBMR (TIVA_TIMER5_BASE + TIVA_TIMER_TBMR_OFFSET)
#define TIVA_TIMER5_CTL (TIVA_TIMER5_BASE + TIVA_TIMER_CTL_OFFSET)
#define TIVA_TIMER5_IMR (TIVA_TIMER5_BASE + TIVA_TIMER_IMR_OFFSET)
#define TIVA_TIMER5_RIS (TIVA_TIMER5_BASE + TIVA_TIMER_RIS_OFFSET)
#define TIVA_TIMER5_MIS (TIVA_TIMER5_BASE + TIVA_TIMER_MIS_OFFSET)
#define TIVA_TIMER5_ICR (TIVA_TIMER5_BASE + TIVA_TIMER_ICR_OFFSET)
#define TIVA_TIMER5_TAILR (TIVA_TIMER5_BASE + TIVA_TIMER_TAILR_OFFSET)
#define TIVA_TIMER5_TBILR (TIVA_TIMER5_BASE + TIVA_TIMER_TBILR_OFFSET)
#define TIVA_TIMER5_TAMATCHR (TIVA_TIMER5_BASE + TIVA_TIMER_TAMATCHR_OFFSET)
#define TIVA_TIMER5_TBMATCHR (TIVA_TIMER5_BASE + TIVA_TIMER_TBMATCHR_OFFSET)
#define TIVA_TIMER5_TAPR (TIVA_TIMER5_BASE + TIVA_TIMER_TAPR_OFFSET)
#define TIVA_TIMER5_TBPR (TIVA_TIMER5_BASE + TIVA_TIMER_TBPR_OFFSET)
#define TIVA_TIMER5_TAPMR (TIVA_TIMER5_BASE + TIVA_TIMER_TAPMR_OFFSET)
#define TIVA_TIMER5_TBPMR (TIVA_TIMER5_BASE + TIVA_TIMER_TBPMR_OFFSET)
#define TIVA_TIMER5_TAR (TIVA_TIMER5_BASE + TIVA_TIMER_TAR_OFFSET)
#define TIVA_TIMER5_TBR (TIVA_TIMER5_BASE + TIVA_TIMER_TBR_OFFSET)
#endif /* TIVA_NTIMERS > 5 */
#if TIVA_NTIMERS > 6
#define TIVA_TIMER6_CFG (TIVA_TIMER6_BASE + TIVA_TIMER_CFG_OFFSET)
#define TIVA_TIMER6_TAMR (TIVA_TIMER6_BASE + TIVA_TIMER_TAMR_OFFSET)
#define TIVA_TIMER6_TBMR (TIVA_TIMER6_BASE + TIVA_TIMER_TBMR_OFFSET)
#define TIVA_TIMER6_CTL (TIVA_TIMER6_BASE + TIVA_TIMER_CTL_OFFSET)
#define TIVA_TIMER6_IMR (TIVA_TIMER6_BASE + TIVA_TIMER_IMR_OFFSET)
#define TIVA_TIMER6_RIS (TIVA_TIMER6_BASE + TIVA_TIMER_RIS_OFFSET)
#define TIVA_TIMER6_MIS (TIVA_TIMER6_BASE + TIVA_TIMER_MIS_OFFSET)
#define TIVA_TIMER6_ICR (TIVA_TIMER6_BASE + TIVA_TIMER_ICR_OFFSET)
#define TIVA_TIMER6_TAILR (TIVA_TIMER6_BASE + TIVA_TIMER_TAILR_OFFSET)
#define TIVA_TIMER6_TBILR (TIVA_TIMER6_BASE + TIVA_TIMER_TBILR_OFFSET)
#define TIVA_TIMER6_TAMATCHR (TIVA_TIMER6_BASE + TIVA_TIMER_TAMATCHR_OFFSET)
#define TIVA_TIMER6_TBMATCHR (TIVA_TIMER6_BASE + TIVA_TIMER_TBMATCHR_OFFSET)
#define TIVA_TIMER6_TAPR (TIVA_TIMER6_BASE + TIVA_TIMER_TAPR_OFFSET)
#define TIVA_TIMER6_TBPR (TIVA_TIMER6_BASE + TIVA_TIMER_TBPR_OFFSET)
#define TIVA_TIMER6_TAPMR (TIVA_TIMER6_BASE + TIVA_TIMER_TAPMR_OFFSET)
#define TIVA_TIMER6_TBPMR (TIVA_TIMER6_BASE + TIVA_TIMER_TBPMR_OFFSET)
#define TIVA_TIMER6_TAR (TIVA_TIMER6_BASE + TIVA_TIMER_TAR_OFFSET)
#define TIVA_TIMER6_TBR (TIVA_TIMER6_BASE + TIVA_TIMER_TBR_OFFSET)
#endif /* TIVA_NTIMERS > 6 */
#if TIVA_NTIMERS > 7
#define TIVA_TIMER7_CFG (TIVA_TIMER7_BASE + TIVA_TIMER_CFG_OFFSET)
#define TIVA_TIMER7_TAMR (TIVA_TIMER7_BASE + TIVA_TIMER_TAMR_OFFSET)
#define TIVA_TIMER7_TBMR (TIVA_TIMER7_BASE + TIVA_TIMER_TBMR_OFFSET)
#define TIVA_TIMER7_CTL (TIVA_TIMER7_BASE + TIVA_TIMER_CTL_OFFSET)
#define TIVA_TIMER7_IMR (TIVA_TIMER7_BASE + TIVA_TIMER_IMR_OFFSET)
#define TIVA_TIMER7_RIS (TIVA_TIMER7_BASE + TIVA_TIMER_RIS_OFFSET)
#define TIVA_TIMER7_MIS (TIVA_TIMER7_BASE + TIVA_TIMER_MIS_OFFSET)
#define TIVA_TIMER7_ICR (TIVA_TIMER7_BASE + TIVA_TIMER_ICR_OFFSET)
#define TIVA_TIMER7_TAILR (TIVA_TIMER7_BASE + TIVA_TIMER_TAILR_OFFSET)
#define TIVA_TIMER7_TBILR (TIVA_TIMER7_BASE + TIVA_TIMER_TBILR_OFFSET)
#define TIVA_TIMER7_TAMATCHR (TIVA_TIMER7_BASE + TIVA_TIMER_TAMATCHR_OFFSET)
#define TIVA_TIMER7_TBMATCHR (TIVA_TIMER7_BASE + TIVA_TIMER_TBMATCHR_OFFSET)
#define TIVA_TIMER7_TAPR (TIVA_TIMER7_BASE + TIVA_TIMER_TAPR_OFFSET)
#define TIVA_TIMER7_TBPR (TIVA_TIMER7_BASE + TIVA_TIMER_TBPR_OFFSET)
#define TIVA_TIMER7_TAPMR (TIVA_TIMER7_BASE + TIVA_TIMER_TAPMR_OFFSET)
#define TIVA_TIMER7_TBPMR (TIVA_TIMER7_BASE + TIVA_TIMER_TBPMR_OFFSET)
#define TIVA_TIMER7_TAR (TIVA_TIMER7_BASE + TIVA_TIMER_TAR_OFFSET)
#define TIVA_TIMER7_TBR (TIVA_TIMER7_BASE + TIVA_TIMER_TBR_OFFSET)
#endif /* TIVA_NTIMERS > 7 */
/* GPTM register bit definitions ****************************************************/
/* GPTM Configuration (CFG) */
#define TIMER_CFG_CFG_SHIFT 0 /* Bits 2-0: Configuration */
#define TIMER__CFG_MASK (7 << TIMER_CFG_CFG_SHIFT)
# define TIMER_CFG_CFG_32 (0 << TIMER_CFG_CFG_SHIFT) /* 32-bit timer configuration */
# define TIMER_CFG_CFG_RTC (1 << TIMER_CFG_CFG_SHIFT) /* 32-bit real-time clock (RTC) counter configuration */
# define TIMER_CFG_CFG_16 (4 << TIMER_CFG_CFG_SHIFT) /* 16-bit timer configuration */
/* GPTM Timer A/B Mode (TAMR and TBMR) */
#define TIMER_TnMR_TnMR_SHIFT 0 /* Bits 1-0: Timer A/B Mode */
#define TIMER_TnMR_TnMR_MASK (3 << TIMER_TnMR_TnMR_SHIFT)
# define TIMER_TnMR_TnMR_ONESHOT (1 << TIMER_TnMR_TnMR_SHIFT) /* One-Shot Timer mode */
# define TIMER_TnMR_TnMR_PERIODIC (2 << TIMER_TnMR_TnMR_SHIFT) /* Periodic Timer mode */
# define TIMER_TnMR_TnMR_CAPTURE (3 << TIMER_TnMR_TnMR_SHIFT) /* Capture mode */
#define TIMER_TnMR_TnCMR (1 << 2) /* Bit 2: Timer A/B Capture Mode */
# define TIMER_TnMR_TnCMR_EDGECOUNT (0 << TIMER_TnMR_TnCMR_SHIFT) /* Edge-Count mode */
# define TIMER_TnMR_TnCMR_EDGETIME (1 << TIMER_TnMR_TnCMR_SHIFT) /* Edge-Time mode */
#define TIMER_TnMR_TnAMS (1 << 3) /* Bit 3: Timer A/B Alternate Mode Select */
# define TIMER_TnMR_TnAMS_CAPTURE (0 << TIMER_TnMR_TnAMS_SHIFT) /* Capture mode is enabled */
# define TIMER_TnMR_TnAMS_PWM (1 << TIMER_TnMR_TnAMS_SHIFT) /* PWM mode is enabled */
/* GPTM Control (CTL) */
#define TIMER_CTL_TAEN (1 << 0) /* Bit 0: Timer A Enable */
#define TIMER_CTL_TASTALL (1 << 1) /* Bit 1: Timer A Stall Enable */
#define TIMER_CTL_TAEVENT_SHIFT (2) /* Bits 2-3: GPTM Timer A Event Mode */
#define TIMER_CTL_TAEVENT_MASK (3 << TIMER_CTL_TAEVENT_SHIFT)
# define TIMER_CTL_TAEVENT_POS (0 << TIMER_CTL_TAEVENT_SHIFT) /* Positive edge */
# define TIMER_CTL_TAEVENT_NEG (1 << TIMER_CTL_TAEVENT_SHIFT) /* Negative edge */
# define TIMER_CTL_TAEVENT_BOTH (3 << TIMER_CTL_TAEVENT_SHIFT) /* Both edges */
#define TIMER_CTL_RTCEN (1 << 4) /* Bit 4: GPTM RTC Stall Enable */
#define TIMER_CTL_TAOTE (1 << 5) /* Bit 5: GPTM Timer A Output Trigger Enable */
#define TIMER_CTL_TAPWML (1 << 6) /* Bit 6: GPTM Timer A PWM Output Level */
#define TIMER_CTL_TBEN (1 << 8) /* Bit 8: GPTM Timer B Enable */
#define TIMER_CTL_TBSTALL (1 << 9) /* Bit 9: GPTM Timer B Stall Enable */
#define TIMER_CTL_TBEVENT_SHFIT (10) /* Bits 10-11: GPTM Timer B Event Mode */
#define TIMER_CTL_TBEVENT_MASK (3 << TIMER_CTL_TBEVENT_SHFIT)
# define TIMER_CTL_TBEVENT_POS (0 << TIMER_CTL_TBEVENT_SHFIT) /* Positive edge */
# define TIMER_CTL_TBEVENT_NEG (1 << TIMER_CTL_TBEVENT_SHFIT) /* Negative edge */
# define TIMER_CTL_TBEVENT_BOTH (3 << TIMER_CTL_TBEVENT_SHFIT) /* Both edges */
#define TIMER_CTL_TBOTE (1 << 13) /* Bit 13: GPTM Timer B Output Trigger Enable */
#define TIMER_CTL_TBPWML (1 << 14) /* Bit 14: GPTM Timer B PWM Output Level */
/* Common bit definitions used with:
*
* - GPTM Interrupt Mask (IMR)
* - GPTM Raw Interrupt Status (RIS)
* - GPTM Masked Interrupt Status (MIS)
* - GPTM Interrupt Clear (ICR)
*/
#define TIMER_INT_TATO (1 << 0) /* Bit 0: Timer A Time-Out Interrupt */
#define TIMER_INT_TBTO (1 << 8) /* Bit 8: GPTM Timer B Time-Out Interrupt */
#define TIMERA_INTS 0x00000001
#define TIMERB_INTS 0x00000100
#define TIMER_ALLINTS 0x00000101
/* GPTM Timer A Interval Load (TAILR) (32-bit value) */
/* GPTM Timer B Interval Load (TBILR) (32-bit value) */
/* GPTM Timer A Match (TAMATCHR) (32-bit value) */
/* GPTM Timer B Match (TBMATCHR) (32-bit value) */
/* GPTM Timer A/B Prescale (TnPR) */
#define TIMER_TnPR_TnPSR_SHIFT (0) /* Bits 0-8: GPTM Timer A/B Prescale */
#define TIMER_TnPR_TnPSR_MASK (0xff << TIMER_TnPR_TnPSR_SHIFT)
# define TIMER_TnPR_TnPSR(n) ((uint32_t)(n) << TIMER_TnPR_TnPSR_SHIFT)
/* GPTM Timer A/B Prescale Match (TnPMR) */
#define TIMER_TnPMR_TnPSMR_SHIFT (0) /* Bits 0-8: GPTM Timer A/B Prescale Match */
#define TIMER_TnPMR_TnPSMR_MASK (0xff << TIMER_TnPMR_TnPSMR_SHIFT)
# define TIMER_TnPMR_TnPSMR(n) ((uint32_t)(n) << TIMER_TnPMR_TnPSMR_SHIFT)
/* GPTM Timer A (TAR) (16/32-bit value) */
/* GPTM Timer B (TBR) (16/32-bit value) */
#endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_LM_LM3S_TIMER_H */
arch/arm/src/tiva/hardware/lm/lm4f_timer.h
+574
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File diff suppressed because it is too large Load Diff
arch/arm/src/tiva/hardware/tiva_gpio.h
+1 -1
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@@ -43,7 +43,7 @@
#include <nuttx/config.h>
/* Include the GPIO header file for the specific Tiva/Stellaris chip */
/* Include the GPIO header file for the specific Tiva/Stellaris/SimpleLink chip */
#if defined(CONFIG_ARCH_CHIP_LM3S)
# include "hardware/lm/lm3s_gpio.h"
arch/arm/src/tiva/hardware/tiva_sysctrl.h
+2 -4
View File
@@ -52,10 +52,8 @@
# include "hardware/tm4c/tm4c123_sysctrl.h"
#elif defined(CONFIG_ARCH_CHIP_TM4C129)
# include "hardware/tm4c/tm4c129_sysctrl.h"
#elif defined(CONFIG_ARCH_CHIP_CC13X0)
# include "hardware/cc13x0/cc13x0_sysctrl.h"
#elif defined(CONFIG_ARCH_CHIP_CC13X2)
# include "hardware/cc13x2_cc26x2/cc13x2_cc26x2_sysctrl.h"
#elif defined(CONFIG_ARCH_CHIP_CC13X0) || defined(CONFIG_ARCH_CHIP_CC13X2)
/* These MCUs have no SYSCTL block */
#else
# error "Unsupported Tiva/Stellaris system control module"
#endif
arch/arm/src/tiva/hardware/tiva_timer.h
+16 -765
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File diff suppressed because it is too large Load Diff
arch/arm/src/tiva/hardware/tm4c/tm4c123_timer.h
+574
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File diff suppressed because it is too large Load Diff
arch/arm/src/tiva/hardware/tm4c/tm4c129_timer.h
+644
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File diff suppressed because it is too large Load Diff
arch/arm/src/tiva/tiva_lowputc.h
+2 -2
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@@ -198,14 +198,14 @@ extern "C"
****************************************************************************/
/****************************************************************************
* Name: up_lowsetup
* Name: tiva_lowsetup
*
* Description:
* Called at the very beginning of _start. Performs low level initialization.
*
****************************************************************************/
void up_lowsetup(void);
void tiva_lowsetup(void);
#if defined(__cplusplus)
}
configs/launchxl-cc1312r1/include/board.h
+44
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@@ -54,6 +54,50 @@
/* LED definitions **********************************************************/
/* The LaunchXL-cc1312R1 and two LEDs controlled by software: DIO7_GLED (CR1)
* and DIO6_RLED (CR2). A high output value illuminates an LED.
*
* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in
* any way. The following definitions are used to access individual LEDs.
*/
/* LED index values for use with board_userled() */
#define BOARD_GLED 0
#define BOARD_RLED 1
#define BOARD_NLEDS 2
/* LED bits for use with board_userled_all() */
#define BOARD_GLED_BIT (1 << BOARD_GLED)
#define BOARD_RLED_BIT (1 << BOARD_RLED)
/* These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is
* defined. In that case, the usage by the board port is defined in
* include/board.h and src/cc1312_autoleds.c. The LEDs are used to
* encode OS-related events as follows:
*
* ------------------- ---------------------------- ---- ----
* SYMBOL Meaning GLED RLED
* ------------------- ---------------------------- ---- ---- */
#define LED_STARTED 0 /* NuttX has been started OFF OFF */
#define LED_HEAPALLOCATE 1 /* Heap has been allocated OFF ON */
#define LED_IRQSENABLED 1 /* Interrupts enabled OFF ON */
#define LED_STACKCREATED 2 /* Idle stack created ON OFF */
#define LED_INIRQ 3 /* In an interrupt N/C GLOW */
#define LED_SIGNAL 3 /* In a signal handler N/C GLOW */
#define LED_ASSERTION 3 /* An assertion failed N/C GLOW */
#define LED_PANIC 4 /* The system has crashed OFF BLINK */
#undef LED_IDLE /* MCU is is sleep mode -Not used- */
/* Thus iF GLED is statically on, NuttX has successfully booted and is,
* apparently, running normally. A soft glow of the RLED means that the
* board is taking interrupts. If GLED is off and GLED is flashing at
* approximately 2Hz, then a fatal error has been detected and the system
* has halted.
*/
/* Button definitions *******************************************************/
/* Pin Disambiguation *******************************************************/
configs/max32660-evsys/include/board.h
+1 -1
View File
@@ -87,7 +87,7 @@
#define LED_PANIC 3 /* The system has crashed FLASH */
#undef LED_IDLE /* MCU is is sleep mode Not used */
/* Thus is LED is statically on, NuttX has successfully booted and is,
/* Thus if LED is statically on, NuttX has successfully booted and is,
* apparently, running normally. If LED is flashing at approximately
* 2Hz, then a fatal error has been detected and the system has halted.
*/