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arch/stm32h5: Add ethernet hardware support files

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This commit adds files in preperation of adding ethernet drivers for the STM32H563 and Nucleo-H563ZI board.
It also modifies the pinmap to include ethernet pins (and cleaned up leftover comments from L5 file), as well as
add those pins to the board.h for the nucleo-h563zi.

Files added:
  - arch/arm/src/stm32h5/hardware/stm32_ethernet.h
  - arch/arm/src/stm32h5/hardware/stm32_sbs.h
    - Not fully implemented, just register necessary for ethernet driver.
This commit is contained in:
stbenn
2024-11-05 13:18:17 -06:00
committed by Xiang Xiao
parent 0702dc5361
commit cd479f6752
5 changed files with 842 additions and 563 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm/src/stm32h5/hardware/stm32_ethernet.h
+678
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arch/arm/src/stm32h5/hardware/stm32_sbs.h
+98
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@@ -0,0 +1,98 @@
/****************************************************************************
* arch/arm/src/stm32h5/hardware/stm32_sbs.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32_SBS_H
#define __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32_SBS_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#if !defined(CONFIG_STM32H5_STM32H52XXX) && \
!defined(CONFIG_STM32H5_STM32H53XXX) && \
!defined(CONFIG_STM32H5_STM32H56XXX) && \
!defined(CONFIG_STM32H5_STM32H57XXX)
# warning "SBS not verified on STM32H50x variants."
#endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register Offsets *********************************************************/
#define STM32_SBS_HDPLCR_OFFSET 0x0010
#define STM32_SBS_HPDLSR_OFFSET 0x0014
#define STM32_SBS_NEXTHDPLCR_OFFSET 0x0018
#define STM32_SBS_DBGCR_OFFSET 0x0020
#define STM32_SBS_DBGLOCKR_OFFSET 0x0024
#define STM32_SBS_RSSCMDR_OFFSET 0x0034
#define STM32_SBS_EPOCHSELCR_OFFSET 0x00A0
#define STM32_SBS_SECCFGR_OFFSET 0x00C0
#define STM32_SBS_PMCR_OFFSET 0x0100
#define STM32_SBS_FPUIMR_OFFSET 0x0104
#define STM32_SBS_MESR_OFFSET 0x0108
#define STM32_SBS_CCCSR_OFFSET 0x0110
#define STM32_SBS_CCVALR_OFFSET 0x0114
#define STM32_SBS_CCSWCR_OFFSET 0x0118
#define STM32_SBS_CFGR2_OFFSET 0x0120
#define STM32_SBS_CNSLCKR_OFFSET 0x0144
#define STM32_SBS_CSLCKR_OFFSET 0x0148
#define STM32_SBS_ECCNMIR_OFFSET 0x014C
/* Register Addresses *******************************************************/
#define STM32_SBS_HDPLCR (STM32_SBS_BASE + STM32_SBS_HDPLCR_OFFSET)
#define STM32_SBS_HPDLSR (STM32_SBS_BASE + STM32_SBS_HPDLSR_OFFSET)
#define STM32_SBS_NEXTHDPLCR (STM32_SBS_BASE + STM32_SBS_NEXTHDPLCR_OFFSET)
#define STM32_SBS_DBGCR (STM32_SBS_BASE + STM32_SBS_DBGCR_OFFSET)
#define STM32_SBS_DBGLOCKR (STM32_SBS_BASE + STM32_SBS_DBGLOCKR_OFFSET)
#define STM32_SBS_RSSCMDR (STM32_SBS_BASE + STM32_SBS_RSSCMDR_OFFSET)
#define STM32_SBS_EPOCHSELCR (STM32_SBS_BASE + STM32_SBS_EPOCHSELCR_OFFSET)
#define STM32_SBS_SECCFGR (STM32_SBS_BASE + STM32_SBS_SECCFGR_OFFSET)
#define STM32_SBS_PMCR (STM32_SBS_BASE + STM32_SBS_PMCR_OFFSET)
#define STM32_SBS_FPUIMR (STM32_SBS_BASE + STM32_SBS_FPUIMR_OFFSET)
#define STM32_SBS_MESR (STM32_SBS_BASE + STM32_SBS_MESR_OFFSET)
#define STM32_SBS_CCCSR (STM32_SBS_BASE + STM32_SBS_CCCSR_OFFSET)
#define STM32_SBS_CCVALR (STM32_SBS_BASE + STM32_SBS_CCVALR_OFFSET)
#define STM32_SBS_CCSWCR (STM32_SBS_BASE + STM32_SBS_CCSWCR_OFFSET)
#define STM32_SBS_CFGR2 (STM32_SBS_BASE + STM32_SBS_CFGR2_OFFSET)
#define STM32_SBS_CNSLCKR (STM32_SBS_BASE + STM32_SBS_CNSLCKR_OFFSET)
#define STM32_SBS_CSLCKR (STM32_SBS_BASE + STM32_SBS_CSLCKR_OFFSET)
#define STM32_SBS_ECCNMIR (STM32_SBS_BASE + STM32_SBS_ECCNMIR_OFFSET)
/* Register Bitfield Definitions ********************************************/
/* Product mode and configuration register (PMCR) */
#define SBS_PMCR_PB6_FMP (1 << 16) /* Fast-mode Plus on PB6*/
#define SBS_PMCR_PB7_FMP (1 << 17) /* Fast-mode Plus on PB7*/
#define SBS_PMCR_PB8_FMP (1 << 18) /* Fast-mode Plus on PB8*/
#define SBS_PMCR_PB9_FMP (1 << 19) /* Fast-mode Plus on PB9*/
#define SBS_PMCR_ETH_SEL_PHY_SHIFT (21) /* Bits 23-21 Ethernet PHY interface selection */
#define SBS_PMCR_ETH_SEL_PHY_MASK (0b111 << SBS_ETH_SEL_PHY_SHIFT)
# define SBS_PMCR_ETH_SEL_PHY_GMII_OR_MII (0 << SBS_ETH_SEL_PHY_SHIFT)
# define SBS_PMCR_ETH_SEL_PHY_RMII (4 << SBS_ETH_SEL_PHY_SHIFT)
#endif /* __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32_SBS_H */
arch/arm/src/stm32h5/hardware/stm32h56xxx_pinmap.h
+52 -558
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arch/arm/src/stm32h5/stm32_gpio.h
+1
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@@ -194,6 +194,7 @@
# define GPIO_PORTF (5 << GPIO_PORT_SHIFT) /* GPIOF */
# define GPIO_PORTG (6 << GPIO_PORT_SHIFT) /* GPIOG */
# define GPIO_PORTH (7 << GPIO_PORT_SHIFT) /* GPIOH */
# define GPIO_PORTI (8 << GPIO_PORT_SHIFT) /* GPIOI*/
/* This identifies the bit in the port:
*
boards/arm/stm32h5/nucleo-h563zi/include/board.h
+13 -5
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@@ -163,7 +163,7 @@
/* Configure the APB1 prescaler */
#define STM32_RCC_CFGR2_PPRE1 RCC_CFGR2_PPRE1_HCLK1 /* PCLK1 = HCLK / 1 */
#define STM32_RCC_CFGR2_PPRE1 RCC_CFGR2_PPRE1_HCLK1 /* PCLK1 = HCLK / 1 */
#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1)
#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY)
@@ -190,8 +190,8 @@
/* Configure the APB3 prescaler */
#define STM32_RCC_CFGR2_PPRE3 RCC_CFGR2_PPRE3_HCLK1 /* PCLK2 = HCLK / 1 */
#define STM32_PCLK3_FREQUENCY (STM32_HCLK_FREQUENCY / 1)
#define STM32_RCC_CFGR2_PPRE3 RCC_CFGR2_PPRE3_HCLK1 /* PCLK2 = HCLK / 1 */
#define STM32_PCLK3_FREQUENCY (STM32_HCLK_FREQUENCY / 1)
#define STM32_APB3_LPTIM1_CLKIN (STM32_PCLK3_FREQUENCY)
#define STM32_APB3_LPTIM3_CLKIN (STM32_PCLK3_FREQUENCY)
@@ -225,9 +225,17 @@
/* Configure the Kernel clocks */
/* DMA Channel/Stream Selections ********************************************/
/* Ethernet definitions *****************************************************/
/* Alternate function pin selections ****************************************/
#define GPIO_ETH_MDC (GPIO_ETH_MDC_0 | GPIO_SPEED_100MHz) /* PC1 */
#define GPIO_ETH_MDIO (GPIO_ETH_MDIO_0 | GPIO_SPEED_100MHz) /* PA2 */
#define GPIO_ETH_RMII_RXD0 (GPIO_ETH_RMII_RXD0_0 | GPIO_SPEED_100MHz) /* PC4 */
#define GPIO_ETH_RMII_RXD1 (GPIO_ETH_RMII_RXD1_0 | GPIO_SPEED_100MHz) /* PC5 */
#define GPIO_ETH_RMII_TXD0 (GPIO_ETH_RMII_TXD0_3 | GPIO_SPEED_100MHz) /* PG13 */
#define GPIO_ETH_RMII_TXD1 (GPIO_ETH_RMII_TXD1_1 | GPIO_SPEED_100MHz) /* PB15 */
#define GPIO_ETH_RMII_TX_EN (GPIO_ETH_RMII_TX_EN_3 | GPIO_SPEED_100MHz) /* PG11 */
#define GPIO_ETH_RMII_CRS_DV (GPIO_ETH_RMII_CRS_DV_0 | GPIO_SPEED_100MHz) /* PA7 */
#define GPIO_ETH_RMII_REF_CLK (GPIO_ETH_RMII_REF_CLK_0 | GPIO_SPEED_100MHz) /* PA1 */
/* USART3: Connected to Arduino connector D0/D1 (or to STLink VCP if solder
* bridges SB123 to SB130 are re-worked accordingly).