STM32 F7 Ethernet: Add logic to align all DMA memory to the D-Cache line size

This commit is contained in:
Gregory Nutt
2015-07-19 16:35:25 -06:00
parent 8b9cafe70a
commit ccd3ec0f52
3 changed files with 236 additions and 146 deletions
File diff suppressed because it is too large Load Diff
+2 -2
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@@ -394,9 +394,9 @@ static const struct uart_ops_s g_uart_dma_ops =
/* DMA buffers. DMA buffers must:
*
* 1. Be a multiple of the I-Cache line size. This requirement is assured
* 1. Be a multiple of the D-Cache line size. This requirement is assured
* by the definition of RXDMA buffer size above.
* 2. Be aligned a I-Cache line boundaries, and
* 2. Be aligned a D-Cache line boundaries, and
* 3. Be positioned in DMA-able memory (*NOT* DTCM memory). This must
* be managed by logic in the linker script file.
*
+1 -1
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@@ -339,7 +339,7 @@ static int lib_dns_query(FAR const char *hostname,
sd = dns_bind();
if (sd < 0)
{
return sd;
return sd;
}
/* Perform the query to get the IP address */