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https://github.com/apache/nuttx.git
synced 2026-05-21 04:52:02 +08:00
arch/nrf52: add QSPI support
This commit is contained in:
raiden00pl
Xiang Xiao
@@ -115,6 +115,10 @@ ifeq ($(CONFIG_USBDEV),y)
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CHIP_CSRCS += nrf52_usbd.c
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endif
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ifeq ($(CONFIG_NRF52_QSPI),y)
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CHIP_CSRCS += nrf52_qspi.c
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endif
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ifeq ($(CONFIG_NRF52_SOFTDEVICE_CONTROLLER),y)
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NRFXLIB_UNPACK := sdk-nrfxlib
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@@ -0,0 +1,207 @@
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/****************************************************************************
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* arch/arm/src/nrf52/hardware/nrf52_qspi.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_QSPI_H
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#define __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_QSPI_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include "hardware/nrf52_memorymap.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Register offsets *********************************************************/
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#define NRF52_QSPI_TASKS_ACTIVATE_OFFSET 0x0000 /* Activate QSPI interface */
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#define NRF52_QSPI_TASKS_READSTART_OFFSET 0x0004 /* Start transfer from external flash memory to internal RAM */
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#define NRF52_QSPI_TASKS_WRITESTART_OFFSET 0x0008 /* Start transfer from internal RAM to external flash memory */
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#define NRF52_QSPI_TASKS_ERASESTART_OFFSET 0x000c /* Start external flash memory erase operation */
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#define NRF52_QSPI_TASKS_DEACTIVATE_OFFSET 0x0010 /* Deactivate QSPI interface */
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#define NRF52_QSPI_EVENTS_READY_OFFSET 0x0100 /* QSPI peripheral is ready */
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#define NRF52_QSPI_INTEN_OFFSET 0x0300 /* Enable or disable interrupt */
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#define NRF52_QSPI_INTENSET_OFFSET 0x0304 /* Enable interrupt */
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#define NRF52_QSPI_INTENCLR_OFFSET 0x0308 /* Disable interrupt */
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#define NRF52_QSPI_ENABLE_OFFSET 0x0500 /* Enable QSPI peripheral */
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#define NRF52_QSPI_READ_SRC_OFFSET 0x0504 /* Flash memory source address */
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#define NRF52_QSPI_READ_DST_OFFSET 0x0508 /* RAM destination address */
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#define NRF52_QSPI_READ_CNT_OFFSET 0x050c /* Read transfer length */
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#define NRF52_QSPI_WRITE_SRC_OFFSET 0x0510 /* Flash destination address */
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#define NRF52_QSPI_WRITE_DST_OFFSET 0x0514 /* RAM source address */
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#define NRF52_QSPI_WRITE_CNT_OFFSET 0x0518 /* Write transfer length */
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#define NRF52_QSPI_ERASE_PTR_OFFSET 0x051c /* Start address of flash block to be erased */
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#define NRF52_QSPI_ERASE_LEN_OFFSET 0x0520 /* Size of block to be erased */
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#define NRF52_QSPI_PSEL_SCK_OFFSET 0x0524 /* Pin select for serial clock SCK */
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#define NRF52_QSPI_PSEL_CSN_OFFSET 0x0528 /* Pin select for chip select signal CSN */
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#define NRF52_QSPI_PSEL_IO0_OFFSET 0x0530 /* Pin select for serial data MOSI/IO0 */
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#define NRF52_QSPI_PSEL_IO1_OFFSET 0x0534 /* Pin select for serial data MISO/IO1 */
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#define NRF52_QSPI_PSEL_IO2_OFFSET 0x0538 /* Pin select for serial data IO2 */
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#define NRF52_QSPI_PSEL_IO3_OFFSET 0x053c /* Pin select for serial data IO3 */
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#define NRF52_QSPI_XIPOFFSET_OFFSET 0x0540 /* Address offset into the external memory for XIP */
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#define NRF52_QSPI_IFCONFIG0_OFFSET 0x0544 /* Interface configuration */
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#define NRF52_QSPI_IFCONFIG1_OFFSET 0x0600 /* Interface configuration */
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#define NRF52_QSPI_STATUS_OFFSET 0x0604 /* Status register */
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#define NRF52_QSPI_DPMDUR_OFFSET 0x0614 /* DPM duration */
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#define NRF52_QSPI_ADDRCONF_OFFSET 0x0624 /* Extended address configuration. */
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#define NRF52_QSPI_CINSTRCONF_OFFSET 0x0634 /* Custom instruction configuration register. */
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#define NRF52_QSPI_CINSTRDAT0_OFFSET 0x0638 /* Custom instruction data register 0. */
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#define NRF52_QSPI_CINSTRDAT1_OFFSET 0x063c /* Custom instruction data register 1. */
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#define NRF52_QSPI_IFTIMING_OFFSET 0x0640 /* SPI interface timing. */
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/* Register Bitfield Definitions ********************************************/
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/* INTEN/INTENSET/INTENCLR */
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#define QSPI_INT_READY (1 << 0)
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/* ENABLE */
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#define QSPI_ENABLE_EN (1)
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#define QSPI_ENABLE_DIS (0)
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/* ERASE.LEN */
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#define QSPI_ERASE_SECTOR (0)
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#define QSPI_ERASE_PAGE (1)
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#define QSPI_ERASE_ALL (2)
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/* PSEL */
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#define QSPI_PSEL_PIN_SHIFT (0)
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#define QSPI_PSEL_PORT_SHIFT (5)
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#define QSPI_PSEL_CONNECT (1 << 31)
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/* IFCONFIG0 */
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#define QSPI_IFCONFIG0_READOC_SHIFT (0)
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#define QSPI_IFCONFIG0_READOC_MASK (0x7 << QSPI_IFCONFIG0_READOC_SHIFT)
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# define QSPI_IFCONFIG0_READOC_FASTREAD (0 << QSPI_IFCONFIG0_READOC_SHIFT)
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# define QSPI_IFCONFIG0_READOC_READ2O (1 << QSPI_IFCONFIG0_READOC_SHIFT)
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# define QSPI_IFCONFIG0_READOC_READ2IO (2 << QSPI_IFCONFIG0_READOC_SHIFT)
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# define QSPI_IFCONFIG0_READOC_READ4O (3 << QSPI_IFCONFIG0_READOC_SHIFT)
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# define QSPI_IFCONFIG0_READOC_READ4IO (4 << QSPI_IFCONFIG0_READOC_SHIFT)
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#define QSPI_IFCONFIG0_WRITEOC_SHIFT (3)
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#define QSPI_IFCONFIG0_WRITEOC_MASK (0x7 << QSPI_IFCONFIG0_WRITEOC_SHIFT)
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# define QSPI_IFCONFIG0_WRITEOC_PP (0 << QSPI_IFCONFIG0_WRITEOC_SHIFT)
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# define QSPI_IFCONFIG0_WRITEOC_PP2O (1 << QSPI_IFCONFIG0_WRITEOC_SHIFT)
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# define QSPI_IFCONFIG0_WRITEOC_PP4O (2 << QSPI_IFCONFIG0_WRITEOC_SHIFT)
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# define QSPI_IFCONFIG0_WRITEOC_PP4IO (3 << QSPI_IFCONFIG0_WRITEOC_SHIFT)
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#define QSPI_IFCONFIG0_ADDRMODE_24 (0 << 6)
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#define QSPI_IFCONFIG0_ADDRMODE_32 (1 << 6)
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#define QSPI_IFCONFIG0_DPMENABLE (1 << 7)
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#define QSPI_IFCONFIG0_PPSIZE_512 (1 << 12)
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/* IFCONFIG1 */
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#define QSPI_IFCONFIG1_SCKDELAY_SHIFT (0)
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#define QSPI_IFCONFIG1_SCKDELAY_MASK (0xff << QSPI_IFCONFIG1_SCKDELAY_SHIFT)
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#define QSPI_IFCONFIG1_DPMEN_EXIT (0 << 24)
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#define QSPI_IFCONFIG1_DPMEN_ENTER (1 << 24)
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#define QSPI_IFCONFIG1_SPIMODE_0 (0 << 25)
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#define QSPI_IFCONFIG1_SPIMODE_3 (1 << 25)
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#define QSPI_IFCONFIG1_SCKFREQ_SHIFT (28)
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#define QSPI_IFCONFIG1_SCKFREQ_MASK (0xf << QSPI_IFCONFIG1_SCKFREQ_SHIFT)
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/* STATUS */
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#define QSPI_STATUS_DPM (1 << 2)
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#define QSPI_STATUS_READY (1 << 3)
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#define QSPI_STATUS_SREG_SHIFT (24)
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#define QSPI_STATUS_SREG_MASK (0xff << QSPI_STATUS_SREG_SHIFT)
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/* DPMDUR */
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#define QSPI_DPMDUR_ENTER_SHIFT (0)
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#define QSPI_DPMDUR_ENTER_MASK (0xffff << QSPI_DPMDUR_ENTER_SHIFT)
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#define QSPI_DPMDUR_EXIT_SHIFT (16)
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#define QSPI_DPMDUR_EXIT_MASK (0xffff << QSPI_DPMDUR_EXIT_SHIFT)
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/* ADDRCONF */
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#define QSPI_ADDRCONF_OPCODE_SHIFT (0)
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#define QSPI_ADDRCONF_OPCODE_MASK (0xff << QSPI_ADDRCONF_OPCODE_SHIFT)
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#define QSPI_ADDRCONF_BYTE0_SHIFT (8)
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#define QSPI_ADDRCONF_BYTE0_MASK (0xff << QSPI_ADDRCONF_BYTE0_SHIFT)
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#define QSPI_ADDRCONF_BYTE1_SHIFT (16)
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#define QSPI_ADDRCONF_BYTE1_MASK (0xff << QSPI_ADDRCONF_BYTE1_SHIFT)
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#define QSPI_ADDRCONF_MODE_SHIFT (24)
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#define QSPI_ADDRCONF_MODE_MASK (0x3 << QSPI_ADDRCONF_MODE_SHIFT)
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# define QSPI_ADDRCONF_MODE_NOINSTR (0 << QSPI_ADDRCONF_MODE_SHIFT)
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# define QSPI_ADDRCONF_MODE_OPCODE (1 << QSPI_ADDRCONF_MODE_SHIFT)
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# define QSPI_ADDRCONF_MODE_OPBYTE0 (2 << QSPI_ADDRCONF_MODE_SHIFT)
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# define QSPI_ADDRCONF_MODE_ALL (3 << QSPI_ADDRCONF_MODE_SHIFT)
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#define QSPI_ADDRCONF_WIPWAIT (1 << 26)
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#define QSPI_ADDRCONF_WREN (1 << 27)
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/* CINSTRCONF */
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#define QSPI_CINSTRCONF_OPCODE_SHIFT (0)
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#define QSPI_CINSTRCONF_OPCODE_MASK (0xff << QSPI_CINSTRCONF_OPCODE_SHIFT)
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#define QSPI_CINSTRCONF_LENGTH_SHIFT (8)
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#define QSPI_CINSTRCONF_LENGTH_MASK (0xf << QSPI_CINSTRCONF_LENGTH_SHIFT)
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#define QSPI_CINSTRCONF_LENGTH(n) ((n) << QSPI_CINSTRCONF_LENGTH_SHIFT)
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#define QSPI_CINSTRCONF_LIO2 (1 << 12)
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#define QSPI_CINSTRCONF_LIO3 (1 << 13)
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#define QSPI_CINSTRCONF_WIPWAIT (1 << 14)
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#define QSPI_CINSTRCONF_WREN (1 << 15)
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#define QSPI_CINSTRCONF_LFEN (1 << 16)
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#define QSPI_CINSTRCONF_LFSTOP_STOP (1 << 17)
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/* CINSTRDAT0 */
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#define QSPI_CINSTRDAT0_BYTE0_SHIFT (0)
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#define QSPI_CINSTRDAT0_BYTE0_MASK (0xff << QSPI_CINSTRDAT0_BYTE0_SHIFT)
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#define QSPI_CINSTRDAT0_BYTE0(n) ((n) << QSPI_CINSTRDAT0_BYTE0_SHIFT)
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#define QSPI_CINSTRDAT0_BYTE1_SHIFT (8)
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#define QSPI_CINSTRDAT0_BYTE1_MASK (0xff << QSPI_CINSTRDAT0_BYTE1_SHIFT)
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#define QSPI_CINSTRDAT0_BYTE1(n) ((n) << QSPI_CINSTRDAT0_BYTE1_SHIFT)
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#define QSPI_CINSTRDAT0_BYTE2_SHIFT (16)
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#define QSPI_CINSTRDAT0_BYTE2_MASK (0xff << QSPI_CINSTRDAT0_BYTE2_SHIFT)
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#define QSPI_CINSTRDAT0_BYTE2(n) ((n) << QSPI_CINSTRDAT0_BYTE2_SHIFT)
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#define QSPI_CINSTRDAT0_BYTE3_SHIFT (24)
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#define QSPI_CINSTRDAT0_BYTE3_MASK (0xff << QSPI_CINSTRDAT0_BYTE3_SHIFT)
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#define QSPI_CINSTRDAT0_BYTE3(n) ((n) << QSPI_CINSTRDAT0_BYTE3_SHIFT)
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/* CINSTRDAT1 */
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#define QSPI_CINSTRDAT1_BYTE0_SHIFT (0)
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#define QSPI_CINSTRDAT1_BYTE0_MASK (0xff << QSPI_CINSTRDAT1_BYTE0_SHIFT)
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#define QSPI_CINSTRDAT1_BYTE0(n) ((n) << QSPI_CINSTRDAT1_BYTE0_SHIFT)
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#define QSPI_CINSTRDAT1_BYTE1_SHIFT (8)
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#define QSPI_CINSTRDAT1_BYTE1_MASK (0xff << QSPI_CINSTRDAT1_BYTE1_SHIFT)
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#define QSPI_CINSTRDAT1_BYTE1(n) ((n) << QSPI_CINSTRDAT1_BYTE1_SHIFT)
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#define QSPI_CINSTRDAT1_BYTE2_SHIFT (16)
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#define QSPI_CINSTRDAT1_BYTE2_MASK (0xff << QSPI_CINSTRDAT1_BYTE2_SHIFT)
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#define QSPI_CINSTRDAT1_BYTE2(n) ((n) << QSPI_CINSTRDAT1_BYTE2_SHIFT)
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#define QSPI_CINSTRDAT1_BYTE3_SHIFT (24)
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#define QSPI_CINSTRDAT1_BYTE3_MASK (0xff << QSPI_CINSTRDAT1_BYTE3_SHIFT)
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#define QSPI_CINSTRDAT1_BYTE3(n) ((n) << QSPI_CINSTRDAT1_BYTE3_SHIFT)
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/* IFTIMING */
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#define QSPI_IFTIMING_RXDELAY_SHIFT (8)
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#define QSPI_IFTIMING_RXDELAY_MASK (0xff << QSPI_IFTIMING_RXDELAY_SHIFT)
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#define QSPI_IFTIMING_RXDELAY(n) ((n) << QSPI_IFTIMING_RXDELAY_SHIFT)
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#endif /* __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_QSPI_H */
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,52 @@
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/****************************************************************************
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* arch/arm/src/nrf52/nrf52_qspi.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_NRF52_NRF52_QSPI_H
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#define __ARCH_ARM_SRC_NRF52_NRF52_QSPI_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <nuttx/spi/qspi.h>
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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/****************************************************************************
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* Name: nrf52_qspi_initialize
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*
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* Description:
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* Initialize the selected QSPI port in master mode
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*
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* Input Parameters:
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* intf - Interface number(must be zero)
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*
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* Returned Value:
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* Valid QSPI device structure reference on success; a NULL on failure
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*
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****************************************************************************/
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struct qspi_dev_s *nrf52_qspi_initialize(int intf);
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#endif /* __ARCH_ARM_SRC_NRF52_NRF52_QSPI_H */
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