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arch/arm/src/lpc54xx: Add some Ethernet PHY initialization logic.

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This commit is contained in:
Gregory Nutt
2017-12-27 12:01:24 -06:00
parent 31330b2479
commit cb9e1e7716
6 changed files with 459 additions and 38 deletions
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arch/arm/src/lpc54xx/Kconfig
+6
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@@ -671,6 +671,12 @@ endmenu # EMC Configuration
menu "Ethernet configuration"
depends on LPC54_ETHERNET
config LPC54_PHYADDR
int "PHY address"
default 1
---help---
The 5-bit address of the PHY on the board. Default: 1
config LPC54_MII
bool "Use MII interface"
default n
arch/arm/src/lpc54xx/chip/lpc54_ethernet.h
+34 -5
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@@ -341,13 +341,42 @@
#define ETH_MAC_HW_FEAT2_
/* MIDO address */
#define ETH_MAC_MDIO_ADDR_
#define ETH_MAC_MDIO_ADDR_MB (1 << 0) /* Bit 0 MII busy */
#define ETH_MAC_MDIO_ADDR_MOC_SHIFT (2) /* Bits 2-3: MII operation command */
#define ETH_MAC_MDIO_ADDR_MOC_MASK (3 << ETH_MAC_MDIO_ADDR_MOC_SHIFT)
# define ETH_MAC_MDIO_ADDR_MOC_WRITE (1 << ETH_MAC_MDIO_ADDR_MOC_SHIFT) /* Write */
# define ETH_MAC_MDIO_ADDR_MOC_READ (3 << ETH_MAC_MDIO_ADDR_MOC_SHIFT) /* Read */
#define ETH_MAC_MDIO_ADDR_CR_SHIFT (8) /* Bits 8-11: CSR clock range */
#define ETH_MAC_MDIO_ADDR_CR_MASK (15 << ETH_MAC_MDIO_ADDR_CR_SHIFT)
# define ETH_MAC_MDIO_ADDR_CR_DIV42 (0 << ETH_MAC_MDIO_ADDR_CR_SHIFT) /* CSR=60-100 MHz; MDC=CSR/42 */
# define ETH_MAC_MDIO_ADDR_CR_DIV62 (1 << ETH_MAC_MDIO_ADDR_CR_SHIFT) /* CSR=100-150 MHz; MDC=CSR/62 */
# define ETH_MAC_MDIO_ADDR_CR_DIV16 (2 << ETH_MAC_MDIO_ADDR_CR_SHIFT) /* CSR=20-35 MHz; MDC=CSR/16 */
# define ETH_MAC_MDIO_ADDR_CR_DIV26 (3 << ETH_MAC_MDIO_ADDR_CR_SHIFT) /* CSR=35-60 MHz; MDC=CSR/26 */
#define ETH_MAC_MDIO_ADDR_NTC_SHIFT (12) /* Bits 12-14: Number of training clocks */
#define ETH_MAC_MDIO_ADDR_NTC_MASK (7 << ETH_MAC_MDIO_ADDR_NTC_SHIFT)
# define ETH_MAC_MDIO_ADDR_NTC(n) ((uint32_t)(n) << ETH_MAC_MDIO_ADDR_NTC_SHIFT)
#define ETH_MAC_MDIO_ADDR_RDA_SHIFT (16) /* Bits 16-20: Register/device address */
#define ETH_MAC_MDIO_ADDR_RDA_MASK (31 << ETH_MAC_MDIO_ADDR_RDA_SHIFT)
# define ETH_MAC_MDIO_ADDR_RDA(n) ((uint32_t)(n) << ETH_MAC_MDIO_ADDR_RDA_SHIFT)
#define ETH_MAC_MDIO_ADDR_PA_SHIFT (21) /* Bits 21-25: Physical layer address */
#define ETH_MAC_MDIO_ADDR_PA_MASK (31 << ETH_MAC_MDIO_ADDR_PA_SHIFT)
# define ETH_MAC_MDIO_ADDR_PA(n) ((uint32_t)(n) << ETH_MAC_MDIO_ADDR_PA_SHIFT)
#define ETH_MAC_MDIO_ADDR_BTB (1 << 26) /* Bit 26 Back to back transactions */
#define ETH_MAC_MDIO_ADDR_PSE (1 << 27) /* Bit 27 Preamble suppression enable */
/* MDIO data */
#define ETH_MAC_MDIO_DATA_
#define ETH_MAC_MDIO_DATA_MASK 0xffff /* Bits 0-15: 16 bit PHY data */
/* MAC address0 high */
#define ETH_MAC_ADDR_HIGH_
/* MAC address0 low */
#define ETH_MAC_ADDR_LOW_
#define ETH_MAC_ADDR_HIGH_A32_47_SHIFT (0) /* MAC address 32-47 */
#define ETH_MAC_ADDR_HIGH_A32_47_MASK (0xffff << ETH_MAC_ADDR_HIGH_A32_47_SHIFT)
# define ETH_MAC_ADDR_HIGH_A32_47(n) ((uint32_t)(n) << ETH_MAC_ADDR_HIGH_A32_47_SHIFT)
#define ETH_MAC_ADDR_HIGH_DCS (1 << 16) /* Bit 16: DMA channel select */
/* MAC address0 low (32-bit MAC address 0-31) */
/* Timestamp control */
#define ETH_MAC_TIMESTAMP_CTRL_
arch/arm/src/lpc54xx/chip/lpc54_syscon.h
+1 -1
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@@ -701,7 +701,7 @@
#define SYSCON_EMCDLYCAL_
/* Ethernet PHY selection */
#define SYSCON_ETHPHYSEL (1 << 2) /* Bit 2: PHY_SEL PHY interface */
#define SYSCON_ETHPHYSEL_MASK (1 << 2) /* Bit 2: PHY_SEL PHY interface */
# define SYSCON_ETHPHYSEL_MII (0) /* Select MII PHY Interface */
# define SYSCON_ETHPHYSEL_RMII (1 << 2) /* Select RMII PHY Interface */
arch/arm/src/lpc54xx/lpc54_ethernet.c
+368 -32
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File diff suppressed because it is too large Load Diff
configs/lpcxpresso-lpc54628/include/board.h
+42
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@@ -383,6 +383,48 @@
#define GPIO_LCD_VD3 GPIO_LCD_VD3_1
/* Ethernet Clock
*
* The Lpcxpresso-LPC546258 uses a LAN8720A PHY in RMII mode. Clocking is
* provided via a 25MHz crystal (Y1). CLKOUT on P3.12 is an option if JS4
* is reversed.
*/
#define BOARD_PHY_CLOCK 25000000 /* 25MHz crystal */
/* Ethernet RMII mode pins:
*
* P4_16-ENET_MDIO Ethernet MIIM data input and output
* P4_15-ENET_MDC Ethernet MIIM clock
*
* P4_11-ENET_RXD0 Ethernet receive data 0-1
* P4_12-ENET_RXD1
* P4_8-ENET_TXD0 Ethernet transmit data 0-1
* P0_17-ENET_TXD1
* P4_10-ENET_CRS_DV Ethernet receive data valid
* P4_13-ENET_TX_EN Ethernet transmit data enable
*
* P4_14-ENET_RX_CLK REF_CLK, Reference clock (Not used)
* P2_26-ENET_PHY_RSTn nRST (Controlled by board logic)
*
* NOTE: You must set JP11 and JP12 to close 1-2 to enable Ethernet
* port functionality. Some pins are shared with USB0 overcurrent
* feature.
*/
#define GPIO_ENET_MDIO GPIO_ENET_MDIO_2 /* P4.16 */
#define GPIO_ENET_MDC GPIO_ENET_MDC_2 /* P4.15 */
#define GPIO_ENET_RXD0 GPIO_ENET_RXD0_2 /* P4.11 */
#define GPIO_ENET_RXD1 GPIO_ENET_RXD1_2 /* P4.12 */
#define GPIO_ENET_TXD0 GPIO_ENET_TXD0_3 /* P4.8 */
#define GPIO_ENET_TXD1 GPIO_ENET_TXD1_4 /* P0.17 */
#define GPIO_ENET_RX_DV GPIO_ENET_RX_DV_2 /* P4.10 */
#define GPIO_ENET_TX_EN GPIO_ENET_TX_EN_2 /* P4.13 */
#define GPIO_ENET_RX_CLK GPIO_ENET_RX_CLK_2 /* P4.14 */
/****************************************************************************
* Public Types
****************************************************************************/
include/nuttx/net/mii.h
+8
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@@ -351,6 +351,14 @@
#define MII_PHYID1_LAN8720 0x0007 /* ID1 value for LAN8720 */
#define MII_PHYID2_LAN8720 0xc0f1 /* ID2 value for LAN8720 */
/* SMSC LAN8720 SPCR register bits */
#define MII_LAN8720_SPSCR_10MBPS (1 << 2) /* Bit 2: 10MBPS speed */
#define MII_LAN8720_SPSCR_100MBPS (1 << 3) /* Bit 3: 100MBPS speed */
#define MII_LAN8720_SPSCR_DUPLEX (1 << 4) /* Bit 4: Duplex mode */
#define MII_LAN8720_SPSCR_MODEMASK 0x1c /* Mode/speed mask */
#define MII_LAN8720_SPSCR_ANEGDONE (1 << 12) /* Bit 12: Autonegotiation complete */
/* SMSC LAN8740 MII ID1/2 register bits */
#define MII_PHYID1_LAN8740 0x0007 /* ID1 value for LAN8740 */